Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_INTLV_256B

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 7921682..6b6f722 100644 (file)
--- a/README
+++ b/README
@@ -413,11 +413,6 @@ The following options need to be configured:
                same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
                it could be different for ARM SoCs.
 
-               CONFIG_SYS_FSL_DDR_INTLV_256B
-               DDR controller interleaving on 256-byte. This is a special
-               interleaving mode, handled by Dickens for Freescale layerscape
-               SoCs with ARM core.
-
                CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
                Number of controllers used as main memory.
 

diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index a414387..afb4e48 100644 (file)
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -56,6 +56,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y

diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 91b5226..15dadeb 100644 (file)
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y

diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 7d3cce0..9fc1801 100644 (file)
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -79,6 +79,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57

diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 6bb3781..d2dd95e 100644 (file)
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -60,6 +60,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57

diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index e2710b8..e2e4cfd 100644 (file)
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -74,6 +74,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57

diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 1d0aea0..5378876 100644 (file)
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -60,6 +60,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y

diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index ec6869c..6570a46 100644 (file)
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y

diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index fa929ac..7c87f89 100644 (file)
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -83,6 +83,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y

diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index e6e6fe6..a426d6d 100644 (file)
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57

diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 2a7cbd3..f082fa5 100644 (file)
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -66,6 +66,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index 5d9c48b..1972fc9 100644 (file)
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -56,6 +56,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y

diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 0628cc2..dedc191 100644 (file)
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y

diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index 5fb1346..1674a2c 100644 (file)
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index bf9a016..071db6b 100644 (file)
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -68,6 +68,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 21c6052..84aea7f 100644 (file)
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -61,6 +61,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 62b214b..7fce30b 100644 (file)
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -68,6 +68,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 65e43bf..42efefa 100644 (file)
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 8cdebc8..85ee4ca 100644 (file)
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index c7e9afe..547c868 100644 (file)
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
index ca70f8b..4210084 100644 (file)
--- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
@@ -63,6 +63,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index 68cdefb..dd1c076 100644 (file)
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -70,6 +70,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig
index ee3134e..70faef8 100644 (file)
--- a/configs/lx2162aqds_tfa_verified_boot_defconfig
+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
@@ -71,6 +71,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index d93ed8d..22400a9 100644 (file)
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -182,6 +182,13 @@ config SYS_DDR_RAW_TIMING
          timing parameters are extracted from datasheet and hard-coded into
          header files or board specific files.
 
+config SYS_FSL_DDR_INTLV_256B
+       bool "Enforce 256-byte interleave"
+       help
+         DDR controller interleaving on 256-byte. This is a special
+         interleaving mode, handled by Dickens for Freescale layerscape SoCs
+         with ARM core.
+
 endif
 
 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 3e86d1b..ba5af6c 100644 (file)
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -16,8 +16,6 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_FSL_DDR_INTLV_256B  /* force 256 byte interleaving */
-
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0

diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 0f5b044..6187071 100644 (file)
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -13,7 +13,6 @@
 #define CONFIG_SYS_FLASH_BASE          0x20000000
 
 /* DDR */
-#define CONFIG_SYS_FSL_DDR_INTLV_256B  /* force 256 byte interleaving */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE              0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0