Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region

In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.

The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.

The commit changes R5 MCU scratchpad for j721e to an SRAM region.

Old Map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│                STACK                │
├─────────────────────────────────────┤ 0x41c85b20
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x70000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41cf5bfc)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
			                (0x41cffbfc)

New Map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│                EMPTY                │
├─────────────────────────────────────┤ 0x41c81920
│                STACK                │
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
├─────────────────────────────────────┤ 0x41c85920
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x70000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41cf59f0)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
├─────────────────────────────────────┤ 0x41cff9fc
│         NEW MCU SCRATCHPAD          │
│  SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
			                (0x41cffbfc)

Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[n-francis@ti.com: SRAM allocation addressing diagram]
Signed-off-by: Neha Francis <n-francis@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 0ffbbf9..0991b42 100644 (file)
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -52,7 +52,8 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 config SYS_K3_MCU_SCRATCHPAD_BASE
        hex
        default 0x40280000 if SOC_K3_AM654
-       default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2
+       default 0x40280000 if SOC_K3_J721S2
+       default 0x41cff9fc if SOC_K3_J721E
        help
          Describes the base address of MCU Scratchpad RAM.
 

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 4760726..afe1f3a 100644 (file)
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -21,10 +21,16 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0xf59f0
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
@@ -32,9 +38,9 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_BOOTCOMMAND=y
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_MAX_SIZE=0xf59f0
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
+CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
 CONFIG_SPL_BSS_MAX_SIZE=0xa000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_STACK_R=y

diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index e898601..feaa2da 100644 (file)
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -268,6 +268,49 @@ Image formats:
                 | +-------------------+ |
                 +-----------------------+
 
+R5 Memory Map:
+--------------
+
+.. list-table::
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Region
+     - Start Address
+     - End Address
+
+   * - SPL
+     - 0x41c00000
+     - 0x41c40000
+
+   * - EMPTY
+     - 0x41c40000
+     - 0x41c81920
+
+   * - STACK
+     - 0x41c85920
+     - 0x41c81920
+
+   * - Global data
+     - 0x41c859f0
+     - 0x41c85920
+
+   * - Heap
+     - 0x41c859f0
+     - 0x41cf59f0
+
+   * - BSS
+     - 0x41cf59f0
+     - 0x41cff9f0
+
+   * - MCU Scratchpad
+     - 0x41cff9fc
+     - 0x41cffbfc
+
+   * - ROM DATA
+     - 0x41cffbfc
+     - 0x41cfffff
+
 OSPI:
 -----
 ROM supports booting from OSPI from offset 0x0.