Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

diff --git a/CREDITS b/CREDITS
index 7c1458f..3b657e9 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -124,6 +124,10 @@ N: James F. Dougherty
 E: jfd@GigabitNetworks.COM
 D: Port to the MOUSSE board
 
+N: Mike Dunn
+E: mikedunn@newsguy.com
+D: Palmtreo680 board, docg4 nand flash driver
+
 N: Dave Ellis
 E: DGE@sixnetio.com
 D: EEPROM Speedup, SXNI855T port

diff --git a/MAINTAINERS b/MAINTAINERS
index 7820375..3e70b03 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -651,6 +651,9 @@ Wolfgang Denk <wd@denx.de>
        imx27lite       i.MX27
        qong            i.MX31
 
+Mike Dunn <mikedunn@newsguy.com>
+       palmtreo680     pxa270
+
 Kristoffer Ericson <kristoffer.ericson@gmail.com>
 
        jornada SA1110
@@ -662,9 +665,9 @@ Fabio Estevam <fabio.estevam@freescale.com>
        mx31pdk         i.MX31
        mx53ard         i.MX53
        mx53smd         i.MX53
-       mx6qsabresd     i.MX6Q
+       mx6sabresd      i.MX6Q/DL
        mx6qsabreauto   i.MX6Q
-       wandboard       i.MX6DL/S
+       wandboard       i.MX6DL/S/Q
        mx6slevk        i.MX6SL
 
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>

diff --git a/Makefile b/Makefile
index af4c3c0..b1e5d5f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -743,6 +743,13 @@ tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
        $(MAKE) -C $@ all
 endif  # config.mk
 
+# ARM relocations should all be R_ARM_RELATIVE.
+checkarmreloc: $(obj)u-boot
+       @if test "R_ARM_RELATIVE" != \
+               "`readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
+               then echo "$< contains relocations other than \
+               R_ARM_RELATIVE"; false; fi
+
 $(VERSION_FILE):
                @mkdir -p $(dir $(VERSION_FILE))
                @( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index dc64160..e80e1ed 100644 (file)
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -109,3 +109,8 @@ ifeq ($(GAS_BUG_12532),y)
 PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
 endif
 endif
+
+# check that only R_ARM_RELATIVE relocations are generated
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y  += checkarmreloc
+endif

diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index cf55bf7..367c805 100644 (file)
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -31,6 +31,7 @@ SECTIONS
        . = ALIGN(4);
        .text      :
        {
+               *(.__image_copy_start)
          arch/arm/cpu/arm920t/start.o  (.text*)
                /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
          . = 0x1000;
@@ -56,7 +57,10 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
 
        __bss_start = .;
        .bss : { *(.bss*) }

diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
index 41bb84b..a9a13cb 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -159,6 +159,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        switch (clk) {
        case MXC_ARM_CLK:
                return imx_get_armclk();
+       case MXC_I2C_CLK:
+               return imx_get_ahbclk()/2;
        case MXC_UART_CLK:
                return imx_get_perclk1();
        case MXC_FEC_CLK:
@@ -380,3 +382,11 @@ void mx27_sd2_init_pins(void)
 
 }
 #endif /* CONFIG_MXC_MMC */
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */

diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 673c725..f4e7525 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -57,11 +57,6 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       }
-
        .bss : {
                . = ALIGN(4);
                __bss_start = .;

diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index 967a135..446d095 100644 (file)
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -57,11 +57,6 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       }
-
        .bss : {
                . = ALIGN(4);
                __bss_start = .;

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 652e5a7..9ede3f5 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1200,6 +1200,9 @@ void dmm_init(u32 base)
        /* TRAP for invalid TILER mappings in section 0 */
        lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
 
+       if (omap_revision() >= OMAP4460_ES1_0)
+               lis_map_regs_calculated.is_ma_present = 1;
+
        lisa_map_regs = &lis_map_regs_calculated;
 #endif
        struct dmm_lisa_map_regs *hw_lisa_map_regs =

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 56cf1f8..07b1108 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -412,6 +412,8 @@ void enable_basic_clocks(void)
                (*prcm)->cm_l4per_gpio4_clkctrl,
                (*prcm)->cm_l4per_gpio5_clkctrl,
                (*prcm)->cm_l4per_gpio6_clkctrl,
+               (*prcm)->cm_l4per_gpio7_clkctrl,
+               (*prcm)->cm_l4per_gpio8_clkctrl,
                0
        };
 

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index daf124e..11ba36b 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -43,13 +43,15 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
 
-static struct gpio_bank gpio_bank_54xx[6] = {
+static struct gpio_bank gpio_bank_54xx[8] = {
        { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
        { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
        { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
        { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
        { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
        { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
 };
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;

diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 553589c..54bafda 100644 (file)
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -31,6 +31,7 @@ SECTIONS
        . = ALIGN(4);
        .text :
        {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                *(.text*)
        }
@@ -54,17 +55,23 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -88,6 +95,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }

diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk
index 0bbe295..ea55859 100644 (file)
--- a/arch/arm/cpu/pxa/config.mk
+++ b/arch/arm/cpu/pxa/config.mk
@@ -24,7 +24,7 @@
 
 PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
-PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
+PLATFORM_CPPFLAGS += -mcpu=xscale
 # =========================================================================
 #
 # Supply options according to compiler version

diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 2e3f65e..2e623b1 100644 (file)
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -208,10 +208,9 @@ cpu_init_crit:
         * disable MMU stuff and caches
         */
        mrc     p15, 0, r0, c1, c0, 0
-       bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
+       bic     r0, r0, #0x00003300     @ clear bits 13:12, 9:8 (--VI --RS)
        bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
        orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
-       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
        mcr     p15, 0, r0, c1, c0, 0
 
        mov     pc, lr          /* back to my caller */

diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 1408f03..b6ed25f 100644 (file)
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -58,11 +58,6 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       }
-
        _end = .;
 
        .bss __rel_dyn_start (OVERLAY) : {
@@ -72,6 +67,7 @@ SECTIONS
                __bss_end = .;
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index d9bbee3..3037885 100644 (file)
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -33,7 +33,7 @@ SECTIONS
        . = ALIGN(4);
        .text :
        {
-               __image_copy_start = .;
+               *(.__image_copy_start)
                CPUDIR/start.o (.text*)
                *(.text*)
        }
@@ -57,17 +57,23 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -101,6 +107,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index bb53a6a..d2f3a78 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -284,7 +284,6 @@ void config_ddr_data(const struct ddr_data *data, int nr);
  * This structure represents the DDR io control on AM33XX devices.
  */
 struct ddr_cmdtctrl {
-       unsigned int resv1[1];
        unsigned int cm0ioctl;
        unsigned int cm1ioctl;
        unsigned int cm2ioctl;

diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h
index 1a211e9..8346979 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -21,6 +21,8 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO          128
+
 #define AM33XX_GPIO0_BASE       0x44E07000
 #define AM33XX_GPIO1_BASE       0x4804C000
 #define AM33XX_GPIO2_BASE       0x481AC000

diff --git a/arch/arm/include/asm/arch-mx27/clock.h b/arch/arm/include/asm/arch-mx27/clock.h
index fd062d3..2b03a41 100644 (file)
--- a/arch/arm/include/asm/arch-mx27/clock.h
+++ b/arch/arm/include/asm/arch-mx27/clock.h
@@ -26,6 +26,7 @@
 
 enum mxc_clock {
        MXC_ARM_CLK,
+       MXC_I2C_CLK,
        MXC_UART_CLK,
        MXC_ESDHC_CLK,
        MXC_FEC_CLK,

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 03abb2a..45824f9 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -364,7 +364,7 @@ struct iomuxc {
 
 #define IOMUXC_GPR2_MODE_DISABLED      0
 #define IOMUXC_GPR2_MODE_ENABLED_DI0   1
-#define IOMUXC_GPR2_MODE_ENABLED_DI1   2
+#define IOMUXC_GPR2_MODE_ENABLED_DI1   3
 
 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET               2
 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                 (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)

diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index a4134a0..dbb7856 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -23,114 +23,1661 @@
 #include <asm/imx-common/iomux-v3.h>
 
 enum {
+       MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10      = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC     = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT10__ECSPI2_MISO         = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0),
        MX6_PAD_CSI0_DAT10__UART1_TXD           = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT10__UART1_RXD           = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0),
+       MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4     = IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT10__GPIO_5_28           = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33  = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7       = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11      = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS    = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT11__ECSPI2_SS0          = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0),
+       MX6_PAD_CSI0_DAT11__UART1_TXD           = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0),
        MX6_PAD_CSI0_DAT11__UART1_RXD           = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
-       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5     = IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT11__GPIO_5_29           = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34  = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8       = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12      = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8       = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16    = IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__UART4_TXD           = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__UART4_RXD           = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0),
+       MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6     = IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__GPIO_5_30           = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35  = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9       = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13      = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9       = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17    = IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__UART4_TXD           = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__UART4_RXD           = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0),
+       MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7     = IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__GPIO_5_31           = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36  = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10      = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14      = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10      = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18    = IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__UART5_TXD           = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__UART5_RXD           = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0),
+       MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8     = IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__GPIO_6_0            = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37  = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11      = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15      = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11      = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19    = IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__UART5_TXD           = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__UART5_RXD           = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0),
+       MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9     = IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__GPIO_6_1            = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38  = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12      = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16      = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12      = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20    = IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__UART4_CTS           = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__UART4_RTS           = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0),
+       MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10    = IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__GPIO_6_2            = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39  = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13      = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17      = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13      = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21    = IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__UART4_CTS           = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__UART4_RTS           = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0),
+       MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11    = IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__GPIO_6_3            = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40  = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14      = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18      = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14      = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22    = IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__UART5_CTS           = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__UART5_RTS           = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0),
+       MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12    = IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__GPIO_6_4            = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41  = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15      = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19      = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15      = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23    = IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__UART5_CTS           = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__UART5_RTS           = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0),
+       MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13    = IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__GPIO_6_5            = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42  = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9       = IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4        = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2        = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT4__ECSPI1_SCLK          = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0),
+       MX6_PAD_CSI0_DAT4__KPP_COL_5            = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0),
+       MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC      = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT4__GPIO_5_22            = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43   = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1        = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5        = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3        = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT5__ECSPI1_MOSI          = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0),
+       MX6_PAD_CSI0_DAT5__KPP_ROW_5            = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0),
+       MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD      = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT5__GPIO_5_23            = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44   = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2        = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6        = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4        = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT6__ECSPI1_MISO          = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0),
+       MX6_PAD_CSI0_DAT6__KPP_COL_6            = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0),
+       MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS     = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT6__GPIO_5_24            = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45   = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3        = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7        = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5        = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT7__ECSPI1_SS0           = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0),
+       MX6_PAD_CSI0_DAT7__KPP_ROW_6            = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0),
+       MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD      = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT7__GPIO_5_25            = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46   = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4        = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8        = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6        = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT8__ECSPI2_SCLK          = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0),
+       MX6_PAD_CSI0_DAT8__KPP_COL_7            = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0),
+       MX6_PAD_CSI0_DAT8__I2C1_SDA             = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0),
+       MX6_PAD_CSI0_DAT8__GPIO_5_26            = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47   = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5        = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9        = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7        = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT9__ECSPI2_MOSI          = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0),
+       MX6_PAD_CSI0_DAT9__KPP_ROW_7            = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0),
+       MX6_PAD_CSI0_DAT9__I2C1_SCL             = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0),
+       MX6_PAD_CSI0_DAT9__GPIO_5_27            = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48   = IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6        = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0     = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14  = IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2   = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DATA_EN__GPIO_5_20         = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31        = IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK       = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13     = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_MCLK__CCM_CLKO             = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0),
+       MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1      = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_MCLK__GPIO_5_19            = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30   = IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_MCLK__SIMBA_TRCTL          = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12   = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0    = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_PIXCLK__GPIO_5_18          = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO       = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
+       MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
+       MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1       = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0),
+       MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15    = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
+       MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3     = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
+       MX6_PAD_CSI0_VSYNC__GPIO_5_21           = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
+       MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32  = IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0),
+       MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0       = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
+       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DI0_DISP_CLK__LCDIF_CLK         = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0),
+       MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28        = IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0),
+       MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0   = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0),
+       MX6_PAD_DI0_DISP_CLK__GPIO_4_16         = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
+       MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
+       MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR   = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
+       MX6_PAD_DI0_DISP_CLK__LCDIF_WR_RWN      = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0),
        MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15       = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DI0_PIN4__GPIO_4_20             = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DI0_PIN15__LCDIF_ENABLE         = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC      = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29   = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1      = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN15__GPIO_4_17            = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1    = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN15__LCDIF_RD_E           = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2         = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DI0_PIN2__LCDIF_HSYNC           = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0),
+       MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD       = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30    = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2       = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN2__GPIO_4_18             = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2     = IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9  = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN2__LCDIF_RS              = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3         = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DI0_PIN3__LCDIF_VSYNC           = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS      = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31    = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3       = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__GPIO_4_19             = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3     = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN3__LCDIF_CS              = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4         = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DI0_PIN4__LCDIF_BUSY            = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0),
+       MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD       = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN4__USDHC1_WP             = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0),
+       MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD      = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN4__GPIO_4_20             = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4     = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
+       MX6_PAD_DI0_PIN4__LCDIF_RESET           = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0    = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT0__LCDIF_DAT_0         = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT0__ECSPI3_SCLK         = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0        = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT0__GPIO_4_21           = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5   = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1        = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1    = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2     = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT1__LCDIF_DAT_1         = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT1__ECSPI3_MOSI         = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1        = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL        = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT1__GPIO_4_22           = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6   = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12       = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10  = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT10__LCDIF_DAT_10       = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6       = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT10__GPIO_4_31          = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21      = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11  = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT11__LCDIF_DAT_11       = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7       = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT11__GPIO_5_5           = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22      = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12  = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT12__LCDIF_DAT_12       = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT12__GPIO_5_6           = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23      = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13  = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT13__LCDIF_DAT_13       = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS   = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0),
+       MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT13__GPIO_5_7           = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24      = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14  = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT14__LCDIF_DAT_14       = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC    = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0),
+       MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT14__GPIO_5_8           = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2       = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15  = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT15__LCDIF_DAT_15       = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT15__ECSPI1_SS1         = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0),
+       MX6_PAD_DISP0_DAT15__ECSPI2_SS1         = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0),
+       MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT15__GPIO_5_9           = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25      = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16  = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT16__LCDIF_DAT_16       = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT16__ECSPI2_MOSI        = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0),
+       MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC    = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0),
+       MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0      = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0),
+       MX6_PAD_DISP0_DAT16__GPIO_5_10          = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26      = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17  = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT17__LCDIF_DAT_17       = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT17__ECSPI2_MISO        = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0),
+       MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD    = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0),
+       MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1      = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0),
+       MX6_PAD_DISP0_DAT17__GPIO_5_11          = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27      = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18  = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT18__LCDIF_DAT_18       = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT18__ECSPI2_SS0         = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0),
+       MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS   = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0),
+       MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS   = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0),
+       MX6_PAD_DISP0_DAT18__GPIO_5_12          = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2     = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19  = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT19__LCDIF_DAT_19       = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT19__ECSPI2_SCLK        = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0),
+       MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD    = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0),
+       MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC    = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0),
+       MX6_PAD_DISP0_DAT19__GPIO_5_13          = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3     = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2    = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__LCDIF_DAT_2         = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__ECSPI3_MISO         = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2        = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE     = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__GPIO_4_23           = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7   = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13       = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20  = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT20__LCDIF_DAT_20       = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT20__ECSPI1_SCLK        = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0),
+       MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC    = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0),
+       MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT20__GPIO_5_14          = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28      = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21  = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT21__LCDIF_DAT_21       = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT21__ECSPI1_MOSI        = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0),
+       MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD    = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0),
+       MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0    = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT21__GPIO_5_15          = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29      = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22  = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT22__LCDIF_DAT_22       = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT22__ECSPI1_MISO        = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0),
+       MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS   = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0),
+       MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1    = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT22__GPIO_5_16          = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30      = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23  = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT23__LCDIF_DAT_23       = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT23__ECSPI1_SS0         = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0),
+       MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD    = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0),
+       MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2    = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT23__GPIO_5_17          = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31      = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3    = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT3__LCDIF_DAT_3         = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT3__ECSPI3_SS0          = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3        = IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR        = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT3__GPIO_4_24           = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8   = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14       = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4    = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT4__LCDIF_DAT_4         = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT4__ECSPI3_SS1          = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4        = IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB  = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT4__GPIO_4_25           = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9   = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15       = IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5    = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT5__LCDIF_DAT_5         = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT5__ECSPI3_SS2          = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS    = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS    = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT5__GPIO_4_26           = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10  = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16       = IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6    = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT6__LCDIF_DAT_6         = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT6__ECSPI3_SS3          = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC     = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE   = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT6__GPIO_4_27           = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11  = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17       = IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7    = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT7__LCDIF_DAT_7         = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT7__ECSPI3_RDY          = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5        = IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0  = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT7__GPIO_4_28           = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12  = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18       = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8    = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT8__LCDIF_DAT_8         = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT8__PWM1_PWMO           = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B        = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1  = IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT8__GPIO_4_29           = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13  = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19       = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9    = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6_PAD_DISP0_DAT9__LCDIF_DAT_9         = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT9__PWM2_PWMO           = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B        = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2  = IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT9__GPIO_4_30           = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14  = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20       = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A0__MMDC_DRAM_A_0          = IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A1__MMDC_DRAM_A_1          = IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A10__MMDC_DRAM_A_10        = IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A11__MMDC_DRAM_A_11        = IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A12__MMDC_DRAM_A_12        = IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A13__MMDC_DRAM_A_13        = IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A14__MMDC_DRAM_A_14        = IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A15__MMDC_DRAM_A_15        = IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A2__MMDC_DRAM_A_2          = IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A3__MMDC_DRAM_A_3          = IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A4__MMDC_DRAM_A_4          = IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A5__MMDC_DRAM_A_5          = IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A6__MMDC_DRAM_A_6          = IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A7__MMDC_DRAM_A_7          = IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A8__MMDC_DRAM_A_8          = IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_A9__MMDC_DRAM_A_9          = IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS         = IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0        = IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1        = IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D0__MMDC_DRAM_D_0          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D1__MMDC_DRAM_D_1          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D10__MMDC_DRAM_D_10        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D11__MMDC_DRAM_D_11        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D12__MMDC_DRAM_D_12        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D13__MMDC_DRAM_D_13        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D14__MMDC_DRAM_D_14        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D15__MMDC_DRAM_D_15        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D16__MMDC_DRAM_D_16        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D17__MMDC_DRAM_D_17        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D18__MMDC_DRAM_D_18        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D19__MMDC_DRAM_D_19        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D2__MMDC_DRAM_D_2          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D20__MMDC_DRAM_D_20        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D21__MMDC_DRAM_D_21        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D22__MMDC_DRAM_D_22        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D23__MMDC_DRAM_D_23        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D24__MMDC_DRAM_D_24        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D25__MMDC_DRAM_D_25        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D26__MMDC_DRAM_D_26        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D27__MMDC_DRAM_D_27        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D28__MMDC_DRAM_D_28        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D29__MMDC_DRAM_D_29        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D3__MMDC_DRAM_D_3          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D30__MMDC_DRAM_D_30        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D31__MMDC_DRAM_D_31        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D32__MMDC_DRAM_D_32        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D33__MMDC_DRAM_D_33        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D34__MMDC_DRAM_D_34        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D35__MMDC_DRAM_D_35        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D36__MMDC_DRAM_D_36        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D37__MMDC_DRAM_D_37        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D38__MMDC_DRAM_D_38        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D39__MMDC_DRAM_D_39        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D4__MMDC_DRAM_D_4          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D40__MMDC_DRAM_D_40        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D41__MMDC_DRAM_D_41        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D42__MMDC_DRAM_D_42        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D43__MMDC_DRAM_D_43        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D44__MMDC_DRAM_D_44        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D45__MMDC_DRAM_D_45        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D46__MMDC_DRAM_D_46        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D47__MMDC_DRAM_D_47        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D48__MMDC_DRAM_D_48        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D49__MMDC_DRAM_D_49        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D5__MMDC_DRAM_D_5          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D50__MMDC_DRAM_D_50        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D51__MMDC_DRAM_D_51        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D52__MMDC_DRAM_D_52        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D53__MMDC_DRAM_D_53        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D54__MMDC_DRAM_D_54        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D55__MMDC_DRAM_D_55        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D56__MMDC_DRAM_D_56        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D57__MMDC_DRAM_D_57        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D58__MMDC_DRAM_D_58        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D59__MMDC_DRAM_D_59        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D6__MMDC_DRAM_D_6          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D60__MMDC_DRAM_D_60        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D61__MMDC_DRAM_D_61        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D62__MMDC_DRAM_D_62        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D63__MMDC_DRAM_D_63        = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D7__MMDC_DRAM_D_7          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D8__MMDC_DRAM_D_8          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_D9__MMDC_DRAM_D_9          = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0      = IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1      = IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2      = IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3      = IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4      = IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5      = IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6      = IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7      = IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS         = IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET     = IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0    = IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1    = IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2    = IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0  = IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1  = IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0  = IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1  = IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0    = IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1    = IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0    = IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1    = IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2    = IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3    = IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4    = IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5    = IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6    = IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7    = IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE       = IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A16__WEIM_WEIM_A_16         = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK      = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK       = IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0),
+       MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23     = IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A16__GPIO_2_22              = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A16__TPSMP_HDATA_6          = IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A16__SRC_BT_CFG_16          = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A16__EPDC_SDDO_0            = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A17__WEIM_WEIM_A_17         = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12      = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A17__IPU1_CSI1_D_12         = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0),
+       MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22     = IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A17__GPIO_2_21              = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A17__TPSMP_HDATA_5          = IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A17__SRC_BT_CFG_17          = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A17__EPDC_PWRSTAT           = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A18__WEIM_WEIM_A_18         = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13      = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A18__IPU1_CSI1_D_13         = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0),
+       MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21     = IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A18__GPIO_2_20              = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A18__TPSMP_HDATA_4          = IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A18__SRC_BT_CFG_18          = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A18__EPDC_PWRCTRL_0         = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A19__WEIM_WEIM_A_19         = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14      = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A19__IPU1_CSI1_D_14         = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0),
+       MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20     = IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A19__GPIO_2_19              = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A19__TPSMP_HDATA_3          = IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A19__SRC_BT_CFG_19          = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A19__EPDC_PWRCTRL_1         = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A20__WEIM_WEIM_A_20         = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15      = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A20__IPU1_CSI1_D_15         = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0),
+       MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19     = IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A20__GPIO_2_18              = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A20__TPSMP_HDATA_2          = IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A20__SRC_BT_CFG_20          = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A20__EPDC_PWRCTRL_2         = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A21__WEIM_WEIM_A_21         = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16      = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A21__IPU1_CSI1_D_16         = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0),
+       MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18     = IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A21__GPIO_2_17              = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A21__TPSMP_HDATA_1          = IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A21__SRC_BT_CFG_21          = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A21__EPDC_GDCLK             = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A22__WEIM_WEIM_A_22         = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17      = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A22__IPU1_CSI1_D_17         = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0),
+       MX6_PAD_EIM_A22__GPIO_2_16              = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A22__TPSMP_HDATA_0          = IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A22__SRC_BT_CFG_22          = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A22__EPDC_GDSP              = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A23__WEIM_WEIM_A_23         = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18      = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A23__IPU1_CSI1_D_18         = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0),
+       MX6_PAD_EIM_A23__IPU1_SISG_3            = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A23__GPIO_6_6               = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3   = IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A23__SRC_BT_CFG_23          = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A23__EPDC_GDOE              = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A24__WEIM_WEIM_A_24         = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19      = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A24__IPU1_CSI1_D_19         = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0),
+       MX6_PAD_EIM_A24__IPU1_SISG_2            = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A24__GPIO_5_4               = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2   = IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_A24__SRC_BT_CFG_24          = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A24__EPDC_GDRL              = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__WEIM_WEIM_A_25         = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__ECSPI4_SS1             = IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__ECSPI2_RDY             = IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__IPU1_DI1_PIN12         = IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__IPU1_DI0_D1_CS         = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__GPIO_5_2               = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE       = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0),
+       MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0  = IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__EPDC_SDDO_15           = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN      = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0),
+       MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK        = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16        = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_BCLK__GPIO_6_31             = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_BCLK__TPSMP_HDATA_31        = IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_BCLK__EPDC_SDCE_9           = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0         = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS0__IPU1_DI1_PIN5          = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS0__ECSPI2_SCLK            = IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0),
+       MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24     = IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS0__GPIO_2_23              = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS0__TPSMP_HDATA_7          = IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS0__EPDC_SDDO_6            = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1         = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS1__IPU1_DI1_PIN6          = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS1__ECSPI2_MOSI            = IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0),
+       MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25     = IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS1__GPIO_2_24              = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS1__TPSMP_HDATA_8          = IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_CS1__EPDC_SDDO_8            = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D16__WEIM_WEIM_D_16         = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0),
        MX6_PAD_EIM_D16__ECSPI1_SCLK            = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+       MX6_PAD_EIM_D16__IPU1_DI0_PIN5          = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D16__IPU1_CSI1_D_18         = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0),
+       MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA        = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0),
+       MX6_PAD_EIM_D16__GPIO_3_16              = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D16__I2C2_SDA               = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0),
+       MX6_PAD_EIM_D16__TPSMP_HTRANS_0         = IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D16__EPDC_SDDO_10           = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D17__WEIM_WEIM_D_17         = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0),
        MX6_PAD_EIM_D17__ECSPI1_MISO            = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+       MX6_PAD_EIM_D17__IPU1_DI0_PIN6          = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK       = IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0),
+       MX6_PAD_EIM_D17__DCIC1_DCIC_OUT         = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D17__GPIO_3_17              = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D17__I2C3_SCL               = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0),
+       MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1  = IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D17__EPDC_VCOM_0            = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D18__WEIM_WEIM_D_18         = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0),
        MX6_PAD_EIM_D18__ECSPI1_MOSI            = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+       MX6_PAD_EIM_D18__IPU1_DI0_PIN7          = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D18__IPU1_CSI1_D_17         = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0),
+       MX6_PAD_EIM_D18__IPU1_DI1_D0_CS         = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D18__GPIO_3_18              = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D18__I2C3_SDA               = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0),
+       MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2  = IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D18__EPDC_VCOM_1            = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D19__WEIM_WEIM_D_19         = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D19__ECSPI1_SS1             = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0),
+       MX6_PAD_EIM_D19__IPU1_DI0_PIN8          = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D19__IPU1_CSI1_D_16         = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0),
+       MX6_PAD_EIM_D19__UART1_CTS              = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D19__UART1_RTS              = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0),
        MX6_PAD_EIM_D19__GPIO_3_19              = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D19__EPIT1_EPITO            = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP     = IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D19__EPDC_SDDO_12           = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D20__WEIM_WEIM_D_20         = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D20__ECSPI4_SS0             = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0),
+       MX6_PAD_EIM_D20__IPU1_DI0_PIN16         = IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D20__IPU1_CSI1_D_15         = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0),
+       MX6_PAD_EIM_D20__UART1_CTS              = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D20__UART1_RTS              = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0),
+       MX6_PAD_EIM_D20__GPIO_3_20              = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D20__EPIT2_EPITO            = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D20__TPSMP_HTRANS_1         = IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D21__WEIM_WEIM_D_21         = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D21__ECSPI4_SCLK            = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D21__IPU1_DI0_PIN17         = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D21__IPU1_CSI1_D_11         = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0),
+       MX6_PAD_EIM_D21__USBOH3_USBOTG_OC       = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0),
        MX6_PAD_EIM_D21__GPIO_3_21              = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
        MX6_PAD_EIM_D21__I2C1_SCL               = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+       MX6_PAD_EIM_D21__SPDIF_IN1              = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0),
+       MX6_PAD_EIM_D22__WEIM_WEIM_D_22         = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D22__ECSPI4_MISO            = IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D22__IPU1_DI0_PIN1          = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D22__IPU1_CSI1_D_10         = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0),
+       MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR      = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D22__GPIO_3_22              = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D22__SPDIF_OUT1             = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE    = IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D22__EPDC_SDCE_6            = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__WEIM_WEIM_D_23         = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__IPU1_DI0_D0_CS         = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__UART3_CTS              = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__UART3_RTS              = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0),
+       MX6_PAD_EIM_D23__UART1_DCD              = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN      = IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0),
        MX6_PAD_EIM_D23__GPIO_3_23              = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__IPU1_DI1_PIN2          = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__IPU1_DI1_PIN14         = IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D23__EPDC_SDDO_11           = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D24__WEIM_WEIM_D_24         = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D24__ECSPI4_SS2             = IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D24__UART3_TXD              = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D24__UART3_RXD              = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0),
+       MX6_PAD_EIM_D24__ECSPI1_SS2             = IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0),
+       MX6_PAD_EIM_D24__ECSPI2_SS2             = IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D24__GPIO_3_24              = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS       = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0),
+       MX6_PAD_EIM_D24__UART1_DTR              = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D24__EPDC_SDCE_7            = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D25__WEIM_WEIM_D_25         = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D25__ECSPI4_SS3             = IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D25__UART3_TXD              = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D25__UART3_RXD              = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0),
+       MX6_PAD_EIM_D25__ECSPI1_SS3             = IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0),
+       MX6_PAD_EIM_D25__ECSPI2_SS3             = IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D25__GPIO_3_25              = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC        = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0),
+       MX6_PAD_EIM_D25__UART1_DSR              = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D25__EPDC_SDCE_8            = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__WEIM_WEIM_D_26         = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__IPU1_DI1_PIN11         = IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__IPU1_CSI0_D_1          = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__IPU1_CSI1_D_14         = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0),
        MX6_PAD_EIM_D26__UART2_TXD              = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__UART2_RXD              = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0),
+       MX6_PAD_EIM_D26__GPIO_3_26              = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__IPU1_SISG_2            = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22      = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D26__EPDC_SDOED             = IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D27__WEIM_WEIM_D_27         = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D27__IPU1_DI1_PIN13         = IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D27__IPU1_CSI0_D_0          = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D27__IPU1_CSI1_D_13         = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0),
+       MX6_PAD_EIM_D27__UART2_TXD              = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0),
        MX6_PAD_EIM_D27__UART2_RXD              = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+       MX6_PAD_EIM_D27__GPIO_3_27              = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D27__IPU1_SISG_3            = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23      = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D27__EPDC_SDOE              = IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D28__WEIM_WEIM_D_28         = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0),
        MX6_PAD_EIM_D28__I2C1_SDA               = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+       MX6_PAD_EIM_D28__ECSPI4_MOSI            = IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D28__IPU1_CSI1_D_12         = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0),
+       MX6_PAD_EIM_D28__UART2_CTS              = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D28__UART2_RTS              = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0),
        MX6_PAD_EIM_D28__GPIO_3_28              = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D28__IPU1_EXT_TRIG          = IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D28__IPU1_DI0_PIN13         = IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D28__EPDC_PWRCTRL_3         = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D29__WEIM_WEIM_D_29         = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D29__IPU1_DI1_PIN15         = IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D29__ECSPI4_SS0             = IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0),
+       MX6_PAD_EIM_D29__UART2_CTS              = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D29__UART2_RTS              = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0),
        MX6_PAD_EIM_D29__GPIO_3_29              = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC        = IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0),
+       MX6_PAD_EIM_D29__IPU1_DI0_PIN14         = IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D29__EPDC_PWRWAKE           = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__WEIM_WEIM_D_30         = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21      = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__IPU1_DI0_PIN11         = IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__IPU1_CSI0_D_3          = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__UART3_CTS              = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__UART3_RTS              = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0),
+       MX6_PAD_EIM_D30__GPIO_3_30              = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__USBOH3_USBH1_OC        = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0),
+       MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0   = IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D30__EPDC_SDOEZ             = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__WEIM_WEIM_D_31         = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20      = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__IPU1_DI0_PIN12         = IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__IPU1_CSI0_D_2          = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__UART3_CTS              = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__UART3_RTS              = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0),
+       MX6_PAD_EIM_D31__GPIO_3_31              = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__USBOH3_USBH1_PWR       = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1   = IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__EPDC_SDCLK             = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN      = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0       = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9       = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__IPU1_CSI1_D_9          = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2      = IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__GPIO_3_0               = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__TPSMP_HDATA_14         = IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__SRC_BT_CFG_0           = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA0__EPDC_SDCLKN            = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1       = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8       = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__IPU1_CSI1_D_8          = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3      = IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__GPIO_3_1               = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__TPSMP_HDATA_15         = IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__SRC_BT_CFG_1           = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA1__EPDC_SDLE              = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10     = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA10__IPU1_DI1_PIN15        = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN     = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0),
+       MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12    = IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA10__GPIO_3_10             = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA10__TPSMP_HDATA_24        = IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA10__SRC_BT_CFG_10         = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA10__EPDC_SDDO_1           = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11     = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__IPU1_DI1_PIN2         = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC       = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0),
+       MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13    = IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6    = IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__GPIO_3_11             = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__TPSMP_HDATA_25        = IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__SRC_BT_CFG_11         = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA11__EPDC_SDDO_3           = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12     = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__IPU1_DI1_PIN3         = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC       = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0),
+       MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14    = IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3    = IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__GPIO_3_12             = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__TPSMP_HDATA_26        = IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__SRC_BT_CFG_12         = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA12__EPDC_SDDO_2           = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13     = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS        = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK       = IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0),
+       MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15    = IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4    = IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__GPIO_3_13             = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__TPSMP_HDATA_27        = IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__SRC_BT_CFG_13         = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA13__EPDC_SDDO_13          = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14     = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS        = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK       = IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16    = IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5    = IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__GPIO_3_14             = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__TPSMP_HDATA_28        = IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__SRC_BT_CFG_14         = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA14__EPDC_SDDO_14          = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15     = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__IPU1_DI1_PIN1         = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__IPU1_DI1_PIN4         = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17    = IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__GPIO_3_15             = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__TPSMP_HDATA_29        = IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__SRC_BT_CFG_15         = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA15__EPDC_SDDO_9           = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2       = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7       = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__IPU1_CSI1_D_7          = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4      = IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__GPIO_3_2               = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__TPSMP_HDATA_16         = IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__SRC_BT_CFG_2           = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA2__EPDC_BDR_0             = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3       = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6       = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__IPU1_CSI1_D_6          = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5      = IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ     = IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__GPIO_3_3               = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__TPSMP_HDATA_17         = IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__SRC_BT_CFG_3           = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA3__EPDC_BDR_1             = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4       = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5       = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__IPU1_CSI1_D_5          = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6      = IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN      = IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__GPIO_3_4               = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__TPSMP_HDATA_18         = IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__SRC_BT_CFG_4           = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA4__EPDC_SDCE_0            = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5       = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4       = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__IPU1_CSI1_D_4          = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7      = IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP      = IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__GPIO_3_5               = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__TPSMP_HDATA_19         = IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__SRC_BT_CFG_5           = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA5__EPDC_SDCE_1            = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6       = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3       = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__IPU1_CSI1_D_3          = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8      = IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN      = IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__GPIO_3_6               = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__TPSMP_HDATA_20         = IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__SRC_BT_CFG_6           = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA6__EPDC_SDCE_2            = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7       = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2       = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__IPU1_CSI1_D_2          = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9      = IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__GPIO_3_7               = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__TPSMP_HDATA_21         = IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__SRC_BT_CFG_7           = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA7__EPDC_SDCE_3            = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8       = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1       = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__IPU1_CSI1_D_1          = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10     = IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__GPIO_3_8               = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__TPSMP_HDATA_22         = IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__SRC_BT_CFG_8           = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA8__EPDC_SDCE_4            = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9       = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0       = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA9__IPU1_CSI1_D_0          = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11     = IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0),
        MX6_PAD_EIM_DA9__GPIO_3_9               = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA9__TPSMP_HDATA_23         = IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA9__SRC_BT_CFG_9           = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_DA9__EPDC_SDCE_5            = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0         = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11      = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB0__IPU1_CSI1_D_11         = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0),
+       MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0      = IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB0__CCM_PMIC_RDY           = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0),
+       MX6_PAD_EIM_EB0__GPIO_2_28              = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB0__TPSMP_HDATA_12         = IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB0__SRC_BT_CFG_27          = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB0__EPDC_PWRCOM            = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1         = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10      = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB1__IPU1_CSI1_D_10         = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0),
+       MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1      = IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB1__GPIO_2_29              = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB1__TPSMP_HDATA_13         = IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB1__SRC_BT_CFG_28          = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB1__EPDC_SDSHR             = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2         = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB2__ECSPI1_SS0             = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0),
+       MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK        = IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0),
+       MX6_PAD_EIM_EB2__IPU1_CSI1_D_19         = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0),
+       MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL        = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0),
+       MX6_PAD_EIM_EB2__GPIO_2_30              = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB2__I2C2_SCL               = IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0),
+       MX6_PAD_EIM_EB2__SRC_BT_CFG_30          = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB2__EPDC_SDDO_5            = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3         = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__ECSPI4_RDY             = IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__UART3_CTS              = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__UART3_RTS              = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0),
+       MX6_PAD_EIM_EB3__UART1_RI               = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC        = IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0),
+       MX6_PAD_EIM_EB3__GPIO_2_31              = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__IPU1_DI1_PIN3          = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__SRC_BT_CFG_31          = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__EPDC_SDCE_0            = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_EB3__WEIM_ACLK_FREERUN      = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0),
+       MX6_PAD_EIM_LBA__WEIM_WEIM_LBA          = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_LBA__IPU1_DI1_PIN17         = IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_LBA__ECSPI2_SS1             = IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0),
+       MX6_PAD_EIM_LBA__GPIO_2_27              = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_LBA__TPSMP_HDATA_11         = IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_LBA__SRC_BT_CFG_26          = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_LBA__EPDC_SDDO_4            = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_OE__WEIM_WEIM_OE            = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_OE__IPU1_DI1_PIN7           = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_OE__ECSPI2_MISO             = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0),
+       MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26      = IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_OE__GPIO_2_25               = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_OE__TPSMP_HDATA_9           = IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_OE__EPDC_PWRIRQ             = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_RW__WEIM_WEIM_RW            = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_RW__IPU1_DI1_PIN8           = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_RW__ECSPI2_SS0              = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0),
+       MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27      = IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0),
+       MX6_PAD_EIM_RW__GPIO_2_26               = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_RW__TPSMP_HDATA_10          = IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_RW__SRC_BT_CFG_29           = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0),
+       MX6_PAD_EIM_RW__EPDC_SDDO_7             = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0),
+       MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT        = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0),
+       MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B     = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0),
+       MX6_PAD_EIM_WAIT__GPIO_5_0              = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0),
+       MX6_PAD_EIM_WAIT__TPSMP_HDATA_30        = IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0),
+       MX6_PAD_EIM_WAIT__SRC_BT_CFG_25         = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_CRS_DV__ENET_RX_EN         = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0),
+       MX6_PAD_ENET_CRS_DV__ESAI1_SCKT         = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0),
+       MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0),
+       MX6_PAD_ENET_CRS_DV__GPIO_1_25          = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_CRS_DV__PHY_TDO            = IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0),
+       MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD      = IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_MDC__MLB_MLBDAT            = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0),
        MX6_PAD_ENET_MDC__ENET_MDC              = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0,  0),
+       MX6_PAD_ENET_MDC__ESAI1_TX5_RX0         = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0),
+       MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN   = IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0),
+       MX6_PAD_ENET_MDC__GPIO_1_31             = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET     = IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0),
        MX6_PAD_ENET_MDIO__ENET_MDIO            = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+       MX6_PAD_ENET_MDIO__ESAI1_SCKR           = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0),
+       MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3      = IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0),
+       MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0),
+       MX6_PAD_ENET_MDIO__GPIO_1_22            = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_MDIO__SPDIF_PLOCK          = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0),
        MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+       MX6_PAD_ENET_REF_CLK__ESAI1_FSR         = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0),
+       MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4   = IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0),
+       MX6_PAD_ENET_REF_CLK__GPIO_1_23         = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK       = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0),
+       MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH    = IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID    = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0),
+       MX6_PAD_ENET_RX_ER__ENET_RX_ER          = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0),
+       MX6_PAD_ENET_RX_ER__ESAI1_HCKR          = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0),
+       MX6_PAD_ENET_RX_ER__SPDIF_IN1           = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0),
+       MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT        = IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0),
+       MX6_PAD_ENET_RX_ER__GPIO_1_24           = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_RX_ER__PHY_TDI             = IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0),
+       MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD       = IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD0__OSC32K_32K_OUT       = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD0__ENET_RDATA_0         = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0),
+       MX6_PAD_ENET_RXD0__ESAI1_HCKT           = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0),
+       MX6_PAD_ENET_RXD0__SPDIF_OUT1           = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
        MX6_PAD_ENET_RXD0__GPIO_1_27            = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD0__PHY_TMS              = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV     = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD1__MLB_MLBSIG           = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0),
+       MX6_PAD_ENET_RXD1__ENET_RDATA_1         = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0),
+       MX6_PAD_ENET_RXD1__ESAI1_FST            = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0),
+       MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD1__GPIO_1_26            = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD1__PHY_TCK              = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
+       MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET    = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_TX_EN__ENET_TX_EN          = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0),
+       MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2       = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0),
+       MX6_PAD_ENET_TX_EN__GPIO_1_28           = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH      = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_TX_EN__I2C4_SCL            = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0),
+       MX6_PAD_ENET_TXD0__ENET_TDATA_0         = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
+       MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1        = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0),
+       MX6_PAD_ENET_TXD0__GPIO_1_30            = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD        = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_TXD1__MLB_MLBCLK           = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0),
+       MX6_PAD_ENET_TXD1__ENET_TDATA_1         = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0),
+       MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3        = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0),
+       MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN  = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
+       MX6_PAD_ENET_TXD1__GPIO_1_29            = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
+       MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD        = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
+       MX6_PAD_ENET_TXD1__I2C4_SDA             = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0),
+       MX6_PAD_GPIO_0__CCM_CLKO                = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0),
+       MX6_PAD_GPIO_0__KPP_COL_5               = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0),
+       MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK       = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0),
+       MX6_PAD_GPIO_0__EPIT1_EPITO             = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_0__GPIO_1_0                = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_0__USBOH3_USBH1_PWR        = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5      = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_1__ESAI1_SCKR              = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0),
+       MX6_PAD_GPIO_1__WDOG2_WDOG_B            = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_1__KPP_ROW_5               = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0),
+       MX6_PAD_GPIO_1__USBOTG_ID               = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
+       MX6_PAD_GPIO_1__PWM2_PWMO               = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_1__GPIO_1_1                = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_1__USDHC1_CD               = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_1__SRC_TESTER_ACK          = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_16__ESAI1_TX3_RX2          = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0),
+       MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN    = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT   = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0),
+       MX6_PAD_GPIO_16__USDHC1_LCTL            = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_16__SPDIF_IN1              = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0),
        MX6_PAD_GPIO_16__GPIO_7_11              = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
        MX6_PAD_GPIO_16__I2C3_SDA               = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+       MX6_PAD_GPIO_16__SJC_DE_B               = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_17__ESAI1_TX0              = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0),
+       MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN    = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_17__CCM_PMIC_RDY           = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0),
+       MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0  = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0),
+       MX6_PAD_GPIO_17__SPDIF_OUT1             = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
        MX6_PAD_GPIO_17__GPIO_7_12              = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_17__SJC_JTAG_ACT           = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_18__ESAI1_TX1              = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0),
+       MX6_PAD_GPIO_18__ENET_RX_CLK            = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0),
+       MX6_PAD_GPIO_18__USDHC3_VSELECT         = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
+       MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1  = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0),
+       MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK      = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0),
        MX6_PAD_GPIO_18__GPIO_7_13              = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_18__SRC_SYSTEM_RST         = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_19__KPP_COL_5              = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0),
+       MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT   = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_19__SPDIF_OUT1             = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0),
+       MX6_PAD_GPIO_19__CCM_CLKO               = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_19__ECSPI1_RDY             = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
        MX6_PAD_GPIO_19__GPIO_4_5               = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_19__ENET_TX_ER             = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_19__SRC_INT_BOOT           = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_2__ESAI1_FST               = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0),
+       MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2      = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_2__KPP_ROW_6               = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0),
+       MX6_PAD_GPIO_2__CCM_CCM_OUT_1           = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0     = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
        MX6_PAD_GPIO_2__GPIO_1_2                = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_2__USDHC2_WP               = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_2__MLB_MLBDAT              = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0),
+       MX6_PAD_GPIO_3__ESAI1_HCKR              = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0),
+       MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0      = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_3__I2C3_SCL                = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0),
+       MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT   = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_3__CCM_CLKO2               = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_3__GPIO_1_3                = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_3__USBOH3_USBH1_OC         = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0),
+       MX6_PAD_GPIO_3__MLB_MLBCLK              = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0),
+       MX6_PAD_GPIO_4__ESAI1_HCKT              = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0),
+       MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3      = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_4__KPP_COL_7               = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0),
+       MX6_PAD_GPIO_4__CCM_CCM_OUT_2           = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1     = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_4__GPIO_1_4                = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_4__USDHC2_CD               = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_5__ESAI1_TX2_RX3           = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0),
+       MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4      = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_5__KPP_ROW_7               = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0),
+       MX6_PAD_GPIO_5__CCM_CLKO                = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2     = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
        MX6_PAD_GPIO_5__GPIO_1_5                = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
        MX6_PAD_GPIO_5__I2C3_SCL                = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+       MX6_PAD_GPIO_5__SIMBA_EVENTI            = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_6__ESAI1_SCKT              = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0),
+       MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1      = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_6__I2C3_SDA                = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0),
+       MX6_PAD_GPIO_6__CCM_CCM_OUT_0           = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_6__CSU_CSU_INT_DEB         = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_6__GPIO_1_6                = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_6__USDHC2_LCTL             = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_6__MLB_MLBSIG              = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0),
+       MX6_PAD_GPIO_7__ESAI1_TX4_RX1           = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0),
+       MX6_PAD_GPIO_7__EPIT1_EPITO             = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0),
+       MX6_PAD_GPIO_7__CAN1_TXCAN              = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_7__UART2_TXD               = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_7__UART2_RXD               = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0),
+       MX6_PAD_GPIO_7__GPIO_1_7                = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_7__SPDIF_PLOCK             = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_7__I2C4_SCL                = IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0),
+       MX6_PAD_GPIO_8__ESAI1_TX5_RX0           = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0),
+       MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT   = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_8__EPIT2_EPITO             = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0),
+       MX6_PAD_GPIO_8__CAN1_RXCAN              = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0),
+       MX6_PAD_GPIO_8__UART2_TXD               = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_8__UART2_RXD               = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0),
+       MX6_PAD_GPIO_8__GPIO_1_8                = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_8__SPDIF_SRCLK             = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0),
+       MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP     = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
+       MX6_PAD_GPIO_8__I2C4_SDA                = IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0),
+       MX6_PAD_GPIO_9__ESAI1_FSR               = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0),
+       MX6_PAD_GPIO_9__WDOG1_WDOG_B            = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
+       MX6_PAD_GPIO_9__KPP_COL_6               = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0),
+       MX6_PAD_GPIO_9__CCM_REF_EN_B            = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
+       MX6_PAD_GPIO_9__PWM1_PWMO               = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
+       MX6_PAD_GPIO_9__GPIO_1_9                = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
+       MX6_PAD_GPIO_9__USDHC1_WP               = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0),
+       MX6_PAD_GPIO_9__SRC_EARLY_RST           = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
+       MX6_PAD_JTAG_MOD__SJC_MOD               = IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_JTAG_TCK__SJC_TCK               = IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_JTAG_TDI__SJC_TDI               = IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_JTAG_TDO__SJC_TDO               = IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_JTAG_TMS__SJC_TMS               = IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_JTAG_TRSTB__SJC_TRSTB           = IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL0__ECSPI1_SCLK           = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0),
+       MX6_PAD_KEY_COL0__ENET_RDATA_3          = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0),
+       MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC       = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0),
+       MX6_PAD_KEY_COL0__KPP_COL_0             = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL0__UART4_TXD             = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL0__UART4_RXD             = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0),
+       MX6_PAD_KEY_COL0__GPIO_4_6              = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT        = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL0__SRC_ANY_PU_RST        = IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL1__ECSPI1_MISO           = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0),
+       MX6_PAD_KEY_COL1__ENET_MDIO             = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0),
+       MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS      = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0),
+       MX6_PAD_KEY_COL1__KPP_COL_1             = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL1__UART5_TXD             = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL1__UART5_RXD             = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0),
+       MX6_PAD_KEY_COL1__GPIO_4_8              = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL1__USDHC1_VSELECT        = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1  = IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL2__ECSPI1_SS1            = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0),
+       MX6_PAD_KEY_COL2__ENET_RDATA_2          = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0),
+       MX6_PAD_KEY_COL2__CAN1_TXCAN            = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL2__KPP_COL_2             = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL2__ENET_MDC              = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL2__GPIO_4_10             = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP    = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3  = IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL3__ECSPI1_SS3            = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0),
+       MX6_PAD_KEY_COL3__ENET_CRS              = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL       = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0),
+       MX6_PAD_KEY_COL3__KPP_COL_3             = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0),
        MX6_PAD_KEY_COL3__I2C2_SCL              = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
        MX6_PAD_KEY_COL3__GPIO_4_12             = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL3__SPDIF_IN1             = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0),
+       MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5  = IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL4__CAN2_TXCAN            = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL4__IPU1_SISG_4           = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC      = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0),
+       MX6_PAD_KEY_COL4__KPP_COL_4             = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL4__UART5_CTS             = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL4__UART5_RTS             = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0),
+       MX6_PAD_KEY_COL4__GPIO_4_14             = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49    = IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7  = IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW0__ECSPI1_MOSI           = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0),
+       MX6_PAD_KEY_ROW0__ENET_TDATA_3          = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD       = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0),
+       MX6_PAD_KEY_ROW0__KPP_ROW_0             = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW0__UART4_TXD             = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW0__UART4_RXD             = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0),
+       MX6_PAD_KEY_ROW0__GPIO_4_7              = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT        = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0  = IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW1__ECSPI1_SS0            = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0),
+       MX6_PAD_KEY_ROW1__ENET_COL              = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD       = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0),
+       MX6_PAD_KEY_ROW1__KPP_ROW_1             = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW1__UART5_TXD             = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW1__UART5_RXD             = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0),
+       MX6_PAD_KEY_ROW1__GPIO_4_9              = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW1__USDHC2_VSELECT        = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2  = IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW2__ECSPI1_SS2            = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0),
+       MX6_PAD_KEY_ROW2__ENET_TDATA_2          = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW2__CAN1_RXCAN            = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0),
+       MX6_PAD_KEY_ROW2__KPP_ROW_2             = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW2__USDHC2_VSELECT        = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW2__GPIO_4_11             = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE      = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0),
+       MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4  = IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW3__OSC32K_32K_OUT        = IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK     = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0),
+       MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA       = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0),
+       MX6_PAD_KEY_ROW3__KPP_ROW_3             = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0),
        MX6_PAD_KEY_ROW3__I2C2_SDA              = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
        MX6_PAD_KEY_ROW3__GPIO_4_13             = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW3__USDHC1_VSELECT        = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6  = IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW4__CAN2_RXCAN            = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0),
+       MX6_PAD_KEY_ROW4__IPU1_SISG_5           = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR     = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW4__KPP_ROW_4             = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW4__UART5_CTS             = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW4__UART5_RTS             = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0),
+       MX6_PAD_KEY_ROW4__GPIO_4_15             = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50    = IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0),
+       MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8  = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0),
+       MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3      = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__RAWNAND_ALE          = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__USDHC4_RST           = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0      = IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12        = IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12        = IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__GPIO_6_8             = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24    = IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_ALE__USDHC3_CLKI          = IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, 0),
+       MX6_PAD_NANDF_CLE__RAWNAND_CLE          = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31     = IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11        = IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11        = IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CLE__GPIO_6_7             = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23    = IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CLE__USDHC3_CLKO          = IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS0__RAWNAND_CE0N         = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15        = IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15        = IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS0__GPIO_6_11            = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS0__USDHC1_CLKO          = IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS1__RAWNAND_CE1N         = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS1__USDHC4_VSELECT       = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS1__USDHC3_VSELECT       = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3      = IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_CS1__GPIO_6_14            = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT       = IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS1__USDHC1_CLKI          = IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0),
+       MX6_PAD_NANDF_CS2__RAWNAND_CE2N         = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS2__IPU1_SISG_0          = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS2__ESAI1_TX0            = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0),
+       MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE        = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS2__CCM_CLKO2            = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_CS2__GPIO_6_15            = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS2__USDHC2_CLKO          = IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS3__RAWNAND_CE3N         = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS3__IPU1_SISG_1          = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS3__ESAI1_TX1            = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0),
+       MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26       = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4      = IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_CS3__GPIO_6_16            = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS3__TPSMP_CLK            = IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0),
+       MX6_PAD_NANDF_CS3__USDHC2_CLKI          = IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, 0),
+       MX6_PAD_NANDF_CS3__I2C4_SDA             = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0),
+       MX6_PAD_NANDF_D0__RAWNAND_D0            = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D0__USDHC1_DAT4           = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D0__GPIO_2_0              = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0   = IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D1__RAWNAND_D1            = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D1__USDHC1_DAT5           = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_D1__GPIO_2_1              = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1   = IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D2__RAWNAND_D2            = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D2__USDHC1_DAT6           = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_D2__GPIO_2_2              = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2   = IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D3__RAWNAND_D3            = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D3__USDHC1_DAT7           = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_D3__GPIO_2_3              = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3   = IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D4__RAWNAND_D4            = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D4__USDHC2_DAT4           = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_D4__GPIO_2_4              = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4   = IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D5__RAWNAND_D5            = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D5__USDHC2_DAT5           = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D5__GPIO_2_5              = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5   = IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D6__RAWNAND_D6            = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D6__USDHC2_DAT6           = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0),
        MX6_PAD_NANDF_D6__GPIO_2_6              = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
-       MX6_PAD_RGMII_RD0__ENET_RGMII_RD0     = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+       MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6   = IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D7__RAWNAND_D7            = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D7__USDHC2_DAT7           = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D7__GPIO_2_7              = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7   = IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_RB0__RAWNAND_READY0       = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2      = IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14        = IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14        = IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_RB0__GPIO_6_10            = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33   = IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_RB0__USDHC4_CLKI          = IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, 0),
+       MX6_PAD_NANDF_WP_B__RAWNAND_RESETN      = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
+       MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1     = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
+       MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13       = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
+       MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13       = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
+       MX6_PAD_NANDF_WP_B__GPIO_6_9            = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
+       MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32  = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
+       MX6_PAD_NANDF_WP_B__USDHC4_CLKO         = IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0),
+       MX6_PAD_NANDF_WP_B__I2C4_SCL            = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0),
+       MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM  = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ       = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_POR_B__SRC_POR_B                = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_RESET_IN_B__SRC_RESET_B         = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY       = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
        MX6_PAD_RGMII_RD0__GPIO_6_25            = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6     = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG        = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
        MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
        MX6_PAD_RGMII_RD1__GPIO_6_27            = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8     = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD1__SJC_FAIL             = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA        = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
        MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
        MX6_PAD_RGMII_RD2__GPIO_6_28            = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9     = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE        = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0),
        MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
        MX6_PAD_RGMII_RD3__GPIO_6_29            = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10    = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA    = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
        MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
-       MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RX_CTL__GPIO_6_24         = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5  = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE     = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE_START       = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP),
        MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
        MX6_PAD_RGMII_RXC__GPIO_6_30            = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11    = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY       = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
        MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD0__GPIO_6_20            = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1     = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG        = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
        MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD1__GPIO_6_21            = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2     = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD1__CCM_PLL3_BYP         = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA        = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
        MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD2__GPIO_6_22            = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3     = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD2__CCM_PLL2_BYP         = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE        = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
        MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD3__GPIO_6_23            = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4     = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE  = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START    = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP),
        MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TX_CTL__GPIO_6_26         = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7  = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT      = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0),
+       MX6_PAD_RGMII_TXC__USBOH3_H2_DATA       = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
        MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK   = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0),
+       MX6_PAD_RGMII_TXC__GPIO_6_19            = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0     = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
+       MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT        = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
        MX6_PAD_SD1_CLK__USDHC1_CLK             = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0),
+       MX6_PAD_SD1_CLK__OSC32K_32K_OUT         = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
+       MX6_PAD_SD1_CLK__GPT_CLKIN              = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
+       MX6_PAD_SD1_CLK__GPIO_1_20              = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
+       MX6_PAD_SD1_CLK__PHY_DTB_0              = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
        MX6_PAD_SD1_CMD__USDHC1_CMD             = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6_PAD_SD1_CMD__PWM4_PWMO              = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
+       MX6_PAD_SD1_CMD__GPT_CMPOUT1            = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
        MX6_PAD_SD1_CMD__GPIO_1_18              = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
-       MX6_PAD_SD1_DAT3__GPIO_1_21             = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+       MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5  = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
        MX6_PAD_SD1_DAT0__USDHC1_DAT0           = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS      = IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT0__GPT_CAPIN1            = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8       = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT0__GPIO_1_16             = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1     = IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
        MX6_PAD_SD1_DAT1__USDHC1_DAT1           = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT1__PWM3_PWMO             = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT1__GPT_CAPIN2            = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7       = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT1__GPIO_1_17             = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0     = IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
        MX6_PAD_SD1_DAT2__USDHC1_DAT2           = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT2__GPT_CMPOUT2           = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT2__PWM2_PWMO             = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT2__WDOG1_WDOG_B          = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT2__GPIO_1_19             = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB  = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 = IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0),
        MX6_PAD_SD1_DAT3__USDHC1_DAT3           = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT3__GPT_CMPOUT3           = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT3__PWM1_PWMO             = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT3__WDOG2_WDOG_B          = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT3__GPIO_1_21             = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB  = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
+       MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
+       MX6_PAD_SD2_CLK__USDHC2_CLK             = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0),
+       MX6_PAD_SD2_CLK__KPP_COL_5              = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0),
+       MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS       = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0),
+       MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9        = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
+       MX6_PAD_SD2_CLK__GPIO_1_10              = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
+       MX6_PAD_SD2_CLK__PHY_DTB_1              = IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0),
+       MX6_PAD_SD2_CMD__USDHC2_CMD             = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6_PAD_SD2_CMD__KPP_ROW_5              = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0),
+       MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC        = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0),
+       MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10       = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
+       MX6_PAD_SD2_CMD__GPIO_1_11              = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT0__USDHC2_DAT0           = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD       = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0),
+       MX6_PAD_SD2_DAT0__KPP_ROW_7             = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0),
+       MX6_PAD_SD2_DAT0__GPIO_1_15             = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT        = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT1__USDHC2_DAT1           = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2        = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS      = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0),
+       MX6_PAD_SD2_DAT1__KPP_COL_7             = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0),
+       MX6_PAD_SD2_DAT1__GPIO_1_14             = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT1__CCM_WAIT              = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT2__USDHC2_DAT2           = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3        = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD       = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0),
+       MX6_PAD_SD2_DAT2__KPP_ROW_6             = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0),
+       MX6_PAD_SD2_DAT2__GPIO_1_13             = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT2__CCM_STOP              = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT3__USDHC2_DAT3           = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT3__KPP_COL_6             = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0),
+       MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC       = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0),
+       MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11      = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT3__GPIO_1_12             = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT3__SJC_DONE              = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
+       MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
        MX6_PAD_SD3_CLK__USDHC3_CLK             = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+       MX6_PAD_SD3_CLK__UART2_CTS              = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_CLK__UART2_RTS              = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0),
+       MX6_PAD_SD3_CLK__CAN1_RXCAN             = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0),
+       MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5   = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5   = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_CLK__GPIO_7_3               = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17      = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
        MX6_PAD_SD3_CMD__USDHC3_CMD             = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6_PAD_SD3_CMD__UART2_CTS              = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_CMD__UART2_RTS              = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0),
+       MX6_PAD_SD3_CMD__CAN1_TXCAN             = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4   = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4   = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_CMD__GPIO_7_2               = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16      = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
        MX6_PAD_SD3_DAT0__USDHC3_DAT0           = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT0__UART1_CTS             = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT0__UART1_RTS             = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0),
+       MX6_PAD_SD3_DAT0__CAN2_TXCAN            = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6  = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6  = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT0__GPIO_7_4              = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18     = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15        = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
        MX6_PAD_SD3_DAT1__USDHC3_DAT1           = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT1__UART1_CTS             = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT1__UART1_RTS             = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0),
+       MX6_PAD_SD3_DAT1__CAN2_RXCAN            = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0),
+       MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7  = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7  = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT1__GPIO_7_5              = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19     = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
        MX6_PAD_SD3_DAT2__USDHC3_DAT2           = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28      = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8  = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8  = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT2__GPIO_7_6              = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20     = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
        MX6_PAD_SD3_DAT3__USDHC3_DAT3           = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT3__UART3_CTS             = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT3__UART3_RTS             = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0),
+       MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29      = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9  = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9  = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT3__GPIO_7_7              = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21     = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__USDHC3_DAT4           = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__UART2_TXD             = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__UART2_RXD             = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0),
+       MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27      = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3  = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3  = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__GPIO_7_1              = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15     = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12        = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT5__USDHC3_DAT5           = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT5__UART2_TXD             = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT5__UART2_RXD             = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0),
+       MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26      = IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2  = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2  = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
        MX6_PAD_SD3_DAT5__GPIO_7_0              = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14     = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11        = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT6__USDHC3_DAT6           = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT6__UART1_TXD             = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
        MX6_PAD_SD3_DAT6__UART1_RXD             = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+       MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25      = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1  = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1  = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT6__GPIO_6_18             = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13     = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10        = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT7__USDHC3_DAT7           = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
        MX6_PAD_SD3_DAT7__UART1_TXD             = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT7__UART1_RXD             = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0),
+       MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24      = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0  = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0  = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT7__GPIO_6_17             = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12     = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV      = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__USDHC3_RST             = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__UART3_CTS              = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__UART3_RTS              = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0),
+       MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30       = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10  = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10  = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__GPIO_7_8               = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22      = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
+       MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3  = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
        MX6_PAD_SD4_CLK__USDHC4_CLK             = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+       MX6_PAD_SD4_CLK__RAWNAND_WRN            = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_CLK__UART3_TXD              = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_CLK__UART3_RXD              = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0),
+       MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6        = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_CLK__GPIO_7_10              = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
        MX6_PAD_SD4_CMD__USDHC4_CMD             = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6_PAD_SD4_CMD__RAWNAND_RDN            = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_CMD__UART3_TXD              = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_CMD__UART3_RXD              = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0),
+       MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5        = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_CMD__GPIO_7_9               = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT0__RAWNAND_D8            = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
        MX6_PAD_SD4_DAT0__USDHC4_DAT0           = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT0__RAWNAND_DQS           = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT0__GPIO_2_8              = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8   = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT1__RAWNAND_D9            = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
        MX6_PAD_SD4_DAT1__USDHC4_DAT1           = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT1__PWM3_PWMO             = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT1__GPIO_2_9              = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9   = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT2__RAWNAND_D10           = IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0),
        MX6_PAD_SD4_DAT2__USDHC4_DAT2           = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT2__PWM4_PWMO             = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT2__GPIO_2_10             = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10  = IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT3__RAWNAND_D11           = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
        MX6_PAD_SD4_DAT3__USDHC4_DAT3           = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT3__GPIO_2_11             = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11  = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT4__RAWNAND_D12           = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT4__USDHC4_DAT4           = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT4__UART2_TXD             = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT4__UART2_RXD             = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0),
+       MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT4__GPIO_2_12             = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12  = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT5__RAWNAND_D13           = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT5__USDHC4_DAT5           = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT5__UART2_CTS             = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT5__UART2_RTS             = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0),
+       MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT5__GPIO_2_13             = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13  = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT6__RAWNAND_D14           = IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT6__USDHC4_DAT6           = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT6__UART2_CTS             = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT6__UART2_RTS             = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0),
+       MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT6__GPIO_2_14             = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14  = IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT7__RAWNAND_D15           = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT7__USDHC4_DAT7           = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT7__UART2_TXD             = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT7__UART2_RXD             = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0),
+       MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT7__GPIO_2_15             = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
+       MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15  = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
 };
 #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */

diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h
index 8bba3b0..d72f5e5 100644 (file)
--- a/arch/arm/include/asm/arch-omap3/gpio.h
+++ b/arch/arm/include/asm/arch-omap3/gpio.h
@@ -40,6 +40,8 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO                  192
+
 #define OMAP34XX_GPIO1_BASE            0x48310000
 #define OMAP34XX_GPIO2_BASE            0x49050000
 #define OMAP34XX_GPIO3_BASE            0x49052000

diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h
index 26f19d1..fdf65ed 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/gpio.h
+++ b/arch/arm/include/asm/arch-omap4/gpio.h
@@ -40,6 +40,8 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO                  192
+
 #define OMAP44XX_GPIO1_BASE            0x4A310000
 #define OMAP44XX_GPIO2_BASE            0x48055000
 #define OMAP44XX_GPIO3_BASE            0x48057000

diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
index c14dff0..7c82f90 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -40,11 +40,15 @@
 
 #include <asm/omap_gpio.h>
 
+#define OMAP_MAX_GPIO                  256
+
 #define OMAP54XX_GPIO1_BASE            0x4Ae10000
 #define OMAP54XX_GPIO2_BASE            0x48055000
 #define OMAP54XX_GPIO3_BASE            0x48057000
 #define OMAP54XX_GPIO4_BASE            0x48059000
 #define OMAP54XX_GPIO5_BASE            0x4805B000
 #define OMAP54XX_GPIO6_BASE            0x4805D000
+#define OMAP54XX_GPIO7_BASE            0x48051000
+#define OMAP54XX_GPIO8_BASE            0x48053000
 
 #endif /* _GPIO_OMAP5_H */

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8ad9f66..9ecafb2 100644 (file)
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -43,7 +43,7 @@ SOBJS-y += relocate.o
 ifndef CONFIG_SYS_GENERIC_BOARD
 COBJS-y        += board.o
 endif
-COBJS-y += bss.o
+COBJS-y += sections.o
 
 COBJS-y        += bootm.o
 COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o

diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 4446da9..cd2bab6 100644 (file)
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -37,61 +37,48 @@
  */
 
 ENTRY(relocate_code)
-       mov     r6, r0  /* save addr of destination */
-
-       ldr     r0, =_start             /* r0 <- SRC &_start */
-       subs    r9, r6, r0              /* r9 <- relocation offset */
+       ldr     r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
+       subs    r9, r0, r1              /* r9 <- relocation offset */
        beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy loop */
-       adr     r7, relocate_code       /* r7 <- SRC &relocate_code */
-       ldr     r3, _image_copy_end_ofs /* r3 <- __image_copy_end local ofs */
-       add     r2, r7, r3              /* r2 <- SRC &__image_copy_end */
+       ldr     r2, =__image_copy_end   /* r2 <- SRC &__image_copy_end */
 
 copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
+       ldmia   r1!, {r10-r11}          /* copy from source address [r1]    */
+       stmia   r0!, {r10-r11}          /* copy to   target address [r0]    */
+       cmp     r1, r2                  /* until source end address [r2]    */
        blo     copy_loop
 
        /*
         * fix .rel.dyn relocations
         */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- __dynsym_start local ofs */
-       add     r10, r10, r7            /* r10 <- SRC &__dynsym_start */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- __rel_dyn_start local ofs */
-       add     r2, r2, r7              /* r2 <- SRC &__rel_dyn_start */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- __rel_dyn_end local ofs */
-       add     r3, r3, r7              /* r3 <- SRC &__rel_dyn_end */
+       ldr     r2, =__rel_dyn_start    /* r2 <- SRC &__rel_dyn_start */
+       ldr     r3, =__rel_dyn_end      /* r3 <- SRC &__rel_dyn_end */
 fixloop:
-       ldr     r0, [r2]                /* r0 <- SRC location to fix up */
-       add     r0, r0, r9              /* r0 <- DST location to fix up */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
+       ldmia   r2!, {r0-r1}            /* (r0,r1) <- (SRC location,fixup) */
+       and     r1, r1, #0xff
+       cmp     r1, #23                 /* relative fixup? */
+       bne     fixnext
+
        /* relative fix: increase location by offset */
+       add     r0, r0, r9
        ldr     r1, [r0]
        add     r1, r1, r9
-fixnext:
        str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
+fixnext:
        cmp     r2, r3
        blo     fixloop
 
 relocate_done:
 
+#ifdef __XSCALE__
+       /*
+        * On xscale, icache must be invalidated and write buffers drained,
+        * even with cache disabled - 4.2.7 of xscale core developer's manual
+        */
+       mcr     p15, 0, r0, c7, c7, 0   /* invalidate icache */
+       mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
+#endif
+
        /* ARMv4- don't know bx lr but the assembler fails to see that */
 
 #ifdef __ARM_ARCH_4__
@@ -100,13 +87,4 @@ relocate_done:
         bx        lr
 #endif
 
-_image_copy_end_ofs:
-       .word __image_copy_end - relocate_code
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - relocate_code
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - relocate_code
-_dynsym_start_ofs:
-       .word __dynsym_start - relocate_code
-
 ENDPROC(relocate_code)

diff --git a/arch/arm/lib/bss.c b/arch/arm/lib/sections.c
similarity index 79%
rename from arch/arm/lib/bss.c
rename to arch/arm/lib/sections.c
index 99eda59..5921dd8 100644 (file)
--- a/arch/arm/lib/bss.c
+++ b/arch/arm/lib/sections.c
@@ -35,5 +35,9 @@
  * aliasing warnings.
  */
 
-char __bss_start[0] __attribute__((used, section(".__bss_start")));
-char __bss_end[0] __attribute__((used, section(".__bss_end")));
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));

diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index ef4a25b..74aec5f 100644 (file)
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/actux1/libactux1.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }

diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 00ad8b7..c276501 100644 (file)
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/actux2/libactux2.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }

diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 44b990e..5610644 100644 (file)
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/actux3/libactux3.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }

diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index 1daa1b3..3972685 100644 (file)
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -54,11 +54,6 @@ SECTIONS
                __rel_dyn_end = .;
        } >.sram
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       } >.sram
-
        .bss :
        {
                . = ALIGN(4);

diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index b1b8701..6fa4509 100644 (file)
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -55,11 +55,6 @@ SECTIONS
                __rel_dyn_end = .;
        } >.sram
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       } >.sram
-
        .bss :
        {
                . = ALIGN(4);

diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index 596a9e0..b452f20 100644 (file)
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -61,7 +61,6 @@ SECTIONS
        __image_copy_end = .;
        __rel_dyn_start = .;
        __rel_dyn_end = .;
-       __dynsym_start = .;
 
        __got_start = .;
        . = ALIGN(4);

diff --git a/doc/README.m28 b/board/denx/m28evk/README
similarity index 75%
rename from doc/README.m28
rename to board/denx/m28evk/README
index 2a92226..cb3ae20 100644 (file)
--- a/doc/README.m28
+++ b/board/denx/m28evk/README
@@ -9,5 +9,5 @@ arch/arm/include/asm/arch-mxs/  - Header files for the Freescale i.MX28
 board/denx/m28evk/             - M28EVK board specific files
 include/configs/m28evk.h       - M28EVK configuration file
 
-Follow the instructions from doc/README.mx28_common to generate a bootable SD
-card or to boot from NAND flash.
+Follow the instructions from doc/README.mxs to generate a bootable SD card or to
+boot from NAND flash.

diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 6d4b187..f359112 100644 (file)
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/dvlhost/libdvlhost.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }

diff --git a/doc/README.mx28evk b/board/freescale/mx28evk/README
similarity index 93%
rename from doc/README.mx28evk
rename to board/freescale/mx28evk/README
index 76db474..524f3fc 100644 (file)
--- a/doc/README.mx28evk
+++ b/board/freescale/mx28evk/README
@@ -41,7 +41,6 @@ Note: The mx28evk board does not come with a NAND flash populated from the
 factory. It comes with an empty slot (U23), which allows the insertion of a
 48-pin TSOP flash device.
 
-Follow the instructions from doc/README.mx28_common to generate a bootable SD
-card.
+Follow the instructions from doc/README.mxs to generate a bootable SD card.
 
 Insert the SD card in slot 0, power up the board and U-boot will boot.

diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 4969960..963d29f 100644 (file)
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -34,6 +34,7 @@ SECTIONS
        . = ALIGN(4);
        .text      :
        {
+               *(.__image_copy_start)
          /* WARNING - the following is hand-optimized to fit within    */
          /* the sector layout of our flash chips!      XXX FIXME XXX   */
 
@@ -65,17 +66,23 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -100,6 +107,7 @@ SECTIONS
        }
 
        /DISCARD/ : { *(.bss*) }
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynsym*) }
        /DISCARD/ : { *(.dynamic*) }

diff --git a/board/freescale/mx6qsabresd/Makefile b/board/freescale/mx6sabresd/Makefile
similarity index 98%
rename from board/freescale/mx6qsabresd/Makefile
rename to board/freescale/mx6sabresd/Makefile
index 5693772..ff3c94b 100644 (file)
--- a/board/freescale/mx6qsabresd/Makefile
+++ b/board/freescale/mx6sabresd/Makefile
@@ -23,7 +23,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
-COBJS  := mx6qsabresd.o
+COBJS  := mx6sabresd.o
 
 SRCS   := $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))

diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
similarity index 98%
rename from board/freescale/mx6qsabresd/mx6qsabresd.c
rename to board/freescale/mx6sabresd/mx6sabresd.c
index 2529826..222ee98 100644 (file)
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -17,12 +17,10 @@
  * GNU General Public License for more details.
  */
 
-#include <common.h>
-#include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/mx6-pins.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -291,7 +289,6 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-       puts("Board: MX6Q-SabreSD\n");
-
+       puts("Board: MX6-SabreSD\n");
        return 0;
 }

diff --git a/board/palmtreo680/Makefile b/board/palmtreo680/Makefile
new file mode 100644 (file)
index 0000000..34ffb99
--- /dev/null
+++ b/board/palmtreo680/Makefile
@@ -0,0 +1,34 @@
+#
+# Palm Treo680 Support
+#
+# Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := palmtreo680.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+clean:
+       rm -f $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/palmtreo680/README b/board/palmtreo680/README
new file mode 100644 (file)
index 0000000..159f1f6
--- /dev/null
+++ b/board/palmtreo680/README
@@ -0,0 +1,581 @@
+
+README for the Palm Treo 680.
+
+Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+
+You may reproduce the contents of this file entirely or in part, but please
+credit me by name if you do.  Thanks.
+
+
+Intro
+=====
+
+Yes, you can program u-boot onto the flash of your Palm Treo 680 so that u-boot
+(then Linux, Android, ...) runs at power-up.  This document describes how, and
+gives some implementation details on this port of u-boot and describes how the
+Treo 680 boots from reset.
+
+But first, I probably don't need to tell you that after doing this, your phone
+will no longer run PalmOS.  You *may* be able to later restore your phone to its
+original state by creating a backup image of the flash before writing u-boot
+(details below), but this is not heavily tested and should not be relied upon.
+There is also the possibility that something may go wrong during the process of
+programming u-boot, leaving you with a bricked phone.  If you follow these
+instructions carefully this chance will be minimized, but I do not recommend
+that you program u-boot onto a phone that you can not afford to lose, and
+certainly not one that contains important data that is not backed up elsewhere.
+I AM NOT RESPONSIBLE FOR THE LOSS OF YOUR PHONE.  DO THIS AT YOUR OWN RISK.
+Having said that, feel free to send me a note cursing me out if something does
+go wrong, but please tell me what happened exactly.  For that matter, I'd love
+to hear from you if you succeed.
+
+
+
+Details on the SPL
+==================
+
+The docg4 features a 2k region at the start of its address space that interfaces
+to the system bus like a NOR flash.  This allows the docg4 to function as a boot
+ROM.  The Treo 680 uses this feature.  The contents of this 2k region are
+write-protected and can not be reprogrammed.  Fortunately, the code it contains
+does what we need to do, at least partially.  After some essential hardware
+initialization (like the SDRAM controller), it runs an IPL (initial program
+loader) that copies 128K (no more, no less) from flash to a fixed address in
+SDRAM (0xa1700000) and jumps to it.  128K is too small for u-boot, so we use it
+to load a u-boot secondary program loader (SPL).  But since our SPL only
+occupies a little over 1k, we can economize on flash usage by having the IPL
+load a portion of u-boot proper as well.  We let the IPL load the first 128k of
+a concatenated spl + u-boot image, and because the SPL is placed before u-boot
+proper, the IPL jumps to the SPL, which copies the portion of u-boot that the
+IPL has already loaded to its correct SDRAM address, and then loads the
+remainder of u-boot and jumps to it.
+
+
+
+The docg4's "reliable mode"
+===========================
+
+This is a special mode of operation of the docg4's integrated controller whereby
+consecutive pairs of 2k regions are used in parallel (in some fashion) to store
+2k of data.  In other words, the normal capacity is halved, but the data
+integrity is improved.  In this mode, the data is read or written from pages in
+even-numbered 2k regions (regions starting at 0x000, 0x1000, 0x2000, ...).  The
+odd-numbered 2k regions (regions starting at 0x800, 0x1800, 0x2800, ...) are
+transparently used in parallel.  In reliable mode, the odd-numbered 2k regions
+are not meant to be read or written directly.
+
+Reliable mode is used by the IPL because there is not enough space in its 2k
+footprint to implement the BCH ecc algorithm.  Data that is read while reliable
+mode is enabled must have been written in reliable mode, or the read fails.
+However, data written in reliable mode can also be read in normal mode (just not
+as reliably), but only from the even-numbered 2k regions; the odd-numbered 2k
+regions appear to contain junk, and will generate ecc errors.  When the IPL and
+SPL read from flash, the odd-numbered 2k regions are explicitly skipped.  The
+same is true for the flash_u-boot utility when it writes the u-boot image in
+reliable mode.
+
+The docg4 Linux driver supports writing in reliable mode (it is enabled by the
+module parameter), but not reading.  However, the u-boot docg4_spl driver does
+read in reliable mode, in the same fashion as the IPL.
+
+
+
+Details on the IPL and its data format
+======================================
+
+Starting from block 5 and counting upward, the IPL will search for and load the
+first two blocks it finds that contain a magic number in the oob of the first
+page of the block.  The contents are loaded to SDRAM starting at address
+0xa1700000.  After two blocks have been loaded, it jumps to 0xa1700000.  The
+number of blocks loaded and the load address in SDRAM are hard-coded; only the
+flash offset of the blocks can vary at run-time (based on the presence of the
+magic number).
+
+In addition to using the docg4's reliable mode, the IPL expects each 512 byte
+page to be written redundantly in the subsequent page.  The hardware is capable
+of detecting bit errors (but not correcting them), and if a bit error is
+detected when a page is read, the page contents are discarded and the subsequent
+page is read.
+
+Reliable mode reduces the capacity of a block by half, and the redundant pages
+reduce it by half again.  As a result, the normal 256k capacity of a block is
+reduced to 64k for the purposes of the IPL/SPL.
+
+For the sake of simplicity and uniformity, the u-boot SPL mimics the operation
+of the IPL, and expects the image to be stored in the same format.
+
+
+
+Instructions on Programming u-boot to flash
+===========================================
+
+To program u-boot to your flash, you will need to boot the Linux kernel on your
+phone using a PalmOS bootloader such as cocoboot.  The details of building and
+running Linux on your Treo (cross-compiling, creating a root filesystem,
+configuring the kernel, etc) are beyond the scope of this document.  The
+remainder of this document describes in detail how to program u-boot to the
+flash using Linux running on the Treo.
+
+
+
+Hardware Prerequisites
+======================
+
+A Palm Treo 680:
+  (dugh)
+
+A Palm usb cable:
+  You'll need this to establish a usbtty console connection to u-boot from a
+  desktop PC.  Currently there is no support in u-boot for the pxa27x keypad
+  (coming soon), so a serial link must be used for the console.
+  These cables are still widely available if you don't already have one.
+
+A Linux desktop PC.
+  You may be able to use Windows for the u-boot console if you have a usb driver
+  that is compatible with the Linux usbserial driver, but for programming u-boot
+  to flash, you'll really want to use a Linux PC.
+
+
+
+Treo-side Software Prerequisites
+================================
+
+Linux bootloader for PalmOS:
+
+  Cocoboot is the only one I'm aware of.  If you don't already have this, you
+  can download it from
+  https://download.enlightenment.org/misc/Illume/Treo-650/2008-11-13/sdcard-base.tar.gz
+  which is a compressed tar archive of the contents of an sd card containing
+  cocoboot.  Use mkdosfs to create a fat16 filesystem on the first primary
+  partition of the card, mount the partition, and extract the tar file to it.
+  You will probably need to edit the cocoboot.conf file to customize the
+  parameters passed to the kernel.
+
+
+
+Linux kernel:
+
+  The kernel on the Treo 680 is still a little rough around the edges, and the
+  official kernel frequently breaks on the Treo :(  A development kernel
+  specifically for the Treo 680 can be found on github:
+    http://github.com/mike-dunn/linux-treo680
+  The master branch of this tree has been tested on the Treo, and I recommend
+  using this kernel for programming u-boot.  As of this writing, there may be a
+  bug in the docg4 nand flash driver that sometimes causes block erasures to
+  fail.  This has been fixed in the above tree.
+
+  If you choose to use the official kernel, it must contain the docg4 driver that
+  includes the reliable_mode module parameter.  This was a later enhancement to
+  the driver, and was merged to the kernel as of v3.8.  Do not try to use an
+  earlier kernel that contains the docg4 driver without support for writing in
+  reliable mode.  If you try to program u-boot to flash with the docg4 driver
+  loaded without the reliable_mode parameter enabled, you *will* brick your
+  phone!
+
+  For the purpose of programming u-boot to flash, the following options must be
+  enabled in the Treo kernel's .config:
+
+     CONFIG_MTD=y
+     CONFIG_MTD_CMDLINE_PARTS=y
+     CONFIG_MTD_CHAR=y
+     CONFIG_MTD_NAND_DOCG4=m
+
+  Note that the docg4 nand driver is configured as a module, because we will
+  want to load and unload it with reliable_mode enabled or disabled as needed.
+
+  You will also need to specify mtd partitions on the kernel command line.  In
+  the instructions that follow, we will assume that the flash blocks to which
+  u-boot will be programmed are defined by the second partition on the device.
+  The u-boot config file (include/configs/palmtreo680.h) places the u-boot image
+  at the start of block 6 (offset 0x180000), which is the first writable
+  (non-protected) block on the flash (this is also where the PalmOS SPL starts).
+  The u-boot image occupies four blocks, so to create the u-boot partition, pass
+  this command line to the kernel:
+    mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part)
+  This will create three partitions:
+    protected_part: the first six blocks, which are read-only
+    bootloader_part: the next four blocks, for the u-boot image
+    filesys_part: the remainder of the device
+  The mtdchar kernel device driver will use device nodes /dev/mtd0, /dev/mtd1,
+  and /dev/mtd2 for these partitions, respectively.  Ensure that your root file
+  system at least has /dev/mtd1 if you are not running udev or mdev.
+
+
+Userspace Utilities:
+
+  In addition to everything necessary to provide a useful userspace environment
+  (busybox is indispensable, of course), you will need the mtd-utils package on
+  your root filesystem.  I use version 1.5.0 of mtd-utils, and I suggest you use
+  this version as well, or at leat a version very close to this one, as
+  mtd-utils has tended to be fluid.
+
+  Note that busybox includes a version of mtd-utils.  These are deficient and
+  should not be used.  When you run one of these utilities (nanddump, etc),
+  ensure you are invoking the separate executable from mtd-utils, and not the
+  one built into busybox.  I recommend that you configure busybox with its
+  mtd-utils disabled to avoid any possibility of confusion.
+
+  You will also need to cross-compile the userspace Linux utility in
+  tools/palmtreo680/flash_u-boot.c, which we will run on the Treo to perform the
+  actual write of the u-boot image to flash.  This utility links against libmtd
+  from the mtd-utils package.
+
+
+
+Desktop PC-side Software Prerequisites
+======================================
+
+Terminal emulator application:
+  minicom, kermit, etc.
+
+
+Linux kernel:
+  Compiled with CONFIG_USB_SERIAL enabled.  Build this as a module.
+
+
+
+Recommended (Not directly related to u-boot)
+============================================
+
+Working directly on the Treo's tiny screen and keypad is difficult and
+error-prone.  I recommend that you log into the Linux kernel running on your
+Treo from your desktop PC using ethernet over usb.  The desktop's kernel must be
+configured with CONFIG_USB_USBNET, CONFIG_USB_NET_CDCETHER, and
+CONFIG_USB_NET_CDC_SUBSET.  The Treo's kernel will need CONFIG_USB_ETH, and its
+init script will need to start an ssh daemon like dropbear.  Note that the usb0
+network interface will not appear on the desktop PC until the Treo kernel's usb
+ethernet gadget driver has initialized.  You must wait for this to occur (watch
+the PC's kernel log) before you can assign usb0 an ip address and log in to the
+Treo.  If you also build the Treo's kernel with CONFIG_IP_PNP enabled, you can
+pass its ip address on the kernel command line, and obviate the need to
+initialize the network interface in your init script.
+
+Having the Palm usb cable connected to the host has the added benefit of keeping
+power supplied to your Treo, reducing the drain on the battery.  If something
+goes wrong while you're programming u-boot to the flash, you will have lots of
+time to correct it before the battery dies.
+
+I have encountered a situation where the kernel is sometimes unable to mount a
+root filesystem on the mmc card due to the mmc controller not initializing in
+time, (and CONFIG_MMC_UNSAFE_RESUME doesn't seem to help) so I recommend that
+you build a minimal root filesystem into the kernel using the kernel's initramfs
+feature (CONFIG_BLK_DEV_INITRD).  If you want your root filesystem on the mmc
+card, your init script can mount and switch_root to the mmc card after a short
+sleep.  But keep in mind that in this case you won't be able to use an mmc card
+to transfer files between your desktop and the Treo once Linux is running.
+Another option for transfering files is to mount an nfs filesystem exported by
+the desktop PC.  For greatest convenience, you can export the root filesystem
+itself from your desktop PC and switch_root to it in your init script.  This
+will work if your initramfs init script contains a loop that waits for you to
+initialize the usb0 network interface on the desktop PC; e.g., loop while a ping
+to the desktop PC returns an error.  After the loop exits, do the nfs mount and
+call switch_root.  (You can not use the kernel nfsroot feature because the
+network will not be up when the kernel expects it to be; i.e., not until you
+configure the usb0 interface on the desktop.)  Use the nfs 'nolock' option when
+mounting to avoid the need to run a portmapper like rpcbind.
+
+
+
+Preliminaries
+=============
+
+Once Linux is running on your Treo, you may want to perform a few sanity checks
+before programming u-boot.  These checks will verify my assumptions regarding
+all the Treo 680s out there, and also ensure that the flash and mtd-utils are
+working correctly.  If you are impatient and reckless, you may skip this
+section, but see disclaimer at the top of this file!
+
+Load the docg4 driver:
+
+  $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
+
+We tell the driver to use the docg4's "reliable mode" when writing because this
+is the format required by the IPL, which runs from power-up and loads the first
+portion of u-boot.  We must ignore bad blocks because linux mtd uses out-of-band
+(oob) bytes to mark bad blocks, which will cause the blocks written by PalmOS to
+be misidentified as "bad" by libmtd.
+
+Check the kernel log to ensure that all's well:
+
+  $ dmesg | tail
+             <... snip ...>
+  docg4 docg4: NAND device: 128MiB Diskonchip G4 detected
+  3 cmdlinepart partitions found on MTD device Msys_Diskonchip_G4
+  Creating 3 MTD partitions on "Msys_Diskonchip_G4":
+  0x000000000000-0x000000180000 : "protected_part"
+  0x000000180000-0x000000280000 : "bootloader_part"
+  0x000000280000-0x000008000000 : "filesys_part"
+
+Ensure that the partition boundaries are as shown.  (If no partitions are shown,
+did you remember to pass them to the kernel on the command line?)  We will write
+u-boot to bootloader_part, which starts at offset 0x180000 (block 6) and spans 4
+256k blocks.  This partition is accessed through the device node /dev/mtd1.
+
+The docg4 contains a read-only table that identifies blocks that were marked as
+bad at the factory.  This table is in the page at offset 0x2000, which is within
+the partition protected_part (/dev/mtd0).  There is a slight chance that one or
+more of the four blocks that we will use for u-boot is listed in the table, so
+use nanddump to inspect the table to see if this is the case:
+
+  $ nanddump -p -l 512 -s 0x2000 -o /dev/mtd0
+  ECC failed: 0
+  ECC corrected: 0
+  Number of bad blocks: 0
+  Number of bbt blocks: 0
+  Block size 262144, page size 512, OOB size 16
+  Dumping data starting at 0x00002000 and ending at 0x00002200...
+  0x00002000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+             <... snip ...>
+
+The format of the table is simple: one bit per block, with block numbers
+increasing from left to right, starting with block 0 as the most significant bit
+of the first byte.  A bit will be clear if the corresponding block is bad.  We
+want to use blocks 6 throgh 9, so both of the two least significant bits of the
+first byte must be set, as must the two most significant bits of the second
+byte.  If this is not true in your case (you are very unlucky), you should use
+the first contiguous set of four good blocks after block 6, and adjust the
+partition boundaries accordingly.  You will also have to change the value of
+CONFIG_SYS_NAND_U_BOOT_OFFS in include/configs/palmtreo680.h and recompile
+u-boot.  Because the two blocks loaded by the IPL do not have to be contiguous,
+but our SPL expects them to be, you will need to erase any good blocks that are
+at an offset prior to CONFIG_SYS_NAND_U_BOOT_OFFS, so that the IPL does not find
+the magic number in oob and load it.  Once you have done all this, the
+instructions in this file still apply, except that the instructions below for
+restoring the original PalmOS block contents may need to be modified.
+
+Next, use nanddump to verify that the PalmOS SPL is where we expect it to be.
+The SPL can be identified by a magic number in the oob bytes of the first page
+of each of the two blocks containing the SPL image.  Pages are 512 bytes in
+size, so to dump the first page, plus the oob:
+
+  $ nanddump -p -l 512 -s 0 -o /dev/mtd1
+  ECC failed: 0
+  ECC corrected: 0
+  Number of bad blocks: 0
+  Number of bbt blocks: 0
+  Block size 262144, page size 512, OOB size 16
+  Dumping data starting at 0x00000000 and ending at 0x00000200...
+  0x00000000: 0a 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
+             <... snip ...>
+  0x000001f0: 13 4c 21 60 13 4d 2a 69 13 4b 29 69 89 1a 99 42
+    OOB Data: 42 49 50 4f 30 30 30 10 3a e2 00 92 be a0 11 ff
+
+Verify that the first seven bytes of oob data match those in the above line.
+(This is ASCII "BIPO000".)
+
+Do the same for the next block:
+  $ nanddump -p -l 512 -s 0x40000 -o /dev/mtd1
+
+The first seven oob bytes in last line should read:
+
+    OOB Data: 42 49 50 4f 30 30 31 81 db 8e 8f 46 07 9b 59 ff
+
+(This is ASCII "BIPO001".)
+
+For additional assurance, verify that the next block does *not* contain SPL
+data.
+
+  $ nanddump -p -l 512 -s 0x80000 -o /dev/mtd1
+
+It doesn't matter what the oob contains, as long as the first four bytes are
+*not* ASCII "BIPO".  PalmOS should only be using two blocks for the SPL
+(although we will need four for u-boot).
+
+If you want, you can back up the contents of bootloader_part to a file.  You may
+be able to restore it later, if desired (see "Restoring PalmOS" below).
+
+  $ nanddump -l 0x100000 -s 0 -o -f bootloader_part.orig /dev/mtd1
+
+nanddump will spew voluminous warnings about uncorrectable ecc errors.  This is
+a consequence of reading pages that were written in reliable mode, and is
+expected (these should all occur on pages in odd-numbered 2k regions; i.e.,
+0x800, 0xa00, 0xc00, 0xe00, 0x1800, 0x1a00, ...).  The size of the file
+bootloader_part.orig should be 1081344, which is 2048 pages, each of size 512
+plus 16 oob bytes.  If you are using initramfs for the root filesystem, don't
+forget to copy the file to permanent storage, such as an mmc card.
+
+If all of the above went well, you can now program u-boot.
+
+
+
+Programming u-boot
+==================
+
+Our u-boot includes a small SPL that must be prepended to u-boot proper.  From
+the base u-boot source directory on your desktop PC:
+
+  $ cat spl/u-boot-spl.bin u-boot.bin > u-boot-concat.bin
+
+cd to the tools/palmtreo680/ directory, and cross-compile flash_u-boot.c for the
+Treo:
+
+  $(CC) -o flash_u-boot $(CFLAGS) $(INCLUDEPATH) $(LIBPATH) flash_u-boot.c -lmtd
+
+Substitute variable values from your cross-compilation environment as
+appropriate.  Note that it links to libmtd from mtd-utils, and this must be
+included in $(LIBPATH) and $(INCLUDEPATH).
+
+Transfer u-boot-concat.bin and the compiled flash_u-boot utility to the Treo's
+root filesystem.  On the Treo, cd to the directory where these files were
+placed.
+
+Load the docg4 driver if you have not already done so.
+
+  $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
+
+Erase the blocks to which we will write u-boot:
+
+  $ flash_erase /dev/mtd1 0x00 4
+
+If no errors are reported, write u-boot to the flash:
+
+  $ ./flash_u-boot u-boot-concat.bin /dev/mtd1
+
+You can use nanddump (see above) to verify that the data was written.  This
+time, "BIPO" should be seen in the first four oob bytes of the first page of all
+four blocks in /dev/mtd1; i.e., at offsets 0x00000, 0x40000, 0x80000, 0xc0000.
+
+Shutdown linux, remove and re-insert the battery, hold your breath...
+
+
+
+Enjoying u-boot
+===============
+
+After you insert the battery, the u-boot splash screen should appear on the lcd
+after a few seconds.  With the usb cable connecting the Treo to your PC, in the
+kernel log of your PC you should see
+
+  <6>usb 3-1: New USB device found, idVendor=0525, idProduct=a4a6
+  <6>usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+  <6>usb 3-1: Product: U-Boot 2013.01-00167-gd62ef56-dirty
+  <6>usb 3-1: Manufacturer: Das U-Boot
+
+Load the usbserial module on your desktop PC:
+
+  $ modprobe usbserial vendor=0x0525 product=0xa4a6
+
+and run your favorite terminal emulation utility (minicom, kermit, etc) with the
+serial device set to /dev/ttyUSB0 (assuming this is your only usb serial
+device).  You should be at the u-boot console (type 'help').
+
+There is not much that is unique about using u-boot on the palm treo 680.
+Kernels can be loaded from mmc, flash, and from the desktop PC via kermit.  You
+can expand the size of the second partition on the flash to contain a kernel, or
+else put the kernel(s) in their own partition.
+
+Nand commands work as expected, with the excepton that blocks not written by the
+linux mtd subsystem may be misidentified by the u-boot docg4 driver as "bad" if
+they contain data in the oob bytes.  This will be the case for the blocks
+containing the u-boot image, for example.  To work around this, use 'nand scrub'
+instead of 'nand erase' to erase these blocks, and 'nand read.raw' to read them
+to memory.  (It would be useful if u-boot's nand commands provided a way to
+explicitly ignore "bad" blocks, because read.raw does not perform ecc.)  The
+'nand dump' command will read these "bad" blocks, however.
+
+Currently u-boot itself can only be programmed to flash from Linux; there is no
+support for reliable mode in u-boot's docg4 flash driver.  This should be
+corrected soon.
+
+
+
+Customizing
+===========
+
+If you change u-boot's configuration significantly (adding or removing
+features), you may have to adjust the value of CONFIG_SYS_NAND_U_BOOT_SIZE.
+This is the size of the concatenated spl + u-boot image, and tells the SPL how
+many flash blocks it needs to load.  It will be rounded up to the next 64k
+boundary (the spl flash block capacity), so it does not have to be exact, but
+you must ensure that it is not less than the actual image size.  If it is larger
+than the image, blocks may be needlessly loaded, but if too small, u-boot may
+only be partially loaded, resulting in a boot failure (bricked phone), so better
+to be too large.  The flash_u-boot utility will work with any size image and
+write the required number of blocks, provided that the partition is large
+enough.
+
+As the first writable block on the device, block 6 seems to make the most sense
+as the flash offset for writing u-boot (and this is where PalmOS places its
+SPL).  But you can place it elsewhere if you like.  If you do, you need to
+adjust CONFIG_SYS_NAND_U_BOOT_OFFS accordingly, and you must ensure that blocks
+preceeding the ones containing u-boot do *not* have the magic number in oob (the
+IPL looks for this).  In other words, make sure that any blocks that previously
+contained the u-boot image or PalmOS SPL are erased (and optionally written with
+something else) so that the IPL does not load it.  Also make sure that the new
+u-boot starting offset is at the start of a flash partition (check the kernel
+log after loading the docg4 driver), and pass the corresponding mtd device file
+to the flash_u-boot utility.
+
+The u-boot built-in default environment is used because a writable environment
+in flash did not seem worth the cost of a 256k flash block.  But adding this
+should be straightforward.
+
+
+
+Restoring PalmOS
+================
+
+If you backed up the contents of bootloader_part flash partition earlier, you
+should be able to restore it with the shell script shown below.  The first two
+blocks of data contain the PalmOS SPL and were written in reliable mode, whereas
+the next two blocks were written in normal mode, so the script has to load and
+unload the docg4 driver.  Make sure that the mtd-utils nandwrite and flash_erase
+are in your path (and are not those from busybox).  Also double-check that the
+backup image file bootloader_part.orig is exactly 1081344 bytes in length.  If
+not, it was not backed up correctly.  Run the script as:
+
+  ./restore_bootpart bootloader_part.orig /dev/mtd1
+
+The script will take a minute or so to run.  When it finishes, you may want to
+verify with nanddump that the data looks correct before you cycle power, because
+if the backup or restore failed, your phone will be bricked.  Note that as a
+consequence of reliable mode, the odd-numbered 2k regions in the first two
+blocks will not exactly match the contents of the backup file, (so unfortunately
+we can't simply dump the flash contents to a file and do a binary diff with the
+original back-up image to verify that it was restored correctly).  Also,
+nanddump will report uncorrectable ecc errors when it reads those regions.
+
+#!/bin/sh
+
+if [ $# -ne 2 ]; then
+    echo "usage: $0: <image file> <mtd device node>"
+    exit 1
+fi
+
+# reliable mode used for the first two blocks
+modprobe -r docg4
+modprobe docg4 ignore_badblocks=1 reliable_mode=1 || exit 1
+
+# erase all four blocks
+flash_erase $2 0 4
+
+# Program the first two blocks in reliable mode.
+# 2k (4 pages) is written at a time, skipping alternate 2k regions
+# Note that "2k" is 2112 bytes, including 64 oob bytes
+file_ofs=0
+flash_ofs=0
+page=0
+while [ $page -ne 1024 ]; do
+    dd if=$1 bs=2112 skip=$file_ofs count=1 | nandwrite -o -n -s $flash_ofs $2 - || exit 1
+    file_ofs=$((file_ofs+2))
+    flash_ofs=$((flash_ofs+0x1000))
+    page=$((page+8))
+done;
+
+# normal mode used for the next two blocks
+modprobe -r docg4
+modprobe docg4 ignore_badblocks=1 || exit 1
+dd if=$1 bs=1 skip=$file_ofs count=540672 | nandwrite -o -n -s 0x80000 $2 - || exit 1
+modprobe -r docg4
+
+
+TODO
+====
+
+  - Keypad support.
+  - Interactive boot menu using keypad and lcd.
+  - Add reliable mode support to the u-boot docg4 driver.
+  - U-boot command that will write a new image to the bootloader partition in
+    flash.
+  - Linux FTD support.
+

diff --git a/board/palmtreo680/palmtreo680.c b/board/palmtreo680/palmtreo680.c
new file mode 100644 (file)
index 0000000..f4f6e1f
--- /dev/null
+++ b/board/palmtreo680/palmtreo680.c
@@ -0,0 +1,148 @@
+/*
+ * Palm Treo 680 Support
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <nand.h>
+#include <malloc.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch-pxa/pxa.h>
+#include <asm/arch-pxa/regs-mmc.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <u-boot/crc.h>
+#include <linux/mtd/docg4.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct nand_chip docg4_nand_chip;
+
+int board_init(void)
+{
+       /* We have RAM, disable cache */
+       dcache_disable();
+       icache_disable();
+
+       gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+       gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100;
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       /* IPL initializes SDRAM (we're already running from it) */
+       gd->ram_size = PHYS_SDRAM_1_SIZE;
+       return 0;
+}
+
+#ifdef CONFIG_LCD
+void lcd_enable(void)
+{
+       /*
+        * Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd
+        * driver code.  We need it as an output gpio.
+        */
+       writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L);
+
+       /* power-up and enable the lcd */
+       writel(0x00400000, GPSR(86)); /* enable; drive high */
+       writel(0x00002000, GPSR(77)); /* power; drive high */
+       writel(0x02000000, GPCR(25)); /* enable_n; drive low */
+
+       /* turn on LCD backlight and configure PWM for reasonable brightness */
+       writel(0x00, PWM_CTRL0);
+       writel(0x1b1, PWM_PERVAL0);
+       writel(0xfd, PWM_PWDUTY0);
+       writel(0x00000040, GPSR(38)); /*  backlight power on */
+}
+#endif
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+       writel(1 << 10, GPSR(42)); /* power on */
+       return pxa_mmc_register(0);
+}
+#endif
+
+void board_nand_init(void)
+{
+       /* we have one 128M diskonchip G4  */
+
+       struct mtd_info *mtd = &nand_info[0];
+       struct nand_chip *nand = &docg4_nand_chip;
+       if (docg4_nand_init(mtd, nand, 0))
+               hang();
+}
+
+#ifdef CONFIG_SPL_BUILD
+void nand_boot(void)
+{
+       __attribute__((noreturn)) void (*uboot)(void);
+
+       extern const void *_start, *_end;   /* boundaries of spl in memory */
+
+       /* size of spl; ipl loads this, and then a portion of u-boot */
+       const size_t spl_image_size = ((size_t)&_end - (size_t)&_start);
+
+       /* the flash offset of the blocks that are loaded by the spl */
+       const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS +
+               DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE;
+
+       /* total number of bytes loaded by IPL */
+       const size_t ipl_load_size =
+               DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL;
+
+       /* number of bytes of u-boot proper that was loaded by the IPL */
+       const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size;
+
+       /* number of remaining bytes of u-boot that the SPL must load */
+       const size_t spl_load_size =
+               CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size;
+
+       /* memory address where we resume loading u-boot */
+       void *const load_addr =
+               (void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size);
+
+       /*
+        * Copy the portion of u-boot already read from flash by the IPL to its
+        * correct load address.
+        */
+       memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size);
+
+       /*
+        * Resume loading u-boot where the IPL left off.
+        */
+       nand_spl_load_image(spl_load_offset, spl_load_size, load_addr);
+
+#ifdef CONFIG_NAND_ENV_DST
+       nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                           (void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+       nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+                           (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+       /*
+        * Jump to U-Boot image
+        */
+       uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+       (*uboot)();
+}
+
+void board_init_f(ulong bootflag)
+{
+       nand_boot();
+}
+
+#endif  /* CONFIG_SPL_BUILD */

diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 61d1154..1a3ef92 100644 (file)
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -67,11 +67,6 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       }
-
        . = ALIGN(0x800);
 
        _end = .;
@@ -84,6 +79,7 @@ SECTIONS
        }
 
        /DISCARD/ : { *(.bss*) }
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynsym*) }
        /DISCARD/ : { *(.dynamic*) }

diff --git a/board/wandboard/README b/board/wandboard/README
index ce83bbe..498db2f 100644 (file)
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -22,6 +22,11 @@ To build U-Boot for the Wandboard Solo version:
 $ make wandboard_solo_config
 $ make
 
+To build U-Boot for the Wandboard Quad version:
+
+$ make wandboard_quad_config
+$ make
+
 Flashing U-boot into the SD card
 --------------------------------
 

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 5666cbf..43c02ac 100644 (file)
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -48,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-       gd->ram_size = CONFIG_DDR_MB * SZ_1M;
+       gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
 
        return 0;
 }

diff --git a/boards.cfg b/boards.cfg
index 1e598cb..1458289 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -267,9 +267,10 @@ ima3-mx53                    arm         armv7       ima3-mx53           esg
 vision2                      arm         armv7       vision2             ttcontrol      mx5            vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 cgtqmx6qeval                            arm             armv7           cgtqmx6eval             congatec               mx6             cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6            mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
-mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6            mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
+mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6            mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6            mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
-mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6            mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6dlsabresd                 arm         armv7       mx6sabresd          freescale      mx6            mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
+mx6qsabresd                  arm         armv7       mx6sabresd          freescale      mx6            mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
 mx6slevk                     arm         armv7       mx6slevk            freescale      mx6            mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
 titanium                     arm         armv7       titanium            freescale      mx6            titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
 vf610twr                     arm         armv7       vf610twr            freescale      vf610          vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg
@@ -281,6 +282,7 @@ nitrogen6q2g                 arm         armv7       nitrogen6x          boundar
 nitrogen6s                   arm         armv7       nitrogen6x          boundary       mx6            nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
 nitrogen6s1g                 arm         armv7       nitrogen6x          boundary       mx6            nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024
 wandboard_dl                arm         armv7       wandboard           -              mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
+wandboard_quad              arm         armv7       wandboard           -              mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048
 wandboard_solo              arm         armv7       wandboard           -              mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
@@ -352,6 +354,7 @@ lp8x4x                       arm         pxa         lp8x4x              icpdas
 lubbock                      arm         pxa
 palmld                       arm         pxa
 palmtc                       arm         pxa
+palmtreo680                  arm         pxa
 polaris                      arm         pxa         trizepsiv           -              -           trizepsiv:POLARIS
 pxa255_idp                   arm         pxa
 trizepsiv                    arm         pxa

diff --git a/doc/README.mx28_common b/doc/README.mx28_common
index 8bacaf8..5d9e72f 100644 (file)
--- a/doc/README.mx28_common
+++ b/doc/README.mx28_common
@@ -1,12 +1,15 @@
-Booting U-boot on a MX28 processor
-==================================
+Booting U-boot on a MXS processor
+=================================
 
-This document describes the MX28 U-Boot port. This document mostly
-covers topics related to making the module/board bootable.
+This document describes the MXS U-Boot port. This document mostly covers topics
+related to making the module/board bootable.
 
 Terminology
 -----------
 
+The term "MXS" refers to a family of Freescale SoCs that is composed by MX23
+and MX28.
+
 The dollar symbol ($) introduces a snipped of shell code. This shall be typed
 into the unix command prompt in U-Boot source code root directory.
 
@@ -17,16 +20,16 @@ Contents
 --------
 
 1) Prerequisites
-2) Compiling U-Boot for a MX28 based board
-3) Installation of U-Boot for a MX28 based board to SD card
-4) Installation of U-Boot into NAND flash
+2) Compiling U-Boot for a MXS based board
+3) Installation of U-Boot for a MXS based board to SD card
+4) Installation of U-Boot into NAND flash on a MX28 based board
 
 1) Prerequisites
 ----------------
 
-To make a MX28 based board bootable, some tools are necessary. The first one
-is the "elftosb" tool distributed by Freescale Semiconductor. The other one
-is the "mxsboot" tool found in U-Boot source tree.
+To make a MXS based board bootable, some tools are necessary. The first one is
+the "elftosb" tool distributed by Freescale Semiconductor. The other one is the
+"mxsboot" tool found in U-Boot source tree.
 
 Firstly, obtain the elftosb archive from the following location:
 
@@ -60,18 +63,18 @@ copy the binary by hand:
 Make sure the "elftosb" binary can be found in your $PATH, in this case this
 means "/usr/local/bin/" has to be in your $PATH.
 
-2) Compiling U-Boot for a MX28 based board
+2) Compiling U-Boot for a MXS based board
 -------------------------------------------
 
-Compiling the U-Boot for a MX28 board is straightforward and done as compiling U-Boot
-for any other ARM device. For cross-compiler setup, please refer to ELDK5.0
-documentation. First, clean up the source code:
+Compiling the U-Boot for a MXS board is straightforward and done as compiling
+U-Boot for any other ARM device. For cross-compiler setup, please refer to
+ELDK5.0 documentation. First, clean up the source code:
 
        $ make mrproper
 
-Next, configure U-Boot for a MX28 based board
+Next, configure U-Boot for a MXS based board
 
-       $ make <mx28_based_board_name>_config
+       $ make <mxs_based_board_name>_config
 
 Examples:
 
@@ -83,8 +86,16 @@ Examples:
 
        $ make mx28evk_config
 
+3. For building U-boot for Freescale MX23EVK board:
+
+       $ make mx23evk_config
+
+4. For building U-boot for Olimex MX23 Olinuxino board:
+
+       $ make mx23_olinuxino_config
+
 Lastly, compile U-Boot and prepare a "BootStream". The "BootStream" is a special
-type of file, which the i.MX28 CPU can boot. This is handled by the following
+type of file, which MXS CPUs can boot. This is handled by the following
 command:
 
        $ make u-boot.sb
@@ -96,18 +107,16 @@ The code produces "u-boot.sb" file. This file needs to be augmented with a
 proper header to allow successful boot from SD or NAND. Adding the header is
 discussed in the following chapters.
 
-3) Installation of U-Boot for a MX28 based board to SD card
------------------------------------------------------------
-
-To boot a MX28 based board from SD, set the boot mode DIP switches according
-to i.MX28 manual chapter 12.2.1 (Table 12-2), PORT=SSP0, SD/MMC master on
-SSP0, 3.3V.
+3) Installation of U-Boot for a MXS based board to SD card
+----------------------------------------------------------
 
+To boot a MXS based board from SD, set the boot mode DIP switches according to
+to MX28 manual, section 12.2.1 (Table 12-2) or MX23 manual, section 35.1.2
+(Table 35-3).
 
-An SD card the i.MX28 CPU can use to boot U-Boot must contain a DOS partition
-table, which in turn carries a partition of special type and which contains a
-special header. The rest of partitions in the DOS partition table can be used
-by the user.
+The SD card used to boot U-Boot must contain a DOS partition table, which in
+turn carries a partition of special type and which contains a special header.
+The rest of partitions in the DOS partition table can be used by the user.
 
 To prepare such partition, use your favourite partitioning tool. The partition
 must have the following parameters:
@@ -141,17 +150,17 @@ case, we assume the first partition of the SD card is /dev/mmcblk0p1:
 
        $ dd if=u-boot.sd of=/dev/mmcblk0p1
 
-Last step is to insert the card into MX28 based board and boot.
+Last step is to insert the card into the MXS based board and boot.
 
 NOTE: If the user needs to adjust the start sector, the "mxsboot" tool contains
       a "-p" switch for that purpose. The "-p" switch takes the sector number as
       an argument.
 
-4) Installation of U-Boot into NAND flash
------------------------------------------
+4) Installation of U-Boot into NAND flash on a MX28 based board
+---------------------------------------------------------------
 
-To boot a MX28 based board from NAND, set the boot mode DIP switches according to i.MX28
-manual chapter 12.2.1 (Table 12-2), PORT=GPMI, NAND 1.8 V.
+To boot a MX28 based board from NAND, set the boot mode DIP switches according
+to MX28 manual section 12.2.1 (Table 12-2), PORT=GPMI, NAND 1.8 V.
 
 There are two possibilities when preparing an image writable to NAND flash.
 
@@ -214,7 +223,7 @@ There are two possibilities when preparing an image writable to NAND flash.
        --------------------------------------------
           There is a slight possibility of the user wanting to adjust the
           STRIDE and COUNT options of the NAND boot. For description of these,
-          see i.MX28 manual section 12.12.1.2 and 12.12.1.3.
+          see MX28 manual section 12.12.1.2 and 12.12.1.3.
 
           The update scripts take this possibility into account. In case the
           user changes STRIDE by blowing fuses, the user also has to change

diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index c9b71f7..98f2c52 100644 (file)
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -447,10 +447,13 @@ static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
        if (buf && buf_len)
                sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
        opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
-       if (is_write)
+       if (is_write) {
                opts |= 0x40;
+               flush_cache((ulong)buf, buf_len);
+       }
        ahci_fill_cmd_slot(pp, cmd_slot, opts);
 
+       flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
        writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
 
        if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
@@ -458,8 +461,12 @@ static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
                printf("timeout exit!\n");
                return -1;
        }
+       invalidate_dcache_range((int)(pp->cmd_slot),
+                               (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
        debug("ahci_exec_ata_cmd: %d byte transferred.\n",
              pp->cmd_slot->status);
+       if (!is_write)
+               invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
 
        return buf_len;
 }
@@ -468,7 +475,8 @@ static void ahci_set_feature(u8 dev, u8 port)
 {
        struct ahci_probe_ent *probe_ent =
                (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_fis_h2d h2d, *cfis = &h2d;
+       struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+       struct sata_fis_h2d *cfis = &h2d;
 
        memset(cfis, 0, sizeof(struct sata_fis_h2d));
        cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
@@ -615,7 +623,8 @@ static void dwc_ahsata_identify(int dev, u16 *id)
 {
        struct ahci_probe_ent *probe_ent =
                (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_fis_h2d h2d, *cfis = &h2d;
+       struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+       struct sata_fis_h2d *cfis = &h2d;
        u8 port = probe_ent->hard_port_no;
 
        memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -645,7 +654,8 @@ static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
 {
        struct ahci_probe_ent *probe_ent =
                (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_fis_h2d h2d, *cfis = &h2d;
+       struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+       struct sata_fis_h2d *cfis = &h2d;
        u8 port = probe_ent->hard_port_no;
        u32 block;
 
@@ -675,7 +685,8 @@ void dwc_ahsata_flush_cache(int dev)
 {
        struct ahci_probe_ent *probe_ent =
                (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_fis_h2d h2d, *cfis = &h2d;
+       struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+       struct sata_fis_h2d *cfis = &h2d;
        u8 port = probe_ent->hard_port_no;
 
        memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -692,7 +703,8 @@ static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
 {
        struct ahci_probe_ent *probe_ent =
                (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_fis_h2d h2d, *cfis = &h2d;
+       struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+       struct sata_fis_h2d *cfis = &h2d;
        u8 port = probe_ent->hard_port_no;
        u64 block;
 
@@ -728,7 +740,8 @@ u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
 {
        struct ahci_probe_ent *probe_ent =
                (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_fis_h2d h2d, *cfis = &h2d;
+       struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+       struct sata_fis_h2d *cfis = &h2d;
        u8 port = probe_ent->hard_port_no;
        u64 block;
 
@@ -769,7 +782,8 @@ void dwc_ahsata_flush_cache_ext(int dev)
 {
        struct ahci_probe_ent *probe_ent =
                (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_fis_h2d h2d, *cfis = &h2d;
+       struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+       struct sata_fis_h2d *cfis = &h2d;
        u8 port = probe_ent->hard_port_no;
 
        memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -912,7 +926,9 @@ int scan_sata(int dev)
        u8 port = probe_ent->hard_port_no;
        block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
 
-       id = (u16 *)malloc(ATA_ID_WORDS * 2);
+       id = (u16 *)memalign(ARCH_DMA_MINALIGN,
+                               roundup(ARCH_DMA_MINALIGN,
+                                       (ATA_ID_WORDS * 2)));
        if (!id) {
                printf("id malloc failed\n\r");
                return -1;

diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index a30d7f0..f16e9ae 100644 (file)
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -55,7 +55,7 @@ static inline int get_gpio_index(int gpio)
 
 int gpio_is_valid(int gpio)
 {
-       return (gpio >= 0) && (gpio < 192);
+       return (gpio >= 0) && (gpio < OMAP_MAX_GPIO);
 }
 
 static int check_gpio(int gpio)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 5bed858..0eca776 100644 (file)
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -128,8 +128,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
                unsigned int max_hz, unsigned int mode)
 {
        u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
-       s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
-       u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+       s32 reg_ctrl, reg_config;
+       u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
        struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 
        if (max_hz == 0) {
@@ -147,26 +147,20 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
        reg_ctrl |=  MXC_CSPICTRL_EN;
        reg_write(&regs->ctrl, reg_ctrl);
 
-       /*
-        * The following computation is taken directly from Freescale's code.
-        */
        if (clk_src > max_hz) {
-               pre_div = DIV_ROUND_UP(clk_src, max_hz);
-               if (pre_div > 16) {
-                       post_div = pre_div / 16;
-                       pre_div = 15;
-               }
-               if (post_div != 0) {
-                       for (i = 0; i < 16; i++) {
-                               if ((1 << i) >= post_div)
-                                       break;
-                       }
-                       if (i == 16) {
+               pre_div = (clk_src - 1) / max_hz;
+               /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
+               post_div = fls(pre_div);
+               if (post_div > 4) {
+                       post_div -= 4;
+                       if (post_div >= 16) {
                                printf("Error: no divider for the freq: %d\n",
                                        max_hz);
                                return -1;
                        }
-                       post_div = i;
+                       pre_div >>= post_div;
+               } else {
+                       post_div = 0;
                }
        }
 

diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c
index 3c1ea1a..4db7fa4 100644 (file)
--- a/drivers/usb/ulpi/omap-ulpi-viewport.c
+++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
@@ -22,18 +22,19 @@
 #include <asm/io.h>
 #include <usb/ulpi.h>
 
-#define OMAP_ULPI_WR_OPSEL     (3 << 21)
-#define OMAP_ULPI_ACCESS       (1 << 31)
+#define OMAP_ULPI_WR_OPSEL     (2 << 22)
+#define OMAP_ULPI_RD_OPSEL     (3 << 22)
+#define OMAP_ULPI_START                (1 << 31)
 
 /*
- * Wait for the ULPI Access to complete
+ * Wait for having ulpi in done state
  */
 static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 mask)
 {
        int timeout = CONFIG_USB_ULPI_TIMEOUT;
 
        while (--timeout) {
-               if ((readl(ulpi_vp->viewport_addr) & mask))
+               if (!(readl(ulpi_vp->viewport_addr) & mask))
                        return 0;
 
                udelay(1);
@@ -43,40 +44,15 @@ static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 mask)
 }
 
 /*
- * Wake the ULPI PHY up for communication
- *
- * returns 0 on success.
- */
-static int ulpi_wakeup(struct ulpi_viewport *ulpi_vp)
-{
-       int err;
-
-       if (readl(ulpi_vp->viewport_addr) & OMAP_ULPI_ACCESS)
-               return 0; /* already awake */
-
-       writel(OMAP_ULPI_ACCESS, ulpi_vp->viewport_addr);
-
-       err = ulpi_wait(ulpi_vp, OMAP_ULPI_ACCESS);
-       if (err)
-               debug("ULPI wakeup timed out\n");
-
-       return err;
-}
-
-/*
  * Issue a ULPI read/write request
  */
 static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 value)
 {
        int err;
 
-       err = ulpi_wakeup(ulpi_vp);
-       if (err)
-               return err;
-
        writel(value, ulpi_vp->viewport_addr);
 
-       err = ulpi_wait(ulpi_vp, OMAP_ULPI_ACCESS);
+       err = ulpi_wait(ulpi_vp, OMAP_ULPI_START);
        if (err)
                debug("ULPI request timed out\n");
 
@@ -85,7 +61,7 @@ static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 value)
 
 int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
 {
-       u32 val = ((ulpi_vp->port_num & 0xf) << 24) |
+       u32 val = OMAP_ULPI_START | (((ulpi_vp->port_num + 1) & 0xf) << 24) |
                        OMAP_ULPI_WR_OPSEL | ((u32)reg << 16) | (value & 0xff);
 
        return ulpi_request(ulpi_vp, val);
@@ -94,8 +70,8 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
 u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg)
 {
        int err;
-       u32 val = ((ulpi_vp->port_num & 0xf) << 24) |
-                        OMAP_ULPI_WR_OPSEL | ((u32)reg << 16);
+       u32 val = OMAP_ULPI_START | (((ulpi_vp->port_num + 1) & 0xf) << 24) |
+                        OMAP_ULPI_RD_OPSEL | ((u32)reg << 16);
 
        err = ulpi_request(ulpi_vp, val);
        if (err)

diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index b189419..b0f7ef8 100644 (file)
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -137,7 +137,7 @@ void *video_hw_init(void)
        /* Suck display configuration from "videomode" variable */
        penv = getenv("videomode");
        if (!penv) {
-               printf("MXSFB: 'videomode' variable not set!");
+               puts("MXSFB: 'videomode' variable not set!\n");
                return NULL;
        }
 

diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 4b39844..3e32eee 100644 (file)
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -90,9 +90,6 @@ extern void _start(void);
 extern ulong _rel_dyn_start_ofs;
 extern ulong _rel_dyn_end_ofs;
 
-/* Start/end of the relocation symbol table, as an offset from _start */
-extern ulong _dynsym_start_ofs;
-
 /* End of the region to be relocated, as an offset form _start */
 extern ulong _image_copy_end_ofs;
 

diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 76f7812..a396acf 100644 (file)
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -30,7 +30,7 @@
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
 
-#include "mx6qsabre_common.h"
+#include "mx6sabre_common.h"
 
 #define CONFIG_SYS_FSL_USDHC_NUM       2
 #if defined(CONFIG_ENV_IS_IN_MMC)

diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6sabre_common.h
similarity index 99%
rename from include/configs/mx6qsabre_common.h
rename to include/configs/mx6sabre_common.h
index bfaa420..53cc559 100644 (file)
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -18,7 +18,6 @@
 #define __MX6QSABRE_COMMON_CONFIG_H
 
 #define CONFIG_MX6
-#define CONFIG_MX6Q
 
 #include "mx6_common.h"
 

diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6sabresd.h
similarity index 97%
rename from include/configs/mx6qsabresd.h
rename to include/configs/mx6sabresd.h
index 44f07cb..76675f4 100644 (file)
--- a/include/configs/mx6qsabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -24,7 +24,7 @@
 #define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabresd.dtb"
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 
-#include "mx6qsabre_common.h"
+#include "mx6sabre_common.h"
 
 #define CONFIG_SYS_FSL_USDHC_NUM       3
 #if defined(CONFIG_ENV_IS_IN_MMC)

diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index aea91bc..74df66c 100644 (file)
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -276,8 +276,6 @@
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
-#define CONFIG_SYS_DCACHE_OFF
-
 #ifndef CONFIG_SYS_DCACHE_OFF
 #define CONFIG_CMD_CACHE
 #endif
@@ -287,4 +285,8 @@
 #define CONFIG_CMD_TIME
 #define CONFIG_SYS_ALT_MEMTEST
 
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_CMD_FS_GENERIC
+
 #endif        /* __CONFIG_H */

diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h
new file mode 100644 (file)
index 0000000..2ab6fd2
--- /dev/null
+++ b/include/configs/palmtreo680.h
@@ -0,0 +1,286 @@
+/*
+ * Palm Treo 680 configuration file
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#ifndef        __CONFIG_H
+#define        __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_CPU_PXA27X
+#define CONFIG_PALMTREO680
+#define CONFIG_MACH_TYPE                MACH_TYPE_TREO680
+
+#define CONFIG_SYS_MALLOC_LEN           (4096*1024)
+
+#define CONFIG_LZMA
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART                   1
+#define CONFIG_BAUDRATE                 9600
+#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX               3
+
+/* we have nand (although technically nand *is* flash...) */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_LCD
+/* #define CONFIG_KEYBOARD */  /* TODO */
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+#undef  CONFIG_CMD_FPGA
+#undef  CONFIG_CMD_LOADS
+#undef  CONFIG_CMD_NET
+#undef  CONFIG_CMD_NFS
+#undef  CONFIG_CMD_IMLS
+#undef  CONFIG_CMD_FLASH
+#undef  CONFIG_CMD_SETGETDCR
+#undef  CONFIG_CMD_SOURCE
+#undef  CONFIG_CMD_XIMG
+
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_PXA_LCD
+#define CONFIG_ACX544AKN
+#define CONFIG_LCD_LOGO
+#define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_FB_ADDR 0x5c000000    /* internal SRAM */
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN         /* requires "splashimage" env var */
+#define CONFIG_SPLASH_SCREEN_ALIGN   /* requires "splashpos" env var */
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
+
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER          1
+#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT               "$ "
+#else
+#define CONFIG_SYS_PROMPT               "=> "
+#endif
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_PBSIZE               \
+       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV       1
+
+/*
+ * Clock Configuration
+ */
+#undef  CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ                   1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
+#define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
+
+#define CONFIG_SYS_DRAM_BASE            0xa0000000
+#define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL  0x0E000000
+#define CONFIG_SYS_GAFR0_U_VAL  0xA500001A
+#define CONFIG_SYS_GAFR1_L_VAL  0x60000002
+#define CONFIG_SYS_GAFR1_U_VAL  0xAAA07959
+#define CONFIG_SYS_GAFR2_L_VAL  0x02AAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL  0x41440F08
+#define CONFIG_SYS_GAFR3_L_VAL  0x56AA95FF
+#define CONFIG_SYS_GAFR3_U_VAL  0x00001401
+#define CONFIG_SYS_GPCR0_VAL    0x1FF80400
+#define CONFIG_SYS_GPCR1_VAL    0x03003FC1
+#define CONFIG_SYS_GPCR2_VAL    0x01C1E000
+#define CONFIG_SYS_GPCR3_VAL    0x01C1E000
+#define CONFIG_SYS_GPDR0_VAL    0xCFF90400
+#define CONFIG_SYS_GPDR1_VAL    0xFB22BFC1
+#define CONFIG_SYS_GPDR2_VAL    0x93CDFFDF
+#define CONFIG_SYS_GPDR3_VAL    0x0069FF81
+#define CONFIG_SYS_GPSR0_VAL    0x02000018
+#define CONFIG_SYS_GPSR1_VAL    0x00000000
+#define CONFIG_SYS_GPSR2_VAL    0x000C0000
+#define CONFIG_SYS_GPSR3_VAL    0x00080000
+
+#define CONFIG_SYS_PSSR_VAL     0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN         0x01ffffff
+#define CONFIG_SYS_CCCR         0x02000210
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL     0x7ff844c8
+#define CONFIG_SYS_MSC1_VAL     0x7ff86ab4
+#define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
+#define CONFIG_SYS_MDCNFG_VAL   0x0B880acd
+#define CONFIG_SYS_MDREFR_VAL   0x201fa031
+#define CONFIG_SYS_MDMRS_VAL    0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL  0x00000000
+#define CONFIG_SYS_SXCNFG_VAL   0x40044004
+#define CONFIG_SYS_MECR_VAL     0x00000003
+#define CONFIG_SYS_MCMEM0_VAL   0x0001c391
+#define CONFIG_SYS_MCMEM1_VAL   0x0001c391
+#define CONFIG_SYS_MCATT0_VAL   0x0001c391
+#define CONFIG_SYS_MCATT1_VAL   0x0001c391
+#define CONFIG_SYS_MCIO0_VAL    0x00014611
+#define CONFIG_SYS_MCIO1_VAL    0x0001c391
+
+/*
+ * USB
+ */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_USB_DEV_PULLUP_GPIO 114
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE    0xa1700000 /* IPL loads SPL here */
+#define CONFIG_SPL_STACK        0x5c040000 /* end of internal SRAM */
+#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
+#define CONFIG_SPL_NAND_DOCG4   /* use lean docg4 nand spl driver */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT  /* spl uses memcpy */
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_DOCG4
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
+#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x200
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
+#define CONFIG_BITREVERSE       /* needed by docg4 driver */
+#define CONFIG_BCH              /* needed by docg4 driver */
+
+/*
+ * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image.  It
+ * will be rounded up to the next 64k boundary (the spl flash block size), so it
+ * does not have to be exact, but you must ensure that it is not less than the
+ * actual image size, or it may fail to boot (bricked phone)!
+ * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
+*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
+
+/*
+ * This is the byte offset into the flash at which the concatenated spl + u-boot
+ * image is placed.  It must be at the start of a block (256k boundary).  Blocks
+ * 0 - 5 are write-protected, so we start at block 6.
+ */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000  /* block 6 */
+
+/* DRAM address to which u-boot proper is loaded (before it relocates itself) */
+#define CONFIG_SYS_NAND_U_BOOT_DST  0xa0000000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+/* passed to linker by Makefile as arg to -Ttext option */
+#define CONFIG_SYS_TEXT_BASE 0xa0000000
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x5c040000 /* end of internal SRAM */
+
+/*
+ * environment
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_BUILD_ENVCRC
+#define CONFIG_ENV_SIZE 0x200
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+       "stdin=usbtty\0"           \
+       "stdout=usbtty\0"          \
+       "stderr=usbtty"
+#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
+ip=192.168.11.102:::255.255.255.0:treo:usb0"
+#define CONFIG_BOOTDELAY   3
+
+#if 0 /* example: try 2nd mmc partition, then nand */
+#define CONFIG_BOOTCOMMAND                                              \
+       "mmc rescan; "                                                  \
+       "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then "       \
+           "bootm 0xa1000000; "                                        \
+       "elif nand read 0xa1000000 0x280000 0x240000; then "            \
+           "bootm 0xa1000000; "                                        \
+       "fi; "
+#endif
+
+/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
+#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#endif  /* __CONFIG_H */

diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 77fe893..5012fc8 100644 (file)
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -83,13 +83,101 @@
 
 #define CONFIG_BOOTDELAY               3
 
+#define CONFIG_LOADADDR                        0x82000000
 #define CONFIG_SYS_TEXT_BASE           0x3f008000
 
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "script=boot.scr\0" \
+       "uimage=uImage\0" \
+       "console=ttyLP1\0" \
+       "fdt_high=0xffffffff\0" \
+       "initrd_high=0xffffffff\0" \
+       "fdt_file=vf610-twr.dtb\0" \
+       "fdt_addr=0x81000000\0" \
+       "boot_fdt=try\0" \
+       "ip_dyn=yes\0" \
+       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+       "mmcpart=1\0" \
+       "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+       "update_sd_firmware_filename=u-boot.imx\0" \
+       "update_sd_firmware=" \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "if mmc dev ${mmcdev}; then "   \
+                       "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+                               "setexpr fw_sz ${filesize} / 0x200; " \
+                               "setexpr fw_sz ${fw_sz} + 1; "  \
+                               "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+                       "fi; "  \
+               "fi\0" \
+       "mmcargs=setenv bootargs console=${console},${baudrate} " \
+               "root=${mmcroot}\0" \
+       "loadbootscript=" \
+               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if run loadfdt; then " \
+                               "bootm ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootm; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootm; " \
+               "fi;\0" \
+       "netargs=setenv bootargs console=${console},${baudrate} " \
+               "root=/dev/nfs " \
+       "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+               "netboot=echo Booting from net ...; " \
+               "run netargs; " \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "${get_cmd} ${uimage}; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+                               "bootm ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootm; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootm; " \
+               "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+          "mmc dev ${mmcdev}; if mmc rescan; then " \
+                  "if run loadbootscript; then " \
+                          "run bootscript; " \
+                  "else " \
+                          "if run loaduimage; then " \
+                                  "run mmcboot; " \
+                          "else run netboot; " \
+                          "fi; " \
+                  "fi; " \
+          "else run netboot; fi"
+
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP            /* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
-#define CONFIG_SYS_PROMPT              "Vybrid U-Boot > "
+#define CONFIG_SYS_PROMPT              "=> "
 #undef CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE              \
@@ -101,8 +189,7 @@
 #define CONFIG_SYS_MEMTEST_START       0x80010000
 #define CONFIG_SYS_MEMTEST_END         0x87C00000
 
-#define CONFIG_SYS_LOAD_ADDR           0x80010000
-
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 #define CONFIG_SYS_HZ                  1000
 
 /*

diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 5593f1c..b2995d8 100644 (file)
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -103,6 +103,8 @@
 
 #if defined(CONFIG_MX6DL)
 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-wandboard.dtb"
+#elif defined(CONFIG_MX6Q)
+#define CONFIG_DEFAULT_FDT_FILE                "imx6q-wandboard.dtb"
 #elif defined(CONFIG_MX6S)
 #define CONFIG_DEFAULT_FDT_FILE                "imx6s-wandboard.dtb"
 #endif

diff --git a/tools/palmtreo680/flash_u-boot.c b/tools/palmtreo680/flash_u-boot.c
new file mode 100644 (file)
index 0000000..3d8296f
--- /dev/null
+++ b/tools/palmtreo680/flash_u-boot.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ *
+ * This is a userspace Linux utility that, when run on the Treo 680, will
+ * program u-boot to flash.  The docg4 driver *must* be loaded with the
+ * reliable_mode and ignore_badblocks parameters enabled:
+ *
+ *        modprobe docg4 ignore_badblocks=1 reliable_mode=1
+ *
+ * This utility writes the concatenated spl + u-boot image to the start of the
+ * mtd device in the format expected by the IPL/SPL.  The image file and mtd
+ * device node are passed to the utility as arguments.  The blocks must have
+ * been erased beforehand.
+ *
+ * When you compile this, note that it links to libmtd from mtd-utils, so ensure
+ * that your include and lib paths include this.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <errno.h>
+#include <mtd/mtd-user.h>
+#include "libmtd.h"
+
+#define RELIABLE_BLOCKSIZE  0x10000 /* block capacity in reliable mode */
+#define STANDARD_BLOCKSIZE  0x40000 /* block capacity in normal mode */
+#define PAGESIZE 512
+#define PAGES_PER_BLOCK 512
+#define OOBSIZE 7              /* available to user (16 total) */
+
+uint8_t ff_oob[OOBSIZE] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+/* this is the magic number the IPL looks for (ASCII "BIPO") */
+uint8_t page0_oob[OOBSIZE] = {'B', 'I', 'P', 'O', 0xff, 0xff, 0xff};
+
+int main(int argc, char * const argv[])
+{
+       int devfd, datafd, num_blocks, block;
+       off_t file_size;
+       libmtd_t mtd_desc;
+       struct mtd_dev_info devinfo;
+       uint8_t *blockbuf;
+       char response[8];
+
+       if (argc != 3) {
+               printf("usage: %s <image file> <mtd dev node>\n", argv[0]);
+               return -EINVAL;
+       }
+
+       mtd_desc = libmtd_open();
+       if (mtd_desc == NULL) {
+               int errsv = errno;
+               fprintf(stderr, "can't initialize libmtd\n");
+               return -errsv;
+       }
+
+       /* open the spl image file and mtd device */
+       datafd = open(argv[1], O_RDONLY);
+       if (datafd == -1) {
+               int errsv = errno;
+               perror(argv[1]);
+               return -errsv;
+       }
+       devfd = open(argv[2], O_WRONLY);
+       if (devfd == -1) {
+               int errsv = errno;
+               perror(argv[2]);
+               return -errsv;
+       }
+       if (mtd_get_dev_info(mtd_desc, argv[2], &devinfo) < 0) {
+               int errsv = errno;
+               perror(argv[2]);
+               return -errsv;
+       }
+
+       /* determine the number of blocks needed by the image */
+       file_size = lseek(datafd, 0, SEEK_END);
+       if (file_size == (off_t)-1) {
+               int errsv = errno;
+               perror("lseek");
+               return -errsv;
+       }
+       num_blocks = (file_size + RELIABLE_BLOCKSIZE - 1) / RELIABLE_BLOCKSIZE;
+       file_size = lseek(datafd, 0, SEEK_SET);
+       if (file_size == (off_t)-1) {
+               int errsv = errno;
+               perror("lseek");
+               return -errsv;
+       }
+       printf("The mtd partition contains %d blocks\n", devinfo.eb_cnt);
+       printf("U-boot will occupy %d blocks\n", num_blocks);
+       if (num_blocks > devinfo.eb_cnt) {
+               fprintf(stderr, "Insufficient blocks on partition\n");
+               return -EINVAL;
+       }
+
+       printf("IMPORTANT: These blocks must be in an erased state!\n");
+       printf("Do you want to proceed?\n");
+       scanf("%s", response);
+       if ((response[0] != 'y') && (response[0] != 'Y')) {
+               printf("Exiting\n");
+               close(devfd);
+               close(datafd);
+               return 0;
+       }
+
+       blockbuf = calloc(RELIABLE_BLOCKSIZE, 1);
+       if (blockbuf == NULL) {
+               int errsv = errno;
+               perror("calloc");
+               return -errsv;
+       }
+
+       for (block = 0; block < num_blocks; block++) {
+               int ofs, page;
+               uint8_t *pagebuf = blockbuf, *buf = blockbuf;
+               uint8_t *oobbuf = page0_oob; /* magic num in oob of 1st page */
+               size_t len = RELIABLE_BLOCKSIZE;
+               int ret;
+
+               /* read data for one block from file */
+               while (len) {
+                       ssize_t read_ret = read(datafd, buf, len);
+                       if (read_ret == -1) {
+                               int errsv = errno;
+                               if (errno == EINTR)
+                                       continue;
+                               perror("read");
+                               return -errsv;
+                       } else if (read_ret == 0) {
+                               break; /* EOF */
+                       }
+                       len -= read_ret;
+                       buf += read_ret;
+               }
+
+               printf("Block %d: writing\r", block + 1);
+               fflush(stdout);
+
+               for (page = 0, ofs = 0;
+                    page < PAGES_PER_BLOCK;
+                    page++, ofs += PAGESIZE) {
+                       if (page & 0x04)  /* Odd-numbered 2k page */
+                               continue; /* skipped in reliable mode */
+
+                       ret = mtd_write(mtd_desc, &devinfo, devfd, block, ofs,
+                                       pagebuf, PAGESIZE, oobbuf, OOBSIZE,
+                                       MTD_OPS_PLACE_OOB);
+                       if (ret) {
+                               fprintf(stderr,
+                                       "\nmtd_write returned %d on block %d, ofs %x\n",
+                                       ret, block + 1, ofs);
+                               return -EIO;
+                       }
+                       oobbuf = ff_oob;  /* oob for subsequent pages */
+
+                       if (page & 0x01)  /* odd-numbered subpage */
+                               pagebuf += PAGESIZE;
+               }
+       }
+
+       printf("\nDone\n");
+
+       close(devfd);
+       close(datafd);
+       free(blockbuf);
+       return 0;
+}