+commit d318d0c44d8e91e937c4dad0c5b1d2f6bb9d9fd8
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jun 29 13:30:50 2009 +0200
+
+ UBI: Fix build problem noticed on Apollon (arm/testing repo)
+
+ This patch fixes a build problem noticed on Apollon by using
+ mtd_dev_by_eb() instead of "/" as done in the Linux UBI version.
+ So this brings the U-Boot UBI version more in sync with the Linux
+ version again.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2efee52b09657e9353655b9dae9e1d1a67a2abe4
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Mon Jul 6 20:29:15 2009 +0530
+
+ sf: Macronix additional chips supported
+
+ new chips supported:-
+ MX25L1605D, MX25L3205D, MX25L6405D, MX25L12855E
+ out of which MX25L6405D and MX25L12855E tested on Kirkwood platforms
+
+ Modified the Macronix flash support to use 2 bytes of device id instead of 1
+ This was required to support MX25L12855E
+
+ Signed-off-by: Piyush Shah <spiyush@marvell.com>
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit dd54126715b89ed0c43322aa78b0dad306f043b6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Jun 19 03:27:28 2009 -0400
+
+ sf: sst: add sst25vf###b ids
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 7d907f0ea993b179a197d8db2a36f122bc673c2d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Jun 19 03:20:06 2009 -0400
+
+ sf: sst: fix sector size
+
+ Looks like when I was encoding the sector sizes, I forgot to divide by 8
+ (due to the stupid marketing driven process that declares all sizes in
+ useless megabits and not megabytes).
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ceb70b466e75ceb1a621b6163f7e31116bfc8094
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Jul 5 01:06:06 2009 +0200
+
+ nhk8815: fix MAKEALL
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d08e5ca301b69ab77ecdd34e2b06aee30d6057d1
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date: Sat Jul 4 10:31:24 2009 +0200
+
+ MX31: Add NAND SPL boot support to i.MX31 PDK board.
+
+ Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit 78eabb90b793fafe875a7469526d1715fa56cbb4
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Mon Jun 29 20:55:54 2009 +0530
+
+ arm: Kirkwood: arch specific updated for ehci-Kirkwood driver support
+
+ This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 095a460b49022e64df76134300643606e3acb4e9
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Mon Jun 29 10:52:37 2009 +0200
+
+ arm nomadik: use 1000 as HZ value and rewrite timer code
+
+ This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites
+ timer code, which is now both correct and much smaller. Unused
+ functions like udelay_masked() have been removed as no driver uses
+ them, even the ones that are not currently active for this board.
+ mtu.h is copied literally from the kernel sources.
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f7aa59b29a451cc502078a9e4ba32345a4250c05
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Mon Jun 22 09:18:57 2009 +0200
+
+ arm nomadik: allow Nand and OneNand to coexists
+
+ The evaluation kit has both Nand and OneNand, both drivers are there
+ and the two configurations only select a different default for the
+ jffs partition. This adds the OneNand driver and cleans up storage.
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
+
+commit fd14c41a861cd38ee2fe3abd61d59b57b4eb23c9
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Mon Jun 22 09:18:47 2009 +0200
+
+ arm nomadik: cleanup reset
+
+ There is only one public release of the Nomadik chip, so the ifdef
+ in reset code as well as a define in the config file are not needed
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
+
+commit ee1363f2da3996bafdecdd8f4e48862ebff3f271
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Mon Jun 22 09:18:37 2009 +0200
+
+ arm nomadik: rename board to nhk8815
+
+ This is an error in my side in the initial submission: nobody
+ calls it ""nmdk8815", it's "nomadik hardware kit", nhk8815, instead.
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
+
+commit 040f8f63e922bbfb8ba0958bf637f11a917f5c38
+Author: Stefano Babic <sbabic@denx.de>
+Date: Wed Jul 1 20:40:41 2009 +0200
+
+ xscale: add support for the polaris board
+
+ The Polaris board is based on the TrizepsIV module of
+ Keith & Koep (http://www.keith-koep.com).
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 88bd97501314683b87f3f1edcf55b347c041b722
+Author: Stefano Babic <sbabic@denx.de>
+Date: Wed Jul 1 04:33:56 2009 +0200
+
+ xscale: fix USB initialization for Trizepsiv module
+
+ Due to change in the usb_board_init() prototype, the USB for
+ the TrizepsIV was not correctly initialized.
+ Removed dummy print from usb_board_stop().
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 0b785ddd60120cfb74d18e58c56054238219f6db
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Wed Jul 1 20:34:51 2009 +0200
+
+ net: merge bugfix: Marvell Kirkwood gigabit ethernet driver
+
+ This patch looks okay on u-boot-net.git/next branch
+ but when it was merged to u-boot.git/master the last line is missing
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 33b1d3f43a16fbb79004075ce89ae4e618b288a2
+Author: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
+Date: Tue Jun 30 21:03:37 2009 +0200
+
+ at91: Add esd gmbh MEESC board support
+
+ This patch adds support for esd gmbh MEESC board.
+ The MEESC is based on an Atmel AT91SAM9263 SoC.
+
+ Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
+
+commit 21761540b43c7086c75ee9afb412da1e5ddde2e9
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Jun 30 21:03:35 2009 +0200
+
+ ARM: Update mach-types
+
+ update against linux v2.6.30
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 45627fce18139a74e0755124d27376b520db156c
+Author: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
+Date: Tue Jun 30 23:03:33 2009 +0200
+
+ at91: Add CAN init function
+
+ To enable CAN init, CONFIG_CAN has to be defined in the board config file
+ and at91_can_hw_init() has to be called in the board specific code.
+
+ CAN is available on AT91SAM9263 and AT91CAP9 SoC.
+
+ Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
+
+commit 2e23008e5dbde7fe4c4758bee5a393e1db796cdf
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date: Tue Jun 30 23:03:31 2009 +0200
+
+ arm: Kirkwood: Correct header define
+
+ Correct define typo (. -> ,)
+
+ Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+
+commit 8449f287f5c53d59db13c3c512e6bd1750b692d1
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date: Wed Jul 1 01:07:55 2009 +0200
+
+ MX31: Add basic support for Freescale i.MX31 PDK board.
+
+ Add support for Freescale's i.MX31 PDK board (a.k.a. 3 stack board).
+
+ This patch assumes that some other program performs the actual
+ NAND boot.
+
+ Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+ Acked-by: Fabio Estevam <fabioestevam@yahoo.com>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8d460a573e2a2ac4834636903865a0428ad0e629
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Jun 23 00:12:01 2009 +0200
+
+ S3C24x0: extract interrupts from timer
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c8badbe500a752f42049e51042767ee62ea714e0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Jun 28 14:14:21 2009 +0200
+
+ dm355/pm9261: add missing CONFIG_NET_MULTI
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 798bf9a9ade1cfbe85a16d180cad720927d8e10a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Jun 23 00:12:01 2009 +0200
+
+ arm920t/interrupts: Move conditional compilation to Makefile
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 06e758e75c79ce8761866bf8165c443584a20893
+Author: Kim, Heung Jun <riverful@gmail.com>
+Date: Sat Jun 20 11:02:17 2009 +0200
+
+ move L2 cache enable/disable function to cache.c in the omap3 SoC directory
+
+ Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
+ CC: Dirk Behme <dirk.behme@googlemail.com>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d583ef5147066d3609de21f3beebbab99a19bad4
+Author: Thomas Lange <thomas@corelatus.se>
+Date: Sat Jun 20 11:02:17 2009 +0200
+
+ ARM DaVinci: EMIF settings
+
+ NAND module should not modify EMIF registers unrelated to CS2
+ that is used for NAND, i.e. do not modify EWAIT config register
+ or registers for other Chip Selects.
+
+ Without this patch, EMIF configurations made in board_init()
+ will be invalidated.
+
+ Signed-off-by: Thomas Lange <thomas@corelatus.se>
+
+commit 2600b8571a26c10c1c43401d7af38e2333cc5381
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jun 20 11:02:17 2009 +0200
+
+ versatile: config coding style cleanup
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Peter Pearse <peter.pearse@arm.com>
+
+commit 4efb77d41f9c5d93f0f92dda60e742023fa03c72
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Sat Jun 20 11:01:53 2009 +0200
+
+ arm: Kirkwood: Basic SOCs support
+
+ Kirkwood family controllers are highly integrated SOCs
+ based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core.
+
+ SOC versions supported:-
+ 1) 88F6281-A0 define CONFIG_KW88F6281_A0
+ 2) 88F6192-A0 define CONFIG_KW88F6192_A0
+
+ Other supported features:-
+ 1) get_random_hex() fucntion
+ 2) PCI Express port initialization
+ 3) NS16550 driver support
+
+ Contributors:
+ Yotam Admon <yotam@marvell.com>
+ Michael Blostein <michaelbl@marvell.com
+
+ Reviewed-by: Ronen Shitrit <rshitrit@marvell.com>
+ Acked-by: Stefan Rose <sr@denx.de>
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 5c3d5817e5e68b828c165c501c215e793dc63aac
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Sat Jun 20 11:01:52 2009 +0200
+
+ arm: generic cache.h for ARM architectures
+
+ This patch is required for Kirkwood SoC support
+ may be used by other ARM architectures
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 9c8c706c92e53433a871a563946c38075d76504d
+Author: Matthias Ludwig <mludwig@ultratronik.de>
+Date: Sat Jun 20 11:01:50 2009 +0200
+
+ OMAP3EVM: fix typo. replace CS6 by CS5, no functionality change
+
+ Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
+
+commit 0aafde1dc76d6d65d6be10bf499ec86d9ffee8b9
+Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
+Date: Wed Jun 24 08:32:09 2009 +0200
+
+ at91sam9260/9263: add back up for the rst(reset controller).
+
+ On the boards at91sam9260ek, at91sam9263ek and afed9260, the rstc register was
+ set to 0 after being set to 500 ms for the PHY reset.
+ Do backup the old reset length and restore it after the MACB initialisation.
+
+ Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
+ Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit afb0b1315c048ce2b1f35f0183b8b118ad0c14e1
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Jul 3 12:45:44 2009 -0500
+
+ fsl: Fix compiler warnings from gcc-4.4 in sys_eeprom code
+
+ sys_eeprom.c: In function 'do_mac':
+ sys_eeprom.c:323: warning: dereferencing type-punned pointer will break strict-aliasing rules
+ sys_eeprom.c: In function 'mac_read_from_eeprom':
+ sys_eeprom.c:395: warning: dereferencing type-punned pointer will break strict-aliasing rules
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:51 2009 -0500
+
+ 83xx: Add support for fsl_dma driver
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu>
+ Tested-by: Ira W. Snyder <iws@ovro.caltech.edu>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9adda5459ca62120c0c50b82b766fe1cf6925bbf
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:50 2009 -0500
+
+ 83xx: Replace CONFIG_ECC_INIT_VIA_DDRC references
+
+ Update 83xx architecture's CONFIG_ECC_INIT_VIA_DDRC references to
+ CONFIG_ECC_INIT_VIA_DDRCONTROLLER, which other Freescale architectures
+ use
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 039594a4301dadceb267db5e8b9c8c78b1bb86b5
+Author: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Date: Thu Jul 2 16:15:01 2009 +0530
+
+ 8xxx: Second UART port added for MPC85xx, MPC83xx, MPC86xx processors
+
+ Defining the next two configs allows to switch the serial port from the
+ console using the setenv stdin and stdout
+ 1. #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
+ 2. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+ Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 546b1032907df70f2dd0f98f3ad09885a88411e5
+Author: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Date: Thu Jul 2 16:14:40 2009 +0530
+
+ 85xx: Adds GPIO registers to MPC85xx Memory Map.
+
+ Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 5da6f806b400372b8a0664f3282c9e83a402eb66
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:26:01 2009 -0500
+
+ 86xx: XPedite5170 board support
+
+ Initial support for Extreme Engineering Solutions XPedite5170 -
+ a MPC8640-based 3U VPX single board computer with a PMC/XMC
+ site.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e66f38da8434425aca8df08d06d9ef41b3478d3b
+Author: Timur Tabi <timur@freescale.com>
+Date: Wed Jul 1 16:51:59 2009 -0500
+
+ fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more
+
+ The calculate for rank density in compute_ranksize() for DDR3 used all
+ integers for the expression, so the result was also a 32-bit integer, even
+ though the 'bsize' variable is a u64. Fix the expression to calculate a
+ true 64-bit value.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6af015b86b86d94de7ca1b23a3890bc93a50c2ab
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:49 2009 -0500
+
+ fsl_dma: Make DMA transactions snoopable
+
+ Make DMA transactions snoopable so that CPUs can keep caches up-to-date.
+ This allows dma transactions to be used for operations such as memory
+ copies without any additional cache control operations.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0d595f76bc9c7c8dff5bd31dffed87a840a03c56
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:48 2009 -0500
+
+ fsl_dma: Break out common memory initialization function
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 79f4333ceb059049b3ee560167d6cbaec493695f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:47 2009 -0500
+
+ 8xxx: Move dma_init() call to common code
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 191c7118592cd182f2dc7f46b4f72d9bed0e2c76
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:46 2009 -0500
+
+ fsl_dma: Move dma function prototypes to common header file
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 7892f619d40f4196e41e7114c5dfee9fad0f572f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:45 2009 -0500
+
+ 8xxx: Rename dma_xfer() to dmacpy()
+
+ Also update dmacpy()'s argument order to match memcpy's and use
+ phys_addr_t/phy_size_t for address/size arguments
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 484919cf3351212ebf748b9b13ece1ddaf7e7d1c
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:44 2009 -0500
+
+ fsl_dma: Fix Channel Start bug in dma_check()
+
+ The Channel Start (CS) bit in the Mode Register (MR) should actually be
+ cleared as the comment in the code suggests. Previously, CS was being
+ set, not cleared.
+
+ Assuming normal operation of the DMA engine, this change shouldn't have
+ any real affect.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 51402ac12be9a0025f16db51fbde7c050a54e5fe
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:43 2009 -0500
+
+ fsl_dma: Add support for arbitrarily large transfers
+
+ Support DMA transfers larger than the DMA controller's limit of
+ (2 ^ 26 - 1) bytes
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a730393a362741c318b21771b8d7b2647e546c3e
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:42 2009 -0500
+
+ fsl_dma: Use proper I/O access functions
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9c06071a6077ba95e9d43226156e39567d5d064a
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:41 2009 -0500
+
+ fsl_dma: Add bitfield definitions for common registers
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 017f11f68ef543e866be033bcb7b8058a8a380d8
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jun 30 17:15:40 2009 -0500
+
+ 8xxx: Break out DMA code to a common file
+
+ DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
+ previous CONFIG_DDR_ECC
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 29c35182462feea09f322e51913759a53359a3e0
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date: Tue Jun 30 13:56:23 2009 +0800
+
+ 85xx: Add pci e1000 Ethernet support for P2020 board
+
+ Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 156984a3611c28093919d3e3c042f722b5548253
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Jun 18 08:39:42 2009 -0500
+
+ 8xxx: Fix PCI bus address setup for 36-bit configs
+
+ We want the outbound PCI memory map to end at the 4G boundary so we
+ can maximize the amount of space available for inbound mappings if
+ we have large amounts of memory.
+
+ This matches the device tree setup in the kernel for the 36-bit physical
+ configs for the platforms that have one (MPC8641 HPCN & MPC8572 DS).
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 480f61790565d77432b70b4016b73f2ae27d530f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Jun 18 08:23:01 2009 -0500
+
+ 86xx: Add CPU_TYPE_ENTRY support
+
+ Unify with 83xx and 85xx and use CPU_TYPE_ENTRY. We are going to use
+ this to convey the # of cores and DDR width in the near future so its
+ good to keep in sync.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 98ab14e858bf60306d0aa3f0df5a7a5f88264aff
+Author: Peter Meerwald <pmeerw@pmeerw.net>
+Date: Mon Jun 29 15:48:33 2009 -0400
+
+ Blackfin: TWI/I2C: fix pure writes
+
+ If doing a pure write with register address and data (not a read/write
+ combo transfer), we don't set the initial transfer length properly which
+ ends up causing only the register address to be transferred.
+
+ While we're here, fix the i2c_write() parameter description of the buffer.
+
+ Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 5710de45808eb8f1cc34b51dc3e67e2422113249
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Sat May 30 01:13:33 2009 +0530
+
+ spi: Add Marvell Kirkwood SPI driver
+
+ This patch adds a SPI driver for the Marvell Kirkwood SoC's.
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 6bde171a4c4116cee179167cb65335a28f99932d
+Author: Minkyu Kang <mk7.kang@samsung.com>
+Date: Thu Jun 25 19:21:33 2009 +0900
+
+ s3c64xx: move the reset_cpu function
+
+ Because of the reset_cpu is soc specific, should be move to soc
+ And read reset value from SYS_ID register instead of hard code
+ this patch also supports s3c6410
+
+ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
+
+commit 576afd4faeba1519bcb8c0083c3e4d45e5643a48
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 17 00:58:37 2009 +0200
+
+ integrator: merge integratorap and integratorcp
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Peter Pearse <peter.pearse@arm.com>
+
+commit 46937b27427688a56bf7f5944a92d962dc43c3fa
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 17 00:58:36 2009 +0200
+
+ integratorap/cp: use cfi driver
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Peter Pearse <peter.pearse@arm.com>
+
+commit de7a01abd8aeb167946f391327e1e0d1e01f90c9
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 17 00:58:36 2009 +0200
+
+ integratorap/cp/versatile: remove non used functions
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Peter Pearse <peter.pearse@arm.com>
+
+commit f54851a6e3844b7e01581b5a9681f294118b7529
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 17 00:58:36 2009 +0200
+
+ integratorcp: split timer support
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Peter Pearse <peter.pearse@arm.com>
+
+commit 2bcef0723ea11c4e9bfbcfff2a93ec2da520b5f1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 17 00:58:36 2009 +0200
+
+ integratorap: split timer support
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Peter Pearse <peter.pearse@arm.com>
+
+commit 86baa085c52a7f3377a88074679c5aca9b9e4d38
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 17 00:58:36 2009 +0200
+
+ integratorap: split pci support
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Peter Pearse <peter.pearse@arm.com>
+
+commit 379e9fc0a319b8f6ae16d763590bf023f3afb87c
+Author: Ilya Yanok <yanok@emcraft.com>
+Date: Mon Jun 8 04:12:50 2009 +0400
+
+ arm: add support for CONFIG_GENERIC_MMC
+
+ Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 47d19da4d3f9ac4787abe9dee32406478424be52
+Author: Ilya Yanok <yanok@emcraft.com>
+Date: Mon Jun 8 04:12:46 2009 +0400
+
+ serial_mx31: allow it to work with mx27 too and rename to serial_mxc
+
+ UART hardware on i.MX27 is the same as on the i.MX31 so we just
+ need to provide the driver with correct address of the registers.
+
+ Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 1dc4da749dbde27ec862f5b65703e8e4541fbba3
+Author: Ilya Yanok <yanok@emcraft.com>
+Date: Mon Jun 8 04:12:45 2009 +0400
+
+ mx27: basic cpu support
+
+ This patch adds generic code to support Freescale's i.MX27 SoCs.
+
+ Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit dd2f6965a6c71f6f711ec98827880152e022c236
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date: Sat Jun 13 20:50:03 2009 +0200
+
+ i.MX31: Create a common device file.
+
+ Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit 958f7da7887fea4a2091ae60944d62c1708c2c55
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jun 13 20:50:02 2009 +0200
+
+ ARM: Add macros.h to be used in assembler file.
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 40c642bc19b9fa2906e3172487a522fee456340b
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date: Sat Jun 13 20:50:01 2009 +0200
+
+ MX31: Add NAND SPL for i.MX31.
+
+ This patch adds the NAND SPL framework needed to boot i.MX31 boards
+ from NAND.
+
+ It has been tested on a i.MX31 PDK board with large page NAND. Small
+ page NANDs should work as well, but this has not been tested.
+
+ Note: The i.MX31 NFC uses a non-standard layout for large page NANDs,
+ whether this is compatible with a particular setup depends on how
+ the NAND device is programmed by the flash programmer (e.g. JTAG
+ debugger).
+
+ The patch is based on the work by Maxim Artamonov.
+
+ Signed-off-by: Maxim Artamonov <scn1874@yandex.ru>
+ Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit df81238b3e27a791da996a9208402ac8f40b9862
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date: Sat Jun 13 20:50:00 2009 +0200
+
+ ARM1136: Introduce CONFIG_PRELOADER macro.
+
+ Currently CONFIG_ONENAND_IPL is used in a number of #ifdef's
+ in start.S. In preparation for adding support for NAND SPL
+ the macro CONFIG_PRELOADER is introducted and replaces the
+ CONFIG_ONENAND_IPL in start.S.
+
+ Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit 8096c51fd4e611ed666dbe77767e81af5d94fc7b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jun 13 12:50:04 2009 +0200
+
+ at91: unify nor boot support
+
+ the lowlevel init sequence is the same so unify it
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1b3b7c640d04df2ba9a9d947117d112a75fee7f4
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jun 13 12:48:36 2009 +0200
+
+ at91sam9263ek: add nor flash support
+
+ this will allow you to store use it for the env and to boot directly U-Boot from
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 329492329700812c6df275aa0fda09d609cd0fd4
+Author: Ilko Iliev <iliev@ronetix.at>
+Date: Fri Jun 12 21:20:39 2009 +0200
+
+ at91: add support for the PM9261 board of Ronetix GmbH
+
+ The PM9261 board is based on the AT91SAM9261-EK board.
+
+ Here is the page on Ronetix website:
+ http://www.ronetix.at/starter_kit_9261.html
+
+ Signed-off-by: Ilko Iliev <iliev@ronetix.at>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 01550a2b650fbabc03334f9eadcc6083601a2414
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Jun 12 21:20:38 2009 +0200
+
+ pm9263: use macro instead of hardcode value for the lowlevel_init
+
+ optimize a few the RAM init
+
+ Signed-off-by: Ilko Iliev <iliev@ronetix.at>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7a11c7f9747240dc770954d320569596c0fbcb50
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Jun 12 21:20:37 2009 +0200
+
+ pm9263: lowlevel init update
+
+ move PSRAM init to pm9263.c
+ this will allow us after to make the nor lowlevel_init generic
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 3e88337b225bf796f6df21d0a7f591530e9d4ce0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Jun 15 00:25:19 2009 -0400
+
+ Blackfin: move ALL += u-boot.ldr to blackfin_config.mk
+
+ The way the ALL variable is used allows for config.mk's to add more
+ targets themselves without having to clutter up the top level Makefile.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit afac8b07172d7e4a65f86ce1ec4c783a6165ba1f
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 22:29:35 2009 -0400
+
+ Blackfin: fix SPI flash speed define name
+
+ The SPI flash define is named CONFIG_SF_DEFAULT_SPEED, not
+ CONFIG_SF_DEFAULT_HZ, so fix the typos in the Blackfin boards.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 9ae55ccf601de7a5b75eb418f3fc3d5eca92c106
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 22:26:31 2009 -0400
+
+ Blackfin: enable -O2 in lib_generic/ for ADI/Bluetechnix boards
+
+ Building the compression code in lib_generic/ with -O2 rather than -Os
+ gives a nice speed boost without too much code size increase.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit fea63e2a44f0db51d2e39ee7793e8c6d7f3cf5d4
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 21:23:27 2009 -0400
+
+ Blackfin: bf548-ezkit: bump up monitor size
+
+ The latest version of U-Boot got a bit fatter in the BSS section which
+ caused overflows in the RAM region, so increase the monitor size.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit bc43a8d8994c2f0be29e09b13b15da7f79e2c081
+Author: Vivi Li <vivi.li@analog.com>
+Date: Fri Jun 12 10:53:22 2009 +0000
+
+ Blackfin: bf533-stamp/bf537-stamp: fix env settings for SPI flash
+
+ The SPI flash layer is much stricter about sector usage than the eeprom
+ layer we used to use, so update the env settings to better match the
+ sector alignment of the flashes we use.
+
+ Signed-off-by: Vivi Li <vivi.li@analog.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 63cb0f4eb2d3cf15e7a1add19d1289f4ae75816c
+Author: Vivi Li <vivi.li@analog.com>
+Date: Fri Jun 12 10:33:23 2009 +0000
+
+ Blackfin: bump up default JTAG console timeout
+
+ The debug tools that interface with the other side of the JTAG console
+ got much slower when generalizing things, so bump up the default timeout
+ value on the U-Boot side to cope. Hopefully at some point we can improve
+ the debug tools to speed things back up.
+
+ Signed-off-by: Vivi Li <vivi.li@analog.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c11ff779f4e0e0c7edc322e84dd229ad28709595
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Jun 1 19:08:33 2009 -0400
+
+ Blackfin: add jtagconsole helper script
+
+ This script is similar to the netconsole script, but instead works with
+ the JTAG console device driver that exists on Blackfin parts.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 60f61e6d7655400bb785a2ef637581679941f6d1
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Sat May 2 21:49:18 2009 +0200
+
+ Convert DM9000 driver for CONFIG_NET_MULTI
+
+ All drivers need to be converted to CONFIG_NET_MULTI.
+ This patch converts the dm9000 driver.
+
+ Signed-off-by: Thomas Smits <ts.smits@gmail.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 9131589ada4dda0718604d0a425ca46e52775f6e
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Sun Jun 14 22:33:46 2009 +0530
+
+ net: Add Marvell Kirkwood gigabit ethernet driver
+
+ This patch adds a egiga driver for the Marvell Kirkwood SoC's.
+
+ Contributors:
+ Yotam Admon <yotam@marvell.com>
+ Michael Blostein <michaelbl@marvell.com
+
+ Reviewed-by: Ronen Shitrit <rshitrit@marvell.com>
+ Acked-by: Stefan Rose <sr@denx.de>
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 7835f4b94927ecb5affd99aad62592108db606ad
+Author: s-paulraj@ti.com <s-paulraj@ti.com>
+Date: Tue May 12 11:45:34 2009 -0400
+
+ DaVinci Network Driver Updates
+
+ Different flavours of DaVinci SOC's have differences in their EMAC IP
+ This patch does the following
+ 1) Updates base addresses for DM365
+ 2) Updates MDIO frequencies for DM365 and DM646x
+ 3) Update EMAC wrapper registers for DM365 and DM646x
+
+ Patch applies to u-boot-net git. the EMAC driver itself
+ will be updated shortly to add support for DM365 and DM646x
+
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 44578bea14e49035331a8f0e000e935e0d830ff4
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Tue May 26 08:29:29 2009 -0400
+
+ Subject: [PATCH] [repost] Standardize the use of MCFFEC_TOUT_LOOP as a udelay(1) loop counter.
+
+ From 584b5fbd4abfc43f920cc1c329633e03816e28be Mon Sep 17 00:00:00 2001
+ From: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+ Date: Wed, 20 May 2009 18:26:01 -0400
+ Subject: [PATCH] Standardize the use of MCFFEC_TOUT_LOOP as a udelay(1) loop counter.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit c9a2aab1512fb2d132670fff9c27656d2eb949cd
+Author: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
+Date: Thu Jun 4 09:39:48 2009 +0200
+
+ A VLAN tagged DHCP request/discover is 4 bytes short
+
+ The problem is that BOOTP_SIZE uses ETHER_HDR_SIZE which is 14 bytes.
+ If sending a VLAN tagged frame (when env variable vlan is set) this
+ should be VLAN_ETHER_HDR_SIZE=18 which is what NetSetEther returns.
+
+ Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 6e0d2fc7fe0dcfa2f51ab8931d706940ee364193
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Tue Apr 28 16:39:19 2009 -0700
+
+ Remove support for non-CONFIG_NET_MULTI on PPC4xx EMAC
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8453587ef9137daf98b7c9cf4f3b865f4039cea0
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Tue May 26 00:34:07 2009 -0700
+
+ Switched davinci_emac Ethernet driver to use newer API
+
+ Added CONFIG_NET_MULTI to all Davinci boards
+ Removed all calls to Davinci network driver from board code
+ Added cpu_eth_init() to cpu/arm926ejs/cpu.c
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8cc13c13f1d154c8fa8fff56cea357ed38af76bf
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Mon Apr 27 23:19:10 2009 -0700
+
+ Initial cleanup of Davinci Ethernet driver
+
+ Removed pointless #ifdefs
+ Moved functions around in file in preparation for switch to newer API
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 09cdd1b9b01450e91786d26ff3c866dc9c8d8d6b
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Tue May 26 00:17:59 2009 -0700
+
+ Moved Davinci Ethernet driver to drivers/net
+
+ This driver has been renamed davinci_emac.c
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 6f51deb7f298413cfcb0a36d24c97ef7dd69d48f
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Tue May 19 01:40:16 2009 +0530
+
+ Marvell MV88E61XX Switch Driver support
+
+ Chips supported:-
+ 1. 88E6161 6 port gbe swtich with 5 integrated PHYs
+ 2. 88E6165 6 port gbe swtich with 5 integrated PHYs
+ 2. 88E6132 3 port gbe swtich with 2 integrated PHYs
+ Platform specific configuration supported for:-
+ default or router port vlan configuration
+ led_init configuration
+ mdip/n polarity reversal configuration
+
+ Note: This driver is supported and tested against
+ kirkwood egiga interface
+
+ Contributors:
+ Yotam Admon <yotam@marvell.com>
+ Michael Blostein <michaelbl@marvell.com
+
+ Reviewed by: Ronen Shitrit <rshitrit@marvell.com>
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 091dc9f6adaf572b067ae91af92c4e7db33d7903
+Author: Zach LeRoy <zleroy@xes-inc.com>
+Date: Fri May 22 10:26:33 2009 -0500
+
+ tsec: Add support for BCM5482S PHY
+
+ Signed-off-by: Zach LeRoy <zleroy@xes-inc.com>
+ Acked-by: Kumar Gala <galak@kernel.crashing.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 9ff67e5e4c719556d57f136a6453f8e4798d85c0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 06:29:07 2009 -0400
+
+ Blackfin: unify u-boot linker scripts
+
+ All the Blackfin linker scripts were duplicated across the board dirs with
+ no difference save from the semi-often used ENV_IS_EMBEDDED option. So
+ unify all of them in the lib_blackfin/ dir and for the few boards that
+ need to embedded the environment directly, add a LDS_BOARD_TEXT define for
+ them to customize via their board config file. This is much simpler than
+ forcing them to duplicate the rest of the linker script.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit f52efcae98cbb8a39f1d0535df8d9646a776af9e
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri May 29 17:02:37 2009 -0400
+
+ Blackfin: bf518f-ezbrd: enable SST SPI flash driver
+
+ The BF51xF parts have an internal SST SPI flash, so make sure the driver is
+ enabled by default so we can access it.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit f348ab85f741dc98b2d202c04b5f430eace94925
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Apr 24 17:22:40 2009 -0400
+
+ Blackfin: convert specific pre/post config headers to common method
+
+ The Blackfin port was using asm/blackfin-config-{pre,post}.h to setup
+ common Blackfin board defines. The common method now is to use config.h,
+ so convert blackfin-config-post.h to that. Rename the still Blackfin
+ specific blackfin-config-pre.h to config-pre.h so the naming conventions
+ at least line up.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 7c7503ee6cd03c0f3b16e98d33d5aa23b30d65b1
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Apr 24 17:11:47 2009 -0400
+
+ Blackfin: enable LZMA for all ADI boards
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0e63dc0679451d48f8b727c543ce48b488f7a33f
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Apr 13 05:52:45 2009 -0400
+
+ Blackfin: make default ADI env more flexible
+
+ Allow boards to easily override the root= and default bootcmd, allow
+ people to tweak the file used in default bootcmds at runtime via one env
+ var, and add a stock nandboot command.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0f52b560f19623ec651f9b9b40405d138ec251d3
+Author: Hoan Hoang <hnhoan@i-syst.com>
+Date: Sun Jan 18 22:44:17 2009 -0500
+
+ Blackfin: ibf-dsp561: new board port
+
+ Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 3088189a15d219c48fd7e71623ca4daa08b80b59
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 23:28:33 2008 -0400
+
+ Blackfin: blackstamp: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 59ac9729700db1d4446c1a6db3ffe38398b7abb2
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 23:22:25 2008 -0400
+
+ Blackfin: bf537-srv1: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d7fdc1410b5fa5ef623b35a283733b6bcee3753b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 23:16:52 2008 -0400
+
+ Blackfin: bf537-minotaur: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit cb4b5e874f3c9b882a6f4394bbebbbd91fd01bbf
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 23:08:03 2008 -0400
+
+ Blackfin: bf537-pnav: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 59e4be945b6469e31eee721e0bcdccf4940d75ac
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 21:55:45 2008 -0400
+
+ Blackfin: cm-bf527: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8b219cf07c186cc9d97354cf4b14f24a53d193c5
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 21:54:07 2008 -0400
+
+ Blackfin: cm-bf548: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 9417d9a21384279308abe5b4dd8dfd418742484c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 21:49:28 2008 -0400
+
+ Blackfin: tcm-bf537: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e548321af00e869af7194896576beb9b68457ff7
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 21:45:05 2008 -0400
+
+ Blackfin: cm-bf561: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8a9bab08a6fe93e5f3bf57b90438f1d2a67fad3c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 21:41:06 2008 -0400
+
+ Blackfin: cm-bf537e: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e82d8a1f028bedb12c4ab88a35a935010d92898c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 21:36:22 2008 -0400
+
+ Blackfin: cm-bf533: new board port
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit dd14af7640f7d48d8e9768eeeb09592e6f94ed38
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Nov 27 16:50:32 2008 -0500
+
+ Blackfin: new spibootldr command
+
+ Newer Blackfin parts can an on-chip ROM that can boot LDRs over SPI flashes,
+ so add a new 'spibootldr' command to take advantage of it.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 67c2829b646bb5b859088b36fbc89e971b9c1960
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 04:42:33 2008 -0400
+
+ Blackfin: support embedding the environment into loader files (LDRs)
+
+ For the most part, the Blackfin processor boots files in the LDR format
+ rather than binary/ELF files. So we want to export the environment as a
+ raw blob to the LDR utility so it can embed it at the right location.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 31f30c9eb60d9ab0bd702e31f66345f99b34bdc6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 11:03:48 2009 -0400
+
+ add %.c->%.i and %.c->%.s rules
+
+ The Linux kernel has some helper rules which allow you to quickly produce
+ some of the intermediary files from C source. Specifically, you can
+ create .i files which is the preprocessed output and you can create .s
+ files which is the assembler output. This is useful when you are trying
+ to track down header/macro expansion errors or inline assembly errors.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6d1ce387874c1060f27656f70151a52c511cd0e3
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat May 30 01:02:03 2009 -0400
+
+ make sure toplevel $(SUBDIRS) is always declared
+
+ The $(SUBDIRS) variable is only declared when U-Boot has been configured,
+ but it gets used all the time. In the non-configured case, it is used to
+ generate a helpful error message, but it needs to be set properly for that
+ to occur.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1260233982f7dfbdfd1adee12daa95a0c0e84a43
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Jun 12 11:33:55 2009 +0200
+
+ digsy mtc: Add description to GPIO initial configuration.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 12304871bc7839145f2b4238923e9023616d7399
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Jun 12 11:33:54 2009 +0200
+
+ digsy MTC: Add 'mtc' command.
+
+ New command allows to:
+ o check FW version
+ o set LED status
+ o set digital output status
+ o get digital input status
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit f1f66edfc76f4a9f5b9f63972d90309784a8cae5
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Jun 12 11:33:53 2009 +0200
+
+ digsy MTC: Add SPI support.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 6325b7780dad8be26ba6fc25ef88ba338c50205b
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Jun 12 11:33:52 2009 +0200
+
+ mpc52xx: Add SPI driver.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 5ec5529b82f314ca2cf9c262cdfc985d5fc468a0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 09:33:00 2009 -0400
+
+ allow boards to customize compiler options on a per-file/dir basis
+
+ With our Blackfin boards, we like to build the compression routines with
+ -O2 as our tests show a pretty good size/speed tradeoff. For the rest of
+ U-Boot though, we want to stick with the default -Os as that is mostly
+ control code. So in our case, we would add a line like so to the board
+ specific config.mk file:
+ CFLAGS_lib_generic += -O2
+
+ Now all files under lib_generic/ will have -O2 appended to their build.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6b1f78ae6ad037382ad430b07064105c88f7ac02
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 21:30:39 2009 +0200
+
+ Prepare v2009.06
+
+ Update CHANGELOG, fix minor coding stylke issue. Update Makefile.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit c3147c1762f8caf99649051116a2411bdf887c10
Author: Wolfgang Denk <wd@denx.de>
-Date: Sun Jun 14 20:31:36 2009 +0200
+Date: Sun Jun 14 20:31:36 2009 +0200
+
+ Revert "SMC911x driver fixed for NFS boot"
+
+ This reverts commit ca9c8a1e10fac01e6a1129f82a7ce18bd818fa43,
+ which causes compile warnings ("large integer implicitly truncated
+ to unsigned type") on all systems that use this driver. The warning
+ results from passing long constants (TX_CFG, RX_CFG) into
+ smc911x_set_mac_csr() which is declared to accept "unsigned
+ character" arguments only.
+
+ Being close to a release, with nobody available to actually test the
+ code or the suggested fixes, it seems better to revert the patch.
+
+commit 388517e4b745b00256c2fa201ce7bccb67b4f245
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri May 22 10:26:37 2009 -0500
+
+ xes: Update Freescale clock code to work with 86xx processors
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 25623937bb81cae788d767e6c59a11c96fc82866
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri May 22 10:26:36 2009 -0500
+
+ xes: Update Freescale DDR code to work with 86xx processors
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit bef3013908bbc68f24084174a3ca86cc2a3eb986
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri May 22 10:26:35 2009 -0500
+
+ xes: Update Freescale PCI code to work with 86xx processors
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6442b71b522face775c1c31bd43121db3b4bf7d6
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri May 22 10:26:32 2009 -0500
+
+ 85xx: Add PORBMSR and PORDEVSR shift defines
+
+ Add defines similar to those already used for the the 86xx architecture.
+ This will ease sharing of PCI code between the 85xx and 86xx
+ architectures.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 2f21ce4d546d31289ac49a680f78bcc9a792c6ec
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Thu May 21 12:10:00 2009 -0500
+
+ fsl/85xx, 86xx: Sync up DMA code
+
+ The following changes were made to sync up the DMA code between the 85xx
+ and 86xx architectures which will make it easier to break out common
+ 8xxx DMA code:
+
+ 85xx:
+ - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits
+ only have an affect when the SBPATMU bit is set.
+ - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
+ status register. We may as well clear all 32 bits of the register...
+
+ 86xx:
+ - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
+ - Add clearing of errors in the DMA status register when initializing
+ the controller
+ - Clear the channel start bit in the DMA mode register after a transfer
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b1f12650d332eadac1306a772cab6096abee6ddd
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Thu May 21 12:09:59 2009 -0500
+
+ fsl: Create common fsl_dma.h for 85xx and 86xx cpus
+
+ Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
+ reduce a large amount of code duplication
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 3bd8e532b5de20647aeaff94a1cbf33fb8b897b9
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed May 20 12:30:41 2009 -0400
+
+ 85xx: Add UEC6 and UEC8 at SGMII mode for MPC8569MDS
+
+ On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via
+ UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we
+ disable UEC6 and UEC8 by default.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e8efef7c1b457442583a8b9d38d8a5b667661616
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Thu Jun 4 16:12:42 2009 -0400
+
+ drivers/qe: add sgmii support in for UEC driver
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 8e55258f144764de8902e9f078a7ad4c6c022c2f
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Thu Jun 4 16:12:41 2009 -0400
+
+ qe: Pass in uec_info struct through uec_initialize
+
+ The uec driver contains code to hard code configuration information for the uec
+ ethernet controllers. This patch creates an array of uec_info structures, which
+ are then parsed by the corresponding driver instance to determine configuration.
+ It also creates function uec_standard_init() to initialize all UEC interfaces
+ for 83xx and 85xx.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9a6110897fc9282ade598bbba70ad72b940436e3
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Thu Jun 4 16:12:40 2009 -0400
+
+ fsl: Update the number of ethxaddr in reading system eeprom
+
+ We support up to 8 mac addresses in system eeprom, so we define the macro
+ MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
+ according to mac_count.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f82107f637f167a77803c0933f9b24741a91c711
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed May 20 12:30:37 2009 -0400
+
+ 85xx: Add RMII support for MPC8569MDS
+
+ This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
+ support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
+ enalbe_mpc8569mds_qe_uec which is more accurate.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 750098d33bc362ac4263863e92da158cf011063f
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed May 20 12:30:36 2009 -0400
+
+ 85xx: Add UEC3 and UEC4 support for MPC8569MDS
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 4e7b25e4fe777f525e426cbd58c3a3976c564f2e
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed May 20 12:30:35 2009 -0400
+
+ drivers/qe: Add more SNUM number for QE
+
+ Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
+ 1000 mode.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Acked-by: Timur Tabi <timur@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 7211fbfa18f3061858696150ee6e9e093d9eceae
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Thu May 21 15:34:14 2009 -0400
+
+ drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs
+
+ Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
+ define MAX_QE_RISC for QE based silicons.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Acked-by: Timur Tabi <timur@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b3d7f20f43a0f8d11c65e2f92153b5512b11580c
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed May 20 12:30:29 2009 -0400
+
+ 85xx: Add QE clk support
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Acked-by: Timur Tabi <Timur@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 71b358cc26792889bbac35054d8e89d59b3fabc4
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed May 20 01:11:33 2009 -0500
+
+ 85xx: Added MPC8535/E identifiers
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 22419d77976bbd0df9fcf45513f1b96bd73e50d1
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu May 21 08:36:43 2009 -0500
+
+ 85xx: Always attempt ethernet device tree fixup
+
+ Its reasonable that we may have ethernet devices but dont have drivers
+ or support enabled for them in u-boot and want the device tree fixed up.
+ Unconditionally calling the ethernet fixup is fine since if we dont have
+ ethernet nodes that match (or aliases) we will not attempt to do
+ anything.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Timur Tabi <timur@freescale.com>
+
+commit 52d6ad5ecfb22938441c8e3e62935fbd7b0f0920
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Thu May 21 15:32:13 2009 -0400
+
+ drivers/qe: Rename the camel-case identifiers in uec
+
+ Rename riscRx/riscTx to risc_rx/risc_tx to comply with Codingstyle.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit feb7838f979ec2b581df3c791b9ae3284c36bb47
+Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+Date: Fri Apr 3 15:36:13 2009 -0500
+
+ 85xx: Add P2020DS support
+
+ The patch adds support for P2020DS reference platform.
+ DDR3 interface uses hard-coded initialization rather than SPD
+ for now and was tested at 667Mhz. Some PIXIS register
+ definitions and associated code sections need to be fixed.
+ TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all
+ tested under u-boot.
+
+ Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 229549a56d9ae413c00f64fd7c728c6879a1b54b
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jun 9 16:57:47 2009 +0200
+
+ mpc512x: MPC5121ADS: Add NAND support
+
+ This patch adds NAND support to the MPC5121ADS board. Please
+ note that the image size increased since NAND support didn't
+ fit in the current image size (256k).
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Wolfgang Denk <wd@denx.de>
+
+commit 35f2edbb6cad043ccd5ea6e78fe9b7aa21d8395f
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jun 9 16:57:03 2009 +0200
+
+ nand/mpc512x: Add MPC512x NAND support (NFC)
+
+ This patch adds NAND Flash Controller driver for MPC5121 revision 2.
+ All device features, except hardware ECC and power management, are
+ supported.
+
+ This NFC driver replaces the one orignally posted by John Rigby:
+
+ "[PATCH] Freescale NFC NAND driver"
+
+ It's a port of the Linux driver version posted by Piotr Ziecik a few
+ weeks ago. Using this driver has the following advantages (from my
+ point of view):
+
+ - Compatibility with the Linux NAND driver (e.g. ECC usage)
+ - Better code quality in general
+ - Resulting U-Boot image is a bit smaller (approx. 3k)
+ - Better to sync with newer Linux driver versions
+
+ The only disadvantage I can see, is that HW-ECC is not supported right
+ now. But this could be added later (e.g. port from Linux driver after
+ it's supported there). Using HW-ECC on the MCP5121 NFC has a general
+ problem because of the ECC usage in the spare area. This collides with
+ JFFS2 for example.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Piotr Ziecik <kosmo@semihalf.com>
+ Cc: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+ Cc: Scott Wood <scottwood@freescale.com>
+
+commit e53b507cee5d976953134a565c72fd32c967d7dd
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jun 9 11:50:40 2009 +0200
+
+ mpc512x: Add esd gmbh mecp5123 board support
+
+ MECP5123 is a MPC5121E based module by esd gmbh.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 6bd55cc65d0c3aa84d719518254fb3c650239ed9
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jun 9 11:50:05 2009 +0200
+
+ mcp512x: Add macros for SCFR LPC divisor access
+
+ Thos macros will be used by the esd mecp5123 board.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c60dc8527dbb2a1318c03bc18bdebcfbd0164551
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jun 8 09:38:07 2009 +0200
+
+ mpc512x: Fix problem with I2C access before relocation
+
+ This is needed for the upcoming esd MECP5123 board port which uses
+ I2C EEPROM for environment storage.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ Acked-by: Heiko Schocher<hs@denx.de>
+
+commit 58f10460b05e0928d986b15edd4f2e1e99403f7e
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jun 4 13:35:39 2009 +0200
+
+ 74xx_7xx: CPCI750: Add CPCI adapter/target support
+
+ The CPCI750 can be built as CPCI host or adapter/target board. This patch
+ adds support for runtime detection of those variants.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit ae7a2739d7a0704437376e229bb21940952c55be
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Jun 5 05:45:41 2009 +0200
+
+ 74xx_7xx: CPCI750: Enable access to PCI function > 0
+
+ The Marvell bridge 64360 supports serveral PCI functions, not only 0. This
+ patch enables access to those functions.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit e5b563e9ec54c3f6d702c8fa2b711b4a6150243a
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jun 4 13:35:37 2009 +0200
+
+ 74xx_7xx: CPCI750: Minor coding style cleanup of cpci750.c
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 0e5ef07d0d91bd3d87ebea0534f538561aa974d5
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jun 4 13:35:36 2009 +0200
+
+ 74xx_7xx: CPCI750: Add loadpci command
+
+ This command is used to load/boot an OS-image which is transferred from
+ the CPCI host to the CPCI target/adapter.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 0a14d6b8f4d21ff59a9b7686a49a77069a9fcd2a
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jun 4 13:35:35 2009 +0200
+
+ 74xx_7xx: CPCI750: Add commandline editing/history
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 60cfe87bd39e6f07f2b92eb4bff82bfd105f4724
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jun 4 16:55:34 2009 +0200
+
+ UBI: Add compile-time check for correct malloc area configuration
+
+ UBI is quite memory greedy and requires at least approx. 512k of malloc
+ area. This patch adds a compile-time check, so that boards will not
+ build with less memory reserved for this area (CONFIG_SYS_MALLOC_LEN).
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7ce6031afc8671c8b47c6135b3678d43fcd02852
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Mon Apr 6 21:24:43 2009 +0530
+
+ sf: new Macronix MX25xx SPI flash driver
+
+ Added macronix SF driver for MTD framework
+ MX25L12805D is supported and tested
+ TBD: sector erase implementation, other deivces support
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2a6cc58869305f346e389eefdfa96dea5146cb0c
+Author: Todor I Mollov <tmollov@ucsd.edu>
+Date: Sat Apr 4 07:14:44 2009 -0400
+
+ sf: atmel: implement power-of-two write/erase funcs
+
+ Signed-off-by: Todor I Mollov <tmollov@ucsd.edu>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+
+commit 4bc6eb79be2a7317425575184324b94e3b43fbc2
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Mon May 25 17:23:18 2009 +0530
+
+ mpc85xx: 8536ds: Add USB related CONFIGs
+
+ This patch adds CONFIGs for enabling USB in mpc8536ds and also
+ adds usb_phy_type in CONFIG_EXTRA_ENV_SETTINGS. Also revamps its
+ Copyright.
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 6823e9b01290977c4d9c90381459c01f66e12e79
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Mon May 25 17:23:17 2009 +0530
+
+ mpc83xx: 8315erdb: Add USB related CONFIGs
+
+ This patch adds CONFIGs for enabling USB in mpc8315erdb and also
+ adds usb_phy_type in CONFIG_EXTRA_ENV_SETTINGS. Also revamps its
+ Copyright.
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit a07bf180efc3c0de4a89a3bd49a7c7584dfb95a8
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Thu May 21 17:32:48 2009 +0530
+
+ mpc85xx: USB: Add support
+
+ The following patch adds 85xx-specific USB support and also
+ revamps Copyright in immap_85xx.h
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 4ef01010aa4799c759d75e67007fdd3a38c88c8a
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Mon May 25 17:23:16 2009 +0530
+
+ mpc83xx: USB: Reorganized its support
+
+ The following patch reorganizes/reworks the USB support for mpc83xx
+ as under:-
+
+ * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
+ cpu/mpx83xx/cpu_init.c
+
+ * Board specific usb_phy_type is read from the environment
+
+ * Adds USB EHCI specific structure in include/usb/ehci-fsl.h
+
+ * Copyrights revamped in most of the following files
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit ed90d2c87158e5114b6009fa95bb6417e4b27b3e
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Thu May 21 17:32:27 2009 +0530
+
+ mpc8xxx: USB: Relocates ehci-fsl.h to include/usb
+
+ The following patch moves 8xxx-specifc USB #defines from
+ drivers/usb/host/ehci-fsl.h to include/usb.
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit cfd39cdf9422d3d25e9b3c058865f4c1f66f34da
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Thu May 21 17:32:15 2009 +0530
+
+ mpc8xxx: USB: Removed reenablement of its interface
+
+ To prepare for the 85xx USB support, which requires interface enablement
+ only once in (specified) order, no different than instructions for
+ enabling the interface under 83xx. It is unknown why the original author
+ enabled the interface twice (checked for references in errata, etc).
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 2c7920afaf96d9779304202cd8a355b4f7576a83
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri May 22 17:23:25 2009 -0500
+
+ 83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]x
+
+ Use the standard lowercase "x" capitalization that other Freescale
+ architectures use for CPU defines to prevent confusion and errors
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 0f898604945af4543c1525fc33b6bae621a3b805
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri May 22 17:23:24 2009 -0500
+
+ 83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xx
+
+ Use the standard lowercase "xx" capitalization that other Freescale
+ architectures use for CPU defines to prevent confusion and errors
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit ba4feae90ca71de1681d5808f17e73224d8f03c4
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jun 2 16:53:16 2009 +0200
+
+ mpc512x: Use serial_setbrg() in serial_init() to not duplicate the code
+
+ This patch removes the duplicated code for baudrate generator configuration
+ in the PSC serial_init() implementation by calling serial_setbrg() instead
+ of duplicating the code.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b8c1d6a54ff8195488b68e163de8ec31f1603496
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jun 2 16:53:15 2009 +0200
+
+ mpc512x: Fix PSC divisor calculation for baudrate setting
+
+ The wrong input frequency was used in serial_setbrg(). This patch fixes
+ this by using ips_clk as input frequency for the PSC baudrate generator.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 52568c3654b2b257016d52167805ae132faac14e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:46 2009 +0200
+
+ MPC512x: add support for ARIA board
+
+ ARIA is a MPC5121E based COM Express module by Dave/DENX.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit 3b74e7ec58e2cc352b0a396a614065cfeb8d138f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:45 2009 +0200
+
+ MPC512x: remove include/mpc512x.h
+
+ Move needed definitions (register descriptions etc.) from
+ include/mpc512x.h into include/asm-ppc/immap_512x.h.
+
+ Instead of using a #define'd register offset, use a function that
+ provides the PATA controller's base address.
+
+ All the rest of include/mpc512x.h are register offset definitions
+ which can be eliminated by proper use of C structures.
+
+ There are only a few register offsets remaining that are needed in
+ cpu/mpc512x/start.S; for these we provide cpu/mpc512x/asm-offsets.h
+ which is intended as a temporary workaround only. In a later patch
+ this file will be removed, too, and then auto-generated from the
+ respective C structs.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit a927e491b2a326c1e9c4313e3ce4042988422697
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:44 2009 +0200
+
+ MPC512x FEC: get rid of duplicated struct ethernet_regs
+
+ Use existing struct fec512x instead.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 843efb1192cc8fd4f904a23dbab4e0fe3e1c5bc2
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:43 2009 +0200
+
+ MPC512x: use I/O accessors instead of pointer accesses
+
+ This commit changes the MPC512x code to use I/O accessor calls (i.e.
+ out_*() and in_*()) instead of using deprecated pointer accesses.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit 19dc7e179268be148e550c36203208c662610d76
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:42 2009 +0200
+
+ MPC512x: add more hardware description to immap_512x.h
+
+ - add GPIO module description
+ - add Address Latch Timing Register description
+ - add IO Control Memory Map
+ - add FEC Memory Map
+
+ Also change board/freescale/mpc5121ads/mpc5121ads.c and
+ cpu/mpc512x/iopin.c as needed.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit 72601d04fdfdd4c7597afcf1f6aab654bd99366c
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:41 2009 +0200
+
+ Rename ads5121 board into mpc5121ads
+
+ We rename the board so we use a consistent name in U-Boot and in
+ Linux. Also, we use this opportunity to move the board into the
+ Freecale vendor directory.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit debf87415579c0f50aab9e0832976d4506babe0f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:40 2009 +0200
+
+ cpu/mpc512x/diu.c: fix warning: assignment from incompatible pointer type
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit 8b251263191ec554967dd1add6237c1ba7f7eb25
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:39 2009 +0200
+
+ cpu/mpc512x/pci.c: minor coding style cleanup
+
+ Get rid of variable declaration in the middle of the code.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit de26ef99bddbce4ed225f93afcf0bee99c3b6f87
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:38 2009 +0200
+
+ mpc512x: Move common files to share them by several boards
+
+ We will soon see several new MPC521x based boards added. This patch
+ moves files that are not board specific to a common directory so they
+ can be shared by all such ports. It also splits off common IDE code
+ into a new file, cpu/mpc512x/ide.c .
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit 03e069dc0a765d506f78a68319acf33d432e035b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 16 10:47:37 2009 +0200
+
+ mpc512x: change cpu/mpc512x/Makefile to use Kconfig style
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit a89c33db96a1e55319a286dd4c3c05ca64ac6bfd
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun May 24 17:06:54 2009 +0200
+
+ General help message cleanup
+
+ Many of the help messages were not really helpful; for example, many
+ commands that take no arguments would not print a correct synopsis
+ line, but "No additional help available." which is not exactly wrong,
+ but not helpful either.
+
+ Commit ``Make "usage" messages more helpful.'' changed this
+ partially. But it also became clear that lots of "Usage" and "Help"
+ messages (fields "usage" and "help" in struct cmd_tbl_s respective)
+ were actually redundant.
+
+ This patch cleans this up - for example:
+
+ Before:
+ => help dtt
+ dtt - Digital Thermometer and Thermostat
+
+ Usage:
+ dtt - Read temperature from digital thermometer and thermostat.
+
+ After:
+ => help dtt
+ dtt - Read temperature from Digital Thermometer and Thermostat
+
+ Usage:
+ dtt
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 94796d8544d4248028141bad11c6a74b840e9d6e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun May 24 19:17:29 2009 +0200
+
+ Make "usage" messages more helpful.
+
+ In case of incorrect command invocations U-Boot used to print pretty
+ useless "usage" messages, for example:
+
+ => nand markbad
+ Usage:
+ nand - NAND sub-system
+
+ In the result, the user would have to run the "help" command to get
+ the (available) information about correct command usage. Change this,
+ so that this information gets always printed.
+
+ Note that this changes the user interface of all commands, but
+ hopefully to the better.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4c94f6c54bbc4dc5f418da01d8ec01e2adf636be
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun May 24 02:26:19 2009 -0400
+
+ nvedit: speed up printing of environment
+
+ The printing code would check the same environment byte multiple times and
+ write to the console one byte at a time. For some devices (such as the
+ Blackfin JTAG console which operates in 8 bytes at a time), this is pretty
+ damned slow. So create a small 16 byte buffer to fill up and send to puts
+ as needed. In the process, unify the different print functions, shrink
+ the resulting code (source and compiled), and avoid excess env reads as
+ those too can be somewhat expensive depending on the board.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 3112030a430553768de5d30c05bedf8710784452
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 22 19:28:52 2009 +0200
+
+ config.mk: remove un-needed REMOTE_BUILD check
+
+ as $(obj) is empty when in tree build
+
+ %.s: %.S
+ $(CPP) $(AFLAGS) -o $@ $<
+
+ and
+
+ $(obj)%.s: %.S
+ $(CPP) $(AFLAGS) -o $@ $<
+
+ are the same
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Acked-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 651351fe980b20217b014b9a888398f18d77951c
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Wed May 20 07:55:41 2009 -0500
+
+ FAT replace compare_sign with strncmp.
+
+ The static function compare_sign is only used to compare the fs_type string
+ and does not do anything more than what strncmp does.
+
+ The addition of the trailing '\0' to fs_type, while legal, is not needed
+ because the it is never printed out and strncmp does not depend on NULL
+ terminated strings.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit ecb1dc892297d5d99876907328fed732feefeab2
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed May 20 04:35:14 2009 -0400
+
+ Add support for Linux-like kallsysms
+
+ The kernel stores address<->symbol names in it so things can be decoded at
+ runtime. Do it in U-Boot, and we get nice symbol decoding when crashing.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 36c9169aa6f79ddf604a3bca64e145654f94888b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun May 17 16:01:54 2009 +0200
+
+ cmd_mtdparts.c: allow to omit definitions for default settings
+
+ There is actually no good reason to enforce that all board
+ configuations must define default settings for "mtdids" and
+ "mtdparts". Actually this may be difficult to handle, especially on
+ boards where different sizes of flash chips can be fit, so there is no
+ real "default" partition map for all boards.
+
+ Lift this arbitrary limitation.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 864aa034f3a0e10ce710e8bbda171df3cab59414
+Author: Stefan Roese <sr@denx.de>
+Date: Tue May 12 14:31:56 2009 +0200
+
+ cmd_mtdparts: Move to common handling of FLASH devices via MTD layer
+
+ This patch removes all references to the direct CFI FLASH interface
+ (via flash_info[]). Now that all FLASH types currently handled in
+ mtdparts are available (if selected, see below) via the MTD infrastructure.
+ This is NOR, NAND and OneNAND right now. This can be achieved by defining
+ the following options:
+
+ CONFIG_MTD_DEVICE (for all FLASH types)
+
+ plus
+
+ CONFIG_FLASH_CFI_MTD (for NOR FLASH)
+
+ So we need to add those defines to the board config headers currently
+ using the mtdparts commands. This is done via another patch, so
+ we shouldn't break mtdparts compatibility.
+
+ One big advantage from this solution is that the cmd_mtdparts.c is
+ *much* cleaner now. Lot's of #ifdef's are removed and the code itself
+ is smaller. Additionally the newly added MDT concatenation feature
+ can new be used via the mtdparts infrastructure and therefor via
+ UBI etc.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Ladislav Michl <ladis@linux-mips.org>
+ Cc: Scott Wood <scottwood@freescale.com>
+
+commit d558107c18708050f05b6639b2192efb67c905dc
+Author: Stefan Roese <sr@denx.de>
+Date: Tue May 12 14:31:18 2009 +0200
+
+ mtd: Introduce CONFIG_MTD_DEVICE to select compilation of mtdcore.o
+
+ This new define enables mtdcore.c compilation and with this we can
+ select the MTD device infrastructure needed for the reworked mtdparts
+ command.
+
+ We now have the 2 MTD infrastructure defines, CONFIG_MTD_DEVICE and
+ CONFIG_MTD_PARTITIONS. CONFIG_MTD_DEVICE is needed (as explained above)
+ for the "mtdparts" command and CONFIG_MTD_PARTITIONS is needed for UBI.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Scott Wood <scottwood@freescale.com>
+
+commit 942556a92a8c1eb1bd76584a5143f6f57dcb25ad
+Author: Stefan Roese <sr@denx.de>
+Date: Tue May 12 14:32:58 2009 +0200
+
+ mtd: MTD related config header changes (mtdparts command)
+
+ By changing the cmd_mtdparts to only use the MTD infrastructure and
+ not the direct interface to the CFI NOR FLASH driver we now need
+ to add the MTD infrastructure to all boards using those mtdparts
+ commands. This patch adds those components:
+
+ CONFIG_MTD_DEVICE (for all FLASH types)
+
+ plus
+
+ CONFIG_FLASH_CFI_MTD (for NOR FLASH)
+
+ To all board maintainers: Please test this on your platforms and
+ report any problems/issues found. Thanks.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Wolfgang Denk <wd@denx.de>
+ Cc: Ron Madrid <info@sheldoninst.com>
+ Cc: Georg Schardt <schardt@team-ctech.de>
+ Cc: Michal Simek <monstr@monstr.eu>
+ Cc: Ladislav Michl <ladis@linux-mips.org>
+ Cc: Martin Krause <martin.krause@tqs.de>
+ Cc: Gary Jennejohn <garyj@denx.de>
+ Cc: Ricardo Ribalda <ricardo.ribalda@uam.es>
+
+commit 8d2effea23e938631126a7888008a0637e13b389
+Author: Stefan Roese <sr@denx.de>
+Date: Mon May 11 16:03:55 2009 +0200
+
+ mtd: Update MTD infrastructure to support 64bit device size
+
+ This patch brings the U-Boot MTD infrastructure in sync with the current
+ Linux MTD version (2.6.30-rc3). Biggest change is the 64bit device size
+ support and a resync of the mtdpart.c file which has seen multiple fixes
+ meanwhile.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Scott Wood <scottwood@freescale.com>
+ Cc: Kyungmin Park <kmpark@infradead.org>
+
+commit 0a57265533c412adf6024f4b4955141f4346b2b9
+Author: Stefan Roese <sr@denx.de>
+Date: Tue May 12 14:29:39 2009 +0200
+
+ mtd: Add MTD concat support to concatenate multiple MTD NOR devices
+
+ This patch adds concatenation support to the U-Boot MTD infrastructure.
+ By enabling CONFIG_MTD_CONCAT this MTD CFI wrapper will concatenate
+ all found NOR devices into one single MTD device. This can be used by
+ e.g by UBI to access a partition that spans over multiple NOR chips.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 55e0ed6078b10b0d425b6a0677f38a015c277df6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Apr 25 14:57:52 2009 +0200
+
+ make MODEM SUPPORT generic instead of duplicate it
+
+ and fix comment
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+ Adjusted Copyright message.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a30f519bd0cde78ba46b424314de94fdab863726
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Tue Jun 2 20:53:56 2009 -0500
+
+ ZOOM2 detect the version of the zoom2 board at runtime.
+
+ There are currently 3 versions of the zoom2 board.
+ The production board, that is currently being released.
+ The beta board, similar in form to the production board but not released.
+ The alpha board, a set of PCBs with a very limited circulation.
+
+ GPIO 94 is used to determine the version of the board. If GPIO 94 is clear,
+ the board is a production board, otherwise it is a beta board.
+
+ The alpha board will likely be mistaken for a beta board. An alpha board
+ was unavailible for testing.
+
+ This has been tested on the beta and production boards.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 718763c4745fd3d987a5576d2a67325e9444f9d4
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Wed Jun 3 01:53:57 2009 -0500
+
+ Beagle Convert the board version detection to use the OMAP3 GPIO interface.
+
+ There is no new functionality in the change.
+
+ This change is a conversion from the using raw register access to using
+ the OMAP3 GPIO API described in doc/README.omap3.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 7caa13fdd2d3dc957b4e0a228810a3a4a8ba499b
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Wed Jun 3 01:53:55 2009 -0500
+
+ Fix a typo in the instructions on using omap3's gpio interface.
+
+ Using the example for reading a gpio, shows the problem.
+ NULL should be the gpio number.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 0c9520efd651ce13451654a35307ec87d4a13a69
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 29 18:57:32 2009 -0500
+
+ ZOOM2 Define GPIO banks used.
+
+ Enable the function and interface clocks for banks 2,3,5 and 6.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 708cfb74b7c6df9c37d3c48988a154be79daefeb
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 29 18:57:31 2009 -0500
+
+ OMAP3 Turn on the GPIO bank clocks
+
+ The function and interface clocks for each GPIO bank, except the first, must
+ be explicitly turned on. These are controlled by the config level defines
+ CONFIG_OMAP3_GPIO_n where n is from 2 to 6.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+ Acked-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 59272620c24549b5bcd03c94ba12ec302c1476a2
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Thu Mar 26 15:26:01 2009 -0400
+
+ Coldfire M5271: Activate u-boot system timer interrupt.
+
+ This patch assigns the u-boot system timer interrupt to
+ interrupt level 3, priority 6. Without this patch the interrupt
+ will be a level 0, priority 0, which disables it and cause
+ u-boot functions that relies on the timer (e.g. sleep command)
+ to never return.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit dc26965ad3acdfb18780361d77a276b2843a90af
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Mon Mar 23 13:35:48 2009 -0400
+
+ Compier warning cleanup
+
+ Follow up to git commit: 19b5b533ccd522abeb501d510750693c35e20456
+
+ Cleanup on compiler warnings on unused variables now that
+ bd->bi_enetaddr is no longer used.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit 42a83765d54f042b4079e05a3438789542429981
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Fri Mar 20 15:30:10 2009 -0400
+
+ Adds WATCHDOG_RESET() function call to lib_m68k dtimer_interrupt.
+
+ Ported from lib_ppc/interrupts.c, this adds the ability for
+ the coldfire system timer to auto-reset the watchdog when
+ dtimer_interrupts is called.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit a24d96e40e1ca66dde6e6c158e7ecffafc5a2199
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Sun May 31 14:53:20 2009 +0200
+
+ arch_misc_init support for ARM architectures
+
+ This patch is required for Kirkwood support
+ may be used by other ARM architectures
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit b2403589b4d9996394bafc73eca3623f43ac2c31
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 31 14:53:18 2009 +0200
+
+ at91: move cpu info print to cpu
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit b32e189079fa16e1b647ac6b949fd4e0a9435343
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 31 12:44:46 2009 +0200
+
+ at91: move cpu name define to arm/arch/ cpu header
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 5bb59b3c906ee01adfaac9565443e5236a793079
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 31 12:44:45 2009 +0200
+
+ at91: extract reset from timer
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 61cf851b09cf8b67009ec11fc47c16add6b142a5
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 31 12:44:43 2009 +0200
+
+ omap24xx: rename reset file
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun May 31 12:44:42 2009 +0200
+
+ OMAP3: Fix CKE1 MUX setting to allow self-refresh
+
+ The Beagle rev Cx and Overo boards are using both SDRC CSes. The MUX
+ setting is needed for the second CS clock signal to allow the 2 RAM
+ parts to be put in self-refresh correctly. This also works on rev B
+ Beagle boards with 128M of RAM.
+
+ From: Steve Sakoman <steve@sakoman.com>
+ From: Jean Pihet <jpihet@mvista.com>
+ Signed-off-by: Jean Pihet <jpihet@mvista.com>
+ Signed-off-by: Steve Sakoman <steve@sakoman.com>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 3962c4f9fc4482a6547f3c3d3d5e986e625abb8a
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun May 31 12:44:41 2009 +0200
+
+ OMAP3: Zoom2: Enable Board and CPU info
+
+ With other OMAP3 boards we recently switched to CPU and Board
+ info API. From parallel merge, this is missing for Zoom2.
+ Enable it for Zoom2, too.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+ Acked-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 83ae698ff26b81b569ca32f7f2b008ad0da15e66
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun May 31 12:44:39 2009 +0200
+
+ ZOOM2 Add led support.
+
+ This patch controls the large LED on the top left of the zoom2.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 660888b7fb8840ce169dcd2589e49ab44c46b87b
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Sun May 31 12:44:37 2009 +0200
+
+ ZOOM2 Add serial support.
+
+ Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board.
+ The default serial is from the USB connector on left side of the debug board.
+ The USB connector will produce 2 of the 4 UARTS. On your host pick the first
+ enumeration.
+
+ The details of the setting of the serial gpmc setup are not available.
+ The values were provided by another party.
+
+ The serial port set up is the same with Zoom1.
+ Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow.
+
+ The kernel bootargs are
+ console=ttyS3,115200n8
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 3ea201b016ab259a5ac8824af767569522768c47
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun May 31 12:44:27 2009 +0200
+
+ lh7a40x: move serial driver to drivers/serial
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 379be585eb2343d8814a5cee5fb3da930d846bee
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 16 22:48:46 2009 +0200
+
+ pxa: move serial driver to drivers/serial
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit ad7e8aac6920f8b8a85b3cc2e93bca7458e99aa1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 9 13:21:19 2009 +0200
+
+ arm: remove cpu_init
+
+ move s3c44b0 to arch_cpu_init and as noone use cpu_init remove it
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c358d9c3f16571e8f825e81b75eaf32e228cb669
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 9 13:21:18 2009 +0200
+
+ arm: unify interrupt init
+
+ all arm init the IRQ stack the same way
+ so unify it in lib_arm/interrupts.c and then call arch specific interrupt init
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 10a451cd57cffbca875c97bbd8929059c5627ec6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 8 20:24:12 2009 +0200
+
+ arm: unify linker script
+
+ all arm boards except a few use the same cpu linker script
+ so move it to cpu/$(CPU)
+
+ that could be overwrite in following order
+ SOC
+ BOARD
+ via the corresponding config.mk
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9475c63c7855edd863c93a9bb0f4b8e240d9d212
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 16 10:02:05 2009 +0200
+
+ afeb9260: fix macb device init
+
+ uses PA10, PA11 for ETX2 and ETX3.
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1bbae2b816d4ed38db2ebf42166a973b1ffc0df7
+Author: Stefan Roese <sr@denx.de>
+Date: Wed May 27 10:34:32 2009 +0200
+
+ ppc4xx: Remove PCI async bootup message if PCI is not used
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a3455c00510c5abf1e91743c4a02d8393b6df18d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri May 15 09:19:52 2009 +0200
+
+ TQM834x: use buffered writes to accelerate writing to flash
+
+ Also enable display of 'E'mpty sectors in "flinfo" output.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 4681e673a51c48f4c096aa3c8fae5e6217ffd58d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu May 14 23:18:34 2009 +0200
+
+ TQM834x: add FDT support
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 929b79a0b5e48303ab04aae9d0abceb0c707f111
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu May 14 23:18:33 2009 +0200
+
+ TQM834x: fix environment size; add redundant env.
+
+ Also reserve more space for U-Boot as it will probably grow soon.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 2ae0f35fd60c7345446835b95a4daff356e1f031
+Author: Thomas Lange <thomas@corelatus.se>
+Date: Sun May 3 20:07:33 2009 +0200
+
+ ARM DaVinci: Reset with watchdog enabled
+
+ Once the Davinci watchdog has been enabled, the timeout
+ value cannot be changed. If the timeout in use is long,
+ it can take a long time for card to reset. By writing
+ an invalid service key, we can trigger an immediate reset.
+
+ Signed-off-by: Thomas Lange <thomas@corelatus.se>
+
+commit 6cc7ba9ed43106946aa9aa868302aa2faf1d17be
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri May 15 10:07:43 2009 +0200
+
+ video: Add an option to skip video initialization
+
+ This patch adds an option to skip the video initialization on for all
+ video drivers. This is needed for the CPCI750 which can be built as
+ CPCI host and adapter/target board. And the adapter board can't
+ access the video cards located on the CompactPCI bus.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Anatolij Gustschin <agust@denx.de>
+
+ Rebased against simplifying patch.
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f62f64692ff7f6226ad221d5df6487ea5ef39bdd
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri May 15 10:07:42 2009 +0200
+
+ drv_video_init(): simplify logic
+
+ Simplify nesting of drv_video_init() and use a consistent way of
+ indicating failure / success. Before, it took me some time to realize
+ which of the returns was due to an error condition and which of them
+ indicated success.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Anatolij Gustschin <agust@denx.de>
+
+commit 1699da6297b8c22da16cf85b3c79192f1a6d70ca
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed May 13 21:01:13 2009 +0200
+
+ at91: regroup IP hw init in one file per soc
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 28b00324becf3552134ae1e086509dc9c3d6e932
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Fri May 15 23:48:37 2009 +0200
+
+ dm355 evm support
+
+ Initial U-Boot support for the DaVinci DM355 EVM. This is a board
+ from Spectrum Digital. Board docs include schematic and firmware
+ for its microcontroller:
+
+ http://c6000.spectrumdigital.com/evmdm355/revd/
+
+ Most of the DM355 chip is fully documented by TI, the most notable
+ exception being the MPEG/JPEG coprocessor (programmable using codecs
+ available at no cost from TI), which is omitted from its DM335 sibling:
+
+ http://focus.ti.com/docs/prod/folders/print/tms320dm355.html
+
+ This version can boot from the on-board DM9000 Ethernet chip, after
+ being loaded (from NAND, MMC/SD, or UART). In the near future, NAND
+ and USB support could be added ... NAND support is being held back
+ until the support for the 4-bit ECC hardware is ready.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit 136cf92dc9e84c9a1bf567f1fe741092bf765495
+Author: Sanjeev Premi <premi@ti.com>
+Date: Fri May 15 23:48:37 2009 +0200
+
+ OMAP3EVM: Set default bootfile
+
+ The current configuration doesn't define default
+ bootfile; leading to this warning at execution:
+
+ OMAP3_EVM # dhcp
+ ...
+ ...
+ DHCP client bound to address 192.168.1.11
+ *** Warning: no boot file name; using 'AC18BE16.img'
+ TFTP from server 0.0.0.0; our IP address is 192.168.1.11;
+ sending through gateway 192.168.1.1
+ Filename 'AC18BE16.img'.
+ Load address: 0x82000000
+ Loading: *
+ TFTP error: 'File not found' (1)
+
+ Signed-off-by: Sanjeev Premi <premi@ti.com>
+
+commit 1a09d05abfc6d4d4f1fce9f6bd0275bd1c08d4f5
+Author: s-paulraj@ti.com <s-paulraj@ti.com>
+Date: Fri May 15 23:48:36 2009 +0200
+
+ ARM DaVinci: Minor Updates to base addresses
+
+ Patch adds base addresses for DaVinci DM365. Updated patches for DM365
+ will be posted soon.
+
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit de193e8e369f5f029ed3b6e2fc60341098eea766
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 15 23:48:36 2009 +0200
+
+ ZOOM2 Add support for debug board detection.
+
+ The logicpd web site is a good source for general information on this board.
+ Please start looking here if the below links are broken.
+ http://www.logicpd.com
+
+ This is a pdf of the product
+ http://www.logicpd.com/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Brief.pdf
+
+ This is a pdf of the product quick start guide.
+ The debug board is described here.
+ http://support.logicpd.com/downloads/1165/
+
+ This is a wiki showing the debug board in use
+ https://omapzoom.org/gf/project/omapzoom/wiki/?pagename=GettingStartedWithZoomII_AKA_OMAP34XII_MDP
+
+ The zoom2 has an auxillary board that contains the serial, net, jtag and
+ battery simulator. This change supports a runtime check if the debug board is
+ connected.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 0c872ecd01d6782ae9d37b6eb721404a4a48f356
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 15 23:48:36 2009 +0200
+
+ OMAP3 Port kernel omap gpio interface.
+
+ Port version 2.6.27 of the linux kernel's omap gpio interface to u-boot.
+ The orignal source is in linux/arch/arm/plat-omap/gpio.c
+
+ See doc/README.omap3 for instructions on use.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 376aee78dd66ae0dc4ce496cbe93ecc80aaad48e
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 15 23:48:36 2009 +0200
+
+ ZOOM2 Add initial support for Zoom2
+
+ Zoom2 is a new board from Texas Instruments and LogicPD
+
+ The logicpd web site is a good source for general information on this board.
+ Please start looking here if the below links are broken.
+ http://www.logicpd.com
+
+ This is a pdf of the product
+ http://www.logicpd.com/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Brief.pdf
+ This is the product description web page
+ http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap34x-ii-mdp
+
+ This patch provides a zoom2 base target by copying zoom1 and by making some
+ obvious changes.
+
+ To configure, run
+ make omap3_zoom2_config
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 53925acf1b5c1a1e6230cda2697640cd05bd1104
+Author: Sandeep Paulraj <s-paulraj@ti.com>
+Date: Fri May 15 23:48:33 2009 +0200
+
+ ARM DaVinci:Consolidate common u-boot.lds
+
+ The u-boot.lds is common for all DaVinci boards. The patch removes
+ multiple instances and moves the u-boot.lds to /cpu/arm926ejs/davinci
+ folder. This addresses one of the comments i received while submitting
+ patches for DM3xx
+
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 68a531fd465f5c0b3d373e0010afed32e88d37c4
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 15 23:47:52 2009 +0200
+
+ OMAP Consolidate common u-boot.lds to cpu layer.
+
+ The u-boot.lds file is common for all omap boards.
+ Move a cleaned up version to the cpu layer and add makefile logic to use it.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 65a76d4f947a193e57bb8f8093c481f27e059f8f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:47:14 2009 +0200
+
+ arm/dcc: add xscale support
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 66e8f9da6879fe37f3159b3997bff874842dc51d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:47:14 2009 +0200
+
+ arm/dcc: use static support to allow to use it at anytime
+
+ the dcc can be used at the start of the cpu
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7893aa1eb6f52c3957efc301b436f1fa11e91a00
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:47:13 2009 +0200
+
+ ARM: Update mach-types
+
+ update against linux v2.6.29
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 2907798926ee932f453ac8538e7a6c05c18428a5
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:47:13 2009 +0200
+
+ arm920/926/926: remove non needed header
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 269dfea017b09c5a999d3053d00505c19789c350
+Author: David Brownell <david-b@pacbell.net>
+Date: Fri May 15 23:47:13 2009 +0200
+
+ davinci dm6446evm NAND update
+
+ This updates the optional (non-default!) NAND support for the
+ DaVinci DM6446 EVM:
+
+ - include MTD partitioning, defaulting to what Linux uses
+
+ - use a flash-based BBT, which among other things speeds bootup
+
+ This matches code that's now queued for mainline Linux, and might
+ even merge in an upcoming 2.6.30-rc; and the MTIDS are set up so
+ that the U-Boot $mtdparts environment variable can be passed as-is
+ on the kernel command line as a cmdlinepart override.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit 7a4f511b59f08f51dde4ceacbd45f49b8bf2a5cc
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Fri May 15 23:47:12 2009 +0200
+
+ davinci: display correct clock info
+
+ Move the clock-rate dumping code into the cpu/.../davinci area
+ where it should have been, enabled by CONFIG_DISPLAY_CPUINFO,
+ updating the format and showing the DSP clock (where relevant).
+
+ Switch boards to use the cpuinfo() hook for this stuff.
+
+ Remove a few now-obsolete PLL #defines.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit daea928829098cae3c9ec6b801e52ba616725034
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 15 23:47:12 2009 +0200
+
+ ZOOM1 Remove more legacy NAND defines.
+
+ These legacy NAND defines are no longer needed by this target.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 65fd21c80fcaca2bbfe3ab06ab6ac68207408078
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 15 23:47:12 2009 +0200
+
+ LED Add documentation describing the status_led and colour led API.
+
+ This document describes the u-boot status LED API.
+ This allows common u-boot commands to use a board's leds to
+ provide status for activities like booting and downloading files.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit 7cdf804f34378b910b4c4edd2dac7e3ca61c0825
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Fri May 15 23:47:12 2009 +0200
- Revert "SMC911x driver fixed for NFS boot"
+ ARM Add blue colour LED to status_led.
- This reverts commit ca9c8a1e10fac01e6a1129f82a7ce18bd818fa43,
- which causes compile warnings ("large integer implicitly truncated
- to unsigned type") on all systems that use this driver. The warning
- results from passing long constants (TX_CFG, RX_CFG) into
- smc911x_set_mac_csr() which is declared to accept "unsigned
- character" arguments only.
+ There is exiting support for red,yellow,green but no blue.
+ The main LED on the zoom2 is a blue LED.
- Being close to a release, with nobody available to actually test the
- code or the suggested fixes, it seems better to revert the patch.
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit b54384e3ba6b5535751f317fcd3940a53eed0d3a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:47:02 2009 +0200
+
+ arm: timer and interrupt init rework
+
+ actually the timer init use the interrupt_init as init callback
+ which make the interrupt and timer implementation difficult to follow
+
+ so now rename it as int timer_init(void) and use interrupt_init for interrupt
+
+ btw also remane the corresponding file to the functionnality implemented
+
+ as ixp arch implement two timer - one based on interrupt - so all the timer
+ related code is moved to timer.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 5b4bebe1d20c4f2b70d48b06aed1016785efcc25
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:45:22 2009 +0200
+
+ OMAP3: Reorganize Makefile style
+
+ Reformat COBJS handling.
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit b1966982718347f67317b3fb356439743ca68a37
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:45:22 2009 +0200
+
+ OMAP3: Remove dublicated interrupt code
+
+ Remove duplicated interrupt code. Original, identical code can be found
+ in lib_arm/interrupts.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit ac7260a4190315eba4a6e526c764f6cad0bbf8c5
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:45:22 2009 +0200
+
+ at91rm9200: move reset code to reset.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 2c75c78d94574ee996db2aa9b511258519471dd6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:45:22 2009 +0200
+
+ ixp/interrupts: Move conditional compilation to Makefile
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8fc3bb4b0603516ad641e2de252a400b85fd869b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:45:20 2009 +0200
+
+ arm: cleanup remaining CONFIG_INIT_CRITICAL
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c20e28f49aaf38c7dede46d8f8fe8234fe90822c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri May 15 23:45:12 2009 +0200
+
+ arm946es: remove non used timer
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f1d944e30eb8ff89080fa03fb98d8fb5c82388d2
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Fri May 15 23:44:09 2009 +0200
+
+ davinci: add basic dm355/dm350/dm335 support
+
+ Add some basic declarations for DaVinci DM355/DM350/DM335 support,
+ keyed on CONFIG_SOC_DM355. (DM35X isn't quite right because the
+ DM357 is very different; while the DM355 is like a DM355 without
+ the MPEG/JPEG coprocessor).
+
+ These have different peripherals than the DM6446, and some of
+ the peripherals are at different addresses. Notably for U-Boot,
+ there's no EMAC, and the NAND controller address is different
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit bd36fdc146654f9de4e2ad346126e6bd2990fb19
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Fri May 15 23:44:09 2009 +0200
+
+ davinci: fix dm644x buglets
+
+ Fix two buglets in the dm644x support: don't set two must-be-zero
+ bits in the UART management register; and only include the I2C hooks
+ if the I2C driver is being included.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit f79043681ff44bae435c06f830e51e1546db7e19
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Fri May 15 23:44:08 2009 +0200
+
+ davinci: split out some dm644x-specific bits from psc
+
+ Split out DaVinci DM6446-specific bits from more generic bits:
+
+ - Add a CONFIG_SOC_DM644X. All current boards use DM6446 chips;
+ DM6443 and DM6441 chips differ in available peripherals.
+
+ - Move most DM644X-specific bits from psc.c to a new dm644x.c file,
+ which is conditionally built. It provides device-specific setup.
+
+ Plus minor coding style and comment updates with respect to the PSC.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit 48ef5729555f41f51618b6a3016ac5c53c7c75dc
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Fri May 15 23:44:08 2009 +0200
+
+ davinci: cpu-specific build uses conditional make syntax
+
+ Update cpu/arm926ejs/davinci/Makefile to use COBJ-y type syntax.
+ Add the first conditional: for EMAC driver support. Not all
+ chips have an EMAC; and boards might not use it, anyway.
+
+ This doesn't touch PHY configuration; that should eventually
+ become conditional too.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit 7b7808ae6dace59287f565e9323cda7b098a5612
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Fri May 15 23:44:06 2009 +0200
+
+ davinci: move psc support board-->cpu
+
+ Move DaVinci PSC support from board/* to cpu/* where it belongs.
+ The PSC module manages clocks and resets for all DaVinci-family
+ SoCs, and isn't at all board-specific.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit 84f7411cb901b8df2391cf7e967ad0737f6194aa
+Author: David Brownell <david-b@pacbell.net>
+Date: Tue Apr 14 08:52:58 2009 -0700
+
+ DaVinci now respects SKIP_LOWLEVEL_INIT
+
+ Don't needlessly include lowlevel init code; that's only really
+ needed with boot-from NOR (not boot-from-NAND). The 2nd stage
+ loader (UBL) handles that before it loads U-Boot.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit 641e0925e4bf7adf8e2e04e3ad81b840fd71cadd
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Sun Apr 12 22:49:26 2009 -0700
+
+ DaVinci Ethernet cleanup
+
+ Chips without the EMAC controller won't need the utilities
+ it uses to read an Ethernet address from EEPROM; so don't
+ include them needlessly.
+
+ Use is_valid_ether() to validate the address from EEPROM.
+ All-zero addresses aren't the only invalid addresses.
+ A fully erased EEPROM returns all-ones, also invalid...
+
+ Switch those Ethernet utilities to use "%pM" for printing
+ MAC addresses; and not say ROM when they mean EEPROM.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit c790b04d230363d03939dc008bcc80f3ba4de1ae
+Author: Stefan Roese <sr@denx.de>
+Date: Mon May 11 15:50:12 2009 +0200
+
+ lib_arch/board.c: Move malloc initialization before flash_init()
+
+ This patch moves the malloc initialization before calling flash_init().
+ Upcoming changes to the NOR FLASH common CFI driver with optional
+ MTD infrastructure and MTD concatenation support will call malloc().
+ And nothing really speaks against enabling malloc just a little earlier
+ in the boot stage. Some architectures already enable malloc before
+ calling flash_init() so they don't need any changes here.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Wolfgang Denk <wd@denx.de>
+ Cc: Mike Frysinger <vapier@gentoo.org>
+ Cc: Scott McNutt <smcnutt@psyent.com>
+ Cc: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+ Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ Cc: Daniel Hellstrom <daniel@gaisler.com>
+ Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: John Rigby <jcrigby@gmail.com>
+
+commit d873133f2ba9bd613d5f6552c31cc70fb13f15d3
+Author: Stefan Roese <sr@denx.de>
+Date: Mon May 11 13:46:14 2009 +0200
+
+ ppc4xx: Add Sequoia RAM-booting target
+
+ This patch adds another build target for the AMCC Sequoia PPC440EPx
+ eval board. This RAM-booting version is targeted for boards without
+ NOR FLASH (NAND booting) which need a possibility to initially
+ program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000)
+ configured to setup the SDRAM, this debugger can load this RAM-
+ booting image to the target address in SDRAM (in this case 0x1000000)
+ and start it there. Then U-Boot's standard NAND commands can be
+ used to program the NAND FLASH (e.g. "nand write ...").
+
+ Here the commands to load and start this image from the BDI2000:
+
+ 440EPX>reset halt
+ 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin
+ 440EPX>go 0x1000000
+
+ Please note that this image automatically scans for an already
+ initialized SDRAM TLB (detected by EPN=0). This TLB will not be
+ cleared. This TLB doesn't need to be TLB #0, this RAM-booting
+ version will detect it and preserve it. So booting via BDI2000
+ will work and booting with a complete different TLB init via
+ U-Boot works as well.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 837db3d87f4bfe9261629fb4a1bb433506a3056a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed May 6 08:41:45 2009 -0400
+
+ tools/envcrc: add --binary option to export embedded env
+
+ The --binary option to envcrc can be used to export the embedded env as a
+ binary blob so that it can be manipulated/examined/whatever externally.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 18cc7afd9a153a66854af862d14ba01c5496cf07
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Tue Apr 28 16:50:53 2009 -0700
+
+ Enable CONFIG_NET_MULTI on all remaining PPC4xx boards
+
+ All in-tree PPC4xx boards now use CONFIG_NET_MULTI
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 70be6c2d40076f14062b892152649f9a62832fc9
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Apr 29 09:51:01 2009 +0200
+
+ 4xx: Add support for DP405 hardware variants
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit de47a34d4de1d007a8951efd072283516d580ffa
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Apr 29 09:51:00 2009 +0200
+
+ 4xx: Remove binary cpld bitstream from DP405 board
+
+ This patch removes the cpld binary bitstream that is
+ used by esd's cpld command on DP405 boards.
+
+ Because u-boot with an external cpld bitstream may not
+ take more space in flash than before the u-boot binary is
+ shrinked a little bit. Some unused featues have been
+ removed therefore.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 700d553fd3afe804086de8f73d95153315eb0c32
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Apr 29 09:50:59 2009 +0200
+
+ 4xx: Remove binary cpld bitstream from VOM405 board
+
+ This patch removes the cpld binary bitstream that is
+ used by esd's cpld command on VOM405 boards.
+
+ Because u-boot with an external cpld bitstream may not
+ take more space in flash than before the u-boot binary is
+ shrinked a little bit.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0bb10630364c48d9857cbf5353da609fc4dd6751
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Apr 29 09:50:58 2009 +0200
+
+ 4xx: Remove binary cpld bitstream from PMC405 board
+
+ This patch removes the cpld binary bitstream that is
+ used by esd's cpld command on PMC405 boards.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7cc635fb35f5b94e304fa2243d56758f57f6416b
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Apr 29 09:50:57 2009 +0200
+
+ 4xx: Remove binary cpld bitstream from CMS700 board
+
+ This patch removes the cpld binary bitstream that is
+ used by esd's cpld command on CMS700 boards.
+
+ Because u-boot with an external cpld bitstream may not
+ take more space in flash than before the u-boot binary is
+ shrinked a little bit. Some unused featues have been
+ removed therefore.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c1b2f79788deec75773b1d944d8aaf4a6d5baf9e
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Apr 29 09:50:56 2009 +0200
+
+ esd/common: extend cpld command with address parameter
+
+ This patch adds support for an address parameter to esd's
+ cpld command. This is in preparation to remove compiled-in
+ binary cpld (xsvf) bitstreams.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9166b776350d16460c7330bfb0a50154ea0a1903
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sat Apr 18 22:34:06 2009 -0500
+
+ cmd_i2c: Fix i2c help command output when CONFIG_I2C_MUX
+
+ When CONFIG_I2C_MUX was defined the output of 'help i2c' was not
+ correct, eg:
+
+ => help i2c
+ i2c bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes.
+ speed [speed] - show or set I2C bus speed
+ i2c dev [dev] - show or set current I2C bus
+ ...
+
+ It has been changed to:
+ i2c speed [speed] - show or set I2C bus speed
+ i2c bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes
+ i2c dev [dev] - show or set current I2C bus
+ ...
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 0a45a6357b02e5ce5bf899a60db09def6a129fee
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sat Apr 18 22:34:05 2009 -0500
+
+ cmd_i2c: Clean up trivial helper functions
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit e96ad5d3aba42f8ffe99f7cc5ec1bb9f21810035
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sat Apr 18 22:34:04 2009 -0500
+
+ cmd_i2c: Clean up i2c command argument parsing
+
+ argc and argv should only be modified once instead of once for
+ every i2c sub-command
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 0f89c54be92773b23d66ac401ba6acb6144100c3
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sat Apr 18 22:34:03 2009 -0500
+
+ i2c: Update references to individual i2c commands
+
+ The individual i2c commands imd, imm, inm, imw, icrc32, iprobe, iloop,
+ and isdram are no longer available so all references to them have been
+ updated to the new form of "i2c <cmd>".
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit d48eb5131d287f52bb85b4c58c8680a2e8e3b641
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sat Apr 18 22:34:02 2009 -0500
+
+ i2c: Remove deprecated individual i2c commands
+
+ The following individual I2C commands have been removed: imd, imm, inm,
+ imw, icrc32, iprobe, iloop, isdram.
+
+ The functionality of the individual commands is still available via
+ the 'i2c' command.
+
+ This change only has an impact on those boards which did not have
+ CONFIG_I2C_CMD_TREE defined.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 655b34a78adf60ef260981688837904208883ae9
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sat Apr 18 22:34:01 2009 -0500
+
+ i2c: Create common default i2c_[set|get]_bus_speed() functions
+
+ New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions
+ replace a number of architecture-specific implementations.
+
+ Also, providing default functions will allow all boards to enable
+ CONFIG_I2C_CMD_TREE. This was previously not possible since the
+ tree-form of the i2c command provides the ability to display and modify
+ the i2c bus speed which requires i2c_[set|get]_bus_speed() to be
+ present.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 8229e9c04f7019ddd76aea05d4dca044cbc9a34a
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sat Apr 18 22:34:00 2009 -0500
+
+ cm5200: Make function test command names more unique
+
+ Add "_test" to cm5200's function test command names to prevent
+ overlap with common, global function names. Originally, the
+ "do_i2c" function test command interfered with
+ common/cmd_i2c.c's "do_i2c" when CONFIG_I2C_CMD_TREE was defined.
+
+ The functions were also made static as they are not globally accessed.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit f0722ee762e8dada9d7f74ac2745e043f83aae85
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Apr 24 15:34:09 2009 -0500
+
+ tsi108_i2c: Add i2c_init() stub function
+
+ Add the i2c_init() function so that the tsi108_i2c.c driver fits
+ U-Boot's standard I2C API which is utilized by cmd_i2c.c
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 8d907e79bc9babb27396e34be54cfdc36ff62fb9
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Apr 24 15:34:08 2009 -0500
+
+ mpc7448hpc2: Add CONFIG_SYS_I2C_SPEED define
+
+ Add standard CONFIG_SYS_I2C_SPEED define for the mpc7448hpc2 so that
+ it can use the common 'i2c speed' command. Note that the I2C controller
+ utilized by the mpc7448hpc2 has a fixed speed and cannot be changed
+ dynamically.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit a056b1ce9e19b4d4ab3dd01c3f897dcd832cd37f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Apr 24 15:34:07 2009 -0500
+
+ Marvell: i2c cleanup
+
+ The following changes were made, primarily to bring the Marvell i2c
+ driver in line with U-Boot's current I2C API:
+ - Made i2c_init() globally accessible
+ - Made i2c_read() and i2c_write() return an integer
+ - Updated i2c_init() calls to pass in CONFIG_SYS_I2C_SLAVE in the
+ offhand chance someone adds slave support in the future
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 54afc6ee10c8cd09598d814d49e601359b005e49
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Apr 24 15:34:06 2009 -0500
+
+ cpci750: i2c cleanup
+
+ The following changes were made, primarily to bring the cpci750 i2c
+ driver in line with U-Boot's current I2C API:
+ - Made i2c_init() globally accessible
+ - Made i2c_read() and i2c_write() return an integer
+ - Updated i2c_init() calls to pass in CONFIG_SYS_I2C_SLAVE in the
+ offhand chance someone adds slave support in the future
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 9c90a2c8e87414007a016b7cd099ac1e32fd301b
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Apr 24 15:34:05 2009 -0500
+
+ i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE value
+
+ Many boards/controllers/drivers don't support an I2C slave interface,
+ however CONFIG_SYS_I2C_SLAVE is used in common code so provide a
+ default
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
commit e7563aff174f77aa61dab1ef5d9b47bebaa43702
Author: Kumar Gala <galak@kernel.crashing.org>
Ilko Iliev <iliev@ronetix.at>
+ PM9261 AT91SAM9261
PM9263 AT91SAM9263
Gary Jennejohn <garyj@denx.de>
Peter Tyser <ptyser@xes-inc.com>
+ XPEDITE5170 MPC8640
XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
armadillo ARM720T
+Stefano Babic <sbabic@denx.de>
+
+ polaris xscale
+ trizepsiv xscale
+
Dirk Behme <dirk.behme@gmail.com>
omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
modnet50 ARM720T (NET+50)
+Fabio Estevam <Fabio.Estevam@freescale.com>
+
+ mx31pdk i.MX31
+
Peter Figuli <peposh@etc.sk>
wepep250 xscale
+Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+
+ meesc ARM926EJS (AT91SAM9263 SoC)
+
Marius Gröger <mag@sysgo.de>
impa7 ARM720T (EP7211)
MPC8610HPCD \
MPC8641HPCN \
sbc8641d \
+ XPEDITE5170 \
"
#########################################################################
mx1ads \
mx1fs2 \
netstar \
- nmdk8815 \
+ nhk8815 \
+ nhk8815_onenand \
omap1510inn \
omap1610h2 \
omap1610inn \
imx31_phycore \
imx31_phycore_eet \
mx31ads \
+ mx31pdk \
+ mx31pdk_nand \
qong \
smdk6400 \
"
cmc_pu2 \
csb637 \
kb9202 \
+ meesc \
mp2usb \
m501sk \
+ pm9261 \
pm9263 \
"
innokom \
lubbock \
pleb2 \
+ polaris \
pxa255_idp \
+ trizepsiv \
wepep250 \
xaeniax \
xm250 \
sbc8641d_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
+XPEDITE5170_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc86xx xpedite5170 xes
+
#########################################################################
## 74xx/7xx Systems
#########################################################################
fi;
@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
+at91sam9263ek_norflash_config \
+at91sam9263ek_norflash_boot_config \
at91sam9263ek_nandflash_config \
at91sam9263ek_dataflash_config \
at91sam9263ek_dataflash_cs0_config \
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
+ elif [ "$(findstring norflash,$@)" ] ; then \
+ echo "#define CONFIG_SYS_USE_NORFLASH 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in NOR FLASH" ; \
else \
echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
fi;
+ @if [ "$(findstring norflash_boot,$@)" ] ; then \
+ echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... and boot from NOR FLASH" ; \
+ fi;
@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
at91sam9rlek_nandflash_config \
fi;
@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
+meesc_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91
+
+pm9261_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91
+
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
ap920t_config \
ap926ejs_config \
ap946es_config: unconfig
- @board/armltd/integratorap/split_by_variant.sh $@
+ @board/armltd/integrator/split_by_variant.sh ap $@
integratorcp_config \
cp_config \
cp922_config \
cp922_XA10_config \
cp1026_config: unconfig
- @board/armltd/integratorcp/split_by_variant.sh $@
+ @board/armltd/integrator/split_by_variant.sh cp $@
davinci_dvevm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci
netstar_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm925t netstar
-nmdk8815_config \
-nmdk8815_onenand_config: unconfig
+nhk8815_config \
+nhk8815_onenand_config: unconfig
@mkdir -p $(obj)include
@ > $(obj)include/config.h
@if [ "$(findstring _onenand, $@)" ] ; then \
echo "#define CONFIG_BOOT_ONENAND" >> $(obj)include/config.h; \
- $(XECHO) "... configured for OneNand Flash"; \
+ $(XECHO) "... configured to boot from OneNand Flash"; \
else \
- $(XECHO) "... configured for Nand Flash"; \
+ $(XECHO) "... configured to boot from Nand Flash"; \
fi
- @$(MKCONFIG) -a nmdk8815 arm arm926ejs nmdk8815 st nomadik
+ @$(MKCONFIG) -a nhk8815 arm arm926ejs nhk8815 st nomadik
omap1510inn_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
pxa255_idp_config: unconfig
@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
+polaris_config \
trizepsiv_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
+ @mkdir -p $(obj)include
+ @if [ "$(findstring polaris,$@)" ] ; then \
+ echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \
+ fi;
+ @$(MKCONFIG) -a trizepsiv arm pxa trizepsiv
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250
mx31ads_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
+mx31pdk_config \
+mx31pdk_nand_config : unconfig
+ @mkdir -p $(obj)include
+ @if [ -n "$(findstring _nand_,$@)" ]; then \
+ echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \
+ else \
+ echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \
+ echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h; \
+ fi
+ @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
+
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
some other boot loader or by a debugger which
performs these initializations itself.
+- CONFIG_PRELOADER
+
+ Modifies the behaviour of start.S when compiling a loader
+ that is executed before the actual U-Boot. E.g. when
+ compiling a NAND SPL.
Building the Software:
======================
#ifdef CONFIG_MACB
static void afeb9260_macb_hw_init(void)
{
+ unsigned long rstc;
+
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+ rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- AT91_RSTC_ERSTL | (0x0 << 8) |
+ (rstc) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
+++ /dev/null
-/integratorap/u-boot.lds
-/integratorcp/u-boot.lds
LIB = $(obj)lib$(BOARD).a
-COBJS := integratorap.o flash.o
-SOBJS := lowlevel_init.o
+SOBJS-y := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+COBJS-y := integrator.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-y += timer.o
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+COBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(COBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(SOBJS) $(COBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#ifdef CONFIG_PCI
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* arch number of Integrator Board */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+ gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
+#else
+ gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x00000100;
+
+ gd->flags = 0;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+ cm_remap(); /* remaps writeable memory to 0x00000000 */
+#endif
+
+ icache_enable ();
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PCI
+ pci_init();
+#endif
+ setenv("verify", "n");
+ return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+ {
+extern void dram_query(void);
+ unsigned long cm_reg_sdram;
+ unsigned long sdram_shift;
+
+ dram_query(); /* Assembler accesses to CM registers */
+ /* Queries the SPD values */
+
+ /* Obtain the SDRAM size from the CM SDRAM register */
+
+ cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+ /* Register SDRAM size
+ *
+ * 0xXXXXXXbbb000bb 16 MB
+ * 0xXXXXXXbbb001bb 32 MB
+ * 0xXXXXXXbbb010bb 64 MB
+ * 0xXXXXXXbbb011bb 128 MB
+ * 0xXXXXXXbbb100bb 256 MB
+ *
+ */
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
+
+ }
+#endif /* CM_SPD_DETECT */
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif
*/
#include <common.h>
-
-#ifdef CONFIG_PCI
#include <pci.h>
-#endif
-
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init (void);
-void ether__init (void);
-void peripheral_power_enable (void);
-
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
- printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* arch number of Integrator Board */
- gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- gd->flags = 0;
-
-#ifdef CONFIG_CM_REMAP
-extern void cm_remap(void);
- cm_remap(); /* remaps writeable memory to 0x00000000 */
-#endif
-
- icache_enable ();
-
- flash__init ();
- return 0;
-}
-
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_PCI
- pci_init();
-#endif
- setenv("verify", "n");
- return (0);
-}
/*
* Initialize PCI Devices, report devices found.
*/
-#ifdef CONFIG_PCI
#ifndef CONFIG_PCI_PNP
-
static struct pci_config_table pci_integrator_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ }
};
-#endif
+#endif /* CONFIG_PCI_PNP */
/* V3 access routines */
#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
hose->last_busno = pci_hose_scan (hose);
}
-#endif
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-#ifdef CONFIG_CM_SPD_DETECT
- {
-extern void dram_query(void);
- unsigned long cm_reg_sdram;
- unsigned long sdram_shift;
-
- dram_query(); /* Assembler accesses to CM registers */
- /* Queries the SPD values */
-
- /* Obtain the SDRAM size from the CM SDRAM register */
-
- cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
- /* Register SDRAM size
- *
- * 0xXXXXXXbbb000bb 16 MB
- * 0xXXXXXXbbb001bb 32 MB
- * 0xXXXXXXbbb010bb 64 MB
- * 0xXXXXXXbbb011bb 128 MB
- * 0xXXXXXXbbb100bb 256 MB
- *
- */
- sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
- gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
-
- }
-#endif /* CM_SPD_DETECT */
-
- return 0;
-}
-
-/* The Integrator/AP timer1 is clocked at 24MHz
- * can be divided by 16 or 256
- * and is a 16-bit counter
- */
-/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/
-static ulong timestamp; /* U-Boot ticks since startup */
-static ulong total_count = 0; /* Total timer count */
-static ulong lastdec; /* Timer reading at last call */
-static ulong div_clock = 256; /* Divisor applied to the timer clock */
-static ulong div_timer = 1; /* Divisor to convert timer reading
- * change to U-Boot ticks
- */
-/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
-
-#define TIMER_LOAD_VAL 0x0000FFFFL
-#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL)
-
-/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
- * - unless otherwise stated
- */
-
-/* starts a counter
- * - the Integrator/AP timer issues an interrupt
- * each time it reaches zero
- */
-int timer_init (void)
-{
- /* Load timer with initial value */
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
- /* Set timer to be
- * enabled 1
- * free-running 0
- * XX 00
- * divider 256 10
- * XX 00
- */
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
- total_count = 0;
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- div_timer = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
- div_timer /= div_clock;
-
- return (0);
-}
-
-/*
- * timer without interrupts
- */
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
-ulong get_timer (ulong base_ticks)
-{
- return get_timer_masked () - base_ticks;
-}
-
-void set_timer (ulong ticks)
-{
- timestamp = ticks;
- total_count = ticks * div_timer;
- reset_timer_masked();
-}
-
-/* delay x useconds */
-void udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- /* Convert to U-Boot ticks */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000000L);
-
- tmp = get_timer_masked(); /* get current timestamp */
- tmo += tmp; /* wake up timestamp */
-
- while (get_timer_masked () < tmo) { /* loop till event */
- /*NOP*/;
- }
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER; /* capture current decrementer value */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-/* converts the timer reading to U-Boot ticks */
-/* the timestamp is the number of ticks since reset */
-/* This routine does not detect wraps unless called regularly
- ASSUMES a call at least every 16 seconds to detect every reload */
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current count */
-
- if (now > lastdec) {
- /* Must have wrapped */
- total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
- } else {
- total_count += lastdec - now;
- }
- lastdec = now;
- timestamp = total_count/div_timer;
-
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
- udelay(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * Return the timebase clock frequency
- * i.e. how often the timer decrements
- */
-ulong get_tbclk (void)
-{
- return CONFIG_SYS_HZ_CLOCK/div_clock;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
--- /dev/null
+#!/bin/sh
+
+mkdir -p ${obj}include
+mkdir -p ${obj}board/armltd/integrator
+
+config_file=${obj}include/config.h
+
+if [ "$1" = "ap" ]
+then
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied " > ${config_file}
+echo " by Makefile target */" >> ${config_file}
+echo -n "#define CONFIG_INTEGRATOR" >> ${config_file}
+echo " /* Integrator board */" >> ${config_file}
+echo -n "#define CONFIG_ARCH_INTEGRATOR" >> ${config_file}
+echo " 1 /* Integrator/AP */" >> ${config_file}
+# ---------------------------------------------------------
+# Set the core module defines according to Core Module
+# ---------------------------------------------------------
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$2" = "" ]
+then
+ echo "$0:: No parameters - using arm_intcm"
+else
+ case "$2" in
+ ap7_config)
+ cpu="arm_intcm"
+ variant="unported core module CM7TDMI"
+ ;;
+
+ ap966)
+ cpu="arm_intcm"
+ variant="unported core module CM966E-S"
+ ;;
+
+ ap922_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T"
+ ;;
+
+ integratorap_config | \
+ ap_config)
+ cpu="arm_intcm"
+ variant="unspecified core module"
+ ;;
+
+ ap720t_config)
+ cpu="arm720t"
+ echo -n "#define CONFIG_CM720T" >> ${config_file}
+ echo " 1 /* CPU core is ARM720T */ " >> ${config_file}
+ variant="Core module CM720T"
+ ;;
+
+ ap922_XA10_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T_XA10"
+ echo -n "#define CONFIG_CM922T_XA10" >> ${config_file}
+ echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file}
+ ;;
+
+ ap920t_config)
+ cpu="arm920t"
+ variant="Core module CM920T"
+ echo -n "#define CONFIG_CM920T" >> ${config_file}
+ echo " 1 /* CPU core is ARM920T */" >> ${config_file}
+ ;;
+
+ ap926ejs_config)
+ cpu="arm926ejs"
+ variant="Core module CM926EJ-S"
+ echo -n "#define CONFIG_CM926EJ_S" >> ${config_file}
+ echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file}
+ ;;
+
+ ap946es_config)
+ cpu="arm946es"
+ variant="Core module CM946E-S"
+ echo -n "#define CONFIG_CM946E_S" >> ${config_file}
+ echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file}
+ ;;
+
+ *)
+ echo "$0:: Unknown core module"
+ variant="unknown core module"
+ cpu="arm_intcm"
+ ;;
+
+ esac
+fi
+
+case "$cpu" in
+ arm_intcm)
+ echo "/* Core module undefined/not ported */" >> ${config_file}
+ echo "#define CONFIG_ARM_INTCM 1" >> ${config_file}
+ echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file}
+ echo -n " /* CM may not have " >> ${config_file}
+ echo "multiple SSRAM mapping */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file}
+ echo -n " /* CM may not support SPD " >> ${config_file}
+ echo "query */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_REMAP " >> ${config_file}
+ echo -n " /* CM may not support " >> ${config_file}
+ echo "remapping */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_INIT " >> ${config_file}
+ echo -n " /* CM may not have " >> ${config_file}
+ echo "initialization reg */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file}
+ echo " /* CM may not have TCRAM */" >> ${config_file}
+ echo -n " /* May not be processor " >> ${config_file}
+ echo "without cache support */" >> ${config_file}
+ echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file}
+ echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file}
+ ;;
+
+ arm720t)
+ echo -n " /* May not be processor " >> ${config_file}
+ echo "without cache support */" >> ${config_file}
+ echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file}
+ echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file}
+ ;;
+esac
+
+else
+
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied " > ${config_file}
+echo " by Makefile target */" >> ${config_file}
+echo -n "#define CONFIG_INTEGRATOR" >> ${config_file}
+echo " /* Integrator board */" >> ${config_file}
+echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> ${config_file}
+echo " 1 /* Integrator/CP */" >> ${config_file}
+
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$2" = "" ]
+then
+ echo "$0:: No parameters - using arm_intcm"
+else
+ case "$2" in
+ ap966)
+ cpu="arm_intcm"
+ variant="unported core module CM966E-S"
+ ;;
+
+ ap922_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T"
+ ;;
+
+ integratorcp_config | \
+ cp_config)
+ cpu="arm_intcm"
+ variant="unspecified core module"
+ ;;
+
+ cp922_XA10_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T_XA10"
+ echo -n "#define CONFIG_CM922T_XA10" >> ${config_file}
+ echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file}
+ ;;
+
+ cp920t_config)
+ cpu="arm920t"
+ variant="Core module CM920T"
+ echo -n "#define CONFIG_CM920T" >> ${config_file}
+ echo " 1 /* CPU core is ARM920T */" >> ${config_file}
+ ;;
+
+ cp926ejs_config)
+ cpu="arm926ejs"
+ variant="Core module CM926EJ-S"
+ echo -n "#define CONFIG_CM926EJ_S" >> ${config_file}
+ echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file}
+ ;;
+
+
+ cp946es_config)
+ cpu="arm946es"
+ variant="Core module CM946E-S"
+ echo -n "#define CONFIG_CM946E_S" >> ${config_file}
+ echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file}
+ ;;
+
+ cp1136_config)
+ cpu="arm1136"
+ variant="Core module CM1136EJF-S"
+ echo -n "#define CONFIG_CM1136EJF_S" >> ${config_file}
+ echo " 1 /* CPU core is ARM1136JF-S */ " >> ${config_file}
+ ;;
+
+ *)
+ echo "$0:: Unknown core module"
+ variant="unknown core module"
+ cpu="arm_intcm"
+ ;;
+
+ esac
+
+fi
+
+if [ "$cpu" = "arm_intcm" ]
+then
+ echo "/* Core module undefined/not ported */" >> ${config_file}
+ echo "#define CONFIG_ARM_INTCM 1" >> ${config_file}
+ echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file}
+ echo -n " /* CM may not have " >> ${config_file}
+ echo "multiple SSRAM mapping */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file}
+ echo -n " /* CM may not support SPD " >> ${config_file}
+ echo "query */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_REMAP " >> ${config_file}
+ echo -n " /* CM may not support " >> ${config_file}
+ echo "remapping */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_INIT " >> ${config_file}
+ echo -n " /* CM may not have " >> ${config_file}
+ echo "initialization reg */" >> ${config_file}
+ echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file}
+ echo " /* CM may not have TCRAM */" >> ${config_file}
+fi
+
+fi # ap
+
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+$MKCONFIG -a integrator$1 arm $cpu integrator armltd;
+echo "Variant:: $variant with core $cpu"
#include <common.h>
#include <div64.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init (void);
-void ether__init (void);
-void peripheral_power_enable (void);
-
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
- printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* arch number of Integrator Board */
- gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- gd->flags = 0;
-
-#ifdef CONFIG_CM_REMAP
-extern void cm_remap(void);
- cm_remap(); /* remaps writeable memory to 0x00000000 */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+#define DIV_CLOCK_INIT 1
+#define TIMER_LOAD_VAL 0xFFFFFFFFL
+#else
+#define DIV_CLOCK_INIT 256
+#define TIMER_LOAD_VAL 0x0000FFFFL
#endif
-
- icache_enable ();
-
- flash__init ();
- ether__init ();
- return 0;
-}
-
-
-int misc_init_r (void)
-{
- setenv("verify", "n");
- return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-#ifdef CONFIG_CM_SPD_DETECT
- {
-extern void dram_query(void);
- unsigned long cm_reg_sdram;
- unsigned long sdram_shift;
-
- dram_query(); /* Assembler accesses to CM registers */
- /* Queries the SPD values */
-
- /* Obtain the SDRAM size from the CM SDRAM register */
-
- cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
- /* Register SDRAM size
- *
- * 0xXXXXXXbbb000bb 16 MB
- * 0xXXXXXXbbb001bb 32 MB
- * 0xXXXXXXbbb010bb 64 MB
- * 0xXXXXXXbbb011bb 128 MB
- * 0xXXXXXXbbb100bb 256 MB
- *
- */
- sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
- gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
-
- }
-#endif /* CM_SPD_DETECT */
-
- return 0;
-}
-
/* The Integrator/CP timer1 is clocked at 1MHz
* can be divided by 16 or 256
* and can be set up as a 32-bit timer
/* Keep total timer count to avoid losing decrements < div_timer */
static unsigned long long total_count = 0;
static unsigned long long lastdec; /* Timer reading at last call */
-static unsigned long long div_clock = 1; /* Divisor applied to timer clock */
+/* Divisor applied to timer clock */
+static unsigned long long div_clock = DIV_CLOCK_INIT;
static unsigned long long div_timer = 1; /* Divisor to convert timer reading
* change to U-Boot ticks
*/
/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
-static ulong timestamp; /* U-Boot ticks since startup */
+static ulong timestamp; /* U-Boot ticks since startup */
-#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
{
/* Load timer with initial value */
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+#ifdef CONFIG_ARCH_CINTEGRATOR
/* Set timer to be
- * enabled 1
- * periodic 1
- * no interrupts 0
- * X 0
- * divider 1 00 == less rounding error
- * 32 bit 1
- * wrapping 0
+ * enabled 1
+ * periodic 1
+ * no interrupts 0
+ * X 0
+ * divider 1 00 == less rounding error
+ * 32 bit 1
+ * wrapping 0
*/
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+#else
+ /* Set timer to be
+ * enabled 1
+ * free-running 0
+ * XX 00
+ * divider 256 10
+ * XX 00
+ */
+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+#endif
+
/* init the timestamp */
total_count = 0ULL;
reset_timer_masked();
- div_timer = (unsigned long long)(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ);
- div_timer /= div_clock;
+ div_timer = CONFIG_SYS_HZ_CLOCK;
+ do_div(div_timer, CONFIG_SYS_HZ);
+ do_div(div_timer, div_clock);
return (0);
}
void set_timer (ulong ticks)
{
timestamp = ticks;
- total_count = (unsigned long long)ticks * div_timer;
+ total_count = ticks * div_timer;
}
/* delay usec useconds */
void reset_timer_masked (void)
{
/* capure current decrementer value */
- lastdec = (unsigned long long)READ_TIMER;
+ lastdec = READ_TIMER;
/* start "advancing" time stamp from 0 */
timestamp = 0L;
}
ulong get_timer_masked (void)
{
/* get current count */
- unsigned long long now = (unsigned long long)READ_TIMER;
+ unsigned long long now = READ_TIMER;
if(now > lastdec) {
/* Must have wrapped */
} else {
total_count += lastdec - now;
}
- lastdec = now;
+ lastdec = now;
/* Reuse "now" */
now = total_count;
*/
unsigned long long get_ticks(void)
{
- return (unsigned long long)get_timer(0);
+ return get_timer(0);
}
/*
*/
ulong get_tbclk (void)
{
- return (ulong)(((unsigned long long)CONFIG_SYS_HZ_CLOCK)/div_clock);
+ unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+
+ do_div(tmp, div_clock);
+
+ return tmp;
}
+++ /dev/null
-#
-# image should be loaded at 0x01000000
-#
-
-TEXT_BASE = 0x01000000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
- unsigned int sector_number;
- unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
- {4, 32 * 1024}, /* 4 * 32kBytes sectors */
- {255, 128 * 1024}, /* 255 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
- OrgDef *pOrgDef;
-
- pOrgDef = OrgIntel_28F256L18T;
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- if (i > 255) {
- info->start[i] = base + (i * 0x8000);
- info->protect[i] = 0;
- } else {
- info->start[i] = base +
- (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256L18T:
- printf ("FLASH 28F256L18T\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
- volatile FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
- switch (value) {
-
- case (FPW) (INTEL_ID_28F256L18T):
- info->flash_id += FLASH_28F256L18T;
- info->sector_count = 259;
- info->size = 0x02000000;
- break; /* => 32 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK 0x0080
-
- *addr = (FPW) 0x00500050; /* clear status register */
-
- /* this sends the clear lock bit command */
- *addr = (FPW) 0x00600060;
- *addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-
- start = get_timer (0);
- last = start;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- flash_unprotect_sectors (addr);
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- *addr = (FPW) 0x00500050;/* clear status register */
- *addr = (FPW) 0x00200020;/* erase setup */
- *addr = (FPW) 0x00D000D0;/* erase confirm */
-
- while (((status =
- *addr) & (FPW) 0x00800080) !=
- (FPW) 0x00800080) {
- if (get_timer_masked () >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- /* suspend erase */
- *addr = (FPW) 0x00B000B0;
- /* reset to read mode */
- *addr = (FPW) 0x00FF00FF;
- rcode = 1;
- break;
- }
- }
-
- /* clear status register cmd. */
- *addr = (FPW) 0x00500050;
- *addr = (FPW) 0x00FF00FF;/* resest to read mode */
- printf (" done\n");
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
- return (2);
- }
- flash_unprotect_sectors (addr);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
+++ /dev/null
-#!/bin/sh
-# ---------------------------------------------------------
-# Set the platform defines
-# ---------------------------------------------------------
-echo -n "/* Integrator configuration implied " > tmp.fil
-echo " by Makefile target */" >> tmp.fil
-echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil
-echo " /* Integrator board */" >> tmp.fil
-echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil
-echo " 1 /* Integrator/AP */" >> tmp.fil
-# ---------------------------------------------------------
-# Set the core module defines according to Core Module
-# ---------------------------------------------------------
-cpu="arm_intcm"
-variant="unknown core module"
-
-if [ "$1" = "" ]
-then
- echo "$0:: No parameters - using arm_intcm"
-else
- case "$1" in
- ap7_config)
- cpu="arm_intcm"
- variant="unported core module CM7TDMI"
- ;;
-
- ap966)
- cpu="arm_intcm"
- variant="unported core module CM966E-S"
- ;;
-
- ap922_config)
- cpu="arm_intcm"
- variant="unported core module CM922T"
- ;;
-
- integratorap_config | \
- ap_config)
- cpu="arm_intcm"
- variant="unspecified core module"
- ;;
-
- ap720t_config)
- cpu="arm720t"
- echo -n "#define CONFIG_CM720T" >> tmp.fil
- echo " 1 /* CPU core is ARM720T */ " >> tmp.fil
- variant="Core module CM720T"
- ;;
-
- ap922_XA10_config)
- cpu="arm_intcm"
- variant="unported core module CM922T_XA10"
- echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil
- echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil
- ;;
-
- ap920t_config)
- cpu="arm920t"
- variant="Core module CM920T"
- echo -n "#define CONFIG_CM920T" >> tmp.fil
- echo " 1 /* CPU core is ARM920T */" >> tmp.fil
- ;;
-
- ap926ejs_config)
- cpu="arm926ejs"
- variant="Core module CM926EJ-S"
- echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil
- echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil
- ;;
-
- ap946es_config)
- cpu="arm946es"
- variant="Core module CM946E-S"
- echo -n "#define CONFIG_CM946E_S" >> tmp.fil
- echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil
- ;;
-
- *)
- echo "$0:: Unknown core module"
- variant="unknown core module"
- cpu="arm_intcm"
- ;;
-
- esac
-fi
-
-case "$cpu" in
- arm_intcm)
- echo "/* Core module undefined/not ported */" >> tmp.fil
- echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
- echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil
- echo -n " /* CM may not have " >> tmp.fil
- echo "multiple SSRAM mapping */" >> tmp.fil
- echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil
- echo -n " /* CM may not support SPD " >> tmp.fil
- echo "query */" >> tmp.fil
- echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil
- echo -n " /* CM may not support " >> tmp.fil
- echo "remapping */" >> tmp.fil
- echo -n "#undef CONFIG_CM_INIT " >> tmp.fil
- echo -n " /* CM may not have " >> tmp.fil
- echo "initialization reg */" >> tmp.fil
- echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
- echo " /* CM may not have TCRAM */" >> tmp.fil
- echo -n " /* May not be processor " >> tmp.fil
- echo "without cache support */" >> tmp.fil
- echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil
- echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil
- ;;
-
- arm720t)
- echo -n " /* May not be processor " >> tmp.fil
- echo "without cache support */" >> tmp.fil
- echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil
- echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil
- ;;
-esac
-
-mkdir -p ${obj}include
-mkdir -p ${obj}board/armltd/integratorap
-mv tmp.fil ${obj}include/config.h
-# ---------------------------------------------------------
-# Complete the configuration
-# ---------------------------------------------------------
-$MKCONFIG -a integratorap arm $cpu integratorap armltd;
-echo "Variant:: $variant with core $cpu"
-
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define DEBUG
-
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
- unsigned int sector_number;
- unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
- {4, 32 * 1024}, /* 4 * 32kBytes sectors */
- {255, 128 * 1024}, /* 255 * 128kBytes sectors */
-};
-
-/* CP control register base address */
-#define CPCR_BASE 0xCB000000
-#define CPCR_EXTRABANK 0x8
-#define CPCR_FLASHSIZE 0x4
-#define CPCR_FLWREN 0x2
-#define CPCR_FLVPPEN 0x1
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- int i, nbanks;
- ulong size = 0;
- vu_long *cpcr = (vu_long *)CPCR_BASE;
-
- /* Check if there is an extra bank of flash */
- if (cpcr[1] & CPCR_EXTRABANK)
- nbanks = 2;
- else
- nbanks = 1;
-
- if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
- nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-
- /* Enable flash write */
- cpcr[1] |= 3;
-
- for (i = 0; i < nbanks; i++) {
- flash_get_size ((FPW *)(CONFIG_SYS_FLASH_BASE + size), &flash_info[i]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size, &flash_info[i]);
- size += flash_info[i].size;
- }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */
- flash_protect (FLAG_PROTECT_SET,
- flash_info[0].start[62],
- flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1,
- &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- /* Integrator CP board uses 28F640J3C or 28F128J3C parts,
- * which have the same device id numbers as 28F640J3A or
- * 28F128J3A
- */
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256L18T:
- printf ("FLASH 28F256L18T\n");
- break;
- case FLASH_28F640J3A:
- printf ("FLASH 28F640J3C\n");
- break;
- case FLASH_28F128J3A:
- printf ("FLASH 28F128J3C\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
- volatile FPW value;
- vu_long *cpcr = (vu_long *)CPCR_BASE;
- int nsects;
-
- /* Check the flash size */
- if (cpcr[1] & CPCR_FLASHSIZE)
- nsects = 128;
- else
- nsects = 64;
-
- if (nsects > CONFIG_SYS_MAX_FLASH_SECT)
- nsects = CONFIG_SYS_MAX_FLASH_SECT;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
- switch (value) {
-
- case (FPW) (INTEL_ID_28F256L18T):
- info->flash_id += FLASH_28F256L18T;
- info->sector_count = 259;
- info->size = 0x02000000;
- break; /* => 32 MB */
-
- case (FPW) (INTEL_ID_28F640J3A):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = nsects;
- info->size = nsects * PHYS_FLASH_SECT_SIZE;
- break;
-
- case (FPW) (INTEL_ID_28F128J3A):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = nsects;
- info->size = nsects * PHYS_FLASH_SECT_SIZE;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
- FPW status;
-
- *addr = (FPW) 0x00500050; /* clear status register */
-
- /* this sends the clear lock bit command */
- *addr = (FPW) 0x00600060;
- *addr = (FPW) 0x00D000D0;
-
- reset_timer_masked();
- while (((status = *addr) & (FPW)0x00800080) != 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout");
- break;
- }
- }
-
- *addr = (FPW) 0x00FF00FF;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* flash_unprotect_sectors (addr); */
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
- mb();
-
- udelay(1000); /* Let's wait 1 ms */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = (FPW)0x00700070;
- status = *addr;
- if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) {
- /* erase suspended? Resume it */
- reset_timer_masked();
- *addr = (FPW) 0x00D000D0;
- } else {
-#ifdef DEBUG
- printf ("Timeout,0x%08lx\n", status);
-#else
- printf("Timeout\n");
-#endif
-
- *addr = (FPW) 0x00500050;
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* resest to read mode */
- printf (" done\n");
- }
- }
-
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* flash_unprotect_sectors (addr); */
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- mb();
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
-#ifdef DEBUG
- *addr = (FPW) 0x00700070;
- status = *addr;
- printf("## status=0x%08lx, addr=0x%p\n", status, addr);
-#endif
- *addr = (FPW) 0x00500050; /* clear status register cmd */
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-/* Reset using CM control register */
-.global reset_cpu
-reset_cpu:
- mov r0, #CM_BASE
- ldr r1,[r0,#OS_CTRL]
- orr r1,r1,#CMMASK_RESET
- str r1,[r0,#OS_CTRL]
-
-reset_failed:
- b reset_failed
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
- /* If U-Boot has been run after the ARM boot monitor
- * then all the necessary actions have been done
- * otherwise we are running from user flash mapped to 0x00000000
- * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
- * Changes to the (possibly soft) reset defaults of the processor
- * itself should be performed in cpu/arm<>/start.S
- * This function affects only the core module or board settings
- */
-
-#ifdef CONFIG_CM_INIT
- /* CM has an initialization register
- * - bits in it are wired into test-chip pins to force
- * reset defaults
- * - may need to change its contents for U-Boot
- */
-
- /* set the desired CM specific value */
- mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
-
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
- orr r2,r2,#CMMASK_INIT_102
-#else
-
-#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
- !defined (CONFIG_CM940T)
- /* CMxx6 code */
-
-#ifdef CONFIG_CM_MULTIPLE_SSRAM
- /* set simple mapping */
- and r2,r2,#CMMASK_MAP_SIMPLE
-#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
-
-#ifdef CONFIG_CM_TCRAM
- /* disable TCRAM */
- and r2,r2,#CMMASK_TCRAM_DISABLE
-#endif /* #ifdef CONFIG_CM_TCRAM */
-
-#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
- defined (CONFIG_CM1136JF_S)
-
- and r2,r2,#CMMASK_LE
-
-#endif /* cpu with little endian initialization */
-
- orr r2,r2,#CMMASK_CMxx6_COMMON
-
-#endif /* CMxx6 code */
-
-#endif /* ARM102xxE value */
-
- /* read CM_INIT */
- mov r0, #CM_BASE
- ldr r1, [r0, #OS_INIT]
- /* check against desired bit setting */
- and r3,r1,r2
- cmp r3,r2
- beq init_reg_OK
-
- /* lock for change */
- mov r3, #CMVAL_LOCK1
- and r3, r3, #CMVAL_LOCK2
- str r3, [r0, #OS_LOCK]
- /* set desired value */
- orr r1,r1,r2
- /* write & relock CM_INIT */
- str r1, [r0, #OS_INIT]
- mov r1, #CMVAL_UNLOCK
- str r1, [r0, #OS_LOCK]
-
- /* soft reset so new values used */
- b reset_cpu
-
-init_reg_OK:
-
-#endif /* CONFIG_CM_INIT */
-
- mov pc, lr
-
-#ifdef CONFIG_CM_SPD_DETECT
- /* Fast memory is available for the DRAM data
- * - ensure it has been transferred, then summarize the data
- * into a CM register
- */
-.globl dram_query
-dram_query:
- stmfd r13!,{r4-r6,lr}
- /* set up SDRAM info */
- /* - based on example code from the CM User Guide */
- mov r0, #CM_BASE
-
-readspdbit:
- ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
- and r1, r1, #0x20 /* mask SPD bit (5) */
- cmp r1, #0x20 /* test if set */
- bne readspdbit
-
-setupsdram:
- add r0, r0, #OS_SPD /* address the copy of the SDP data */
- ldrb r1, [r0, #3] /* number of row address lines */
- ldrb r2, [r0, #4] /* number of column address lines */
- ldrb r3, [r0, #5] /* number of banks */
- ldrb r4, [r0, #31] /* module bank density */
- mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
- mov r5, r5, ASL#2 /* size in MB */
- mov r0, #CM_BASE /* reload for later code */
- cmp r5, #0x10 /* is it 16MB? */
- bne not16
- mov r6, #0x2 /* store size and CAS latency of 2 */
- b writesize
-
-not16:
- cmp r5, #0x20 /* is it 32MB? */
- bne not32
- mov r6, #0x6
- b writesize
-
-not32:
- cmp r5, #0x40 /* is it 64MB? */
- bne not64
- mov r6, #0xa
- b writesize
-
-not64:
- cmp r5, #0x80 /* is it 128MB? */
- bne not128
- mov r6, #0xe
- b writesize
-
-not128:
- /* if it is none of these sizes then it is either 256MB, or
- * there is no SDRAM fitted so default to 256MB
- */
- mov r6, #0x12
-
-writesize:
- mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
- orr r2, r1, r2, ASL#12 /* OR in column address lines */
- orr r3, r2, r3, ASL#16 /* OR in number of banks */
- orr r6, r6, r3 /* OR in size and CAS latency */
- str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
-
-#endif /* #ifdef CONFIG_CM_SPD_DETECT */
-
- ldmfd r13!,{r4-r6,pc} /* back to caller */
-
-#ifdef CONFIG_CM_REMAP
- /* CM remap bit is operational
- * - use it to map writeable memory at 0x00000000, in place of flash
- */
-.globl cm_remap
-cm_remap:
- stmfd r13!,{r4-r10,lr}
-
- mov r0, #CM_BASE
- ldr r1, [r0, #OS_CTRL]
- orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
- str r1, [r0, #OS_CTRL]
-
- /* Now 0x00000000 is writeable, replace the vectors */
- ldr r0, =_start /* r0 <- start of vectors */
- ldr r2, =_armboot_start /* r2 <- past vectors */
- sub r1,r1,r1 /* destination 0x00000000 */
-
-copy_vec:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- ble copy_vec
-
- ldmfd r13!,{r4-r10,pc} /* back to caller */
-
-#endif /* #ifdef CONFIG_CM_REMAP */
+++ /dev/null
-#!/bin/sh
-# ---------------------------------------------------------
-# Set the platform defines
-# ---------------------------------------------------------
-echo -n "/* Integrator configuration implied " > tmp.fil
-echo " by Makefile target */" >> tmp.fil
-echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil
-echo " /* Integrator board */" >> tmp.fil
-echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil
-echo " 1 /* Integrator/CP */" >> tmp.fil
-
-cpu="arm_intcm"
-variant="unknown core module"
-
-if [ "$1" = "" ]
-then
- echo "$0:: No parameters - using arm_intcm"
-else
- case "$1" in
- ap966)
- cpu="arm_intcm"
- variant="unported core module CM966E-S"
- ;;
-
- ap922_config)
- cpu="arm_intcm"
- variant="unported core module CM922T"
- ;;
-
- integratorcp_config | \
- cp_config)
- cpu="arm_intcm"
- variant="unspecified core module"
- ;;
-
- cp922_XA10_config)
- cpu="arm_intcm"
- variant="unported core module CM922T_XA10"
- echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil
- echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil
- ;;
-
- cp920t_config)
- cpu="arm920t"
- variant="Core module CM920T"
- echo -n "#define CONFIG_CM920T" >> tmp.fil
- echo " 1 /* CPU core is ARM920T */" >> tmp.fil
- ;;
-
- cp926ejs_config)
- cpu="arm926ejs"
- variant="Core module CM926EJ-S"
- echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil
- echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil
- ;;
-
-
- cp946es_config)
- cpu="arm946es"
- variant="Core module CM946E-S"
- echo -n "#define CONFIG_CM946E_S" >> tmp.fil
- echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil
- ;;
-
- cp1136_config)
- cpu="arm1136"
- variant="Core module CM1136EJF-S"
- echo -n "#define CONFIG_CM1136EJF_S" >> tmp.fil
- echo " 1 /* CPU core is ARM1136JF-S */ " >> tmp.fil
- ;;
-
- *)
- echo "$0:: Unknown core module"
- variant="unknown core module"
- cpu="arm_intcm"
- ;;
-
- esac
-
-fi
-
-if [ "$cpu" = "arm_intcm" ]
-then
- echo "/* Core module undefined/not ported */" >> tmp.fil
- echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
- echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil
- echo -n " /* CM may not have " >> tmp.fil
- echo "multiple SSRAM mapping */" >> tmp.fil
- echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil
- echo -n " /* CM may not support SPD " >> tmp.fil
- echo "query */" >> tmp.fil
- echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil
- echo -n " /* CM may not support " >> tmp.fil
- echo "remapping */" >> tmp.fil
- echo -n "#undef CONFIG_CM_INIT " >> tmp.fil
- echo -n " /* CM may not have " >> tmp.fil
- echo "initialization reg */" >> tmp.fil
- echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
- echo " /* CM may not have TCRAM */" >> tmp.fil
-fi
-
-mkdir -p ${obj}include
-mkdir -p ${obj}board/armltd/integratorcp
-mv tmp.fil ${obj}include/config.h
-# ---------------------------------------------------------
-# Complete the configuration
-# ---------------------------------------------------------
-$MKCONFIG -a integratorcp arm $cpu integratorcp armltd;
-echo "Variant:: $variant with core $cpu"
-
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
/*
* Miscellaneous platform dependent initialisations
*/
#ifdef CONFIG_MACB
static void at91sam9260ek_macb_hw_init(void)
{
+ unsigned long rstc;
+
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+ rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0 << 8)) |
+ (rstc) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
+ unsigned long rstc;
+
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
+ rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0 << 8)) |
+ (rstc) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
#include <nand.h>
#include <version.h>
+#ifndef CONFIG_SYS_NO_FLASH
+extern flash_info_t flash_info[];
+#endif
+
void lcd_show_board_info(void)
{
ulong dram_size, nand_size;
+#ifndef CONFIG_SYS_NO_FLASH
+ ulong flash_size;
+#endif
int i;
char temp[32];
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
- lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
+#ifndef CONFIG_SYS_NO_FLASH
+ flash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+ flash_size += flash_info[i].size;
+#endif
+ lcd_printf (" %ld MB SDRAM, %ld MB NAND",
dram_size >> 20,
nand_size >> 20 );
+#ifndef CONFIG_SYS_NO_FLASH
+ lcd_printf (",\n %ld MB NOR",
+ flash_size >> 20);
+#endif
+ lcd_puts ("\n");
}
#endif /* CONFIG_LCD_INFO */
#endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS := $(BOARD).o cmd_mtc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Werner Pfister <Pfister_Werner@intercontrol.de>
+ *
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include "spi.h"
+#include "cmd_mtc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *led_names[] = {
+ "diag",
+ "can1",
+ "can2",
+ "can3",
+ "can4",
+ "usbpwr",
+ "usbbusy",
+ "user1",
+ "user2",
+ ""
+};
+
+static void mtc_calculate_checksum(tx_msp_cmd *packet)
+{
+ int i;
+ uchar *buff;
+
+ buff = (uchar *) packet;
+
+ for (i = 0; i < 6; i++)
+ packet->cks += buff[i];
+}
+
+static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err = 0;
+ int i;
+
+ if (argc < 2) {
+ cmd_usage(cmdtp);
+ return -1;
+ }
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_SET_LED;
+
+ pcmd.cmd_val0 = 0xff;
+ for (i = 0; strlen(led_names[i]) != 0; i++) {
+ if (strncmp(argv[1], led_names[i], strlen(led_names[i])) == 0) {
+ pcmd.cmd_val0 = i;
+ break;
+ }
+ }
+
+ if (pcmd.cmd_val0 == 0xff) {
+ printf("Usage:\n%s\n", cmdtp->help);
+ return -1;
+ }
+
+ if (argc >= 3) {
+ if (strncmp(argv[2], "red", 3) == 0)
+ pcmd.cmd_val1 = 1;
+ else if (strncmp(argv[2], "green", 5) == 0)
+ pcmd.cmd_val1 = 2;
+ else if (strncmp(argv[2], "orange", 6) == 0)
+ pcmd.cmd_val1 = 3;
+ else
+ pcmd.cmd_val1 = 0;
+ }
+
+ if (argc >= 4)
+ pcmd.cmd_val2 = simple_strtol(argv[3], NULL, 10);
+ else
+ pcmd.cmd_val2 = 0;
+
+ mtc_calculate_checksum(&pcmd);
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ return err;
+}
+
+static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err = 0;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_GET_VIM;
+
+ mtc_calculate_checksum(&pcmd);
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (!err) {
+ /* function returns '0' if key is pressed */
+ err = (prx.input & 0x80) ? 0 : 1;
+ }
+
+ return err;
+}
+
+static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err = 0;
+ uchar channel_mask = 0;
+
+ if (argc < 3) {
+ cmd_usage(cmdtp);
+ return -1;
+ }
+
+ if (strncmp(argv[1], "on", 2) == 0)
+ channel_mask |= 1;
+ if (strncmp(argv[2], "on", 2) == 0)
+ channel_mask |= 2;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_GET_VIM;
+ pcmd.user_out = channel_mask;
+
+ mtc_calculate_checksum(&pcmd);
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ return err;
+}
+
+static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err = 0;
+ uchar channel_num = 0;
+
+ if (argc < 2) {
+ cmd_usage(cmdtp);
+ return -1;
+ }
+
+ channel_num = simple_strtol(argv[1], NULL, 10);
+ if ((channel_num != 1) && (channel_num != 2)) {
+ printf("mtc digin: invalid parameter - must be '1' or '2'\n");
+ return -1;
+ }
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_GET_VIM;
+
+ mtc_calculate_checksum(&pcmd);
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (!err) {
+ /* function returns '0' when digin is on */
+ err = (prx.input & channel_num) ? 0 : 1;
+ }
+
+ return err;
+}
+
+static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+ char buf[5];
+
+ /* read appreg */
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_WD_PARA;
+ pcmd.cmd_val0 = 5; /* max. Count */
+ pcmd.cmd_val1 = 5; /* max. Time */
+ pcmd.cmd_val2 = 0; /* =0 means read appreg */
+
+ mtc_calculate_checksum(&pcmd);
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ if (!err) {
+ sprintf(buf, "%d", prx.ack2);
+ setenv("appreg", buf);
+ }
+
+ return err;
+}
+
+static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err = 0;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_FW_VERSION;
+
+ mtc_calculate_checksum(&pcmd);
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (!err) {
+ printf("FW V%d.%d.%d / HW %d\n",
+ prx.ack0, prx.ack1, prx.ack3, prx.ack2);
+ }
+
+ return err;
+}
+
+static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+cmd_tbl_t cmd_mtc_sub[] = {
+ U_BOOT_CMD_MKENT(led, 3, 1, do_mtc_led,
+ "set state of leds",
+ "[ledname] [state] [blink]\n"
+ " - lednames: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
+ " - state: off red green orange\n"
+ " - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"),
+ U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key,
+ "returns state of user key\n", ""),
+ U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
+ "returns firmware version of supervisor uC\n", ""),
+ U_BOOT_CMD_MKENT(appreg, 0, 1, do_mtc_appreg,
+ "reads appreg value and stores in environment variable 'appreg'\n", ""),
+ U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
+ "returns state of digital input",
+ "<channel_num> - get state of digital input (1 or 2)\n"),
+ U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout,
+ "sets digital outputs",
+ "<on|off> <on|off>- set state of digital output 1 and 2\n"),
+ U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help",
+ "[command] - get help for command\n"),
+};
+
+static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern int _do_help(cmd_tbl_t *cmd_start, int cmd_items,
+ cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[]);
+#ifdef CONFIG_SYS_LONGHELP
+ puts("mtc ");
+#endif
+ return _do_help(&cmd_mtc_sub[0],
+ ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv);
+}
+
+/* Relocate the command table function pointers when running in RAM */
+int mtc_cmd_init_r(void)
+{
+ cmd_tbl_t *cmdtp;
+
+ for (cmdtp = &cmd_mtc_sub[0]; cmdtp !=
+ &cmd_mtc_sub[ARRAY_SIZE(cmd_mtc_sub)]; cmdtp++) {
+ ulong addr;
+
+ addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
+ cmdtp->cmd =
+ (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
+
+ addr = (ulong)(cmdtp->name) + gd->reloc_off;
+ cmdtp->name = (char *)addr;
+
+ if (cmdtp->usage) {
+ addr = (ulong)(cmdtp->usage) + gd->reloc_off;
+ cmdtp->usage = (char *)addr;
+ }
+#ifdef CONFIG_SYS_LONGHELP
+ if (cmdtp->help) {
+ addr = (ulong)(cmdtp->help) + gd->reloc_off;
+ cmdtp->help = (char *)addr;
+ }
+#endif
+ }
+ return 0;
+}
+
+int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ cmd_tbl_t *c;
+ int err = 0;
+
+ c = find_cmd_tbl(argv[1], &cmd_mtc_sub[0], ARRAY_SIZE(cmd_mtc_sub));
+ if (c) {
+ argc--;
+ argv++;
+ return c->cmd(c, flag, argc, argv);
+ } else {
+ /* Unrecognized command */
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ return err;
+}
+
+U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
+ "mtc - special commands for digsyMTC\n",
+ "[subcommand] [args...]\n"
+ "Subcommands list:\n"
+ "led [ledname] [state] [blink] - set state of leds\n"
+ " [ledname]: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
+ " [state]: off red green orange\n"
+ " [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n"
+ "key - returns state of user key\n"
+ "version - returns firmware version of supervisor uC\n"
+ "appreg - reads appreg value and stores in environment variable"
+ " 'appreg'\n"
+ "digin [channel] - returns state of digital input (1 or 2)\n"
+ "digout <on|off> <on|off> - sets state of two digital outputs\n"
+ "help [subcommand] - get help for subcommand\n"
+);
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Werner Pfister <Pfister_Werner@intercontrol.de>
+ *
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef CMD_MTC_H
+#define CMD_MTC_H
+
+#define CMD_WD_PARA 0x02
+#define CMD_FW_VERSION 0x10
+#define CMD_GET_VIM 0x30
+#define CMD_SET_LED 0x40
+
+typedef struct {
+ u8 cmd;
+ u8 sys_in;
+ u8 cmd_val0;
+ u8 cmd_val1;
+ u8 cmd_val2;
+ u8 user_out;
+ u8 cks;
+ u8 dummy1;
+ u8 dummy2;
+} tx_msp_cmd;
+
+typedef struct {
+ u8 input;
+ u8 state;
+ u8 ack2;
+ u8 ack3;
+ u8 ack0;
+ u8 ack1;
+ u8 ack;
+ u8 dummy;
+ u8 cks;
+} rx_msp_cmd;
+
+#define MTC_TRANSFER_SIZE (sizeof(tx_msp_cmd) * 8)
+
+#endif
int board_early_init_r(void)
{
+#ifdef CONFIG_MPC52XX_SPI
+ struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
+#endif
/*
* Now, when we are in RAM, enable flash write access for detection
* process. Note that CS_BOOT cannot be cleared when executing in
/* Low level USB init, required for proper kernel operation */
usb_cpu_init();
#endif
+#ifdef CONFIG_MPC52XX_SPI
+ /* GPT 6 Output Enable */
+ out_be32(&gpt[6].emsr, 0x00000034);
+ /* GPT 7 Output Enable */
+ out_be32(&gpt[7].emsr, 0x00000034);
+#endif
+
return (0);
}
int misc_init_r(void)
{
+ extern int mtc_cmd_init_r (void);
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
eth_setenv_enetaddr("ethaddr", enetaddr);
}
+ mtc_cmd_init_r();
return 0;
}
id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
- rev = in_8((void *)0xf0001000);
- if (rev & 0x10) /* old DP405 compatibility */
- rev = in_8((void *)0xf0000800);
-
- switch (rev & 0xc0) {
- case 0x00:
- puts(" (HW=DP405");
- break;
- case 0x80:
- puts(" (HW=DP405/CO");
- break;
- case 0xc0:
- puts(" (HW=DN405");
- break;
- }
- printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
-
- if ((rev & 0xc0) == 0xc0) {
- printf(", C5V=%s",
- in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
- }
- puts(")\n");
+ rev = in_8((void *)0xf0001000);
+ if (rev & 0x10) /* old DP405 compatibility */
+ rev = in_8((void *)0xf0000800);
+
+ switch (rev & 0xc0) {
+ case 0x00:
+ puts(" (HW=DP405");
+ break;
+ case 0x80:
+ puts(" (HW=DP405/CO");
+ break;
+ case 0xc0:
+ puts(" (HW=DN405");
+ break;
+ }
+ printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
+
+ if ((rev & 0xc0) == 0xc0) {
+ printf(", C5V=%s",
+ in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
+ }
+ puts(")\n");
return 0;
}
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x21f00000
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1; /* hardware revision */
+
+int get_hw_rev(void)
+{
+ if (hw_rev >= 0)
+ return hw_rev;
+
+ hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
+ hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
+ hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
+ hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+
+ if (hw_rev == 15)
+ hw_rev = 0;
+
+ return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void meesc_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+ at91_sys_write(AT91_MATRIX_EBI0CSA,
+ csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_DBW_8 |
+#endif
+ AT91_SMC_TDF_(2));
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void meesc_macb_hw_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+ at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void meesc_ethercat_hw_init(void)
+{
+ /* Configure SMC EBI1_CS0 for EtherCAT */
+ at91_sys_write(AT91_SMC1_SETUP(0),
+ AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC1_PULSE(0),
+ AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
+ AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
+ at91_sys_write(AT91_SMC1_CYCLE(0),
+ AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
+ /* Configure behavior at external wait signal, byte-select mode, 16 bit
+ data bus width, none data float wait states and TDF optimization */
+ at91_sys_write(AT91_SMC1_MODE(0),
+ AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
+ AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
+ AT91_SMC_TDFMODE);
+
+ /* Configure RDY/BSY */
+ at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
+
+int checkboard(void)
+{
+ char str[32];
+
+ puts("Board: esd CAN-EtherCAT Gateway");
+ if (getenv_r("serial#", str, sizeof(str)) > 0) {
+ puts(", serial# ");
+ puts(str);
+ }
+ printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+ printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Peripheral Clock Enable Register */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
+ 1 << AT91SAM9263_ID_PIOB |
+ 1 << AT91SAM9263_ID_PIOCDE);
+
+ /* arch number of MEESC-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_MEESC;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ meesc_nand_hw_init();
+#endif
+ meesc_ethercat_hw_init();
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ meesc_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+ at91_can_hw_init();
+#endif
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+};
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
/* Is this a valid NXID EEPROM? */
-#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D'))
+#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
+ (e.id[2] == 'I') || (e.id[3] == 'D'))
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_CCID
/* Is this a valid CCID EEPROM? */
-#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
+#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \
+ (e.id[2] == 'I') || (e.id[3] == 'D'))
#endif
/**
return 0;
}
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
msize = fixed_sdram();
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize DDR ECC byte
*/
phys_size_t initdram(int board_type)
{
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize DDR ECC byte
*/
return 0;
}
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
msize = fixed_sdram();
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize DDR ECC byte */
ddr_enable_ecc(msize * 1024 * 1024);
#endif
}
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
msize = fixed_sdram();
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize DDR ECC byte */
ddr_enable_ecc(msize * 1024 * 1024);
#endif
#
+# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
LIB = $(obj)lib$(BOARD).a
-COBJS := integratorcp.o flash.o
-SOBJS := lowlevel_init.o
+COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+ifdef CONFIG_NAND_SPL
+TEXT_BASE = 0x87ec0000
+else
+TEXT_BASE = 0x87f00000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ write32 IPU_CONF, IPU_CONF_DI_EN
+ write32 CCM_CCMR, CCM_CCMR_SETUP
+
+ wait_timer 0x40000
+
+ write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
+ write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
+
+ /* Set up clock to 532MHz */
+ write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
+ write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
+
+ write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ /* Set up MX31 DDR pins */
+ write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
+ write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
+ write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
+ write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
+ write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
+ write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
+ write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
+ write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
+ write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
+ write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
+ write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
+ write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
+ write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
+ write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
+ write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
+ write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
+ write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
+ write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
+ write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
+ write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
+ write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
+ write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
+ write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
+ write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
+ write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
+ write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
+ write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
+
+ /* Set up MX31 DDR Memory Controller */
+ write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
+ write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
+
+ /* Perform DDR init sequence */
+ write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
+ write32 CSD0_BASE | 0x0f00, 0x12344321
+ write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
+ write32 CSD0_BASE, 0x12344321
+ write32 CSD0_BASE, 0x12344321
+ write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
+ write8 CSD0_BASE | 0x00000033, 0xda
+ write8 CSD0_BASE | 0x01000000, 0xff
+ write32 WEIM_ESDCTL0, ESDCTL_RW
+ write32 CSD0_BASE, 0xDEADBEEF
+ write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
+
+ mov pc, lr
--- /dev/null
+/*
+ *
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* CS5: CPLD incl. network controller */
+ __REG(CSCR_U(5)) = 0x0000d843;
+ __REG(CSCR_L(5)) = 0x22252521;
+ __REG(CSCR_A(5)) = 0x22220a00;
+
+ /* Setup UART1 and SPI2 pins */
+ mx31_uart1_hw_init();
+ mx31_spi2_hw_init();
+
+ gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: i.MX31 MAX PDK (3DS)\n");
+ return 0;
+}
#include <tsec.h>
#include <asm/fsl_law.h>
#include <asm/mp.h>
+#include <netdev.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
tsec_eth_init(bis, tsec_info, num);
- return 0;
+ return pci_eth_init(bis);
}
#endif
phys_size_t initdram (int board_type)
{
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc (unsigned int dram_size);
#endif
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram ();
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize DDR ECC byte
*/
{
/* Initialize all of memory for ECC, then
* enable errors */
- uint *p = 0;
- uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
- *p = (unsigned int)0xdeadbeef;
- if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
- }
-
- /* 8K */
- dma_xfer((uint *)0x2000,0x2000,(uint *)0);
- /* 16K */
- dma_xfer((uint *)0x4000,0x4000,(uint *)0);
- /* 32K */
- dma_xfer((uint *)0x8000,0x8000,(uint *)0);
- /* 64K */
- dma_xfer((uint *)0x10000,0x10000,(uint *)0);
- /* 128k */
- dma_xfer((uint *)0x20000,0x20000,(uint *)0);
- /* 256k */
- dma_xfer((uint *)0x40000,0x40000,(uint *)0);
- /* 512k */
- dma_xfer((uint *)0x80000,0x80000,(uint *)0);
- /* 1M */
- dma_xfer((uint *)0x100000,0x100000,(uint *)0);
- /* 2M */
- dma_xfer((uint *)0x200000,0x200000,(uint *)0);
- /* 4M */
- dma_xfer((uint *)0x400000,0x400000,(uint *)0);
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
- }
+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
static void setup_net_chip(void)
{
gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
- gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
+ gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
- writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
- writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
- writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
- writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
- writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
- writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
- writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
+ writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x23f00000
\ No newline at end of file
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+#ifdef CONFIG_SYS_USE_DATAFLASH
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""},
+};
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9261_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <dataflash.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9261_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_DBW_8 |
+#endif
+ AT91_SMC_TDF_(2));
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(AT91_PIN_PA16, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(AT91_PIN_PC14, 1);
+
+ at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
+ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
+}
+#endif
+
+
+#ifdef CONFIG_DRIVER_DM9000
+static void pm9261_dm9000_hw_init(void)
+{
+ /* Configure SMC CS2 for DM9000 */
+ at91_sys_write(AT91_SMC_SETUP(2),
+ AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(2),
+ AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
+ AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
+ at91_sys_write(AT91_SMC_CYCLE(2),
+ AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
+ at91_sys_write(AT91_SMC_MODE(2),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
+ AT91_SMC_TDF_(1));
+
+ /* Configure Interrupt pin as input, no pull-up */
+ at91_set_gpio_input(AT91_PIN_PA24, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ vl_col: 240,
+ vl_row: 320,
+ vl_clk: 4965000,
+ vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ vl_bpix: 3,
+ vl_tft: 1,
+ vl_hsync_len: 5,
+ vl_left_margin: 1,
+ vl_right_margin:33,
+ vl_vsync_len: 1,
+ vl_upper_margin:1,
+ vl_lower_margin:0,
+ mmio: AT91SAM9261_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */
+}
+
+static void pm9261_lcd_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
+ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
+ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
+ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
+ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
+ at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
+ at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
+ at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
+ at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
+ at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
+ at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
+ at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
+ at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
+ at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
+ at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
+ at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
+ at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
+ at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
+ at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
+ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
+
+ at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+
+ gd->fb_base = AT91SAM9261_SRAM_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+extern flash_info_t flash_info[];
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size, flash_size, dataflash_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2009 Ronetix GmbH\n");
+ lcd_printf ("support@ronetix.at\n");
+ lcd_printf ("%s CPU at %s MHz",
+ AT91_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+
+ flash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+ flash_size += flash_info[i].size;
+
+ dataflash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+ dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+ dataflash_info[i].Device.pages_size;
+
+ lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
+ "%ld MB DataFlash\n",
+ dram_size >> 20,
+ nand_size >> 20,
+ flash_size >> 20,
+ dataflash_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+
+ /* arch number of PM9261-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PM9261;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ pm9261_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+ pm9261_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ pm9261_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+ char buf[32];
+
+ printf ("Board : Ronetix PM9261\n");
+ printf ("Crystal frequency: %8s MHz\n",
+ strmhz(buf, get_main_clk_rate()));
+ printf ("CPU clock : %8s MHz\n",
+ strmhz(buf, get_cpu_clk_rate()));
+ printf ("Master clock : %8s MHz\n",
+ strmhz(buf, get_mck_clk_rate()));
+
+ return 0;
+}
+#endif
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y := lowlevel_init.o
-endif
-
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
static int pm9263_lcd_hw_psram_init(void)
{
volatile uint16_t x;
+ unsigned long csa;
+
+ /* Enable CS3 3.3v, no pull-ups */
+ csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
+ at91_sys_write(AT91_MATRIX_EBI1CSA,
+ csa | AT91_MATRIX_EBI1_DBPUC |
+ AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
+
+ /* Configure SMC1 CS0 for PSRAM - 16-bit */
+ at91_sys_write(AT91_SMC1_SETUP(0),
+ AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC1_PULSE(0),
+ AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
+ at91_sys_write(AT91_SMC1_CYCLE(0),
+ AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+ at91_sys_write(AT91_SMC1_MODE(0),
+ AT91_SMC_DBW_16 |
+ AT91_SMC_PMEN |
+ AT91_SMC_PS_32);
/* setup PB29 as output */
at91_set_gpio_output(PSRAM_CRE_PIN, 1);
at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
AT91_MATRIX_DEFMSTR_TYPE_FIXED |
- (AT91_MATRIX_SLOT_CYCLE & (0x80 << 0)));
+ (AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
return 0;
}
{
/* Initialize all of memory for ECC, then
* enable errors */
- uint *p = 0;
- uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
- *p = (unsigned int)0xdeadbeef;
- if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
- }
- /* 8K */
- dma_xfer((uint *)0x2000,0x2000,(uint *)0);
- /* 16K */
- dma_xfer((uint *)0x4000,0x4000,(uint *)0);
- /* 32K */
- dma_xfer((uint *)0x8000,0x8000,(uint *)0);
- /* 64K */
- dma_xfer((uint *)0x10000,0x10000,(uint *)0);
- /* 128k */
- dma_xfer((uint *)0x20000,0x20000,(uint *)0);
- /* 256k */
- dma_xfer((uint *)0x40000,0x40000,(uint *)0);
- /* 512k */
- dma_xfer((uint *)0x80000,0x80000,(uint *)0);
- /* 1M */
- dma_xfer((uint *)0x100000,0x100000,(uint *)0);
- /* 2M */
- dma_xfer((uint *)0x200000,0x200000,(uint *)0);
- /* 4M */
- dma_xfer((uint *)0x400000,0x400000,(uint *)0);
-
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
- }
+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
LIB = $(obj)lib$(BOARD).a
-COBJS := nmdk8815.o
+COBJS := nhk8815.o
SOBJS := platform.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
writel(0x0000305b, REG_FSMC_BCR1);
writel(0x00033f33, REG_FSMC_BTR1);
+ /* Set up SMCS0 for OneNand: sram-like once again */
+ writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
+ writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
+
icache_enable();
return 0;
}
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
+#if CONFIG_POLARIS
+#define BOOT_CONSOLE "serial_stuart"
+#else
+#define BOOT_CONSOLE "serial_ffuart"
+#endif
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
-void usb_board_init(void)
+int usb_board_init(void)
{
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
/* Set port power control mask bits, only 3 ports. */
UHCRHDB |= (0x7<<17);
+
+ return 0;
}
void usb_board_init_fail(void)
CKEN &= ~CKEN10_USBHOST;
- puts("Called USB STOP\n");
return;
}
#if defined(CONFIG_SERIAL_MULTI)
char *console=getenv("boot_console");
- if ((strcmp(console,"serial_btuart") == 0) ||
- (strcmp(console,"serial_stuart") == 0) ||
- (strcmp(console,"serial_ffuart") == 0)) {
- setenv("stdout",console);
- setenv("stdin", console);
- setenv("stderr",console);
- } else {
- setenv("stdout", "serial");
- setenv("stdin", "serial");
- setenv("stderr", "serial");
+ if ((console == NULL) || (strcmp(console,"serial_btuart") &&
+ strcmp(console,"serial_stuart") &&
+ strcmp(console,"serial_ffuart"))) {
+ console = BOOT_CONSOLE;
}
+ setenv("stdout",console);
+ setenv("stdin", console);
+ setenv("stderr",console);
#endif
return 0;
}
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2009 Extreme Engineering Solutions, Inc.
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# XPedite5170
+#
+TEXT_BASE = 0xfff00000
+
+PLATFORM_RELFLAGS += -mrelocatable
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
--- /dev/null
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+ sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS1;
+#ifdef SPD_EEPROM_ADDRESS2
+ } else if (ctrl_num == 1) {
+ i2c_address = SPD_EEPROM_ADDRESS2;
+#endif
+ } else {
+ /* An inalid ctrl number was give, use default SPD */
+ printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num);
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ }
+
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork. These are:
+ * 1.) CPO (Read Capture Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
+ * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths.
+ * Unless clock and DQ lanes are very different
+ * lengths (>2"), this should be set to the nominal value
+ * of 1/2 clock delay.
+ * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
+ * 4.) 2T Timing on Addr/Ctl
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ * PCB routing on the XPedite5170 is nearly identical to the XPedite5370
+ * so we use the XPedite5370 settings as a basis for the XPedite5170.
+ */
+
+typedef struct board_memctl_options {
+ uint16_t datarate_mhz_low;
+ uint16_t datarate_mhz_high;
+ uint8_t clk_adjust;
+ uint8_t cpo_override;
+ uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+ {
+ /* Controller 0 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 9,
+ .write_data_delay = 2,
+ },
+ },
+ {
+ /* Controller 1 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 7,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+ sys_info_t sysinfo;
+ int i;
+ unsigned int datarate;
+
+ get_sys_info(&sysinfo);
+ datarate = fsl_ddr_get_mem_data_rate() / 1000000;
+
+ for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+ if ((bopts[i].datarate_mhz_low <= datarate) &&
+ (bopts[i].datarate_mhz_high >= datarate)) {
+ debug("controller %d:\n", ctrl_num);
+ debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+ debug(" cpo = %d\n", bopts[i].cpo_override);
+ debug(" write_data_delay = %d\n",
+ bopts[i].write_data_delay);
+ popts->clk_adjust = bopts[i].clk_adjust;
+ popts->cpo_override = bopts[i].cpo_override;
+ popts->write_data_delay = bopts[i].write_data_delay;
+ }
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE
+ /* NAND LAW covers 2 NAND flashes */
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
+#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2006, 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+
+ /* Read-only sections, merged into text segment: */
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc86xx/start.o (.text)
+ cpu/mpc86xx/traps.o (.text)
+ cpu/mpc86xx/interrupts.o (.text)
+ cpu/mpc86xx/cpu_init.o (.text)
+ cpu/mpc86xx/cpu.o (.text)
+ cpu/mpc86xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+#endif
+
+int checkboard(void)
+{
+ char *s;
+
+ printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
+ printf(" ");
+ s = getenv("board_rev");
+ if (s)
+ printf("Rev %s, ", s);
+ s = getenv("serial#");
+ if (s)
+ printf("Serial# %s, ", s);
+ s = getenv("board_cfg");
+ if (s)
+ printf("Cfg %s", s);
+ printf("\n");
+
+ return 0;
+}
+/*
+ * Print out which flash was booted from and if booting from the 2nd flash,
+ * swap flash chip selects to maintain consistent flash numbering/addresses.
+ */
+static void flash_cs_fixup(void)
+{
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ ccsr_lbc_t *lbc = &immap->im_lbc;
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+ printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
+ out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+
+ out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
+ out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
- || defined(CONFIG_MPC5xxx)
+ || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \
+ || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
COBJS += generic.o
COBJS += timer.o
+COBJS += devices.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
--- /dev/null
+/*
+ *
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/arch/mx31.h>
+
+#ifdef CONFIG_SYS_MX31_UART1
+void mx31_uart1_hw_init(void)
+{
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+void mx31_spi2_hw_init(void)
+{
+ /* SPI2 */
+ mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+ mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+ mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+ mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+ mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+ mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+ mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+ /* start SPI2 clock */
+ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+}
+#endif
#include <version.h>
.globl _start
_start: b reset
-#ifdef CONFIG_ONENAND_IPL
+#ifdef CONFIG_PRELOADER
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
-#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_PRELOADER */
.global _end_vect
_end_vect:
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
-#ifndef CONFIG_ONENAND_IPL
+#ifndef CONFIG_PRELOADER
beq stack_setup
-#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_PRELOADER */
ldr r2, _armboot_start
ldr r3, _bss_start
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
-#ifdef CONFIG_ONENAND_IPL
+#ifdef CONFIG_PRELOADER
sub sp, r0, #128 /* leave 32 words for abort-stack */
#else
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
-#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_PRELOADER */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
-#ifndef CONFIG_ONENAND_IPL
+#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ldr pc, _start_armboot
+#ifdef CONFIG_NAND_SPL
+_start_armboot: .word nand_boot
+#else
#ifdef CONFIG_ONENAND_IPL
_start_armboot: .word start_oneboot
#else
_start_armboot: .word start_armboot
-#endif
-
+#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_NAND_SPL */
/*
*************************************************************************
*
*************************************************************************
*/
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush v4 I/D caches
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-#ifndef CONFIG_ONENAND_IPL
+#ifndef CONFIG_PRELOADER
/*
*************************************************************************
*
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
-#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_PRELOADER */
/*
* exception handlers
*/
-#ifdef CONFIG_ONENAND_IPL
+#ifdef CONFIG_PRELOADER
.align 5
do_hang:
ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
-#else /* !CONFIG_ONENAND IPL */
+#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
arm1136_cache_flush:
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
mov pc, lr @ back to caller
-#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_PRELOADER */
return 0;
}
-
-/* * reset the cpu by setting up the watchdog timer and let him time out */
-void reset_cpu (ulong ignored)
-{
- printf("reset... \n\n\n");
- SW_RST_REG = 0x6400;
- /* loop forever and wait for reset to happen */
- while (1) {
- if (serial_tstc()) {
- serial_getc();
- break;
- }
- }
- /*NOTREACHED*/
-}
-
/* flush I/D-cache */
static void cache_flush (void)
{
LIB = $(obj)lib$(SOC).a
+SOBJS = reset.o
+
COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o
COBJS-y += timer.o
--- /dev/null
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <s3c6400.h>
+
+.globl reset_cpu
+reset_cpu:
+ ldr r1, =ELFIN_CLOCK_POWER_BASE
+ ldr r2, [r1, #SYS_ID_OFFSET]
+ ldr r3, =0xffff
+ and r2, r3, r2, lsr #12
+ str r2, [r1, #SW_RST_OFFSET]
+_loop_forever:
+ b _loop_forever
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = cpu.o interrupts.o
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+COBJS-y += cpu.o
+COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
*/
#include <common.h>
-
-#ifdef CONFIG_USE_IRQ
#include <asm/proc-armv/ptrace.h>
+
+#if defined (CONFIG_ARCH_INTEGRATOR)
void do_irq (struct pt_regs *pt_regs)
{
-#if defined (ARM920_IRQ_CALLBACK)
- ARM920_IRQ_CALLBACK();
-#elif defined (CONFIG_ARCH_INTEGRATOR)
/* ASSUMED to be a timer interrupt */
/* Just clear it - count handled in */
/* integratorap.c */
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
-#else
-#error do_irq() not defined for this cpu type
-#endif
}
#endif
LIB = $(obj)lib$(SOC).a
-COBJS += speed.o
-COBJS += timer.o
-COBJS += usb.o
-COBJS += usb_ohci.o
+COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+COBJS-y += speed.o
+COBJS-y += timer.o
+COBJS-y += usb.o
+COBJS-y += usb_ohci.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_S3C2400)
+#include <s3c2400.h>
+#elif defined(CONFIG_S3C2410)
+#include <s3c2410.h>
+#endif
+#include <asm/proc-armv/ptrace.h>
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
+ u_int32_t intpnd = irq->INTPND;
+
+}
/*NOTREACHED*/
}
-#ifdef CONFIG_USE_IRQ
-void s3c2410_irq(void)
-{
- S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
- u_int32_t intpnd = irq->INTPND;
-
-}
-#endif /* USE_IRQ */
-
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
COBJS-y += reset.o
COBJS-y += timer.o
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS-y := lowlevel_init.o
+endif
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
all: $(obj).depend $(LIB)
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
+ * (C) Copyright 2009
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#endif
}
#endif
+
+#ifdef CONFIG_AT91_CAN
+void at91_can_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */
+ at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN);
+}
+#endif
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
+ * (C) Copyright 2009
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
at91_set_gpio_output(AT91_PIN_PA24, 0);
}
#endif
+
+#ifdef CONFIG_AT91_CAN
+void at91_can_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */
+ at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN);
+}
+#endif
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_wdt.h>
+#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91sam9263_matrix.h>
_TEXT_BASE:
.word TEXT_BASE
*/
ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
- ldr r0, =0x0000FF01
- str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
+ /* Main oscillator Enable register PMC_MOR: */
+ ldr r0, =CONFIG_SYS_MOR_VAL
+ str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
mov r4, #AT91_PMC_MOSCS
/* ----------------------------------------------------------------------------
* PMC Init Step 3.
* ----------------------------------------------------------------------------
- * - Switch on the Main Oscillator 18.432 MHz
+ * - Switch on the Main Oscillator
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
.word (AT91_BASE_SYS + AT91_WDT_MR)
.word CONFIG_SYS_WDTC_WDMR_VAL
+ /* configure PIOx as EBI0 D[16-31] */
+#if defined(CONFIG_AT91SAM9263)
.word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
.word CONFIG_SYS_PIOD_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
.word CONFIG_SYS_PIOD_PPUDR_VAL
+#elif defined(CONFIG_AT91SAM9261)
+ .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
+ .word CONFIG_SYS_PIOC_PDR_VAL1
+ .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
+ .word CONFIG_SYS_PIOC_PPUDR_VAL
+#endif
+#if defined(AT91_MATRIX_EBI0CSA)
.word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
.word CONFIG_SYS_MATRIX_EBI0CSA_VAL
- .word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
- .word CONFIG_SYS_MATRIX_EBI1CSA_VAL
+#else /* AT91_MATRIX_EBICSA */
+ .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA)
+ .word CONFIG_SYS_MATRIX_EBICSA_VAL
+#endif
/* flash */
.word (AT91_BASE_SYS + AT91_SMC_MODE(0))
- .word CONFIG_SYS_SMC0_CTRL0_VAL
+ .word CONFIG_SYS_SMC0_MODE0_VAL
.word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
.word CONFIG_SYS_SMC0_CYCLE0_VAL
.word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
.word CONFIG_SYS_SMC0_SETUP0_VAL
- /* PSRAM */
- .word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
- .word CONFIG_SYS_SMC1_CTRL0_VAL
-
- .word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
- .word CONFIG_SYS_SMC1_CYCLE0_VAL
-
- .word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
- .word CONFIG_SYS_SMC1_PULSE0_VAL
-
- .word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
- .word CONFIG_SYS_SMC1_SETUP0_VAL
-
SMRDATA1:
.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
.word CONFIG_SYS_SDRC_MR_VAL1
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS-y = dram.o
+COBJS-y += cpu.o
+COBJS-y += mpp.o
+COBJS-y += timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/arch/kirkwood.h>
+
+#define BUFLEN 16
+
+void reset_cpu(unsigned long ignored)
+{
+ struct kwcpu_registers *cpureg =
+ (struct kwcpu_registers *)KW_CPU_REG_BASE;
+
+ writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+ &cpureg->rstoutn_mask);
+ writel(readl(&cpureg->sys_soft_rst) | 1,
+ &cpureg->sys_soft_rst);
+ while (1) ;
+}
+
+/*
+ * Generates Ramdom hex number reading some time varient system registers
+ * and using md5 algorithm
+ */
+unsigned char get_random_hex(void)
+{
+ int i;
+ u32 inbuf[BUFLEN];
+ u8 outbuf[BUFLEN];
+
+ /*
+ * in case of 88F6281/88F6192 A0,
+ * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
+ * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and
+ * Does not have names at this moment (no errata available)
+ */
+ writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
+ for (i = 0; i < BUFLEN; i++) {
+ inbuf[i] = readl(KW_REG_UNDOC_0x1470);
+ }
+ md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
+ return outbuf[outbuf[7] % 0x0f];
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int kw_winctrl_calcsize(unsigned int sizeval)
+{
+ int i;
+ unsigned int j = 0;
+ u32 val = sizeval >> 1;
+
+ for (i = 0; val > 0x10000; i++) {
+ j |= (1 << i);
+ val = val >> 1;
+ }
+ return (0x0000ffff & j);
+}
+
+/*
+ * kw_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Kirkwood Soc to addess different
+ * devices. Each window can be configured for size, BAR and remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int kw_config_adr_windows(void)
+{
+ struct kwwin_registers *winregs =
+ (struct kwwin_registers *)KW_CPU_WIN_BASE;
+
+ /* Window 0: PCIE MEM address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
+ KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
+
+ writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
+ writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
+ writel(0x0, &winregs[0].remap_hi);
+
+ /* Window 1: PCIE IO address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
+ KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
+ writel(KW_DEFADR_PCI_IO, &winregs[1].base);
+ writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
+ writel(0x0, &winregs[1].remap_hi);
+
+ /* Window 2: NAND Flash address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+ KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
+ writel(KW_DEFADR_NANDF, &winregs[2].base);
+ writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
+ writel(0x0, &winregs[2].remap_hi);
+
+ /* Window 3: SPI Flash address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+ KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
+ writel(KW_DEFADR_SPIF, &winregs[3].base);
+ writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
+ writel(0x0, &winregs[3].remap_hi);
+
+ /* Window 4: BOOT Memory address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+ KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
+ writel(KW_DEFADR_BOOTROM, &winregs[4].base);
+
+ /* Window 5: Security SRAM address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
+ KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
+ writel(KW_DEFADR_SASRAM, &winregs[5].base);
+
+ /* Window 6-7: Disabled */
+ writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
+ writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
+
+ return 0;
+}
+
+/*
+ * kw_config_gpio - GPIO configuration
+ */
+void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
+{
+ struct kwgpio_registers *gpio0reg =
+ (struct kwgpio_registers *)KW_GPIO0_BASE;
+ struct kwgpio_registers *gpio1reg =
+ (struct kwgpio_registers *)KW_GPIO1_BASE;
+
+ /* Init GPIOS to default values as per board requirement */
+ writel(gpp0_oe_val, &gpio0reg->dout);
+ writel(gpp1_oe_val, &gpio1reg->dout);
+ writel(gpp0_oe, &gpio0reg->oe);
+ writel(gpp1_oe, &gpio1reg->oe);
+}
+
+/*
+ * kw_config_mpp - Multi-Purpose Pins Functionality configuration
+ *
+ * Each MPP can be configured to different functionality through
+ * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
+ *
+ * There are maximum 64 Multi-Pourpose Pins on Kirkwood
+ * Each MPP functionality can be configuration by a 4bit value
+ * of MPP control reg, the value and associated functionality depends
+ * upon used SoC varient
+ */
+int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
+ u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
+{
+ u32 *mppreg = (u32 *) KW_MPP_BASE;
+
+ /* program mpp registers */
+ writel(mpp0_7, &mppreg[0]);
+ writel(mpp8_15, &mppreg[1]);
+ writel(mpp16_23, &mppreg[2]);
+ writel(mpp24_31, &mppreg[3]);
+ writel(mpp32_39, &mppreg[4]);
+ writel(mpp40_47, &mppreg[5]);
+ writel(mpp48_55, &mppreg[6]);
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ char *name = "Unknown";
+
+ switch (readl(KW_REG_DEVICE_ID) & 0x03) {
+ case 1:
+ name = "88F6192_A0";
+ break;
+ case 2:
+ name = "88F6281_A0";
+ break;
+ default:
+ printf("SoC: Unsupported Kirkwood\n");
+ return -1;
+ }
+ printf("SoC: Kirkwood %s\n", name);
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ u32 reg;
+ struct kwcpu_registers *cpureg =
+ (struct kwcpu_registers *)KW_CPU_REG_BASE;
+
+ /* Linux expects` the internal registers to be at 0xf1000000 */
+ writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
+
+ /* Enable and invalidate L2 cache in write through mode */
+ writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
+ invalidate_l2_cache();
+
+ kw_config_adr_windows();
+
+#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
+ /*
+ * Configures the I/O voltage of the pads connected to Egigabit
+ * Ethernet interface to 1.8V
+ * By defult it is set to 3.3V
+ */
+ reg = readl(KW_REG_MPP_OUT_DRV_REG);
+ reg |= (1 << 7);
+ writel(reg, KW_REG_MPP_OUT_DRV_REG);
+#endif
+#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
+ /*
+ * Set egiga port0/1 in normal functional mode
+ * This is required becasue on kirkwood by default ports are in reset mode
+ * OS egiga driver may not have provision to set them in normal mode
+ * and if u-boot is build without network support, network may fail at OS level
+ */
+ reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
+ reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
+#endif
+#ifdef CONFIG_KIRKWOOD_PCIE_INIT
+ /*
+ * Enable PCI Express Port0
+ */
+ reg = readl(&cpureg->ctrl_stat);
+ reg |= (1 << 0); /* Set PEX0En Bit */
+ writel(reg, &cpureg->ctrl_stat);
+#endif
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ volatile u32 temp;
+
+ /*CPU streaming & write allocate */
+ temp = readfr_extra_feature_reg();
+ temp &= ~(1 << 28); /* disable wr alloc */
+ writefr_extra_feature_reg(temp);
+
+ temp = readfr_extra_feature_reg();
+ temp &= ~(1 << 29); /* streaming disabled */
+ writefr_extra_feature_reg(temp);
+
+ /* L2Cache settings */
+ temp = readfr_extra_feature_reg();
+ /* Disable L2C pre fetch - Set bit 24 */
+ temp |= (1 << 24);
+ /* enable L2C - Set bit 22 */
+ temp |= (1 << 22);
+ writefr_extra_feature_reg(temp);
+
+ icache_enable();
+ /* Change reset vector to address 0x0 */
+ temp = get_cr();
+ set_cr(temp & ~CR_V);
+
+ return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_KIRKWOOD_EGIGA
+int cpu_eth_init(bd_t *bis)
+{
+ kirkwood_egiga_initialize(bis);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <asm/arch/kirkwood.h>
+
+#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
+#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
+/*
+ * kw_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 kw_sdram_bar(enum memory_bank bank)
+{
+ u32 result = 0;
+ u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+
+ result = readl(KW_REG_CPUCS_WIN_BAR(bank));
+ return result;
+}
+
+/*
+ * kw_sdram_bs - reads SDRAM Bank size
+ */
+u32 kw_sdram_bs(enum memory_bank bank)
+{
+ u32 result = 0;
+ u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+ result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+ result += 0x01000000;
+ return result;
+}
--- /dev/null
+/*
+ * arch/arm/mach-kirkwood/mpp.c
+ *
+ * MPP functions for Marvell Kirkwood SoCs
+ * Referenced from Linux kernel source
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+
+static u32 kirkwood_variant(void)
+{
+ switch (readl(KW_REG_DEVICE_ID) & 0x03) {
+ case 1:
+ return MPP_F6192_MASK;
+ case 2:
+ return MPP_F6281_MASK;
+ default:
+ debug("MPP setup: unknown kirkwood variant\n");
+ return 0;
+ }
+}
+
+#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
+#define MPP_NR_REGS (1 + MPP_MAX/8)
+
+void kirkwood_mpp_conf(u32 *mpp_list)
+{
+ u32 mpp_ctrl[MPP_NR_REGS];
+ unsigned int variant_mask;
+ int i;
+
+ variant_mask = kirkwood_variant();
+ if (!variant_mask)
+ return;
+
+ debug( "initial MPP regs:");
+ for (i = 0; i < MPP_NR_REGS; i++) {
+ mpp_ctrl[i] = readl(MPP_CTRL(i));
+ debug(" %08x", mpp_ctrl[i]);
+ }
+ debug("\n");
+
+
+ while (*mpp_list) {
+ unsigned int num = MPP_NUM(*mpp_list);
+ unsigned int sel = MPP_SEL(*mpp_list);
+ int shift;
+
+ if (num > MPP_MAX) {
+ debug("kirkwood_mpp_conf: invalid MPP "
+ "number (%u)\n", num);
+ continue;
+ }
+ if (!(*mpp_list & variant_mask)) {
+ debug("kirkwood_mpp_conf: requested MPP%u config "
+ "unavailable on this hardware\n", num);
+ continue;
+ }
+
+ shift = (num & 7) << 2;
+ mpp_ctrl[num / 8] &= ~(0xf << shift);
+ mpp_ctrl[num / 8] |= sel << shift;
+
+ mpp_list++;
+ }
+
+ debug(" final MPP regs:");
+ for (i = 0; i < MPP_NR_REGS; i++) {
+ writel(mpp_ctrl[i], MPP_CTRL(i));
+ debug(" %08x", mpp_ctrl[i]);
+ }
+ debug("\n");
+
+}
--- /dev/null
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/kirkwood.h>
+
+#define UBOOT_CNTR 0 /* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct kwtmr_val {
+ u32 reload; /* Timer reload reg */
+ u32 val; /* Timer value reg */
+};
+
+/* Timer registers */
+struct kwtmr_registers {
+ u32 ctrl; /* Timer control reg */
+ u32 pad[3];
+ struct kwtmr_val tmr[2];
+ u32 wdt_reload;
+ u32 wdt_val;
+};
+
+struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG &kwtmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS 0
+#define TRG_ARM_TIMER_REL_MASK 0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS 0
+#define TVR_ARM_TIMER_MASK 0xffffffff
+#define TVR_ARM_TIMER_MAX 0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff
+
+#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
+ (CONFIG_SYS_TCLK / 1000))
+
+static ulong timestamp;
+static ulong lastdec;
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER;
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER;
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec +
+ (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+ uint current;
+ ulong delayticks;
+
+ current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+ delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+ if (current < delayticks) {
+ delayticks -= current;
+ while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
+ while ((TIMER_LOAD_VAL - delayticks) <
+ readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
+ } else {
+ while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+ (current - delayticks)) ;
+ }
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+ unsigned int cntmrctrl;
+
+ /* load value into timer */
+ writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+ writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+ /* enable timer in auto reload mode */
+ cntmrctrl = readl(CNTMR_CTRL_REG);
+ cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+ cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+ writel(cntmrctrl, CNTMR_CTRL_REG);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = generic.o reset.o timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * get the system pll clock in Hz
+ *
+ * mfi + mfn / (mfd +1)
+ * f = 2 * f_ref * --------------------
+ * pd + 1
+ */
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+ unsigned int mfi = (pll >> 10) & 0xf;
+ unsigned int mfn = pll & 0x3ff;
+ unsigned int mfd = (pll >> 16) & 0x3ff;
+ unsigned int pd = (pll >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+
+ return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
+ (mfd + 1) * (pd + 1));
+}
+
+static ulong clk_in_32k(void)
+{
+ return 1024 * CONFIG_MX27_CLK32;
+}
+
+static ulong clk_in_26m(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
+ /* divide by 1.5 */
+ return 26000000 * 2 / 3;
+ } else {
+ return 26000000;
+ }
+}
+
+ulong imx_get_mpllclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->cscr);
+ ulong fref;
+
+ if (cscr & CSCR_MCU_SEL)
+ fref = clk_in_26m();
+ else
+ fref = clk_in_32k();
+
+ return imx_decode_pll(readl(&pll->mpctl0), fref);
+}
+
+ulong imx_get_armclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->cscr);
+ ulong fref = imx_get_mpllclk();
+ ulong div;
+
+ if (!(cscr & CSCR_ARM_SRC_MPLL))
+ fref = lldiv((fref * 2), 3);
+
+ div = ((cscr >> 12) & 0x3) + 1;
+
+ return lldiv(fref, div);
+}
+
+ulong imx_get_ahbclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->cscr);
+ ulong fref = imx_get_mpllclk();
+ ulong div;
+
+ div = ((cscr >> 8) & 0x3) + 1;
+
+ return lldiv(fref * 2, 3 * div);
+}
+
+ulong imx_get_spllclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->cscr);
+ ulong fref;
+
+ if (cscr & CSCR_SP_SEL)
+ fref = clk_in_26m();
+ else
+ fref = clk_in_32k();
+
+ return imx_decode_pll(readl(&pll->spctl0), fref);
+}
+
+static ulong imx_decode_perclk(ulong div)
+{
+ return lldiv((imx_get_mpllclk() * 2), (div * 3));
+}
+
+ulong imx_get_perclk1(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
+}
+
+ulong imx_get_perclk2(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
+}
+
+ulong imx_get_perclk3(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
+}
+
+ulong imx_get_perclk4(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale i.MX27 at %s MHz\n\n",
+ strmhz(buf, imx_get_mpllclk()));
+ return 0;
+}
+#endif
+
+void imx_gpio_mode(int gpio_mode)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+ unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+ unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+ unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
+ unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
+ unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
+ unsigned int tmp;
+
+ /* Pullup enable */
+ if (gpio_mode & GPIO_PUEN) {
+ writel(readl(®s->port[port].puen) | (1 << pin),
+ ®s->port[port].puen);
+ } else {
+ writel(readl(®s->port[port].puen) & ~(1 << pin),
+ ®s->port[port].puen);
+ }
+
+ /* Data direction */
+ if (gpio_mode & GPIO_OUT) {
+ writel(readl(®s->port[port].ddir) | 1 << pin,
+ ®s->port[port].ddir);
+ } else {
+ writel(readl(®s->port[port].ddir) & ~(1 << pin),
+ ®s->port[port].ddir);
+ }
+
+ /* Primary / alternate function */
+ if (gpio_mode & GPIO_AF) {
+ writel(readl(®s->port[port].gpr) | (1 << pin),
+ ®s->port[port].gpr);
+ } else {
+ writel(readl(®s->port[port].gpr) & ~(1 << pin),
+ ®s->port[port].gpr);
+ }
+
+ /* use as gpio? */
+ if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
+ writel(readl(®s->port[port].gius) | (1 << pin),
+ ®s->port[port].gius);
+ } else {
+ writel(readl(®s->port[port].gius) & ~(1 << pin),
+ ®s->port[port].gius);
+ }
+
+ /* Output / input configuration */
+ if (pin < 16) {
+ tmp = readl(®s->port[port].ocr1);
+ tmp &= ~(3 << (pin * 2));
+ tmp |= (ocr << (pin * 2));
+ writel(tmp, ®s->port[port].ocr1);
+
+ writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)),
+ ®s->port[port].iconfa1);
+ writel(readl(®s->port[port].iconfa1) | aout << (pin * 2),
+ ®s->port[port].iconfa1);
+ writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)),
+ ®s->port[port].iconfb1);
+ writel(readl(®s->port[port].iconfb1) | bout << (pin * 2),
+ ®s->port[port].iconfb1);
+ } else {
+ pin -= 16;
+
+ tmp = readl(®s->port[port].ocr2);
+ tmp &= ~(3 << (pin * 2));
+ tmp |= (ocr << (pin * 2));
+ writel(tmp, ®s->port[port].ocr2);
+
+ writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)),
+ ®s->port[port].iconfa2);
+ writel(readl(®s->port[port].iconfa2) | aout << (pin * 2),
+ ®s->port[port].iconfa2);
+ writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)),
+ ®s->port[port].iconfb2);
+ writel(readl(®s->port[port].iconfb2) | bout << (pin * 2),
+ ®s->port[port].iconfb2);
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu (ulong ignored)
+{
+ struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+ /* Disable watchdog and set Time-Out field to 0 */
+ writel(0x00000000, ®s->wcr);
+
+ /* Write Service Sequence */
+ writel(0x00005555, ®s->wsr);
+ writel(0x0000AAAA, ®s->wsr);
+
+ /* Enable watchdog */
+ writel(WCR_WDE, ®s->wcr);
+
+ while (1);
+ /*NOTREACHED*/
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_FRR (1 << 8) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
+#define GPTCR_TEN 1 /* Timer enable */
+
+static ulong timestamp;
+static ulong lastinc;
+
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, CONFIG_MX27_CLK32);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ time *= CONFIG_MX27_CLK32;
+ do_div(time, CONFIG_SYS_HZ);
+ return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us = us * CONFIG_MX27_CLK32 + 999999;
+ do_div(us, 1000000);
+ return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
+ CONFIG_SYS_HZ)
+#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ do_div(tick, TICK_PER_TIME);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us += US_PER_TICK - 1;
+ do_div(us, US_PER_TICK);
+ return us;
+}
+#endif
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init(void)
+{
+ int i;
+ struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ /* setup GP Timer 1 */
+ writel(GPTCR_SWR, ®s->gpt_tctl);
+
+ writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
+ writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
+
+ for (i = 0; i < 100; i++)
+ writel(0, ®s->gpt_tctl); /* We have no udelay by now */
+ writel(0, ®s->gpt_tprer); /* 32Khz */
+ /* Freerun Mode, PERCLK1 input */
+ writel(readl(®s->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+ ®s->gpt_tctl);
+ writel(readl(®s->gpt_tctl) | GPTCR_TEN, ®s->gpt_tctl);
+
+ return 0;
+}
+
+void reset_timer_masked(void)
+{
+ struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+ /* reset time */
+ /* capture current incrementer value time */
+ lastinc = readl(®s->gpt_tcn);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+ struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+ ulong now = readl(®s->gpt_tcn); /* current tick value */
+
+ if (now >= lastinc) {
+ /*
+ * normal mode (non roll)
+ * move stamp forward with absolut diff ticks
+ */
+ timestamp += (now - lastinc);
+ } else {
+ /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ }
+ lastinc = now;
+ return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+ /*
+ * get_ticks() returns a long long (64 bit), it wraps in
+ * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+ * 5 * 10^6 days - long enough.
+ */
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
.align 5
.globl reset_cpu
reset_cpu:
-#if defined CONFIG_NOMADIK_8815
- ldr r0, =NOMADIK_SRC_BASE
+ ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */
ldr r1, =0x1
str r1, [r0, #0x18]
-#else
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
-#endif
_loop_forever:
b _loop_forever
-
-rstctl1:
- .word 0xfffece10
/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ * (C) Copyright 2009 Alessandro Rubini
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/mtu.h>
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER readl(CONFIG_SYS_TIMERBASE + 20)
+/*
+ * The timer is a decrementer, we'll left it free running at 2.4MHz.
+ * We have 2.4 ticks per microsecond and an overflow in almost 30min
+ */
+#define TIMER_CLOCK (24 * 100 * 1000)
+#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
+#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
+#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-static ulong timestamp;
-static ulong lastdec;
+/* macro to read the 32 bit timer: since it decrements, we invert read value */
+#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-/* nothing really to do with interrupts, just starts up a counter. */
+/* Configure a free-running, auto-wrap counter with no prescaler */
int timer_init(void)
{
- /* Load timer with initial value */
- writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16);
-
- /*
- * Set timer to be enabled, free-running, no interrupts, 256 divider,
- * 32-bit, wrap-mode
- */
- writel(0x8a, CONFIG_SYS_TIMERBASE + 24);
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
+ writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
+ CONFIG_SYS_TIMERBASE + MTU_CR(0));
+ reset_timer();
return 0;
}
-/*
- * timer without interrupts
- */
+/* Restart counting from 0 */
void reset_timer(void)
{
- reset_timer_masked();
+ writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */
}
+/* Return how many HZ passed since "base" */
ulong get_timer(ulong base)
{
- return get_timer_masked() - base;
+ return TICKS_TO_HZ(READ_TIMER()) - base;
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
+/* Delay x useconds */
void udelay(unsigned long usec)
{
- ulong tmo, tmp;
-
- if (usec >= 1000) {
- /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
- tmo /= 1000; /* finish normalize. */
- } else {
- /* small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000 * 1000);
- }
-
- tmp = get_timer(0); /* get current timestamp */
- if ((tmo + tmp + 1) < tmp) /* will roll time stamp? */
- reset_timer_masked(); /* reset to 0, set lastdec value */
- else
- tmo += tmp;
-
- while (get_timer_masked() < tmo)
- /* nothing */ ;
-}
-
-void reset_timer_masked(void)
-{
- /* reset time */
- lastdec = READ_TIMER; /* capure current decrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (lastdec >= now) { /* normal mode (non roll) */
- /* move stamp fordward */
- timestamp += lastdec - now;
- } else {
- /*
- * An overflow is expected.
- * nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll
- */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked(unsigned long usec)
-{
- ulong tmo;
-
- if (usec >= 1000) {
- /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
- tmo /= 1000; /* finish normalize. */
- } else {
- /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- reset_timer_masked();
- /* set "advancing" timestamp to 0, set lastdec vaule */
-
- while (get_timer_masked() < tmo)
- /* nothing */ ;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
+ ulong ini, end;
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
+ ini = READ_TIMER();
+ end = ini + USEC_TO_COUNT(usec);
+ while ((signed)(end - READ_TIMER()) > 0)
+ ;
}
#include <common.h>
#include <command.h>
-#include <asm/arch/sys_proto.h>
#include <asm/system.h>
-
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
+#include <asm/cache.h>
static void cache_flush(void);
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
#ifndef CONFIG_L2_OFF
- l2cache_enable();
+ l2_cache_enable();
#endif
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() >= CPU_3XX_ES20) {
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- __asm__ __volatile__("orr r0, r0, #0x2");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() >= CPU_3XX_ES20) {
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- __asm__ __volatile__("bic r0, r0, #0x2");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
- }
-}
-
static void cache_flush(void)
{
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
SOBJS := lowlevel_init.o
COBJS += board.o
+COBJS += cache.o
COBJS += clock.o
COBJS += gpio.o
COBJS += mem.o
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
+#include <asm/cache.h>
extern omap3_sysinfo sysinfo;
#endif
#ifdef CONFIG_L2_OFF
- l2cache_disable();
+ l2_cache_disable();
#else
- l2cache_enable();
+ l2_cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV
--- /dev/null
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * omap3 L2 cache code
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
+
+void l2_cache_enable(void)
+{
+ unsigned long i;
+ volatile unsigned int j;
+
+ /* ES2 onwards we can disable/enable L2 ourselves */
+ if (get_cpu_rev() >= CPU_3XX_ES20) {
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+ } else {
+ /* Save r0, r12 and restore them after usage */
+ __asm__ __volatile__("mov %0, r12":"=r"(j));
+ __asm__ __volatile__("mov %0, r0":"=r"(i));
+
+ /*
+ * GP Device ROM code API usage here
+ * r12 = AUXCR Write function and r0 value
+ */
+ __asm__ __volatile__("mov r12, #0x3");
+ __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+ __asm__ __volatile__("orr r0, r0, #0x2");
+ /* SMI instruction to call ROM Code API */
+ __asm__ __volatile__(".word 0xE1600070");
+ __asm__ __volatile__("mov r0, %0":"=r"(i));
+ __asm__ __volatile__("mov r12, %0":"=r"(j));
+ }
+
+}
+
+void l2_cache_disable(void)
+{
+ unsigned long i;
+ volatile unsigned int j;
+
+ /* ES2 onwards we can disable/enable L2 ourselves */
+ if (get_cpu_rev() >= CPU_3XX_ES20) {
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+ } else {
+ /* Save r0, r12 and restore them after usage */
+ __asm__ __volatile__("mov %0, r12":"=r"(j));
+ __asm__ __volatile__("mov %0, r0":"=r"(i));
+
+ /*
+ * GP Device ROM code API usage here
+ * r12 = AUXCR Write function and r0 value
+ */
+ __asm__ __volatile__("mov r12, #0x3");
+ __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+ __asm__ __volatile__("bic r0, r0, #0x2");
+ /* SMI instruction to call ROM Code API */
+ __asm__ __volatile__(".word 0xE1600070");
+ __asm__ __volatile__("mov r0, %0":"=r"(i));
+ __asm__ __volatile__("mov r12, %0":"=r"(j));
+ }
+}
}
#endif
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 dmamr0 = swab32(dma->dmamr0);
-
- debug("DMA-init\n");
-
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = (u32)0;
- dma->dmasar0 = (u32)0;
- dma->dmabcr0 = 0;
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* clear CS bit */
- dmamr0 &= ~DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* while the channel is busy, spin */
- while(status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
-
- debug("DMA-init end\n");
-}
-
-uint dma_check(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 byte_count = swab32(dma->dmabcr0);
-
- /* while the channel is busy, spin */
- while (status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
-
- if (status & DMA_CHANNEL_TRANSFER_ERROR) {
- printf ("DMA Error: status = %x @ %d\n", status, byte_count);
- }
-
- return status;
-}
-
-int dma_xfer(void *dest, u32 count, void *src)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 dmamr0;
-
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = swab32((u32)dest);
- dma->dmasar0 = swab32((u32)src);
- dma->dmabcr0 = swab32(count);
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* init direct transfer, clear CS bit */
- dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
- DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
- DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
-
- dma->dmamr0 = swab32(dmamr0);
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* set CS to start DMA transfer */
- dmamr0 |= DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- return ((int)dma_check());
-}
-#endif /*CONFIG_DDR_ECC*/
-
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
}
#ifdef CONFIG_SPD_EEPROM
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dma_xfer(void *dest, uint count, void *src);
-#endif
-
#ifndef CONFIG_SYS_READ_SPD
#define CONFIG_SYS_READ_SPD i2c_read
#endif
}
#endif /* CONFIG_SPD_EEPROM */
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Use timebase counter, get_timer() is not availabe
* at this point of initialization yet.
/*
* Initialize all of memory for ECC, then enable errors.
*/
-/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
void ddr_enable_ecc(unsigned int dram_size)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
register u64 *p;
register uint size;
unsigned int pattern[2];
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
- uint i;
-#endif
+
icache_enable();
t_start = get_tbms();
pattern[0] = 0xdeadbeef;
pattern[1] = 0xdeadbeef;
-#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+ dma_meminit(pattern[0], dram_size);
+#else
debug("ddr init: CPU FP write method\n");
size = dram_size;
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
__asm__ __volatile__ ("sync");
-#else
- debug("ddr init: DMA method\n");
- size = 0x2000;
- for (p = 0; p < (u64*)(size); p++) {
- ppcDWstore((u32*)p, pattern);
- }
- __asm__ __volatile__ ("sync");
-
- /* Initialise DMA for direct transfer */
- dma_init();
- /* Start DMA to transfer */
- dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
- dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
- dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
- dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
- dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
- dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
- dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
- dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
- dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
- dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
-
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
- }
#endif
t_end = get_tbms();
}
#endif /* CONFIG_WATCHDOG */
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->satr = 0x00040000;
- dma->datr = 0x00040000;
- dma->sr = 0xffffffff; /* clear any errors */
- asm("sync; isync; msync");
- return;
-}
-
-uint dma_check(void) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
- volatile uint status = dma->sr;
-
- /* While the channel is busy, spin */
- while((status & 4) == 4) {
- status = dma->sr;
- }
-
- /* clear MR[CS] channel start bit */
- dma->mr &= 0x00000001;
- asm("sync;isync;msync");
-
- if (status != 0) {
- printf ("DMA Error: status = %x\n", status);
- }
- return status;
-}
-
-int dma_xfer(void *dest, uint count, void *src) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->dar = (uint) dest;
- dma->sar = (uint) src;
- dma->bcr = count;
- dma->mr = 0xf000004;
- asm("sync;isync;msync");
- dma->mr = 0xf000005;
- asm("sync;isync;msync");
- return dma_check();
-}
-#endif
-
/*
* Configures a UPM. The function requires the respective MxMR to be set
* before calling this function. "size" is the number or entries, not a sizeof.
#if defined(CONFIG_MPC8536)
fsl_serdes_init();
#endif
-
+#if defined(CONFIG_FSL_DMA)
+ dma_init();
+#endif
}
}
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dma_xfer(void *dest, uint count, void *src);
-
/*
* Initialize all of memory for ECC, then enable errors.
*/
void
ddr_enable_ecc(unsigned int dram_size)
{
- uint *p = 0;
- uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
-
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) {
- ppcDcbz((unsigned long) p);
- }
- *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
- if (((unsigned int)p & 0x1c) == 0x1c) {
- ppcDcbf((unsigned long) p);
- }
- }
-
- dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
- dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
- dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
- dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
- dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
- dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
- dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
- dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
- dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
- dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
-
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
- }
+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/*
* Enable errors for ECC.
#include <tsec.h>
#include <asm/fsl_law.h>
+struct cpu_type cpu_type_list [] = {
+ CPU_TYPE_ENTRY(8610, 8610),
+ CPU_TYPE_ENTRY(8641, 8641),
+ CPU_TYPE_ENTRY(8641D, 8641D),
+};
+
+struct cpu_type *identify_cpu(u32 ver)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+ if (cpu_type_list[i].soc_ver == ver)
+ return &cpu_type_list[i];
+
+ return NULL;
+}
/*
* Default board reset function
char buf1[32], buf2[32];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
+ struct cpu_type *cpu;
uint msscr0 = mfspr(MSSCR0);
svr = get_svr();
puts("CPU: ");
- switch (ver) {
- case SVR_8641:
- puts("8641");
- break;
- case SVR_8641D:
- puts("8641D");
- break;
- case SVR_8610:
- puts("8610");
- break;
- default:
+ cpu = identify_cpu(ver);
+ if (cpu) {
+ puts(cpu->name);
+ } else {
puts("Unknown");
- break;
}
+
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
puts("Core: ");
}
#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_DDR_ECC)
-void
-dma_init(void)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->satr = 0x00040000;
- dma->datr = 0x00040000;
- dma->sr = 0xffffffff; /* clear any errors */
- asm("sync; isync");
-}
-
-uint
-dma_check(void)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
- volatile uint status = dma->sr;
-
- /* While the channel is busy, spin */
- while ((status & 4) == 4) {
- status = dma->sr;
- }
-
- /* clear MR[CS] channel start bit */
- dma->mr &= 0x00000001;
- asm("sync;isync");
-
- if (status != 0) {
- printf("DMA Error: status = %x\n", status);
- }
- return status;
-}
-
-int
-dma_xfer(void *dest, uint count, void *src)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->dar = (uint) dest;
- dma->sar = (uint) src;
- dma->bcr = count;
- dma->mr = 0xf000004;
- asm("sync;isync");
- dma->mr = 0xf000005;
- asm("sync;isync");
- return dma_check();
-}
-
-#endif /* CONFIG_DDR_ECC */
-
-
/*
* Print out the state of various machine registers.
* Currently prints out LAWs, BR0/OR0, and BATs
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
+#if defined(CONFIG_FSL_DMA)
+ dma_init();
+#endif
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
if ((spd->organization & 0x7) < 4)
nbit_sdram_width = (spd->organization & 0x7) + 2;
- bsize = 1 << (nbit_sdram_cap_bsize - 3
+ bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width);
debug("DDR: DDR III rank density = 0x%08x\n", bsize);
If the LED support is only for a single board, define CONFIG_BOARD_SPECIFIC_LED
in the board config file.
-At a minimum, these macros must be defined at
+At a minimum, these macros must be defined at
STATUS_LED_BIT
STATUS_LED_STATE
STATUS_LED_PERIOD
STATUS_LED_STATE<n>
STATUS_LED_PERIOD<n>
-Where <n> can a integer 1 through 3.
+Where <n> can a integer 1 through 3.
STATUS_LED_BIT is passed into the __led_* functions to identify which LED is
being acted on. As such, the value choose must be unique with with respect to
Some other LED macros
STATUS_LED_BOOT is the LED to light when the board is booting. This must be a
-valid STATUS_LED_BIT value.
+valid STATUS_LED_BIT value.
STATUS_LED_RED is the red LED. It is used signal errors. This must be a valid
STATUS_LED_BIT value. Other similar color LED's are STATUS_LED_YELLOW and
-STATUS_LED_BLUE.
+STATUS_LED_BLUE.
These board must define these functions
__led_init is called once to initialize the LED to STATUS_LED_STATE. One time
start up code should be placed here.
-__led_set is called to change the state of the LED.
+__led_set is called to change the state of the LED.
__led_toggle is called to toggle the current state of the LED.
Colour LED
========================================
-Colour LED's are at present only used by ARM.
+Colour LED's are at present only used by ARM.
The functions names explain their purpose.
U-Boot environment variables can be stored at different places:
- Dataflash on SPI chip select 0 (dataflash card)
- Nand flash.
+ - Nor falsh (not populate by default)
You can choose your storage location at config step (here for at91sam9260ek) :
make at91sam9263ek_config - use data flash (spi cs0) (default)
make at91sam9263ek_nandflash_config - use nand flash
make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
+ make at91sam9263ek_norflash_config - use nor falsh
+
+ You can choose to boot directly from U-Boot at config step
+ make at91sam9263ek_norflash_boot_config - boot from nor falsh
------------------------------------------------------------------------------
implemented in the X-Loader, so U-Boot is already running in SDRAM
when control is handed over to it.
+The Makefile offers two different configurations to be used if you
+boot from Nand or OneNand.
+
+ make nhk8815_config
+ make nhk8815_onenand_config
+
+Both support OneNand and Nand. Since U-Boot, running in RAM, can't know
+where it was loaded from, the configurations differ in where the filesystem
+is looked for by default.
+
On www.st.com/nomadik and on www.stnwireless.com there are documents,
summary data and white papers on Nomadik. The full datasheet for
[8] TI OMAP3 U-Boot:
http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz
-
LIB := $(obj)libdma.a
COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
+COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
+ * (C) Copyright 2002, 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_dma.h>
+
+/* Controller can only transfer 2^26 - 1 bytes at a time */
+#define FSL_DMA_MAX_SIZE (0x3ffffff)
+
+#if defined(CONFIG_MPC83xx)
+#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
+#else
+#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
+#endif
+
+
+#if defined(CONFIG_MPC83xx)
+dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
+#elif defined(CONFIG_MPC85xx)
+ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+#elif defined(CONFIG_MPC86xx)
+ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
+#else
+#error "Freescale DMA engine not supported on your processor"
+#endif
+
+static void dma_sync(void)
+{
+#if defined(CONFIG_MPC85xx)
+ asm("sync; isync; msync");
+#elif defined(CONFIG_MPC86xx)
+ asm("sync; isync");
+#endif
+}
+
+static void out_dma32(volatile unsigned *addr, int val)
+{
+#if defined(CONFIG_MPC83xx)
+ out_le32(addr, val);
+#else
+ out_be32(addr, val);
+#endif
+}
+
+static uint in_dma32(volatile unsigned *addr)
+{
+#if defined(CONFIG_MPC83xx)
+ return in_le32(addr);
+#else
+ return in_be32(addr);
+#endif
+}
+
+static uint dma_check(void) {
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
+ uint status;
+
+ /* While the channel is busy, spin */
+ do {
+ status = in_dma32(&dma->sr);
+ } while (status & FSL_DMA_SR_CB);
+
+ /* clear MR[CS] channel start bit */
+ out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
+ dma_sync();
+
+ if (status != 0)
+ printf ("DMA Error: status = %x\n", status);
+
+ return status;
+}
+
+#if !defined(CONFIG_MPC83xx)
+void dma_init(void) {
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
+
+ out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
+ out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
+ out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
+ dma_sync();
+}
+#endif
+
+int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
+ uint xfer_size;
+
+ while (count) {
+ xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
+
+ out_dma32(&dma->dar, (uint) dest);
+ out_dma32(&dma->sar, (uint) src);
+ out_dma32(&dma->bcr, xfer_size);
+ dma_sync();
+
+ /* Prepare mode register */
+ out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
+ dma_sync();
+
+ /* Start the transfer */
+ out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
+
+ count -= xfer_size;
+ src += xfer_size;
+ dest += xfer_size;
+
+ dma_sync();
+
+ if (dma_check())
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+ * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
+ */
+#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
+ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
+ (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+void dma_meminit(uint val, uint size)
+{
+ uint *p = 0;
+ uint i = 0;
+
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((uint)p & 0x1f) == 0)
+ ppcDcbz((ulong)p);
+
+ *p = (uint)CONFIG_MEM_INIT_VALUE;
+
+ if (((uint)p & 0x1c) == 0x1c)
+ ppcDcbf((ulong)p);
+ }
+
+ dmacpy(0x002000, 0, 0x002000); /* 8K */
+ dmacpy(0x004000, 0, 0x004000); /* 16K */
+ dmacpy(0x008000, 0, 0x008000); /* 32K */
+ dmacpy(0x010000, 0, 0x010000); /* 64K */
+ dmacpy(0x020000, 0, 0x020000); /* 128K */
+ dmacpy(0x040000, 0, 0x040000); /* 256K */
+ dmacpy(0x080000, 0, 0x080000); /* 512K */
+ dmacpy(0x100000, 0, 0x100000); /* 1M */
+ dmacpy(0x200000, 0, 0x200000); /* 2M */
+ dmacpy(0x400000, 0, 0x400000); /* 4M */
+
+ for (i = 1; i < size / 0x800000; i++)
+ dmacpy((0x800000 * i), 0, 0x800000);
+}
+#endif
/* prime the pump */
if (msg.alen) {
- len = msg.alen;
+ len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
debugi("first byte=0x%02x", *msg.abuf);
bfin_write_TWI_XMT_DATA8(*(msg.abuf++));
--msg.alen;
* @chip: i2c chip addr
* @addr: memory (register) address in the chip
* @alen: byte size of address
- * @buffer: buffer to store data read from chip
+ * @buffer: buffer holding data to write to chip
* @len: how many bytes to write
* @return: 0 on success, non-0 on failure
*/
static void nand_flash_init(void)
{
u_int32_t acfg1 = 0x3ffffffc;
- u_int32_t acfg2 = 0x3ffffffc;
- u_int32_t acfg3 = 0x3ffffffc;
- u_int32_t acfg4 = 0x3ffffffc;
emifregs emif_regs;
/*------------------------------------------------------------------*
emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
- emif_regs->AWCCR |= 0x10000000;
- emif_regs->AB1CR = acfg1; /* 0x08244128 */;
- emif_regs->AB2CR = acfg2;
- emif_regs->AB3CR = acfg3;
- emif_regs->AB4CR = acfg4;
- emif_regs->NANDFCR = 0x00000101;
+ emif_regs->AB1CR = acfg1; /* CS2 */
+
+ emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
}
int board_nand_init(struct nand_chip *nand)
#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */
#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */
-#define MXIC_ID_MX2516 0x15
-#define MXIC_ID_MX2520 0x12
-#define MXIC_ID_MX2532 0x16
-#define MXIC_ID_MX2540 0x13
-#define MXIC_ID_MX2564 0x17
-#define MXIC_ID_MX2580 0x14
-#define MXIC_ID_MX25128 0x18
-
#define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */
struct macronix_spi_flash_params {
- u8 idcode1;
+ u16 idcode;
u16 page_size;
u16 pages_per_sector;
u16 sectors_per_block;
static const struct macronix_spi_flash_params macronix_spi_flash_table[] = {
{
- .idcode1 = MXIC_ID_MX25128,
+ .idcode = 0x2015,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "MX25L1605D",
+ },
+ {
+ .idcode = 0x2016,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "MX25L3205D",
+ },
+ {
+ .idcode = 0x2017,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "MX25L6405D",
+ },
+ {
+ .idcode = 0x2018,
.page_size = 256,
.pages_per_sector = 16,
.sectors_per_block = 16,
.nr_blocks = 256,
.name = "MX25L12805D",
},
+ {
+ .idcode = 0x2618,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 256,
+ .name = "MX25L12855E",
+ },
};
static int macronix_wait_ready(struct spi_flash *flash, unsigned long timeout)
const struct macronix_spi_flash_params *params;
struct macronix_spi_flash *mcx;
unsigned int i;
+ u16 id = idcode[2] | idcode[1] << 8;
for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) {
params = ¯onix_spi_flash_table[i];
- if (params->idcode1 == idcode[2])
+ if (params->idcode == id)
break;
}
if (i == ARRAY_SIZE(macronix_spi_flash_table)) {
- debug("SF: Unsupported Macronix ID %02x\n", idcode[1]);
+ debug("SF: Unsupported Macronix ID %04x\n", id);
return NULL;
}
#define SST_SECTOR_SIZE (4 * 1024)
static const struct sst_spi_flash_params sst_spi_flash_table[] = {
{
- .idcode1 = 0x01,
+ .idcode1 = 0x8d,
.nr_sectors = 128,
+ .name = "SST25VF040B",
+ },{
+ .idcode1 = 0x8e,
+ .nr_sectors = 256,
+ .name = "SST25VF080B",
+ },{
+ .idcode1 = 0x41,
+ .nr_sectors = 512,
+ .name = "SST25VF016B",
+ },{
+ .idcode1 = 0x4a,
+ .nr_sectors = 1024,
+ .name = "SST25VF032B",
+ },{
+ .idcode1 = 0x01,
+ .nr_sectors = 16,
.name = "SST25WF512",
},{
.idcode1 = 0x02,
- .nr_sectors = 256,
+ .nr_sectors = 32,
.name = "SST25WF010",
},{
.idcode1 = 0x03,
- .nr_sectors = 512,
+ .nr_sectors = 64,
.name = "SST25WF020",
},{
.idcode1 = 0x04,
- .nr_sectors = 1024,
+ .nr_sectors = 128,
.name = "SST25WF040",
},
};
*/
ubi->peb_size = ubi->mtd->erasesize;
- ubi->peb_count = ubi->mtd->size / ubi->mtd->erasesize;
+ ubi->peb_count = mtd_div_by_eb(ubi->mtd->size, ubi->mtd);
ubi->flash_size = ubi->mtd->size;
if (ubi->mtd->block_isbad && ubi->mtd->block_markbad)
{
return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
}
-
-
COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
-COBJS-$(CONFIG_MX31_UART) += serial_mx31.o
+COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
#ifdef CONFIG_NS87308
#include <ns87308.h>
#endif
+#ifdef CONFIG_KIRKWOOD
+#include <asm/arch/kirkwood.h>
+#endif
#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
*/
#include <common.h>
+#ifdef CONFIG_MX31
#include <asm/arch/mx31.h>
+#else
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#endif
#define __REG(x) (*((volatile u32 *)(x)))
#define UART_PHYS 0x43fb0000
#elif defined(CONFIG_SYS_MX31_UART5)
#define UART_PHYS 0x43fb4000
+#elif defined(CONFIG_SYS_MX27_UART1)
+#define UART_PHYS 0x1000a000
+#elif defined(CONFIG_SYS_MX27_UART2)
+#define UART_PHYS 0x1000b000
+#elif defined(CONFIG_SYS_MX27_UART3)
+#define UART_PHYS 0x1000c000
+#elif defined(CONFIG_SYS_MX27_UART4)
+#define UART_PHYS 0x1000d000
+#elif defined(CONFIG_SYS_MX27_UART5)
+#define UART_PHYS 0x1001b000
+#elif defined(CONFIG_SYS_MX27_UART6)
+#define UART_PHYS 0x1001c000
#else
#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
#endif
void serial_setbrg (void)
{
+#ifdef CONFIG_MX31
u32 clk = mx31_get_ipg_clk();
+#else
+ u32 clk = imx_get_perclk1();
+#endif
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
+COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Derived from drivers/spi/mpc8xxx_spi.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/spi.h>
+#include <asm/arch/mpp.h>
+
+static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct spi_slave *slave;
+ u32 data;
+ u32 kwspi_mpp_config[] = {
+ MPP0_GPIO,
+ MPP7_SPI_SCn,
+ 0
+ };
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ slave->bus = bus;
+ slave->cs = cs;
+
+ writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+
+ /* calculate spi clock prescaller using max_hz */
+ data = ((CONFIG_SYS_TCLK / 2) / max_hz) & KWSPI_CLKPRESCL_MASK;
+ data |= 0x10;
+
+ /* program spi clock prescaller using max_hz */
+ writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
+ debug("data = 0x%08x \n", data);
+
+ writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
+ writel(KWSPI_IRQMASK, spireg->irq_mask);
+
+ /* program mpp registers to select SPI_CSn */
+ if (cs) {
+ kwspi_mpp_config[0] = MPP0_GPIO;
+ kwspi_mpp_config[1] = MPP7_SPI_SCn;
+ } else {
+ kwspi_mpp_config[0] = MPP0_SPI_SCn;
+ kwspi_mpp_config[1] = MPP7_GPO;
+ }
+ kirkwood_mpp_conf(kwspi_mpp_config);
+
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+#ifndef CONFIG_SPI_CS_IS_VALID
+/*
+ * you can define this function board specific
+ * define above CONFIG in board specific config file and
+ * provide the function in board specific src file
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return (bus == 0 && (cs == 0 || cs == 1));
+}
+#endif
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ writel(readl(&spireg->ctrl) & KWSPI_IRQMASK, &spireg->ctrl);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ unsigned int tmpdout, tmpdin;
+ int tm, isread = 0;
+
+ debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+ slave->bus, slave->cs, dout, din, bitlen);
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ /*
+ * handle data in 8-bit chunks
+ * TBD: 2byte xfer mode to be enabled
+ */
+ writel(((readl(&spireg->cfg) & ~KWSPI_XFERLEN_MASK) |
+ KWSPI_XFERLEN_1BYTE), &spireg->cfg);
+
+ while (bitlen > 4) {
+ debug("loopstart bitlen %d\n", bitlen);
+ tmpdout = 0;
+
+ /* Shift data so it's msb-justified */
+ if (dout)
+ tmpdout = *(u32 *) dout & 0x0ff;
+
+ writel(~KWSPI_SMEMRDIRQ, &spireg->irq_cause);
+ writel(tmpdout, &spireg->dout); /* Write the data out */
+ debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+ tmpdout, bitlen);
+
+ /*
+ * Wait for SPI transmit to get out
+ * or time out (1 second = 1000 ms)
+ * The NE event must be read and cleared first
+ */
+ for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
+ if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
+ isread = 1;
+ tmpdin = readl(&spireg->din);
+ debug
+ ("spi_xfer: din %08x..%08x read\n",
+ din, tmpdin);
+
+ if (din) {
+ *((u8 *) din) = (u8) tmpdin;
+ din += 1;
+ }
+ if (dout)
+ dout += 1;
+ bitlen -= 8;
+ }
+ if (isread)
+ break;
+ }
+ if (tm >= KWSPI_TIMEOUT)
+ printf("*** spi_xfer: Time out during SPI transfer\n");
+
+ debug("loopend bitlen %d\n", bitlen);
+ }
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Frank Bodammer <frank.bodammer@gcd-solutions.de>
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <spi.h>
+#include <mpc5xxx.h>
+
+void spi_init(void)
+{
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI;
+ /*
+ * Its important to use the correct order when initializing the
+ * registers
+ */
+ out_8(&spi->ddr, 0x0F); /* set all SPI pins as output */
+ out_8(&spi->pdr, 0x00); /* set SS low */
+ /* SPI is master, SS is general purpose output */
+ out_8(&spi->cr1, SPI_CR_MSTR | SPI_CR_SPE);
+ out_8(&spi->cr2, 0x00); /* normal operation */
+ out_8(&spi->brr, 0x77); /* baud rate: IPB clock / 2048 */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct spi_slave *slave;
+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ slave->bus = bus;
+ slave->cs = cs;
+
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ return;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI;
+ int i, iter = bitlen >> 3;
+ const uchar *txp = dout;
+ uchar *rxp = din;
+
+ debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+ slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
+
+ if (flags & SPI_XFER_BEGIN)
+ setbits_8(&spi->pdr, SPI_PDR_SS);
+
+ for (i = 0; i < iter; i++) {
+ udelay(1000);
+ debug("spi_xfer: sending %x\n", txp[i]);
+ out_8(&spi->dr, txp[i]);
+ while (!(in_8(&spi->sr) & SPI_SR_SPIF)) {
+ udelay(1000);
+ if (in_8(&spi->sr) & SPI_SR_WCOL) {
+ rxp[i] = in_8(&spi->dr);
+ puts("spi_xfer: write collision\n");
+ return -1;
+ }
+ }
+ rxp[i] = in_8(&spi->dr);
+ debug("spi_xfer: received %x\n", rxp[i]);
+ }
+ if (flags & SPI_XFER_END)
+ clrbits_8(&spi->pdr, SPI_PDR_SS);
+
+ return 0;
+}
#ifndef AT91_COMMON_H
#define AT91_COMMON_H
+void at91_can_hw_init(void);
void at91_macb_hw_init(void);
void at91_serial_hw_init(void);
void at91_serial0_hw_init(void);
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
+#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
--- /dev/null
+/*
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
+#define __ASM_ARCH_AT91SAM9_MATRIX_H
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#include <asm/arch/at91sam9260_matrix.h>
+#elif defined(CONFIG_AT91SAM9261)
+#include <asm/arch/at91sam9261_matrix.h>
+#elif defined(CONFIG_AT91SAM9263)
+#include <asm/arch/at91sam9263_matrix.h>
+#elif defined(CONFIG_AT91SAM9RL)
+#include <asm/arch/at91sam9rl_matrix.h>
+#elif defined(CONFIG_AT91CAP9)
+#include <asm/arch/at91cap9_matrix.h>
+#else
+#error "Unsupported AT91SAM9/CAP9 processor"
+#endif
+
+#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _KWCPU_H
+#define _KWCPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+ | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
+
+#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
+ ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
+
+#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
+#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
+
+enum memory_bank {
+ BANK0,
+ BANK1,
+ BANK2,
+ BANK3
+};
+
+enum kwcpu_winen {
+ KWCPU_WIN_DISABLE,
+ KWCPU_WIN_ENABLE
+};
+
+enum kwcpu_target {
+ KWCPU_TARGET_RESERVED,
+ KWCPU_TARGET_MEMORY,
+ KWCPU_TARGET_1RESERVED,
+ KWCPU_TARGET_SASRAM,
+ KWCPU_TARGET_PCIE
+};
+
+enum kwcpu_attrib {
+ KWCPU_ATTR_SASRAM = 0x01,
+ KWCPU_ATTR_DRAM_CS0 = 0x0e,
+ KWCPU_ATTR_DRAM_CS1 = 0x0d,
+ KWCPU_ATTR_DRAM_CS2 = 0x0b,
+ KWCPU_ATTR_DRAM_CS3 = 0x07,
+ KWCPU_ATTR_NANDFLASH = 0x2f,
+ KWCPU_ATTR_SPIFLASH = 0x1e,
+ KWCPU_ATTR_BOOTROM = 0x1d,
+ KWCPU_ATTR_PCIE_IO = 0xe0,
+ KWCPU_ATTR_PCIE_MEM = 0xe8
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define KW_DEFADR_PCI_MEM 0x90000000
+#define KW_DEFADR_PCI_IO 0xC0000000
+#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
+#define KW_DEFADR_SASRAM 0xC8010000
+#define KW_DEFADR_NANDF 0xD8000000
+#define KW_DEFADR_SPIF 0xE8000000
+#define KW_DEFADR_BOOTROM 0xF8000000
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+ unsigned int val;
+ asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
+ (val)::"cc");
+ return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
+ (val):"cc");
+ isb();
+}
+
+/*
+ * MBus-L to Mbus Bridge Registers
+ * Ref: Datasheet sec:A.3
+ */
+struct kwwin_registers {
+ u32 ctrl;
+ u32 base;
+ u32 remap_lo;
+ u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ * Ref: Datasheet sec:A.3.2
+ */
+struct kwcpu_registers {
+ u32 config; /*0x20100 */
+ u32 ctrl_stat; /*0x20104 */
+ u32 rstoutn_mask; /* 0x20108 */
+ u32 sys_soft_rst; /* 0x2010C */
+ u32 ahb_mbus_cause_irq; /* 0x20110 */
+ u32 ahb_mbus_mask_irq; /* 0x20114 */
+ u32 pad1[2];
+ u32 ftdll_config; /* 0x20120 */
+ u32 pad2;
+ u32 l2_cfg; /* 0x20128 */
+};
+
+/*
+ * GPIO Registers
+ * Ref: Datasheet sec:A.19
+ */
+struct kwgpio_registers {
+ u32 dout;
+ u32 oe;
+ u32 blink_en;
+ u32 din_pol;
+ u32 din;
+ u32 irq_cause;
+ u32 irq_mask;
+ u32 irq_level;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+unsigned char get_random_hex(void);
+unsigned int kw_sdram_bar(enum memory_bank bank);
+unsigned int kw_sdram_bs(enum memory_bank bank);
+int kw_config_adr_windows(void);
+void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
+ unsigned int gpp0_oe, unsigned int gpp1_oe);
+int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
+ unsigned int mpp16_23, unsigned int mpp24_31,
+ unsigned int mpp32_39, unsigned int mpp40_47,
+ unsigned int mpp48_55);
+unsigned int kw_winctrl_calcsize(unsigned int sizeval);
+#endif /* __ASSEMBLY__ */
+#endif /* _KWCPU_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for the Marvell's Feroceon CPU core.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_KIRKWOOD_H
+#define _ASM_ARCH_KIRKWOOD_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
+#include <asm/arch/cpu.h>
+
+/* SOC specific definations */
+#define INTREG_BASE 0xd0000000
+#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x)
+#define KW_OFFSET_REG (INTREG_BASE + 0x20080)
+
+/* undocumented registers */
+#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
+#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
+
+#define KW_UART0_BASE (KW_REGISTER(0x12000))
+#define KW_UART1_BASE (KW_REGISTER(0x13000))
+#define KW_MPP_BASE (KW_REGISTER(0x10000))
+#define KW_GPIO0_BASE (KW_REGISTER(0x10100))
+#define KW_GPIO1_BASE (KW_REGISTER(0x10140))
+#define KW_NANDF_BASE (KW_REGISTER(0x10418))
+#define KW_SPI_BASE (KW_REGISTER(0x10600))
+#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000))
+#define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
+#define KW_TIMER_BASE (KW_REGISTER(0x20300))
+#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
+#define KW_USB20_BASE (KW_REGISTER(0x50000))
+#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
+#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
+
+#if defined (CONFIG_KW88F6281)
+#include <asm/arch/kw88f6281.h>
+#elif defined (CONFIG_KW88F6192)
+#include <asm/arch/kw88f6192.h>
+#else
+#error "SOC Name not defined"
+#endif /* CONFIG_KW88F6281 */
+#endif /* CONFIG_FEROCEON_88FR131 */
+#endif /* _ASM_ARCH_KIRKWOOD_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_KW88F6192_H
+#define _CONFIG_KW88F6192_H
+
+/* SOC specific definations */
+#define KW88F6192_REGS_PHYS_BASE 0xf1000000
+#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination */
+#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+
+#endif /* _CONFIG_KW88F6192_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_KW88F6281_H
+#define _ASM_ARCH_KW88F6281_H
+
+/* SOC specific definations */
+#define KW88F6281_REGS_PHYS_BASE 0xf1000000
+#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination*/
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+
+#endif /* _ASM_ARCH_KW88F6281_H */
--- /dev/null
+/*
+ * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
+ *
+ * Copyright 2009: Marvell Technology Group Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __KIRKWOOD_MPP_H
+#define __KIRKWOOD_MPP_H
+
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+ /* MPP number */ ((_num) & 0xff) | \
+ /* MPP select value */ (((_sel) & 0xf) << 8) | \
+ /* may be input signal */ ((!!(_in)) << 12) | \
+ /* may be output signal */ ((!!(_out)) << 13) | \
+ /* available on F6180 */ ((!!(_F6180)) << 14) | \
+ /* available on F6190 */ ((!!(_F6190)) << 15) | \
+ /* available on F6192 */ ((!!(_F6192)) << 16) | \
+ /* available on F6281 */ ((!!(_F6281)) << 17))
+
+#define MPP_NUM(x) ((x) & 0xff)
+#define MPP_SEL(x) (((x) >> 8) & 0xf)
+
+ /* num sel i o 6180 6190 6192 6281 */
+
+#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 )
+#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 )
+
+#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 )
+#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 )
+#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 )
+#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 )
+
+#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 )
+
+#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 )
+
+#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 )
+
+#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 )
+
+#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 )
+#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 )
+#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 )
+
+#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 )
+#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 )
+#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 )
+
+#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 )
+#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 )
+#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 )
+
+#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 )
+#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
+#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
+
+#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
+#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
+#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 )
+#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 )
+#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 )
+#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 )
+
+#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 )
+#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 )
+#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 )
+#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 )
+#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 )
+
+#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 )
+#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 )
+#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 )
+#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 )
+
+#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 )
+#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 )
+#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 )
+#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 )
+#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 )
+#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 )
+
+#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 )
+
+#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 )
+
+#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 )
+#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 )
+#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 )
+
+#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 )
+#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 )
+#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 )
+
+#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 )
+#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 )
+#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 )
+#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 )
+
+#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 )
+#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 )
+
+#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 )
+
+#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 )
+#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 )
+
+#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 )
+#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 )
+
+#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 )
+#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 )
+
+#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 )
+#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 )
+
+#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 )
+#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 )
+#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 )
+
+#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 )
+
+#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 )
+
+#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 )
+#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 )
+
+#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 )
+
+#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 )
+#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 )
+
+#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 )
+#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 )
+
+#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 )
+#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 )
+
+#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 )
+#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 )
+
+#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 )
+#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 )
+#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 )
+
+#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 )
+
+#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 )
+#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 )
+
+#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 )
+#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 )
+#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 )
+#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 )
+
+#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 )
+#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 )
+
+#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 )
+#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 )
+
+#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 )
+#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 )
+
+#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 )
+#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 )
+
+#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 )
+#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 )
+
+#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 )
+#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 )
+
+#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 )
+#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 )
+
+#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 )
+#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 )
+
+#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 )
+#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 )
+#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 )
+
+#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 )
+#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 )
+
+#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 )
+#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 )
+
+#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 )
+#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 )
+
+#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 )
+#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 )
+
+#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 )
+#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 )
+#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 )
+#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 )
+
+#define MPP_MAX 49
+
+void kirkwood_mpp_conf(unsigned int *mpp_list);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Derived from drivers/spi/mpc8xxx_spi.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __KW_SPI_H__
+#define __KW_SPI_H__
+
+/* SPI Registers on kirkwood SOC */
+struct kwspi_registers {
+ u32 ctrl; /* 0x10600 */
+ u32 cfg; /* 0x10604 */
+ u32 dout; /* 0x10608 */
+ u32 din; /* 0x1060c */
+ u32 irq_cause; /* 0x10610 */
+ u32 irq_mask; /* 0x10614 */
+};
+
+#define KWSPI_CLKPRESCL_MASK 0x1f
+#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
+#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
+#define KWSPI_XFERLEN_1BYTE 0
+#define KWSPI_XFERLEN_2BYTE (1 << 5)
+#define KWSPI_XFERLEN_MASK (1 << 5)
+#define KWSPI_ADRLEN_1BYTE 0
+#define KWSPI_ADRLEN_2BYTE 1 << 8
+#define KWSPI_ADRLEN_3BYTE 2 << 8
+#define KWSPI_ADRLEN_4BYTE 3 << 8
+#define KWSPI_ADRLEN_MASK 3 << 8
+#define KWSPI_TIMEOUT 10000
+
+#endif /* __KW_SPI_H__ */
--- /dev/null
+#define AIPI1_PSR0 0x10000000
+#define AIPI1_PSR1 0x10000004
+#define AIPI2_PSR0 0x10020000
+#define AIPI2_PSR1 0x10020004
+#define CSCR 0x10027000
+#define MPCTL0 0x10027004
+#define SPCTL0 0x1002700c
+#define PCDR0 0x10027018
+#define PCDR1 0x1002701c
+#define PCCR0 0x10027020
+#define PCCR1 0x10027024
+#define ESDCTL0_ROF 0x00
+#define ESDCFG0_ROF 0x04
+#define ESDCTL1_ROF 0x08
+#define ESDCFG1_ROF 0x0C
+#define ESDMISC_ROF 0x10
--- /dev/null
+/*
+ *
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+
+ulong imx_get_mpllclk(void);
+ulong imx_get_armclk(void);
+ulong imx_get_spllclk(void);
+ulong imx_get_fclk(void);
+ulong imx_get_hclk(void);
+ulong imx_get_bclk(void);
+ulong imx_get_perclk1(void);
+ulong imx_get_perclk2(void);
+ulong imx_get_perclk3(void);
+ulong imx_get_ahbclk(void);
+
+#endif /* __ASM_ARCH_CLOCK_H */
--- /dev/null
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#ifndef __ASSEMBLY__
+
+extern void imx_gpio_mode (int gpio_mode);
+
+/* AIPI */
+struct aipi_regs {
+ u32 psr0;
+ u32 psr1;
+};
+
+/* System Control */
+struct system_control_regs {
+ u32 res[5];
+ u32 fmcr;
+ u32 gpcr;
+ u32 wbcr;
+ u32 dscr1;
+ u32 dscr2;
+ u32 dscr3;
+ u32 dscr4;
+ u32 dscr5;
+ u32 dscr6;
+ u32 dscr7;
+ u32 dscr8;
+ u32 dscr9;
+ u32 dscr10;
+ u32 dscr11;
+ u32 dscr12;
+ u32 dscr13;
+ u32 pscr;
+ u32 pmcr;
+ u32 res1;
+ u32 dcvr0;
+ u32 dcvr1;
+ u32 dcvr2;
+ u32 dcvr3;
+};
+
+/* Chip Select Registers */
+struct weim_regs {
+ u32 cs0u; /* Chip Select 0 Upper Register */
+ u32 cs0l; /* Chip Select 0 Lower Register */
+ u32 cs0a; /* Chip Select 0 Addition Register */
+ u32 pad0;
+ u32 cs1u; /* Chip Select 1 Upper Register */
+ u32 cs1l; /* Chip Select 1 Lower Register */
+ u32 cs1a; /* Chip Select 1 Addition Register */
+ u32 pad1;
+ u32 cs2u; /* Chip Select 2 Upper Register */
+ u32 cs2l; /* Chip Select 2 Lower Register */
+ u32 cs2a; /* Chip Select 2 Addition Register */
+ u32 pad2;
+ u32 cs3u; /* Chip Select 3 Upper Register */
+ u32 cs3l; /* Chip Select 3 Lower Register */
+ u32 cs3a; /* Chip Select 3 Addition Register */
+ u32 pad3;
+ u32 cs4u; /* Chip Select 4 Upper Register */
+ u32 cs4l; /* Chip Select 4 Lower Register */
+ u32 cs4a; /* Chip Select 4 Addition Register */
+ u32 pad4;
+ u32 cs5u; /* Chip Select 5 Upper Register */
+ u32 cs5l; /* Chip Select 5 Lower Register */
+ u32 cs5a; /* Chip Select 5 Addition Register */
+ u32 pad5;
+ u32 eim; /* WEIM Configuration Register */
+};
+
+/* SDRAM Controller registers */
+struct esdramc_regs {
+/* Enhanced SDRAM Control Register 0 */
+ u32 esdctl0;
+/* Enhanced SDRAM Configuration Register 0 */
+ u32 esdcfg0;
+/* Enhanced SDRAM Control Register 1 */
+ u32 esdctl1;
+/* Enhanced SDRAM Configuration Register 1 */
+ u32 esdcfg1;
+/* Enhanced SDRAM Miscellanious Register */
+ u32 esdmisc;
+};
+
+/* Watchdog Registers*/
+struct wdog_regs {
+ u32 wcr;
+ u32 wsr;
+ u32 wstr;
+};
+
+/* PLL registers */
+struct pll_regs {
+ u32 cscr; /* Clock Source Control Register */
+ u32 mpctl0; /* MCU PLL Control Register 0 */
+ u32 mpctl1; /* MCU PLL Control Register 1 */
+ u32 spctl0; /* System PLL Control Register 0 */
+ u32 spctl1; /* System PLL Control Register 1 */
+ u32 osc26mctl; /* Oscillator 26M Register */
+ u32 pcdr0; /* Peripheral Clock Divider Register 0 */
+ u32 pcdr1; /* Peripheral Clock Divider Register 1 */
+ u32 pccr0; /* Peripheral Clock Control Register 0 */
+ u32 pccr1; /* Peripheral Clock Control Register 1 */
+ u32 ccsr; /* Clock Control Status Register */
+};
+
+/*
+ * Definitions for the clocksource registers
+ */
+struct gpt_regs {
+ u32 gpt_tctl;
+ u32 gpt_tprer;
+ u32 gpt_tcmp;
+ u32 gpt_tcr;
+ u32 gpt_tcn;
+ u32 gpt_tstat;
+};
+
+/*
+ * GPIO Module and I/O Multiplexer
+ */
+#define PORTA 0
+#define PORTB 1
+#define PORTC 2
+#define PORTD 3
+#define PORTE 4
+#define PORTF 5
+
+struct gpio_regs {
+ struct {
+ u32 ddir;
+ u32 ocr1;
+ u32 ocr2;
+ u32 iconfa1;
+ u32 iconfa2;
+ u32 iconfb1;
+ u32 iconfb2;
+ u32 dr;
+ u32 gius;
+ u32 ssr;
+ u32 icr1;
+ u32 icr2;
+ u32 imr;
+ u32 isr;
+ u32 gpr;
+ u32 swr;
+ u32 puen;
+ u32 res[0x2f];
+ } port[6];
+};
+
+/* IIM Control Registers */
+struct iim_regs {
+ u32 iim_stat;
+ u32 iim_statm;
+ u32 iim_err;
+ u32 iim_emask;
+ u32 iim_fctl;
+ u32 iim_ua;
+ u32 iim_la;
+ u32 iim_sdat;
+ u32 iim_prev;
+ u32 iim_srev;
+ u32 iim_prog_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+ u32 res[0x1F0];
+ u32 iim_bank_area0[0x100];
+};
+#endif
+
+#define IMX_IO_BASE 0x10000000
+
+#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
+#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
+#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
+#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
+#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
+#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
+#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
+#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
+#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
+#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
+#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
+#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
+#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
+#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
+#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
+#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
+#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
+#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
+
+#define IMX_ESD_BASE (0xD8001000)
+#define IMX_WEIM_BASE (0xD8002000)
+
+/* FMCR System Control bit definition*/
+#define UART4_RXD_CTL (1 << 25)
+#define UART4_RTS_CTL (1 << 24)
+#define KP_COL6_CTL (1 << 18)
+#define KP_ROW7_CTL (1 << 17)
+#define KP_ROW6_CTL (1 << 16)
+#define PC_WAIT_B_CTL (1 << 14)
+#define PC_READY_CTL (1 << 13)
+#define PC_VS1_CTL (1 << 12)
+#define PC_VS2_CTL (1 << 11)
+#define PC_BVD1_CTL (1 << 10)
+#define PC_BVD2_CTL (1 << 9)
+#define IOS16_CTL (1 << 8)
+#define NF_FMS (1 << 5)
+#define NF_16BIT_SEL (1 << 4)
+#define SLCDC_SEL (1 << 2)
+#define SDCS1_SEL (1 << 1)
+#define SDCS0_SEL (1 << 0)
+
+
+/* important definition of some bits of WCR */
+#define WCR_WDE 0x04
+
+#define CSCR_MPEN (1 << 0)
+#define CSCR_SPEN (1 << 1)
+#define CSCR_FPM_EN (1 << 2)
+#define CSCR_OSC26M_DIS (1 << 3)
+#define CSCR_OSC26M_DIV1P5 (1 << 4)
+#define CSCR_AHB_DIV
+#define CSCR_ARM_DIV
+#define CSCR_ARM_SRC_MPLL (1 << 15)
+#define CSCR_MCU_SEL (1 << 16)
+#define CSCR_SP_SEL (1 << 17)
+#define CSCR_MPLL_RESTART (1 << 18)
+#define CSCR_SPLL_RESTART (1 << 19)
+#define CSCR_MSHC_SEL (1 << 20)
+#define CSCR_H264_SEL (1 << 21)
+#define CSCR_SSI1_SEL (1 << 22)
+#define CSCR_SSI2_SEL (1 << 23)
+#define CSCR_SD_CNT
+#define CSCR_USB_DIV
+#define CSCR_UPDATE_DIS (1 << 31)
+
+#define MPCTL1_BRMO (1 << 6)
+#define MPCTL1_LF (1 << 15)
+
+#define PCCR0_SSI2_EN (1 << 0)
+#define PCCR0_SSI1_EN (1 << 1)
+#define PCCR0_SLCDC_EN (1 << 2)
+#define PCCR0_SDHC3_EN (1 << 3)
+#define PCCR0_SDHC2_EN (1 << 4)
+#define PCCR0_SDHC1_EN (1 << 5)
+#define PCCR0_SDC_EN (1 << 6)
+#define PCCR0_SAHARA_EN (1 << 7)
+#define PCCR0_RTIC_EN (1 << 8)
+#define PCCR0_RTC_EN (1 << 9)
+#define PCCR0_PWM_EN (1 << 11)
+#define PCCR0_OWIRE_EN (1 << 12)
+#define PCCR0_MSHC_EN (1 << 13)
+#define PCCR0_LCDC_EN (1 << 14)
+#define PCCR0_KPP_EN (1 << 15)
+#define PCCR0_IIM_EN (1 << 16)
+#define PCCR0_I2C2_EN (1 << 17)
+#define PCCR0_I2C1_EN (1 << 18)
+#define PCCR0_GPT6_EN (1 << 19)
+#define PCCR0_GPT5_EN (1 << 20)
+#define PCCR0_GPT4_EN (1 << 21)
+#define PCCR0_GPT3_EN (1 << 22)
+#define PCCR0_GPT2_EN (1 << 23)
+#define PCCR0_GPT1_EN (1 << 24)
+#define PCCR0_GPIO_EN (1 << 25)
+#define PCCR0_FEC_EN (1 << 26)
+#define PCCR0_EMMA_EN (1 << 27)
+#define PCCR0_DMA_EN (1 << 28)
+#define PCCR0_CSPI3_EN (1 << 29)
+#define PCCR0_CSPI2_EN (1 << 30)
+#define PCCR0_CSPI1_EN (1 << 31)
+
+#define PCCR1_MSHC_BAUDEN (1 << 2)
+#define PCCR1_NFC_BAUDEN (1 << 3)
+#define PCCR1_SSI2_BAUDEN (1 << 4)
+#define PCCR1_SSI1_BAUDEN (1 << 5)
+#define PCCR1_H264_BAUDEN (1 << 6)
+#define PCCR1_PERCLK4_EN (1 << 7)
+#define PCCR1_PERCLK3_EN (1 << 8)
+#define PCCR1_PERCLK2_EN (1 << 9)
+#define PCCR1_PERCLK1_EN (1 << 10)
+#define PCCR1_HCLK_USB (1 << 11)
+#define PCCR1_HCLK_SLCDC (1 << 12)
+#define PCCR1_HCLK_SAHARA (1 << 13)
+#define PCCR1_HCLK_RTIC (1 << 14)
+#define PCCR1_HCLK_LCDC (1 << 15)
+#define PCCR1_HCLK_H264 (1 << 16)
+#define PCCR1_HCLK_FEC (1 << 17)
+#define PCCR1_HCLK_EMMA (1 << 18)
+#define PCCR1_HCLK_EMI (1 << 19)
+#define PCCR1_HCLK_DMA (1 << 20)
+#define PCCR1_HCLK_CSI (1 << 21)
+#define PCCR1_HCLK_BROM (1 << 22)
+#define PCCR1_HCLK_ATA (1 << 23)
+#define PCCR1_WDT_EN (1 << 24)
+#define PCCR1_USB_EN (1 << 25)
+#define PCCR1_UART6_EN (1 << 26)
+#define PCCR1_UART5_EN (1 << 27)
+#define PCCR1_UART4_EN (1 << 28)
+#define PCCR1_UART3_EN (1 << 29)
+#define PCCR1_UART2_EN (1 << 30)
+#define PCCR1_UART1_EN (1 << 31)
+
+/* SDRAM Controller registers bitfields */
+#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
+#define ESDCTL_BL (1 << 7)
+#define ESDCTL_FP (1 << 8)
+#define ESDCTL_PWDT(x) (((x) & 3) << 10)
+#define ESDCTL_SREFR(x) (((x) & 7) << 13)
+#define ESDCTL_DSIZ_16_UPPER (0 << 16)
+#define ESDCTL_DSIZ_16_LOWER (1 << 16)
+#define ESDCTL_DSIZ_32 (2 << 16)
+#define ESDCTL_COL8 (0 << 20)
+#define ESDCTL_COL9 (1 << 20)
+#define ESDCTL_COL10 (2 << 20)
+#define ESDCTL_ROW11 (0 << 24)
+#define ESDCTL_ROW12 (1 << 24)
+#define ESDCTL_ROW13 (2 << 24)
+#define ESDCTL_ROW14 (3 << 24)
+#define ESDCTL_ROW15 (4 << 24)
+#define ESDCTL_SP (1 << 27)
+#define ESDCTL_SMODE_NORMAL (0 << 28)
+#define ESDCTL_SMODE_PRECHARGE (1 << 28)
+#define ESDCTL_SMODE_AUTO_REF (2 << 28)
+#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
+#define ESDCTL_SMODE_MAN_REF (4 << 28)
+#define ESDCTL_SDE (1 << 31)
+
+#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
+#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
+#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
+#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
+#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
+#define ESDCFG_TWR (1 << 15)
+#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
+#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
+#define ESDCFG_TWTR (1 << 20)
+#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
+
+#define ESDMISC_RST (1 << 1)
+#define ESDMISC_MDDREN (1 << 2)
+#define ESDMISC_MDDR_DL_RST (1 << 3)
+#define ESDMISC_MDDR_MDIS (1 << 4)
+#define ESDMISC_LHD (1 << 5)
+#define ESDMISC_MA10_SHARE (1 << 6)
+#define ESDMISC_SDRAM_RDY (1 << 31)
+
+#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
+#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
+#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
+#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
+#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
+#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
+
+#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+
+#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
+#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
+#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
+#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
+#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
+#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
+#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
+#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
+#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
+#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
+#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
+#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
+#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
+#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
+#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
+#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
+#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
+#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
+
+/* Clocksource Bitfields */
+#define TCTL_SWR (1 << 15) /* Software reset */
+#define TCTL_FRR (1 << 8) /* Freerun / restart */
+#define TCTL_CAP (3 << 6) /* Capture Edge */
+#define TCTL_OM (1 << 5) /* output mode */
+#define TCTL_IRQEN (1 << 4) /* interrupt enable */
+#define TCTL_CLKSOURCE 1 /* Clock source bit position */
+#define TCTL_TEN 1 /* Timer enable */
+#define TPRER_PRES 0xff /* Prescale */
+#define TSTAT_CAPT (1 << 1) /* Capture event */
+#define TSTAT_COMP 1 /* Compare event */
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT (1 << 8)
+#define GPIO_IN (0 << 8)
+#define GPIO_PUEN (1 << 9)
+
+#define GPIO_PF (1 << 10)
+#define GPIO_AF (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
+
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+
+/* Definitions for i.MX27 TO2 */
+#define IIM0_MAC 5
+#define IIM0_SCC_KEY 11
+#define IIM1_SUID 1
+
+#endif /* _IMX_REGS_H */
#define PLL_MFI(x) (((x) & 0xf) << 10)
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+#define WEIM_ESDCTL0 0xB8001000
+#define WEIM_ESDCFG0 0xB8001004
+#define WEIM_ESDCTL1 0xB8001008
+#define WEIM_ESDCFG1 0xB800100C
+#define WEIM_ESDMISC 0xB8001010
+
+#define ESDCTL_SDE (1 << 31)
+#define ESDCTL_CMD_RW (0 << 28)
+#define ESDCTL_CMD_PRECHARGE (1 << 28)
+#define ESDCTL_CMD_AUTOREFRESH (2 << 28)
+#define ESDCTL_CMD_LOADMODEREG (3 << 28)
+#define ESDCTL_CMD_MANUALREFRESH (4 << 28)
+#define ESDCTL_ROW_13 (2 << 24)
+#define ESDCTL_ROW(x) ((x) << 24)
+#define ESDCTL_COL_9 (1 << 20)
+#define ESDCTL_COL(x) ((x) << 20)
+#define ESDCTL_DSIZ(x) ((x) << 16)
+#define ESDCTL_SREFR(x) ((x) << 13)
+#define ESDCTL_PWDT(x) ((x) << 10)
+#define ESDCTL_FP(x) ((x) << 8)
+#define ESDCTL_BL(x) ((x) << 7)
+#define ESDCTL_PRCT(x) ((x) << 0)
+
#define WEIM_BASE 0xb8002000
#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
#define IPU_CONF_IC_EN (1<<1)
#define IPU_CONF_SCI_EN (1<<0)
+#define ARM_PPMRR 0x40000015
+
#define WDOG_BASE 0x53FDC000
/*
#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
+/* PAD control registers for SDR/DDR */
+#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
+#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
+#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
+#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
+#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
+#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
+#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
+#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
+#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
+#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
+#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
+#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
+#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
+#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
+#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
+#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
+#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
+#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
+#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
+#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
+#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
+#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
+#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
+#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
+#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
+#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
+#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
+#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
+#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
+
/*
* Memory regions and CS
*/
#define CS5_BASE 0xB6000000
#define PCMCIA_MEM_BASE 0xC0000000
+/*
+ * NAND controller
+ */
+#define NFC_BASE_ADDR 0xB8000000
+
#endif /* __ASM_ARCH_MX31_REGS_H */
}
#endif
+void mx31_uart1_hw_init(void);
+void mx31_spi2_hw_init(void);
+
#endif /* __ASM_ARCH_MX31_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MTU_H
+#define __ASM_ARCH_MTU_H
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
+#define MTU_RIS 0x04 /* Raw interrupt status */
+#define MTU_MIS 0x08 /* Masked interrupt status */
+#define MTU_ICR 0x0C /* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
+#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
+#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
+#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA 0x80
+#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK 0x0c
+#define MTU_CRn_PRESCALE_1 0x00
+#define MTU_CRn_PRESCALE_16 0x04
+#define MTU_CRn_PRESCALE_256 0x08
+#define MTU_CRn_32BITS 0x02
+#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR 0xff0
+#define MTU_ITOP 0xff4
+
+#define MTU_PERIPH_ID0 0xfe0
+#define MTU_PERIPH_ID1 0xfe4
+#define MTU_PERIPH_ID2 0xfe8
+#define MTU_PERIPH_ID3 0xfeC
+
+#define MTU_PCELL0 0xff0
+#define MTU_PCELL1 0xff4
+#define MTU_PCELL2 0xff8
+#define MTU_PCELL3 0xffC
+
+#endif /* __ASM_ARCH_MTU_H */
/* GPMC CS3/cs4/cs6 not avaliable */
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
-#define GPMC_CONFIG_CS6 0x150
+#define GPMC_CONFIG_CS5 0x150
+
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
-#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
+#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5)
#define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <asm/system.h>
+
+/*
+ * Invalidate L2 Cache using co-proc instruction
+ */
+static inline void invalidate_l2_cache(void)
+{
+ unsigned int val=0;
+
+ asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+ : : "r" (val) : "cc");
+ isb();
+}
+
+void l2_cache_enable(void);
+void l2_cache_disable(void);
+
+#endif /* _ASM_CACHE_H */
#define MACH_TYPE_APF9328 906
#define MACH_TYPE_OMAP_WIPOQ 907
#define MACH_TYPE_OMAP_TWIP 908
-#define MACH_TYPE_PALMT650 909
+#define MACH_TYPE_TREO650 909
#define MACH_TYPE_ACUMEN 910
#define MACH_TYPE_XP100 911
#define MACH_TYPE_FS2410 912
#define MACH_TYPE_VPAC270 1227
#define MACH_TYPE_RD129 1228
#define MACH_TYPE_HTCWIZARD 1229
-#define MACH_TYPE_XSCALE_TREO680 1230
+#define MACH_TYPE_TREO680 1230
#define MACH_TYPE_TECON_TMEZON 1231
#define MACH_TYPE_ZYLONITE 1233
#define MACH_TYPE_GENE1270 1234
#define MACH_TYPE_CNTY_TITAN 1418
#define MACH_TYPE_APP3XX 1419
#define MACH_TYPE_SIDEOATSGRAMA 1420
-#define MACH_TYPE_PALMTREO700P 1421
-#define MACH_TYPE_PALMTREO700W 1422
-#define MACH_TYPE_PALMTREO750 1423
-#define MACH_TYPE_PALMTREO755P 1424
+#define MACH_TYPE_TREO700P 1421
+#define MACH_TYPE_TREO700W 1422
+#define MACH_TYPE_TREO750 1423
+#define MACH_TYPE_TREO755P 1424
#define MACH_TYPE_EZREGANUT9200 1425
#define MACH_TYPE_SARGE 1426
#define MACH_TYPE_A696 1427
#define MACH_TYPE_CSB637XO 1730
#define MACH_TYPE_EVISIONG 1731
#define MACH_TYPE_STMP37XX 1732
-#define MACH_TYPE_STMP38XX 1733
+#define MACH_TYPE_STMP378X 1733
#define MACH_TYPE_TNT 1734
#define MACH_TYPE_TBXT 1735
#define MACH_TYPE_PLAYMATE 1736
#define MACH_TYPE_TAVOREVB 1827
#define MACH_TYPE_SAAR 1828
#define MACH_TYPE_DEISTER_EYECAM 1829
-#define MACH_TYPE_AT91SAM9M10EK 1830
+#define MACH_TYPE_AT91SAM9M10G45EK 1830
#define MACH_TYPE_LINKSTATION_PRODUO 1831
#define MACH_TYPE_HIT_B0 1832
#define MACH_TYPE_ADX_RMU 1833
#define MACH_TYPE_FMZWEBMODUL 2134
#define MACH_TYPE_RD78X00_MASA 2135
#define MACH_TYPE_SMALLOGGER 2136
+#define MACH_TYPE_CCW9P9215 2137
+#define MACH_TYPE_DM355_LEOPARD 2138
+#define MACH_TYPE_TS219 2139
+#define MACH_TYPE_TNY_A9263 2140
+#define MACH_TYPE_APOLLO 2141
+#define MACH_TYPE_AT91CAP9STK 2142
+#define MACH_TYPE_SPC300 2143
+#define MACH_TYPE_EKO 2144
+#define MACH_TYPE_CCW9M2443 2145
+#define MACH_TYPE_CCW9M2443JS 2146
+#define MACH_TYPE_M2M_ROUTER_DEVICE 2147
+#define MACH_TYPE_STAR9104NAS 2148
+#define MACH_TYPE_PCA100 2149
+#define MACH_TYPE_Z3_DM365_MOD_01 2150
+#define MACH_TYPE_HIPOX 2151
+#define MACH_TYPE_OMAP3_PITEDS 2152
+#define MACH_TYPE_BM150R 2153
+#define MACH_TYPE_TBONE 2154
+#define MACH_TYPE_MERLIN 2155
+#define MACH_TYPE_FALCON 2156
+#define MACH_TYPE_DAVINCI_DA850_EVM 2157
+#define MACH_TYPE_S5P6440 2158
+#define MACH_TYPE_AT91SAM9G10EK 2159
+#define MACH_TYPE_OMAP_4430SDP 2160
+#define MACH_TYPE_LPC313X 2161
+#define MACH_TYPE_MAGX_ZN5 2162
+#define MACH_TYPE_MAGX_EM30 2163
+#define MACH_TYPE_MAGX_VE66 2164
+#define MACH_TYPE_MEESC 2165
+#define MACH_TYPE_OTC570 2166
+#define MACH_TYPE_BCU2412 2167
+#define MACH_TYPE_BEACON 2168
+#define MACH_TYPE_ACTIA_TGW 2169
+#define MACH_TYPE_E4430 2170
+#define MACH_TYPE_QL300 2171
+#define MACH_TYPE_BTMAVB101 2172
+#define MACH_TYPE_BTMAWB101 2173
+#define MACH_TYPE_SQ201 2174
+#define MACH_TYPE_QUATRO45XX 2175
+#define MACH_TYPE_OPENPAD 2176
+#define MACH_TYPE_TX25 2177
+#define MACH_TYPE_OMAP3_TORPEDO 2178
+#define MACH_TYPE_HTCRAPHAEL_K 2179
+#define MACH_TYPE_LAL43 2181
+#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182
+#define MACH_TYPE_ANW6410 2183
+#define MACH_TYPE_HTCPROPHET 2185
+#define MACH_TYPE_CFA_10022 2186
+#define MACH_TYPE_IMX27_VISSTRIM_M10 2187
+#define MACH_TYPE_PX2IMX27 2188
+#define MACH_TYPE_STM3210E_EVAL 2189
+#define MACH_TYPE_DVS10 2190
+#define MACH_TYPE_PORTUXG20 2191
+#define MACH_TYPE_ARM_SPV 2192
+#define MACH_TYPE_SMDKC110 2193
+#define MACH_TYPE_CABESPRESSO 2194
+#define MACH_TYPE_HMC800 2195
+#define MACH_TYPE_SHOLES 2196
+#define MACH_TYPE_BTMXC31 2197
+#define MACH_TYPE_DT501 2198
+#define MACH_TYPE_KTX 2199
+#define MACH_TYPE_OMAP3517EVM 2200
+#define MACH_TYPE_NETSPACE_V2 2201
+#define MACH_TYPE_NETSPACE_MAX_V2 2202
+#define MACH_TYPE_D2NET_V2 2203
+#define MACH_TYPE_NET2BIG_V2 2204
+#define MACH_TYPE_NET4BIG_V2 2205
+#define MACH_TYPE_NET5BIG_V2 2206
+#define MACH_TYPE_ENDB2443 2207
+#define MACH_TYPE_INETSPACE_V2 2208
+#define MACH_TYPE_TROS 2209
+#define MACH_TYPE_PELCO_HOMER 2210
+#define MACH_TYPE_OFSP8 2211
+#define MACH_TYPE_AT91SAM9G45EKES 2212
+#define MACH_TYPE_GUF_CUPID 2213
+#define MACH_TYPE_EAB1R 2214
+#define MACH_TYPE_DESIREC 2215
+#define MACH_TYPE_CORDOBA 2216
+#define MACH_TYPE_IRVINE 2217
+#define MACH_TYPE_SFF772 2218
+#define MACH_TYPE_PELCO_MILANO 2219
+#define MACH_TYPE_PC7302 2220
+#define MACH_TYPE_BIP6000 2221
+#define MACH_TYPE_SILVERMOON 2222
+#define MACH_TYPE_VC0830 2223
+#define MACH_TYPE_DT430 2224
+#define MACH_TYPE_JI42PF 2225
+#define MACH_TYPE_GNET_KSM 2226
+#define MACH_TYPE_GNET_SGM 2227
+#define MACH_TYPE_GNET_SGR 2228
+#define MACH_TYPE_OMAP3_ICETEKEVM 2229
+#define MACH_TYPE_PNP 2230
+#define MACH_TYPE_CTERA_2BAY_K 2231
+#define MACH_TYPE_CTERA_2BAY_U 2232
+#define MACH_TYPE_SAS_C 2233
+#define MACH_TYPE_VMA2315 2234
+#define MACH_TYPE_VCS 2235
+#define MACH_TYPE_SPEAR600 2236
+#define MACH_TYPE_SPEAR300 2237
+#define MACH_TYPE_SPEAR1300 2238
+#define MACH_TYPE_LILLY1131 2239
+#define MACH_TYPE_ARVOO_AX301 2240
+#define MACH_TYPE_MAPPHONE 2241
+#define MACH_TYPE_LEGEND 2242
+#define MACH_TYPE_SALSA 2243
+#define MACH_TYPE_LOUNGE 2244
+#define MACH_TYPE_VISION 2245
+#define MACH_TYPE_VMB20 2246
+#define MACH_TYPE_HY2410 2247
+#define MACH_TYPE_HY9315 2248
+#define MACH_TYPE_BULLWINKLE 2249
+#define MACH_TYPE_ARM_ULTIMATOR2 2250
+#define MACH_TYPE_VS_V210 2252
+#define MACH_TYPE_VS_V212 2253
+#define MACH_TYPE_HMT 2254
+#define MACH_TYPE_SUEN3 2255
+#define MACH_TYPE_VESPER 2256
+#define MACH_TYPE_STR9 2257
+#define MACH_TYPE_OMAP3_WL_FF 2258
+#define MACH_TYPE_SIMCOM 2259
+#define MACH_TYPE_MCWEBIO 2260
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# define machine_is_omap_twip() (0)
#endif
-#ifdef CONFIG_MACH_PALMT650
+#ifdef CONFIG_MACH_TREO650
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_PALMT650
+# define machine_arch_type MACH_TYPE_TREO650
# endif
-# define machine_is_palmt650() (machine_arch_type == MACH_TYPE_PALMT650)
+# define machine_is_treo650() (machine_arch_type == MACH_TYPE_TREO650)
#else
-# define machine_is_palmt650() (0)
+# define machine_is_treo650() (0)
#endif
#ifdef CONFIG_MACH_ACUMEN
# define machine_is_htcwizard() (0)
#endif
-#ifdef CONFIG_MACH_XSCALE_TREO680
+#ifdef CONFIG_MACH_TREO680
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_XSCALE_TREO680
+# define machine_arch_type MACH_TYPE_TREO680
# endif
-# define machine_is_xscale_treo680() (machine_arch_type == MACH_TYPE_XSCALE_TREO680)
+# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680)
#else
-# define machine_is_xscale_treo680() (0)
+# define machine_is_treo680() (0)
#endif
#ifdef CONFIG_MACH_TECON_TMEZON
# define machine_is_sideoatsgrama() (0)
#endif
-#ifdef CONFIG_MACH_PALMTREO700P
+#ifdef CONFIG_MACH_TREO700P
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_PALMTREO700P
+# define machine_arch_type MACH_TYPE_TREO700P
# endif
-# define machine_is_palmtreo700p() (machine_arch_type == MACH_TYPE_PALMTREO700P)
+# define machine_is_treo700p() (machine_arch_type == MACH_TYPE_TREO700P)
#else
-# define machine_is_palmtreo700p() (0)
+# define machine_is_treo700p() (0)
#endif
-#ifdef CONFIG_MACH_PALMTREO700W
+#ifdef CONFIG_MACH_TREO700W
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_PALMTREO700W
+# define machine_arch_type MACH_TYPE_TREO700W
# endif
-# define machine_is_palmtreo700w() (machine_arch_type == MACH_TYPE_PALMTREO700W)
+# define machine_is_treo700w() (machine_arch_type == MACH_TYPE_TREO700W)
#else
-# define machine_is_palmtreo700w() (0)
+# define machine_is_treo700w() (0)
#endif
-#ifdef CONFIG_MACH_PALMTREO750
+#ifdef CONFIG_MACH_TREO750
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_PALMTREO750
+# define machine_arch_type MACH_TYPE_TREO750
# endif
-# define machine_is_palmtreo750() (machine_arch_type == MACH_TYPE_PALMTREO750)
+# define machine_is_treo750() (machine_arch_type == MACH_TYPE_TREO750)
#else
-# define machine_is_palmtreo750() (0)
+# define machine_is_treo750() (0)
#endif
-#ifdef CONFIG_MACH_PALMTREO755P
+#ifdef CONFIG_MACH_TREO755P
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_PALMTREO755P
+# define machine_arch_type MACH_TYPE_TREO755P
# endif
-# define machine_is_palmtreo755p() (machine_arch_type == MACH_TYPE_PALMTREO755P)
+# define machine_is_treo755p() (machine_arch_type == MACH_TYPE_TREO755P)
#else
-# define machine_is_palmtreo755p() (0)
+# define machine_is_treo755p() (0)
#endif
#ifdef CONFIG_MACH_EZREGANUT9200
# define machine_is_stmp37xx() (0)
#endif
-#ifdef CONFIG_MACH_STMP38XX
+#ifdef CONFIG_MACH_STMP378X
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_STMP38XX
+# define machine_arch_type MACH_TYPE_STMP378X
# endif
-# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP38XX)
+# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X)
#else
# define machine_is_stmp378x() (0)
#endif
# define machine_is_deister_eyecam() (0)
#endif
-#ifdef CONFIG_MACH_AT91SAM9M10EK
+#ifdef CONFIG_MACH_AT91SAM9M10G45EK
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_AT91SAM9M10EK
+# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK
# endif
-# define machine_is_at91sam9m10ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10EK)
+# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK)
#else
-# define machine_is_at91sam9m10ek() (0)
+# define machine_is_at91sam9m10g45ek() (0)
#endif
#ifdef CONFIG_MACH_LINKSTATION_PRODUO
# define machine_is_smallogger() (0)
#endif
+#ifdef CONFIG_MACH_CCW9P9215
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCW9P9215
+# endif
+# define machine_is_ccw9p9215() (machine_arch_type == MACH_TYPE_CCW9P9215)
+#else
+# define machine_is_ccw9p9215() (0)
+#endif
+
+#ifdef CONFIG_MACH_DM355_LEOPARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DM355_LEOPARD
+# endif
+# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD)
+#else
+# define machine_is_dm355_leopard() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS219
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS219
+# endif
+# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219)
+#else
+# define machine_is_ts219() (0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_A9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TNY_A9263
+# endif
+# define machine_is_tny_a9263() (machine_arch_type == MACH_TYPE_TNY_A9263)
+#else
+# define machine_is_tny_a9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_APOLLO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_APOLLO
+# endif
+# define machine_is_apollo() (machine_arch_type == MACH_TYPE_APOLLO)
+#else
+# define machine_is_apollo() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91CAP9STK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91CAP9STK
+# endif
+# define machine_is_at91cap9stk() (machine_arch_type == MACH_TYPE_AT91CAP9STK)
+#else
+# define machine_is_at91cap9stk() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPC300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPC300
+# endif
+# define machine_is_spc300() (machine_arch_type == MACH_TYPE_SPC300)
+#else
+# define machine_is_spc300() (0)
+#endif
+
+#ifdef CONFIG_MACH_EKO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EKO
+# endif
+# define machine_is_eko() (machine_arch_type == MACH_TYPE_EKO)
+#else
+# define machine_is_eko() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCW9M2443
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCW9M2443
+# endif
+# define machine_is_ccw9m2443() (machine_arch_type == MACH_TYPE_CCW9M2443)
+#else
+# define machine_is_ccw9m2443() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCW9M2443JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCW9M2443JS
+# endif
+# define machine_is_ccw9m2443js() (machine_arch_type == MACH_TYPE_CCW9M2443JS)
+#else
+# define machine_is_ccw9m2443js() (0)
+#endif
+
+#ifdef CONFIG_MACH_M2M_ROUTER_DEVICE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_M2M_ROUTER_DEVICE
+# endif
+# define machine_is_m2m_router_device() (machine_arch_type == MACH_TYPE_M2M_ROUTER_DEVICE)
+#else
+# define machine_is_m2m_router_device() (0)
+#endif
+
+#ifdef CONFIG_MACH_STAR9104NAS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STAR9104NAS
+# endif
+# define machine_is_str9104nas() (machine_arch_type == MACH_TYPE_STAR9104NAS)
+#else
+# define machine_is_str9104nas() (0)
+#endif
+
+#ifdef CONFIG_MACH_PCA100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PCA100
+# endif
+# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100)
+#else
+# define machine_is_pca100() (0)
+#endif
+
+#ifdef CONFIG_MACH_Z3_DM365_MOD_01
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_Z3_DM365_MOD_01
+# endif
+# define machine_is_z3_dm365_mod_01() (machine_arch_type == MACH_TYPE_Z3_DM365_MOD_01)
+#else
+# define machine_is_z3_dm365_mod_01() (0)
+#endif
+
+#ifdef CONFIG_MACH_HIPOX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HIPOX
+# endif
+# define machine_is_hipox() (machine_arch_type == MACH_TYPE_HIPOX)
+#else
+# define machine_is_hipox() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_PITEDS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_PITEDS
+# endif
+# define machine_is_omap3_piteds() (machine_arch_type == MACH_TYPE_OMAP3_PITEDS)
+#else
+# define machine_is_omap3_piteds() (0)
+#endif
+
+#ifdef CONFIG_MACH_BM150R
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BM150R
+# endif
+# define machine_is_bm150r() (machine_arch_type == MACH_TYPE_BM150R)
+#else
+# define machine_is_bm150r() (0)
+#endif
+
+#ifdef CONFIG_MACH_TBONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TBONE
+# endif
+# define machine_is_tbone() (machine_arch_type == MACH_TYPE_TBONE)
+#else
+# define machine_is_tbone() (0)
+#endif
+
+#ifdef CONFIG_MACH_MERLIN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MERLIN
+# endif
+# define machine_is_merlin() (machine_arch_type == MACH_TYPE_MERLIN)
+#else
+# define machine_is_merlin() (0)
+#endif
+
+#ifdef CONFIG_MACH_FALCON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FALCON
+# endif
+# define machine_is_falcon() (machine_arch_type == MACH_TYPE_FALCON)
+#else
+# define machine_is_falcon() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DA850_EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM
+# endif
+# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
+#else
+# define machine_is_davinci_da850_evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_S5P6440
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_S5P6440
+# endif
+# define machine_is_s5p6440() (machine_arch_type == MACH_TYPE_S5P6440)
+#else
+# define machine_is_s5p6440() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G10EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G10EK
+# endif
+# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK)
+#else
+# define machine_is_at91sam9g10ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_4430SDP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_4430SDP
+# endif
+# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP)
+#else
+# define machine_is_omap_4430sdp() (0)
+#endif
+
+#ifdef CONFIG_MACH_LPC313X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LPC313X
+# endif
+# define machine_is_lpc313x() (machine_arch_type == MACH_TYPE_LPC313X)
+#else
+# define machine_is_lpc313x() (0)
+#endif
+
+#ifdef CONFIG_MACH_MAGX_ZN5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MAGX_ZN5
+# endif
+# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5)
+#else
+# define machine_is_magx_zn5() (0)
+#endif
+
+#ifdef CONFIG_MACH_MAGX_EM30
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MAGX_EM30
+# endif
+# define machine_is_magx_em30() (machine_arch_type == MACH_TYPE_MAGX_EM30)
+#else
+# define machine_is_magx_em30() (0)
+#endif
+
+#ifdef CONFIG_MACH_MAGX_VE66
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MAGX_VE66
+# endif
+# define machine_is_magx_ve66() (machine_arch_type == MACH_TYPE_MAGX_VE66)
+#else
+# define machine_is_magx_ve66() (0)
+#endif
+
+#ifdef CONFIG_MACH_MEESC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MEESC
+# endif
+# define machine_is_meesc() (machine_arch_type == MACH_TYPE_MEESC)
+#else
+# define machine_is_meesc() (0)
+#endif
+
+#ifdef CONFIG_MACH_OTC570
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OTC570
+# endif
+# define machine_is_otc570() (machine_arch_type == MACH_TYPE_OTC570)
+#else
+# define machine_is_otc570() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCU2412
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCU2412
+# endif
+# define machine_is_bcu2412() (machine_arch_type == MACH_TYPE_BCU2412)
+#else
+# define machine_is_bcu2412() (0)
+#endif
+
+#ifdef CONFIG_MACH_BEACON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BEACON
+# endif
+# define machine_is_beacon() (machine_arch_type == MACH_TYPE_BEACON)
+#else
+# define machine_is_beacon() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACTIA_TGW
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACTIA_TGW
+# endif
+# define machine_is_actia_tgw() (machine_arch_type == MACH_TYPE_ACTIA_TGW)
+#else
+# define machine_is_actia_tgw() (0)
+#endif
+
+#ifdef CONFIG_MACH_E4430
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_E4430
+# endif
+# define machine_is_e4430() (machine_arch_type == MACH_TYPE_E4430)
+#else
+# define machine_is_e4430() (0)
+#endif
+
+#ifdef CONFIG_MACH_QL300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QL300
+# endif
+# define machine_is_ql300() (machine_arch_type == MACH_TYPE_QL300)
+#else
+# define machine_is_ql300() (0)
+#endif
+
+#ifdef CONFIG_MACH_BTMAVB101
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BTMAVB101
+# endif
+# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101)
+#else
+# define machine_is_btmavb101() (0)
+#endif
+
+#ifdef CONFIG_MACH_BTMAWB101
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BTMAWB101
+# endif
+# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101)
+#else
+# define machine_is_btmawb101() (0)
+#endif
+
+#ifdef CONFIG_MACH_SQ201
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SQ201
+# endif
+# define machine_is_sq201() (machine_arch_type == MACH_TYPE_SQ201)
+#else
+# define machine_is_sq201() (0)
+#endif
+
+#ifdef CONFIG_MACH_QUATRO45XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QUATRO45XX
+# endif
+# define machine_is_quatro45xx() (machine_arch_type == MACH_TYPE_QUATRO45XX)
+#else
+# define machine_is_quatro45xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_OPENPAD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OPENPAD
+# endif
+# define machine_is_openpad() (machine_arch_type == MACH_TYPE_OPENPAD)
+#else
+# define machine_is_openpad() (0)
+#endif
+
+#ifdef CONFIG_MACH_TX25
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TX25
+# endif
+# define machine_is_tx25() (machine_arch_type == MACH_TYPE_TX25)
+#else
+# define machine_is_tx25() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_TORPEDO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO
+# endif
+# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO)
+#else
+# define machine_is_omap3_torpedo() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCRAPHAEL_K
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCRAPHAEL_K
+# endif
+# define machine_is_htcraphael_k() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_K)
+#else
+# define machine_is_htcraphael_k() (0)
+#endif
+
+#ifdef CONFIG_MACH_LAL43
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LAL43
+# endif
+# define machine_is_lal43() (machine_arch_type == MACH_TYPE_LAL43)
+#else
+# define machine_is_lal43() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA500
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA500
+# endif
+# define machine_is_htcraphael_cdma500() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA500)
+#else
+# define machine_is_htcraphael_cdma500() (0)
+#endif
+
+#ifdef CONFIG_MACH_ANW6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ANW6410
+# endif
+# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410)
+#else
+# define machine_is_anw6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCPROPHET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCPROPHET
+# endif
+# define machine_is_htcprophet() (machine_arch_type == MACH_TYPE_HTCPROPHET)
+#else
+# define machine_is_htcprophet() (0)
+#endif
+
+#ifdef CONFIG_MACH_CFA_10022
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CFA_10022
+# endif
+# define machine_is_cfa_10022() (machine_arch_type == MACH_TYPE_CFA_10022)
+#else
+# define machine_is_cfa_10022() (0)
+#endif
+
+#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10
+# endif
+# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10)
+#else
+# define machine_is_imx27_visstrim_m10() (0)
+#endif
+
+#ifdef CONFIG_MACH_PX2IMX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PX2IMX27
+# endif
+# define machine_is_px2imx27() (machine_arch_type == MACH_TYPE_PX2IMX27)
+#else
+# define machine_is_px2imx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_STM3210E_EVAL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STM3210E_EVAL
+# endif
+# define machine_is_stm3210e_eval() (machine_arch_type == MACH_TYPE_STM3210E_EVAL)
+#else
+# define machine_is_stm3210e_eval() (0)
+#endif
+
+#ifdef CONFIG_MACH_DVS10
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DVS10
+# endif
+# define machine_is_dvs10() (machine_arch_type == MACH_TYPE_DVS10)
+#else
+# define machine_is_dvs10() (0)
+#endif
+
+#ifdef CONFIG_MACH_PORTUXG20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PORTUXG20
+# endif
+# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20)
+#else
+# define machine_is_portuxg20() (0)
+#endif
+
+#ifdef CONFIG_MACH_ARM_SPV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ARM_SPV
+# endif
+# define machine_is_arm_spv() (machine_arch_type == MACH_TYPE_ARM_SPV)
+#else
+# define machine_is_arm_spv() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKC110
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMDKC110
+# endif
+# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110)
+#else
+# define machine_is_smdkc110() (0)
+#endif
+
+#ifdef CONFIG_MACH_CABESPRESSO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CABESPRESSO
+# endif
+# define machine_is_cabespresso() (machine_arch_type == MACH_TYPE_CABESPRESSO)
+#else
+# define machine_is_cabespresso() (0)
+#endif
+
+#ifdef CONFIG_MACH_HMC800
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HMC800
+# endif
+# define machine_is_hmc800() (machine_arch_type == MACH_TYPE_HMC800)
+#else
+# define machine_is_hmc800() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHOLES
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHOLES
+# endif
+# define machine_is_sholes() (machine_arch_type == MACH_TYPE_SHOLES)
+#else
+# define machine_is_sholes() (0)
+#endif
+
+#ifdef CONFIG_MACH_BTMXC31
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BTMXC31
+# endif
+# define machine_is_btmxc31() (machine_arch_type == MACH_TYPE_BTMXC31)
+#else
+# define machine_is_btmxc31() (0)
+#endif
+
+#ifdef CONFIG_MACH_DT501
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DT501
+# endif
+# define machine_is_dt501() (machine_arch_type == MACH_TYPE_DT501)
+#else
+# define machine_is_dt501() (0)
+#endif
+
+#ifdef CONFIG_MACH_KTX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KTX
+# endif
+# define machine_is_ktx() (machine_arch_type == MACH_TYPE_KTX)
+#else
+# define machine_is_ktx() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3517EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3517EVM
+# endif
+# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM)
+#else
+# define machine_is_omap3517evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NETSPACE_V2
+# endif
+# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2)
+#else
+# define machine_is_netspace_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_MAX_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2
+# endif
+# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2)
+#else
+# define machine_is_netspace_max_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_D2NET_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_D2NET_V2
+# endif
+# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2)
+#else
+# define machine_is_d2net_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_NET2BIG_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NET2BIG_V2
+# endif
+# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2)
+#else
+# define machine_is_net2big_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_NET4BIG_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NET4BIG_V2
+# endif
+# define machine_is_net4big_v2() (machine_arch_type == MACH_TYPE_NET4BIG_V2)
+#else
+# define machine_is_net4big_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_NET5BIG_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NET5BIG_V2
+# endif
+# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2)
+#else
+# define machine_is_net5big_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_ENDB2443
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ENDB2443
+# endif
+# define machine_is_endb2443() (machine_arch_type == MACH_TYPE_ENDB2443)
+#else
+# define machine_is_endb2443() (0)
+#endif
+
+#ifdef CONFIG_MACH_INETSPACE_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_INETSPACE_V2
+# endif
+# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2)
+#else
+# define machine_is_inetspace_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_TROS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TROS
+# endif
+# define machine_is_tros() (machine_arch_type == MACH_TYPE_TROS)
+#else
+# define machine_is_tros() (0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_HOMER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PELCO_HOMER
+# endif
+# define machine_is_pelco_homer() (machine_arch_type == MACH_TYPE_PELCO_HOMER)
+#else
+# define machine_is_pelco_homer() (0)
+#endif
+
+#ifdef CONFIG_MACH_OFSP8
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OFSP8
+# endif
+# define machine_is_ofsp8() (machine_arch_type == MACH_TYPE_OFSP8)
+#else
+# define machine_is_ofsp8() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G45EKES
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES
+# endif
+# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES)
+#else
+# define machine_is_at91sam9g45ekes() (0)
+#endif
+
+#ifdef CONFIG_MACH_GUF_CUPID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GUF_CUPID
+# endif
+# define machine_is_guf_cupid() (machine_arch_type == MACH_TYPE_GUF_CUPID)
+#else
+# define machine_is_guf_cupid() (0)
+#endif
+
+#ifdef CONFIG_MACH_EAB1R
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EAB1R
+# endif
+# define machine_is_eab1r() (machine_arch_type == MACH_TYPE_EAB1R)
+#else
+# define machine_is_eab1r() (0)
+#endif
+
+#ifdef CONFIG_MACH_DESIREC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DESIREC
+# endif
+# define machine_is_desirec() (machine_arch_type == MACH_TYPE_DESIREC)
+#else
+# define machine_is_desirec() (0)
+#endif
+
+#ifdef CONFIG_MACH_CORDOBA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CORDOBA
+# endif
+# define machine_is_cordoba() (machine_arch_type == MACH_TYPE_CORDOBA)
+#else
+# define machine_is_cordoba() (0)
+#endif
+
+#ifdef CONFIG_MACH_IRVINE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IRVINE
+# endif
+# define machine_is_irvine() (machine_arch_type == MACH_TYPE_IRVINE)
+#else
+# define machine_is_irvine() (0)
+#endif
+
+#ifdef CONFIG_MACH_SFF772
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SFF772
+# endif
+# define machine_is_sff772() (machine_arch_type == MACH_TYPE_SFF772)
+#else
+# define machine_is_sff772() (0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_MILANO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PELCO_MILANO
+# endif
+# define machine_is_pelco_milano() (machine_arch_type == MACH_TYPE_PELCO_MILANO)
+#else
+# define machine_is_pelco_milano() (0)
+#endif
+
+#ifdef CONFIG_MACH_PC7302
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PC7302
+# endif
+# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302)
+#else
+# define machine_is_pc7302() (0)
+#endif
+
+#ifdef CONFIG_MACH_BIP6000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BIP6000
+# endif
+# define machine_is_bip6000() (machine_arch_type == MACH_TYPE_BIP6000)
+#else
+# define machine_is_bip6000() (0)
+#endif
+
+#ifdef CONFIG_MACH_SILVERMOON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SILVERMOON
+# endif
+# define machine_is_silvermoon() (machine_arch_type == MACH_TYPE_SILVERMOON)
+#else
+# define machine_is_silvermoon() (0)
+#endif
+
+#ifdef CONFIG_MACH_VC0830
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VC0830
+# endif
+# define machine_is_vc0830() (machine_arch_type == MACH_TYPE_VC0830)
+#else
+# define machine_is_vc0830() (0)
+#endif
+
+#ifdef CONFIG_MACH_DT430
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DT430
+# endif
+# define machine_is_dt430() (machine_arch_type == MACH_TYPE_DT430)
+#else
+# define machine_is_dt430() (0)
+#endif
+
+#ifdef CONFIG_MACH_JI42PF
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_JI42PF
+# endif
+# define machine_is_ji42pf() (machine_arch_type == MACH_TYPE_JI42PF)
+#else
+# define machine_is_ji42pf() (0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_KSM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GNET_KSM
+# endif
+# define machine_is_gnet_ksm() (machine_arch_type == MACH_TYPE_GNET_KSM)
+#else
+# define machine_is_gnet_ksm() (0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SGM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GNET_SGM
+# endif
+# define machine_is_gnet_sgm() (machine_arch_type == MACH_TYPE_GNET_SGM)
+#else
+# define machine_is_gnet_sgm() (0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SGR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GNET_SGR
+# endif
+# define machine_is_gnet_sgr() (machine_arch_type == MACH_TYPE_GNET_SGR)
+#else
+# define machine_is_gnet_sgr() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_ICETEKEVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_ICETEKEVM
+# endif
+# define machine_is_omap3_icetekevm() (machine_arch_type == MACH_TYPE_OMAP3_ICETEKEVM)
+#else
+# define machine_is_omap3_icetekevm() (0)
+#endif
+
+#ifdef CONFIG_MACH_PNP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PNP
+# endif
+# define machine_is_pnp() (machine_arch_type == MACH_TYPE_PNP)
+#else
+# define machine_is_pnp() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_2BAY_K
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_2BAY_K
+# endif
+# define machine_is_ctera_2bay_k() (machine_arch_type == MACH_TYPE_CTERA_2BAY_K)
+#else
+# define machine_is_ctera_2bay_k() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_2BAY_U
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_2BAY_U
+# endif
+# define machine_is_ctera_2bay_u() (machine_arch_type == MACH_TYPE_CTERA_2BAY_U)
+#else
+# define machine_is_ctera_2bay_u() (0)
+#endif
+
+#ifdef CONFIG_MACH_SAS_C
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SAS_C
+# endif
+# define machine_is_sas_c() (machine_arch_type == MACH_TYPE_SAS_C)
+#else
+# define machine_is_sas_c() (0)
+#endif
+
+#ifdef CONFIG_MACH_VMA2315
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VMA2315
+# endif
+# define machine_is_vma2315() (machine_arch_type == MACH_TYPE_VMA2315)
+#else
+# define machine_is_vma2315() (0)
+#endif
+
+#ifdef CONFIG_MACH_VCS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VCS
+# endif
+# define machine_is_vcs() (machine_arch_type == MACH_TYPE_VCS)
+#else
+# define machine_is_vcs() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR600
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPEAR600
+# endif
+# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600)
+#else
+# define machine_is_spear600() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPEAR300
+# endif
+# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300)
+#else
+# define machine_is_spear300() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPEAR1300
+# endif
+# define machine_is_spear1300() (machine_arch_type == MACH_TYPE_SPEAR1300)
+#else
+# define machine_is_spear1300() (0)
+#endif
+
+#ifdef CONFIG_MACH_LILLY1131
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LILLY1131
+# endif
+# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131)
+#else
+# define machine_is_lilly1131() (0)
+#endif
+
+#ifdef CONFIG_MACH_ARVOO_AX301
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ARVOO_AX301
+# endif
+# define machine_is_arvoo_ax301() (machine_arch_type == MACH_TYPE_ARVOO_AX301)
+#else
+# define machine_is_arvoo_ax301() (0)
+#endif
+
+#ifdef CONFIG_MACH_MAPPHONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MAPPHONE
+# endif
+# define machine_is_mapphone() (machine_arch_type == MACH_TYPE_MAPPHONE)
+#else
+# define machine_is_mapphone() (0)
+#endif
+
+#ifdef CONFIG_MACH_LEGEND
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LEGEND
+# endif
+# define machine_is_legend() (machine_arch_type == MACH_TYPE_LEGEND)
+#else
+# define machine_is_legend() (0)
+#endif
+
+#ifdef CONFIG_MACH_SALSA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SALSA
+# endif
+# define machine_is_salsa() (machine_arch_type == MACH_TYPE_SALSA)
+#else
+# define machine_is_salsa() (0)
+#endif
+
+#ifdef CONFIG_MACH_LOUNGE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LOUNGE
+# endif
+# define machine_is_lounge() (machine_arch_type == MACH_TYPE_LOUNGE)
+#else
+# define machine_is_lounge() (0)
+#endif
+
+#ifdef CONFIG_MACH_VISION
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VISION
+# endif
+# define machine_is_vision() (machine_arch_type == MACH_TYPE_VISION)
+#else
+# define machine_is_vision() (0)
+#endif
+
+#ifdef CONFIG_MACH_VMB20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VMB20
+# endif
+# define machine_is_vmb20() (machine_arch_type == MACH_TYPE_VMB20)
+#else
+# define machine_is_vmb20() (0)
+#endif
+
+#ifdef CONFIG_MACH_HY2410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HY2410
+# endif
+# define machine_is_hy2410() (machine_arch_type == MACH_TYPE_HY2410)
+#else
+# define machine_is_hy2410() (0)
+#endif
+
+#ifdef CONFIG_MACH_HY9315
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HY9315
+# endif
+# define machine_is_hy9315() (machine_arch_type == MACH_TYPE_HY9315)
+#else
+# define machine_is_hy9315() (0)
+#endif
+
+#ifdef CONFIG_MACH_BULLWINKLE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BULLWINKLE
+# endif
+# define machine_is_bullwinkle() (machine_arch_type == MACH_TYPE_BULLWINKLE)
+#else
+# define machine_is_bullwinkle() (0)
+#endif
+
+#ifdef CONFIG_MACH_ARM_ULTIMATOR2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ARM_ULTIMATOR2
+# endif
+# define machine_is_arm_ultimator2() (machine_arch_type == MACH_TYPE_ARM_ULTIMATOR2)
+#else
+# define machine_is_arm_ultimator2() (0)
+#endif
+
+#ifdef CONFIG_MACH_VS_V210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VS_V210
+# endif
+# define machine_is_vs_v210() (machine_arch_type == MACH_TYPE_VS_V210)
+#else
+# define machine_is_vs_v210() (0)
+#endif
+
+#ifdef CONFIG_MACH_VS_V212
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VS_V212
+# endif
+# define machine_is_vs_v212() (machine_arch_type == MACH_TYPE_VS_V212)
+#else
+# define machine_is_vs_v212() (0)
+#endif
+
+#ifdef CONFIG_MACH_HMT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HMT
+# endif
+# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT)
+#else
+# define machine_is_hmt() (0)
+#endif
+
+#ifdef CONFIG_MACH_SUEN3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SUEN3
+# endif
+# define machine_is_suen3() (machine_arch_type == MACH_TYPE_SUEN3)
+#else
+# define machine_is_suen3() (0)
+#endif
+
+#ifdef CONFIG_MACH_VESPER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VESPER
+# endif
+# define machine_is_vesper() (machine_arch_type == MACH_TYPE_VESPER)
+#else
+# define machine_is_vesper() (0)
+#endif
+
+#ifdef CONFIG_MACH_STR9
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STR9
+# endif
+# define machine_is_str9() (machine_arch_type == MACH_TYPE_STR9)
+#else
+# define machine_is_str9() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_WL_FF
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_WL_FF
+# endif
+# define machine_is_omap3_wl_ff() (machine_arch_type == MACH_TYPE_OMAP3_WL_FF)
+#else
+# define machine_is_omap3_wl_ff() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIMCOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIMCOM
+# endif
+# define machine_is_simcom() (machine_arch_type == MACH_TYPE_SIMCOM)
+#else
+# define machine_is_simcom() (0)
+#endif
+
+#ifdef CONFIG_MACH_MCWEBIO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MCWEBIO
+# endif
+# define machine_is_mcwebio() (machine_arch_type == MACH_TYPE_MCWEBIO)
+#else
+# define machine_is_mcwebio() (0)
+#endif
+
/*
* These have not yet been registered
*/
--- /dev/null
+/*
+ * include/asm-arm/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_MACRO_H__
+#define __ASM_ARM_MACRO_H__
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to any address.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any ARM architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro write32, addr, data
+ ldr r4, =\addr
+ ldr r5, =\data
+ str r5, [r4]
+.endm
+
+.macro write16, addr, data
+ ldr r4, =\addr
+ ldrh r5, =\data
+ strh r5, [r4]
+.endm
+
+.macro write8, addr, data
+ ldr r4, =\addr
+ ldrb r5, =\data
+ strb r5, [r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any ARM architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro wait_timer, time
+ ldr r4, =\time
+1:
+ nop
+ subs r4, r4, #1
+ bcs 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H__ */
#endif
#endif
+#ifndef CONFIG_FSL_DMA
+#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
+ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
+ (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+#define CONFIG_FSL_DMA
#endif
+#endif
+
+#endif /* _ASM_CONFIG_H_ */
#include <asm/types.h>
+#ifdef CONFIG_MPC83xx
typedef struct fsl_dma {
uint mr; /* DMA mode register */
+#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
+#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
+#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
+#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
+#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
+#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
+#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
+#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */
+#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */
+#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */
+#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */
uint sr; /* DMA status register */
+#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */
+#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
+#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
+#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
+ uint cdar; /* DMA current descriptor address register */
+ char res0[4];
+ uint sar; /* DMA source address register */
+ char res1[4];
+ uint dar; /* DMA destination address register */
+ char res2[4];
+ uint bcr; /* DMA byte count register */
+ uint ndar; /* DMA next descriptor address register */
+ uint gsr; /* DMA general status register (DMA3 ONLY!) */
+ char res3[84];
+} fsl_dma_t;
+#else
+typedef struct fsl_dma {
+ uint mr; /* DMA mode register */
+#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
+#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
+#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
+#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */
+#define FSL_DMA_MR_CDSM 0x00000010
+#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */
+#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */
+#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */
+#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */
+#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */
+#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */
+#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
+#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
+#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */
+#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */
+#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */
+ uint sr; /* DMA status register */
+#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */
+#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
+#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
+#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */
+#define FSL_DMA_SR_PE 0x00000010 /* Programming error */
+#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */
+#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
char res0[4];
uint clndar; /* DMA current link descriptor address register */
uint satr; /* DMA source attributes register */
+#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */
+#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */
+#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */
+#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */
+#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */
+#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */
+#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */
+#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */
+#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */
uint sar; /* DMA source address register */
uint datr; /* DMA destination attributes register */
+#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */
+#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */
+#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */
+#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */
+#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */
+#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */
+#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */
+#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */
+#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */
+#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */
uint dar; /* DMA destination address register */
uint bcr; /* DMA byte count register */
char res1[4];
uint dsr; /* DMA destination stride register */
char res4[56];
} fsl_dma_t;
+#endif /* !CONFIG_MPC83xx */
+
+#ifdef CONFIG_FSL_DMA
+void dma_init(void);
+int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
+#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
+void dma_meminit(uint val, uint size);
+#endif
+#endif
#endif /* _ASM_DMA_H_ */
#include <asm/fsl_i2c.h>
#include <asm/mpc8xxx_spi.h>
#include <asm/fsl_lbc.h>
+#include <asm/fsl_dma.h>
/*
* Local Access Window
u32 imisr; /* 0x80 Inbound message interrupt status register */
u32 imimr; /* 0x84 Inbound message interrupt mask register */
u32 res4[0x1E]; /* 0x88-0x99 reserved */
- u32 dmamr0; /* 0x100 DMA 0 mode register */
- u32 dmasr0; /* 0x104 DMA 0 status register */
- u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
- u32 res5; /* 0x10C reserved */
- u32 dmasar0; /* 0x110 DMA 0 source address register */
- u32 res6; /* 0x114 reserved */
- u32 dmadar0; /* 0x118 DMA 0 destination address register */
- u32 res7; /* 0x11C reserved */
- u32 dmabcr0; /* 0x120 DMA 0 byte count register */
- u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
- u32 res8[0x16]; /* 0x128-0x179 reserved */
- u32 dmamr1; /* 0x180 DMA 1 mode register */
- u32 dmasr1; /* 0x184 DMA 1 status register */
- u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
- u32 res9; /* 0x18C reserved */
- u32 dmasar1; /* 0x190 DMA 1 source address register */
- u32 res10; /* 0x194 reserved */
- u32 dmadar1; /* 0x198 DMA 1 destination address register */
- u32 res11; /* 0x19C reserved */
- u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
- u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
- u32 res12[0x16]; /* 0x1A8-0x199 reserved */
- u32 dmamr2; /* 0x200 DMA 2 mode register */
- u32 dmasr2; /* 0x204 DMA 2 status register */
- u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
- u32 res13; /* 0x20C reserved */
- u32 dmasar2; /* 0x210 DMA 2 source address register */
- u32 res14; /* 0x214 reserved */
- u32 dmadar2; /* 0x218 DMA 2 destination address register */
- u32 res15; /* 0x21C reserved */
- u32 dmabcr2; /* 0x220 DMA 2 byte count register */
- u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
- u32 res16[0x16]; /* 0x228-0x279 reserved */
- u32 dmamr3; /* 0x280 DMA 3 mode register */
- u32 dmasr3; /* 0x284 DMA 3 status register */
- u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
- u32 res17; /* 0x28C reserved */
- u32 dmasar3; /* 0x290 DMA 3 source address register */
- u32 res18; /* 0x294 reserved */
- u32 dmadar3; /* 0x298 DMA 3 destination address register */
- u32 res19; /* 0x29C reserved */
- u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
- u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
- u32 dmagsr; /* 0x2A8 DMA general status register */
- u32 res20[0x15]; /* 0x2AC-0x2FF reserved */
+ struct fsl_dma dma[4];
} dma83xx_t;
/*
} immap_t;
#endif
+#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
+#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
char res11[476];
} ccsr_pcix_t;
+typedef struct ccsr_gpio {
+ uint gpdir;
+ uint gpodr;
+ uint gpdat;
+ uint gpier;
+ uint gpimr;
+ uint gpicr;
+} ccsr_gpio_t;
+
#define PCIX_COMMAND 0x62
#define POWAR_EN 0x80000000
#define POWAR_IO_READ 0x00080000
#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
struct cpu_type *identify_cpu(u32 ver);
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v) \
{ .name = #n, .soc_ver = SVR_##v, }
#else
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400)
-void s3c2410_irq(void);
-#define ARM920_IRQ_CALLBACK s3c2410_irq
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
#else
#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_DDR3 1
#undef CONFIG_FSL_DDR_INTERACTIVE
-// #define CONFIG_DDR_ECC /* ECC will be enabled based on perf_mode environment variable */
+/* ECC will be enabled based on perf_mode environment variable */
+/* #define CONFIG_DDR_ECC */
+
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
-//#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
/* Default settings for "stable" mode */
/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#undef CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#undef CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
--- /dev/null
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5170 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC86xx 1 /* MPC86xx */
+#define CONFIG_MPC8641 1 /* MPC8641 specific */
+#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
+#define CONFIG_SYS_BOARD_NAME "XPedite5170"
+#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
+#define CONFIG_ALTIVEC 1
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
+#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
+#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
+
+/*
+ * virtual address to be used for temporary mappings. There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA 0xe0000000
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
+
+/*
+ * L2CR setup
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT 0
+#define L2_ENABLE (L2CR_L2E)
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
+ * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
+ * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
+ * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
+ * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
+ * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
+ * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE 0xef800000
+#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
+#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
+#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY 25
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_JFFS2_NAND
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000
+#define CONFIG_SYS_FLASH_BASE2 0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
+ {0xf7f00000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
+ BR_PS_16 |\
+ BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
+ OR_GPCM_CSNT |\
+ OR_GPCM_XACS |\
+ OR_GPCM_ACS_DIV2 |\
+ OR_GPCM_SCY_8 |\
+ OR_GPCM_TRLX |\
+ OR_GPCM_EHTR |\
+ OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
+ BR_PS_16 |\
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
+ BR_PS_8 |\
+ BR_V)
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
+ OR_GPCM_BCTLD |\
+ OR_GPCM_CSNT |\
+ OR_GPCM_ACS_DIV4 |\
+ OR_GPCM_SCY_4 |\
+ OR_GPCM_TRLX |\
+ OR_GPCM_EHTR)
+
+/* Optional NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
+ BR_PS_8 |\
+ BR_V)
+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
+#define CONFIG_SYS_INIT_RAM_END 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
+#define CONFIG_DTT_DS1621
+#define CONFIG_DTT_SENSORS { 0 }
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* GPIO/EEPROM/SRAM */
+#define CONFIG_DS4510
+#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
+#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - PEX8518 */
+#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
+
+/* PCIE2 - VPX P1 */
+#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR 2
+#define TSEC2_PHYIDX 0
+#define CONFIG_HAS_ETH1
+
+/*
+ * BAT mappings
+ */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
+ BATU_BL_1M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT0 2G Cacheable, non-guarded
+ * 0x0000_0000 2G DDR
+ */
+#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
+
+/*
+ * BAT1 1G Cache-inhibited, guarded
+ * 0x8000_0000 1G PCI-Express 1 Memory
+ */
+#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
+ BATU_BL_1G |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
+
+/*
+ * BAT2 512M Cache-inhibited, guarded
+ * 0xc000_0000 512M PCI-Express 2 Memory
+ */
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
+ BATU_BL_512M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+
+/*
+ * BAT3 1M Cache-inhibited, guarded
+ * 0xe000_0000 1M CCSR
+ */
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
+ BATU_BL_1M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+
+/*
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 16M PCI-Express 1 I/O
+ * 0xe300_0000 16M PCI-Express 2 I/0
+ */
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
+ BATU_BL_32M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5 128K Cacheable, non-guarded
+ * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
+ BATL_PP_RW |\
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
+ BATU_BL_128K |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6 256M Cache-inhibited, guarded
+ * 0xf000_0000 256M FLASH
+ */
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
+ BATU_BL_256M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
+ BATL_PP_RW |\
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\
+ BATU_BL_1M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
+ BATL_PP_RW |\
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7 64M Cache-inhibited, guarded
+ * 0xe800_0000 64K NAND FLASH
+ * 0xe804_0000 128K DUART Registers
+ */
+#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
+ BATU_BL_512K |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
+ BATL_PP_RW |\
+ BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DS4510
+#define CONFIG_CMD_DS4510_INFO
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
+#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * Flash memory map:
+ * fffc0000 - ffffffff Pri FDT (256KB)
+ * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
+ * fff00000 - fff7ffff Pri U-Boot (512 KB)
+ * fef00000 - ffefffff Pri OS image (16MB)
+ * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
+ *
+ * f7fc0000 - f7ffffff Sec FDT (256KB)
+ * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
+ * f6f00000 - f7efffff Sec OS image (16MB)
+ * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
+#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
+#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
+#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_UBOOT2 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS1 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS2 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT1 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT2 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/uImage-XPedite5170\0" \
+ "fdtfile=/home/user/xpedite5170.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
+ "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
+ "prog_os1="CONFIG_PROG_OS1"\0" \
+ "prog_os2="CONFIG_PROG_OS2"\0" \
+ "prog_fdt1="CONFIG_PROG_FDT1"\0" \
+ "prog_fdt2="CONFIG_PROG_FDT2"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash1=run set_bootargs; " \
+ "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+ "bootcmd_flash2=run set_bootargs; " \
+ "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+ "bootcmd=run bootcmd_flash1\0"
+#endif /* __CONFIG_H */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
/*
* Hardware drivers
#define DATAFLASH_TCHS (0x1 << 24)
/* NOR flash, if populated */
-#if 1
-#define CONFIG_SYS_NO_FLASH 1
-#else
+#ifdef CONFIG_SYS_USE_NORFLASH
#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define PHYS_FLASH_1 0x10000000
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define PHYS_FLASH_1 0x10000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_MONITOR_SEC 1:0-3
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE 0x2000
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=" \
+ "protect off ${monitor_base} +${filesize};" \
+ "erase ${monitor_base} +${filesize};" \
+ "cp.b ${load_addr} ${monitor_base} ${filesize};" \
+ "protect on ${monitor_base} +${filesize}\0"
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define MASTER_PLL_MUL 171
+#define MASTER_PLL_DIV 14
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL \
+ (AT91_PMC_MOSCEN | \
+ (255 << 8)) /* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_OUT | \
+ AT91_PMC_PLLCOUNT | /* PLL Counter */ \
+ (2 << 28) | /* PLL Clock Frequency Range */ \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
+ (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
+ AT91_MATRIX_EBI0_CS1A_SDRAMC)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1 0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_3 | \
+ AT91_SDRAMC_DBW_32 | \
+ (1 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (2 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (1 << 28)) /* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_16 | \
+ AT91_SMC_TDFMODE | \
+ AT91_SMC_TDF_(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_PROCRST | \
+ AT91_RSTC_RSTTYP_WAKEUP | \
+ AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
+ AT91_WDT_WDV | \
+ AT91_WDT_WDDIS | \
+ AT91_WDT_WDD)
+#endif
+
+#else
+#define CONFIG_SYS_NO_FLASH 1
#endif
/* NAND flash */
"mtdparts=at91_nand:-(root) "\
"rw rootfstype=jffs2"
-#else /* CONFIG_SYS_USE_NANDFLASH */
+#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_DM9000_BASE 0x04014000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
+#define CONFIG_NET_MULTI
/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
#if (TEXT_BASE == 0xFF000000)
""
/*
+ * SPI configuration
+ */
+#define CONFIG_HARD_SPI 1
+#define CONFIG_MPC52XX_SPI 1
+
+/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1
/*
* GPIO configuration
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
+ * Bit 0 (mask 0x80000000) : 0x1
+ * SPI on Tmr2/3/4/5 pins
+ * Bit 2:3 (mask 0x30000000) : 0x2
+ * ATA cs0/1 on csb_4/5
+ * Bit 6:7 (mask 0x03000000) : 0x2
+ * Ethernet 100Mbit with MD
+ * Bits 12:15 (mask 0x000f0000): 0x5
+ * USB - Two UARTs
+ * Bits 18:19 (mask 0x00003000) : 0x2
+ * PSC3 - USB2 on PSC3
+ * Bits 20:23 (mask 0x00000f00) : 0x1
+ * PSC2 - CAN1&2 on PSC2 pins
+ * Bits 25:27 (mask 0x00000070) : 0x1
+ * PSC1 - AC97 functionality
+ * Bits 29:31 (mask 0x00000007) : 0x2
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
* Hardware drivers
*/
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_HARD_SPI 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
/* allow to overwrite serial and ethaddr */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CONFIG_SYS_FLASH_BASE 0x24000000
+#define CONFIG_SYS_FLASH_BASE 0x24000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_ENV_SIZE 32768
+#define CONFIG_ENV_SIZE 32768
-#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE)
/*-----------------------------------------------------------------------
* PCI definitions
*/
#define CONFIG_SYS_FLASH_BASE 0x24000000
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_SECT 64
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * Configuation settings for the esd MEESC board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Common stuff */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq */
+#define CONFIG_MEESC 1 /* Board is esd MEESC */
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */
+#define CONFIG_ENV_OVERWRITE 1 /* necessary on prototypes */
+#define CONFIG_DISPLAY_BOARDINFO 1
+#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+
+/*
+ * Hardware drivers
+ */
+
+/* Console output */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_USB
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+
+/* LED */
+#define CONFIG_AT91_LED 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH 1
+#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NOR flash is not populated, disable it */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#undef CONFIG_RESET_PHY_R
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END 0x21e00000
+
+#define CONFIG_SYS_USE_DATAFLASH 1
+#undef CONFIG_SYS_USE_NANDFLASH
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* CAN */
+#define CONFIG_AT91_CAN 1
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH 1
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+ 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+ CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b C0042000 22000000 210000; bootm"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 22000000 A0000 200000; bootm"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN 0x2D000
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
* Hardware drivers
*/
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_HARD_SPI 1
--- /dev/null
+/*
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the Freescale i.MX31 PDK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+/* Bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART 1
+#define CONFIG_SYS_MX31_UART1 1
+
+#define CONFIG_HARD_SPI 1
+#define CONFIG_MXC_SPI 1
+#define CONFIG_DEFAULT_SPI_BUS 1
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+
+#define CONFIG_RTC_MC13783 1
+
+/* MC13783 connected to CSPI2 and SS2 */
+#define CONFIG_MC13783_SPI_BUS 1
+#define CONFIG_MC13783_SPI_CS 2
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+
+/*
+ * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
+ * that CFG_NO_FLASH is undefined).
+ */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x81000000 uImage-mx31; bootm\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xB6000000
+#define CONFIG_DRIVER_SMC911X_32_BIT 1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "uboot> "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* No NOR flash present */
+#define CONFIG_SYS_NO_FLASH 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+#define CONFIG_ENV_SIZE (128 * 1024)
+
+/* NAND configuration for the NAND_SPL */
+
+/* Start copying real U-boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+
+
+/* Configuration of lowlevel_init.S (clocks and SDRAM) */
+#define CCM_CCMR_SETUP 0x074B0BF5
+#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+ PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
+ PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
+ PLL_MFN(12))
+
+#define ESDMISC_MDDR_SETUP 0x00000004
+#define ESDMISC_MDDR_RESET_DL 0x0000000c
+#define ESDCFG0_MDDR_SETUP 0x006ac73a
+
+#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+ ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW ESDCTL_SETTINGS
+
+#endif /* __CONFIG_H */
/*
* (C) Copyright 2005
* STMicroelectronics.
- * Configuration settings for the STn8815 nomadik board.
+ * Configuration settings for the "Nomadik Hardware Kit" NHK-8815,
+ * the evaluation board for the Nomadik 8815 System on Chip.
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_ARM926EJS
#define CONFIG_NOMADIK
-#define CONFIG_NOMADIK_8815
-#define CONFIG_NOMADIK_NDK15
-#define CONFIG_NOMADIK_NHK15
+#define CONFIG_NOMADIK_8815 /* cpu variant */
+#define CONFIG_NOMADIK_NHK8815 /* board variant */
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "Nomadik> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
+#define CONFIG_SYS_64BIT_VSPRINTF /* mtd desires this */
#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
/* timing informazion */
-#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */
+#define CONFIG_SYS_HZ 1000 /* Mandatory... */
#define CONFIG_SYS_TIMERBASE 0x101E2000
/* serial port (PL011) configuration */
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_BOOTFILE "uImage"
-/* flash memory and filesystem information */
-#define CONFIG_DOS_PARTITION
+/* Storage information: onenand and nand */
+#define CONFIG_CMD_ONENAND
#define CONFIG_MTD_ONENAND_VERIFY_WRITE
#define CONFIG_SYS_ONENAND_BASE 0x30000000
+
+#define CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */
+/*
+ * Filesystem information
+ *
+ * Since U-Boot has been loaded to RAM by vendor code, we could use
+ * either or both OneNand and Nand. However, we need to know where the
+ * filesystem lives. Comments below report vendor-selected partitions
+ */
#ifdef CONFIG_BOOT_ONENAND
-
-# define CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */
/* Partition Size Start
* XloaderTOC + X-Loader 256KB 0x00000000
* Memory init function 256KB 0x00040000
- * U-Boot 2MB 0x00080000
+ * U-Boot + env 2MB 0x00080000
* Sysimage (kernel + ramdisk) 4MB 0x00280000
* JFFS2 Root filesystem 22MB 0x00680000
* JFFS2 User Data 227.5MB 0x01C80000
*/
-# define CONFIG_JFFS2_PART_SIZE 0x400000
-# define CONFIG_JFFS2_PART_OFFSET 0x280000
-
+# define CONFIG_JFFS2_DEV "onenand0"
+# define CONFIG_JFFS2_PART_SIZE 0x01600000
+# define CONFIG_JFFS2_PART_OFFSET 0x00680000
# define CONFIG_ENV_IS_IN_ONENAND
-# define CONFIG_ENV_SIZE (256 * 1024)
-# define CONFIG_ENV_ADDR 0x30300000
-
-#else /* ! CONFIG_BOOT_ONENAND */
-
-# define CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */
+# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
+# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE)
+#else /* BOOT_NAND */
+ /* Partition Size Start
+ * XloaderTOC + X-Loader 256KB 0x00000000
+ * Memory init function 256KB 0x00040000
+ * U-Boot + env 2MB 0x00080000
+ * Kernel Image 3MB 0x00280000
+ * JFFS2 Root filesystem 22MB 0x00580000
+ * JFFS2 User Data 100.5MB 0x01b80000
+ */
# define CONFIG_JFFS2_DEV "nand0"
# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/
-# define CONFIG_JFFS2_PART_SIZE 0x00300000
-# define CONFIG_JFFS2_PART_OFFSET 0x00280000
-
+# define CONFIG_JFFS2_PART_SIZE 0x01600000
+# define CONFIG_JFFS2_PART_OFFSET 0x00580000
# define CONFIG_ENV_IS_IN_NAND
# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
-# define CONFIG_ENV_OFFSET (0x8000000 - CONFIG_ENV_SIZE)
+# define CONFIG_ENV_OFFSET (0x00280000 - CONFIG_ENV_SIZE)
#endif /* CONFIG_BOOT_ONENAND */
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * Configuation settings for the RONETIX PM9261 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME "AT91SAM9261"
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MASTER_PLL_DIV 15
+#define MASTER_PLL_MUL 162
+#define MAIN_PLL_DIV 2
+#define AT91_MAIN_CLOCK 18432000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
+#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/* clocks */
+/* CKGR_MOR - enable main osc. */
+#define CONFIG_SYS_MOR_VAL \
+ (AT91_PMC_MOSCEN | \
+ (255 << 8)) /* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_OUT | \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
+
+/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+ (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_3 | \
+ AT91_SDRAMC_DBW_32 | \
+ (1 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (3 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (1 << 28)) /* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_16 | \
+ AT91_SMC_TDFMODE | \
+ AT91_SMC_TDF_(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_PROCRST | \
+ AT91_RSTC_RSTTYP_WAKEUP | \
+ AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
+ AT91_WDT_WDV | \
+ AT91_WDT_WDDIS | \
+ AT91_WDT_WDD)
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CONFIG_SYS_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_BGR555 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED AT91_PIN_PC12
+#define CONFIG_GREEN_LED AT91_PIN_PC13
+#define CONFIG_YELLOW_LED AT91_PIN_PC15
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NAND flash */
+#define CONFIG_NAND_ATMEL
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD22 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
+/* our CLE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
+
+
+/* NOR flash */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define PHYS_FLASH_1 0x10000000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* Ethernet */
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x30000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+#define CONFIG_NET_MULTI
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END 0x23e00000
+
+#undef CONFIG_SYS_USE_DATAFLASH_CS0
+#undef CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SYS_USE_FLASH 1
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH 1
+#define CONFIG_SYS_MONITOR_BASE \
+ (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=at91_nand:-(root) " \
+ "rw rootfstype=jffs2"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock5 " \
+ "mtdparts=at91_nand:128k(bootstrap)ro," \
+ "256k(uboot)ro,128k(env1)ro," \
+ "128k(env2)ro,2M(linux),-(root) " \
+ "rw rootfstype=jffs2"
+
+#elif defined (CONFIG_SYS_USE_FLASH)
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_OVERWRITE 1
+
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK 0
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
+
+#define CONFIG_BOOTCOMMAND "run flashboot"
+
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:" \
+ "256k(u-boot)ro," \
+ "64k(u-boot-env)ro," \
+ "1408k(kernel)," \
+ "-(rootfs);" \
+ "nand:-(nand)"
+
+#define CONFIG_CON_ROT "fbcon=rotate:3 "
+#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,0\0" \
+ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ CONFIG_CON_ROT \
+ "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
+ ":$(hostname):eth0:off\0" \
+ "ramboot=tftpboot 0x22000000 vmImage;" \
+ "run ramargs;run addip;bootm 22000000\0" \
+ "nfsboot=tftpboot 0x22000000 vmImage;" \
+ "run nfsargs;run addip;bootm 22000000\0" \
+ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
+ ""
+#else
+#error "Undefined memory device"
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "pm9261> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define MASTER_PLL_DIV 15
-#define MASTER_PLL_MUL 162
+#define MASTER_PLL_DIV 6
+#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
#define AT91_MAIN_CLOCK 18432000
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* clocks */
-#define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
-#define CONFIG_SYS_PLLAR_VAL \
- (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+#define CONFIG_SYS_MOR_VAL \
+ (AT91_PMC_MOSCEN | \
+ (255 << 8)) /* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_OUT | \
+ AT91_PMC_PLLCOUNT | /* PLL Counter */ \
+ (2 << 28) | /* PLL Clock Frequency Range */ \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL 0x00000100
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL 0x00000102
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
#else
/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL 0x00000200
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91RM9200_PMC_MDIV_3 | \
+ AT91_PMC_PDIV_1)
/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL 0x00000202
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91RM9200_PMC_MDIV_3 | \
+ AT91_PMC_PDIV_1)
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A
-/* EBI1_CSA, 3.3v, no pull-ups */
-#define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
+ (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
+ AT91_MATRIX_EBI0_CS1A_SDRAMC)
/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1 0
/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
-#define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/
+#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_2 | \
+ AT91_SDRAMC_DBW_32 | \
+ (2 << 8) | /* tWR - Write Recovery Delay */ \
+ (7 << 12) | /* tRC - Row Cycle Delay */ \
+ (2 << 16) | /* tRP - Row Precharge Delay */ \
+ (2 << 20) | /* tRCD - Row to Column Delay */ \
+ (5 << 24) | /* tRAS - Active to Precharge Delay */ \
+ (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
+
/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL 0
-#define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */
+#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */
+#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */
+#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
-#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
-#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
-#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
-
-/* setup SMC1, CS0 (PSRAM) - 16-bit */
-#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */
-#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */
-#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */
-#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */
-
-#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */
-
-/* Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
-
-/* */
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_16 | \
+ AT91_SMC_TDFMODE | \
+ AT91_SMC_TDF_(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_PROCRST | \
+ AT91_RSTC_RSTTYP_WAKEUP | \
+ AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
+ AT91_WDT_WDV | \
+ AT91_WDT_WDDIS | \
+ AT91_WDT_WDD)
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
* Hardware drivers
*/
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
/* FPGA */
#define CONFIG_SYS_GRER1_VAL 0x00000000
#define CONFIG_SYS_GRER2_VAL 0x00000000
#define CONFIG_SYS_GRER3_VAL 0x00000000
-#define CONFIG_SYS_GFER0_VAL 0x00000000
+
#define CONFIG_SYS_GFER1_VAL 0x00000000
-#define CONFIG_SYS_GFER2_VAL 0x00000000
#define CONFIG_SYS_GFER3_VAL 0x00000020
+#if CONFIG_POLARIS
+#define CONFIG_SYS_GFER0_VAL 0x00000001
+#define CONFIG_SYS_GFER2_VAL 0x00200000
+#else
+#define CONFIG_SYS_GFER0_VAL 0x00000000
+#define CONFIG_SYS_GFER2_VAL 0x00000000
+#endif
#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
#define CONFIG_SYS_MSC0_VAL 0x4df84df0
#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
+#if CONFIG_POLARIS
+#define CONFIG_SYS_MSC2_VAL 0xa2697ff8
+#else
#define CONFIG_SYS_MSC2_VAL 0xa26936d4
+#endif
#define CONFIG_SYS_MDCNFG_VAL 0x880009C9
#define CONFIG_SYS_MDREFR_VAL 0x20ca201e
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_NET_MULTI 1
#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x08000000
+
+#if CONFIG_POLARIS
+#define CONFIG_DM9000_BASE 0x0C800000
+#else
+#define CONFIG_DM9000_BASE 0x08000000
+#endif
+
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
/* write flash less slowly */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+/* Unlock to be used with Intel chips */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
/* Flash environment locations */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
-#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
+#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
-
-#define CONFIG_SYS_MEMTEST_START 0x100000
-#define CONFIG_SYS_MEMTEST_END 0x10000000
-#define CONFIG_SYS_HZ (1000000 / 256)
-#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
+#define CONFIG_SYS_MEMTEST_START 0x100000
+#define CONFIG_SYS_MEMTEST_END 0x10000000
+#define CONFIG_SYS_HZ (1000000 / 256)
+#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
#define CONFIG_SYS_TIMER_INTERVAL 10000
-#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4) /* Divide by 16 */
-#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */
+#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4)
+#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */
/*
* control registers
*/
-#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
+#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
/*
* System controller bit assignment
#define VERSATILE_TIMER3_EnSel 19
#define VERSATILE_TIMER4_EnSel 21
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
+#define CONFIG_MISC_INIT_R 1
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
*/
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
+#define CONFIG_PL01x_PORTS \
+ {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 38400
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_SERIAL0 0x101F1000
#define CONFIG_SYS_SERIAL1 0x101F2000
-
/*
* Command line configuration.
*/
+#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SAVEENV
-
/*
* BOOTP options
*/
-#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
+#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
-/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */
+#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\
+ "netdev=25,0,0xf1010000,0xf1010010,eth0"
/*
* Static configuration when assigning fixed address
*/
-/*#define CONFIG_NETMASK 255.255.255.0 /--* talk on MY local net */
-/*#define CONFIG_IPADDR xx.xx.xx.xx /--* static IP I currently own */
-/*#define CONFIG_SERVERIP xx.xx.xx.xx /--* current IP of my dev pc */
-#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
-
+#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Versatile # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "Versatile # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
*
* The stack sizes are set up in start.S using the settings below
*/
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define CONFIG_SYS_FLASH_BASE 0x34000000
+#define CONFIG_SYS_FLASH_BASE 0x34000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-#define VERSATILE_SYS_BASE 0x10000000
-#define VERSATILE_SYS_FLASH_OFFSET 0x4C
-#define VERSATILE_FLASHCTRL (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
-#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
+#define VERSATILE_SYS_BASE 0x10000000
+#define VERSATILE_SYS_FLASH_OFFSET 0x4C
+#define VERSATILE_FLASHCTRL \
+ (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
+/* Enable writing to flash */
+#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */
/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (20 * CONFIG_SYS_HZ) /* Write Timeout */
#define CONFIG_SYS_MAX_FLASH_SECT (256)
-#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE)
+#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE)
-#define CONFIG_ENV_IS_IN_FLASH 1 /* env in flash instead of CONFIG_ENV_IS_NOWHERE */
-#define CONFIG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET 0x01f00000 /* environment starts here */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_IS_IN_FLASH 1 /* env in flash */
+#define CONFIG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
+#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment */
+#define CONFIG_ENV_OFFSET 0x01f00000 /* environment starts */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ *
+ * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_NFC_H
+#define __FSL_NFC_H
+
+/*
+ * Register map and bit definitions for the Freescale NAND Flash
+ * Controller present in i.MX31 and other devices.
+ */
+
+struct fsl_nfc_regs {
+ u32 main_area0[128]; /* @0x000 */
+ u32 main_area1[128];
+ u32 main_area2[128];
+ u32 main_area3[128];
+ u32 spare_area0[4];
+ u32 spare_area1[4];
+ u32 spare_area2[4];
+ u32 spare_area3[4];
+ u32 reserved1[64 - 16 + 64 * 5];
+ u16 bufsiz; /* @ 0xe00 */
+ u16 reserved2;
+ u16 buffer_address;
+ u16 flash_add;
+ u16 flash_cmd;
+ u16 configuration;
+ u16 ecc_status_result;
+ u16 ecc_rslt_main_area;
+ u16 ecc_rslt_spare_area;
+ u16 nf_wr_prot;
+ u16 unlock_start_blk_add;
+ u16 unlock_end_blk_add;
+ u16 nand_flash_wr_pr_st;
+ u16 nand_flash_config1;
+ u16 nand_flash_config2;
+};
+
+/*
+ * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
+ * operation
+ */
+#define NFC_CMD 0x1
+
+/*
+ * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
+ * operation
+ */
+#define NFC_ADDR 0x2
+
+/*
+ * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
+ * operation
+ */
+#define NFC_INPUT 0x4
+
+/*
+ * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
+ * Output operation
+ */
+#define NFC_OUTPUT 0x8
+
+/*
+ * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
+ * operation
+ */
+#define NFC_ID 0x10
+
+/*
+ * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
+ * Status operation
+ */
+#define NFC_STATUS 0x20
+
+/*
+ * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
+ * operation
+ */
+#define NFC_INT 0x8000
+
+#define NFC_SP_EN (1 << 2)
+#define NFC_ECC_EN (1 << 3)
+#define NFC_INT_MSK (1 << 4)
+#define NFC_BIG (1 << 5)
+#define NFC_RST (1 << 6)
+#define NFC_CE (1 << 7)
+#define NFC_ONE_CYCLE (1 << 8)
+
+#endif /* __FSL_NFC_H */
#ifndef MTD_CONCAT_H
#define MTD_CONCAT_H
-
struct mtd_info *mtd_concat_create(
struct mtd_info *subdev[], /* subdevices to concatenate */
int num_devs, /* number of subdevices */
void mtd_concat_destroy(struct mtd_info *mtd);
#endif
-
struct mtd_info {
u_char type;
u_int32_t flags;
- uint64_t size; // Total size of the MTD
+ uint64_t size; /* Total size of the MTD */
- /* "Major" erase size for the device. Naïve users may take this
+ /* "Major" erase size for the device. Naïve users may take this
* to be the only erase size available, or may use the more detailed
* information below if they desire
*/
#define I2C_IF 0x02
#define I2C_RXAK 0x01
+/* SPI control register 1 bits */
+#define SPI_CR_LSBFE 0x01
+#define SPI_CR_SSOE 0x02
+#define SPI_CR_CPHA 0x04
+#define SPI_CR_CPOL 0x08
+#define SPI_CR_MSTR 0x10
+#define SPI_CR_SWOM 0x20
+#define SPI_CR_SPE 0x40
+#define SPI_CR_SPIE 0x80
+
+/* SPI status register bits */
+#define SPI_SR_MODF 0x10
+#define SPI_SR_WCOL 0x40
+#define SPI_SR_SPIF 0x80
+
+/* SPI port data register bits */
+#define SPI_PDR_SS 0x08
+
/* Programmable Serial Controller (PSC) status register bits */
#define PSC_SR_CDE 0x0080
#define PSC_SR_RXRDY 0x0100
#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
#define ECC_ERROR_MAN_SBEC_SHIFT 0
-/* DMAMR - DMA Mode Register
- */
-#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */
-#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */
-#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */
-#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */
-
-/* DMASR - DMA Status Register
- */
-#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */
-#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */
-
/* CONFIG_ADDRESS - PCI Config Address Register
*/
#define PCI_CONFIG_ADDRESS_EN 0x80000000
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
- defined(CONFIG_MPC5xxx)
+ defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \
+ defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
#include <serial.h>
#include <nand.h>
#include <onenand_uboot.h>
+#include <mmc.h>
#ifdef CONFIG_DRIVER_SMC91111
#include "../drivers/net/smc91111.h"
#ifdef BOARD_LATE_INIT
board_late_init ();
#endif
+
+#ifdef CONFIG_GENERIC_MMC
+ puts ("MMC: ");
+ mmc_initialize (gd->bd);
+#endif
+
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
--- /dev/null
+CONFIG_NAND_SPL = y
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+
+SOBJS = start.o lowlevel_init.o
+COBJS = nand_boot_fsl_nfc.o
+
+SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
+SRCS += $(SRCTREE)/cpu/arm1136/start.S
+SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $@
+
+#########################################################################
+
+$(obj)%.o: $(SRCTREE)/cpu/arm1136/%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(SRCTREE)/nand_spl/%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+PAD_TO := 2048
--- /dev/null
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ start.o (.text)
+ lowlevel_init.o (.text)
+ nand_boot_fsl_nfc.o (.text)
+ *(.text)
+ . = 2K;
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (C) Copyright 2008
+ * Maxim Artamonov, <scn1874 at yandex.ru>
+ *
+ * (C) Copyright 2006-2008
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm-arm/arch/mx31-regs.h>
+#include <asm/io.h>
+#include <fsl_nfc.h>
+
+static struct fsl_nfc_regs *nfc;
+
+static void nfc_wait_ready(void)
+{
+ uint32_t tmp;
+
+ while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
+ ;
+
+ /* Reset interrupt flag */
+ tmp = readw(&nfc->nand_flash_config2);
+ tmp &= ~NFC_INT;
+ writew(tmp, &nfc->nand_flash_config2);
+}
+
+static void nfc_nand_init(void)
+{
+ /* unlocking RAM Buff */
+ writew(0x2, &nfc->configuration);
+
+ /* hardware ECC checking and correct */
+ writew(NFC_ECC_EN, &nfc->nand_flash_config1);
+}
+
+static void nfc_nand_command(unsigned short command)
+{
+ writew(command, &nfc->flash_cmd);
+ writew(NFC_CMD, &nfc->nand_flash_config2);
+ nfc_wait_ready();
+}
+
+static void nfc_nand_page_address(unsigned int page_address)
+{
+ unsigned int page_count;
+
+ writew(0x00, &nfc->flash_cmd);
+ writew(NFC_ADDR, &nfc->nand_flash_config2);
+ nfc_wait_ready();
+
+ /* code only for 2kb flash */
+ if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) {
+ writew(0x00, &nfc->flash_add);
+ writew(NFC_ADDR, &nfc->nand_flash_config2);
+ nfc_wait_ready();
+ }
+
+ page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
+
+ if (page_address <= page_count) {
+ page_count--; /* transform 0x01000000 to 0x00ffffff */
+ do {
+ writew(page_address & 0xff, &nfc->flash_add);
+ writew(NFC_ADDR, &nfc->nand_flash_config2);
+ nfc_wait_ready();
+ page_address = page_address >> 8;
+ page_count = page_count >> 8;
+ } while (page_count);
+ }
+}
+
+static void nfc_nand_data_output(void)
+{
+ int i;
+
+ /*
+ * The NAND controller requires four output commands for
+ * large page devices.
+ */
+ for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
+ writew(NFC_ECC_EN, &nfc->nand_flash_config1);
+ writew(i, &nfc->buffer_address); /* read in i:th buffer */
+ writew(NFC_OUTPUT, &nfc->nand_flash_config2);
+ nfc_wait_ready();
+ }
+}
+
+static int nfc_nand_check_ecc(void)
+{
+ return readw(&nfc->ecc_status_result);
+}
+
+static int nfc_read_page(unsigned int page_address, unsigned char *buf)
+{
+ int i;
+ u32 *src;
+ u32 *dst;
+
+ writew(0, &nfc->buffer_address); /* read in first 0 buffer */
+ nfc_nand_command(NAND_CMD_READ0);
+ nfc_nand_page_address(page_address);
+
+ if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
+ nfc_nand_command(NAND_CMD_READSTART);
+
+ nfc_nand_data_output(); /* fill the main buffer 0 */
+
+ if (nfc_nand_check_ecc())
+ return -1;
+
+ src = &nfc->main_area0[0];
+ dst = (u32 *)buf;
+
+ /* main copy loop from NAND-buffer to SDRAM memory */
+ for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) {
+ writel(readl(src), dst);
+ src++;
+ dst++;
+ }
+
+ return 0;
+}
+
+static int is_badblock(int pagenumber)
+{
+ int page = pagenumber;
+ u32 badblock;
+ u32 *src;
+
+ /* Check the first two pages for bad block markers */
+ for (page = pagenumber; page < pagenumber + 2; page++) {
+ writew(0, &nfc->buffer_address); /* read in first 0 buffer */
+ nfc_nand_command(NAND_CMD_READ0);
+ nfc_nand_page_address(page);
+
+ if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
+ nfc_nand_command(NAND_CMD_READSTART);
+
+ nfc_nand_data_output(); /* fill the main buffer 0 */
+
+ src = &nfc->spare_area0[0];
+
+ /*
+ * IMPORTANT NOTE: The nand flash controller uses a non-
+ * standard layout for large page devices. This can
+ * affect the position of the bad block marker.
+ */
+ /* Get the bad block marker */
+ badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
+ badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
+ badblock &= 0xff;
+
+ /* bad block marker verify */
+ if (badblock != 0xff)
+ return 1; /* potential bad block */
+ }
+
+ return 0;
+}
+
+static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
+{
+ int i;
+ unsigned int page;
+ unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
+ CONFIG_SYS_NAND_PAGE_SIZE;
+
+ nfc = (void *)NFC_BASE_ADDR;
+
+ nfc_nand_init();
+
+ /* Convert to page number */
+ page = from / CONFIG_SYS_NAND_PAGE_SIZE;
+ i = 0;
+
+ while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) {
+ if (nfc_read_page(page, buf) < 0)
+ return -1;
+
+ page++;
+ i++;
+ buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
+
+ /*
+ * Check if we have crossed a block boundary, and if so
+ * check for bad block.
+ */
+ if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
+ /*
+ * Yes, new block. See if this block is good. If not,
+ * loop until we find i good block.
+ */
+ while (is_badblock(page)) {
+ page = page + CONFIG_SYS_NAND_PAGE_COUNT;
+ /* Check i we've reached the end of flash. */
+ if (page >= maxpages)
+ return -1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ nfc = (void *)NFC_BASE_ADDR;
+
+ /*
+ * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
+ * be aligned to full pages
+ */
+ if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+ /* Copy from NAND successful, start U-boot */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot();
+ } else {
+ /* Unrecoverable error when copying from NAND */
+ hang();
+ }
+}
+
+/*
+ * Called in case of an exception.
+ */
+void hang(void)
+{
+ /* Loop forever */
+ while (1) ;
+}
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
-AFLAGS += -DCONFIG_ONENAND_IPL
-CFLAGS += -DCONFIG_ONENAND_IPL
+AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
+CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
SOBJS := low_levelinit.o
projects / platform / kernel / u-boot.git / commitdiff