help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
- the image contents have not been corrupted. SHA256 is recommended
- for use in secure applications since (as at 2016) there is no known
- feasible attack that could produce a 'collision' with differing
- input data. Use this for the highest security. Note that only the
- SHA256 variant is supported: SHA512 and others are not currently
- supported in U-Boot.
+ the image contents have not been corrupted.
+
+config FIT_ENABLE_SHA384_SUPPORT
+ bool "Support SHA384 checksum of FIT image contents"
+ default n
+ select SHA384
+ help
+ Enable this to support SHA384 checksum of FIT image contents. A
+ SHA384 checksum is a 384-bit (48-byte) hash value used to check that
+ the image contents have not been corrupted. Use this for the highest
+ security.
+
+config FIT_ENABLE_SHA512_SUPPORT
+ bool "Support SHA512 checksum of FIT image contents"
+ default n
+ select SHA512
+ help
+ Enable this to support SHA512 checksum of FIT image contents. A
+ SHA512 checksum is a 512-bit (64-byte) hash value used to check that
+ the image contents have not been corrupted.
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
T: git https://gitlab.denx.de/u-boot/u-boot.git
F: common/log*
F: cmd/log.c
+F: doc/develop/logging.rst
F: test/log/
F: test/py/tests/test_log.py
dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
omap3-igep0020.dtb
+dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
+ omap4-panda.dtb \
+ omap4-panda-es.dtb
+
+dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
+ omap4-sdp.dtb \
+ omap4-sdp-es23plus.dtb
+
+dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
+ omap5-uevm.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+ elpida_ECB240ABACN: lpddr2 {
+ compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+ density = <2048>;
+ io-width = <32>;
+
+ tRPab-min-tck = <3>;
+ tRCD-min-tck = <3>;
+ tWR-min-tck = <3>;
+ tRASmin-min-tck = <3>;
+ tRRD-min-tck = <2>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tCKE-min-tck = <3>;
+ tCKESR-min-tck = <3>;
+ tFAW-min-tck = <8>;
+
+ timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <7500>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+
+ timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <200000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <10000>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+ };
+};
--- /dev/null
+&l4_abe { /* 0x40100000 */
+ compatible = "ti,omap4-l4-abe", "simple-bus";
+ reg = <0x40100000 0x400>,
+ <0x40100400 0x400>;
+ reg-names = "la", "ap";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
+ <0x49000000 0x49000000 0x100000>;
+ segment@0 { /* 0x40100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges =
+ /* CPU to L4 ABE mapping */
+ <0x00000000 0x00000000 0x000400>, /* ap 0 */
+ <0x00000400 0x00000400 0x000400>, /* ap 1 */
+ <0x00022000 0x00022000 0x001000>, /* ap 2 */
+ <0x00023000 0x00023000 0x001000>, /* ap 3 */
+ <0x00024000 0x00024000 0x001000>, /* ap 4 */
+ <0x00025000 0x00025000 0x001000>, /* ap 5 */
+ <0x00026000 0x00026000 0x001000>, /* ap 6 */
+ <0x00027000 0x00027000 0x001000>, /* ap 7 */
+ <0x00028000 0x00028000 0x001000>, /* ap 8 */
+ <0x00029000 0x00029000 0x001000>, /* ap 9 */
+ <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
+ <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
+ <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
+ <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
+ <0x00030000 0x00030000 0x001000>, /* ap 14 */
+ <0x00031000 0x00031000 0x001000>, /* ap 15 */
+ <0x00032000 0x00032000 0x001000>, /* ap 16 */
+ <0x00033000 0x00033000 0x001000>, /* ap 17 */
+ <0x00038000 0x00038000 0x001000>, /* ap 18 */
+ <0x00039000 0x00039000 0x001000>, /* ap 19 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
+ <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
+ <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
+ <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
+ <0x00080000 0x00080000 0x010000>, /* ap 26 */
+ <0x00080000 0x00080000 0x001000>, /* ap 27 */
+ <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
+ <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
+ <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
+ <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
+ <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
+ <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
+
+ /* L3 to L4 ABE mapping */
+ <0x49000000 0x49000000 0x000400>, /* ap 0 */
+ <0x49000400 0x49000400 0x000400>, /* ap 1 */
+ <0x49022000 0x49022000 0x001000>, /* ap 2 */
+ <0x49023000 0x49023000 0x001000>, /* ap 3 */
+ <0x49024000 0x49024000 0x001000>, /* ap 4 */
+ <0x49025000 0x49025000 0x001000>, /* ap 5 */
+ <0x49026000 0x49026000 0x001000>, /* ap 6 */
+ <0x49027000 0x49027000 0x001000>, /* ap 7 */
+ <0x49028000 0x49028000 0x001000>, /* ap 8 */
+ <0x49029000 0x49029000 0x001000>, /* ap 9 */
+ <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
+ <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
+ <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
+ <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
+ <0x49030000 0x49030000 0x001000>, /* ap 14 */
+ <0x49031000 0x49031000 0x001000>, /* ap 15 */
+ <0x49032000 0x49032000 0x001000>, /* ap 16 */
+ <0x49033000 0x49033000 0x001000>, /* ap 17 */
+ <0x49038000 0x49038000 0x001000>, /* ap 18 */
+ <0x49039000 0x49039000 0x001000>, /* ap 19 */
+ <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
+ <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
+ <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
+ <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
+ <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
+ <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
+ <0x49080000 0x49080000 0x010000>, /* ap 26 */
+ <0x49080000 0x49080000 0x001000>, /* ap 27 */
+ <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
+ <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
+ <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
+ <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
+ <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
+ <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
+
+ target-module@22000 { /* 0x40122000, ap 2 02.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2208c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>,
+ <0x49022000 0x49022000 0x1000>;
+
+ mcbsp1: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49022000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 33>,
+ <&sdma 34>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@24000 { /* 0x40124000, ap 4 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2408c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>,
+ <0x49024000 0x49024000 0x1000>;
+
+ mcbsp2: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49024000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 17>,
+ <&sdma 18>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@26000 { /* 0x40126000, ap 6 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2608c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>,
+ <0x49026000 0x49026000 0x1000>;
+
+ mcbsp3: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49026000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 19>,
+ <&sdma 20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@28000 { /* 0x40128000, ap 8 08.0 */
+ compatible = "ti,sysc-mcasp", "ti,sysc";
+ reg = <0x28000 0x4>,
+ <0x28004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>,
+ <0x49028000 0x49028000 0x1000>;
+
+ /*
+ * Child device unsupported by davinci-mcasp. At least
+ * RX path is disabled for omap4, and only DIT mode
+ * works with no I2S. See also old Android kernel
+ * omap-mcasp driver for more information.
+ */
+ };
+
+ target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>,
+ <0x4902a000 0x4902a000 0x1000>;
+ };
+
+ target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2e000 0x4>,
+ <0x2e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2e000 0x1000>,
+ <0x4902e000 0x4902e000 0x1000>;
+
+ dmic: dmic@0 {
+ compatible = "ti,omap4-dmic";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x4902e000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 67>;
+ dma-names = "up_link";
+ status = "disabled";
+ };
+ };
+
+ target-module@30000 { /* 0x40130000, ap 14 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x30000 0x4>,
+ <0x30010 0x4>,
+ <0x30014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>,
+ <0x49030000 0x49030000 0x1000>;
+
+ wdt3: wdt@0 {
+ compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>,
+ <0x49032000 0x49032000 0x1000>;
+
+ /* Must be only enabled for boards with pdmclk wired */
+ status = "disabled";
+
+ mcpdm: mcpdm@0 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 65>,
+ <&sdma 66>;
+ dma-names = "up_link", "dn_link";
+ };
+ };
+
+ target-module@38000 { /* 0x40138000, ap 18 12.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x38000 0x4>,
+ <0x38010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x1000>,
+ <0x49038000 0x49038000 0x1000>;
+
+ timer5: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x49038000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3a000 0x4>,
+ <0x3a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3a000 0x1000>,
+ <0x4903a000 0x4903a000 0x1000>;
+
+ timer6: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x4903a000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3c000 0x4>,
+ <0x3c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x1000>,
+ <0x4903c000 0x4903c000 0x1000>;
+
+ timer7: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x4903c000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>,
+ <0x4903e000 0x4903e000 0x1000>;
+
+ timer8: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x4903e000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@80000 { /* 0x40180000, ap 26 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>,
+ <0x49080000 0x49080000 0x10000>;
+ };
+
+ target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x10000>,
+ <0x490a0000 0x490a0000 0x10000>;
+ };
+
+ target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc0000 0x10000>,
+ <0x490c0000 0x490c0000 0x10000>;
+ };
+
+ target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xf1000 0x4>,
+ <0xf1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf1000 0x1000>,
+ <0x490f1000 0x490f1000 0x1000>;
+
+ /*
+ * No child device binding or driver in mainline.
+ * See Android tree and related upstreaming efforts
+ * for the old driver.
+ */
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+&l4_cfg { /* 0x4a000000 */
+ compatible = "ti,omap4-l4-cfg", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
+ <0x00080000 0x4a080000 0x080000>, /* segment 1 */
+ <0x00100000 0x4a100000 0x080000>, /* segment 2 */
+ <0x00180000 0x4a180000 0x080000>, /* segment 3 */
+ <0x00200000 0x4a200000 0x080000>, /* segment 4 */
+ <0x00280000 0x4a280000 0x080000>, /* segment 5 */
+ <0x00300000 0x4a300000 0x080000>; /* segment 6 */
+
+ segment@0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00002000 0x00002000 0x001000>, /* ap 3 */
+ <0x00003000 0x00003000 0x001000>, /* ap 4 */
+ <0x00004000 0x00004000 0x001000>, /* ap 5 */
+ <0x00005000 0x00005000 0x001000>, /* ap 6 */
+ <0x00056000 0x00056000 0x001000>, /* ap 7 */
+ <0x00057000 0x00057000 0x001000>, /* ap 8 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
+ <0x00058000 0x00058000 0x004000>, /* ap 10 */
+ <0x00062000 0x00062000 0x001000>, /* ap 11 */
+ <0x00063000 0x00063000 0x001000>, /* ap 12 */
+ <0x00008000 0x00008000 0x002000>, /* ap 23 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 24 */
+ <0x00066000 0x00066000 0x001000>, /* ap 25 */
+ <0x00067000 0x00067000 0x001000>, /* ap 26 */
+ <0x0005e000 0x0005e000 0x002000>, /* ap 80 */
+ <0x00060000 0x00060000 0x001000>, /* ap 81 */
+ <0x00064000 0x00064000 0x001000>, /* ap 86 */
+ <0x00065000 0x00065000 0x001000>; /* ap 87 */
+
+ target-module@2000 { /* 0x4a002000, ap 3 06.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_core";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ omap4_scm_core: scm@0 {
+ compatible = "ti,omap4-scm-core", "simple-bus";
+ reg = <0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ omap_control_usb2phy: control-phy@300 {
+ compatible = "ti,control-phy-usb2";
+ reg = <0x300 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usbotg: control-phy@33c {
+ compatible = "ti,control-phy-otghs";
+ reg = <0x33c 0x4>;
+ reg-names = "otghs_control";
+ };
+ };
+ };
+
+ target-module@4000 { /* 0x4a004000, ap 5 02.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x4000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ cm1: cm1@0 {
+ compatible = "ti,omap4-cm1", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ cm1_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm1_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@8000 { /* 0x4a008000, ap 23 32.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x8000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x2000>;
+
+ cm2: cm2@0 {
+ compatible = "ti,omap4-cm2", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ cm2_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm2_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x56000 0x4>,
+ <0x5602c 0x4>,
+ <0x56028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
+ clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x56000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <127>;
+ };
+ };
+
+ target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000 0x4>,
+ <0x58010 0x4>,
+ <0x58014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x58000 0x5000>;
+
+ hsi: hsi@0 {
+ compatible = "ti,omap4-hsi";
+ reg = <0x0 0x4000>,
+ <0x5000 0x1000>;
+ reg-names = "sys", "gdd";
+
+ clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
+ clock-names = "hsi_fck";
+
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gdd_mpu";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x4000>;
+
+ hsi_port1: hsi-port@2000 {
+ compatible = "ti,omap4-hsi-port";
+ reg = <0x2000 0x800>,
+ <0x2800 0x800>;
+ reg-names = "tx", "rx";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ hsi_port2: hsi-port@3000 {
+ compatible = "ti,omap4-hsi-port";
+ reg = <0x3000 0x800>,
+ <0x3800 0x800>;
+ reg-names = "tx", "rx";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5e000 0x2000>;
+ };
+
+ target-module@62000 { /* 0x4a062000, ap 11 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "usb_tll_hs";
+ reg = <0x62000 0x4>,
+ <0x62010 0x4>,
+ <0x62014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x62000 0x1000>;
+
+ usbhstll: usbhstll@0 {
+ compatible = "ti,usbhs-tll";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_host_hs";
+ reg = <0x64000 0x4>,
+ <0x64010 0x4>,
+ <0x64014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x64000 0x1000>;
+
+ usbhshost: usbhshost@0 {
+ compatible = "ti,usbhs-host";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ clocks = <&init_60m_fclk>,
+ <&xclk60mhsp1_ck>,
+ <&xclk60mhsp2_ck>;
+ clock-names = "refclk_60m_int",
+ "refclk_60m_ext_p1",
+ "refclk_60m_ext_p2";
+
+ usbhsohci: ohci@800 {
+ compatible = "ti,ohci-omap3";
+ reg = <0x800 0x400>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ remote-wakeup-connected;
+ };
+
+ usbhsehci: ehci@c00 {
+ compatible = "ti,ehci-omap";
+ reg = <0xc00 0x400>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ target-module@66000 { /* 0x4a066000, ap 25 26.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x66000 0x4>,
+ <0x66010 0x4>,
+ <0x66014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
+ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_tesla 1>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x1000>;
+
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
+ };
+ };
+
+ segment@80000 { /* 0x4a080000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
+ <0x0005a000 0x000da000 0x001000>, /* ap 14 */
+ <0x0005b000 0x000db000 0x001000>, /* ap 15 */
+ <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
+ <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
+ <0x0005e000 0x000de000 0x001000>, /* ap 18 */
+ <0x00060000 0x000e0000 0x001000>, /* ap 19 */
+ <0x00061000 0x000e1000 0x001000>, /* ap 20 */
+ <0x00074000 0x000f4000 0x001000>, /* ap 27 */
+ <0x00075000 0x000f5000 0x001000>, /* ap 28 */
+ <0x00076000 0x000f6000 0x001000>, /* ap 29 */
+ <0x00077000 0x000f7000 0x001000>, /* ap 30 */
+ <0x00036000 0x000b6000 0x001000>, /* ap 69 */
+ <0x00037000 0x000b7000 0x001000>, /* ap 70 */
+ <0x0004d000 0x000cd000 0x001000>, /* ap 78 */
+ <0x0004e000 0x000ce000 0x001000>, /* ap 79 */
+ <0x00029000 0x000a9000 0x001000>, /* ap 82 */
+ <0x0002a000 0x000aa000 0x001000>, /* ap 83 */
+ <0x0002b000 0x000ab000 0x001000>, /* ap 84 */
+ <0x0002c000 0x000ac000 0x001000>, /* ap 85 */
+ <0x0002d000 0x000ad000 0x001000>, /* ap 88 */
+ <0x0002e000 0x000ae000 0x001000>; /* ap 89 */
+
+ target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x29000 0x1000>;
+ };
+
+ target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2b400 0x4>,
+ <0x2b404 0x4>,
+ <0x2b408 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2b000 0x1000>;
+
+ usb_otg_hs: usb_otg_hs@0 {
+ compatible = "ti,omap4-musb";
+ reg = <0x0 0x7ff>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc", "dma";
+ usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ multipoint = <1>;
+ num-eps = <16>;
+ ram-bits = <12>;
+ ctrl-module = <&omap_control_usbotg>;
+ };
+ };
+
+ target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2d000 0x4>,
+ <0x2d010 0x4>,
+ <0x2d014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2d000 0x1000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ reg = <0x0 0x1f>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ usb2_phy: usb2phy@80 {
+ compatible = "ti,omap-usb2";
+ reg = <0x80 0x58>;
+ ctrl-module = <&omap_control_usb2phy>;
+ clocks = <&usb_phy_cm_clk32k>;
+ clock-names = "wkupclk";
+ #phy-cells = <0>;
+ };
+ };
+ };
+
+ /* d2d mdm */
+ target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x36000 0x4>,
+ <0x36010 0x4>,
+ <0x36014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
+ clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+ };
+
+ /* d2d mpu */
+ target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4d000 0x4>,
+ <0x4d010 0x4>,
+ <0x4d014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
+ clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4d000 0x1000>;
+ };
+
+ target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ reg = <0x59038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+
+ smartreflex_mpu: smartreflex@0 {
+ compatible = "ti,omap4-smartreflex-mpu";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ reg = <0x5b038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ smartreflex_iva: smartreflex@0 {
+ compatible = "ti,omap4-smartreflex-iva";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ reg = <0x5d038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+
+ smartreflex_core: smartreflex@0 {
+ compatible = "ti,omap4-smartreflex-core";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+ };
+
+ target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x74000 0x4>,
+ <0x74010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x74000 0x1000>;
+
+ mailbox: mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ mbox_ipu: mbox_ipu {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ mbox_dsp: mbox_dsp {
+ ti,mbox-tx = <3 0 0>;
+ ti,mbox-rx = <2 0 0>;
+ };
+ };
+ };
+
+ target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x76000 0x4>,
+ <0x76010 0x4>,
+ <0x76014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x76000 0x1000>;
+
+ hwspinlock: spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+ };
+
+ segment@100000 { /* 0x4a100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
+ <0x00001000 0x00101000 0x001000>, /* ap 22 */
+ <0x00002000 0x00102000 0x001000>, /* ap 61 */
+ <0x00003000 0x00103000 0x001000>, /* ap 62 */
+ <0x00008000 0x00108000 0x001000>, /* ap 63 */
+ <0x00009000 0x00109000 0x001000>, /* ap 64 */
+ <0x0000a000 0x0010a000 0x001000>, /* ap 65 */
+ <0x0000b000 0x0010b000 0x001000>; /* ap 66 */
+
+ target-module@0 { /* 0x4a100000, ap 21 2a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_pad_core";
+ reg = <0x0 0x4>,
+ <0x10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ omap4_pmx_core: pinmux@40 {
+ compatible = "ti,omap4-padconf",
+ "pinctrl-single";
+ reg = <0x40 0x0196>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
+ omap4_padconf_global: omap4_padconf_global@5a0 {
+ compatible = "syscon",
+ "simple-bus";
+ reg = <0x5a0 0x170>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5a0 0x170>;
+
+ pbias_regulator: pbias_regulator@60 {
+ compatible = "ti,pbias-omap4", "ti,pbias-omap";
+ reg = <0x60 0x4>;
+ syscon = <&omap4_padconf_global>;
+ pbias_mmc_reg: pbias_mmc_omap4 {
+ regulator-name = "pbias_mmc_omap4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+ };
+ };
+
+ target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@8000 { /* 0x4a108000, ap 63 62.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xa000 0x4>,
+ <0xa010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-delay-us = <2>;
+ /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
+ clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+
+ /* No child device binding or driver in mainline */
+ };
+ };
+
+ segment@180000 { /* 0x4a180000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@200000 { /* 0x4a200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
+ <0x0001f000 0x0021f000 0x001000>, /* ap 32 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 33 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 34 */
+ <0x00004000 0x00204000 0x001000>, /* ap 35 */
+ <0x00005000 0x00205000 0x001000>, /* ap 36 */
+ <0x00006000 0x00206000 0x001000>, /* ap 37 */
+ <0x00007000 0x00207000 0x001000>, /* ap 38 */
+ <0x00012000 0x00212000 0x001000>, /* ap 39 */
+ <0x00013000 0x00213000 0x001000>, /* ap 40 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 41 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 42 */
+ <0x00010000 0x00210000 0x001000>, /* ap 43 */
+ <0x00011000 0x00211000 0x001000>, /* ap 44 */
+ <0x00016000 0x00216000 0x001000>, /* ap 45 */
+ <0x00017000 0x00217000 0x001000>, /* ap 46 */
+ <0x00014000 0x00214000 0x001000>, /* ap 47 */
+ <0x00015000 0x00215000 0x001000>, /* ap 48 */
+ <0x00018000 0x00218000 0x001000>, /* ap 49 */
+ <0x00019000 0x00219000 0x001000>, /* ap 50 */
+ <0x00020000 0x00220000 0x001000>, /* ap 51 */
+ <0x00021000 0x00221000 0x001000>, /* ap 52 */
+ <0x00026000 0x00226000 0x001000>, /* ap 53 */
+ <0x00027000 0x00227000 0x001000>, /* ap 54 */
+ <0x00028000 0x00228000 0x001000>, /* ap 55 */
+ <0x00029000 0x00229000 0x001000>, /* ap 56 */
+ <0x0002a000 0x0022a000 0x001000>, /* ap 57 */
+ <0x0002b000 0x0022b000 0x001000>, /* ap 58 */
+ <0x0001c000 0x0021c000 0x001000>, /* ap 59 */
+ <0x0001d000 0x0021d000 0x001000>; /* ap 60 */
+
+ target-module@4000 { /* 0x4a204000, ap 35 42.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+ };
+
+ target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+ };
+
+ target-module@10000 { /* 0x4a210000, ap 43 52.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x1000>;
+ };
+
+ target-module@12000 { /* 0x4a212000, ap 39 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x12000 0x1000>;
+ };
+
+ target-module@14000 { /* 0x4a214000, ap 47 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module@16000 { /* 0x4a216000, ap 45 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x16000 0x1000>;
+ };
+
+ target-module@18000 { /* 0x4a218000, ap 49 38.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x1000>;
+ };
+
+ target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1c000 0x1000>;
+ };
+
+ target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e000 0x1000>;
+ };
+
+ target-module@20000 { /* 0x4a220000, ap 51 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+ };
+
+ target-module@26000 { /* 0x4a226000, ap 53 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+ };
+
+ target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>;
+ };
+
+ target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+ };
+ };
+
+ segment@280000 { /* 0x4a280000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
+ <0x00040000 0x00340000 0x001000>, /* ap 68 */
+ <0x00020000 0x00320000 0x004000>, /* ap 71 */
+ <0x00024000 0x00324000 0x002000>, /* ap 72 */
+ <0x00026000 0x00326000 0x001000>, /* ap 73 */
+ <0x00027000 0x00327000 0x001000>, /* ap 74 */
+ <0x00028000 0x00328000 0x001000>, /* ap 75 */
+ <0x00029000 0x00329000 0x001000>, /* ap 76 */
+ <0x00030000 0x00330000 0x010000>, /* ap 77 */
+ <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
+ <0x0002c000 0x0032c000 0x004000>; /* ap 91 */
+
+ l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x00020000>,
+ <0x00020000 0x00020000 0x00004000>,
+ <0x00024000 0x00024000 0x00002000>,
+ <0x00026000 0x00026000 0x00001000>,
+ <0x00027000 0x00027000 0x00001000>,
+ <0x00028000 0x00028000 0x00001000>,
+ <0x00029000 0x00029000 0x00001000>,
+ <0x0002a000 0x0002a000 0x00002000>,
+ <0x0002c000 0x0002c000 0x00004000>,
+ <0x00030000 0x00030000 0x00010000>;
+ };
+ };
+};
+
+&l4_wkup { /* 0x4a300000 */
+ compatible = "ti,omap4-l4-wkup", "simple-bus";
+ reg = <0x4a300000 0x800>,
+ <0x4a300800 0x800>,
+ <0x4a301000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
+ <0x00010000 0x4a310000 0x010000>, /* segment 1 */
+ <0x00020000 0x4a320000 0x010000>; /* segment 2 */
+
+ segment@0 { /* 0x4a300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00006000 0x00006000 0x002000>, /* ap 3 */
+ <0x00008000 0x00008000 0x001000>, /* ap 4 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
+ <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
+ <0x00004000 0x00004000 0x001000>, /* ap 17 */
+ <0x00005000 0x00005000 0x001000>, /* ap 18 */
+ <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
+ <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
+
+ target-module@4000 { /* 0x4a304000, ap 17 24.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "counter_32k";
+ reg = <0x4000 0x4>,
+ <0x4004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x0 0x20>;
+ };
+ };
+
+ target-module@6000 { /* 0x4a306000, ap 3 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x6000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x2000>;
+
+ prm: prm@0 {
+ compatible = "ti,omap4-prm", "simple-bus";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@a000 { /* 0x4a30a000, ap 15 34.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xa000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+
+ scrm: scrm@0 {
+ compatible = "ti,omap4-scrm";
+ reg = <0x0 0x2000>;
+
+ scrm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scrm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_wkup";
+ reg = <0xc000 0x4>,
+ <0xc010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ omap4_scm_wkup: scm@c000 {
+ compatible = "ti,omap4-scm-wkup";
+ reg = <0xc000 0x1000>;
+ };
+ };
+ };
+
+ segment@10000 { /* 0x4a310000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
+ <0x00001000 0x00011000 0x001000>, /* ap 6 */
+ <0x00004000 0x00014000 0x001000>, /* ap 7 */
+ <0x00005000 0x00015000 0x001000>, /* ap 8 */
+ <0x00008000 0x00018000 0x001000>, /* ap 9 */
+ <0x00009000 0x00019000 0x001000>, /* ap 10 */
+ <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
+ <0x0000d000 0x0001d000 0x001000>, /* ap 12 */
+ <0x0000e000 0x0001e000 0x001000>, /* ap 21 */
+ <0x0000f000 0x0001f000 0x001000>; /* ap 22 */
+
+ gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x0 0x4>,
+ <0x10 0x4>,
+ <0x114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>,
+ <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ gpio1: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ ti,gpio-always-on;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@4000 { /* 0x4a314000, ap 7 18.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ wdt2: wdt@0 {
+ compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ ti,hwmods = "timer1";
+ reg = <0x8000 0x4>,
+ <0x8010 0x4>,
+ <0x8014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-alwon;
+ };
+ };
+
+ target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xc000 0x4>,
+ <0xc010 0x4>,
+ <0xc014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ keypad: keypad@0 {
+ compatible = "ti,omap4-keypad";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ reg-names = "mpu";
+ };
+ };
+
+ target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_pad_wkup";
+ reg = <0xe000 0x4>,
+ <0xe010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe000 0x1000>;
+
+ omap4_pmx_wkup: pinmux@40 {
+ compatible = "ti,omap4-padconf",
+ "pinctrl-single";
+ reg = <0x40 0x0038>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+ };
+ };
+
+ segment@20000 { /* 0x4a320000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
+ <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
+ <0x00000000 0x00020000 0x001000>, /* ap 23 */
+ <0x00001000 0x00021000 0x001000>, /* ap 24 */
+ <0x00002000 0x00022000 0x001000>, /* ap 25 */
+ <0x00003000 0x00023000 0x001000>, /* ap 26 */
+ <0x00004000 0x00024000 0x001000>, /* ap 27 */
+ <0x00005000 0x00025000 0x001000>, /* ap 28 */
+ <0x00007000 0x00027000 0x000400>, /* ap 29 */
+ <0x00008000 0x00028000 0x000800>, /* ap 30 */
+ <0x00009000 0x00029000 0x000400>; /* ap 31 */
+
+ target-module@0 { /* 0x4a320000, ap 23 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+ };
+
+ target-module@2000 { /* 0x4a322000, ap 25 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@4000 { /* 0x4a324000, ap 27 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4a326000, ap 13 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00006000 0x00001000>,
+ <0x00001000 0x00007000 0x00000400>,
+ <0x00002000 0x00008000 0x00000800>,
+ <0x00003000 0x00009000 0x00000400>;
+ };
+ };
+};
+
+&l4_per { /* 0x48000000 */
+ compatible = "ti,omap4-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
+ <0x00200000 0x48200000 0x200000>; /* segment 1 */
+
+ segment@0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x000400>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00020000 0x00020000 0x001000>, /* ap 3 */
+ <0x00021000 0x00021000 0x001000>, /* ap 4 */
+ <0x00032000 0x00032000 0x001000>, /* ap 5 */
+ <0x00033000 0x00033000 0x001000>, /* ap 6 */
+ <0x00034000 0x00034000 0x001000>, /* ap 7 */
+ <0x00035000 0x00035000 0x001000>, /* ap 8 */
+ <0x00036000 0x00036000 0x001000>, /* ap 9 */
+ <0x00037000 0x00037000 0x001000>, /* ap 10 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
+ <0x00040000 0x00040000 0x010000>, /* ap 13 */
+ <0x00050000 0x00050000 0x001000>, /* ap 14 */
+ <0x00055000 0x00055000 0x001000>, /* ap 15 */
+ <0x00056000 0x00056000 0x001000>, /* ap 16 */
+ <0x00057000 0x00057000 0x001000>, /* ap 17 */
+ <0x00058000 0x00058000 0x001000>, /* ap 18 */
+ <0x00059000 0x00059000 0x001000>, /* ap 19 */
+ <0x0005a000 0x0005a000 0x001000>, /* ap 20 */
+ <0x0005b000 0x0005b000 0x001000>, /* ap 21 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 22 */
+ <0x0005d000 0x0005d000 0x001000>, /* ap 23 */
+ <0x0005e000 0x0005e000 0x001000>, /* ap 24 */
+ <0x00060000 0x00060000 0x001000>, /* ap 25 */
+ <0x0006a000 0x0006a000 0x001000>, /* ap 26 */
+ <0x0006b000 0x0006b000 0x001000>, /* ap 27 */
+ <0x0006c000 0x0006c000 0x001000>, /* ap 28 */
+ <0x0006d000 0x0006d000 0x001000>, /* ap 29 */
+ <0x0006e000 0x0006e000 0x001000>, /* ap 30 */
+ <0x0006f000 0x0006f000 0x001000>, /* ap 31 */
+ <0x00070000 0x00070000 0x001000>, /* ap 32 */
+ <0x00071000 0x00071000 0x001000>, /* ap 33 */
+ <0x00072000 0x00072000 0x001000>, /* ap 34 */
+ <0x00073000 0x00073000 0x001000>, /* ap 35 */
+ <0x00061000 0x00061000 0x001000>, /* ap 36 */
+ <0x00096000 0x00096000 0x001000>, /* ap 37 */
+ <0x00097000 0x00097000 0x001000>, /* ap 38 */
+ <0x00076000 0x00076000 0x001000>, /* ap 39 */
+ <0x00077000 0x00077000 0x001000>, /* ap 40 */
+ <0x00078000 0x00078000 0x001000>, /* ap 41 */
+ <0x00079000 0x00079000 0x001000>, /* ap 42 */
+ <0x00086000 0x00086000 0x001000>, /* ap 43 */
+ <0x00087000 0x00087000 0x001000>, /* ap 44 */
+ <0x00088000 0x00088000 0x001000>, /* ap 45 */
+ <0x00089000 0x00089000 0x001000>, /* ap 46 */
+ <0x000b0000 0x000b0000 0x001000>, /* ap 47 */
+ <0x000b1000 0x000b1000 0x001000>, /* ap 48 */
+ <0x00098000 0x00098000 0x001000>, /* ap 49 */
+ <0x00099000 0x00099000 0x001000>, /* ap 50 */
+ <0x0009a000 0x0009a000 0x001000>, /* ap 51 */
+ <0x0009b000 0x0009b000 0x001000>, /* ap 52 */
+ <0x0009c000 0x0009c000 0x001000>, /* ap 53 */
+ <0x0009d000 0x0009d000 0x001000>, /* ap 54 */
+ <0x0009e000 0x0009e000 0x001000>, /* ap 55 */
+ <0x0009f000 0x0009f000 0x001000>, /* ap 56 */
+ <0x00090000 0x00090000 0x002000>, /* ap 57 */
+ <0x00092000 0x00092000 0x001000>, /* ap 58 */
+ <0x000a4000 0x000a4000 0x001000>, /* ap 59 */
+ <0x000a6000 0x000a6000 0x001000>, /* ap 60 */
+ <0x000a8000 0x000a8000 0x004000>, /* ap 61 */
+ <0x000ac000 0x000ac000 0x001000>, /* ap 62 */
+ <0x000ad000 0x000ad000 0x001000>, /* ap 63 */
+ <0x000ae000 0x000ae000 0x001000>, /* ap 64 */
+ <0x000b2000 0x000b2000 0x001000>, /* ap 65 */
+ <0x000b3000 0x000b3000 0x001000>, /* ap 66 */
+ <0x000b4000 0x000b4000 0x001000>, /* ap 67 */
+ <0x000b5000 0x000b5000 0x001000>, /* ap 68 */
+ <0x000b8000 0x000b8000 0x001000>, /* ap 69 */
+ <0x000b9000 0x000b9000 0x001000>, /* ap 70 */
+ <0x000ba000 0x000ba000 0x001000>, /* ap 71 */
+ <0x000bb000 0x000bb000 0x001000>, /* ap 72 */
+ <0x000d1000 0x000d1000 0x001000>, /* ap 73 */
+ <0x000d2000 0x000d2000 0x001000>, /* ap 74 */
+ <0x000d5000 0x000d5000 0x001000>, /* ap 75 */
+ <0x000d6000 0x000d6000 0x001000>, /* ap 76 */
+ <0x000a2000 0x000a2000 0x001000>, /* ap 79 */
+ <0x000a3000 0x000a3000 0x001000>, /* ap 80 */
+ <0x00001400 0x00001400 0x000400>, /* ap 81 */
+ <0x00001800 0x00001800 0x000400>, /* ap 82 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 83 */
+ <0x000a5000 0x000a5000 0x001000>; /* ap 84 */
+
+ target-module@20000 { /* 0x48020000, ap 3 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x20050 0x4>,
+ <0x20054 0x4>,
+ <0x20058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ uart3: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@32000 { /* 0x48032000, ap 5 02.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>,
+ <0x32014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@34000 { /* 0x48034000, ap 7 04.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x34000 0x4>,
+ <0x34010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x1000>;
+
+ timer3: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@36000 { /* 0x48036000, ap 9 0e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x36000 0x4>,
+ <0x36010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+
+ timer4: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ timer9: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ /* Unused DSS L4 access, see L3 instead */
+ target-module@40000 { /* 0x48040000, ap 13 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x10000>;
+ };
+
+ target-module@55000 { /* 0x48055000, ap 15 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55000 0x4>,
+ <0x55010 0x4>,
+ <0x55114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@57000 { /* 0x48057000, ap 17 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x57000 0x4>,
+ <0x57010 0x4>,
+ <0x57114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x57000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@59000 { /* 0x48059000, ap 19 10.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x59000 0x4>,
+ <0x59010 0x4>,
+ <0x59114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+
+ gpio4: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5b000 0x4>,
+ <0x5b010 0x4>,
+ <0x5b114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ gpio5: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5d000 0x4>,
+ <0x5d010 0x4>,
+ <0x5d114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+
+ gpio6: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@60000 { /* 0x48060000, ap 25 1e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x60000 0x8>,
+ <0x60010 0x8>,
+ <0x60090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+
+ i2c3: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6a050 0x4>,
+ <0x6a054 0x4>,
+ <0x6a058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6a000 0x1000>;
+
+ uart1: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6c050 0x4>,
+ <0x6c054 0x4>,
+ <0x6c058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6c000 0x1000>;
+
+ uart2: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6e050 0x4>,
+ <0x6e054 0x4>,
+ <0x6e058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6e000 0x1000>;
+
+ uart4: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@70000 { /* 0x48070000, ap 32 28.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x70000 0x8>,
+ <0x70010 0x8>,
+ <0x70090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x70000 0x1000>;
+
+ i2c1: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@72000 { /* 0x48072000, ap 34 30.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x72000 0x8>,
+ <0x72010 0x8>,
+ <0x72090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x72000 0x1000>;
+
+ i2c2: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@76000 { /* 0x48076000, ap 39 38.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x76000 0x4>,
+ <0x76010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x76000 0x1000>;
+
+ /* No child device binding or driver in mainline */
+ };
+
+ target-module@78000 { /* 0x48078000, ap 41 1a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x78000 0x4>,
+ <0x78010 0x4>,
+ <0x78014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x78000 0x1000>;
+
+ elm: elm@0 {
+ compatible = "ti,am3352-elm";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@86000 { /* 0x48086000, ap 43 24.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x86000 0x4>,
+ <0x86010 0x4>,
+ <0x86014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x86000 0x1000>;
+
+ timer10: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@88000 { /* 0x48088000, ap 45 2e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x88000 0x4>,
+ <0x88010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x88000 0x1000>;
+
+ timer11: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x91fe0 0x4>,
+ <0x91fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x90000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@96000 { /* 0x48096000, ap 37 26.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x9608c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x96000 0x1000>;
+
+ mcbsp4: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>; /* L4 Interconnect */
+ reg-names = "mpu";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 31>,
+ <&sdma 32>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@98000 { /* 0x48098000, ap 49 22.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x98000 0x4>,
+ <0x98010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x98000 0x1000>;
+
+ mcspi1: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+ };
+
+ target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9a000 0x4>,
+ <0x9a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9a000 0x1000>;
+
+ mcspi2: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+ };
+
+ target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9c000 0x4>,
+ <0x9c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+
+ mmc1: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+ };
+
+ target-module@9e000 { /* 0x4809e000, ap 55 48.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9e000 0x1000>;
+ };
+
+ target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+ };
+
+ target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x000a4000 0x00001000>,
+ <0x00001000 0x000a5000 0x00001000>;
+ };
+
+ des_target: target-module@a5000 { /* 0x480a5000 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa5030 0x4>,
+ <0xa5034 0x4>,
+ <0xa5038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa5000 0x00001000>;
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 117>, <&sdma 116>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x4000>;
+ };
+
+ target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xad000 0x4>,
+ <0xad010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xad000 0x1000>;
+
+ mmc3: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb0000 0x1000>;
+ };
+
+ target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xb2000 0x4>,
+ <0xb2014 0x4>,
+ <0xb2018 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ ti,no-reset-on-init;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb2000 0x1000>;
+
+ hdqw1w: 1w@0 {
+ compatible = "ti,omap3-1w";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb4000 0x4>,
+ <0xb4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb4000 0x1000>;
+
+ mmc2: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb8000 0x4>,
+ <0xb8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb8000 0x1000>;
+
+ mcspi3: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xba000 0x4>,
+ <0xba010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xba000 0x1000>;
+
+ mcspi4: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd1000 0x4>,
+ <0xd1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd1000 0x1000>;
+
+ mmc4: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd5000 0x4>,
+ <0xd5010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd5000 0x1000>;
+
+ mmc5: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 59>, <&sdma 60>;
+ dma-names = "tx", "rx";
+ };
+ };
+ };
+
+ segment@200000 { /* 0x48200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
+ <0x00151000 0x00351000 0x001000>; /* ap 78 */
+
+ target-module@150000 { /* 0x48350000, ap 77 4c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x150000 0x8>,
+ <0x150010 0x8>,
+ <0x150090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x150000 0x1000>;
+
+ i2c4: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common omap4 mcpdm configuration
+ *
+ * Only include this file if your board has pdmclk wired from the
+ * pmic to ABE as mcpdm uses an external clock for the module.
+ */
+
+&omap4_pmx_core {
+ mcpdm_pins: pinmux_mcpdm_pins {
+ pinctrl-single,pins = <
+ /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
+ OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+ /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
+ OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+ /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
+ OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)
+
+ /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
+ OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+ /* 0x4a10010e abe_clks.abe_clks ah26 */
+ OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ >;
+ };
+};
+
+&mcpdm_module {
+ /*
+ * McPDM pads must be muxed at the interconnect target module
+ * level as the module on the SoC needs external clock from
+ * the PMIC
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcpdm_pins>;
+ status = "okay";
+};
+
+&mcpdm {
+ clocks = <&twl6040>;
+ clock-names = "pdmclk";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include <dt-bindings/input/input.h>
+#include "elpida_ecb240abacn.dtsi"
+#include "omap4-mcpdm.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display0 = &dvi0;
+ display1 = &hdmi0;
+ ethernet = ðernet;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &led_wkgpio_pins
+ >;
+
+ heartbeat {
+ label = "pandaboard::status1";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc {
+ label = "pandaboard::status2";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ gpio_keys: gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &button_pins
+ >;
+
+ buttonS2 {
+ label = "button S2";
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */
+ linux,code = <BTN_0>;
+ wakeup-source;
+ };
+ };
+
+ sound: sound {
+ compatible = "ti,abe-twl6040";
+ ti,model = "PandaBoard";
+
+ ti,mclk-freq = <38400000>;
+
+ ti,mcpdm = <&mcpdm>;
+
+ ti,twl6040 = <&twl6040>;
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Ext Spk", "HFL",
+ "Ext Spk", "HFR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "HSMIC", "Headset Mic",
+ "Headset Mic", "Headset Mic Bias",
+ "AFML", "Line In",
+ "AFMR", "Line In";
+ };
+
+ /* HS USB Port 1 Power */
+ hsusb1_power: hsusb1_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ /*
+ * boot-on is required along with always-on as the
+ * regulator framework doesn't enable the regulator
+ * if boot-on is not there.
+ */
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
+ #phy-cells = <0>;
+ vcc-supply = <&hsusb1_power>;
+ clocks = <&auxclk3_ck>;
+ clock-names = "main_clk";
+ clock-frequency = <19200000>;
+ };
+
+ /* regulator for wl12xx on sdio5 */
+ wl12xx_vmmc: wl12xx_vmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_gpio>;
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ tfp410: encoder0 {
+ compatible = "ti,tfp410";
+ powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ dvi0: connector0 {
+ compatible = "dvi-connector";
+ label = "dvi";
+
+ digital;
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder1 {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
+ <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
+ <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector1 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+};
+
+&omap4_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &dss_dpi_pins
+ &tfp410_pins
+ &dss_hdmi_pins
+ &tpd12s015_pins
+ &hsusbb1_pins
+ >;
+
+ twl6040_pins: pinmux_twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
+ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
+ >;
+ };
+
+ mcbsp1_pins: pinmux_mcbsp1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+ OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+ OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
+ >;
+ };
+
+ dss_dpi_pins: pinmux_dss_dpi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */
+ OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */
+ OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */
+ OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */
+ OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */
+ OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */
+ OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */
+ OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */
+ OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */
+ OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */
+ OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */
+
+ OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */
+ OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */
+ OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */
+ OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */
+ OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */
+ OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */
+ OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */
+ OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */
+ OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */
+ OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */
+ OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */
+ OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */
+ OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */
+
+ OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */
+ OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */
+ OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */
+ >;
+ };
+
+ tfp410_pins: pinmux_tfp410_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */
+ >;
+ };
+
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
+ OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
+ >;
+ };
+
+ hsusbb1_pins: pinmux_hsusbb1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+ OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+ OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+ OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+ OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+ OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+ OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+ OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+ OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+ OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+ OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
+ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
+ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
+
+ i2c4_pins: pinmux_i2c4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
+ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
+ >;
+ };
+
+ /*
+ * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
+ * REVISIT: Are the pull-ups needed for GPIO 48 and 49?
+ */
+ wl12xx_gpio: pinmux_wl12xx_gpio {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
+ OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */
+ OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */
+ OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */
+ >;
+ };
+
+ /* wl12xx GPIO inputs and SDIO pins */
+ wl12xx_pins: pinmux_wl12xx_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
+ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
+ OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
+ OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
+ OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
+ OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
+ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
+ >;
+ };
+
+ button_pins: pinmux_button_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
+ OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ >;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ clock-frequency = <400000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ /* IRQ# = 7 */
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
+ };
+
+ twl6040: twl@4b {
+ compatible = "ti,twl6040";
+ #clock-cells = <0>;
+ reg = <0x4b>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&twl6040_pins>;
+
+ /* IRQ# = 119 */
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
+ ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
+
+ vio-supply = <&v1v8>;
+ v2v1-supply = <&v2v1>;
+ enable-active-high;
+ };
+};
+
+#include "twl6030.dtsi"
+#include "twl6030_omap4.dtsi"
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+
+ clock-frequency = <100000>;
+
+ /*
+ * Display monitor features are burnt in their EEPROM as EDID data.
+ * The EEPROM is connected as I2C slave device.
+ */
+ eeprom@50 {
+ compatible = "ti,eeprom";
+ reg = <0x50>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&mmc4 {
+ status = "disabled";
+};
+
+&mmc5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_pins>;
+ vmmc-supply = <&wl12xx_vmmc>;
+ interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x10e>;
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ /* gpio_53 with gpmc_ncs3 pad as wakeup */
+ interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&omap4_pmx_core 0x3a>;
+ interrupt-names = "irq", "wakeup";
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+&emif1 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&mcbsp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp1_pins>;
+ status = "okay";
+};
+
+&twl_usb_comparator {
+ usb-supply = <&vusb>;
+};
+
+&uart2 {
+ interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART2_RX>;
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART3_RX>;
+};
+
+&uart4 {
+ interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART4_RX>;
+};
+
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
+
+&usbhshost {
+ port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&dsi2 {
+ status = "ok";
+ vdd-supply = <&vcxio>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&vdac>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
+
+/ {
+ model = "TI OMAP4 PandaBoard-ES";
+ compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
+};
+
+/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
+&sound {
+ ti,model = "PandaBoardES";
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Ext Spk", "HFL",
+ "Ext Spk", "HFR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "AFML", "Line In",
+ "AFMR", "Line In";
+};
+
+/* PandaboardES has external pullups on SCL & SDA */
+&dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+};
+
+&omap4_pmx_core {
+ led_gpio_pins: gpio_led_pmx {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
+ >;
+ };
+
+ button_pins: pinmux_button_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
+ >;
+ };
+};
+
+&led_wkgpio_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ >;
+};
+
+&leds {
+ pinctrl-0 = <
+ &led_gpio_pins
+ &led_wkgpio_pins
+ >;
+
+ heartbeat {
+ gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+ };
+ mmc {
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&gpio_keys {
+ buttonS2 {
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */
+ };
+};
+
+&gpio1_target {
+ ti,no-reset-on-init;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
+
+/ {
+ model = "TI OMAP4 PandaBoard";
+ compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "omap4-sdp.dts"
+
+/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
+&dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
+#include "omap4-mcpdm.dtsi"
+
+/ {
+ model = "TI OMAP4 SDP board";
+ compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+
+ aliases {
+ display0 = &lcd0;
+ display1 = &lcd1;
+ display2 = &hdmi0;
+ };
+
+ vdd_eth: fixedregulator-vdd-eth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&enet_enable_gpio>;
+
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_ETH";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */
+ enable-active-high;
+ regulator-boot-on;
+ startup-delay-us = <25000>;
+ };
+
+ vbat: fixedregulator-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "VBAT";
+ regulator-min-microvolt = <3750000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ debug0 {
+ label = "omap4:green:debug0";
+ gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
+ };
+
+ debug1 {
+ label = "omap4:green:debug1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
+ };
+
+ debug2 {
+ label = "omap4:green:debug2";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
+ };
+
+ debug3 {
+ label = "omap4:green:debug3";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
+ };
+
+ debug4 {
+ label = "omap4:green:debug4";
+ gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
+ };
+
+ user1 {
+ label = "omap4:blue:user";
+ gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
+ };
+
+ user2 {
+ label = "omap4:red:user";
+ gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
+ };
+
+ user3 {
+ label = "omap4:green:user";
+ gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+ kpad {
+ label = "omap4::keypad";
+ pwms = <&twl_pwm 0 7812500>;
+ max-brightness = <127>;
+ };
+
+ charging {
+ label = "omap4:green:chrg";
+ pwms = <&twl_pwmled 0 7812500>;
+ max-brightness = <255>;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&twl_pwm 1 7812500>;
+ brightness-levels = <
+ 0 10 20 30 40
+ 50 60 70 80 90
+ 100 110 120 127
+ >;
+ default-brightness-level = <13>;
+ };
+
+ sound {
+ compatible = "ti,abe-twl6040";
+ ti,model = "SDP4430";
+
+ ti,jack-detection = <1>;
+ ti,mclk-freq = <38400000>;
+
+ ti,mcpdm = <&mcpdm>;
+ ti,dmic = <&dmic>;
+
+ ti,twl6040 = <&twl6040>;
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Earphone Spk", "EP",
+ "Ext Spk", "HFL",
+ "Ext Spk", "HFR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "Vibrator", "VIBRAL",
+ "Vibrator", "VIBRAR",
+ "HSMIC", "Headset Mic",
+ "Headset Mic", "Headset Mic Bias",
+ "MAINMIC", "Main Handset Mic",
+ "Main Handset Mic", "Main Mic Bias",
+ "SUBMIC", "Sub Handset Mic",
+ "Sub Handset Mic", "Main Mic Bias",
+ "AFML", "Line In",
+ "AFMR", "Line In",
+ "DMic", "Digital Mic",
+ "Digital Mic", "Digital Mic1 Bias";
+ };
+
+ /* regulator for wl12xx on sdio5 */
+ wl12xx_vmmc: wl12xx_vmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_gpio>;
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
+ <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
+ <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "c";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+};
+
+&omap4_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &dss_hdmi_pins
+ &tpd12s015_pins
+ >;
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
+ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
+ OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */
+ OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
+ OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+ >;
+ };
+
+ uart4_pins: pinmux_uart4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */
+ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */
+ >;
+ };
+
+ twl6040_pins: pinmux_twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
+ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
+ >;
+ };
+
+ dmic_pins: pinmux_dmic_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */
+ OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */
+ OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */
+ OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */
+ >;
+ };
+
+ mcbsp1_pins: pinmux_mcbsp1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+ OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+ OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
+ >;
+ };
+
+ mcbsp2_pins: pinmux_mcbsp2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
+ OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */
+ OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */
+ OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
+ >;
+ };
+
+ mcspi1_pins: pinmux_mcspi1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
+ OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
+ OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
+ OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
+ >;
+ };
+
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
+ OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
+ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
+ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
+
+ i2c4_pins: pinmux_i2c4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
+ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
+ >;
+ };
+
+ /* wl12xx GPIO output for WLAN_EN */
+ wl12xx_gpio: pinmux_wl12xx_gpio {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */
+ >;
+ };
+
+ /* wl12xx GPIO inputs and SDIO pins */
+ wl12xx_pins: pinmux_wl12xx_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
+ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
+ OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
+ OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
+ OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
+ OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
+ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
+ >;
+ };
+
+ /* gpio_48 for ENET_ENABLE */
+ enet_enable_gpio: pinmux_enet_enable_gpio {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */
+ >;
+ };
+
+ ks8851_pins: pinmux_ks8851_pins {
+ pinctrl-single,pins = <
+ /* ENET_INT */
+ OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */
+ /*
+ * Misterious pin which makes the ethernet working
+ * The legacy board file requested this pin on boot
+ * (ETH_KS8851_QUART) and set it to high, similarly to
+ * the ENET_ENABLE pin.
+ * We could use gpio-hog to keep it high, but let's use
+ * it as a reset GPIO for ks8851.
+ */
+ OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */
+ >;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ clock-frequency = <400000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
+ };
+
+ twl6040: twl@4b {
+ compatible = "ti,twl6040";
+ #clock-cells = <0>;
+ reg = <0x4b>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&twl6040_pins>;
+
+ /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
+ ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
+
+ vio-supply = <&v1v8>;
+ v2v1-supply = <&v2v1>;
+ enable-active-high;
+
+ /* regulators for vibra motor */
+ vddvibl-supply = <&vbat>;
+ vddvibr-supply = <&vbat>;
+
+ vibra {
+ /* Vibra driver, motor resistance parameters */
+ ti,vibldrv-res = <8>;
+ ti,vibrdrv-res = <3>;
+ ti,viblmotor-res = <10>;
+ ti,vibrmotor-res = <10>;
+ };
+ };
+};
+
+#include "twl6030.dtsi"
+#include "twl6030_omap4.dtsi"
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+
+ clock-frequency = <400000>;
+
+ /*
+ * Temperature Sensor
+ * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+ */
+ tmp105@48 {
+ compatible = "ti,tmp105";
+ reg = <0x48>;
+ };
+
+ /*
+ * Ambient Light Sensor
+ * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
+ */
+ bh1780@29 {
+ compatible = "rohm,bh1780";
+ reg = <0x29>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+
+ clock-frequency = <400000>;
+
+ /*
+ * 3-Axis Digital Compass
+ * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+ */
+ hmc5843@1e {
+ compatible = "honeywell,hmc5843";
+ reg = <0x1e>;
+ };
+};
+
+&mcspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi1_pins>;
+
+ eth@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ks8851_pins>;
+
+ compatible = "ks8851";
+ spi-max-frequency = <24000000>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
+ vdd-supply = <&vdd_eth>;
+ reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vaux1>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&mmc4 {
+ status = "disabled";
+};
+
+&mmc5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_pins>;
+ vmmc-supply = <&wl12xx_vmmc>;
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1281";
+ reg = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&emif1 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&keypad {
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ linux,keymap = <0x00000012 /* KEY_E */
+ 0x00010013 /* KEY_R */
+ 0x00020014 /* KEY_T */
+ 0x00030066 /* KEY_HOME */
+ 0x0004003f /* KEY_F5 */
+ 0x000500f0 /* KEY_UNKNOWN */
+ 0x00060017 /* KEY_I */
+ 0x0007002a /* KEY_LEFTSHIFT */
+ 0x01000020 /* KEY_D*/
+ 0x01010021 /* KEY_F */
+ 0x01020022 /* KEY_G */
+ 0x010300e7 /* KEY_SEND */
+ 0x01040040 /* KEY_F6 */
+ 0x010500f0 /* KEY_UNKNOWN */
+ 0x01060025 /* KEY_K */
+ 0x0107001c /* KEY_ENTER */
+ 0x0200002d /* KEY_X */
+ 0x0201002e /* KEY_C */
+ 0x0202002f /* KEY_V */
+ 0x0203006b /* KEY_END */
+ 0x02040041 /* KEY_F7 */
+ 0x020500f0 /* KEY_UNKNOWN */
+ 0x02060034 /* KEY_DOT */
+ 0x0207003a /* KEY_CAPSLOCK */
+ 0x0300002c /* KEY_Z */
+ 0x0301004e /* KEY_KPLUS */
+ 0x03020030 /* KEY_B */
+ 0x0303003b /* KEY_F1 */
+ 0x03040042 /* KEY_F8 */
+ 0x030500f0 /* KEY_UNKNOWN */
+ 0x03060018 /* KEY_O */
+ 0x03070039 /* KEY_SPACE */
+ 0x04000011 /* KEY_W */
+ 0x04010015 /* KEY_Y */
+ 0x04020016 /* KEY_U */
+ 0x0403003c /* KEY_F2 */
+ 0x04040073 /* KEY_VOLUMEUP */
+ 0x040500f0 /* KEY_UNKNOWN */
+ 0x04060026 /* KEY_L */
+ 0x04070069 /* KEY_LEFT */
+ 0x0500001f /* KEY_S */
+ 0x05010023 /* KEY_H */
+ 0x05020024 /* KEY_J */
+ 0x0503003d /* KEY_F3 */
+ 0x05040043 /* KEY_F9 */
+ 0x05050072 /* KEY_VOLUMEDOWN */
+ 0x05060032 /* KEY_M */
+ 0x0507006a /* KEY_RIGHT */
+ 0x06000010 /* KEY_Q */
+ 0x0601001e /* KEY_A */
+ 0x06020031 /* KEY_N */
+ 0x0603009e /* KEY_BACK */
+ 0x0604000e /* KEY_BACKSPACE */
+ 0x060500f0 /* KEY_UNKNOWN */
+ 0x06060019 /* KEY_P */
+ 0x06070067 /* KEY_UP */
+ 0x07000094 /* KEY_PROG1 */
+ 0x07010095 /* KEY_PROG2 */
+ 0x070200ca /* KEY_PROG3 */
+ 0x070300cb /* KEY_PROG4 */
+ 0x0704003e /* KEY_F4 */
+ 0x070500f0 /* KEY_UNKNOWN */
+ 0x07060160 /* KEY_OK */
+ 0x0707006c>; /* KEY_DOWN */
+ linux,input-no-autorepeat;
+};
+
+&uart2 {
+ interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART2_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART3_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+ interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART4_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+};
+
+&mcbsp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp1_pins>;
+ status = "okay";
+};
+
+&mcbsp2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp2_pins>;
+ status = "okay";
+};
+
+&dmic {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dmic_pins>;
+ status = "okay";
+};
+
+&twl_usb_comparator {
+ usb-supply = <&vusb>;
+};
+
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
+
+&dss {
+ status = "ok";
+};
+
+&dsi1 {
+ status = "ok";
+ vdd-supply = <&vcxio>;
+
+ port {
+ dsi1_out_ep: endpoint {
+ remote-endpoint = <&lcd0_in>;
+ lanes = <0 1 2 3 4 5>;
+ };
+ };
+
+ lcd0: display {
+ compatible = "tpo,taal", "panel-dsi-cm";
+ label = "lcd0";
+
+ reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
+
+ port {
+ lcd0_in: endpoint {
+ remote-endpoint = <&dsi1_out_ep>;
+ };
+ };
+ };
+};
+
+&dsi2 {
+ status = "ok";
+ vdd-supply = <&vcxio>;
+
+ port {
+ dsi2_out_ep: endpoint {
+ remote-endpoint = <&lcd1_in>;
+ lanes = <0 1 2 3 4 5>;
+ };
+ };
+
+ lcd1: display {
+ compatible = "tpo,taal", "panel-dsi-cm";
+ label = "lcd1";
+
+ reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
+
+ port {
+ lcd1_in: endpoint {
+ remote-endpoint = <&dsi2_out_ep>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&vdac>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2020 Tero Kristo <t-kristo@ti.com>
+ */
+
+&l4_cfg {
+ segment@0 {
+ /* SCM Core */
+ target-module@2000 {
+ compatible = "simple-bus";
+ };
+
+ /* USB HS */
+ target-module@64000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+&l4_per {
+ segment@0 {
+ /* UART3 */
+ target-module@20000 {
+ compatible = "simple-bus";
+ };
+
+ /* I2C1 */
+ target-module@70000 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC1 */
+ target-module@9c000 {
+ compatible = "simple-bus";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/clock/omap4.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap4.h>
+
+/ {
+ compatible = "ti,omap4430", "ti,omap4";
+ interrupt-parent = <&wakeupgen>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&L2>;
+ reg = <0x0>;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&L2>;
+ reg = <0x1>;
+ };
+ };
+
+ /*
+ * Note that 4430 needs cross trigger interface (CTI) supported
+ * before we can configure the interrupts. This means sampling
+ * events are not supported for pmu. Note that 4460 does not use
+ * CTI, see also 4460.dtsi.
+ */
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ ti,hwmods = "debugss";
+ };
+
+ gic: interrupt-controller@48241000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48241000 0x1000>,
+ <0x48240100 0x0100>;
+ interrupt-parent = <&gic>;
+ };
+
+ L2: l2-cache-controller@48242000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x48242000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ local-timer@48240600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ clocks = <&mpu_periphclk>;
+ reg = <0x48240600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
+ interrupt-parent = <&gic>;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = "ti,omap4-wugen-mpu";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48281000 0x1000>;
+ interrupt-parent = <&gic>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap4-mpu";
+ ti,hwmods = "mpu";
+ sram = <&ocmcram>;
+ };
+
+ dsp {
+ compatible = "ti,omap3-c64";
+ };
+
+ iva {
+ compatible = "ti,ivahd";
+ ti,hwmods = "iva";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP4 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+ reg = <0x44000000 0x1000>,
+ <0x44800000 0x2000>,
+ <0x45000000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ l4_wkup: interconnect@4a300000 {
+ };
+
+ l4_cfg: interconnect@4a000000 {
+ };
+
+ l4_per: interconnect@48000000 {
+ };
+
+ l4_abe: interconnect@40100000 {
+ };
+
+ ocmcram: sram@40304000 {
+ compatible = "mmio-sram";
+ reg = <0x40304000 0xa000>; /* 40k */
+ };
+
+ gpmc: gpmc@50000000 {
+ compatible = "ti,omap4430-gpmc";
+ reg = <0x50000000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 4>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <4>;
+ ti,hwmods = "gpmc";
+ ti,no-idle-on-init;
+ clocks = <&l3_div_ck>;
+ clock-names = "fck";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ target-module@52000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "iss";
+ reg = <0x52000000 0x4>,
+ <0x52000010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-delay-us = <2>;
+ clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x52000000 0x1000000>;
+
+ /* No child device binding, driver in staging */
+ };
+
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
+ };
+
+ target-module@4012c000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x4012c000 0x4>,
+ <0x4012c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
+ <0x4902c000 0x4902c000 0x1000>; /* L3 */
+
+ /* No child device binding or driver in mainline */
+ };
+
+ dmm@4e000000 {
+ compatible = "ti,omap4-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
+ emif1: emif@4c000000 {
+ compatible = "ti,emif-4d";
+ reg = <0x4c000000 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "emif1";
+ ti,no-idle-on-init;
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ emif2: emif@4d000000 {
+ compatible = "ti,emif-4d";
+ reg = <0x4d000000 0x100>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "emif2";
+ ti,no-idle-on-init;
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ aes1_target: target-module@4b501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b501080 0x4>,
+ <0x4b501084 0x4>,
+ <0x4b501088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b501000 0x1000>;
+
+ aes1: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 111>, <&sdma 110>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ aes2_target: target-module@4b701000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b701080 0x4>,
+ <0x4b701084 0x4>,
+ <0x4b701088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b701000 0x1000>;
+
+ aes2: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 114>, <&sdma 113>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ sham_target: target-module@4b100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x4b100100 0x4>,
+ <0x4b100110 0x4>,
+ <0x4b100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap4-sham";
+ reg = <0 0x300>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 119>;
+ dma-names = "rx";
+ };
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ ti,tranxdone-status-mask = <0x80>;
+ clocks = <&sys_clkin_ck>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ status = "disabled";
+ };
+
+ abb_iva: regulator-abb-iva {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_iva";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ ti,tranxdone-status-mask = <0x80000000>;
+ clocks = <&sys_clkin_ck>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ status = "disabled";
+ };
+
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x2000000>;
+
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
+ };
+
+ /*
+ * DSS is only using l3 mapping without l4 as noted in the TRM
+ * "10.1.3 DSS Register Manual" for omap4460.
+ */
+ target-module@58000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000000 4>,
+ <0x58000014 4>;
+ reg-names = "rev", "syss";
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x58000000 0x1000000>;
+
+ dss: dss@0 {
+ compatible = "ti,omap4-dss";
+ reg = <0 0x80>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000000>;
+
+ target-module@1000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x1000 0x4>,
+ <0x1010 0x4>,
+ <0x1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x1000>;
+
+ dispc@0 {
+ compatible = "ti,omap4-dispc";
+ reg = <0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@2000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>,
+ <0x2014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x1000>;
+
+ rfbi: encoder@0 {
+ reg = <0 0x1000>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
+ clock-names = "fck", "ick";
+ };
+ };
+
+ target-module@3000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x3000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x3000 0x1000>;
+
+ venc: encoder@0 {
+ compatible = "ti,omap4-venc";
+ reg = <0 0x1000>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@4000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x1000>;
+
+ dsi1: encoder@0 {
+ compatible = "ti,omap4-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+
+ target-module@5000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5000 0x4>,
+ <0x5010 0x4>,
+ <0x5014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5000 0x1000>;
+
+ dsi2: encoder@0 {
+ compatible = "ti,omap4-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+
+ target-module@6000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x6000 0x4>,
+ <0x6010 0x4>;
+ reg-names = "rev", "sysc";
+ /*
+ * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
+ * but HDMI audio will fail with them.
+ */
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck", "dss_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x2000>;
+
+ hdmi: encoder@0 {
+ compatible = "ti,omap4-hdmi";
+ reg = <0 0x200>,
+ <0x200 0x100>,
+ <0x300 0x100>,
+ <0x400 0x1000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ dmas = <&sdma 76>;
+ dma-names = "audio_tx";
+ };
+ };
+ };
+ };
+ };
+};
+
+#include "omap4-l4.dtsi"
+#include "omap4-l4-abe.dtsi"
+#include "omap44xx-clocks.dtsi"
+
+&prm {
+ prm_tesla: prm@400 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_ivahd: prm@f00 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@1b00 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&prm_clocks {
+ bandgap_fclk: bandgap_fclk@1888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1888>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for OMAP443x SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "omap4.dtsi"
+
+/ {
+ cpus {
+ cpu0: cpu@0 {
+ /* OMAP443x variants OPP50-OPPNT */
+ operating-points = <
+ /* kHz uV */
+ 300000 1025000
+ 600000 1200000
+ 800000 1313000
+ 1008000 1375000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ };
+
+ ocp {
+ bandgap: bandgap@4a002260 {
+ reg = <0x4a002260 0x4
+ 0x4a00232C 0x4>;
+ compatible = "ti,omap4430-bandgap";
+
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ ocp {
+ abb_mpu: regulator-abb-mpu {
+ status = "okay";
+
+ reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>;
+ reg-names = "base-address", "int-address";
+
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0 0 0 0
+ 1200000 0 0 0 0 0
+ 1313000 0 0 0 0 0
+ 1375000 1 0 0 0 0
+ 1389000 1 0 0 0 0
+ >;
+ };
+
+ /* Default unused, just provide register info for record */
+ abb_iva: regulator-abb-iva {
+ reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>;
+ reg-names = "base-address", "int-address";
+ };
+
+ };
+
+};
+
+&cpu_thermal {
+ coefficients = <0 20000>;
+};
+
+/include/ "omap443x-clocks.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for OMAP4460 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include "omap4.dtsi"
+
+/ {
+ cpus {
+ /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
+ cpu0: cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 350000 1025000
+ 700000 1200000
+ 920000 1313000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "debugss";
+ };
+
+ thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ };
+
+ ocp {
+ bandgap: bandgap@4a002260 {
+ reg = <0x4a002260 0x4
+ 0x4a00232C 0x4
+ 0x4a002378 0x18>;
+ compatible = "ti,omap4460-bandgap";
+ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
+
+ #thermal-sensor-cells = <0>;
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ status = "okay";
+
+ reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
+ <0x4A002268 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address";
+
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0 0 0 0
+ 1200000 0 0 0 0 0
+ 1313000 0 0 0x100000 0x40000 0
+ 1375000 1 0 0 0 0
+ 1389000 1 0 0 0 0
+ >;
+ };
+
+ abb_iva: regulator-abb-iva {
+ status = "okay";
+
+ reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
+ <0x4A002268 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address";
+
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 950000 0 0 0 0 0
+ 1140000 0 0 0 0 0
+ 1291000 0 0 0x200000 0 0
+ 1375000 1 0 0 0 0
+ 1376000 1 0 0 0 0
+ >;
+ };
+ };
+
+};
+
+&cpu_thermal {
+ coefficients = <348 (-9301)>;
+};
+
+/* Only some L4 CFG interconnect ranges are different on 4460 */
+&l4_cfg_segment_300000 {
+ ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
+ <0x00040000 0x00340000 0x001000>, /* ap 68 */
+ <0x00020000 0x00320000 0x004000>, /* ap 71 */
+ <0x00024000 0x00324000 0x002000>, /* ap 72 */
+ <0x00026000 0x00326000 0x001000>, /* ap 73 */
+ <0x00027000 0x00327000 0x001000>, /* ap 74 */
+ <0x00028000 0x00328000 0x001000>, /* ap 75 */
+ <0x00029000 0x00329000 0x001000>, /* ap 76 */
+ <0x00030000 0x00330000 0x010000>, /* ap 77 */
+ <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
+ <0x0002c000 0x0032c000 0x004000>, /* ap 91 */
+ <0x00010000 0x00310000 0x008000>, /* ap 92 */
+ <0x00018000 0x00318000 0x004000>, /* ap 93 */
+ <0x0001c000 0x0031c000 0x002000>, /* ap 94 */
+ <0x0001e000 0x0031e000 0x002000>; /* ap 95 */
+};
+
+&l4_cfg_target_0 {
+ ranges = <0x00000000 0x00000000 0x00010000>,
+ <0x00010000 0x00010000 0x00008000>,
+ <0x00018000 0x00018000 0x00004000>,
+ <0x0001c000 0x0001c000 0x00002000>,
+ <0x0001e000 0x0001e000 0x00002000>,
+ <0x00020000 0x00020000 0x00004000>,
+ <0x00024000 0x00024000 0x00002000>,
+ <0x00026000 0x00026000 0x00001000>,
+ <0x00027000 0x00027000 0x00001000>,
+ <0x00028000 0x00028000 0x00001000>,
+ <0x00029000 0x00029000 0x00001000>,
+ <0x0002a000 0x0002a000 0x00002000>,
+ <0x0002c000 0x0002c000 0x00004000>,
+ <0x00030000 0x00030000 0x00010000>;
+};
+
+/include/ "omap446x-clocks.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&prm_clocks {
+ div_ts_ck: div_ts_ck@1888 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1888>;
+ ti,dividers = <8>, <16>, <32>;
+ };
+
+ bandgap_ts_fclk: bandgap_ts_fclk@1888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&div_ts_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1888>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&cm1_clocks {
+ extalt_clkin_ck: extalt_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <59000000>;
+ };
+
+ pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ pad_clks_ck: pad_clks_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0108>;
+ };
+
+ pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ slimbus_clk: slimbus_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x0108>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ };
+
+ virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ tie_low_clock_ck: tie_low_clock_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60motg_ck: xclk60motg_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ dpll_abe_ck: dpll_abe_ck@1e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+ reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+ };
+
+ dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x01f0>;
+ };
+
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ abe_clk: abe_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x0108>;
+ ti,index-power-of-two;
+ };
+
+
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f4>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x012c>;
+ };
+
+ dpll_core_ck: dpll_core_ck@120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+ reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+ };
+
+ dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+ };
+
+ dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0140>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_m2_ck: dpll_core_m2_ck@130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0130>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ ddrphy_ck: ddrphy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x013c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ div_core_ck: div_core_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x0100>;
+ ti,max-div = <2>;
+ };
+
+ div_iva_hs_clk: div_iva_hs_clk@1dc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x01dc>;
+ ti,index-power-of-two;
+ };
+
+ div_mpu_hs_clk: div_mpu_hs_clk@19c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x019c>;
+ ti,index-power-of-two;
+ };
+
+ dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0138>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dll_clk_div_ck: dll_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ ti,max-div = <31>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0134>;
+ };
+
+ dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0134>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
+ };
+
+ dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0144>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+ ti,bit-shift = <23>;
+ reg = <0x01ac>;
+ };
+
+ dpll_iva_ck: dpll_iva_ck@1a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+ reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <931200000>;
+ };
+
+ dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+ };
+
+ dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01b8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m4x2_ck>;
+ assigned-clock-rates = <465600000>;
+ };
+
+ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01bc>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m5x2_ck>;
+ assigned-clock-rates = <266100000>;
+ };
+
+ dpll_mpu_ck: dpll_mpu_ck@160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+ reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+ };
+
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0170>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ per_hs_clk_div_ck: per_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ l3_div_ck: l3_div_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&div_core_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <2>;
+ reg = <0x0100>;
+ };
+
+ l4_div_ck: l4_div_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <2>;
+ reg = <0x0100>;
+ };
+
+ lp_clk_div_ck: lp_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ mpu_periphclk: mpu_periphclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ ocp_abe_iclk: ocp_abe_iclk@528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
+ ti,bit-shift = <24>;
+ reg = <0x0528>;
+ ti,dividers = <2>, <1>;
+ };
+
+ per_abe_24m_fclk: per_abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
+&prm_clocks {
+ sys_clkin_ck: sys_clkin_ck@110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x0110>;
+ ti,index-starts-at-one;
+ };
+
+ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0108>;
+ };
+
+ abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ reg = <0x010c>;
+ };
+
+ dbgclk_mux_ck: dbgclk_mux_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+ reg = <0x0108>;
+ };
+
+ syc_clk_div_ck: syc_clk_div_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x0100>;
+ ti,max-div = <2>;
+ };
+
+ usim_ck: usim_ck@1858 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1858>;
+ ti,dividers = <14>, <18>;
+ };
+
+ usim_fclk: usim_fclk@1858 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&usim_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1858>;
+ };
+
+ trace_clk_div_ck: trace_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
+ };
+};
+
+&prm_clockdomains {
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+};
+
+&cm2_clocks {
+ per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x014c>;
+ };
+
+ dpll_per_ck: dpll_per_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+ reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+ };
+
+ dpll_per_m2_ck: dpll_per_m2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_x2_ck: dpll_per_x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x0150>;
+ };
+
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0154>;
+ };
+
+ dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
+ };
+
+ dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0160>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0164>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_usb_ck: dpll_usb_ck@180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+ reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+ };
+
+ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,clock-div = <1>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01b4>;
+ ti,clock-mult = <1>;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0190>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+ reg = <0x0100>;
+ };
+
+ func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_24mc_fclk: func_24mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ func_48m_fclk: func_48m_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x0108>;
+ ti,dividers = <4>, <8>;
+ };
+
+ func_48mc_fclk: func_48mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_64m_fclk: func_64m_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ reg = <0x0108>;
+ ti,dividers = <2>, <4>;
+ };
+
+ func_96m_fclk: func_96m_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x0108>;
+ ti,dividers = <2>, <4>;
+ };
+
+ init_60m_fclk: init_60m_fclk@104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x0104>;
+ ti,dividers = <1>, <8>;
+ };
+
+ per_abe_nc_fclk: per_abe_nc_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x0108>;
+ ti,max-div = <2>;
+ };
+
+ sha2md5_fck: sha2md5_fck@15c8 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x15c8>;
+ };
+
+ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0640>;
+ };
+};
+
+&cm2_clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+};
+
+&scrm_clocks {
+ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_ck: auxclk0_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+ };
+
+ auxclk0_ck: auxclk0_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0310>;
+ };
+
+ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_ck: auxclk1_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+ };
+
+ auxclk1_ck: auxclk1_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0314>;
+ };
+
+ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_ck: auxclk2_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+ };
+
+ auxclk2_ck: auxclk2_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0318>;
+ };
+
+ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_ck: auxclk3_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+ };
+
+ auxclk3_ck: auxclk3_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x031c>;
+ };
+
+ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_ck: auxclk4_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+ };
+
+ auxclk4_ck: auxclk4_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0320>;
+ };
+
+ auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0324>;
+ };
+
+ auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0324>;
+ };
+
+ auxclk5_src_ck: auxclk5_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
+ };
+
+ auxclk5_ck: auxclk5_ck@324 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk5_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0324>;
+ };
+
+ auxclkreq0_ck: auxclkreq0_ck@210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0210>;
+ };
+
+ auxclkreq1_ck: auxclkreq1_ck@214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0214>;
+ };
+
+ auxclkreq2_ck: auxclkreq2_ck@218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0218>;
+ };
+
+ auxclkreq3_ck: auxclkreq3_ck@21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x021c>;
+ };
+
+ auxclkreq4_ck: auxclkreq4_ck@220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0220>;
+ };
+
+ auxclkreq5_ck: auxclkreq5_ck@224 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0224>;
+ };
+};
+
+&cm1 {
+ mpuss_cm: mpuss_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpuss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ tesla_cm: tesla_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ tesla_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x6c>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm2 {
+ l4_ao_cm: l4_ao_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ l4_ao_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_1_cm: l3_1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3_1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_2_cm: l3_2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3_2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ducati_cm: ducati_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ducati_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dma_cm: l3_dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ l3_dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_emif_cm: l3_emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ l3_emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ d2d_cm: d2d_cm@c00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xc00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xc00 0x100>;
+
+ d2d_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_cfg_cm: l4_cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4_cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_instr_cm: l3_instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3_instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x24>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ivahd_cm: ivahd_cm@f00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xf00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xf00 0x100>;
+
+ ivahd_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ iss_cm: iss_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x100>;
+
+ iss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dss_cm: l3_dss_cm@1100 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1100 0x100>;
+
+ l3_dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_gfx_cm: l3_gfx_cm@1200 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1200 0x100>;
+
+ l3_gfx_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_init_cm: l3_init_cm@1300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1300 0x100>;
+
+ l3_init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_per_cm: l4_per_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x200>;
+
+ l4_per_clkctrl: clock@20 {
+ compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
+ reg = <0x20 0x144>;
+ #clock-cells = <2>;
+ };
+
+ l4_secure_clkctrl: clock@1a0 {
+ compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
+ reg = <0x1a0 0x3c>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&prm {
+ l4_wkup_cm: l4_wkup_cm@1800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1800 0x100>;
+
+ l4_wkup_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emu_sys_cm: emu_sys_cm@1a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1a00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1a00 0x100>;
+
+ emu_sys_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "omap5.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ aliases {
+ display0 = &hdmi0;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ vmain: fixedregulator-vmain {
+ compatible = "regulator-fixed";
+ regulator-name = "vmain";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vsys_cobra: fixedregulator-vsys_cobra {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_cobra";
+ vin-supply = <&vmain>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vdds_1v8_main: fixedregulator-vdds_1v8_main {
+ compatible = "regulator-fixed";
+ regulator-name = "vdds_1v8_main";
+ vin-supply = <&smps7_reg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vmmcsd_fixed: fixedregulator-mmcsd {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ mmc3_pwrseq: sdhci0_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&clk32kgaudio>;
+ clock-names = "ext_clock";
+ };
+
+ vmmcsdio_fixed: fixedregulator-mmcsdio {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsdio_fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */
+ enable-active-high;
+ startup-delay-us = <70000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_pins>;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
+ clocks = <&auxclk1_ck>;
+ clock-names = "main_clk";
+ clock-frequency = <19200000>;
+ #phy-cells = <0>;
+ };
+
+ /* HS USB Host PHY on PORT 3 */
+ hsusb3_phy: hsusb3_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
+ #phy-cells = <0>;
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tpd12s015_pins>;
+
+ /* gpios defined in the board specific dts */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "b";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ sound: sound {
+ compatible = "ti,abe-twl6040";
+ ti,model = "omap5-uevm";
+
+ ti,jack-detection;
+ ti,mclk-freq = <19200000>;
+
+ ti,mcpdm = <&mcpdm>;
+
+ ti,twl6040 = <&twl6040>;
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "HSMIC", "Headset Mic",
+ "Headset Mic", "Headset Mic Bias",
+ "AFML", "Line In",
+ "AFMR", "Line In";
+ };
+};
+
+&gpio8 {
+ /* TI trees use GPIO instead of msecure, see also muxing */
+ p234 {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "gpio8_234/msecure";
+ };
+};
+
+&omap5_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &usbhost_pins
+ &led_gpio_pins
+ >;
+
+ twl6040_pins: pinmux_twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
+ >;
+ };
+
+ mcpdm_pins: pinmux_mcpdm_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
+ OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
+ OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
+ OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
+ OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
+ >;
+ };
+
+ mcbsp1_pins: pinmux_mcbsp1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
+ OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
+ OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
+ OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
+ >;
+ };
+
+ mcbsp2_pins: pinmux_mcbsp2_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
+ OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
+ OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
+ OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+ OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+ >;
+ };
+
+ mcspi2_pins: pinmux_mcspi2_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
+ OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
+ OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
+ OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
+ >;
+ };
+
+ mcspi3_pins: pinmux_mcspi3_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
+ OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
+ OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
+ OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
+ >;
+ };
+
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
+ OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
+ OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
+ OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
+ OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
+ OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
+ >;
+ };
+
+ wlan_pins: pinmux_wlan_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
+ >;
+ };
+
+ /* TI trees use GPIO mode; msecure mode does not work reliably? */
+ palmas_msecure_pins: palmas_msecure_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
+ >;
+ };
+
+ usbhost_pins: pinmux_usbhost_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
+ OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
+
+ OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
+ OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
+
+ OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
+ OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
+ >;
+ };
+
+ led_gpio_pins: pinmux_led_gpio_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
+ OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
+ OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
+ OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
+ OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
+ >;
+ };
+
+ uart5_pins: pinmux_uart5_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
+ OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
+ OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
+ OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
+ >;
+ };
+
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
+ OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
+ >;
+ };
+};
+
+&omap5_pmx_wkup {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &usbhost_wkup_pins
+ >;
+
+ palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
+ pinctrl-single,pins = <
+ /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+ OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
+ >;
+ };
+
+ usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
+ >;
+ };
+
+ wlcore_irq_pin: pinmux_wlcore_irq_pin {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
+ >;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&ldo9_reg>;
+ bus-width = <4>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ vmmc-supply = <&vmmcsdio_fixed>;
+ mmc-pwrseq = <&mmc3_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ cap-power-off-card;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ &omap5_pmx_core 0x16a>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlcore_irq_pin>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
+ ref-clock-frequency = <26000000>;
+ };
+};
+
+&mmc4 {
+ status = "disabled";
+};
+
+&mmc5 {
+ status = "disabled";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ clock-frequency = <400000>;
+
+ palmas: palmas@48 {
+ compatible = "ti,palmas";
+ /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
+ reg = <0x48>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,system-power-controller;
+ ti,mux-pad1 = <0xa1>;
+ ti,mux-pad2 = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
+
+ palmas_gpio: gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ extcon_usb3: palmas_usb {
+ compatible = "ti,palmas-usb-vid";
+ ti,enable-vbus-detection;
+ ti,enable-id-detection;
+ ti,wakeup;
+ id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ clk32kgaudio: palmas_clk32k@1 {
+ compatible = "ti,palmas-clk32kgaudio";
+ #clock-cells = <0>;
+ };
+
+ rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 IRQ_TYPE_NONE>;
+ ti,backup-battery-chargeable;
+ ti,backup-battery-charge-high-current;
+ };
+
+ gpadc: gpadc {
+ compatible = "ti,palmas-gpadc";
+ interrupts = <18 0
+ 16 0
+ 17 0>;
+ #io-channel-cells = <1>;
+ ti,channel0-current-microamp = <5>;
+ ti,channel3-current-microamp = <10>;
+ };
+
+ palmas_pmic {
+ compatible = "ti,palmas-pmic";
+ interrupt-parent = <&palmas>;
+ interrupts = <14 IRQ_TYPE_NONE>;
+ interrupt-names = "short-irq";
+
+ ti,ldo6-vibrator;
+
+ smps123-in-supply = <&vsys_cobra>;
+ smps45-in-supply = <&vsys_cobra>;
+ smps6-in-supply = <&vsys_cobra>;
+ smps7-in-supply = <&vsys_cobra>;
+ smps8-in-supply = <&vsys_cobra>;
+ smps9-in-supply = <&vsys_cobra>;
+ smps10_out2-in-supply = <&vsys_cobra>;
+ smps10_out1-in-supply = <&vsys_cobra>;
+ ldo1-in-supply = <&vsys_cobra>;
+ ldo2-in-supply = <&vsys_cobra>;
+ ldo3-in-supply = <&vdds_1v8_main>;
+ ldo4-in-supply = <&vdds_1v8_main>;
+ ldo5-in-supply = <&vsys_cobra>;
+ ldo6-in-supply = <&vdds_1v8_main>;
+ ldo7-in-supply = <&vsys_cobra>;
+ ldo8-in-supply = <&vsys_cobra>;
+ ldo9-in-supply = <&vmmcsd_fixed>;
+ ldoln-in-supply = <&vsys_cobra>;
+ ldousb-in-supply = <&vsys_cobra>;
+
+ regulators {
+ smps123_reg: smps123 {
+ /* VDD_OPP_MPU */
+ regulator-name = "smps123";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ /* VDD_OPP_MM */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ /* VDD_DDR3 - over VDD_SMPS6 */
+ regulator-name = "smps6";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps7_reg: smps7 {
+ /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps8_reg: smps8 {
+ /* VDD_OPP_CORE */
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps9_reg: smps9 {
+ /* VDDA_2v1_AUD over VDD_2v1 */
+ regulator-name = "smps9";
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ ti,smps-range = <0x80>;
+ };
+
+ smps10_out2_reg: smps10_out2 {
+ /* VBUS_5V_OTG */
+ regulator-name = "smps10_out2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps10_out1_reg: smps10_out1 {
+ /* VBUS_5V_OTG */
+ regulator-name = "smps10_out1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ ldo1_reg: ldo1 {
+ /* VDDAPHY_CAM: vdda_csiport */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo2_reg: ldo2 {
+ /* VCC_2V8_DISP: Does not go anywhere */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ /* Unused */
+ status = "disabled";
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDAPHY_MDM: vdda_lli */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ /* Only if Modem is used */
+ status = "disabled";
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDAPHY_DISP: vdda_dsiport/hdmi */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PHY: usb/sata/hdmi.. */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo6_reg: ldo6 {
+ /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7_reg: ldo7 {
+ /* VDD_VPP: vpp1 */
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ /* Only for efuse reprograming! */
+ status = "disabled";
+ };
+
+ ldo8_reg: ldo8 {
+ /* VDD_3v0: Does not go anywhere */
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ /* Unused */
+ status = "disabled";
+ };
+
+ ldo9_reg: ldo9 {
+ /* VCC_DV_SDIO: vdds_sdcard */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ regen3_reg: regen3 {
+ /* REGEN3 controls LDO9 supply to card */
+ regulator-name = "regen3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ palmas_power_button: palmas_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&palmas>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+ };
+
+ twl6040: twl@4b {
+ compatible = "ti,twl6040";
+ #clock-cells = <0>;
+ reg = <0x4b>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&twl6040_pins>;
+
+ /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
+
+ /* audpwron gpio defined in the board specific dts */
+
+ vio-supply = <&smps7_reg>;
+ v2v1-supply = <&smps9_reg>;
+ enable-active-high;
+
+ clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
+ clock-names = "clk32k", "mclk";
+ };
+};
+
+&mcpdm_module {
+ /* Module on the SoC needs external clock from the PMIC */
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcpdm_pins>;
+ status = "okay";
+};
+
+&mcpdm {
+ clocks = <&twl6040>;
+ clock-names = "pdmclk";
+};
+
+&mcbsp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp1_pins>;
+ status = "okay";
+};
+
+&mcbsp2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp2_pins>;
+ status = "okay";
+};
+
+&usbhshost {
+ port2-mode = "ehci-hsic";
+ port3-mode = "ehci-hsic";
+};
+
+&usbhsehci {
+ phys = <0 &hsusb2_phy &hsusb3_phy>;
+};
+
+&usb3 {
+ extcon = <&extcon_usb3>;
+ vbus-supply = <&smps10_out1_reg>;
+};
+
+&dwc3 {
+ extcon = <&extcon_usb3>;
+ dr_mode = "otg";
+};
+
+&mcspi1 {
+
+};
+
+&mcspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi2_pins>;
+};
+
+&mcspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi3_pins>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <&omap5_pmx_core 0x19c>;
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pins>;
+};
+
+&cpu0 {
+ cpu0-supply = <&smps123_reg>;
+};
+
+&dss {
+ status = "ok";
+};
+
+&hdmi {
+ status = "ok";
+
+ /* vdda-supply populated in board specific dts file */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_hdmi_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
--- /dev/null
+&l4_abe { /* 0x40100000 */
+ compatible = "ti,omap5-l4-abe", "simple-bus";
+ reg = <0x40100000 0x400>,
+ <0x40100400 0x400>;
+ reg-names = "la", "ap";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
+ <0x49000000 0x49000000 0x100000>;
+ segment@0 { /* 0x40100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges =
+ /* CPU to L4 ABE mapping */
+ <0x00000000 0x00000000 0x000400>, /* ap 0 */
+ <0x00000400 0x00000400 0x000400>, /* ap 1 */
+ <0x00022000 0x00022000 0x001000>, /* ap 2 */
+ <0x00023000 0x00023000 0x001000>, /* ap 3 */
+ <0x00024000 0x00024000 0x001000>, /* ap 4 */
+ <0x00025000 0x00025000 0x001000>, /* ap 5 */
+ <0x00026000 0x00026000 0x001000>, /* ap 6 */
+ <0x00027000 0x00027000 0x001000>, /* ap 7 */
+ <0x00028000 0x00028000 0x001000>, /* ap 8 */
+ <0x00029000 0x00029000 0x001000>, /* ap 9 */
+ <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
+ <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
+ <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
+ <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
+ <0x00030000 0x00030000 0x001000>, /* ap 14 */
+ <0x00031000 0x00031000 0x001000>, /* ap 15 */
+ <0x00032000 0x00032000 0x001000>, /* ap 16 */
+ <0x00033000 0x00033000 0x001000>, /* ap 17 */
+ <0x00038000 0x00038000 0x001000>, /* ap 18 */
+ <0x00039000 0x00039000 0x001000>, /* ap 19 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
+ <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
+ <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
+ <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
+ <0x00080000 0x00080000 0x010000>, /* ap 26 */
+ <0x00080000 0x00080000 0x001000>, /* ap 27 */
+ <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
+ <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
+ <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
+ <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
+ <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
+ <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
+
+ /* L3 to L4 ABE mapping */
+ <0x49000000 0x49000000 0x000400>, /* ap 0 */
+ <0x49000400 0x49000400 0x000400>, /* ap 1 */
+ <0x49022000 0x49022000 0x001000>, /* ap 2 */
+ <0x49023000 0x49023000 0x001000>, /* ap 3 */
+ <0x49024000 0x49024000 0x001000>, /* ap 4 */
+ <0x49025000 0x49025000 0x001000>, /* ap 5 */
+ <0x49026000 0x49026000 0x001000>, /* ap 6 */
+ <0x49027000 0x49027000 0x001000>, /* ap 7 */
+ <0x49028000 0x49028000 0x001000>, /* ap 8 */
+ <0x49029000 0x49029000 0x001000>, /* ap 9 */
+ <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
+ <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
+ <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
+ <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
+ <0x49030000 0x49030000 0x001000>, /* ap 14 */
+ <0x49031000 0x49031000 0x001000>, /* ap 15 */
+ <0x49032000 0x49032000 0x001000>, /* ap 16 */
+ <0x49033000 0x49033000 0x001000>, /* ap 17 */
+ <0x49038000 0x49038000 0x001000>, /* ap 18 */
+ <0x49039000 0x49039000 0x001000>, /* ap 19 */
+ <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
+ <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
+ <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
+ <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
+ <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
+ <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
+ <0x49080000 0x49080000 0x010000>, /* ap 26 */
+ <0x49080000 0x49080000 0x001000>, /* ap 27 */
+ <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
+ <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
+ <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
+ <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
+ <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
+ <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
+
+ target-module@22000 { /* 0x40122000, ap 2 02.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2208c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>,
+ <0x49022000 0x49022000 0x1000>;
+
+ mcbsp1: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49022000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 33>,
+ <&sdma 34>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@24000 { /* 0x40124000, ap 4 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2408c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>,
+ <0x49024000 0x49024000 0x1000>;
+
+ mcbsp2: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49024000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 17>,
+ <&sdma 18>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@26000 { /* 0x40126000, ap 6 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2608c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>,
+ <0x49026000 0x49026000 0x1000>;
+
+ mcbsp3: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49026000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 19>,
+ <&sdma 20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@28000 { /* 0x40128000, ap 8 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>,
+ <0x49028000 0x49028000 0x1000>;
+ };
+
+ target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>,
+ <0x4902a000 0x4902a000 0x1000>;
+ };
+
+ target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2e000 0x4>,
+ <0x2e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2e000 0x1000>,
+ <0x4902e000 0x4902e000 0x1000>;
+
+ dmic: dmic@0 {
+ compatible = "ti,omap4-dmic";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x4902e000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 67>;
+ dma-names = "up_link";
+ status = "disabled";
+ };
+ };
+
+ target-module@30000 { /* 0x40130000, ap 14 0e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>,
+ <0x49030000 0x49030000 0x1000>;
+ };
+
+ mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>,
+ <0x49032000 0x49032000 0x1000>;
+
+ /* Must be only enabled for boards with pdmclk wired */
+ status = "disabled";
+
+ mcpdm: mcpdm@0 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 65>,
+ <&sdma 66>;
+ dma-names = "up_link", "dn_link";
+ };
+ };
+
+ target-module@38000 { /* 0x40138000, ap 18 12.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x38000 0x4>,
+ <0x38010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x1000>,
+ <0x49038000 0x49038000 0x1000>;
+
+ timer5: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x49038000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3a000 0x4>,
+ <0x3a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3a000 0x1000>,
+ <0x4903a000 0x4903a000 0x1000>;
+
+ timer6: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x4903a000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3c000 0x4>,
+ <0x3c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x1000>,
+ <0x4903c000 0x4903c000 0x1000>;
+
+ timer7: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x4903c000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>,
+ <0x4903e000 0x4903e000 0x1000>;
+
+ timer8: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x4903e000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@80000 { /* 0x40180000, ap 26 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>,
+ <0x49080000 0x49080000 0x10000>;
+ };
+
+ target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x10000>,
+ <0x490a0000 0x490a0000 0x10000>;
+ };
+
+ target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc0000 0x10000>,
+ <0x490c0000 0x490c0000 0x10000>;
+ };
+
+ target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xf1000 0x4>,
+ <0xf1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf1000 0x1000>,
+ <0x490f1000 0x490f1000 0x1000>;
+ };
+ };
+};
--- /dev/null
+&l4_cfg { /* 0x4a000000 */
+ compatible = "ti,omap5-l4-cfg", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
+ <0x00080000 0x4a080000 0x080000>, /* segment 1 */
+ <0x00100000 0x4a100000 0x080000>, /* segment 2 */
+ <0x00180000 0x4a180000 0x080000>, /* segment 3 */
+ <0x00200000 0x4a200000 0x080000>, /* segment 4 */
+ <0x00280000 0x4a280000 0x080000>, /* segment 5 */
+ <0x00300000 0x4a300000 0x080000>; /* segment 6 */
+
+ segment@0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00002000 0x00002000 0x001000>, /* ap 3 */
+ <0x00003000 0x00003000 0x001000>, /* ap 4 */
+ <0x00004000 0x00004000 0x001000>, /* ap 5 */
+ <0x00005000 0x00005000 0x001000>, /* ap 6 */
+ <0x00056000 0x00056000 0x001000>, /* ap 7 */
+ <0x00057000 0x00057000 0x001000>, /* ap 8 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
+ <0x00058000 0x00058000 0x001000>, /* ap 10 */
+ <0x00062000 0x00062000 0x001000>, /* ap 11 */
+ <0x00063000 0x00063000 0x001000>, /* ap 12 */
+ <0x00008000 0x00008000 0x002000>, /* ap 21 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
+ <0x00066000 0x00066000 0x001000>, /* ap 23 */
+ <0x00067000 0x00067000 0x001000>, /* ap 24 */
+ <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
+ <0x00060000 0x00060000 0x001000>, /* ap 70 */
+ <0x00064000 0x00064000 0x001000>, /* ap 71 */
+ <0x00065000 0x00065000 0x001000>, /* ap 72 */
+ <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
+ <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
+ <0x00070000 0x00070000 0x004000>, /* ap 79 */
+ <0x00074000 0x00074000 0x001000>, /* ap 80 */
+ <0x00075000 0x00075000 0x001000>, /* ap 81 */
+ <0x00076000 0x00076000 0x001000>, /* ap 82 */
+ <0x00020000 0x00020000 0x020000>, /* ap 109 */
+ <0x00040000 0x00040000 0x001000>, /* ap 110 */
+ <0x00059000 0x00059000 0x001000>; /* ap 111 */
+
+ target-module@2000 { /* 0x4a002000, ap 3 44.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ scm_core: scm@0 {
+ compatible = "ti,omap5-scm-core", "simple-bus";
+ reg = <0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x800>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ scm_padconf_core: scm@800 {
+ compatible = "ti,omap5-scm-padconf-core",
+ "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x800>;
+
+ omap5_pmx_core: pinmux@40 {
+ compatible = "ti,omap5-padconf",
+ "pinctrl-single";
+ reg = <0x40 0x01b6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
+ omap5_padconf_global: omap5_padconf_global@5a0 {
+ compatible = "syscon",
+ "simple-bus";
+ reg = <0x5a0 0xec>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5a0 0xec>;
+
+ pbias_regulator: pbias_regulator@60 {
+ compatible = "ti,pbias-omap5", "ti,pbias-omap";
+ reg = <0x60 0x4>;
+ syscon = <&omap5_padconf_global>;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name = "pbias_mmc_omap5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+ };
+ };
+
+ target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x4000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ cm_core_aon: cm_core_aon@0 {
+ compatible = "ti,omap5-cm-core-aon",
+ "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+
+ cm_core_aon_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_aon_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x8000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x2000>;
+
+ cm_core: cm_core@0 {
+ compatible = "ti,omap5-cm-core", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ cm_core_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@20000 { /* 0x4a020000, ap 109 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_otg_ss";
+ reg = <0x20000 0x4>,
+ <0x20010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x20000>;
+
+ usb3: omap_dwc3@0 {
+ compatible = "ti,dwc3";
+ reg = <0x0 0x10000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges = <0 0 0x20000>;
+ dwc3: dwc3@10000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ phys = <&usb2_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "peripheral";
+ };
+ };
+ };
+
+ target-module@56000 { /* 0x4a056000, ap 7 02.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x56000 0x4>,
+ <0x5602c 0x4>,
+ <0x56028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
+ clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x56000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <127>;
+ };
+ };
+
+ target-module@58000 { /* 0x4a058000, ap 10 06.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00058000 0x00001000>,
+ <0x00001000 0x00059000 0x00001000>,
+ <0x00002000 0x0005a000 0x00001000>,
+ <0x00003000 0x0005b000 0x00001000>;
+ };
+
+ target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5e000 0x2000>;
+ };
+
+ target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "usb_tll_hs";
+ reg = <0x62000 0x4>,
+ <0x62010 0x4>,
+ <0x62014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x62000 0x1000>;
+
+ usbhstll: usbhstll@0 {
+ compatible = "ti,usbhs-tll";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_host_hs";
+ reg = <0x64000 0x4>,
+ <0x64010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x64000 0x1000>;
+
+ usbhshost: usbhshost@0 {
+ compatible = "ti,usbhs-host";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ clocks = <&l3init_60m_fclk>,
+ <&xclk60mhsp1_ck>,
+ <&xclk60mhsp2_ck>;
+ clock-names = "refclk_60m_int",
+ "refclk_60m_ext_p1",
+ "refclk_60m_ext_p2";
+
+ usbhsohci: ohci@800 {
+ compatible = "ti,ohci-omap3";
+ reg = <0x800 0x400>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ remote-wakeup-connected;
+ };
+
+ usbhsehci: ehci@c00 {
+ compatible = "ti,ehci-omap";
+ reg = <0xc00 0x400>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x66000 0x4>,
+ <0x66010 0x4>,
+ <0x66014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
+ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp 1>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x1000>;
+
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
+ };
+
+ target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x70000 0x4000>;
+ };
+
+ target-module@75000 { /* 0x4a075000, ap 81 32.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x75000 0x1000>;
+ };
+ };
+
+ segment@80000 { /* 0x4a080000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
+ <0x0005a000 0x000da000 0x001000>, /* ap 14 */
+ <0x0005b000 0x000db000 0x001000>, /* ap 15 */
+ <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
+ <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
+ <0x0005e000 0x000de000 0x001000>, /* ap 18 */
+ <0x00060000 0x000e0000 0x001000>, /* ap 19 */
+ <0x00061000 0x000e1000 0x001000>, /* ap 20 */
+ <0x00074000 0x000f4000 0x001000>, /* ap 25 */
+ <0x00075000 0x000f5000 0x001000>, /* ap 26 */
+ <0x00076000 0x000f6000 0x001000>, /* ap 27 */
+ <0x00077000 0x000f7000 0x001000>, /* ap 28 */
+ <0x00036000 0x000b6000 0x001000>, /* ap 65 */
+ <0x00037000 0x000b7000 0x001000>, /* ap 66 */
+ <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
+ <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
+ <0x00000000 0x00080000 0x004000>, /* ap 83 */
+ <0x00004000 0x00084000 0x001000>, /* ap 84 */
+ <0x00005000 0x00085000 0x001000>, /* ap 85 */
+ <0x00006000 0x00086000 0x001000>, /* ap 86 */
+ <0x00007000 0x00087000 0x001000>, /* ap 87 */
+ <0x00008000 0x00088000 0x001000>, /* ap 88 */
+ <0x00010000 0x00090000 0x004000>, /* ap 89 */
+ <0x00014000 0x00094000 0x001000>, /* ap 90 */
+ <0x00015000 0x00095000 0x001000>, /* ap 91 */
+ <0x00016000 0x00096000 0x001000>, /* ap 92 */
+ <0x00017000 0x00097000 0x001000>, /* ap 93 */
+ <0x00018000 0x00098000 0x001000>, /* ap 94 */
+ <0x00020000 0x000a0000 0x004000>, /* ap 95 */
+ <0x00024000 0x000a4000 0x001000>, /* ap 96 */
+ <0x00025000 0x000a5000 0x001000>, /* ap 97 */
+ <0x00026000 0x000a6000 0x001000>, /* ap 98 */
+ <0x00027000 0x000a7000 0x001000>, /* ap 99 */
+ <0x00028000 0x000a8000 0x001000>; /* ap 100 */
+
+ target-module@0 { /* 0x4a080000, ap 83 28.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x0 0x4>,
+ <0x10 0x4>,
+ <0x14 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x00004000>,
+ <0x00004000 0x00004000 0x00001000>,
+ <0x00005000 0x00005000 0x00001000>,
+ <0x00006000 0x00006000 0x00001000>,
+ <0x00007000 0x00007000 0x00001000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x20>;
+ };
+
+ usb2_phy: usb2phy@4000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4000 0x7c>;
+ syscon-phy-power = <&scm_conf 0x300>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
+ clock-names = "wkupclk", "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb3_phy: usb3phy@4400 {
+ compatible = "ti,omap-usb3";
+ reg = <0x4400 0x80>,
+ <0x4800 0x64>,
+ <0x4c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ syscon-phy-power = <&scm_conf 0x370>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&sys_clkin>,
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
+ clock-names = "wkupclk",
+ "sysclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ target-module@10000 { /* 0x4a090000, ap 89 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x10000 0x4>,
+ <0x10010 0x4>,
+ <0x10014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x00004000>,
+ <0x00004000 0x00014000 0x00001000>,
+ <0x00005000 0x00015000 0x00001000>,
+ <0x00006000 0x00016000 0x00001000>,
+ <0x00007000 0x00017000 0x00001000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x20>;
+ };
+
+ sata_phy: phy@6000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x6000 0x80>, /* phy_rx */
+ <0x6400 0x64>, /* phy_tx */
+ <0x6800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ syscon-phy-power = <&scm_conf 0x374>;
+ clocks = <&sys_clkin>,
+ <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
+ clock-names = "sysclk", "refclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00020000 0x00004000>,
+ <0x00004000 0x00024000 0x00001000>,
+ <0x00005000 0x00025000 0x00001000>,
+ <0x00006000 0x00026000 0x00001000>,
+ <0x00007000 0x00027000 0x00001000>;
+ };
+
+ target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+ };
+
+ target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4d000 0x1000>;
+ };
+
+ target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+ };
+
+ target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+ };
+
+ target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+ };
+
+ target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+ };
+
+ target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x74000 0x4>,
+ <0x74010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
+ clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x74000 0x1000>;
+
+ mailbox: mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ mbox_ipu: mbox_ipu {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ mbox_dsp: mbox_dsp {
+ ti,mbox-tx = <3 0 0>;
+ ti,mbox-rx = <2 0 0>;
+ };
+ };
+ };
+
+ target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x76000 0x4>,
+ <0x76010 0x4>,
+ <0x76014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
+ clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x76000 0x1000>;
+
+ hwspinlock: spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+ };
+
+ segment@100000 { /* 0x4a100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
+ <0x00003000 0x00103000 0x001000>, /* ap 60 */
+ <0x00008000 0x00108000 0x001000>, /* ap 61 */
+ <0x00009000 0x00109000 0x001000>, /* ap 62 */
+ <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
+ <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
+ <0x00040000 0x00140000 0x010000>, /* ap 101 */
+ <0x00050000 0x00150000 0x001000>; /* ap 102 */
+
+ target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@8000 { /* 0x4a108000, ap 61 26.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+ };
+
+ target-module@40000 { /* 0x4a140000, ap 101 16.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x10000>;
+ };
+ };
+
+ segment@180000 { /* 0x4a180000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@200000 { /* 0x4a200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
+ <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
+ <0x00006000 0x00206000 0x001000>, /* ap 33 */
+ <0x00007000 0x00207000 0x001000>, /* ap 34 */
+ <0x00004000 0x00204000 0x001000>, /* ap 35 */
+ <0x00005000 0x00205000 0x001000>, /* ap 36 */
+ <0x00012000 0x00212000 0x001000>, /* ap 37 */
+ <0x00013000 0x00213000 0x001000>, /* ap 38 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
+ <0x00010000 0x00210000 0x001000>, /* ap 41 */
+ <0x00011000 0x00211000 0x001000>, /* ap 42 */
+ <0x00016000 0x00216000 0x001000>, /* ap 43 */
+ <0x00017000 0x00217000 0x001000>, /* ap 44 */
+ <0x00014000 0x00214000 0x001000>, /* ap 45 */
+ <0x00015000 0x00215000 0x001000>, /* ap 46 */
+ <0x00018000 0x00218000 0x001000>, /* ap 47 */
+ <0x00019000 0x00219000 0x001000>, /* ap 48 */
+ <0x00020000 0x00220000 0x001000>, /* ap 49 */
+ <0x00021000 0x00221000 0x001000>, /* ap 50 */
+ <0x00026000 0x00226000 0x001000>, /* ap 51 */
+ <0x00027000 0x00227000 0x001000>, /* ap 52 */
+ <0x00028000 0x00228000 0x001000>, /* ap 53 */
+ <0x00029000 0x00229000 0x001000>, /* ap 54 */
+ <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
+ <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
+ <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
+ <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
+ <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
+ <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
+ <0x00024000 0x00224000 0x001000>, /* ap 75 */
+ <0x00025000 0x00225000 0x001000>, /* ap 76 */
+ <0x00002000 0x00202000 0x001000>, /* ap 103 */
+ <0x00003000 0x00203000 0x001000>, /* ap 104 */
+ <0x00008000 0x00208000 0x001000>, /* ap 105 */
+ <0x00009000 0x00209000 0x001000>, /* ap 106 */
+ <0x00022000 0x00222000 0x001000>, /* ap 107 */
+ <0x00023000 0x00223000 0x001000>; /* ap 108 */
+
+ target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@4000 { /* 0x4a204000, ap 35 46.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x1000>;
+ };
+
+ target-module@8000 { /* 0x4a208000, ap 105 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+ };
+
+ target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+ };
+
+ target-module@10000 { /* 0x4a210000, ap 41 56.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x1000>;
+ };
+
+ target-module@12000 { /* 0x4a212000, ap 37 52.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x12000 0x1000>;
+ };
+
+ target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module@16000 { /* 0x4a216000, ap 43 42.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x16000 0x1000>;
+ };
+
+ target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x1000>;
+ };
+
+ target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1a000 0x1000>;
+ };
+
+ target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1c000 0x1000>;
+ };
+
+ target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e000 0x1000>;
+ };
+
+ target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+ };
+
+ target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+ };
+
+ target-module@24000 { /* 0x4a224000, ap 75 48.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+ };
+
+ target-module@26000 { /* 0x4a226000, ap 51 24.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+ };
+
+ target-module@28000 { /* 0x4a228000, ap 53 38.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>;
+ };
+
+ target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+ };
+ };
+
+ segment@280000 { /* 0x4a280000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@300000 { /* 0x4a300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&l4_per { /* 0x48000000 */
+ compatible = "ti,omap5-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
+ <0x00200000 0x48200000 0x200000>; /* segment 1 */
+
+ segment@0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x000400>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00020000 0x00020000 0x001000>, /* ap 3 */
+ <0x00021000 0x00021000 0x001000>, /* ap 4 */
+ <0x00032000 0x00032000 0x001000>, /* ap 5 */
+ <0x00033000 0x00033000 0x001000>, /* ap 6 */
+ <0x00034000 0x00034000 0x001000>, /* ap 7 */
+ <0x00035000 0x00035000 0x001000>, /* ap 8 */
+ <0x00036000 0x00036000 0x001000>, /* ap 9 */
+ <0x00037000 0x00037000 0x001000>, /* ap 10 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
+ <0x00055000 0x00055000 0x001000>, /* ap 13 */
+ <0x00056000 0x00056000 0x001000>, /* ap 14 */
+ <0x00057000 0x00057000 0x001000>, /* ap 15 */
+ <0x00058000 0x00058000 0x001000>, /* ap 16 */
+ <0x00059000 0x00059000 0x001000>, /* ap 17 */
+ <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
+ <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
+ <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
+ <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
+ <0x00060000 0x00060000 0x001000>, /* ap 23 */
+ <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
+ <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
+ <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
+ <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
+ <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
+ <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
+ <0x00070000 0x00070000 0x001000>, /* ap 30 */
+ <0x00071000 0x00071000 0x001000>, /* ap 31 */
+ <0x00072000 0x00072000 0x001000>, /* ap 32 */
+ <0x00073000 0x00073000 0x001000>, /* ap 33 */
+ <0x00061000 0x00061000 0x001000>, /* ap 34 */
+ <0x00053000 0x00053000 0x001000>, /* ap 35 */
+ <0x00054000 0x00054000 0x001000>, /* ap 36 */
+ <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
+ <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
+ <0x00078000 0x00078000 0x001000>, /* ap 39 */
+ <0x00079000 0x00079000 0x001000>, /* ap 40 */
+ <0x00086000 0x00086000 0x001000>, /* ap 41 */
+ <0x00087000 0x00087000 0x001000>, /* ap 42 */
+ <0x00088000 0x00088000 0x001000>, /* ap 43 */
+ <0x00089000 0x00089000 0x001000>, /* ap 44 */
+ <0x00051000 0x00051000 0x001000>, /* ap 45 */
+ <0x00052000 0x00052000 0x001000>, /* ap 46 */
+ <0x00098000 0x00098000 0x001000>, /* ap 47 */
+ <0x00099000 0x00099000 0x001000>, /* ap 48 */
+ <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
+ <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
+ <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
+ <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
+ <0x00068000 0x00068000 0x001000>, /* ap 53 */
+ <0x00069000 0x00069000 0x001000>, /* ap 54 */
+ <0x00090000 0x00090000 0x002000>, /* ap 55 */
+ <0x00092000 0x00092000 0x001000>, /* ap 56 */
+ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
+ <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
+ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
+ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
+ <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
+ <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
+ <0x00066000 0x00066000 0x001000>, /* ap 63 */
+ <0x00067000 0x00067000 0x001000>, /* ap 64 */
+ <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
+ <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
+ <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
+ <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
+ <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
+ <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
+ <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
+ <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
+ <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
+ <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
+ <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
+ <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
+ <0x00001400 0x00001400 0x000400>, /* ap 77 */
+ <0x00001800 0x00001800 0x000400>, /* ap 78 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
+ <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
+ <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
+ <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
+ <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
+ <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
+
+ target-module@20000 { /* 0x48020000, ap 3 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x20050 0x4>,
+ <0x20054 0x4>,
+ <0x20058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ uart3: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@32000 { /* 0x48032000, ap 5 3e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@34000 { /* 0x48034000, ap 7 46.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x34000 0x4>,
+ <0x34010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x1000>;
+
+ timer3: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@36000 { /* 0x48036000, ap 9 4e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x36000 0x4>,
+ <0x36010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+
+ timer4: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ timer9: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@51000 { /* 0x48051000, ap 45 2e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x51000 0x4>,
+ <0x51010 0x4>,
+ <0x51114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x51000 0x1000>;
+
+ gpio7: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@53000 { /* 0x48053000, ap 35 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53000 0x4>,
+ <0x53010 0x4>,
+ <0x53114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53000 0x1000>;
+
+ gpio8: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@55000 { /* 0x48055000, ap 13 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55000 0x4>,
+ <0x55010 0x4>,
+ <0x55114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@57000 { /* 0x48057000, ap 15 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x57000 0x4>,
+ <0x57010 0x4>,
+ <0x57114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x57000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@59000 { /* 0x48059000, ap 17 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x59000 0x4>,
+ <0x59010 0x4>,
+ <0x59114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+
+ gpio4: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5b000 0x4>,
+ <0x5b010 0x4>,
+ <0x5b114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ gpio5: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5d000 0x4>,
+ <0x5d010 0x4>,
+ <0x5d114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+
+ gpio6: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@60000 { /* 0x48060000, ap 23 24.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x60000 0x8>,
+ <0x60010 0x8>,
+ <0x60090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+
+ i2c3: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@66000 { /* 0x48066000, ap 63 4c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x66050 0x4>,
+ <0x66054 0x4>,
+ <0x66058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x1000>;
+
+ uart5: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@68000 { /* 0x48068000, ap 53 54.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x68050 0x4>,
+ <0x68054 0x4>,
+ <0x68058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x68000 0x1000>;
+
+ uart6: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6a050 0x4>,
+ <0x6a054 0x4>,
+ <0x6a058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6a000 0x1000>;
+
+ uart1: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6c050 0x4>,
+ <0x6c054 0x4>,
+ <0x6c058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6c000 0x1000>;
+
+ uart2: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6e050 0x4>,
+ <0x6e054 0x4>,
+ <0x6e058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6e000 0x1000>;
+
+ uart4: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@70000 { /* 0x48070000, ap 30 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x70000 0x8>,
+ <0x70010 0x8>,
+ <0x70090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x70000 0x1000>;
+
+ i2c1: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@72000 { /* 0x48072000, ap 32 1c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x72000 0x8>,
+ <0x72010 0x8>,
+ <0x72090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x72000 0x1000>;
+
+ i2c2: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@78000 { /* 0x48078000, ap 39 12.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x78000 0x1000>;
+ };
+
+ target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x7a000 0x8>,
+ <0x7a010 0x8>,
+ <0x7a090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7a000 0x1000>;
+
+ i2c4: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x7c000 0x8>,
+ <0x7c010 0x8>,
+ <0x7c090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7c000 0x1000>;
+
+ i2c5: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@86000 { /* 0x48086000, ap 41 5e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x86000 0x4>,
+ <0x86010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x86000 0x1000>;
+
+ timer10: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@88000 { /* 0x48088000, ap 43 66.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x88000 0x4>,
+ <0x88010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x88000 0x1000>;
+
+ timer11: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x91fe0 0x4>,
+ <0x91fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x90000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@98000 { /* 0x48098000, ap 47 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x98000 0x4>,
+ <0x98010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x98000 0x1000>;
+
+ mcspi1: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+ };
+
+ target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9a000 0x4>,
+ <0x9a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9a000 0x1000>;
+
+ mcspi2: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+ };
+
+ target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9c000 0x4>,
+ <0x9c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+
+ mmc1: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+ };
+
+ target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+ };
+
+ target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x000a4000 0x00001000>,
+ <0x00001000 0x000a5000 0x00001000>;
+ };
+
+ target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x4000>;
+ };
+
+ target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xad000 0x4>,
+ <0xad010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xad000 0x1000>;
+
+ mmc3: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb2000 0x1000>;
+ };
+
+ target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb4000 0x4>,
+ <0xb4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb4000 0x1000>;
+
+ mmc2: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb8000 0x4>,
+ <0xb8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb8000 0x1000>;
+
+ mcspi3: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xba000 0x4>,
+ <0xba010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xba000 0x1000>;
+
+ mcspi4: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd1000 0x4>,
+ <0xd1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd1000 0x1000>;
+
+ mmc4: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd5000 0x4>,
+ <0xd5010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd5000 0x1000>;
+
+ mmc5: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 59>, <&sdma 60>;
+ dma-names = "tx", "rx";
+ };
+ };
+ };
+
+ segment@200000 { /* 0x48200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&l4_wkup { /* 0x4ae00000 */
+ compatible = "ti,omap5-l4-wkup", "simple-bus";
+ reg = <0x4ae00000 0x800>,
+ <0x4ae00800 0x800>,
+ <0x4ae01000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
+ <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
+ <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
+
+ segment@0 { /* 0x4ae00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00006000 0x00006000 0x002000>, /* ap 3 */
+ <0x00008000 0x00008000 0x001000>, /* ap 4 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
+ <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
+ <0x00004000 0x00004000 0x001000>, /* ap 17 */
+ <0x00005000 0x00005000 0x001000>, /* ap 18 */
+ <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
+ <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
+
+ target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "counter_32k";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x0 0x40>;
+ };
+ };
+
+ target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x6000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x2000>;
+
+ prm: prm@0 {
+ compatible = "ti,omap5-prm", "simple-bus";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xa000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+
+ scrm: scrm@0 {
+ compatible = "ti,omap5-scrm";
+ reg = <0x0 0x1000>;
+
+ scrm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scrm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xc000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ omap5_pmx_wkup: pinmux@840 {
+ compatible = "ti,omap5-padconf",
+ "pinctrl-single";
+ reg = <0x840 0x003c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
+ omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 {
+ compatible = "ti,omap5-scm-wkup-pad-conf",
+ "simple-bus";
+ reg = <0xda0 0x60>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x60>;
+
+ scm_wkup_pad_conf: scm_conf@0 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x0 0x60>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x60>;
+
+ scm_wkup_pad_conf_clocks: clocks@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+ };
+ };
+
+ segment@10000 { /* 0x4ae10000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
+ <0x00001000 0x00011000 0x001000>, /* ap 6 */
+ <0x00004000 0x00014000 0x001000>, /* ap 7 */
+ <0x00005000 0x00015000 0x001000>, /* ap 8 */
+ <0x00008000 0x00018000 0x001000>, /* ap 9 */
+ <0x00009000 0x00019000 0x001000>, /* ap 10 */
+ <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
+ <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
+
+ target-module@0 { /* 0x4ae10000, ap 5 10.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x0 0x4>,
+ <0x10 0x4>,
+ <0x114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
+ <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ gpio1: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ ti,gpio-always-on;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ wdt2: wdt@0 {
+ compatible = "ti,omap5-wdt", "ti,omap3-wdt";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer1";
+ reg = <0x8000 0x4>,
+ <0x8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-alwon;
+ };
+ };
+
+ target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xc000 0x4>,
+ <0xc010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ keypad: keypad@0 {
+ compatible = "ti,omap4-keypad";
+ reg = <0x0 0x400>;
+ };
+ };
+ };
+
+ segment@20000 { /* 0x4ae20000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
+ <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
+ <0x00000000 0x00020000 0x001000>, /* ap 21 */
+ <0x00001000 0x00021000 0x001000>, /* ap 22 */
+ <0x00002000 0x00022000 0x001000>, /* ap 23 */
+ <0x00003000 0x00023000 0x001000>, /* ap 24 */
+ <0x00007000 0x00027000 0x000400>, /* ap 25 */
+ <0x00008000 0x00028000 0x000800>, /* ap 26 */
+ <0x00009000 0x00029000 0x000100>, /* ap 27 */
+ <0x00008800 0x00028800 0x000200>, /* ap 28 */
+ <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
+
+ target-module@0 { /* 0x4ae20000, ap 21 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+ };
+
+ target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00006000 0x00001000>,
+ <0x00001000 0x00007000 0x00000400>,
+ <0x00002000 0x00008000 0x00000800>,
+ <0x00002800 0x00008800 0x00000200>,
+ <0x00002a00 0x00008a00 0x00000100>,
+ <0x00003000 0x00009000 0x00000100>;
+ };
+ };
+};
* Based on "dra7.dtsi"
*/
+#ifdef CONFIG_DRA7XX
/{
chosen {
tick-timer = &timer2;
&i2c1 {
u-boot,dm-spl;
};
+
+#else /* OMAP54XX */
+&l4_cfg {
+ segment@0 {
+ /* SCM Core */
+ target-module@2000 {
+ compatible = "simple-bus";
+ };
+
+ /* USB HS */
+ target-module@64000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+&l4_per {
+ segment@0 {
+ /* UART3 */
+ target-module@20000 {
+ compatible = "simple-bus";
+ };
+
+ /* I2C1 */
+ target-module@70000 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC1 */
+ target-module@9c000 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC2 */
+ target-module@b4000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap5-board-common.dtsi"
+
+/ {
+ model = "TI OMAP5 uEVM board";
+ compatible = "ti,omap5-uevm", "ti,omap5";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
+ };
+
+ aliases {
+ ethernet = ðernet;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1 {
+ label = "omap5:blue:usr1";
+ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ evm_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&evm_keys_pins>;
+
+ #address-cells = <7>;
+ #size-cells = <0>;
+
+ btn1 {
+ label = "BTN1";
+ linux,code = <169>;
+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
+ wakeup-source;
+ autorepeat;
+ debounce-interval = <50>;
+ };
+ };
+
+ evm_leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "omap5:red:led";
+ gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "omap5:green:led";
+ gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "omap5:blue:led";
+ gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "omap5:green:led1";
+ gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led5 {
+ label = "omap5:green:led2";
+ gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+
+ led6 {
+ label = "omap5:green:led3";
+ gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led7 {
+ label = "omap5:green:led4";
+ gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+
+ led8 {
+ label = "omap5:green:led5";
+ gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+};
+
+&hdmi {
+ vdda-supply = <&ldo4_reg>;
+};
+
+&i2c1 {
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+
+ clock-frequency = <400000>;
+
+ gpio9: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+
+ cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */
+};
+
+&omap5_pmx_core {
+ evm_keys_pins: pinmux_evm_keys_gpio_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
+ >;
+ };
+
+ i2c5_pins: pinmux_i2c5_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */
+ OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */
+ >;
+ };
+};
+
+&tpd12s015 {
+ gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
+ <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
+ <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
+};
+
+&twl6040 {
+ ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
+};
+
+&twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
+ >;
+};
+
+&usbhsehci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@2 {
+ compatible = "usb424,3503";
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ethernet: usbether@3 {
+ compatible = "usb424,9730";
+ reg = <3>;
+ };
+};
+
+&wlcore {
+ compatible = "ti,wl1837";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on "omap4.dtsi"
+ */
+
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap5.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ compatible = "ti,omap5";
+ interrupt-parent = <&wakeupgen>;
+ chosen { };
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ i2c4 = &i2c5;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1500000 1250000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1500000 1250000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ #include "omap5-gpu-thermal.dtsi"
+ #include "omap5-core-thermal.dtsi"
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ /* PPI secure/nonsecure IRQ */
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0 0x48211000 0 0x1000>,
+ <0 0x48212000 0 0x2000>,
+ <0 0x48214000 0 0x2000>,
+ <0 0x48216000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0 0x48281000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap4-mpu";
+ ti,hwmods = "mpu";
+ sram = <&ocmcram>;
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP3 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap5-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xc0000000>;
+ dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
+ ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+ reg = <0 0x44000000 0 0x2000>,
+ <0 0x44800000 0 0x3000>,
+ <0 0x45000000 0 0x4000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ l4_wkup: interconnect@4ae00000 {
+ };
+
+ l4_cfg: interconnect@4a000000 {
+ };
+
+ l4_per: interconnect@48000000 {
+ };
+
+ l4_abe: interconnect@40100000 {
+ };
+
+ ocmcram: sram@40300000 {
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x20000>; /* 128k */
+ };
+
+ gpmc: gpmc@50000000 {
+ compatible = "ti,omap4430-gpmc";
+ reg = <0x50000000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 4>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <4>;
+ ti,hwmods = "gpmc";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
+ };
+
+ dmm@4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
+ emif1: emif@4c000000 {
+ compatible = "ti,emif-4d5";
+ ti,hwmods = "emif1";
+ ti,no-idle-on-init;
+ phy-type = <2>; /* DDR PHY type: Intelli PHY */
+ reg = <0x4c000000 0x400>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ emif2: emif@4d000000 {
+ compatible = "ti,emif-4d5";
+ ti,hwmods = "emif2";
+ ti,no-idle-on-init;
+ phy-type = <2>; /* DDR PHY type: Intelli PHY */
+ reg = <0x4d000000 0x400>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ bandgap: bandgap@4a0021e0 {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ compatible = "ti,omap5430-bandgap";
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ /* OCP2SCP3 */
+ sata: sata@4a141100 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
+ ti,hwmods = "sata";
+ ports-implemented = <0x1>;
+ };
+
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x2000000>;
+
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
+ };
+
+ target-module@58000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000000 4>,
+ <0x58000014 4>;
+ reg-names = "rev", "syss";
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x58000000 0x1000000>;
+
+ dss: dss@0 {
+ compatible = "ti,omap5-dss";
+ reg = <0 0x80>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000000>;
+
+ target-module@1000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x1000 0x4>,
+ <0x1010 0x4>,
+ <0x1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x1000>;
+
+ dispc@0 {
+ compatible = "ti,omap5-dispc";
+ reg = <0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@2000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>,
+ <0x2014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x1000>;
+
+ rfbi: encoder@0 {
+ compatible = "ti,omap5-rfbi";
+ reg = <0 0x100>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
+ clock-names = "fck", "ick";
+ };
+ };
+
+ target-module@5000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5000 0x4>,
+ <0x5010 0x4>,
+ <0x5014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5000 0x1000>;
+
+ dsi1: encoder@0 {
+ compatible = "ti,omap5-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x40>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@9000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x9000 0x4>,
+ <0x9010 0x4>,
+ <0x9014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x9000 0x1000>;
+
+ dsi2: encoder@0 {
+ compatible = "ti,omap5-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x40>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@40000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck", "dss_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40000 0x40000>;
+
+ hdmi: encoder@0 {
+ compatible = "ti,omap5-hdmi";
+ reg = <0 0x200>,
+ <0x200 0x80>,
+ <0x300 0x80>,
+ <0x20000 0x19000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ dmas = <&sdma 76>;
+ dma-names = "audio_tx";
+ };
+ };
+ };
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
+ <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address", "ldo-address";
+ ti,tranxdone-status-mask = <0x80>;
+ /* LDOVBBMPU_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMPU_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1060000 0 0x0 0 0x02000000 0x01F00000
+ 1250000 0 0x4 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_mm: regulator-abb-mm {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mm";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
+ <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address", "ldo-address";
+ ti,tranxdone-status-mask = <0x80000000>;
+ /* LDOVBBMM_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMM_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0x0 0 0x02000000 0x01F00000
+ 1120000 0 0x4 0 0x02000000 0x01F00000
+ >;
+ };
+ };
+};
+
+&cpu_thermal {
+ polling-delay = <500>; /* milliseconds */
+ coefficients = <65 (-1791)>;
+};
+
+#include "omap5-l4.dtsi"
+#include "omap54xx-clocks.dtsi"
+
+&gpu_thermal {
+ coefficients = <117 (-2992)>;
+};
+
+&core_thermal {
+ coefficients = <0 2000>;
+};
+
+#include "omap5-l4-abe.dtsi"
+#include "omap54xx-clocks.dtsi"
+
+&prm {
+ prm_dsp: prm@400 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_iva: prm@1200 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1200 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@1c00 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1c00 0x100>;
+ #reset-cells = <1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&cm_core_aon_clocks {
+ pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ pad_clks_ck: pad_clks_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0108>;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ slimbus_clk: slimbus_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x0108>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ };
+
+ virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ dpll_abe_ck: dpll_abe_ck@1e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+ };
+
+ dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ };
+
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ };
+
+ abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ abe_clk: abe_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x0108>;
+ ti,index-power-of-two;
+ };
+
+ abe_iclk: abe_iclk@528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x0528>;
+ ti,dividers = <2>, <1>;
+ };
+
+ abe_lp_clk_div: abe_lp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x01f4>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_byp_mux: dpll_core_byp_mux@12c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x012c>;
+ };
+
+ dpll_core_ck: dpll_core_ck@120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
+ reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+ };
+
+ dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+ };
+
+ dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ c2c_fclk: c2c_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h21x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ c2c_iclk: c2c_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&c2c_fclk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0138>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x013c>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0140>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0144>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m2_ck: dpll_core_m2_ck@130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ reg = <0x0130>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0134>;
+ ti,index-starts-at-one;
+ };
+
+ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x01ac>;
+ };
+
+ dpll_iva_ck: dpll_iva_ck@1a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
+ reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <1165000000>;
+ };
+
+ dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+ };
+
+ dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x01b8>;
+ ti,index-starts-at-one;
+ assigned-clocks = <&dpll_iva_h11x2_ck>;
+ assigned-clock-rates = <465920000>;
+ };
+
+ dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x01bc>;
+ ti,index-starts-at-one;
+ assigned-clocks = <&dpll_iva_h12x2_ck>;
+ assigned-clock-rates = <388300000>;
+ };
+
+ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_mpu_ck: dpll_mpu_ck@160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap5-mpu-dpll-clock";
+ clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+ };
+
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ reg = <0x0170>;
+ ti,index-starts-at-one;
+ };
+
+ per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ l3_iclk_div: l3_iclk_div@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,max-div = <2>;
+ ti,bit-shift = <4>;
+ reg = <0x100>;
+ clocks = <&dpll_core_h12x2_ck>;
+ ti,index-power-of-two;
+ };
+
+ gpu_l3_iclk: gpu_l3_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l4_root_clk_div: l4_root_clk_div@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,max-div = <2>;
+ ti,bit-shift = <8>;
+ reg = <0x100>;
+ clocks = <&l3_iclk_div>;
+ ti,index-power-of-two;
+ };
+
+ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x0560>;
+ };
+
+ aess_fclk: aess_fclk@528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ ti,max-div = <2>;
+ reg = <0x0528>;
+ };
+
+ mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x0540>;
+ };
+
+ mcasp_gfclk: mcasp_gfclk@540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x0540>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+&prm_clocks {
+ sys_clkin: sys_clkin@110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x0110>;
+ ti,index-starts-at-one;
+ };
+
+ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x0108>;
+ };
+
+ abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x010c>;
+ };
+
+ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dss_syc_gfclk_div: dss_syc_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+ reg = <0x0108>;
+ };
+
+ l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+};
+
+&cm_core_clocks {
+
+ dpll_per_byp_mux: dpll_per_byp_mux@14c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x014c>;
+ };
+
+ dpll_per_ck: dpll_per_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
+ reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+ };
+
+ dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ };
+
+ dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0164>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m2_ck: dpll_per_m2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_unipro1_ck: dpll_unipro1_ck@200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+ };
+
+ dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro1_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro1_ck>;
+ ti,max-div = <127>;
+ reg = <0x0210>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
+ };
+
+ dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro2_ck>;
+ ti,max-div = <127>;
+ reg = <0x01d0>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x018c>;
+ };
+
+ dpll_usb_ck: dpll_usb_ck@180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
+ reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+ };
+
+ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ reg = <0x0190>;
+ ti,index-starts-at-one;
+ };
+
+ func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l3init_60m_fclk: l3init_60m_fclk@104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x0104>;
+ ti,dividers = <1>, <8>;
+ };
+
+ iss_ctrlclk: iss_ctrlclk@1320 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_96m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x1320>;
+ };
+
+ lli_txphy_clk: lli_txphy_clk@f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x0f20>;
+ };
+
+ lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_m2_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x0f20>;
+ };
+
+ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0640>;
+ };
+
+ fdif_fclk: fdif_fclk@1328 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <2>;
+ reg = <0x1328>;
+ };
+
+ gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1520>;
+ };
+
+ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x1520>;
+ };
+
+ hsi_fclk: hsi_fclk@1638 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <2>;
+ reg = <0x1638>;
+ };
+};
+
+&cm_core_clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+};
+
+&scrm_clocks {
+ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_ck: auxclk0_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+ };
+
+ auxclk0_ck: auxclk0_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0310>;
+ };
+
+ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_ck: auxclk1_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+ };
+
+ auxclk1_ck: auxclk1_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0314>;
+ };
+
+ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_ck: auxclk2_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+ };
+
+ auxclk2_ck: auxclk2_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0318>;
+ };
+
+ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_ck: auxclk3_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+ };
+
+ auxclk3_ck: auxclk3_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x031c>;
+ };
+
+ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_ck: auxclk4_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+ };
+
+ auxclk4_ck: auxclk4_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0320>;
+ };
+
+ auxclkreq0_ck: auxclkreq0_ck@210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0210>;
+ };
+
+ auxclkreq1_ck: auxclkreq1_ck@214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0214>;
+ };
+
+ auxclkreq2_ck: auxclkreq2_ck@218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0218>;
+ };
+
+ auxclkreq3_ck: auxclkreq3_ck@21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x021c>;
+ };
+};
+
+&cm_core_aon {
+ mpu_cm: mpu_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dsp_cm: dsp_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ dsp_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x64>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm_core {
+ l3main1_cm: l3main1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3main1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3main2_cm: l3main2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3main2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ipu_cm: ipu_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ipu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dma_cm: dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emif_cm: emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4cfg_cm: l4cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3instr_cm: l3instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4per_cm: l4per_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x200>;
+
+ l4per_clkctrl: clock@20 {
+ compatible = "ti,clkctrl-l4per", "ti,clkctrl";
+ reg = <0x20 0x15c>;
+ #clock-cells = <2>;
+ };
+
+ l4sec_clkctrl: clock@1a0 {
+ compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
+ reg = <0x1a0 0x3c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dss_cm: dss_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x100>;
+
+ dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ gpu_cm: gpu_cm@1500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1500 0x100>;
+
+ gpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3init_cm: l3init_cm@1600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1600 0x100>;
+
+ l3init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&prm {
+ wkupaon_cm: wkupaon_cm@1900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1900 0x100>;
+
+ wkupaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&scm_wkup_pad_conf_clocks {
+ fref_xtal_ck: fref_xtal_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin>;
+ ti,bit-shift = <28>;
+ reg = <0x14>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+&twl {
+ compatible = "ti,twl6030";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <11>;
+ };
+
+ vaux1: regulator-vaux1 {
+ compatible = "ti,twl6030-vaux1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vaux2: regulator-vaux2 {
+ compatible = "ti,twl6030-vaux2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vaux3: regulator-vaux3 {
+ compatible = "ti,twl6030-vaux3";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vmmc: regulator-vmmc {
+ compatible = "ti,twl6030-vmmc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vpp: regulator-vpp {
+ compatible = "ti,twl6030-vpp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ vusim: regulator-vusim {
+ compatible = "ti,twl6030-vusim";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vdac: regulator-vdac {
+ compatible = "ti,twl6030-vdac";
+ };
+
+ vana: regulator-vana {
+ compatible = "ti,twl6030-vana";
+ };
+
+ vcxio: regulator-vcxio {
+ compatible = "ti,twl6030-vcxio";
+ regulator-always-on;
+ };
+
+ vusb: regulator-vusb {
+ compatible = "ti,twl6030-vusb";
+ };
+
+ v1v8: regulator-v1v8 {
+ compatible = "ti,twl6030-v1v8";
+ regulator-always-on;
+ };
+
+ v2v1: regulator-v2v1 {
+ compatible = "ti,twl6030-v2v1";
+ regulator-always-on;
+ };
+
+ twl_usb_comparator: usb-comparator {
+ compatible = "ti,twl6030-usb";
+ interrupts = <4>, <10>;
+ };
+
+ twl_pwm: pwm {
+ /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */
+ compatible = "ti,twl6030-pwm";
+ #pwm-cells = <2>;
+ };
+
+ twl_pwmled: pwmled {
+ /* provides one PWM (id 0 for Charging indicator LED) */
+ compatible = "ti,twl6030-pwmled";
+ #pwm-cells = <2>;
+ };
+
+ gpadc {
+ compatible = "ti,twl6030-gpadc";
+ interrupts = <3>;
+ #io-channel-cells = <1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&twl {
+ /*
+ * On most OMAP4 platforms, the twl6030 IRQ line is connected
+ * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is
+ * connected to the fref_clk0_out.sys_drm_msecure line.
+ * Therefore, configure the defaults for the SYS_NIRQ1 and
+ * fref_clk0_out.sys_drm_msecure pins here.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &twl6030_pins
+ &twl6030_wkup_pins
+ >;
+};
+
+&omap4_pmx_wkup {
+ twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
+ >;
+ };
+};
+
+&omap4_pmx_core {
+ twl6030_pins: pinmux_twl6030_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
+ >;
+ };
+};
struct mmc_config cfg;
};
+#define DAVINCI_MAX_BLOCKS (32)
+struct davinci_mmc_plat {
+ struct davinci_mmc_regs *reg_base; /* Register base address */
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
#endif /* _SDMMC_DEFS_H */
select MISC
select OF_CONTROL
select SPI
- select VIDCONSOLE_AS_LCD if DM_VIDEO
imply CMD_DM
imply CRC32_VERIFY
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
- remoteproc1 = &rproc_1;
- remoteproc2 = &rproc_2;
+ remoteproc0 = &rproc_1;
+ remoteproc1 = &rproc_2;
rtc0 = &rtc_0;
rtc1 = &rtc_1;
spi0 = "/spi@0";
hub {
compatible = "usb-hub";
usb,device-class = <9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
hub-emul {
compatible = "sandbox,usb-hub";
#address-cells = <1>;
};
};
+
+ usbstor@1 {
+ reg = <1>;
+ };
+ usbstor@3 {
+ reg = <3>;
+ };
};
};
-setenv stdout serial,vga
+setenv stdout serial,vidconsole
echo "check U-Boot" ;
setenv offset 0x400
if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
return 0;
}
+int ipu_displays_init(void)
+{
+ return board_video_skip();
+}
+
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
.platdata = &serial_pdata,
};
+static const struct davinci_mmc_plat mmc_platdata = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .cfg = {
+ .f_min = 200000,
+ .f_max = 25000000,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .host_caps = MMC_MODE_4BIT,
+ .b_max = DAVINCI_MAX_BLOCKS,
+ .name = "da830-mmc",
+ },
+};
U_BOOT_DEVICE(omapl138_mmc) = {
.name = "davinci_mmc",
+ .platdata = &mmc_platdata,
};
void spl_board_init(void)
}
break;
case OMAP_TAG_UART:
- if (!t->u.uart.enabled_uarts)
+ if (t->u.uart.enabled_uarts)
serial_was_console_enabled = 1;
break;
case OMAP_TAG_SERIAL_CONSOLE:
F: arch/arm/dts/imx6q-tbs2910.dts
F: board/tbs/tbs2910/
F: configs/tbs2910_defconfig
+F: doc/board/tbs/
F: include/configs/tbs2910.h
.slaves = 2,
.slave_data = slave_data,
.ale_entries = 1024,
- .bd_ram_ofs = 0x2000,
.mac_control = 0x20,
.active_slave = 0,
.mdio_base = 0x4a101000,
#define board_is_am571x_idk() board_ti_is("AM571IDK")
#define board_is_bbai() board_ti_is("BBONE-AI")
+#define board_is_ti_idk() board_is_am574x_idk() || \
+ board_is_am572x_idk() || \
+ board_is_am571x_idk()
+
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
-/* GPIO 7_11 */
-#define GPIO_DDR_VTT_EN 203
+#define GPIO_DDR_VTT_EN GPIO_TO_PIN(7, 11)
/* Touch screen controller to identify the LCD */
#define OSD_TS_FT_BUS_ADDRESS 0
struct udevice *dev;
/* Only valid for IDKs */
- if (board_is_x15() || board_is_am572x_evm() || board_is_bbai())
+ if (!board_is_ti_idk())
return;
/* Only AM571x IDK has gpio control detect.. so check that */
}
#if defined(CONFIG_TI_SECURE_DEVICE)
- /* Make HW RNG reserved for secure world use */
- ret = fdt_disable_node(blob, "/interconnect@100000/trng@4e10000");
+ /* Make Crypto HW reserved for secure world use */
+ ret = fdt_disable_node(blob, "/interconnect@100000/crypto@4E00000");
if (ret)
- printf("%s: disabling TRGN failed %d\n", __func__, ret);
+ printf("%s: disabling SA2UL failed %d\n", __func__, ret);
#endif
return 0;
if (name)
env_set("board_name", name);
- else if (ep->name)
+ else if (strlen(ep->name) != 0)
env_set("board_name", ep->name);
else
env_set("board_name", unknown);
- if (ep->version)
+ if (strlen(ep->version) != 0)
env_set("board_rev", ep->version);
else
env_set("board_rev", unknown);
- if (ep->serial)
+ if (strlen(ep->serial) != 0)
env_set("board_serial", ep->serial);
else
env_set("board_serial", unknown);
if (name)
env_set("board_name", name);
- else if (ep->name)
+ else if (strlen(ep->name) != 0)
env_set("board_name", ep->name);
else
env_set("board_name", unknown);
- if (ep->version)
+ if (strlen(ep->version) != 0)
env_set("board_rev", ep->version);
else
env_set("board_rev", unknown);
- if (ep->software_revision)
+ if (strlen(ep->software_revision) != 0)
env_set("board_software_revision", ep->software_revision);
else
env_set("board_software_revision", unknown);
- if (ep->serial)
+ if (strlen(ep->serial) != 0)
env_set("board_serial", ep->serial);
else
env_set("board_serial", unknown);
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
+#include <serial.h>
#include <tca642x.h>
#include <usb.h>
#include <linux/delay.h>
return 0;
}
-int board_eth_init(bd_t *bis)
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
return 0;
}
+#endif /* CONFIG_SPL_OS_BOOT */
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
-static void enable_host_clocks(void)
+int board_eth_init(bd_t *bis)
{
- int auxclk;
- int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
- OPTFCLKEN_HSIC480M_P3_CLK |
- OPTFCLKEN_HSIC60M_P2_CLK |
- OPTFCLKEN_HSIC480M_P2_CLK |
- OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
- /* Enable port 2 and 3 clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
- /* Enable port 2 and 3 usb host ports tll clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
- (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
-#ifdef CONFIG_USB_XHCI_OMAP
- /* Enable the USB OTG Super speed clocks */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
- (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
-#endif
-
- auxclk = readl((*prcm)->scrm_auxclk1);
- /* Request auxilary clock */
- auxclk |= AUXCLK_ENABLE_MASK;
- writel(auxclk, (*prcm)->scrm_auxclk1);
+ return 0;
}
-#endif
/**
* @brief misc_init_r - Configure EVM board specific configurations
}
#endif
-#ifdef CONFIG_USB_EHCI_HCD
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
- .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- int ret;
-
- enable_host_clocks();
-
- ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
- if (ret < 0) {
- puts("Failed to initialize ehci\n");
- return ret;
- }
-
- return 0;
-}
-
-int ehci_hcd_stop(void)
-{
- return omap_ehci_hcd_stop();
-}
-
-void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
-{
- /* The LAN9730 needs to be reset after the port power has been set. */
- if (port == 3) {
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
- udelay(10);
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
- }
-}
-#endif
-
#ifdef CONFIG_USB_XHCI_OMAP
/**
* @brief board_usb_init - Configure EVM board specific configurations
ret = palmas_enable_ss_ldo();
#endif
- enable_host_clocks();
-
return 0;
}
#endif
#include <init.h>
#include <log.h>
#include <net.h>
+#include <serial.h>
#include <asm/mach-types.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include "panda_mux_data.h"
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
#define PANDA_ULPI_PHY_TYPE_GPIO 182
#define PANDA_BOARD_ID_1_GPIO 101
#define PANDA_ES_BOARD_ID_1_GPIO 48
return 0;
}
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
int board_eth_init(bd_t *bis)
{
return 0;
#endif
#endif
-#ifdef CONFIG_USB_EHCI_HCD
-
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- int ret;
- unsigned int utmi_clk;
-
- /* Now we can enable our port clocks */
- utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
- utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
- setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
-
- ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-#endif
-
/*
* get_board_rev() - get board revision
*/
#include <init.h>
#include <net.h>
#include <twl6030.h>
+#include <serial.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#endif
#endif
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
/*
* get_board_rev() - get board revision
*/
static int do_log_level(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- if (argc > 1)
- gd->default_log_level = simple_strtol(argv[1], NULL, 10);
- else
+ if (argc > 1) {
+ long log_level = simple_strtol(argv[1], NULL, 10);
+
+ if (log_level < 0 || log_level > _LOG_MAX_LEVEL) {
+ printf("Only log levels <= %d are supported\n",
+ _LOG_MAX_LEVEL);
+ return CMD_RET_FAILURE;
+ }
+ gd->default_log_level = log_level;
+ } else {
printf("Default log level: %d\n", gd->default_log_level);
+ }
return 0;
}
env_set("netmask", tmp);
}
+#ifdef CONFIG_CMD_BOOTP
if (net_hostname[0])
env_set("hostname", net_hostname);
+#endif
+#ifdef CONFIG_CMD_BOOTP
if (net_root_path[0])
env_set("rootpath", net_root_path);
+#endif
if (net_ip.s_addr) {
ip_to_string(net_ip, tmp);
env_set("dnsip2", tmp);
}
#endif
+#ifdef CONFIG_CMD_BOOTP
if (net_nis_domain[0])
env_set("domain", net_nis_domain);
+#endif
#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET)
if (net_ntp_time_offset) {
discarded if not needed. Logging supports various categories and
levels of severity.
-config SPL_LOG
- bool "Enable logging support in SPL"
- depends on LOG
- help
- This enables support for logging of status and debug messages. These
- can be displayed on the console, recorded in a memory buffer, or
- discarded if not needed. Logging supports various categories and
- levels of severity.
-
-config TPL_LOG
- bool "Enable logging support in TPL"
- depends on LOG
- help
- This enables support for logging of status and debug messages. These
- can be displayed on the console, recorded in a memory buffer, or
- discarded if not needed. Logging supports various categories and
- levels of severity.
+if LOG
config LOG_MAX_LEVEL
int "Maximum log level to record"
- depends on LOG
- default 5
+ default 6
+ range 0 9
help
This selects the maximum log level that will be recorded. Any value
higher than this will be ignored. If possible log statements below
8 - debug content
9 - debug hardware I/O
-config SPL_LOG_MAX_LEVEL
- int "Maximum log level to record in SPL"
- depends on SPL_LOG
- default 3
+config LOG_DEFAULT_LEVEL
+ int "Default logging level to display"
+ default LOG_MAX_LEVEL
+ range 0 LOG_MAX_LEVEL
help
- This selects the maximum log level that will be recorded. Any value
- higher than this will be ignored. If possible log statements below
- this level will be discarded at build time. Levels:
+ This is the default logging level set when U-Boot starts. It can
+ be adjusted later using the 'log level' command. Note that setting
+ this to a value above LOG_MAX_LEVEL will be ineffective, since the
+ higher levels are not compiled in to U-Boot.
0 - emergency
1 - alert
8 - debug content
9 - debug hardware I/O
-config TPL_LOG_MAX_LEVEL
- int "Maximum log level to record in TPL"
- depends on TPL_LOG
+config LOG_CONSOLE
+ bool "Allow log output to the console"
+ default y
+ help
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
+config LOG_SYSLOG
+ bool "Log output to syslog server"
+ depends on NET
+ help
+ Enables a log driver which broadcasts log records via UDP port 514
+ to syslog servers.
+
+config SPL_LOG
+ bool "Enable logging support in SPL"
+ depends on LOG
+ help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+if SPL_LOG
+
+config SPL_LOG_MAX_LEVEL
+ int "Maximum log level to record in SPL"
+ depends on SPL_LOG
default 3
+ range 0 9
help
This selects the maximum log level that will be recorded. Any value
higher than this will be ignored. If possible log statements below
8 - debug content
9 - debug hardware I/O
-config LOG_DEFAULT_LEVEL
- int "Default logging level to display"
- default 6
+config SPL_LOG_CONSOLE
+ bool "Allow log output to the console in SPL"
+ default y
help
- This is the default logging level set when U-Boot starts. It can
- be adjusted later using the 'log level' command. Note that setting
- this to a value above LOG_MAX_LEVEL will be ineffective, since the
- higher levels are not compiled in to U-Boot.
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
+endif
+
+config TPL_LOG
+ bool "Enable logging support in TPL"
+ depends on LOG
+ help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+if TPL_LOG
+
+config TPL_LOG_MAX_LEVEL
+ int "Maximum log level to record in TPL"
+ depends on TPL_LOG
+ default 3
+ range 0 9
+ help
+ This selects the maximum log level that will be recorded. Any value
+ higher than this will be ignored. If possible log statements below
+ this level will be discarded at build time. Levels:
0 - emergency
1 - alert
8 - debug content
9 - debug hardware I/O
-config LOG_CONSOLE
- bool "Allow log output to the console"
- depends on LOG
- default y
- help
- Enables a log driver which writes log records to the console.
- Generally the console is the serial port or LCD display. Only the
- log message is shown - other details like level, category, file and
- line number are omitted.
-
-config SPL_LOG_CONSOLE
- bool "Allow log output to the console in SPL"
- depends on SPL_LOG
- default y
- help
- Enables a log driver which writes log records to the console.
- Generally the console is the serial port or LCD display. Only the
- log message is shown - other details like level, category, file and
- line number are omitted.
-
config TPL_LOG_CONSOLE
bool "Allow log output to the console in TPL"
- depends on TPL_LOG
default y
help
Enables a log driver which writes log records to the console.
log message is shown - other details like level, category, file and
line number are omitted.
-config LOG_SYSLOG
- bool "Log output to syslog server"
- depends on LOG && NET
- help
- Enables a log driver which broadcasts log records via UDP port 514
- to syslog servers.
-
-config LOG_TEST
- bool "Provide a test for logging"
- depends on LOG && UNIT_TEST
- default y if SANDBOX
- help
- This enables a 'log test' command to test logging. It is normally
- executed from a pytest and simply outputs logging information
- in various different ways to test that the logging system works
- correctly with various settings.
+endif
config LOG_ERROR_RETURN
bool "Log all functions which return an error"
- depends on LOG
help
When an error is returned in U-Boot it is sometimes difficult to
figure out the root cause. For example, reading from SPI flash may
You can add log_ret() to all functions which return an error code.
+config LOG_TEST
+ bool "Provide a test for logging"
+ depends on UNIT_TEST
+ default y if SANDBOX
+ help
+ This enables a 'log test' command to test logging. It is normally
+ executed from a pytest and simply outputs logging information
+ in various different ways to test that the logging system works
+ correctly with various settings.
+
+endif
+
endmenu
config SUPPORT_RAW_INITRD
dev = stdio_get_by_name(name);
#ifdef CONFIG_VIDCONSOLE_AS_LCD
- if (!dev && !strcmp(name, "lcd"))
+ if (!dev && !strcmp(name, CONFIG_VIDCONSOLE_AS_LCD))
dev = stdio_get_by_name("vidconsole");
#endif
stdio_print_current_devices();
#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
#ifdef CONFIG_VIDCONSOLE_AS_LCD
- if (strstr(stdoutname, "lcd"))
- printf("Warning: Please change 'lcd' to 'vidconsole' in stdout/stderr environment vars\n");
+ if (strstr(stdoutname, CONFIG_VIDCONSOLE_AS_LCD))
+ printf("Warning: Please change '%s' to 'vidconsole' in stdout/stderr environment vars\n",
+ CONFIG_VIDCONSOLE_AS_LCD);
#endif
#ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#include <u-boot/crc.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
#include <u-boot/md5.h>
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
}
#endif
+#if defined(CONFIG_SHA384)
+static int hash_init_sha384(struct hash_algo *algo, void **ctxp)
+{
+ sha512_context *ctx = malloc(sizeof(sha512_context));
+ sha384_starts(ctx);
+ *ctxp = ctx;
+ return 0;
+}
+
+static int hash_update_sha384(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size, int is_last)
+{
+ sha384_update((sha512_context *)ctx, buf, size);
+ return 0;
+}
+
+static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void
+ *dest_buf, int size)
+{
+ if (size < algo->digest_size)
+ return -1;
+
+ sha384_finish((sha512_context *)ctx, dest_buf);
+ free(ctx);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SHA512)
+static int hash_init_sha512(struct hash_algo *algo, void **ctxp)
+{
+ sha512_context *ctx = malloc(sizeof(sha512_context));
+ sha512_starts(ctx);
+ *ctxp = ctx;
+ return 0;
+}
+
+static int hash_update_sha512(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size, int is_last)
+{
+ sha512_update((sha512_context *)ctx, buf, size);
+ return 0;
+}
+
+static int hash_finish_sha512(struct hash_algo *algo, void *ctx, void
+ *dest_buf, int size)
+{
+ if (size < algo->digest_size)
+ return -1;
+
+ sha512_finish((sha512_context *)ctx, dest_buf);
+ free(ctx);
+ return 0;
+}
+#endif
+
+
static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp)
{
uint16_t *ctx = malloc(sizeof(uint16_t));
#endif
},
#endif
+#ifdef CONFIG_SHA384
+ {
+ .name = "sha384",
+ .digest_size = SHA384_SUM_LEN,
+ .chunk_size = CHUNKSZ_SHA384,
+ .hash_func_ws = sha384_csum_wd,
+ .hash_init = hash_init_sha384,
+ .hash_update = hash_update_sha384,
+ .hash_finish = hash_finish_sha384,
+ },
+#endif
+#ifdef CONFIG_SHA512
+ {
+ .name = "sha512",
+ .digest_size = SHA512_SUM_LEN,
+ .chunk_size = CHUNKSZ_SHA512,
+ .hash_func_ws = sha512_csum_wd,
+ .hash_init = hash_init_sha512,
+ .hash_update = hash_update_sha512,
+ .hash_finish = hash_finish_sha512,
+ },
+#endif
{
.name = "crc16-ccitt",
.digest_size = 2,
/* Try to minimize code size for boards that don't want much hashing */
#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM) || \
- defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH)
+ defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH) || \
+ defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
#define multi_hash() 1
#else
#define multi_hash() 0
#include <u-boot/md5.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
/*****************************************************************************/
/* New uImage format routines */
sha256_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA256);
*value_len = SHA256_SUM_LEN;
+ } else if (IMAGE_ENABLE_SHA384 && strcmp(algo, "sha384") == 0) {
+ sha384_csum_wd((unsigned char *)data, data_len,
+ (unsigned char *)value, CHUNKSZ_SHA384);
+ *value_len = SHA384_SUM_LEN;
+ } else if (IMAGE_ENABLE_SHA512 && strcmp(algo, "sha512") == 0) {
+ sha512_csum_wd((unsigned char *)data, data_len,
+ (unsigned char *)value, CHUNKSZ_SHA512);
+ *value_len = SHA512_SUM_LEN;
} else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
*value_len = 16;
.calculate_sign = EVP_sha256,
#endif
.calculate = hash_calculate,
- }
+ },
+#ifdef CONFIG_SHA384
+ {
+ .name = "sha384",
+ .checksum_len = SHA384_SUM_LEN,
+ .der_len = SHA384_DER_LEN,
+ .der_prefix = sha384_der_prefix,
+#if IMAGE_ENABLE_SIGN
+ .calculate_sign = EVP_sha384,
+#endif
+ .calculate = hash_calculate,
+ },
+#endif
+#ifdef CONFIG_SHA512
+ {
+ .name = "sha512",
+ .checksum_len = SHA512_SUM_LEN,
+ .der_len = SHA512_DER_LEN,
+ .der_prefix = sha512_der_prefix,
+#if IMAGE_ENABLE_SIGN
+ .calculate_sign = EVP_sha512,
+#endif
+ .calculate = hash_calculate,
+ },
+#endif
};
secure as it is possible (with a brute-force attack) to adjust the
image while still retaining the same MD5 hash value. For secure
applications where images may be changed maliciously, you should
- consider SHA1 or SHA256.
+ consider SHA256 or SHA384.
config SPL_SHA1_SUPPORT
bool "Support SHA1"
image contents have not been corrupted or maliciously altered.
While SHA1 is fairly secure it is coming to the end of its life
due to the expanding computing power available to brute-force
- attacks. For more security, consider SHA256.
+ attacks. For more security, consider SHA256 or SHA384.
config SPL_SHA256_SUPPORT
bool "Support SHA256"
help
Enable this to support SHA256 in FIT images within SPL. A SHA256
checksum is a 256-bit (32-byte) hash value used to check that the
- image contents have not been corrupted. SHA256 is recommended for
- use in secure applications since (as at 2016) there is no known
- feasible attack that could produce a 'collision' with differing
- input data. Use this for the highest security. Note that only the
- SHA256 variant is supported: SHA512 and others are not currently
- supported in U-Boot.
+ image contents have not been corrupted.
+
+config SPL_SHA384_SUPPORT
+ bool "Support SHA384"
+ depends on SPL_FIT
+ select SHA384
+ select SHA512_ALGO
+ help
+ Enable this to support SHA384 in FIT images within SPL. A SHA384
+ checksum is a 384-bit (48-byte) hash value used to check that the
+ image contents have not been corrupted. Use this for the highest
+ security.
+
+config SPL_SHA512_SUPPORT
+ bool "Support SHA512"
+ depends on SPL_FIT
+ select SHA512
+ select SHA512_ALGO
+ help
+ Enable this to support SHA512 in FIT images within SPL. A SHA512
+ checksum is a 512-bit (64-byte) hash value used to check that the
+ image contents have not been corrupted.
config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_FMAN_ENET=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_CI_UDC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_DM_GPIO=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vga; setenv stderr serial,vga; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
+CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_PANDA=y
+CONFIG_DEFAULT_DEVICE_TREE="omap4-panda"
CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap4-panda.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+# CONFIG_SPI is not set
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_ETH=y
CONFIG_ENV_OFFSET=0xE0000
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_SDP4430=y
+CONFIG_DEFAULT_DEVICE_TREE="omap4-sdp"
CONFIG_CMD_BAT=y
CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap4-sdp.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
# CONFIG_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+# CONFIG_SPI is not set
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_USB_GADGET=y
# CONFIG_REGEX is not set
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_ETH=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_OMAP5_UEVM=y
+CONFIG_DEFAULT_DEVICE_TREE="omap5-uevm"
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_AHCI=y
CONFIG_SCSI_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+# CONFIG_SPI is not set
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_ETH=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_USB_MUSB_DA8XX=y
CONFIG_USB_MUSB_PIO_ONLY=y
CONFIG_USB_STORAGE=y
-# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_OF_LIBFDT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
-CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RESET=y
CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc rescan; if run bootcmd_up1; then run bootcmd_up2; else run bootcmd_mmc || run distro_bootcmd; fi"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="imx6q-tbs2910.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MEMTEST_END=0x2f400000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_I2C_EDID=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_GZIP is not set
CONFIG_OF_LIBFDT_ASSUME_MASK=0xff
# CONFIG_EFI_LOADER is not set
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_GIGE=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_XILINX_GMII2RGMII=y
CONFIG_PHY_FIXED=y
The following options are used to enable logging at compile time:
CONFIG_LOG - Enables the logging system
- CONFIG_MAX_LOG_LEVEL - Max log level to build (anything higher is compiled
+ CONFIG_LOG_MAX_LEVEL - Max log level to build (anything higher is compiled
out)
CONFIG_LOG_CONSOLE - Enable writing log records to the console
If CONFIG_LOG is not set, then no logging will be available.
-The above have SPL versions also, e.g. CONFIG_SPL_MAX_LOG_LEVEL.
+The above have SPL and TPL versions also, e.g. CONFIG_SPL_LOG_MAX_LEVEL and
+CONFIG_TPL_LOG_MAX_LEVEL.
Temporary logging within a single file
the appended kernel image will be booted using some generated and some
stored ATAGs (see boot order).
+For generating combined image of u-boot and kernel there is a simple script
+called u-boot-gen-combined. It is available in following repository:
+
+ https://github.com/pali/u-boot-maemo
+
There is support for hardware watchdog. Hardware watchdog is started by
NOLO so u-boot must kick watchdog to prevent reboot device (but not very
often, max every 2 seconds). There is also support for framebuffer display
rockchip/index
sifive/index
st/index
+ tbs/index
toradex/index
xilinx/index
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+TBS
+===
+
+.. toctree::
+ :maxdepth: 2
+
+ tbs2910
--- /dev/null
+TBS2910 Matrix ARM miniPC
+=========================
+
+Building
+--------
+To build u-boot for the TBS2910 Matrix ARM miniPC, you can use the following
+procedure:
+
+First add the ARM toolchain to your PATH
+
+Then setup the ARCH and cross compilation environment variables.
+
+When this is done you can then build u-boot for the TBS2910 Matrix ARM miniPC
+with the following commands:
+
+.. code-block:: none
+
+ make mrproper
+ make tbs2910_defconfig
+ make
+
+Once the build is complete, you can find the resulting image as u-boot.imx in
+the current directory.
+
+UART
+----
+The UART voltage is at 3.3V and its settings are 115200bps 8N1
+
+BOOT/UPDATE boot switch:
+------------------------
+The BOOT/UPDATE switch (SW11) is connected to the BOOT_MODE0 and
+BOOT_MODE1 SoC pins. It has "BOOT" and "UPDATE" markings both on
+the PCB and on the plastic case.
+
+When set to the "UPDATE" position, the SoC will use the "Boot From Fuses"
+configuration, and since BT_FUSE_SEL is 0, this makes the SOC jump to serial
+downloader.
+
+When set in the "BOOT" position, the SoC will use the "Internal boot"
+configuration, and since BT_FUSE_SEL is 0, it will then use the GPIO pins
+for the boot configuration.
+
+SW6 binary DIP switch array on the PCB revision 2.1:
+----------------------------------------------------
+On that PCB revision, SW6 has 8 positions.
+
+Switching a position to ON sets the corresponding
+register to 1.
+
+See the following table for a correspondence between the switch positions and
+registers:
+
+=============== ============
+Switch position Register
+=============== ============
+1 BOOT_CFG2[3]
+2 BOOT_CFG2[4]
+3 BOOT_CFG2[5]
+4 BOOT_CFG2[6]
+5 BOOT_CFG1[4]
+6 BOOT_CFG1[5]
+7 BOOT_CFG1[6]
+8 BOOT_CFG1[7]
+=============== ============
+
+For example:
+
+ - To boot from the eMMC: 1:ON , 2:ON, 3:ON, 4:OFF, 5:OFF, 6:ON, 7:ON, 8:OFF
+ - To boot from the microSD slot: 1: ON, 2: OFF, 3: OFF, 4: OFF, 5:OFF, 6:OFF,
+ 7:ON, 8:OFF
+ - To boot from the SD slot: 1: OFF, 2: ON, 3: OFF, 4: OFF, 5:OFF, 6:OFF, 7:ON,
+ 8:OFF
+ - To boot from SATA: 1: OFF, 2: OFF, 3: OFF, 4: OFF, 5:OFF, 6:ON, 7:OFF, 8:OFF
+
+You can refer to the BOOT_CFG registers in the I.MX6Q reference manual for
+additional details.
+
+SW6 binary DIP switch array on the PCB revision 2.3:
+----------------------------------------------------
+On that PCB revision, SW6 has only 4 positions.
+
+Switching a position to ON sets the corresponding
+register to 1.
+
+See the following table for a correspondence between the switch positions and
+registers:
+
+=============== ============
+Switch position Register
+=============== ============
+1 BOOT_CFG2[3]
+2 BOOT_CFG2[4]
+3 BOOT_CFG2[5]
+4 BOOT_CFG1[5]
+=============== ============
+
+For example:
+
+- To boot from the eMMC: 1:ON, 2:ON, 3:ON, 4:ON
+- To boot from the microSD slot: 1:ON, 2:OFF, 3:OFF, 4:OFF
+- To boot from the SD slot: 1:OFF, 2:ON, 3:OFF, 4:OFF
+
+You can refer to the BOOT_CFG registers in the I.MX6Q reference manual for
+additional details.
+
+Loading u-boot from USB:
+------------------------
+If you need to load u-boot from USB, you can use the following instructions:
+
+First build imx_usb_loader, as we will need it to load u-boot from USB. This
+can be done with the following commands:
+
+.. code-block:: none
+
+ git clone git://github.com/boundarydevices/imx_usb_loader.git
+ cd imx_usb_loader
+ make
+
+This will create the resulting imx_usb binary.
+
+When this is done, you can copy the u-boot.imx image that you built earlier
+in in the imx_usb_loader directory.
+
+You will then need to power off the TBS2910 Matrix ARM miniPC and make sure that
+the boot switch is set to "UPDATE"
+
+Once this is done you can connect an USB cable between the computer that will
+run imx_usb and the TBS2910 Matrix ARM miniPC.
+
+If you also need to access the u-boot console, you will also need to connect an
+UART cable between the computer running imx_usb and the TBS2910 Matrix ARM
+miniPC.
+
+Once everything is connected you can finally power on the TBS2910 Matrix ARM
+miniPC. The SoC will then jump to the serial download and wait for you.
+
+Finlay, you can load u-boot through USB with with the following command:
+
+.. code-block:: none
+
+ sudo ./imx_usb -v u-boot.imx
+
+The u-boot boot messages will then appear in the serial console.
+
+Install u-boot on the eMMC:
+---------------------------
+To install u-boot on the eMMC, you first need to boot the TBS2910 Matrix ARM
+miniPC.
+
+Once booted, you can flash u-boot.imx to mmcblk0boot0 with the
+following commands:
+
+.. code-block:: none
+
+ sudo echo 0 >/sys/block/mmcblk0boot0/force_ro
+ sudo dd if=u-boot.imx of=/dev/mmcblk0boot0 bs=1k seek=1; sync
+
+Note that the eMMC card node may vary, so adjust this as needed.
+
+Once the new u-boot version is installed, to boot on it you then need to power
+off the TBS2910 Matrix ARM miniPC.
+
+Once it is off, you need make sure that the boot switch is set to "BOOT" and
+that the SW6 switch is set to boot on the eMMC as described in the previous
+sections.
+
+If you also need to access the u-boot console, you will also need to connect an
+UART cable between the computer running imx_usb and the TBS2910 Matrix ARM
+miniPC.
+
+You can then power up the TBS2910 Matrix ARM miniPC and U-Boot messages will
+appear in the serial console.
+
+Booting a distribution:
+-----------------------
+When booting on the TBS2910 Matrix ARM miniPC, by default U-Boot will first try
+to boot from hardcoded offsets from the start of the eMMC. This is for
+compatibility with the stock GNU/Linux distribution.
+
+If that fails it will then try to boot from several interfaces using
+'distro_bootcmd': It will first try to boot from the microSD slot, then the
+SD slot, then the internal eMMC, then the SATA interface and finally the USB
+interface. For more information on how to configure your distribution to boot,
+see 'README.distro'.
+
+Links:
+------
+ - https://www.tbsdtv.com/download/document/tbs2910/TBS2910-Matrix-ARM-mini-PC-SCH_rev2.1.pdf
+ - The schematics for the revision 2.1 of the TBS2910 Matrix ARM miniPC.
+ - https://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf - The
+ SoC reference manual for additional details on the BOOT_CFG registers.
:maxdepth: 2
crash_dumps
+ logging
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2017 Simon Glass <sjg@chromium.org>
+
+Logging in U-Boot
+=================
+
+Introduction
+------------
+
+U-Boot's internal operation involves many different steps and actions. From
+setting up the board to displaying a start-up screen to loading an Operating
+System, there are many component parts each with many actions.
+
+Most of the time this internal detail is not useful. Displaying it on the
+console would delay booting (U-Boot's primary purpose) and confuse users.
+
+But for digging into what is happening in a particular area, or for debugging
+a problem it is often useful to see what U-Boot is doing in more detail than
+is visible from the basic console output.
+
+U-Boot's logging feature aims to satisfy this goal for both users and
+developers.
+
+
+Logging levels
+--------------
+
+There are a number logging levels available, in increasing order of verbosity:
+
+* LOGL_EMERG - Printed before U-Boot halts
+* LOGL_ALERT - Indicates action must be taken immediate or U-Boot will crash
+* LOGL_CRIT - Indicates a critical error that will cause boot failure
+* LOGL_ERR - Indicates an error that may cause boot failure
+* LOGL_WARNING - Warning about an unexpected condition
+* LOGL_NOTE - Important information about progress
+* LOGL_INFO - Information about normal boot progress
+* LOGL_DEBUG - Debug information (useful for debugging a driver or subsystem)
+* LOGL_DEBUG_CONTENT - Debug message showing full message content
+* LOGL_DEBUG_IO - Debug message showing hardware I/O access
+
+
+Logging category
+----------------
+
+Logging can come from a wide variety of places within U-Boot. Each log message
+has a category which is intended to allow messages to be filtered according to
+their source.
+
+The following main categories are defined:
+
+* LOGC_NONE - Unknown category (e.g. a debug() statement)
+* UCLASS\_... - Related to a particular uclass (e.g. UCLASS_USB)
+* LOGC_ARCH - Related to architecture-specific code
+* LOGC_BOARD - Related to board-specific code
+* LOGC_CORE - Related to core driver-model support
+* LOGC_DT - Related to device tree control
+* LOGC_EFI - Related to EFI implementation
+
+
+Enabling logging
+----------------
+
+The following options are used to enable logging at compile time:
+
+* CONFIG_LOG - Enables the logging system
+* CONFIG_LOG_MAX_LEVEL - Max log level to build (anything higher is compiled
+ out)
+* CONFIG_LOG_CONSOLE - Enable writing log records to the console
+
+If CONFIG_LOG is not set, then no logging will be available.
+
+The above have SPL and TPL versions also, e.g. CONFIG_SPL_LOG_MAX_LEVEL and
+CONFIG_TPL_LOG_MAX_LEVEL.
+
+
+Temporary logging within a single file
+--------------------------------------
+
+Sometimes it is useful to turn on logging just in one file. You can use this
+
+.. code-block:: c
+
+ #define LOG_DEBUG
+
+to enable building in of all logging statements in a single file. Put it at
+the top of the file, before any #includes.
+
+To actually get U-Boot to output this you need to also set the default logging
+level - e.g. set CONFIG_LOG_DEFAULT_LEVEL to 7 (LOGL_DEBUG) or more. Otherwise
+debug output is suppressed and will not be generated.
+
+
+Convenience functions
+---------------------
+
+A number of convenience functions are available to shorten the code needed
+for logging:
+
+* log_err(_fmt...)
+* log_warning(_fmt...)
+* log_notice(_fmt...)
+* log_info(_fmt...)
+* log_debug(_fmt...)
+* log_content(_fmt...)
+* log_io(_fmt...)
+
+With these the log level is implicit in the name. The category is set by
+LOG_CATEGORY, which you can only define once per file, above all #includes, e.g.
+
+.. code-block:: c
+
+ #define LOG_CATEGORY LOGC_ALLOC
+
+Remember that all uclasses IDs are log categories too.
+
+
+Log command
+-----------
+
+The 'log' command provides access to several features:
+
+* level - access the default log level
+* format - access the console log format
+* rec - output a log record
+* test - run tests
+
+Type 'help log' for details.
+
+
+Using DEBUG
+-----------
+
+U-Boot has traditionally used a #define called DEBUG to enable debugging on a
+file-by-file basis. The debug() macro compiles to a printf() statement if
+DEBUG is enabled, and an empty statement if not.
+
+With logging enabled, debug() statements are interpreted as logging output
+with a level of LOGL_DEBUG and a category of LOGC_NONE.
+
+The logging facilities are intended to replace DEBUG, but if DEBUG is defined
+at the top of a file, then it takes precedence. This means that debug()
+statements will result in output to the console and this output will not be
+logged.
+
+
+Logging destinations
+--------------------
+
+If logging information goes nowhere then it serves no purpose. U-Boot provides
+several possible determinations for logging information, all of which can be
+enabled or disabled independently:
+
+* console - goes to stdout
+* syslog - broadcast RFC 3164 messages to syslog servers on UDP port 514
+
+The syslog driver sends the value of environmental variable 'log_hostname' as
+HOSTNAME if available.
+
+
+Log format
+----------
+
+You can control the log format using the 'log format' command. The basic
+format is::
+
+ LEVEL.category,file.c:123-func() message
+
+In the above, file.c:123 is the filename where the log record was generated and
+func() is the function name. By default ('log format default') only the
+function name and message are displayed on the console. You can control which
+fields are present, but not the field order.
+
+
+Filters
+-------
+
+Filters are attached to log drivers to control what those drivers emit. Only
+records that pass through the filter make it to the driver.
+
+Filters can be based on several criteria:
+
+* maximum log level
+* in a set of categories
+* in a set of files
+
+If no filters are attached to a driver then a default filter is used, which
+limits output to records with a level less than CONFIG_MAX_LOG_LEVEL.
+
+
+Logging statements
+------------------
+
+The main logging function is:
+
+.. code-block:: c
+
+ log(category, level, format_string, ...)
+
+Also debug() and error() will generate log records - these use LOG_CATEGORY
+as the category, so you should #define this right at the top of the source
+file to ensure the category is correct.
+
+You can also define CONFIG_LOG_ERROR_RETURN to enable the log_ret() macro. This
+can be used whenever your function returns an error value:
+
+.. code-block:: c
+
+ return log_ret(uclass_first_device(UCLASS_MMC, &dev));
+
+This will write a log record when an error code is detected (a value < 0). This
+can make it easier to trace errors that are generated deep in the call stack.
+
+
+Code size
+---------
+
+Code size impact depends largely on what is enabled. The following numbers are
+generated by 'buildman -S' for snow, which is a Thumb-2 board (all units in
+bytes)::
+
+ This series: adds bss +20.0 data +4.0 rodata +4.0 text +44.0
+ CONFIG_LOG: bss -52.0 data +92.0 rodata -635.0 text +1048.0
+ CONFIG_LOG_MAX_LEVEL=7: bss +188.0 data +4.0 rodata +49183.0 text +98124.0
+
+The last option turns every debug() statement into a logging call, which
+bloats the code hugely. The advantage is that it is then possible to enable
+all logging within U-Boot.
+
+
+To Do
+-----
+
+There are lots of useful additions that could be made. None of the below is
+implemented! If you do one, please add a test in test/py/tests/test_log.py
+
+Convenience functions to support setting the category:
+
+* log_arch(level, format_string, ...) - category LOGC_ARCH
+* log_board(level, format_string, ...) - category LOGC_BOARD
+* log_core(level, format_string, ...) - category LOGC_CORE
+* log_dt(level, format_string, ...) - category LOGC_DT
+
+More logging destinations:
+
+* device - goes to a device (e.g. serial)
+* buffer - recorded in a memory buffer
+
+Convert debug() statements in the code to log() statements
+
+Support making printf() emit log statements at L_INFO level
+
+Convert error() statements in the code to log() statements
+
+Figure out what to do with BUG(), BUG_ON() and warn_non_spl()
+
+Figure out what to do with assert()
+
+Add a way to browse log records
+
+Add a way to record log records for browsing using an external tool
+
+Add commands to add and remove filters
+
+Add commands to add and remove log devices
+
+Allow sharing of printf format strings in log records to reduce storage size
+for large numbers of log records
+
+Add a command-line option to sandbox to set the default logging level
+
+Convert core driver model code to use logging
+
+Convert uclasses to use logging with the correct category
+
+Consider making log() calls emit an automatic newline, perhaps with a logn()
+function to avoid that
+
+Passing log records through to linux (e.g. via device tree /chosen)
+
+Provide a command to access the number of log records generated, and the
+number dropped due to them being generated before the log system was ready.
+
+Add a printf() format string pragma so that log statements are checked properly
+
+Enhance the log console driver to show level / category / file / line
+information
+
+Add a command to add new log records and delete existing records.
+
+Provide additional log() functions - e.g. logc() to specify the category
xhci_usb (UCLASS_USB)
flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by USB bus
- sata (UCLASS_SATA)
+ sata (UCLASS_AHCI)
flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by SATA bus
flash (UCLASS_FLASH_STORAGE) - no parent data/methods (not on a bus)
bus device, regardless of its own views on the matter.
The uclass for the device can also contain data private to that uclass.
-But note that each device on the bus may be a memeber of a different
+But note that each device on the bus may be a member of a different
uclass, and this data has nothing to do with the child data for each child
on the bus. It is the bus' uclass that controls the child with respect to
the bus.
}
range = &map->ranges[range_num];
- ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
-
if (offset + val_len > range->size) {
debug("%s: offset/size combination invalid\n", __func__);
return -ERANGE;
}
+ ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
+
switch (val_len) {
case REGMAP_SIZE_8:
*((u8 *)valp) = __read_8(ptr, map->endianness);
}
range = &map->ranges[range_num];
- ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
-
if (offset + val_len > range->size) {
debug("%s: offset/size combination invalid\n", __func__);
return -ERANGE;
}
+ ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
+
switch (val_len) {
case REGMAP_SIZE_8:
__write_8(ptr, val, map->endianness);
int uclass_resolve_seq(struct udevice *dev)
{
+ struct uclass *uc = dev->uclass;
+ struct uclass_driver *uc_drv = uc->uc_drv;
struct udevice *dup;
- int seq;
+ int seq = 0;
int ret;
assert(dev->seq == -1);
- ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, dev->req_seq,
- false, &dup);
+ ret = uclass_find_device_by_seq(uc_drv->id, dev->req_seq, false, &dup);
if (!ret) {
dm_warn("Device '%s': seq %d is in use by '%s'\n",
dev->name, dev->req_seq, dup->name);
return ret;
}
- for (seq = 0; seq < DM_MAX_SEQ; seq++) {
- ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, seq,
- false, &dup);
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS) &&
+ (uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS)) {
+ /*
+ * dev_read_alias_highest_id() will return -1 if there no
+ * alias. Thus we can always add one.
+ */
+ seq = dev_read_alias_highest_id(uc_drv->name) + 1;
+ }
+
+ for (; seq < DM_MAX_SEQ; seq++) {
+ ret = uclass_find_device_by_seq(uc_drv->id, seq, false, &dup);
if (ret == -ENODEV)
break;
if (ret)
#endif
-static inline int get_gpio_index(int gpio)
-{
- return gpio & 0x1f;
-}
-
int gpio_is_valid(int gpio)
{
return (gpio >= 0) && (gpio < OMAP_MAX_GPIO);
}
#if !CONFIG_IS_ENABLED(DM_GPIO)
+static inline int get_gpio_index(int gpio)
+{
+ return gpio & 0x1f;
+}
static inline const struct gpio_bank *get_gpio_bank(int gpio)
{
#include <asm-generic/gpio.h>
#include <linux/delay.h>
-#define DAVINCI_MAX_BLOCKS (32)
#define WATCHDOG_COUNT (100000)
#define get_val(addr) REG(addr)
struct gpio_desc cd_gpio; /* Card Detect GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
};
-
-struct davinci_mmc_plat
-{
- struct mmc_config cfg;
- struct mmc mmc;
-};
#endif
/* Set davinci clock prescalar value based on the required clock in HZ */
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct davinci_mmc_plat *plat = dev_get_platdata(dev);
struct davinci_mmc_priv *priv = dev_get_priv(dev);
- struct mmc_config *cfg = &plat->cfg;
-#ifdef CONFIG_SPL_BUILD
- int ret;
-#endif
-
- cfg->f_min = 200000;
- cfg->f_max = 25000000;
- cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
- cfg->b_max = DAVINCI_MAX_BLOCKS;
- cfg->name = "da830-mmc";
- priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
+ priv->reg_base = plat->reg_base;
priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
-
#if CONFIG_IS_ENABLED(DM_GPIO)
/* These GPIOs are optional */
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
-
upriv->mmc = &plat->mmc;
-#ifdef CONFIG_SPL_BUILD
- /*
- * FIXME This is a temporary workaround to enable the driver model in
- * SPL on omapl138-lcdk. For some reason the bind() callback is not
- * being called in SPL for MMC which breaks the mmc boot - the hack
- * is to call mmc_bind() from probe(). We also don't have full DT
- * support in SPL, hence the hard-coded base register address.
- */
- priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
- ret = mmc_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-#endif
-
return davinci_dm_mmc_init(dev);
}
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int davinci_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg = &plat->cfg;
+
+ plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
+ cfg->f_min = 200000;
+ cfg->f_max = 25000000;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
+ cfg->b_max = DAVINCI_MAX_BLOCKS;
+ cfg->name = "da830-mmc";
+
+ return 0;
+}
+
static const struct udevice_id davinci_mmc_ids[] = {
{ .compatible = "ti,da830-mmc" },
{},
};
-
+#endif
U_BOOT_DRIVER(davinci_mmc_drv) = {
.name = "davinci_mmc",
.id = UCLASS_MMC,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = davinci_mmc_ids,
+ .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
+ .ofdata_to_platdata = davinci_mmc_ofdata_to_platdata,
+#endif
#if CONFIG_BLK
.bind = davinci_mmc_bind,
#endif
.probe = davinci_mmc_probe,
.ops = &davinci_mmc_ops,
- .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+ .flags = DM_FLAG_PRE_RELOC,
+#endif
};
#endif
return (struct omap_hsmmc_data *)mmc->priv;
#endif
}
+
+#if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
{
#if CONFIG_IS_ENABLED(DM_MMC)
return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
#endif
}
+#endif
#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
static int omap_mmc_setup_gpio_in(int gpio, const char *label)
config PHY_TI
bool "Texas Instruments Ethernet PHYs support"
+ ---help---
+ Adds PHY registration support for TI PHYs.
+
+config PHY_TI_DP83867
+ select PHY_TI
+ bool "Texas Instruments Ethernet DP83867 PHY support"
+ ---help---
+ Adds support for the TI DP83867 1Gbit PHY.
+
+config PHY_TI_GENERIC
+ select PHY_TI
+ bool "Texas Instruments Generic Ethernet PHYs support"
+ ---help---
+ Adds support for Generic TI PHYs that don't need special handling but
+ the PHY name is associated with a PHY ID.
config PHY_VITESSE
bool "Vitesse Ethernet PHYs support"
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
-obj-$(CONFIG_PHY_TI) += dp83867.o
+obj-$(CONFIG_PHY_TI) += ti_phy_init.o
+obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o
obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
#include <dm.h>
#include <dt-bindings/net/ti-dp83867.h>
+#include "ti_phy_init.h"
/* TI DP83867 */
#define DP83867_DEVADDR 0x1f
.shutdown = &genphy_shutdown,
};
-int phy_ti_init(void)
+int phy_dp83867_init(void)
{
phy_register(&DP83867_driver);
return 0;
.shutdown = &genphy_shutdown,
};
+static int ksz8061_config(struct phy_device *phydev)
+{
+ return phy_write(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
+}
+
+static struct phy_driver KSZ8061_driver = {
+ .name = "Micrel KSZ8061",
+ .uid = 0x00221570,
+ .mask = 0xfffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &ksz8061_config,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static int ksz8081_config(struct phy_device *phydev)
{
int ret;
phy_register(&KSZ804_driver);
phy_register(&KSZ8031_driver);
phy_register(&KSZ8051_driver);
+ phy_register(&KSZ8061_driver);
phy_register(&KSZ8081_driver);
phy_register(&KS8721_driver);
phy_register(&ksz8895_driver);
uint phy_mask,
phy_interface_t interface)
{
- int i;
struct phy_device *phydev;
-
+ int devad[] = {
+ /* Clause-22 */
+ MDIO_DEVAD_NONE,
+ /* Clause-45 */
+ MDIO_MMD_PMAPMD,
+ MDIO_MMD_WIS,
+ MDIO_MMD_PCS,
+ MDIO_MMD_PHYXS,
+ MDIO_MMD_VEND1,
+ };
+ int i, devad_cnt;
+
+ devad_cnt = sizeof(devad)/sizeof(int);
phydev = search_for_existing_phy(bus, phy_mask, interface);
if (phydev)
return phydev;
- /* Try Standard (ie Clause 22) access */
- /* Otherwise we have to try Clause 45 */
- for (i = 0; i < 5; i++) {
+ /* try different access clauses */
+ for (i = 0; i < devad_cnt; i++) {
phydev = create_phy_by_mask(bus, phy_mask,
- i ? i : MDIO_DEVAD_NONE, interface);
+ devad[i], interface);
if (IS_ERR(phydev))
return NULL;
if (phydev)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI Generic PHY Init to register any TI Ethernet PHYs
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright (C) 2019-20 Texas Instruments Inc.
+ */
+
+#include <phy.h>
+#include "ti_phy_init.h"
+
+#ifdef CONFIG_PHY_TI_GENERIC
+static struct phy_driver dp83822_driver = {
+ .name = "TI DP83822",
+ .uid = 0x2000a240,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83826nc_driver = {
+ .name = "TI DP83826NC",
+ .uid = 0x2000a110,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83826c_driver = {
+ .name = "TI DP83826C",
+ .uid = 0x2000a130,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825s_driver = {
+ .name = "TI DP83825S",
+ .uid = 0x2000a140,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825i_driver = {
+ .name = "TI DP83825I",
+ .uid = 0x2000a150,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825m_driver = {
+ .name = "TI DP83825M",
+ .uid = 0x2000a160,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825cs_driver = {
+ .name = "TI DP83825CS",
+ .uid = 0x2000a170,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+#endif /* CONFIG_PHY_TI_GENERIC */
+
+int phy_ti_init(void)
+{
+#ifdef CONFIG_PHY_TI_DP83867
+ phy_dp83867_init();
+#endif
+
+#ifdef CONFIG_PHY_TI_GENERIC
+ phy_register(&dp83822_driver);
+ phy_register(&dp83825s_driver);
+ phy_register(&dp83825i_driver);
+ phy_register(&dp83825m_driver);
+ phy_register(&dp83825cs_driver);
+ phy_register(&dp83826c_driver);
+ phy_register(&dp83826nc_driver);
+#endif
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * TI Generic Ethernet PHY
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright (C) 2019-20 Texas Instruments Inc.
+ */
+
+#ifndef _TI_GEN_PHY_H
+#define _TI_GEN_PHY_H
+
+int phy_dp83867_init(void);
+
+#endif /* _TI_GEN_PHY_H */
#include <common.h>
#include <cpu_func.h>
+#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <net.h>
#define DEBUG_TX 0 /* set to 1 to enable debug code */
#define DEBUG_RX 0 /* set to 1 to enable debug code */
-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+#ifdef CONFIG_DM_ETH
+#define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
+#define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
+#else
+#define bus_to_phys(devno, a) pci_mem_to_phys((pci_dev_t)(devno), (a))
+#define phys_to_bus(devno, a) pci_phys_to_mem((pci_dev_t)(devno), (a))
+#endif
/* Symbolic offsets to registers. */
/* Ethernet hardware address. */
#define RTL_STS_RXBADALIGN BIT(1)
#define RTL_STS_RXSTATUSOK BIT(0)
-static unsigned int cur_rx, cur_tx;
-static int ioaddr;
+struct rtl8139_priv {
+#ifndef CONFIG_DM_ETH
+ struct eth_device dev;
+ pci_dev_t devno;
+#else
+ struct udevice *devno;
+#endif
+ unsigned int rxstatus;
+ unsigned int cur_rx;
+ unsigned int cur_tx;
+ unsigned long ioaddr;
+ unsigned char enetaddr[6];
+};
/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
#define EE_READ_CMD 6
#define EE_ERASE_CMD 7
-static void rtl8139_eeprom_delay(uintptr_t regbase)
+static void rtl8139_eeprom_delay(struct rtl8139_priv *priv)
{
/*
* Delay between EEPROM clock transitions.
* No extra delay is needed with 33MHz PCI, but 66MHz may change this.
*/
- inl(regbase + RTL_REG_CFG9346);
+ inl(priv->ioaddr + RTL_REG_CFG9346);
}
-static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len)
+static int rtl8139_read_eeprom(struct rtl8139_priv *priv,
+ unsigned int location, unsigned int addr_len)
{
unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
- uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346;
+ uintptr_t ee_addr = priv->ioaddr + RTL_REG_CFG9346;
unsigned int retval = 0;
u8 dataval;
int i;
outb(EE_ENB & ~EE_CS, ee_addr);
outb(EE_ENB, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
outb(EE_ENB | dataval, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
}
outb(EE_ENB, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
for (i = 16; i > 0; i--) {
outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
retval <<= 1;
retval |= inb(ee_addr) & EE_DATA_READ;
outb(EE_ENB, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
}
/* Terminate the EEPROM access. */
outb(~EE_CS, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
return retval;
}
(RX_FIFO_THRESH << 13) |
(RX_DMA_BURST << 8);
-static void rtl8139_set_rx_mode(struct eth_device *dev)
+static void rtl8139_set_rx_mode(struct rtl8139_priv *priv)
{
/* !IFF_PROMISC */
unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
RTL_REG_RXCONFIG_ACCEPTMULTICAST |
RTL_REG_RXCONFIG_ACCEPTMYPHYS;
- outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
+ outl(rtl8139_rx_config | rx_mode, priv->ioaddr + RTL_REG_RXCONFIG);
- outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0);
- outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4);
+ outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 0);
+ outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 4);
}
-static void rtl8139_hw_reset(struct eth_device *dev)
+static void rtl8139_hw_reset(struct rtl8139_priv *priv)
{
u8 reg;
int i;
- outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
+ outb(RTL_REG_CHIPCMD_CMDRESET, priv->ioaddr + RTL_REG_CHIPCMD);
/* Give the chip 10ms to finish the reset. */
for (i = 0; i < 100; i++) {
- reg = inb(ioaddr + RTL_REG_CHIPCMD);
+ reg = inb(priv->ioaddr + RTL_REG_CHIPCMD);
if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
break;
}
}
-static void rtl8139_reset(struct eth_device *dev)
+static void rtl8139_reset(struct rtl8139_priv *priv)
{
int i;
- cur_rx = 0;
- cur_tx = 0;
+ priv->cur_rx = 0;
+ priv->cur_tx = 0;
- rtl8139_hw_reset(dev);
+ rtl8139_hw_reset(priv);
for (i = 0; i < ETH_ALEN; i++)
- outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
+ outb(priv->enetaddr[i], priv->ioaddr + RTL_REG_MAC0 + i);
/* Must enable Tx/Rx before setting transfer thresholds! */
outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
- ioaddr + RTL_REG_CHIPCMD);
+ priv->ioaddr + RTL_REG_CHIPCMD);
/* accept no frames yet! */
- outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
- outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG);
+ outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
+ outl((TX_DMA_BURST << 8) | 0x03000000, priv->ioaddr + RTL_REG_TXCONFIG);
/*
* The Linux driver changes RTL_REG_CONFIG1 here to use a different
debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
- outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
+ outl(phys_to_bus(priv->devno, (int)rx_ring), priv->ioaddr + RTL_REG_RXBUF);
/*
* If we add multicast support, the RTL_REG_MAR0 register would have
* unicast.
*/
outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
- ioaddr + RTL_REG_CHIPCMD);
+ priv->ioaddr + RTL_REG_CHIPCMD);
- outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
+ outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
/* Start the chip's Tx and Rx process. */
- outl(0, ioaddr + RTL_REG_RXMISSED);
+ outl(0, priv->ioaddr + RTL_REG_RXMISSED);
- rtl8139_set_rx_mode(dev);
+ rtl8139_set_rx_mode(priv);
/* Disable all known interrupts by setting the interrupt mask. */
- outw(0, ioaddr + RTL_REG_INTRMASK);
+ outw(0, priv->ioaddr + RTL_REG_INTRMASK);
}
-static int rtl8139_send(struct eth_device *dev, void *packet, int length)
+static int rtl8139_send_common(struct rtl8139_priv *priv,
+ void *packet, int length)
{
unsigned int len = length;
unsigned long txstatus;
unsigned int status;
int i = 0;
- ioaddr = dev->iobase;
-
memcpy(tx_buffer, packet, length);
debug_cond(DEBUG_TX, "sending %d bytes\n", len);
tx_buffer[len++] = '\0';
flush_cache((unsigned long)tx_buffer, length);
- outl(phys_to_bus((unsigned long)tx_buffer),
- ioaddr + RTL_REG_TXADDR0 + cur_tx * 4);
+ outl(phys_to_bus(priv->devno, (unsigned long)tx_buffer),
+ priv->ioaddr + RTL_REG_TXADDR0 + priv->cur_tx * 4);
outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
- ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
+ priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
do {
- status = inw(ioaddr + RTL_REG_INTRSTATUS);
+ status = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
/*
* Only acknlowledge interrupt sources we can properly
* handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
*/
status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
RTL_REG_INTRSTATUS_PCIERR;
- outw(status, ioaddr + RTL_REG_INTRSTATUS);
+ outw(status, priv->ioaddr + RTL_REG_INTRSTATUS);
if (status)
break;
udelay(10);
} while (i++ < RTL_TIMEOUT);
- txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
+ txstatus = inl(priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
debug_cond(DEBUG_TX,
"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
10 * i, status, txstatus);
- rtl8139_reset(dev);
+ rtl8139_reset(priv);
return 0;
}
- cur_tx = (cur_tx + 1) % NUM_TX_DESC;
+ priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC;
debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
status, txstatus);
return length;
}
-static int rtl8139_recv(struct eth_device *dev)
+static int rtl8139_recv_common(struct rtl8139_priv *priv, unsigned char *rxdata,
+ uchar **packetp)
{
const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
RTL_REG_INTRSTATUS_RXOVERFLOW |
RTL_REG_INTRSTATUS_RXOK;
unsigned int rx_size, rx_status;
unsigned int ring_offs;
- unsigned int status;
int length = 0;
- ioaddr = dev->iobase;
-
- if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
+ if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
return 0;
- status = inw(ioaddr + RTL_REG_INTRSTATUS);
+ priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
/* See below for the rest of the interrupt acknowledges. */
- outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS);
+ outw(priv->rxstatus & ~rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
- debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status);
+ debug_cond(DEBUG_RX, "%s: int %hX ", __func__, priv->rxstatus);
- ring_offs = cur_rx % RX_BUF_LEN;
+ ring_offs = priv->cur_rx % RX_BUF_LEN;
/* ring_offs is guaranteed being 4-byte aligned */
rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
rx_size = rx_status >> 16;
(rx_size > ETH_FRAME_LEN + 4)) {
printf("rx error %hX\n", rx_status);
/* this clears all interrupts still pending */
- rtl8139_reset(dev);
+ rtl8139_reset(priv);
return 0;
}
/* Received a good packet */
length = rx_size - 4; /* no one cares about the FCS */
if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
- unsigned char rxdata[RX_BUF_LEN];
int semi_count = RX_BUF_LEN - ring_offs - 4;
memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
memcpy(&rxdata[semi_count], rx_ring,
rx_size - 4 - semi_count);
- net_process_received_packet(rxdata, length);
+ *packetp = rxdata;
debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
semi_count, rx_size - 4 - semi_count);
} else {
- net_process_received_packet(rx_ring + ring_offs + 4, length);
+ *packetp = rx_ring + ring_offs + 4;
debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
}
+
+ return length;
+}
+
+static int rtl8139_free_pkt_common(struct rtl8139_priv *priv, unsigned int len)
+{
+ const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
+ RTL_REG_INTRSTATUS_RXOVERFLOW |
+ RTL_REG_INTRSTATUS_RXOK;
+ unsigned int rx_size = len + 4;
+
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
- cur_rx = ROUND(cur_rx + rx_size + 4, 4);
- outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
+ priv->cur_rx = ROUND(priv->cur_rx + rx_size + 4, 4);
+ outw(priv->cur_rx - 16, priv->ioaddr + RTL_REG_RXBUFPTR);
/*
* See RTL8139 Programming Guide V0.1 for the official handling of
* Rx overflow situations. The document itself contains basically
* no usable information, except for a few exception handling rules.
*/
- outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS);
+ outw(priv->rxstatus & rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
- return length;
+ return 0;
}
-static int rtl8139_init(struct eth_device *dev, bd_t *bis)
+static int rtl8139_init_common(struct rtl8139_priv *priv)
{
- unsigned short *ap = (unsigned short *)dev->enetaddr;
- int addr_len, i;
u8 reg;
- ioaddr = dev->iobase;
-
/* Bring the chip out of low-power mode. */
- outb(0x00, ioaddr + RTL_REG_CONFIG1);
+ outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
- addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6;
- for (i = 0; i < 3; i++)
- *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len));
-
- rtl8139_reset(dev);
+ rtl8139_reset(priv);
- reg = inb(ioaddr + RTL_REG_MEDIASTATUS);
+ reg = inb(priv->ioaddr + RTL_REG_MEDIASTATUS);
if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
printf("Cable not connected or other link failure\n");
return -1;
return 0;
}
-static void rtl8139_stop(struct eth_device *dev)
+static void rtl8139_stop_common(struct rtl8139_priv *priv)
{
- ioaddr = dev->iobase;
+ rtl8139_hw_reset(priv);
+}
- rtl8139_hw_reset(dev);
+static void rtl8139_get_hwaddr(struct rtl8139_priv *priv)
+{
+ unsigned short *ap = (unsigned short *)priv->enetaddr;
+ int i, addr_len;
+
+ /* Bring the chip out of low-power mode. */
+ outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
+
+ addr_len = rtl8139_read_eeprom(priv, 0, 8) == 0x8129 ? 8 : 6;
+ for (i = 0; i < 3; i++)
+ *ap++ = le16_to_cpu(rtl8139_read_eeprom(priv, i + 7, addr_len));
}
-static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
- int join)
+static void rtl8139_name(char *str, int card_number)
{
- return 0;
+ sprintf(str, "RTL8139#%u", card_number);
}
static struct pci_device_id supported[] = {
- { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 },
- { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 },
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139) },
+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139) },
{ }
};
+#ifndef CONFIG_DM_ETH
+static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
+ int join)
+{
+ return 0;
+}
+
+static int rtl8139_init(struct eth_device *dev, bd_t *bis)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+
+ return rtl8139_init_common(priv);
+}
+
+static void rtl8139_stop(struct eth_device *dev)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+
+ return rtl8139_stop_common(priv);
+}
+
+static int rtl8139_send(struct eth_device *dev, void *packet, int length)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+
+ return rtl8139_send_common(priv, packet, length);
+}
+
+static int rtl8139_recv(struct eth_device *dev)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+ unsigned char rxdata[RX_BUF_LEN];
+ uchar *packet;
+ int ret;
+
+ ret = rtl8139_recv_common(priv, rxdata, &packet);
+ if (ret) {
+ net_process_received_packet(packet, ret);
+ rtl8139_free_pkt_common(priv, ret);
+ }
+
+ return ret;
+}
+
int rtl8139_initialize(bd_t *bis)
{
+ struct rtl8139_priv *priv;
struct eth_device *dev;
int card_number = 0;
pci_dev_t devno;
debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
- dev = (struct eth_device *)malloc(sizeof(*dev));
- if (!dev) {
+ priv = calloc(1, sizeof(*priv));
+ if (!priv) {
printf("Can not allocate memory of rtl8139\n");
break;
}
- memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "RTL8139#%d", card_number);
+ priv->devno = devno;
+ priv->ioaddr = (unsigned long)bus_to_phys(devno, iobase);
+
+ dev = &priv->dev;
+
+ rtl8139_name(dev->name, card_number);
- dev->priv = (void *)devno;
- dev->iobase = (int)bus_to_phys(iobase);
+ dev->iobase = priv->ioaddr; /* Non-DM compatibility */
dev->init = rtl8139_init;
dev->halt = rtl8139_stop;
dev->send = rtl8139_send;
dev->recv = rtl8139_recv;
dev->mcast = rtl8139_bcast_addr;
+ rtl8139_get_hwaddr(priv);
+
+ /* Non-DM compatibility */
+ memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
+
eth_register(dev);
card_number++;
return card_number;
}
+#else /* DM_ETH */
+static int rtl8139_start(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+ return rtl8139_init_common(priv);
+}
+
+static void rtl8139_stop(struct udevice *dev)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ rtl8139_stop_common(priv);
+}
+
+static int rtl8139_send(struct udevice *dev, void *packet, int length)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = rtl8139_send_common(priv, packet, length);
+
+ return ret ? 0 : -ETIMEDOUT;
+}
+
+static int rtl8139_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+ static unsigned char rxdata[RX_BUF_LEN];
+
+ return rtl8139_recv_common(priv, rxdata, packetp);
+}
+
+static int rtl8139_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ rtl8139_free_pkt_common(priv, length);
+
+ return 0;
+}
+
+static int rtl8139_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+ rtl8139_reset(priv);
+
+ return 0;
+}
+
+static int rtl8139_read_rom_hwaddr(struct udevice *dev)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ rtl8139_get_hwaddr(priv);
+
+ return 0;
+}
+
+static int rtl8139_bind(struct udevice *dev)
+{
+ static int card_number;
+ char name[16];
+
+ rtl8139_name(name, card_number++);
+
+ return device_set_name(dev, name);
+}
+
+static int rtl8139_probe(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+ u32 iobase;
+
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
+ iobase &= ~0xf;
+
+ debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
+
+ priv->devno = dev;
+ priv->ioaddr = (unsigned long)bus_to_phys(dev, iobase);
+
+ rtl8139_get_hwaddr(priv);
+ memcpy(plat->enetaddr, priv->enetaddr, sizeof(priv->enetaddr));
+
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
+
+ return 0;
+}
+
+static const struct eth_ops rtl8139_ops = {
+ .start = rtl8139_start,
+ .send = rtl8139_send,
+ .recv = rtl8139_recv,
+ .stop = rtl8139_stop,
+ .free_pkt = rtl8139_free_pkt,
+ .write_hwaddr = rtl8139_write_hwaddr,
+ .read_rom_hwaddr = rtl8139_read_rom_hwaddr,
+};
+
+U_BOOT_DRIVER(eth_rtl8139) = {
+ .name = "eth_rtl8139",
+ .id = UCLASS_ETH,
+ .bind = rtl8139_bind,
+ .probe = rtl8139_probe,
+ .ops = &rtl8139_ops,
+ .priv_auto_alloc_size = sizeof(struct rtl8139_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
+#endif
/*_TBICSRBit*/
TBILinkOK = 0x02000000,
+
+ /* FuncEvent/Misc */
+ RxDv_Gated_En = 0x80000,
};
static struct {
return ret;
}
+ /*
+ * WAR for DHCP failure after rebooting from kernel.
+ * Clear RxDv_Gated_En bit which was set by kernel driver.
+ * Without this, U-Boot can't get an IP via DHCP.
+ * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
+ * the r8169.c kernel driver.
+ */
+
+ u32 val = RTL_R32(FuncEvent);
+ debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
+ val &= ~RxDv_Gated_En;
+ RTL_W32(FuncEvent, val);
+
return 0;
}
#include <cpsw.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
+#include <linux/compiler.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
}
#define DEFINE_ALE_FIELD(name, start, bits) \
-static inline int cpsw_ale_get_##name(u32 *ale_entry) \
+static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry) \
{ \
return cpsw_ale_get_field(ale_entry, start, bits); \
} \
-static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
+static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
{ \
cpsw_ale_set_field(ale_entry, start, bits, value); \
}
#include <linux/err.h>
#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT BIT(0)
+#define OMAP_USB2_DISABLE_CHG_DET BIT(1)
#define OMAP_DEV_PHY_PD BIT(0)
#define OMAP_USB2_PHY_PD BIT(28)
#define AM654_USB2_VBUS_DET_EN BIT(5)
#define AM654_USB2_VBUSVALID_DET_EN BIT(4)
+#define USB2PHY_CHRG_DET 0x14
+#define USB2PHY_USE_CHG_DET_REG BIT(29)
+#define USB2PHY_DIS_CHG_DET BIT(28)
+
DECLARE_GLOBAL_DATA_PTR;
struct omap_usb2_phy {
writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1);
}
+ if (priv->flags & OMAP_USB2_DISABLE_CHG_DET) {
+ val = readl(priv->phy_base + USB2PHY_CHRG_DET);
+ val |= USB2PHY_USE_CHG_DET_REG | USB2PHY_DIS_CHG_DET;
+ writel(val, priv->phy_base + USB2PHY_CHRG_DET);
+ }
+
return 0;
}
if (!data)
return -EINVAL;
- if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
- priv->phy_base = dev_read_addr_ptr(dev);
+ priv->phy_base = dev_read_addr_ptr(dev);
- if (!priv->phy_base)
- return -EINVAL;
+ if (!priv->phy_base)
+ return -EINVAL;
+
+ if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT)
priv->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
- }
+
+ /*
+ * AM654x PG1.0 has a silicon bug that D+ is pulled high after
+ * POR, which could cause enumeration failure with some USB hubs.
+ * Disabling the USB2_PHY Charger Detect function will put D+
+ * into the normal state.
+ *
+ * Using property "ti,dis-chg-det-quirk" in the DT usb2-phy node
+ * to enable this workaround for AM654x PG1.0.
+ */
+ if (dev_read_bool(dev, "ti,dis-chg-det-quirk"))
+ priv->flags |= OMAP_USB2_DISABLE_CHG_DET;
regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-phy-power");
if (!IS_ERR(regmap)) {
return usb_match_one_id_intf(desc, int_desc, id);
}
+static ofnode usb_get_ofnode(struct udevice *hub, int port)
+{
+ ofnode node;
+ u32 reg;
+
+ if (!dev_has_of_node(hub))
+ return ofnode_null();
+
+ /*
+ * The USB controller and its USB hub are two different udevices,
+ * but the device tree has only one node for both. Thus we are
+ * assigning this node to both udevices.
+ * If port is zero, the controller scans its root hub, thus we
+ * are using the same ofnode as the controller here.
+ */
+ if (!port)
+ return dev_ofnode(hub);
+
+ ofnode_for_each_subnode(node, dev_ofnode(hub)) {
+ if (ofnode_read_u32(node, "reg", ®))
+ continue;
+
+ if (reg == port)
+ return node;
+ }
+
+ return ofnode_null();
+}
+
/**
* usb_find_and_bind_driver() - Find and bind the right USB driver
*
static int usb_find_and_bind_driver(struct udevice *parent,
struct usb_device_descriptor *desc,
struct usb_interface_descriptor *iface,
- int bus_seq, int devnum,
+ int bus_seq, int devnum, int port,
struct udevice **devp)
{
struct usb_driver_entry *start, *entry;
int n_ents;
int ret;
char name[30], *str;
+ ofnode node = usb_get_ofnode(parent, port);
*devp = NULL;
debug("%s: Searching for driver\n", __func__);
* find another driver. For now this doesn't seem
* necesssary, so just bind the first match.
*/
- ret = device_bind(parent, drv, drv->name, NULL, -1,
- &dev);
+ ret = device_bind_ofnode(parent, drv, drv->name, NULL,
+ node, &dev);
if (ret)
goto error;
debug("%s: Match found: %s\n", __func__, drv->name);
if (ret) {
if (ret != -ENOENT)
return ret;
- ret = usb_find_and_bind_driver(parent, &udev->descriptor, iface,
+ ret = usb_find_and_bind_driver(parent, &udev->descriptor,
+ iface,
udev->controller_dev->seq,
- udev->devnum, &dev);
+ udev->devnum, port, &dev);
if (ret)
return ret;
created = true;
option compiles in the video uclass and routes all LCD/video access
through this.
+config BACKLIGHT
+ bool "Enable panel backlight uclass support"
+ depends on DM_VIDEO
+ default y
+ help
+ This provides backlight uclass driver that enables basic panel
+ backlight support.
+
config BACKLIGHT_PWM
bool "Generic PWM based Backlight Driver"
- depends on DM_VIDEO && DM_PWM
+ depends on BACKLIGHT && DM_PWM
default y
help
If you have a LCD backlight adjustable by PWM, say Y to enable
config BACKLIGHT_GPIO
bool "Generic GPIO based Backlight Driver"
- depends on DM_VIDEO
+ depends on BACKLIGHT
help
If you have a LCD backlight adjustable by GPIO, say Y to enable
this driver.
it understands the standard device tree
(leds/backlight/gpio-backlight.txt)
+config CMD_VIDCONSOLE
+ bool "Enable vidconsole commands lcdputs and setcurs"
+ depends on DM_VIDEO
+ default y
+ help
+ Enabling this will provide 'setcurs' and 'lcdputs' commands which
+ support cursor positioning and drawing strings on video framebuffer.
+
config VIDEO_BPP8
bool "Support 8-bit-per-pixel displays"
depends on DM_VIDEO
loads takes over the screen. This, for example, can be used to
keep splash image on screen until grub graphical boot menu starts.
+config PANEL
+ bool "Enable panel uclass support"
+ depends on DM_VIDEO
+ default y
+ help
+ This provides panel uclass driver that enables basic panel support.
+
+config SIMPLE_PANEL
+ bool "Enable simple panel support"
+ depends on PANEL
+ default y
+ help
+ This turns on a simple panel driver that enables a compatible
+ video panel.
+
source "drivers/video/fonts/Kconfig"
config VIDCONSOLE_AS_LCD
- bool "Use 'vidconsole' when 'lcd' is seen in stdout"
+ string "Use 'vidconsole' when string defined here is seen in stdout"
depends on DM_VIDEO
- help
- This is a work-around for boards which have 'lcd' in their stdout
- environment variable, but have moved to use driver model for video.
- In this case the console will no-longer work. While it is possible
- to update the environment, the breakage may be confusing for users.
- This option will be removed around the end of 2016.
+ default "lcd" if LCD || TEGRA_COMMON
+ default "vga" if !LCD
+ help
+ This is a work-around for boards which have 'lcd' or 'vga' in their
+ stdout environment variable, but have moved to use driver model for
+ video. In this case the console will no-longer work. While it is
+ possible to update the environment, the breakage may be confusing for
+ users. This option will be removed around the end of 2020.
config VIDEO_COREBOOT
bool "Enable coreboot framebuffer driver support"
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifdef CONFIG_DM
+obj-$(CONFIG_BACKLIGHT) += backlight-uclass.o
obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o
obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o
obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o
obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
obj-$(CONFIG_DISPLAY) += display-uclass.o
-obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
-obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
+obj-$(CONFIG_PANEL) += panel-uclass.o
+obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
endif
obj-${CONFIG_EXYNOS_FB} += exynos/
config VIDEO_IPUV3
bool "i.MX IPUv3 Core video support"
- depends on (VIDEO || DM_VIDEO) && (MX5 || MX6)
+ depends on DM_VIDEO && (MX5 || MX6)
help
This enables framebuffer driver for i.MX processors working
on the IPUv3(Image Processing Unit) internal graphic processor.
else
bg_chan = 0;
- if (!g_ipu_clk_enabled)
- clk_enable(g_ipu_clk);
-
if (bg_chan) {
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
- if (!g_ipu_clk_enabled)
- clk_disable(g_ipu_clk);
-
return 0;
}
(channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
return -EINVAL;
- if (!g_ipu_clk_enabled)
- clk_enable(g_ipu_clk);
-
color_key_4rgb = 1;
/* Transform color key from rgb to yuv if CSC is enabled */
if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
- if (!g_ipu_clk_enabled)
- clk_disable(g_ipu_clk);
-
return 0;
}
static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
-/* graphics setup */
-static GraphicDevice panel;
static struct fb_videomode const *gmode;
static uint8_t gdisp;
static uint32_t gpixfmt;
return pixfmt;
}
-/*
- * Set fixed framebuffer parameters based on variable settings.
- *
- * @param info framebuffer information pointer
- */
-static int mxcfb_set_fix(struct fb_info *info)
-{
- struct fb_fix_screeninfo *fix = &info->fix;
- struct fb_var_screeninfo *var = &info->var;
-
- fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
-
- fix->type = FB_TYPE_PACKED_PIXELS;
- fix->accel = FB_ACCEL_NONE;
- fix->visual = FB_VISUAL_TRUECOLOR;
- fix->xpanstep = 1;
- fix->ypanstep = 1;
-
- return 0;
-}
-
static int setup_disp_channel1(struct fb_info *fbi)
{
ipu_channel_params_t params;
ipu_disable_channel(mxc_fbi->ipu_ch);
ipu_uninit_channel(mxc_fbi->ipu_ch);
- mxcfb_set_fix(fbi);
mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
}
fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
-#if CONFIG_IS_ENABLED(DM_VIDEO)
fbi->screen_base = (char *)gd->video_bottom;
-#else
- fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
- fbi->fix.smem_len);
-#endif
fbi->fix.smem_start = (unsigned long)fbi->screen_base;
if (fbi->screen_base == 0) {
(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
fbi->screen_size = fbi->fix.smem_len;
-
-#if CONFIG_IS_ENABLED(VIDEO)
gd->fb_base = fbi->fix.smem_start;
-#endif
/* Clear the screen */
memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
return fbi;
}
+extern struct clk *g_ipu_clk;
+
/*
* Probe routine for the framebuffer driver. It is called during the
* driver binding process. The following functions are performed in
{
struct fb_info *fbi;
struct mxcfb_info *mxcfbi;
- int ret = 0;
/*
* Initialize FB structures
*/
fbi = mxcfb_init_fbinfo();
- if (!fbi) {
- ret = -ENOMEM;
- goto err0;
- }
+ if (!fbi)
+ return -ENOMEM;
+
mxcfbi = (struct mxcfb_info *)fbi->par;
if (!g_dp_in_use) {
mxcfbi->ipu_di = disp;
+ if (!ipu_clk_enabled())
+ clk_enable(g_ipu_clk);
+
ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);
- strcpy(fbi->fix.id, "DISP3 BG");
g_dp_in_use = 1;
mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
fb_videomode_to_var(&fbi->var, mode);
fbi->var.bits_per_pixel = 16;
- fbi->fix.line_length = fbi->var.xres * (fbi->var.bits_per_pixel / 8);
+ fbi->fix.line_length = fbi->var.xres_virtual *
+ (fbi->var.bits_per_pixel / 8);
fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length;
mxcfb_check_var(&fbi->var, fbi);
/* Default Y virtual size is 2x panel size */
fbi->var.yres_virtual = fbi->var.yres * 2;
- mxcfb_set_fix(fbi);
-
/* allocate fb first */
if (mxcfb_map_video_memory(fbi) < 0)
return -ENOMEM;
mxcfb_set_par(fbi);
- panel.winSizeX = mode->xres;
- panel.winSizeY = mode->yres;
- panel.plnSizeX = mode->xres;
- panel.plnSizeY = mode->yres;
-
- panel.frameAdrs = (u32)fbi->screen_base;
- panel.memSize = fbi->screen_size;
-
- panel.gdfBytesPP = 2;
- panel.gdfIndex = GDF_16BIT_565RGB;
-
+#ifdef DEBUG
ipu_dump_registers();
+#endif
return 0;
-
-err0:
- return ret;
}
void ipuv3_fb_shutdown(void)
}
}
-void *video_hw_init(void)
-{
- int ret;
-
- ret = ipu_probe();
- if (ret)
- puts("Error initializing IPU\n");
-
- ret = mxcfb_probe(gpixfmt, gdisp, gmode);
- debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs);
- gd->fb_base = panel.frameAdrs;
-
- return (void *)&panel;
-}
-
int ipuv3_fb_init(struct fb_videomode const *mode,
uint8_t disp,
uint32_t pixfmt)
return 0;
}
-#if CONFIG_IS_ENABLED(DM_VIDEO)
enum {
/* Maximum display size we support */
LCD_MAX_WIDTH = 1920,
#if defined(CONFIG_DISPLAY)
struct udevice *disp_dev;
#endif
- struct udevice *panel_dev;
u32 fb_start, fb_end;
int ret;
return ret;
}
#endif
- ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
- if (panel_dev)
- panel_enable_backlight(panel_dev);
+ if (CONFIG_IS_ENABLED(PANEL)) {
+ struct udevice *panel_dev;
+
+ ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
+ if (panel_dev)
+ panel_enable_backlight(panel_dev);
+ }
uc_priv->xsize = gmode->xres;
uc_priv->ysize = gmode->yres;
}
static const struct udevice_id ipuv3_video_ids[] = {
+#ifdef CONFIG_ARCH_MX6
{ .compatible = "fsl,imx6q-ipu" },
+#endif
+#ifdef CONFIG_ARCH_MX5
{ .compatible = "fsl,imx53-ipu" },
+#endif
{ }
};
.priv_auto_alloc_size = sizeof(struct ipuv3_video_priv),
.flags = DM_FLAG_PRE_RELOC,
};
-#endif /* CONFIG_DM_VIDEO */
.per_device_auto_alloc_size = sizeof(struct vidconsole_priv),
};
+#if CONFIG_IS_ENABLED(CMD_VIDCONSOLE)
void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned row)
{
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
"print string on video framebuffer",
" <string>"
);
+#endif /* CONFIG_IS_ENABLED(CMD_VIDCONSOLE) */
extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
extra-$(CONFIG_PPC) += sched
-ifndef CONFIG_DM_ETH
-extra-$(CONFIG_SMC911X) += smc911x_eeprom
-endif
-
#
# Some versions of make do not handle trailing white spaces properly;
# leading to build failures. The problem was found with GNU Make 3.80.
+++ /dev/null
-/*
- * smc911x_eeprom.c - EEPROM interface to SMC911x parts.
- * Only tested on SMSC9118 though ...
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Based on smc91111_eeprom.c which:
- * Heavily borrowed from the following peoples GPL'ed software:
- * - Wolfgang Denk, DENX Software Engineering, wd@denx.de
- * Das U-Boot
- * - Ladislav Michl ladis@linux-mips.org
- * A rejected patch on the U-Boot mailing list
- */
-
-#include <common.h>
-#include <console.h>
-#include <exports.h>
-#include <net.h>
-#include <linux/ctype.h>
-#include <linux/types.h>
-#include "../drivers/net/smc911x.h"
-
-#define DRIVERNAME "smc911x"
-
-#if defined (CONFIG_SMC911X_32_BIT) && \
- defined (CONFIG_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
- CONFIG_SMC911X_16_BIT shall be set"
-#endif
-
-struct chip_id {
- u16 id;
- char *name;
-};
-
-static const struct chip_id chip_ids[] = {
- { CHIP_89218, "LAN89218" },
- { CHIP_9115, "LAN9115" },
- { CHIP_9116, "LAN9116" },
- { CHIP_9117, "LAN9117" },
- { CHIP_9118, "LAN9118" },
- { CHIP_9211, "LAN9211" },
- { CHIP_9215, "LAN9215" },
- { CHIP_9216, "LAN9216" },
- { CHIP_9217, "LAN9217" },
- { CHIP_9218, "LAN9218" },
- { CHIP_9220, "LAN9220" },
- { CHIP_9221, "LAN9221" },
- { 0, NULL },
-};
-
-#if defined (CONFIG_SMC911X_32_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
- return *(volatile u32*)(dev->iobase + offset);
-}
-
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-{
- *(volatile u32*)(dev->iobase + offset) = val;
-}
-#elif defined (CONFIG_SMC911X_16_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
- return (*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16);
-}
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-{
- *(volatile u16 *)(dev->iobase + offset) = (u16)val;
- *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
-}
-#else
-#error "SMC911X: undefined bus width"
-#endif /* CONFIG_SMC911X_16_BIT */
-
-static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
-{
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
- smc911x_reg_write(dev, MAC_CSR_CMD,
- MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
-
- return smc911x_reg_read(dev, MAC_CSR_DATA);
-}
-
-static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
-{
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
- smc911x_reg_write(dev, MAC_CSR_DATA, data);
- smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
-}
-
-static int smc911x_detect_chip(struct eth_device *dev)
-{
- unsigned long val, i;
-
- val = smc911x_reg_read(dev, BYTE_TEST);
- if (val == 0xffffffff) {
- /* Special case -- no chip present */
- return -1;
- } else if (val != 0x87654321) {
- printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
- return -1;
- }
-
- val = smc911x_reg_read(dev, ID_REV) >> 16;
- for (i = 0; chip_ids[i].id != 0; i++) {
- if (chip_ids[i].id == val) break;
- }
- if (!chip_ids[i].id) {
- printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
- return -1;
- }
-
- dev->priv = (void *)&chip_ids[i];
-
- return 0;
-}
-
-static void smc911x_reset(struct eth_device *dev)
-{
- int timeout;
-
- /*
- * Take out of PM setting first
- * Device is already wake up if PMT_CTRL_READY bit is set
- */
- if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
- /* Write to the bytetest will take out of powerdown */
- smc911x_reg_write(dev, BYTE_TEST, 0x0);
-
- timeout = 10;
-
- while (timeout-- &&
- !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
- udelay(10);
- if (timeout < 0) {
- printf(DRIVERNAME
- ": timeout waiting for PM restore\n");
- return;
- }
- }
-
- /* Disable interrupts */
- smc911x_reg_write(dev, INT_EN, 0);
-
- smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
-
- timeout = 1000;
- while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
- udelay(10);
-
- if (timeout < 0) {
- printf(DRIVERNAME ": reset timeout\n");
- return;
- }
-
- /* Reset the FIFO level and flow control settings */
- smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
- smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
-
- /* Set to LED outputs */
- smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
-}
-
-/**
- * smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?)
- */
-static int smsc_ctrlc(void)
-{
- return (tstc() && getc() == 0x03);
-}
-
-/**
- * usage - dump usage information
- */
-static void usage(void)
-{
- puts(
- "MAC/EEPROM Commands:\n"
- " P : Print the MAC addresses\n"
- " D : Dump the EEPROM contents\n"
- " M : Dump the MAC contents\n"
- " C : Copy the MAC address from the EEPROM to the MAC\n"
- " W : Write a register in the EEPROM or in the MAC\n"
- " Q : Quit\n"
- "\n"
- "Some commands take arguments:\n"
- " W <E|M> <register> <value>\n"
- " E: EEPROM M: MAC\n"
- );
-}
-
-/**
- * dump_regs - dump the MAC registers
- *
- * Registers 0x00 - 0x50 are FIFOs. The 0x50+ are the control registers
- * and they're all 32bits long. 0xB8+ are reserved, so don't bother.
- */
-static void dump_regs(struct eth_device *dev)
-{
- u8 i, j = 0;
- for (i = 0x50; i < 0xB8; i += sizeof(u32))
- printf("%02x: 0x%08x %c", i,
- smc911x_reg_read(dev, i),
- (j++ % 2 ? '\n' : ' '));
-}
-
-/**
- * do_eeprom_cmd - handle eeprom communication
- */
-static int do_eeprom_cmd(struct eth_device *dev, int cmd, u8 reg)
-{
- if (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) {
- printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(dev, E2P_CMD));
- return -1;
- }
-
- smc911x_reg_write(dev, E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
-
- while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
- if (smsc_ctrlc()) {
- printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(dev, E2P_CMD));
- return -1;
- }
-
- return 0;
-}
-
-/**
- * read_eeprom_reg - read specified register in EEPROM
- */
-static u8 read_eeprom_reg(struct eth_device *dev, u8 reg)
-{
- int ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ, reg);
- return (ret ? : smc911x_reg_read(dev, E2P_DATA));
-}
-
-/**
- * write_eeprom_reg - write specified value into specified register in EEPROM
- */
-static int write_eeprom_reg(struct eth_device *dev, u8 value, u8 reg)
-{
- int ret;
-
- /* enable erasing/writing */
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN, reg);
- if (ret)
- goto done;
-
- /* erase the eeprom reg */
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE, reg);
- if (ret)
- goto done;
-
- /* write the eeprom reg */
- smc911x_reg_write(dev, E2P_DATA, value);
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE, reg);
- if (ret)
- goto done;
-
- /* disable erasing/writing */
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWDS, reg);
-
- done:
- return ret;
-}
-
-/**
- * skip_space - find first non-whitespace in given pointer
- */
-static char *skip_space(char *buf)
-{
- while (isblank(buf[0]))
- ++buf;
- return buf;
-}
-
-/**
- * write_stuff - handle writing of MAC registers / eeprom
- */
-static void write_stuff(struct eth_device *dev, char *line)
-{
- char dest;
- char *endp;
- u8 reg;
- u32 value;
-
- /* Skip over the "W " part of the command */
- line = skip_space(line + 1);
-
- /* Figure out destination */
- switch (line[0]) {
- case 'E':
- case 'M':
- dest = line[0];
- break;
- default:
- invalid_usage:
- printf("ERROR: Invalid write usage\n");
- usage();
- return;
- }
-
- /* Get the register to write */
- line = skip_space(line + 1);
- reg = simple_strtoul(line, &endp, 16);
- if (line == endp)
- goto invalid_usage;
-
- /* Get the value to write */
- line = skip_space(endp);
- value = simple_strtoul(line, &endp, 16);
- if (line == endp)
- goto invalid_usage;
-
- /* Check for trailing cruft */
- line = skip_space(endp);
- if (line[0])
- goto invalid_usage;
-
- /* Finally, execute the command */
- if (dest == 'E') {
- printf("Writing EEPROM register %02x with %02x\n", reg, value);
- write_eeprom_reg(dev, value, reg);
- } else {
- printf("Writing MAC register %02x with %08x\n", reg, value);
- smc911x_reg_write(dev, reg, value);
- }
-}
-
-/**
- * copy_from_eeprom - copy MAC address in eeprom to address registers
- */
-static void copy_from_eeprom(struct eth_device *dev)
-{
- ulong addrl =
- read_eeprom_reg(dev, 0x01) |
- read_eeprom_reg(dev, 0x02) << 8 |
- read_eeprom_reg(dev, 0x03) << 16 |
- read_eeprom_reg(dev, 0x04) << 24;
- ulong addrh =
- read_eeprom_reg(dev, 0x05) |
- read_eeprom_reg(dev, 0x06) << 8;
- smc911x_set_mac_csr(dev, ADDRL, addrl);
- smc911x_set_mac_csr(dev, ADDRH, addrh);
- puts("EEPROM contents copied to MAC\n");
-}
-
-/**
- * print_macaddr - print MAC address registers and MAC address in eeprom
- */
-static void print_macaddr(struct eth_device *dev)
-{
- puts("Current MAC Address in MAC: ");
- ulong addrl = smc911x_get_mac_csr(dev, ADDRL);
- ulong addrh = smc911x_get_mac_csr(dev, ADDRH);
- printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- (u8)(addrl), (u8)(addrl >> 8), (u8)(addrl >> 16),
- (u8)(addrl >> 24), (u8)(addrh), (u8)(addrh >> 8));
-
- puts("Current MAC Address in EEPROM: ");
- int i;
- for (i = 1; i < 6; ++i)
- printf("%02x:", read_eeprom_reg(dev, i));
- printf("%02x\n", read_eeprom_reg(dev, i));
-}
-
-/**
- * dump_eeprom - dump the whole content of the EEPROM
- */
-static void dump_eeprom(struct eth_device *dev)
-{
- int i;
- puts("EEPROM:\n");
- for (i = 0; i < 7; ++i)
- printf("%02x: 0x%02x\n", i, read_eeprom_reg(dev, i));
-}
-
-/**
- * smc911x_init - get the MAC/EEPROM up and ready for use
- */
-static int smc911x_init(struct eth_device *dev)
-{
- /* See if there is anything there */
- if (smc911x_detect_chip(dev))
- return 1;
-
- smc911x_reset(dev);
-
- /* Make sure we set EEDIO/EECLK to the EEPROM */
- if (smc911x_reg_read(dev, GPIO_CFG) & GPIO_CFG_EEPR_EN) {
- while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
- if (smsc_ctrlc()) {
- printf("init: timeout (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(dev, E2P_CMD));
- return 1;
- }
- smc911x_reg_write(dev, GPIO_CFG,
- smc911x_reg_read(dev, GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
- }
-
- return 0;
-}
-
-/**
- * getline - consume a line of input and handle some escape sequences
- */
-static char *getline(void)
-{
- static char buffer[100];
- char c;
- size_t i;
-
- i = 0;
- while (1) {
- buffer[i] = '\0';
- while (!tstc())
- continue;
-
- c = getc();
- /* Convert to uppercase */
- if (c >= 'a' && c <= 'z')
- c -= ('a' - 'A');
-
- switch (c) {
- case '\r': /* Enter/Return key */
- case '\n':
- puts("\n");
- return buffer;
-
- case 0x03: /* ^C - break */
- return NULL;
-
- case 0x5F:
- case 0x08: /* ^H - backspace */
- case 0x7F: /* DEL - backspace */
- if (i) {
- puts("\b \b");
- i--;
- }
- break;
-
- default:
- /* Ignore control characters */
- if (c < 0x20)
- break;
- /* Queue up all other characters */
- buffer[i++] = c;
- printf("%c", c);
- break;
- }
- }
-}
-
-/**
- * smc911x_eeprom - our application's main() function
- */
-int smc911x_eeprom(int argc, char *const argv[])
-{
- /* Avoid initializing on stack as gcc likes to call memset() */
- struct eth_device dev;
- dev.iobase = CONFIG_SMC911X_BASE;
-
- /* Print the ABI version */
- app_startup(argv);
- if (XF_VERSION != get_version()) {
- printf("Expects ABI version %d\n", XF_VERSION);
- printf("Actual U-Boot ABI version %lu\n", get_version());
- printf("Can't run\n\n");
- return 1;
- }
-
- /* Initialize the MAC/EEPROM somewhat */
- puts("\n");
- if (smc911x_init(&dev))
- return 1;
-
- /* Dump helpful usage information */
- puts("\n");
- usage();
- puts("\n");
-
- while (1) {
- char *line;
-
- /* Send the prompt and wait for a line */
- puts("eeprom> ");
- line = getline();
-
- /* Got a ctrl+c */
- if (!line)
- return 0;
-
- /* Eat leading space */
- line = skip_space(line);
-
- /* Empty line, try again */
- if (!line[0])
- continue;
-
- /* Only accept 1 letter commands */
- if (line[0] && line[1] && !isblank(line[1]))
- goto unknown_cmd;
-
- /* Now parse the command */
- switch (line[0]) {
- case 'W': write_stuff(&dev, line); break;
- case 'D': dump_eeprom(&dev); break;
- case 'M': dump_regs(&dev); break;
- case 'C': copy_from_eeprom(&dev); break;
- case 'P': print_macaddr(&dev); break;
- unknown_cmd:
- default: puts("ERROR: Unknown command!\n\n");
- case '?':
- case 'H': usage(); break;
- case 'Q': return 0;
- }
- }
-}
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */
-#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#endif
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#endif
#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
- "eth1addr=00:00:11:22:33:45\0" \
- "eth3addr=00:00:11:22:33:46\0" \
- "eth5addr=00:00:11:22:33:47\0" \
+ "eth3addr=00:00:11:22:33:45\0" \
+ "eth5addr=00:00:11:22:33:46\0" \
+ "eth6addr=00:00:11:22:33:47\0" \
"ipaddr=1.2.3.4\0"
#define MEM_LAYOUT_ENV_SETTINGS \
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
/* Framebuffer */
-#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#endif
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */
#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
"bootm 0x10800000 0x10d00000\0" \
"console=ttymxc0\0" \
"fan=gpio set 92\0" \
+ "fdt_addr=0x13000000\0" \
+ "fdt_addr_r=0x13000000\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "kernel_addr_r=0x10008000\0" \
+ "pxefile_addr_r=0x10008000\0" \
+ "ramdisk_addr_r=0x18000000\0" \
+ "scriptaddr=0x14000000\0" \
"set_con_serial=setenv stdout serial; " \
"setenv stderr serial\0" \
- "set_con_hdmi=setenv stdout serial,vga; " \
- "setenv stderr serial,vga\0" \
- "stderr=serial,vga\0" \
+ "set_con_hdmi=setenv stdout serial,vidconsole; " \
+ "setenv stderr serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0" \
"stdin=serial,usbkbd\0" \
- "stdout=serial,vga\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan; " \
- "if run bootcmd_up1; then " \
- "run bootcmd_up2; " \
- "else " \
- "run bootcmd_mmc; " \
- "fi"
+ "stdout=serial,vidconsole\0"
+
+/* Enable distro boot */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(SATA, sata, 0) \
+ func(USB, usb, 0)
+
+#include <config_distro_bootcmd.h>
#endif /* __TBS2910_CONFIG_H * */
static inline int dev_read_alias_highest_id(const char *stem)
{
+ if (!CONFIG_IS_ENABLED(OF_LIBFDT))
+ return -1;
return fdtdec_get_alias_highest_id(gd->fdt_blob, stem);
}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP4_H
+#define __DT_BINDINGS_CLK_OMAP4_H
+
+#define OMAP4_CLKCTRL_OFFSET 0x20
+#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
+
+/* mpuss clocks */
+#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* tesla clocks */
+#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
+
+/* l4_ao clocks */
+#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+
+/* l3_1 clocks */
+#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_2 clocks */
+#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+
+/* ducati clocks */
+#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_dma clocks */
+#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_emif clocks */
+#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+
+/* d2d clocks */
+#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l4_cfg clocks */
+#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+
+/* l3_instr clocks */
+#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+
+/* ivahd clocks */
+#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+
+/* iss clocks */
+#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+
+/* l3_dss clocks */
+#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_gfx clocks */
+#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_init clocks */
+#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0)
+#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
+
+/* l4_per clocks */
+#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0)
+#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8)
+#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0)
+#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8)
+#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0)
+#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0)
+#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8)
+#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100)
+#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108)
+#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120)
+#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128)
+#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138)
+#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140)
+#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
+#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150)
+#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
+#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
+
+/* l4_secure clocks */
+#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
+#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
+#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
+#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
+#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
+#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
+#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
+#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
+#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
+
+/* l4_wkup clocks */
+#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+
+/* emu_sys clocks */
+#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP5_H
+#define __DT_BINDINGS_CLK_OMAP5_H
+
+#define OMAP5_CLKCTRL_OFFSET 0x20
+#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dsp clocks */
+#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+
+/* l3main1 clocks */
+#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3main2 clocks */
+#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dma clocks */
+#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+
+/* l4cfg clocks */
+#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+
+/* l3instr clocks */
+#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+
+/* l4per clocks */
+#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
+#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
+#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
+#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
+#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
+#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
+#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
+#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
+#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
+#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
+#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
+#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
+#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
+#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
+#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
+#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
+#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
+#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
+#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
+#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
+#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
+
+/* l4_secure clocks */
+#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
+#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
+#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
+#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
+#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
+#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
+#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
+#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
+#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
+
+/* iva clocks */
+#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+
+/* dss clocks */
+#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* gpu clocks */
+#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3init clocks */
+#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
+#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
+#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
+#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+
+/* wkupaon clocks */
+#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+
+#endif
* Maximum digest size for all algorithms we support. Having this value
* avoids a malloc() or C99 local declaration in common/cmd_hash.c.
*/
+#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#define HASH_MAX_DIGEST_SIZE 64
+#else
#define HASH_MAX_DIGEST_SIZE 32
+#endif
enum {
HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1
#define CONFIG_FIT_ENABLE_SHA256_SUPPORT
+#define CONFIG_FIT_ENABLE_SHA384_SUPPORT
+#define CONFIG_FIT_ENABLE_SHA512_SUPPORT
#define CONFIG_SHA1
#define CONFIG_SHA256
+#define CONFIG_SHA384
+#define CONFIG_SHA512
#define IMAGE_ENABLE_IGNORE 0
#define IMAGE_INDENT_STRING ""
#define IMAGE_ENABLE_SHA256 0
#endif
+#if defined(CONFIG_FIT_ENABLE_SHA384_SUPPORT) || \
+ defined(CONFIG_SPL_SHA384_SUPPORT)
+#define IMAGE_ENABLE_SHA384 1
+#else
+#define IMAGE_ENABLE_SHA384 0
+#endif
+
+#if defined(CONFIG_FIT_ENABLE_SHA512_SUPPORT) || \
+ defined(CONFIG_SPL_SHA512_SUPPORT)
+#define IMAGE_ENABLE_SHA512 1
+#else
+#define IMAGE_ENABLE_SHA512 0
+#endif
+
#endif /* IMAGE_ENABLE_FIT */
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
*/
int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len);
-/* get a random source port */
-unsigned int random_port(void);
-
/**
* update_tftp - Update firmware over TFTP (via DFU)
*
int asym_pause;
};
+/**
+ * phy_read - Convenience function for reading a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to read
+ * @return: value for success or negative errno for failure
+ */
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
struct mii_dev *bus = phydev->bus;
return bus->read(bus, phydev->addr, devad, regnum);
}
+/**
+ * phy_write - Convenience function for writing a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @val: value to write to @regnum
+ * @return: 0 for success or negative errno for failure
+ */
static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
u16 val)
{
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+/**
+ * phy_mmd_start_indirect - Convenience function for writing MMD registers
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @return: None
+ */
static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
int regnum)
{
(devad | MII_MMD_CTRL_NOINCR));
}
+/**
+ * phy_read_mmd - Convenience function for reading a register
+ * from an MMD on a given PHY.
+ * @phydev: The phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: The register on the MMD to read
+ * @return: Value for success or negative errno for failure
+ */
static inline int phy_read_mmd(struct phy_device *phydev, int devad,
int regnum)
{
return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
}
+/**
+ * phy_write_mmd - Convenience function for writing a register
+ * on an MMD on a given PHY.
+ * @phydev: The phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: The register on the MMD to read
+ * @val: value to write to @regnum
+ * @return: 0 for success or negative errno for failure
+ */
static inline int phy_write_mmd(struct phy_device *phydev, int devad,
int regnum, u16 val)
{
return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
}
+/**
+ * phy_set_bits_mmd - Convenience function for setting bits in a register
+ * on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @val: bits to set
+ * @return: 0 for success or negative errno for failure
+ */
+static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
+ u32 regnum, u16 val)
+{
+ int value, ret;
+
+ value = phy_read_mmd(phydev, devad, regnum);
+ if (value < 0)
+ return value;
+
+ value |= val;
+
+ ret = phy_write_mmd(phydev, devad, regnum, value);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * phy_clear_bits_mmd - Convenience function for clearing bits in a register
+ * on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @val: bits to clear
+ * @return: 0 for success or negative errno for failure
+ */
+static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
+ u32 regnum, u16 val)
+{
+ int value, ret;
+
+ value = phy_read_mmd(phydev, devad, regnum);
+ if (value < 0)
+ return value;
+
+ value &= ~val;
+
+ ret = phy_write_mmd(phydev, devad, regnum, value);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
/**
* phy_init() - Initializes the PHY drivers
- *
* This function registers all available PHY drivers
*
- * @return 0 if OK, -ve on error
+ * @return: 0 if OK, -ve on error
*/
int phy_init(void);
/**
* phy_reset() - Resets the specified PHY
- *
* Issues a reset of the PHY and waits for it to complete
*
* @phydev: PHY to reset
- * @return 0 if OK, -ve on error
+ * @return: 0 if OK, -ve on error
*/
int phy_reset(struct phy_device *phydev);
/**
* phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
- *
* The function checks the PHY addresses flagged in phy_mask and returns a
* phy_device pointer if it detects a PHY.
* This function should only be called if just one PHY is expected to be present
* @bus: MII/MDIO bus to scan
* @phy_mask: bitmap of PYH addresses to scan
* @interface: type of MAC-PHY interface
- * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ * @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
phy_interface_t interface);
/**
* phy_connect() - Creates a PHY device for the Ethernet interface
- *
* Creates a PHY device for the PHY at the given address, if one doesn't exist
* already, and associates it with the Ethernet device.
* The function may be called with addr <= 0, in this case addr value is ignored
* @addr: PHY address on MDIO bus
* @dev: Ethernet device to associate to the PHY
* @interface: type of MAC-PHY interface
- * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ * @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
/**
* phy_connect() - Creates a PHY device for the Ethernet interface
- *
* Creates a PHY device for the PHY at the given address, if one doesn't exist
* already, and associates it with the Ethernet device.
* The function may be called with addr <= 0, in this case addr value is ignored
* @addr: PHY address on MDIO bus
* @dev: Ethernet device to associate to the PHY
* @interface: type of MAC-PHY interface
- * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ * @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
* phy_get_interface_by_name() - Look up a PHY interface name
*
* @str: PHY interface name, e.g. "mii"
- * @return PHY_INTERFACE_MODE_... value, or -1 if not found
+ * @return: PHY_INTERFACE_MODE_... value, or -1 if not found
*/
int phy_get_interface_by_name(const char *str);
* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
* is RGMII (all variants)
* @phydev: the phy_device struct
+ * @return: true if MII bus is RGMII or false if it is not
*/
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
* is SGMII (all variants)
* @phydev: the phy_device struct
+ * @return: true if MII bus is SGMII or false if it is not
*/
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
#include <image.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
/**
* hash_calculate() - Calculate hash over the data
--- /dev/null
+#ifndef _SHA512_H
+#define _SHA512_H
+
+#define SHA384_SUM_LEN 48
+#define SHA384_DER_LEN 19
+#define SHA512_SUM_LEN 64
+#define SHA512_DER_LEN 19
+#define SHA512_BLOCK_SIZE 128
+
+#define CHUNKSZ_SHA384 (16 * 1024)
+#define CHUNKSZ_SHA512 (16 * 1024)
+
+typedef struct {
+ uint64_t state[SHA512_SUM_LEN / 8];
+ uint64_t count[2];
+ uint8_t buf[SHA512_BLOCK_SIZE];
+} sha512_context;
+
+extern const uint8_t sha512_der_prefix[];
+
+void sha512_starts(sha512_context * ctx);
+void sha512_update(sha512_context *ctx, const uint8_t *input, uint32_t length);
+void sha512_finish(sha512_context * ctx, uint8_t digest[SHA512_SUM_LEN]);
+
+void sha512_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz);
+
+extern const uint8_t sha384_der_prefix[];
+
+void sha384_starts(sha512_context * ctx);
+void sha384_update(sha512_context *ctx, const uint8_t *input, uint32_t length);
+void sha384_finish(sha512_context * ctx, uint8_t digest[SHA384_SUM_LEN]);
+
+void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz);
+
+
+#endif /* _SHA512_H */
The SHA256 algorithm produces a 256-bit (32-byte) hash value
(digest).
+config SHA512_ALGO
+ bool "Enable SHA512 algorithm"
+ help
+ This option enables support of internal SHA512 algorithm.
+
+config SHA512
+ bool "Enable SHA512 support"
+ depends on SHA512_ALGO
+ help
+ This option enables support of hashing using SHA512 algorithm.
+ The hash is calculated in software.
+ The SHA512 algorithm produces a 512-bit (64-byte) hash value
+ (digest).
+
+config SHA384
+ bool "Enable SHA384 support"
+ depends on SHA512_ALGO
+ help
+ This option enables support of hashing using SHA384 algorithm.
+ The hash is calculated in software.
+ The SHA384 algorithm produces a 384-bit (48-byte) hash value
+ (digest).
+
config SHA_HW_ACCEL
bool "Enable hashing using hardware"
help
obj-$(CONFIG_$(SPL_)RSA) += rsa/
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SHA256) += sha256.o
+obj-$(CONFIG_SHA512_ALGO) += sha512.o
obj-$(CONFIG_$(SPL_)ZLIB) += zlib/
obj-$(CONFIG_$(SPL_)ZSTD) += zstd/
/* find a matching node and return the phandle to that */
fdt_for_each_subnode(node, blob, parent) {
const char *name = fdt_get_name(blob, node, NULL);
- phys_addr_t addr, size;
+ fdt_addr_t addr;
+ fdt_size_t size;
- addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+ addr = fdtdec_get_addr_size_fixed(blob, node, "reg", 0, na, ns,
+ &size, false);
if (addr == FDT_ADDR_T_NONE) {
debug("failed to read address/size for %s\n", name);
continue;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * FIPS-180-2 compliant SHA-512 and SHA-384 implementation
+ *
+ * SHA-512 code by Jean-Luc Cooke <jlcooke@certainkey.com>
+ *
+ * Copyright (c) Jean-Luc Cooke <jlcooke@certainkey.com>
+ * Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
+ * Copyright (c) 2003 Kyle McMartin <kyle@debian.org>
+ * Copyright (c) 2020 Reuben Dowle <reuben.dowle@4rf.com>
+ */
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <linux/string.h>
+#else
+#include <string.h>
+#endif /* USE_HOSTCC */
+#include <watchdog.h>
+#include <u-boot/sha512.h>
+
+const uint8_t sha384_der_prefix[SHA384_DER_LEN] = {
+ 0x30, 0x41, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+ 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05,
+ 0x00, 0x04, 0x30
+};
+
+const uint8_t sha512_der_prefix[SHA512_DER_LEN] = {
+ 0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+ 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05,
+ 0x00, 0x04, 0x40
+};
+
+#define SHA384_H0 0xcbbb9d5dc1059ed8ULL
+#define SHA384_H1 0x629a292a367cd507ULL
+#define SHA384_H2 0x9159015a3070dd17ULL
+#define SHA384_H3 0x152fecd8f70e5939ULL
+#define SHA384_H4 0x67332667ffc00b31ULL
+#define SHA384_H5 0x8eb44a8768581511ULL
+#define SHA384_H6 0xdb0c2e0d64f98fa7ULL
+#define SHA384_H7 0x47b5481dbefa4fa4ULL
+
+#define SHA512_H0 0x6a09e667f3bcc908ULL
+#define SHA512_H1 0xbb67ae8584caa73bULL
+#define SHA512_H2 0x3c6ef372fe94f82bULL
+#define SHA512_H3 0xa54ff53a5f1d36f1ULL
+#define SHA512_H4 0x510e527fade682d1ULL
+#define SHA512_H5 0x9b05688c2b3e6c1fULL
+#define SHA512_H6 0x1f83d9abfb41bd6bULL
+#define SHA512_H7 0x5be0cd19137e2179ULL
+
+static inline uint64_t Ch(uint64_t x, uint64_t y, uint64_t z)
+{
+ return z ^ (x & (y ^ z));
+}
+
+static inline uint64_t Maj(uint64_t x, uint64_t y, uint64_t z)
+{
+ return (x & y) | (z & (x | y));
+}
+
+static const uint64_t sha512_K[80] = {
+ 0x428a2f98d728ae22ULL, 0x7137449123ef65cdULL, 0xb5c0fbcfec4d3b2fULL,
+ 0xe9b5dba58189dbbcULL, 0x3956c25bf348b538ULL, 0x59f111f1b605d019ULL,
+ 0x923f82a4af194f9bULL, 0xab1c5ed5da6d8118ULL, 0xd807aa98a3030242ULL,
+ 0x12835b0145706fbeULL, 0x243185be4ee4b28cULL, 0x550c7dc3d5ffb4e2ULL,
+ 0x72be5d74f27b896fULL, 0x80deb1fe3b1696b1ULL, 0x9bdc06a725c71235ULL,
+ 0xc19bf174cf692694ULL, 0xe49b69c19ef14ad2ULL, 0xefbe4786384f25e3ULL,
+ 0x0fc19dc68b8cd5b5ULL, 0x240ca1cc77ac9c65ULL, 0x2de92c6f592b0275ULL,
+ 0x4a7484aa6ea6e483ULL, 0x5cb0a9dcbd41fbd4ULL, 0x76f988da831153b5ULL,
+ 0x983e5152ee66dfabULL, 0xa831c66d2db43210ULL, 0xb00327c898fb213fULL,
+ 0xbf597fc7beef0ee4ULL, 0xc6e00bf33da88fc2ULL, 0xd5a79147930aa725ULL,
+ 0x06ca6351e003826fULL, 0x142929670a0e6e70ULL, 0x27b70a8546d22ffcULL,
+ 0x2e1b21385c26c926ULL, 0x4d2c6dfc5ac42aedULL, 0x53380d139d95b3dfULL,
+ 0x650a73548baf63deULL, 0x766a0abb3c77b2a8ULL, 0x81c2c92e47edaee6ULL,
+ 0x92722c851482353bULL, 0xa2bfe8a14cf10364ULL, 0xa81a664bbc423001ULL,
+ 0xc24b8b70d0f89791ULL, 0xc76c51a30654be30ULL, 0xd192e819d6ef5218ULL,
+ 0xd69906245565a910ULL, 0xf40e35855771202aULL, 0x106aa07032bbd1b8ULL,
+ 0x19a4c116b8d2d0c8ULL, 0x1e376c085141ab53ULL, 0x2748774cdf8eeb99ULL,
+ 0x34b0bcb5e19b48a8ULL, 0x391c0cb3c5c95a63ULL, 0x4ed8aa4ae3418acbULL,
+ 0x5b9cca4f7763e373ULL, 0x682e6ff3d6b2b8a3ULL, 0x748f82ee5defb2fcULL,
+ 0x78a5636f43172f60ULL, 0x84c87814a1f0ab72ULL, 0x8cc702081a6439ecULL,
+ 0x90befffa23631e28ULL, 0xa4506cebde82bde9ULL, 0xbef9a3f7b2c67915ULL,
+ 0xc67178f2e372532bULL, 0xca273eceea26619cULL, 0xd186b8c721c0c207ULL,
+ 0xeada7dd6cde0eb1eULL, 0xf57d4f7fee6ed178ULL, 0x06f067aa72176fbaULL,
+ 0x0a637dc5a2c898a6ULL, 0x113f9804bef90daeULL, 0x1b710b35131c471bULL,
+ 0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, 0x3c9ebe0a15c9bebcULL,
+ 0x431d67c49c100d4cULL, 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL,
+ 0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL,
+};
+
+static inline uint64_t ror64(uint64_t word, unsigned int shift)
+{
+ return (word >> (shift & 63)) | (word << ((-shift) & 63));
+}
+
+#define e0(x) (ror64(x,28) ^ ror64(x,34) ^ ror64(x,39))
+#define e1(x) (ror64(x,14) ^ ror64(x,18) ^ ror64(x,41))
+#define s0(x) (ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7))
+#define s1(x) (ror64(x,19) ^ ror64(x,61) ^ (x >> 6))
+
+/*
+ * 64-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_UINT64_BE
+#define GET_UINT64_BE(n,b,i) { \
+ (n) = ( (unsigned long long) (b)[(i) ] << 56 ) \
+ | ( (unsigned long long) (b)[(i) + 1] << 48 ) \
+ | ( (unsigned long long) (b)[(i) + 2] << 40 ) \
+ | ( (unsigned long long) (b)[(i) + 3] << 32 ) \
+ | ( (unsigned long long) (b)[(i) + 4] << 24 ) \
+ | ( (unsigned long long) (b)[(i) + 5] << 16 ) \
+ | ( (unsigned long long) (b)[(i) + 6] << 8 ) \
+ | ( (unsigned long long) (b)[(i) + 7] ); \
+}
+#endif
+#ifndef PUT_UINT64_BE
+#define PUT_UINT64_BE(n,b,i) { \
+ (b)[(i) ] = (unsigned char) ( (n) >> 56 ); \
+ (b)[(i) + 1] = (unsigned char) ( (n) >> 48 ); \
+ (b)[(i) + 2] = (unsigned char) ( (n) >> 40 ); \
+ (b)[(i) + 3] = (unsigned char) ( (n) >> 32 ); \
+ (b)[(i) + 4] = (unsigned char) ( (n) >> 24 ); \
+ (b)[(i) + 5] = (unsigned char) ( (n) >> 16 ); \
+ (b)[(i) + 6] = (unsigned char) ( (n) >> 8 ); \
+ (b)[(i) + 7] = (unsigned char) ( (n) ); \
+}
+#endif
+
+static inline void LOAD_OP(int I, uint64_t *W, const uint8_t *input)
+{
+ GET_UINT64_BE(W[I], input, I*8);
+}
+
+static inline void BLEND_OP(int I, uint64_t *W)
+{
+ W[I & 15] += s1(W[(I-2) & 15]) + W[(I-7) & 15] + s0(W[(I-15) & 15]);
+}
+
+static void
+sha512_transform(uint64_t *state, const uint8_t *input)
+{
+ uint64_t a, b, c, d, e, f, g, h, t1, t2;
+
+ int i;
+ uint64_t W[16];
+
+ /* load the state into our registers */
+ a=state[0]; b=state[1]; c=state[2]; d=state[3];
+ e=state[4]; f=state[5]; g=state[6]; h=state[7];
+
+ /* now iterate */
+ for (i=0; i<80; i+=8) {
+ if (!(i & 8)) {
+ int j;
+
+ if (i < 16) {
+ /* load the input */
+ for (j = 0; j < 16; j++)
+ LOAD_OP(i + j, W, input);
+ } else {
+ for (j = 0; j < 16; j++) {
+ BLEND_OP(i + j, W);
+ }
+ }
+ }
+
+ t1 = h + e1(e) + Ch(e,f,g) + sha512_K[i ] + W[(i & 15)];
+ t2 = e0(a) + Maj(a,b,c); d+=t1; h=t1+t2;
+ t1 = g + e1(d) + Ch(d,e,f) + sha512_K[i+1] + W[(i & 15) + 1];
+ t2 = e0(h) + Maj(h,a,b); c+=t1; g=t1+t2;
+ t1 = f + e1(c) + Ch(c,d,e) + sha512_K[i+2] + W[(i & 15) + 2];
+ t2 = e0(g) + Maj(g,h,a); b+=t1; f=t1+t2;
+ t1 = e + e1(b) + Ch(b,c,d) + sha512_K[i+3] + W[(i & 15) + 3];
+ t2 = e0(f) + Maj(f,g,h); a+=t1; e=t1+t2;
+ t1 = d + e1(a) + Ch(a,b,c) + sha512_K[i+4] + W[(i & 15) + 4];
+ t2 = e0(e) + Maj(e,f,g); h+=t1; d=t1+t2;
+ t1 = c + e1(h) + Ch(h,a,b) + sha512_K[i+5] + W[(i & 15) + 5];
+ t2 = e0(d) + Maj(d,e,f); g+=t1; c=t1+t2;
+ t1 = b + e1(g) + Ch(g,h,a) + sha512_K[i+6] + W[(i & 15) + 6];
+ t2 = e0(c) + Maj(c,d,e); f+=t1; b=t1+t2;
+ t1 = a + e1(f) + Ch(f,g,h) + sha512_K[i+7] + W[(i & 15) + 7];
+ t2 = e0(b) + Maj(b,c,d); e+=t1; a=t1+t2;
+ }
+
+ state[0] += a; state[1] += b; state[2] += c; state[3] += d;
+ state[4] += e; state[5] += f; state[6] += g; state[7] += h;
+
+ /* erase our data */
+ a = b = c = d = e = f = g = h = t1 = t2 = 0;
+}
+
+static void sha512_block_fn(sha512_context *sst, const uint8_t *src,
+ int blocks)
+{
+ while (blocks--) {
+ sha512_transform(sst->state, src);
+ src += SHA512_BLOCK_SIZE;
+ }
+}
+
+static void sha512_base_do_update(sha512_context *sctx,
+ const uint8_t *data,
+ unsigned int len)
+{
+ unsigned int partial = sctx->count[0] % SHA512_BLOCK_SIZE;
+
+ sctx->count[0] += len;
+ if (sctx->count[0] < len)
+ sctx->count[1]++;
+
+ if (unlikely((partial + len) >= SHA512_BLOCK_SIZE)) {
+ int blocks;
+
+ if (partial) {
+ int p = SHA512_BLOCK_SIZE - partial;
+
+ memcpy(sctx->buf + partial, data, p);
+ data += p;
+ len -= p;
+
+ sha512_block_fn(sctx, sctx->buf, 1);
+ }
+
+ blocks = len / SHA512_BLOCK_SIZE;
+ len %= SHA512_BLOCK_SIZE;
+
+ if (blocks) {
+ sha512_block_fn(sctx, data, blocks);
+ data += blocks * SHA512_BLOCK_SIZE;
+ }
+ partial = 0;
+ }
+ if (len)
+ memcpy(sctx->buf + partial, data, len);
+}
+
+static void sha512_base_do_finalize(sha512_context *sctx)
+{
+ const int bit_offset = SHA512_BLOCK_SIZE - sizeof(uint64_t[2]);
+ uint64_t *bits = (uint64_t *)(sctx->buf + bit_offset);
+ unsigned int partial = sctx->count[0] % SHA512_BLOCK_SIZE;
+
+ sctx->buf[partial++] = 0x80;
+ if (partial > bit_offset) {
+ memset(sctx->buf + partial, 0x0, SHA512_BLOCK_SIZE - partial);
+ partial = 0;
+
+ sha512_block_fn(sctx, sctx->buf, 1);
+ }
+
+ memset(sctx->buf + partial, 0x0, bit_offset - partial);
+ bits[0] = cpu_to_be64(sctx->count[1] << 3 | sctx->count[0] >> 61);
+ bits[1] = cpu_to_be64(sctx->count[0] << 3);
+ sha512_block_fn(sctx, sctx->buf, 1);
+}
+
+#if defined(CONFIG_SHA384)
+void sha384_starts(sha512_context * ctx)
+{
+ ctx->state[0] = SHA384_H0;
+ ctx->state[1] = SHA384_H1;
+ ctx->state[2] = SHA384_H2;
+ ctx->state[3] = SHA384_H3;
+ ctx->state[4] = SHA384_H4;
+ ctx->state[5] = SHA384_H5;
+ ctx->state[6] = SHA384_H6;
+ ctx->state[7] = SHA384_H7;
+ ctx->count[0] = ctx->count[1] = 0;
+}
+
+void sha384_update(sha512_context *ctx, const uint8_t *input, uint32_t length)
+{
+ sha512_base_do_update(ctx, input, length);
+}
+
+void sha384_finish(sha512_context * ctx, uint8_t digest[SHA384_SUM_LEN])
+{
+ int i;
+
+ sha512_base_do_finalize(ctx);
+ for(i=0; i<SHA384_SUM_LEN / sizeof(uint64_t); i++)
+ PUT_UINT64_BE(ctx->state[i], digest, i * 8);
+}
+
+/*
+ * Output = SHA-512( input buffer ). Trigger the watchdog every 'chunk_sz'
+ * bytes of input processed.
+ */
+void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz)
+{
+ sha512_context ctx;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ const unsigned char *end;
+ unsigned char *curr;
+ int chunk;
+#endif
+
+ sha384_starts(&ctx);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ curr = (unsigned char *)input;
+ end = input + ilen;
+ while (curr < end) {
+ chunk = end - curr;
+ if (chunk > chunk_sz)
+ chunk = chunk_sz;
+ sha384_update(&ctx, curr, chunk);
+ curr += chunk;
+ WATCHDOG_RESET();
+ }
+#else
+ sha384_update(&ctx, input, ilen);
+#endif
+
+ sha384_finish(&ctx, output);
+}
+
+#endif
+
+#if defined(CONFIG_SHA512)
+void sha512_starts(sha512_context * ctx)
+{
+ ctx->state[0] = SHA512_H0;
+ ctx->state[1] = SHA512_H1;
+ ctx->state[2] = SHA512_H2;
+ ctx->state[3] = SHA512_H3;
+ ctx->state[4] = SHA512_H4;
+ ctx->state[5] = SHA512_H5;
+ ctx->state[6] = SHA512_H6;
+ ctx->state[7] = SHA512_H7;
+ ctx->count[0] = ctx->count[1] = 0;
+}
+
+void sha512_update(sha512_context *ctx, const uint8_t *input, uint32_t length)
+{
+ sha512_base_do_update(ctx, input, length);
+}
+
+void sha512_finish(sha512_context * ctx, uint8_t digest[SHA512_SUM_LEN])
+{
+ int i;
+
+ sha512_base_do_finalize(ctx);
+ for(i=0; i<SHA512_SUM_LEN / sizeof(uint64_t); i++)
+ PUT_UINT64_BE(ctx->state[i], digest, i * 8);
+}
+
+/*
+ * Output = SHA-512( input buffer ). Trigger the watchdog every 'chunk_sz'
+ * bytes of input processed.
+ */
+void sha512_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz)
+{
+ sha512_context ctx;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ const unsigned char *end;
+ unsigned char *curr;
+ int chunk;
+#endif
+
+ sha512_starts(&ctx);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ curr = (unsigned char *)input;
+ end = input + ilen;
+ while (curr < end) {
+ chunk = end - curr;
+ if (chunk > chunk_sz)
+ chunk = chunk_sz;
+ sha512_update(&ctx, curr, chunk);
+ curr += chunk;
+ WATCHDOG_RESET();
+ }
+#else
+ sha512_update(&ctx, input, ilen);
+#endif
+
+ sha512_finish(&ctx, output);
+}
+#endif
static int dns_our_port;
+/*
+ * make port a little random (1024-17407)
+ * This keeps the math somewhat trivial to compute, and seems to work with
+ * all supported protocols/clients/servers
+ */
+static unsigned int random_port(void)
+{
+ return 1024 + (get_timer(0) % 0x4000);
+}
+
static void dns_send(void)
{
struct header *header;
net_dev_exists = 1;
net_boot_file_size = 0;
switch (protocol) {
+#ifdef CONFIG_CMD_TFTPBOOT
case TFTPGET:
#ifdef CONFIG_CMD_TFTPPUT
case TFTPPUT:
/* always use ARP to get server ethernet address */
tftp_start(protocol);
break;
+#endif
#ifdef CONFIG_CMD_TFTPSRV
case TFTPSRV:
tftp_start_server();
dhcp_request(); /* Basically same as BOOTP */
break;
#endif
-
+#if defined(CONFIG_CMD_BOOTP)
case BOOTP:
bootp_reset();
net_ip.s_addr = 0;
bootp_request();
break;
-
+#endif
#if defined(CONFIG_CMD_RARP)
case RARP:
rarp_try = 0;
return 1;
}
-#if defined(CONFIG_CMD_NFS) || \
- defined(CONFIG_CMD_SNTP) || \
- defined(CONFIG_CMD_DNS)
-/*
- * make port a little random (1024-17407)
- * This keeps the math somewhat trivial to compute, and seems to work with
- * all supported protocols/clients/servers
- */
-unsigned int random_port(void)
-{
- return 1024 + (get_timer(0) % 0x4000);
-}
-#endif
-
void ip_to_string(struct in_addr x, char *s)
{
x.s_addr = ntohl(x.s_addr);
TFTP_ERR_UNEXPECTED_OPCODE = 4,
TFTP_ERR_UNKNOWN_TRANSFER_ID = 5,
TFTP_ERR_FILE_ALREADY_EXISTS = 6,
+ TFTP_ERR_OPTION_NEGOTIATION = 8,
};
static struct in_addr tftp_remote_ip;
#define STATE_OACK 5
#define STATE_RECV_WRQ 6
#define STATE_SEND_WRQ 7
+#define STATE_INVALID_OPTION 8
/* default TFTP block size */
#define TFTP_BLOCK_SIZE 512
static void show_block_marker(void)
{
+ ulong pos;
+
#ifdef CONFIG_TFTP_TSIZE
if (tftp_tsize) {
- ulong pos = tftp_cur_block * tftp_block_size +
+ pos = tftp_cur_block * tftp_block_size +
tftp_block_wrap_offset;
if (pos > tftp_tsize)
pos = tftp_tsize;
} else
#endif
{
- if (((tftp_cur_block - 1) % 10) == 0)
+ pos = (tftp_cur_block - 1) +
+ (tftp_block_wrap * TFTP_SEQUENCE_SIZE);
+ if ((pos % 10) == 0)
putc('#');
- else if ((tftp_cur_block % (10 * HASHES_PER_LINE)) == 0)
+ else if (((pos + 1) % (10 * HASHES_PER_LINE)) == 0)
puts("\n\t ");
}
}
tftp_block_wrap++;
tftp_block_wrap_offset += tftp_block_size * TFTP_SEQUENCE_SIZE;
timeout_count = 0; /* we've done well, reset the timeout */
- } else {
- show_block_marker();
}
+ show_block_marker();
}
/* The TFTP get or put is complete */
uchar *xp;
int len = 0;
ushort *s;
+ bool err_pkt = false;
/*
* We will always be sending some sort of packet, so
strcpy((char *)pkt, "File too large");
pkt += 14 /*strlen("File too large")*/ + 1;
len = pkt - xp;
+ err_pkt = true;
break;
case STATE_BAD_MAGIC:
strcpy((char *)pkt, "File has bad magic");
pkt += 18 /*strlen("File has bad magic")*/ + 1;
len = pkt - xp;
+ err_pkt = true;
+ break;
+
+ case STATE_INVALID_OPTION:
+ xp = pkt;
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ERROR);
+ *s++ = htons(TFTP_ERR_OPTION_NEGOTIATION);
+ pkt = (uchar *)s;
+ strcpy((char *)pkt, "Option Negotiation Failed");
+ /* strlen("Option Negotiation Failed") + NULL*/
+ pkt += 25 + 1;
+ len = pkt - xp;
+ err_pkt = true;
break;
}
net_send_udp_packet(net_server_ethaddr, tftp_remote_ip,
tftp_remote_port, tftp_our_port, len);
+
+ if (err_pkt)
+ net_set_state(NETLOOP_FAIL);
}
#ifdef CONFIG_CMD_TFTPPUT
__be16 proto;
__be16 *s;
int i;
+ u16 timeout_val_rcvd;
if (dest != tftp_our_port) {
return;
#endif
case TFTP_OACK:
- debug("Got OACK: %s %s\n",
- pkt, pkt + strlen((char *)pkt) + 1);
+ debug("Got OACK: ");
+ for (i = 0; i < len; i++) {
+ if (pkt[i] == '\0')
+ debug(" ");
+ else
+ debug("%c", pkt[i]);
+ }
+ debug("\n");
tftp_state = STATE_OACK;
tftp_remote_port = src;
/*
* something like "len-8" may give a *huge* number
*/
for (i = 0; i+8 < len; i++) {
- if (strcmp((char *)pkt + i, "blksize") == 0) {
+ if (strcasecmp((char *)pkt + i, "blksize") == 0) {
tftp_block_size = (unsigned short)
simple_strtoul((char *)pkt + i + 8,
NULL, 10);
- debug("Blocksize ack: %s, %d\n",
+ debug("Blocksize oack: %s, %d\n",
(char *)pkt + i + 8, tftp_block_size);
+ if (tftp_block_size > tftp_block_size_option) {
+ printf("Invalid blk size(=%d)\n",
+ tftp_block_size);
+ tftp_state = STATE_INVALID_OPTION;
+ }
+ }
+ if (strcasecmp((char *)pkt + i, "timeout") == 0) {
+ timeout_val_rcvd = (unsigned short)
+ simple_strtoul((char *)pkt + i + 8,
+ NULL, 10);
+ debug("Timeout oack: %s, %d\n",
+ (char *)pkt + i + 8, timeout_val_rcvd);
+ if (timeout_val_rcvd != (timeout_ms / 1000)) {
+ printf("Invalid timeout val(=%d s)\n",
+ timeout_val_rcvd);
+ tftp_state = STATE_INVALID_OPTION;
+ }
}
#ifdef CONFIG_TFTP_TSIZE
- if (strcmp((char *)pkt+i, "tsize") == 0) {
+ if (strcasecmp((char *)pkt + i, "tsize") == 0) {
tftp_tsize = simple_strtoul((char *)pkt + i + 6,
NULL, 10);
debug("size = %s, %d\n",
#endif
}
#ifdef CONFIG_CMD_TFTPPUT
- if (tftp_put_active) {
+ if (tftp_put_active && tftp_state == STATE_OACK) {
/* Get ready to send the first block */
tftp_state = STATE_DATA;
tftp_cur_block++;
len -= 2;
tftp_cur_block = ntohs(*(__be16 *)pkt);
- update_block_number();
-
if (tftp_state == STATE_SEND_RRQ)
- debug("Server did not acknowledge timeout option!\n");
+ debug("Server did not acknowledge any options!\n");
if (tftp_state == STATE_SEND_RRQ || tftp_state == STATE_OACK ||
tftp_state == STATE_RECV_WRQ) {
break;
}
+ update_block_number();
tftp_prev_block = tftp_cur_block;
timeout_count_max = tftp_timeout_count_max;
net_set_timeout_handler(timeout_ms, tftp_timeout_handler);
&& (memcmp(s, "/__overlay__", len - 1) == 0)) {
/* /<fragment-name>/__overlay__ */
rel_path = "";
- rel_path_len = 0;
+ rel_path_len = 1; /* Include NUL character */
} else {
/* Symbol refers to something that won't end
* up in the target tree */
}
ret = fdt_setprop_placeholder(fdt, root_sym, name,
- len + (len > 1) + rel_path_len + 1, &p);
+ len + (len > 1) + rel_path_len, &p);
if (ret < 0)
return ret;
buf[len] = '/';
memcpy(buf + len + 1, rel_path, rel_path_len);
- buf[len + 1 + rel_path_len] = '\0';
}
return 0;
ut_assertok(net_loop(PING));
ut_asserteq_str("eth@10002000", env_get("ethact"));
- env_set("ethact", "eth1");
+ env_set("ethact", "eth6");
ut_assertok(net_loop(PING));
ut_asserteq_str("eth@10004000", env_get("ethact"));
const char *ethname[DM_TEST_ETH_NUM] = {"eth@10002000", "eth@10003000",
"sbe5", "eth@10004000"};
const char *addrname[DM_TEST_ETH_NUM] = {"ethaddr", "eth5addr",
- "eth3addr", "eth1addr"};
+ "eth3addr", "eth6addr"};
char ethaddr[DM_TEST_ETH_NUM][18];
int i;
/* Invalidate eth1's MAC address */
memset(ethaddr, '\0', sizeof(ethaddr));
- strncpy(ethaddr, env_get("eth1addr"), 17);
- /* Must disable access protection for eth1addr before clearing */
- env_set(".flags", "eth1addr");
- env_set("eth1addr", NULL);
+ strncpy(ethaddr, env_get("eth6addr"), 17);
+ /* Must disable access protection for eth6addr before clearing */
+ env_set(".flags", "eth6addr");
+ env_set("eth6addr", NULL);
retval = _dm_test_eth_rotate1(uts);
/* Restore the env */
- env_set("eth1addr", ethaddr);
+ env_set("eth6addr", ethaddr);
env_set("ethrotate", NULL);
if (!retval) {
ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 2, &dev));
ut_asserteq_str("d-test", dev->name);
- /* d-test actually gets 0 */
- ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 0, &dev));
+ /*
+ * d-test actually gets 9, because thats the next free one after the
+ * aliases.
+ */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 9, &dev));
ut_asserteq_str("d-test", dev->name);
- /* initially no one wants seq 1 */
- ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 1,
+ /* initially no one wants seq 10 */
+ ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 10,
&dev));
ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 4, &dev));
/* But now that it is probed, we can find it */
- ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 1, &dev));
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 10, &dev));
ut_asserteq_str("f-test", dev->name);
+ /*
+ * And we should still have holes in our sequence numbers, that is 2
+ * and 4 should not be used.
+ */
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 2,
+ true, &dev));
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 4,
+ true, &dev));
+
return 0;
}
DM_TEST(dm_test_fdt_uclass_seq, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
}
DM_TEST(dm_test_usb_multi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+/* test that we have an associated ofnode with the usb device */
+static int dm_test_usb_fdt_node(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ ofnode node;
+
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
+ node = ofnode_path("/usb@1/hub/usbstor@1");
+ ut_asserteq(1, ofnode_equal(node, dev_ofnode(dev)));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
+ ut_asserteq(1, ofnode_equal(ofnode_null(), dev_ofnode(dev)));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
+ node = ofnode_path("/usb@1/hub/usbstor@3");
+ ut_asserteq(1, ofnode_equal(node, dev_ofnode(dev)));
+ ut_assertok(usb_stop());
+
+ return 0;
+}
+DM_TEST(dm_test_usb_fdt_node, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
static int count_usb_devices(void)
{
struct udevice *hub;
lib/crc16.o \
lib/sha1.o \
lib/sha256.o \
+ lib/sha512.o \
common/hash.o \
ublimage.o \
zynqimage.o \
HOSTCFLAGS_md5.o := -pedantic
HOSTCFLAGS_sha1.o := -pedantic
HOSTCFLAGS_sha256.o := -pedantic
+HOSTCFLAGS_sha512.o := -pedantic -DCONFIG_SHA512 -DCONFIG_SHA384
quiet_cmd_wrap = WRAP $@
cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@
like this:
us-net/ base directory
- 01_of_02_g4ed4ebc_net--Add-tftp-speed-/
+ 01_g4ed4ebc_net--Add-tftp-speed-/
sandbox/
u-boot.bin
seaboard/
u-boot.bin
- 02_of_02_g4ed4ebc_net--Check-tftp-comp/
+ 02_g4ed4ebc_net--Check-tftp-comp/
sandbox/
u-boot.bin
seaboard/
commit = self.commits[commit_upto]
subject = commit.subject.translate(trans_valid_chars)
# See _GetOutputSpaceRemovals() which parses this name
- commit_dir = ('%02d_of_%02d_g%s_%s' % (commit_upto + 1,
- self.commit_count, commit.hash, subject[:20]))
+ commit_dir = ('%02d_g%s_%s' % (commit_upto + 1,
+ commit.hash, subject[:20]))
elif not self.no_subdirs:
commit_dir = 'current'
if not commit_dir:
for dirname in glob.glob(os.path.join(self.base_dir, '*')):
if dirname not in dir_list:
leaf = dirname[len(self.base_dir) + 1:]
- m = re.match('[0-9]+_of_[0-9]+_g[0-9a-f]+_.*', leaf)
+ m = re.match('[0-9]+_g[0-9a-f]+_.*', leaf)
if m:
to_remove.append(dirname)
return to_remove
build.commits = self.commits
build.commit_count = len(self.commits)
subject = self.commits[1].subject.translate(builder.trans_valid_chars)
- dirname ='/%02d_of_%02d_g%s_%s' % (2, build.commit_count, commits[1][0],
+ dirname ='/%02d_g%s_%s' % (2, build.commit_count, commits[1][0],
subject[:20])
self.CheckDirs(build, dirname)
base_dir = tempfile.mkdtemp()
# Add various files that we want removed and left alone
- to_remove = ['01_of_22_g0982734987_title', '102_of_222_g92bf_title',
- '01_of_22_g2938abd8_title']
- to_leave = ['something_else', '01-something.patch', '01_of_22_another']
+ to_remove = ['01_g0982734987_title', '102_g92bf_title',
+ '01_g2938abd8_title']
+ to_leave = ['something_else', '01-something.patch', '01_another']
for name in to_remove + to_leave:
_Touch(name)
LOADADDR=0x41c00000
BOOTCORE_OPTS=0
BOOTCORE=16
+DEBUG_TYPE=0
gen_degen_template() {
cat << 'EOF' > degen-template.txt
[ debug ]
debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000
- debugType = INTEGER:4
+ debugType = INTEGER:TEST_DEBUG_TYPE
coreDbgEn = INTEGER:0
coreDbgSecEn = INTEGER:0
EOF
options_help[o]="output_file:Name of the final output file. default to $OUTPUT"
options_help[c]="core_id:target core id on which the image would be running. Default to $BOOTCORE"
options_help[l]="loadaddr: Target load address of the binary in hex. Default to $LOADADDR"
+options_help[d]="debug_type: Debug type, set to 4 to enable early JTAG. Default to $DEBUG_TYPE"
-while getopts "b:k:o:c:l:h" opt
+while getopts "b:k:o:c:l:d:h" opt
do
case $opt in
b)
c)
BOOTCORE=$OPTARG
;;
+ d)
+ DEBUG_TYPE=$OPTARG
+ ;;
h)
usage
exit 0
#echo " LOADADDR = 0x$ADDR"
#echo " IMAGE_SIZE = $BIN_SIZE"
#echo " CERT_TYPE = $CERTTYPE"
+ #echo " DEBUG_TYPE = $DEBUG_TYPE"
sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/" \
-e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \
-e "s/TEST_CERT_TYPE/$CERTTYPE/" \
-e "s/TEST_BOOT_CORE_OPTS/$BOOTCORE_OPTS/" \
-e "s/TEST_BOOT_CORE/$BOOTCORE/" \
- -e "s/TEST_BOOT_ADDR/$ADDR/" x509-template.txt > $TEMP_X509
+ -e "s/TEST_BOOT_ADDR/$ADDR/" \
+ -e "s/TEST_DEBUG_TYPE/$DEBUG_TYPE/" \
+ x509-template.txt > $TEMP_X509
openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config $TEMP_X509 -sha512
}
'stdout']
result = collections.namedtuple('CheckPatchResult', fields)
result.ok = False
- result.errors, result.warning, result.checks = 0, 0, 0
+ result.errors, result.warnings, result.checks = 0, 0, 0
result.lines = 0
result.problems = []
chk = FindCheckPatch()
# total: 0 errors, 0 warnings, 159 lines checked
# or:
# total: 0 errors, 2 warnings, 7 checks, 473 lines checked
- re_stats = re.compile('total: (\\d+) errors, (\d+) warnings, (\d+)')
- re_stats_full = re.compile('total: (\\d+) errors, (\d+) warnings, (\d+)'
+ emacs_prefix = '(?:[0-9]{4}.*\.patch:[0-9]+: )?'
+ emacs_stats = '(?:[0-9]{4}.*\.patch )?'
+ re_stats = re.compile(emacs_stats +
+ 'total: (\\d+) errors, (\d+) warnings, (\d+)')
+ re_stats_full = re.compile(emacs_stats +
+ 'total: (\\d+) errors, (\d+) warnings, (\d+)'
' checks, (\d+)')
re_ok = re.compile('.*has no obvious style problems')
re_bad = re.compile('.*has style problems, please review')
re_error = re.compile('ERROR: (.*)')
- re_warning = re.compile('WARNING: (.*)')
+ re_warning = re.compile(emacs_prefix + 'WARNING:(?:[A-Z_]+:)? (.*)')
re_check = re.compile('CHECK: (.*)')
re_file = re.compile('#\d+: FILE: ([^:]*):(\d+):')
-
+ re_note = re.compile('NOTE: (.*)')
+ indent = ' ' * 6
for line in result.stdout.splitlines():
if verbose:
print(line)
# A blank line indicates the end of a message
- if not line and item:
- result.problems.append(item)
- item = {}
+ if not line:
+ if item:
+ result.problems.append(item)
+ item = {}
+ continue
+ if re_note.match(line):
+ continue
+ # Skip lines which quote code
+ if line.startswith(indent):
+ continue
+ # Skip code quotes and #<n>
+ if line.startswith('+') or line.startswith('#'):
+ continue
match = re_stats_full.match(line)
if not match:
match = re_stats.match(line)
result.lines = int(match.group(4))
else:
result.lines = int(match.group(3))
+ continue
elif re_ok.match(line):
result.ok = True
+ continue
elif re_bad.match(line):
result.ok = False
+ continue
err_match = re_error.match(line)
warn_match = re_warning.match(line)
file_match = re_file.match(line)
check_match = re_check.match(line)
+ subject_match = line.startswith('Subject:')
if err_match:
item['msg'] = err_match.group(1)
item['type'] = 'error'
elif file_match:
item['file'] = file_match.group(1)
item['line'] = int(file_match.group(2))
+ elif subject_match:
+ item['file'] = '<patch subject>'
+ item['line'] = None
+ else:
+ print('bad line "%s", %d' % (line, len(line)))
return result
msg_type = col.Color(col.RED, msg_type)
elif msg_type == 'check':
msg_type = col.Color(col.MAGENTA, msg_type)
- return '%s:%d: %s: %s\n' % (fname, line, msg_type, msg)
+ line_str = '' if line is None else '%d' % line
+ return '%s:%s: %s: %s\n' % (fname, line_str, msg_type, msg)
def CheckPatches(verbose, args):
'''Run the checkpatch.pl script on each patch'''
projects / platform / kernel / u-boot.git / commitdiff