qemu_mips64el:
TEST_PY_BD: "qemu_mips64el"
TEST_PY_TEST_SPEC: "not sleep"
+ qemu_malta:
+ TEST_PY_BD: "malta"
+ TEST_PY_ID: "--id qemu"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ qemu_maltael:
+ TEST_PY_BD: "maltael"
+ TEST_PY_ID: "--id qemu"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ qemu_malta64:
+ TEST_PY_BD: "malta64"
+ TEST_PY_ID: "--id qemu"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ qemu_malta64el:
+ TEST_PY_BD: "malta64el"
+ TEST_PY_ID: "--id qemu"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_ppce500:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
+qemu_malta test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "malta"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ TEST_PY_ID: "--id qemu"
+ <<: *buildman_and_testpy_dfn
+
+qemu_maltael test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "maltael"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ TEST_PY_ID: "--id qemu"
+ <<: *buildman_and_testpy_dfn
+
+qemu_malta64 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "malta64"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ TEST_PY_ID: "--id qemu"
+ <<: *buildman_and_testpy_dfn
+
+qemu_malta64el test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "malta64el"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ TEST_PY_ID: "--id qemu"
+ <<: *buildman_and_testpy_dfn
+
qemu-ppce500 test.py:
tags: [ 'all' ]
variables:
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mips64el-softmmu"
TOOLCHAIN="mips"
+ - name: "test/py qemu-malta"
+ env:
+ - TEST_PY_BD="malta"
+ TEST_PY_TEST_SPEC="not sleep and not efi"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="mips-softmmu"
+ TOOLCHAIN="mips"
+ - name: "test/py qemu-maltael"
+ env:
+ - TEST_PY_BD="maltael"
+ TEST_PY_TEST_SPEC="not sleep and not efi"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="mipsel-softmmu"
+ TOOLCHAIN="mips"
+ - name: "test/py qemu-malta64"
+ env:
+ - TEST_PY_BD="malta64"
+ TEST_PY_TEST_SPEC="not sleep and not efi"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="mips64-softmmu"
+ TOOLCHAIN="mips"
+ - name: "test/py qemu-malta64el"
+ env:
+ - TEST_PY_BD="malta64el"
+ TEST_PY_TEST_SPEC="not sleep and not efi"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="mips64el-softmmu"
+ TOOLCHAIN="mips"
- name: "test/py qemu-ppce500"
env:
- TEST_PY_BD="qemu-ppce500"
#
mainmenu "U-Boot $(UBOOTVERSION) Configuration"
+comment "Compiler: $(CC_VERSION_TEXT)"
+
+source "scripts/Kconfig.include"
+
# Allow defaults in arch-specific code to override any given here
source "arch/Kconfig"
This option is enabled by default for U-Boot.
+config OPTIMIZE_INLINING
+ bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
+ default n
+ help
+ This option determines if U-Boot forces gcc to inline the functions
+ developers have marked 'inline'. Doing so takes away freedom from gcc to
+ do what it thinks is best, which is desirable in some cases for size
+ reasons.
+
+config SPL_OPTIMIZE_INLINING
+ bool "Allow compiler to uninline functions marked 'inline' in SPL"
+ depends on SPL
+ default n
+ help
+ This option determines if U-Boot forces gcc to inline the functions
+ developers have marked 'inline'. Doing so takes away freedom from gcc to
+ do what it thinks is best, which is desirable in some cases for size
+ reasons.
+
+config TPL_OPTIMIZE_INLINING
+ bool "Allow compiler to uninline functions marked 'inline' in TPL"
+ depends on TPL
+ default n
+ help
+ This option determines if U-Boot forces gcc to inline the functions
+ developers have marked 'inline'. Doing so takes away freedom from gcc to
+ do what it thinks is best, which is desirable in some cases for size
+ reasons.
+
config CC_COVERAGE
bool "Enable code coverage analysis"
depends on SANDBOX
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
+config CC_HAS_ASM_INLINE
+ def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
+
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
select AUTO_COMPLETE
help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
- the image contents have not been corrupted. SHA256 is recommended
- for use in secure applications since (as at 2016) there is no known
- feasible attack that could produce a 'collision' with differing
- input data. Use this for the highest security. Note that only the
- SHA256 variant is supported: SHA512 and others are not currently
- supported in U-Boot.
+ the image contents have not been corrupted.
+
+config FIT_ENABLE_SHA384_SUPPORT
+ bool "Support SHA384 checksum of FIT image contents"
+ default n
+ select SHA384
+ help
+ Enable this to support SHA384 checksum of FIT image contents. A
+ SHA384 checksum is a 384-bit (48-byte) hash value used to check that
+ the image contents have not been corrupted. Use this for the highest
+ security.
+
+config FIT_ENABLE_SHA512_SUPPORT
+ bool "Support SHA512 checksum of FIT image contents"
+ default n
+ select SHA512
+ help
+ Enable this to support SHA512 checksum of FIT image contents. A
+ SHA512 checksum is a 512-bit (64-byte) hash value used to check that
+ the image contents have not been corrupted.
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
F: include/asm-generic/pe.h
F: lib/charset.c
F: lib/efi*/
+F: test/lib/efi_*
F: test/py/tests/test_efi*
F: test/py/tests/test_efi*/
F: test/unicode_ut.c
T: git https://gitlab.denx.de/u-boot/u-boot.git
F: common/log*
F: cmd/log.c
+F: doc/develop/logging.rst
F: test/log/
F: test/py/tests/test_log.py
F: cmd/riscv/
F: tools/prelink-riscv.c
+RISC-V KENDRYTE
+M: Sean Anderson <seanga2@gmail.com>
+S: Maintained
+F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
+F: drivers/clk/kendryte/
+F: include/kendryte/
+
RNG
M: Sughosh Ganu <sughosh.ganu@linaro.org>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
# disable stringop warnings in gcc 8+
KBUILD_CFLAGS += $(call cc-disable-warning, stringop-truncation)
+# Enabled with W=2, disabled by default as noisy
+KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
+
# change __FILE__ to the relative path from the srctree
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
-ifneq ($(CONFIG_SECURE_BOOT), y)
+ifneq ($(CONFIG_NXP_ESBC), y)
# For Secure Boot The Image needs to be signed and Header must also
# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
@echo >&2 "===================================================="
endif
ifeq ($(CONFIG_MMC),y)
-ifneq ($(CONFIG_DM_MMC)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
+ifneq ($(CONFIG_DM_MMC)$(CONFIG_BLK),yy)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board does not use CONFIG_DM_MMC. Please update"
@echo >&2 "the board to use CONFIG_DM_MMC before the v2019.04 release."
$(call if_changed,mkimage)
endif
+quiet_cmd_endian_swap = SWAP $@
+ cmd_endian_swap = $(srctree)/tools/endian-swap.py $< $@
+
+u-boot-swap.bin: u-boot.bin FORCE
+ $(call if_changed,endian_swap)
+
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
such as ARM architectural timer initialization.
- Linux Kernel Interface:
- CONFIG_CLOCKS_IN_MHZ
-
- U-Boot stores all clock information in Hz
- internally. For binary compatibility with older Linux
- kernels (which expect the clocks passed in the
- bd_info data to be in MHz) the environment variable
- "clocks_in_mhz" can be defined so that U-Boot
- converts clock data to MHZ before passing it to the
- Linux kernel.
- When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
- "clocks_in_mhz=1" is automatically included in the
- default environment.
-
CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
When transferring memsize parameter to Linux, some versions
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
-- Console Baudrate:
- CONFIG_BAUDRATE - in bps
- Select one of the baudrates listed in
- CONFIG_SYS_BAUDRATE_TABLE, see below.
-
- Autoboot Command:
CONFIG_BOOTCOMMAND
Only needed when CONFIG_BOOTDELAY is enabled;
Allow generic access to the SPI bus on the Intel 8257x, for
example with the "sspi" command.
- CONFIG_EEPRO100
- Support for Intel 82557/82559/82559ER chips.
- Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
- write routine for first time initialisation.
-
CONFIG_TULIP
Support for Digital 2114x chips.
config ARCH_AT91
bool "Atmel AT91"
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
+ select SPL_SEPARATE_BSS if SPL
config TARGET_EDB93XX
bool "Support edb93xx"
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
+ select SPL_DM_SPI if SPL
imply CMD_SAVES
help
Support for TI's DaVinci platform.
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select SPL_DM_SPI if SPL
+ select SPL_DM_SPI_FLASH if SPL
select OF_CONTROL
select OF_SEPARATE
select SPI
config ARCH_OWL
bool "Actions Semi OWL SoCs"
select DM
+ select DM_ETH
select DM_SERIAL
select OWL_SERIAL
select CLK
imply FAT_WRITE
imply SPL
imply SPL_DM
+ imply SPL_DM_SPI
+ imply SPL_DM_SPI_FLASH
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC_SUPPORT
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
select SPL_DM if SPL
+ select SPL_DM_SPI if SPL
+ select SPL_DM_SPI_FLASH if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
+ select SPL_DM_SPI if SPI
+ select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL
select SPL_FIRMWARE if SPL
select SPL_SEPARATE_BSS if SPL
select DM_SERIAL
select ARM_PSCI_FW
select PSCI_RESET
- select DM
+ select DM_ETH
select BLK
select USB
select DM_USB
select SUPPORT_SPL
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
+ select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+ select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
imply SCSI
config TARGET_LS1021ATWR
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select SUPPORT_SPL
+ select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
imply SCSI
config TARGET_LS1021ATSN
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
+ select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
imply SCSI
help
Support for Freescale LS1021AIOT platform.
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SPL
+ select FSL_DSPI if !SPL_NO_DSPI
+ select DM_SPI_FLASH if FSL_DSPI
imply SCSI
imply SCSI_AHCI
help
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
+ select FSL_DSPI if !SPL_NO_DSPI
+ select DM_SPI_FLASH if FSL_DSPI
help
Support for Freescale LS1043ARDB platform.
select OF_CONTROL
select SPI
select SPL_DM if SPL
+ select SPL_DM_SPI if SPL
+ select SPL_DM_SPI_FLASH if SPL
select SYS_MALLOC_F
select SYS_THUMB_BUILD if !ARM64
imply ADC
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
-
-
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
+ isb
/*
* Enable SMPEN bit for coherency.
mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
orr x0, x0, #0x40
msr S3_1_c15_c2_1, x0
+ isb
1:
#endif
/* Enable data cache clean as data cache clean/invalidate */
orr x0, x0, #1 << 44
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+ isb
#endif
b 0b
/* Disable write streaming no-allocate threshold */
orr x0, x0, #3 << 27
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+ isb
#endif
#ifdef CONFIG_ARM_ERRATA_826974
/* Disable speculative load execution ahead of a DMB */
orr x0, x0, #1 << 59
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+ isb
#endif
#ifdef CONFIG_ARM_ERRATA_833471
could impact performance. */
orr x0, x0, #1 << 38
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+ isb
#endif
#ifdef CONFIG_ARM_ERRATA_829520
could impact performance. */
orr x0, x0, #1 << 4
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+ isb
#endif
#ifdef CONFIG_ARM_ERRATA_833069
/* Disable Enable Invalidates of BTB bit */
and x0, x0, #0xE
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+ isb
#endif
b 0b
ENDPROC(apply_core_errata)
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
+ zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
omap3-igep0020.dtb
+dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
+ omap4-panda.dtb \
+ omap4-panda-es.dtb
+
+dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
+ omap4-sdp.dtb \
+ omap4-sdp-es23plus.dtb
+
+dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
+ omap5-uevm.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+ elpida_ECB240ABACN: lpddr2 {
+ compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+ density = <2048>;
+ io-width = <32>;
+
+ tRPab-min-tck = <3>;
+ tRCD-min-tck = <3>;
+ tWR-min-tck = <3>;
+ tRASmin-min-tck = <3>;
+ tRRD-min-tck = <2>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tCKE-min-tck = <3>;
+ tCKESR-min-tck = <3>;
+ tFAW-min-tck = <8>;
+
+ timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <7500>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+
+ timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <200000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <10000>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+ };
+};
--- /dev/null
+&l4_abe { /* 0x40100000 */
+ compatible = "ti,omap4-l4-abe", "simple-bus";
+ reg = <0x40100000 0x400>,
+ <0x40100400 0x400>;
+ reg-names = "la", "ap";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
+ <0x49000000 0x49000000 0x100000>;
+ segment@0 { /* 0x40100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges =
+ /* CPU to L4 ABE mapping */
+ <0x00000000 0x00000000 0x000400>, /* ap 0 */
+ <0x00000400 0x00000400 0x000400>, /* ap 1 */
+ <0x00022000 0x00022000 0x001000>, /* ap 2 */
+ <0x00023000 0x00023000 0x001000>, /* ap 3 */
+ <0x00024000 0x00024000 0x001000>, /* ap 4 */
+ <0x00025000 0x00025000 0x001000>, /* ap 5 */
+ <0x00026000 0x00026000 0x001000>, /* ap 6 */
+ <0x00027000 0x00027000 0x001000>, /* ap 7 */
+ <0x00028000 0x00028000 0x001000>, /* ap 8 */
+ <0x00029000 0x00029000 0x001000>, /* ap 9 */
+ <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
+ <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
+ <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
+ <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
+ <0x00030000 0x00030000 0x001000>, /* ap 14 */
+ <0x00031000 0x00031000 0x001000>, /* ap 15 */
+ <0x00032000 0x00032000 0x001000>, /* ap 16 */
+ <0x00033000 0x00033000 0x001000>, /* ap 17 */
+ <0x00038000 0x00038000 0x001000>, /* ap 18 */
+ <0x00039000 0x00039000 0x001000>, /* ap 19 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
+ <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
+ <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
+ <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
+ <0x00080000 0x00080000 0x010000>, /* ap 26 */
+ <0x00080000 0x00080000 0x001000>, /* ap 27 */
+ <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
+ <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
+ <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
+ <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
+ <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
+ <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
+
+ /* L3 to L4 ABE mapping */
+ <0x49000000 0x49000000 0x000400>, /* ap 0 */
+ <0x49000400 0x49000400 0x000400>, /* ap 1 */
+ <0x49022000 0x49022000 0x001000>, /* ap 2 */
+ <0x49023000 0x49023000 0x001000>, /* ap 3 */
+ <0x49024000 0x49024000 0x001000>, /* ap 4 */
+ <0x49025000 0x49025000 0x001000>, /* ap 5 */
+ <0x49026000 0x49026000 0x001000>, /* ap 6 */
+ <0x49027000 0x49027000 0x001000>, /* ap 7 */
+ <0x49028000 0x49028000 0x001000>, /* ap 8 */
+ <0x49029000 0x49029000 0x001000>, /* ap 9 */
+ <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
+ <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
+ <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
+ <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
+ <0x49030000 0x49030000 0x001000>, /* ap 14 */
+ <0x49031000 0x49031000 0x001000>, /* ap 15 */
+ <0x49032000 0x49032000 0x001000>, /* ap 16 */
+ <0x49033000 0x49033000 0x001000>, /* ap 17 */
+ <0x49038000 0x49038000 0x001000>, /* ap 18 */
+ <0x49039000 0x49039000 0x001000>, /* ap 19 */
+ <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
+ <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
+ <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
+ <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
+ <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
+ <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
+ <0x49080000 0x49080000 0x010000>, /* ap 26 */
+ <0x49080000 0x49080000 0x001000>, /* ap 27 */
+ <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
+ <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
+ <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
+ <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
+ <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
+ <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
+
+ target-module@22000 { /* 0x40122000, ap 2 02.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2208c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>,
+ <0x49022000 0x49022000 0x1000>;
+
+ mcbsp1: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49022000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 33>,
+ <&sdma 34>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@24000 { /* 0x40124000, ap 4 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2408c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>,
+ <0x49024000 0x49024000 0x1000>;
+
+ mcbsp2: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49024000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 17>,
+ <&sdma 18>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@26000 { /* 0x40126000, ap 6 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2608c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>,
+ <0x49026000 0x49026000 0x1000>;
+
+ mcbsp3: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49026000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 19>,
+ <&sdma 20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@28000 { /* 0x40128000, ap 8 08.0 */
+ compatible = "ti,sysc-mcasp", "ti,sysc";
+ reg = <0x28000 0x4>,
+ <0x28004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>,
+ <0x49028000 0x49028000 0x1000>;
+
+ /*
+ * Child device unsupported by davinci-mcasp. At least
+ * RX path is disabled for omap4, and only DIT mode
+ * works with no I2S. See also old Android kernel
+ * omap-mcasp driver for more information.
+ */
+ };
+
+ target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>,
+ <0x4902a000 0x4902a000 0x1000>;
+ };
+
+ target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2e000 0x4>,
+ <0x2e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2e000 0x1000>,
+ <0x4902e000 0x4902e000 0x1000>;
+
+ dmic: dmic@0 {
+ compatible = "ti,omap4-dmic";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x4902e000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 67>;
+ dma-names = "up_link";
+ status = "disabled";
+ };
+ };
+
+ target-module@30000 { /* 0x40130000, ap 14 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x30000 0x4>,
+ <0x30010 0x4>,
+ <0x30014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>,
+ <0x49030000 0x49030000 0x1000>;
+
+ wdt3: wdt@0 {
+ compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>,
+ <0x49032000 0x49032000 0x1000>;
+
+ /* Must be only enabled for boards with pdmclk wired */
+ status = "disabled";
+
+ mcpdm: mcpdm@0 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 65>,
+ <&sdma 66>;
+ dma-names = "up_link", "dn_link";
+ };
+ };
+
+ target-module@38000 { /* 0x40138000, ap 18 12.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x38000 0x4>,
+ <0x38010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x1000>,
+ <0x49038000 0x49038000 0x1000>;
+
+ timer5: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x49038000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3a000 0x4>,
+ <0x3a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3a000 0x1000>,
+ <0x4903a000 0x4903a000 0x1000>;
+
+ timer6: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x4903a000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3c000 0x4>,
+ <0x3c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x1000>,
+ <0x4903c000 0x4903c000 0x1000>;
+
+ timer7: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x4903c000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>,
+ <0x4903e000 0x4903e000 0x1000>;
+
+ timer8: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x00000000 0x80>,
+ <0x4903e000 0x80>;
+ clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@80000 { /* 0x40180000, ap 26 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>,
+ <0x49080000 0x49080000 0x10000>;
+ };
+
+ target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x10000>,
+ <0x490a0000 0x490a0000 0x10000>;
+ };
+
+ target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc0000 0x10000>,
+ <0x490c0000 0x490c0000 0x10000>;
+ };
+
+ target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xf1000 0x4>,
+ <0xf1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf1000 0x1000>,
+ <0x490f1000 0x490f1000 0x1000>;
+
+ /*
+ * No child device binding or driver in mainline.
+ * See Android tree and related upstreaming efforts
+ * for the old driver.
+ */
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+&l4_cfg { /* 0x4a000000 */
+ compatible = "ti,omap4-l4-cfg", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
+ <0x00080000 0x4a080000 0x080000>, /* segment 1 */
+ <0x00100000 0x4a100000 0x080000>, /* segment 2 */
+ <0x00180000 0x4a180000 0x080000>, /* segment 3 */
+ <0x00200000 0x4a200000 0x080000>, /* segment 4 */
+ <0x00280000 0x4a280000 0x080000>, /* segment 5 */
+ <0x00300000 0x4a300000 0x080000>; /* segment 6 */
+
+ segment@0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00002000 0x00002000 0x001000>, /* ap 3 */
+ <0x00003000 0x00003000 0x001000>, /* ap 4 */
+ <0x00004000 0x00004000 0x001000>, /* ap 5 */
+ <0x00005000 0x00005000 0x001000>, /* ap 6 */
+ <0x00056000 0x00056000 0x001000>, /* ap 7 */
+ <0x00057000 0x00057000 0x001000>, /* ap 8 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
+ <0x00058000 0x00058000 0x004000>, /* ap 10 */
+ <0x00062000 0x00062000 0x001000>, /* ap 11 */
+ <0x00063000 0x00063000 0x001000>, /* ap 12 */
+ <0x00008000 0x00008000 0x002000>, /* ap 23 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 24 */
+ <0x00066000 0x00066000 0x001000>, /* ap 25 */
+ <0x00067000 0x00067000 0x001000>, /* ap 26 */
+ <0x0005e000 0x0005e000 0x002000>, /* ap 80 */
+ <0x00060000 0x00060000 0x001000>, /* ap 81 */
+ <0x00064000 0x00064000 0x001000>, /* ap 86 */
+ <0x00065000 0x00065000 0x001000>; /* ap 87 */
+
+ target-module@2000 { /* 0x4a002000, ap 3 06.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_core";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ omap4_scm_core: scm@0 {
+ compatible = "ti,omap4-scm-core", "simple-bus";
+ reg = <0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ omap_control_usb2phy: control-phy@300 {
+ compatible = "ti,control-phy-usb2";
+ reg = <0x300 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usbotg: control-phy@33c {
+ compatible = "ti,control-phy-otghs";
+ reg = <0x33c 0x4>;
+ reg-names = "otghs_control";
+ };
+ };
+ };
+
+ target-module@4000 { /* 0x4a004000, ap 5 02.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x4000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ cm1: cm1@0 {
+ compatible = "ti,omap4-cm1", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ cm1_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm1_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@8000 { /* 0x4a008000, ap 23 32.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x8000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x2000>;
+
+ cm2: cm2@0 {
+ compatible = "ti,omap4-cm2", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ cm2_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm2_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x56000 0x4>,
+ <0x5602c 0x4>,
+ <0x56028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
+ clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x56000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <127>;
+ };
+ };
+
+ target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000 0x4>,
+ <0x58010 0x4>,
+ <0x58014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x58000 0x5000>;
+
+ hsi: hsi@0 {
+ compatible = "ti,omap4-hsi";
+ reg = <0x0 0x4000>,
+ <0x5000 0x1000>;
+ reg-names = "sys", "gdd";
+
+ clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
+ clock-names = "hsi_fck";
+
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gdd_mpu";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x4000>;
+
+ hsi_port1: hsi-port@2000 {
+ compatible = "ti,omap4-hsi-port";
+ reg = <0x2000 0x800>,
+ <0x2800 0x800>;
+ reg-names = "tx", "rx";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ hsi_port2: hsi-port@3000 {
+ compatible = "ti,omap4-hsi-port";
+ reg = <0x3000 0x800>,
+ <0x3800 0x800>;
+ reg-names = "tx", "rx";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5e000 0x2000>;
+ };
+
+ target-module@62000 { /* 0x4a062000, ap 11 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "usb_tll_hs";
+ reg = <0x62000 0x4>,
+ <0x62010 0x4>,
+ <0x62014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x62000 0x1000>;
+
+ usbhstll: usbhstll@0 {
+ compatible = "ti,usbhs-tll";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_host_hs";
+ reg = <0x64000 0x4>,
+ <0x64010 0x4>,
+ <0x64014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x64000 0x1000>;
+
+ usbhshost: usbhshost@0 {
+ compatible = "ti,usbhs-host";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ clocks = <&init_60m_fclk>,
+ <&xclk60mhsp1_ck>,
+ <&xclk60mhsp2_ck>;
+ clock-names = "refclk_60m_int",
+ "refclk_60m_ext_p1",
+ "refclk_60m_ext_p2";
+
+ usbhsohci: ohci@800 {
+ compatible = "ti,ohci-omap3";
+ reg = <0x800 0x400>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ remote-wakeup-connected;
+ };
+
+ usbhsehci: ehci@c00 {
+ compatible = "ti,ehci-omap";
+ reg = <0xc00 0x400>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ target-module@66000 { /* 0x4a066000, ap 25 26.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x66000 0x4>,
+ <0x66010 0x4>,
+ <0x66014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
+ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_tesla 1>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x1000>;
+
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
+ };
+ };
+
+ segment@80000 { /* 0x4a080000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
+ <0x0005a000 0x000da000 0x001000>, /* ap 14 */
+ <0x0005b000 0x000db000 0x001000>, /* ap 15 */
+ <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
+ <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
+ <0x0005e000 0x000de000 0x001000>, /* ap 18 */
+ <0x00060000 0x000e0000 0x001000>, /* ap 19 */
+ <0x00061000 0x000e1000 0x001000>, /* ap 20 */
+ <0x00074000 0x000f4000 0x001000>, /* ap 27 */
+ <0x00075000 0x000f5000 0x001000>, /* ap 28 */
+ <0x00076000 0x000f6000 0x001000>, /* ap 29 */
+ <0x00077000 0x000f7000 0x001000>, /* ap 30 */
+ <0x00036000 0x000b6000 0x001000>, /* ap 69 */
+ <0x00037000 0x000b7000 0x001000>, /* ap 70 */
+ <0x0004d000 0x000cd000 0x001000>, /* ap 78 */
+ <0x0004e000 0x000ce000 0x001000>, /* ap 79 */
+ <0x00029000 0x000a9000 0x001000>, /* ap 82 */
+ <0x0002a000 0x000aa000 0x001000>, /* ap 83 */
+ <0x0002b000 0x000ab000 0x001000>, /* ap 84 */
+ <0x0002c000 0x000ac000 0x001000>, /* ap 85 */
+ <0x0002d000 0x000ad000 0x001000>, /* ap 88 */
+ <0x0002e000 0x000ae000 0x001000>; /* ap 89 */
+
+ target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x29000 0x1000>;
+ };
+
+ target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2b400 0x4>,
+ <0x2b404 0x4>,
+ <0x2b408 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2b000 0x1000>;
+
+ usb_otg_hs: usb_otg_hs@0 {
+ compatible = "ti,omap4-musb";
+ reg = <0x0 0x7ff>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc", "dma";
+ usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ multipoint = <1>;
+ num-eps = <16>;
+ ram-bits = <12>;
+ ctrl-module = <&omap_control_usbotg>;
+ };
+ };
+
+ target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2d000 0x4>,
+ <0x2d010 0x4>,
+ <0x2d014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2d000 0x1000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ reg = <0x0 0x1f>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ usb2_phy: usb2phy@80 {
+ compatible = "ti,omap-usb2";
+ reg = <0x80 0x58>;
+ ctrl-module = <&omap_control_usb2phy>;
+ clocks = <&usb_phy_cm_clk32k>;
+ clock-names = "wkupclk";
+ #phy-cells = <0>;
+ };
+ };
+ };
+
+ /* d2d mdm */
+ target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x36000 0x4>,
+ <0x36010 0x4>,
+ <0x36014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
+ clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+ };
+
+ /* d2d mpu */
+ target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4d000 0x4>,
+ <0x4d010 0x4>,
+ <0x4d014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
+ clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4d000 0x1000>;
+ };
+
+ target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ reg = <0x59038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+
+ smartreflex_mpu: smartreflex@0 {
+ compatible = "ti,omap4-smartreflex-mpu";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ reg = <0x5b038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ smartreflex_iva: smartreflex@0 {
+ compatible = "ti,omap4-smartreflex-iva";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ reg = <0x5d038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+
+ smartreflex_core: smartreflex@0 {
+ compatible = "ti,omap4-smartreflex-core";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+ };
+
+ target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x74000 0x4>,
+ <0x74010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x74000 0x1000>;
+
+ mailbox: mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ mbox_ipu: mbox_ipu {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ mbox_dsp: mbox_dsp {
+ ti,mbox-tx = <3 0 0>;
+ ti,mbox-rx = <2 0 0>;
+ };
+ };
+ };
+
+ target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x76000 0x4>,
+ <0x76010 0x4>,
+ <0x76014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x76000 0x1000>;
+
+ hwspinlock: spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+ };
+
+ segment@100000 { /* 0x4a100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
+ <0x00001000 0x00101000 0x001000>, /* ap 22 */
+ <0x00002000 0x00102000 0x001000>, /* ap 61 */
+ <0x00003000 0x00103000 0x001000>, /* ap 62 */
+ <0x00008000 0x00108000 0x001000>, /* ap 63 */
+ <0x00009000 0x00109000 0x001000>, /* ap 64 */
+ <0x0000a000 0x0010a000 0x001000>, /* ap 65 */
+ <0x0000b000 0x0010b000 0x001000>; /* ap 66 */
+
+ target-module@0 { /* 0x4a100000, ap 21 2a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_pad_core";
+ reg = <0x0 0x4>,
+ <0x10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ omap4_pmx_core: pinmux@40 {
+ compatible = "ti,omap4-padconf",
+ "pinctrl-single";
+ reg = <0x40 0x0196>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
+ omap4_padconf_global: omap4_padconf_global@5a0 {
+ compatible = "syscon",
+ "simple-bus";
+ reg = <0x5a0 0x170>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5a0 0x170>;
+
+ pbias_regulator: pbias_regulator@60 {
+ compatible = "ti,pbias-omap4", "ti,pbias-omap";
+ reg = <0x60 0x4>;
+ syscon = <&omap4_padconf_global>;
+ pbias_mmc_reg: pbias_mmc_omap4 {
+ regulator-name = "pbias_mmc_omap4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+ };
+ };
+
+ target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@8000 { /* 0x4a108000, ap 63 62.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xa000 0x4>,
+ <0xa010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-delay-us = <2>;
+ /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
+ clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+
+ /* No child device binding or driver in mainline */
+ };
+ };
+
+ segment@180000 { /* 0x4a180000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@200000 { /* 0x4a200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
+ <0x0001f000 0x0021f000 0x001000>, /* ap 32 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 33 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 34 */
+ <0x00004000 0x00204000 0x001000>, /* ap 35 */
+ <0x00005000 0x00205000 0x001000>, /* ap 36 */
+ <0x00006000 0x00206000 0x001000>, /* ap 37 */
+ <0x00007000 0x00207000 0x001000>, /* ap 38 */
+ <0x00012000 0x00212000 0x001000>, /* ap 39 */
+ <0x00013000 0x00213000 0x001000>, /* ap 40 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 41 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 42 */
+ <0x00010000 0x00210000 0x001000>, /* ap 43 */
+ <0x00011000 0x00211000 0x001000>, /* ap 44 */
+ <0x00016000 0x00216000 0x001000>, /* ap 45 */
+ <0x00017000 0x00217000 0x001000>, /* ap 46 */
+ <0x00014000 0x00214000 0x001000>, /* ap 47 */
+ <0x00015000 0x00215000 0x001000>, /* ap 48 */
+ <0x00018000 0x00218000 0x001000>, /* ap 49 */
+ <0x00019000 0x00219000 0x001000>, /* ap 50 */
+ <0x00020000 0x00220000 0x001000>, /* ap 51 */
+ <0x00021000 0x00221000 0x001000>, /* ap 52 */
+ <0x00026000 0x00226000 0x001000>, /* ap 53 */
+ <0x00027000 0x00227000 0x001000>, /* ap 54 */
+ <0x00028000 0x00228000 0x001000>, /* ap 55 */
+ <0x00029000 0x00229000 0x001000>, /* ap 56 */
+ <0x0002a000 0x0022a000 0x001000>, /* ap 57 */
+ <0x0002b000 0x0022b000 0x001000>, /* ap 58 */
+ <0x0001c000 0x0021c000 0x001000>, /* ap 59 */
+ <0x0001d000 0x0021d000 0x001000>; /* ap 60 */
+
+ target-module@4000 { /* 0x4a204000, ap 35 42.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+ };
+
+ target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+ };
+
+ target-module@10000 { /* 0x4a210000, ap 43 52.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x1000>;
+ };
+
+ target-module@12000 { /* 0x4a212000, ap 39 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x12000 0x1000>;
+ };
+
+ target-module@14000 { /* 0x4a214000, ap 47 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module@16000 { /* 0x4a216000, ap 45 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x16000 0x1000>;
+ };
+
+ target-module@18000 { /* 0x4a218000, ap 49 38.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x1000>;
+ };
+
+ target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1c000 0x1000>;
+ };
+
+ target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e000 0x1000>;
+ };
+
+ target-module@20000 { /* 0x4a220000, ap 51 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+ };
+
+ target-module@26000 { /* 0x4a226000, ap 53 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+ };
+
+ target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>;
+ };
+
+ target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+ };
+ };
+
+ segment@280000 { /* 0x4a280000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
+ <0x00040000 0x00340000 0x001000>, /* ap 68 */
+ <0x00020000 0x00320000 0x004000>, /* ap 71 */
+ <0x00024000 0x00324000 0x002000>, /* ap 72 */
+ <0x00026000 0x00326000 0x001000>, /* ap 73 */
+ <0x00027000 0x00327000 0x001000>, /* ap 74 */
+ <0x00028000 0x00328000 0x001000>, /* ap 75 */
+ <0x00029000 0x00329000 0x001000>, /* ap 76 */
+ <0x00030000 0x00330000 0x010000>, /* ap 77 */
+ <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
+ <0x0002c000 0x0032c000 0x004000>; /* ap 91 */
+
+ l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x00020000>,
+ <0x00020000 0x00020000 0x00004000>,
+ <0x00024000 0x00024000 0x00002000>,
+ <0x00026000 0x00026000 0x00001000>,
+ <0x00027000 0x00027000 0x00001000>,
+ <0x00028000 0x00028000 0x00001000>,
+ <0x00029000 0x00029000 0x00001000>,
+ <0x0002a000 0x0002a000 0x00002000>,
+ <0x0002c000 0x0002c000 0x00004000>,
+ <0x00030000 0x00030000 0x00010000>;
+ };
+ };
+};
+
+&l4_wkup { /* 0x4a300000 */
+ compatible = "ti,omap4-l4-wkup", "simple-bus";
+ reg = <0x4a300000 0x800>,
+ <0x4a300800 0x800>,
+ <0x4a301000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
+ <0x00010000 0x4a310000 0x010000>, /* segment 1 */
+ <0x00020000 0x4a320000 0x010000>; /* segment 2 */
+
+ segment@0 { /* 0x4a300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00006000 0x00006000 0x002000>, /* ap 3 */
+ <0x00008000 0x00008000 0x001000>, /* ap 4 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
+ <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
+ <0x00004000 0x00004000 0x001000>, /* ap 17 */
+ <0x00005000 0x00005000 0x001000>, /* ap 18 */
+ <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
+ <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
+
+ target-module@4000 { /* 0x4a304000, ap 17 24.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "counter_32k";
+ reg = <0x4000 0x4>,
+ <0x4004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x0 0x20>;
+ };
+ };
+
+ target-module@6000 { /* 0x4a306000, ap 3 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x6000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x2000>;
+
+ prm: prm@0 {
+ compatible = "ti,omap4-prm", "simple-bus";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@a000 { /* 0x4a30a000, ap 15 34.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xa000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+
+ scrm: scrm@0 {
+ compatible = "ti,omap4-scrm";
+ reg = <0x0 0x2000>;
+
+ scrm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scrm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_wkup";
+ reg = <0xc000 0x4>,
+ <0xc010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ omap4_scm_wkup: scm@c000 {
+ compatible = "ti,omap4-scm-wkup";
+ reg = <0xc000 0x1000>;
+ };
+ };
+ };
+
+ segment@10000 { /* 0x4a310000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
+ <0x00001000 0x00011000 0x001000>, /* ap 6 */
+ <0x00004000 0x00014000 0x001000>, /* ap 7 */
+ <0x00005000 0x00015000 0x001000>, /* ap 8 */
+ <0x00008000 0x00018000 0x001000>, /* ap 9 */
+ <0x00009000 0x00019000 0x001000>, /* ap 10 */
+ <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
+ <0x0000d000 0x0001d000 0x001000>, /* ap 12 */
+ <0x0000e000 0x0001e000 0x001000>, /* ap 21 */
+ <0x0000f000 0x0001f000 0x001000>; /* ap 22 */
+
+ gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x0 0x4>,
+ <0x10 0x4>,
+ <0x114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>,
+ <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ gpio1: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ ti,gpio-always-on;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@4000 { /* 0x4a314000, ap 7 18.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ wdt2: wdt@0 {
+ compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ ti,hwmods = "timer1";
+ reg = <0x8000 0x4>,
+ <0x8010 0x4>,
+ <0x8014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-alwon;
+ };
+ };
+
+ target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xc000 0x4>,
+ <0xc010 0x4>,
+ <0xc014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ keypad: keypad@0 {
+ compatible = "ti,omap4-keypad";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ reg-names = "mpu";
+ };
+ };
+
+ target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ctrl_module_pad_wkup";
+ reg = <0xe000 0x4>,
+ <0xe010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe000 0x1000>;
+
+ omap4_pmx_wkup: pinmux@40 {
+ compatible = "ti,omap4-padconf",
+ "pinctrl-single";
+ reg = <0x40 0x0038>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+ };
+ };
+
+ segment@20000 { /* 0x4a320000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
+ <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
+ <0x00000000 0x00020000 0x001000>, /* ap 23 */
+ <0x00001000 0x00021000 0x001000>, /* ap 24 */
+ <0x00002000 0x00022000 0x001000>, /* ap 25 */
+ <0x00003000 0x00023000 0x001000>, /* ap 26 */
+ <0x00004000 0x00024000 0x001000>, /* ap 27 */
+ <0x00005000 0x00025000 0x001000>, /* ap 28 */
+ <0x00007000 0x00027000 0x000400>, /* ap 29 */
+ <0x00008000 0x00028000 0x000800>, /* ap 30 */
+ <0x00009000 0x00029000 0x000400>; /* ap 31 */
+
+ target-module@0 { /* 0x4a320000, ap 23 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+ };
+
+ target-module@2000 { /* 0x4a322000, ap 25 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@4000 { /* 0x4a324000, ap 27 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4a326000, ap 13 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00006000 0x00001000>,
+ <0x00001000 0x00007000 0x00000400>,
+ <0x00002000 0x00008000 0x00000800>,
+ <0x00003000 0x00009000 0x00000400>;
+ };
+ };
+};
+
+&l4_per { /* 0x48000000 */
+ compatible = "ti,omap4-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
+ <0x00200000 0x48200000 0x200000>; /* segment 1 */
+
+ segment@0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x000400>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00020000 0x00020000 0x001000>, /* ap 3 */
+ <0x00021000 0x00021000 0x001000>, /* ap 4 */
+ <0x00032000 0x00032000 0x001000>, /* ap 5 */
+ <0x00033000 0x00033000 0x001000>, /* ap 6 */
+ <0x00034000 0x00034000 0x001000>, /* ap 7 */
+ <0x00035000 0x00035000 0x001000>, /* ap 8 */
+ <0x00036000 0x00036000 0x001000>, /* ap 9 */
+ <0x00037000 0x00037000 0x001000>, /* ap 10 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
+ <0x00040000 0x00040000 0x010000>, /* ap 13 */
+ <0x00050000 0x00050000 0x001000>, /* ap 14 */
+ <0x00055000 0x00055000 0x001000>, /* ap 15 */
+ <0x00056000 0x00056000 0x001000>, /* ap 16 */
+ <0x00057000 0x00057000 0x001000>, /* ap 17 */
+ <0x00058000 0x00058000 0x001000>, /* ap 18 */
+ <0x00059000 0x00059000 0x001000>, /* ap 19 */
+ <0x0005a000 0x0005a000 0x001000>, /* ap 20 */
+ <0x0005b000 0x0005b000 0x001000>, /* ap 21 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 22 */
+ <0x0005d000 0x0005d000 0x001000>, /* ap 23 */
+ <0x0005e000 0x0005e000 0x001000>, /* ap 24 */
+ <0x00060000 0x00060000 0x001000>, /* ap 25 */
+ <0x0006a000 0x0006a000 0x001000>, /* ap 26 */
+ <0x0006b000 0x0006b000 0x001000>, /* ap 27 */
+ <0x0006c000 0x0006c000 0x001000>, /* ap 28 */
+ <0x0006d000 0x0006d000 0x001000>, /* ap 29 */
+ <0x0006e000 0x0006e000 0x001000>, /* ap 30 */
+ <0x0006f000 0x0006f000 0x001000>, /* ap 31 */
+ <0x00070000 0x00070000 0x001000>, /* ap 32 */
+ <0x00071000 0x00071000 0x001000>, /* ap 33 */
+ <0x00072000 0x00072000 0x001000>, /* ap 34 */
+ <0x00073000 0x00073000 0x001000>, /* ap 35 */
+ <0x00061000 0x00061000 0x001000>, /* ap 36 */
+ <0x00096000 0x00096000 0x001000>, /* ap 37 */
+ <0x00097000 0x00097000 0x001000>, /* ap 38 */
+ <0x00076000 0x00076000 0x001000>, /* ap 39 */
+ <0x00077000 0x00077000 0x001000>, /* ap 40 */
+ <0x00078000 0x00078000 0x001000>, /* ap 41 */
+ <0x00079000 0x00079000 0x001000>, /* ap 42 */
+ <0x00086000 0x00086000 0x001000>, /* ap 43 */
+ <0x00087000 0x00087000 0x001000>, /* ap 44 */
+ <0x00088000 0x00088000 0x001000>, /* ap 45 */
+ <0x00089000 0x00089000 0x001000>, /* ap 46 */
+ <0x000b0000 0x000b0000 0x001000>, /* ap 47 */
+ <0x000b1000 0x000b1000 0x001000>, /* ap 48 */
+ <0x00098000 0x00098000 0x001000>, /* ap 49 */
+ <0x00099000 0x00099000 0x001000>, /* ap 50 */
+ <0x0009a000 0x0009a000 0x001000>, /* ap 51 */
+ <0x0009b000 0x0009b000 0x001000>, /* ap 52 */
+ <0x0009c000 0x0009c000 0x001000>, /* ap 53 */
+ <0x0009d000 0x0009d000 0x001000>, /* ap 54 */
+ <0x0009e000 0x0009e000 0x001000>, /* ap 55 */
+ <0x0009f000 0x0009f000 0x001000>, /* ap 56 */
+ <0x00090000 0x00090000 0x002000>, /* ap 57 */
+ <0x00092000 0x00092000 0x001000>, /* ap 58 */
+ <0x000a4000 0x000a4000 0x001000>, /* ap 59 */
+ <0x000a6000 0x000a6000 0x001000>, /* ap 60 */
+ <0x000a8000 0x000a8000 0x004000>, /* ap 61 */
+ <0x000ac000 0x000ac000 0x001000>, /* ap 62 */
+ <0x000ad000 0x000ad000 0x001000>, /* ap 63 */
+ <0x000ae000 0x000ae000 0x001000>, /* ap 64 */
+ <0x000b2000 0x000b2000 0x001000>, /* ap 65 */
+ <0x000b3000 0x000b3000 0x001000>, /* ap 66 */
+ <0x000b4000 0x000b4000 0x001000>, /* ap 67 */
+ <0x000b5000 0x000b5000 0x001000>, /* ap 68 */
+ <0x000b8000 0x000b8000 0x001000>, /* ap 69 */
+ <0x000b9000 0x000b9000 0x001000>, /* ap 70 */
+ <0x000ba000 0x000ba000 0x001000>, /* ap 71 */
+ <0x000bb000 0x000bb000 0x001000>, /* ap 72 */
+ <0x000d1000 0x000d1000 0x001000>, /* ap 73 */
+ <0x000d2000 0x000d2000 0x001000>, /* ap 74 */
+ <0x000d5000 0x000d5000 0x001000>, /* ap 75 */
+ <0x000d6000 0x000d6000 0x001000>, /* ap 76 */
+ <0x000a2000 0x000a2000 0x001000>, /* ap 79 */
+ <0x000a3000 0x000a3000 0x001000>, /* ap 80 */
+ <0x00001400 0x00001400 0x000400>, /* ap 81 */
+ <0x00001800 0x00001800 0x000400>, /* ap 82 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 83 */
+ <0x000a5000 0x000a5000 0x001000>; /* ap 84 */
+
+ target-module@20000 { /* 0x48020000, ap 3 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x20050 0x4>,
+ <0x20054 0x4>,
+ <0x20058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ uart3: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@32000 { /* 0x48032000, ap 5 02.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>,
+ <0x32014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@34000 { /* 0x48034000, ap 7 04.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x34000 0x4>,
+ <0x34010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x1000>;
+
+ timer3: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@36000 { /* 0x48036000, ap 9 0e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x36000 0x4>,
+ <0x36010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+
+ timer4: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ timer9: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ /* Unused DSS L4 access, see L3 instead */
+ target-module@40000 { /* 0x48040000, ap 13 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x10000>;
+ };
+
+ target-module@55000 { /* 0x48055000, ap 15 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55000 0x4>,
+ <0x55010 0x4>,
+ <0x55114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@57000 { /* 0x48057000, ap 17 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x57000 0x4>,
+ <0x57010 0x4>,
+ <0x57114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x57000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@59000 { /* 0x48059000, ap 19 10.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x59000 0x4>,
+ <0x59010 0x4>,
+ <0x59114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+
+ gpio4: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5b000 0x4>,
+ <0x5b010 0x4>,
+ <0x5b114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ gpio5: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5d000 0x4>,
+ <0x5d010 0x4>,
+ <0x5d114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>,
+ <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+
+ gpio6: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@60000 { /* 0x48060000, ap 25 1e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x60000 0x8>,
+ <0x60010 0x8>,
+ <0x60090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+
+ i2c3: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6a050 0x4>,
+ <0x6a054 0x4>,
+ <0x6a058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6a000 0x1000>;
+
+ uart1: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6c050 0x4>,
+ <0x6c054 0x4>,
+ <0x6c058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6c000 0x1000>;
+
+ uart2: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6e050 0x4>,
+ <0x6e054 0x4>,
+ <0x6e058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6e000 0x1000>;
+
+ uart4: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@70000 { /* 0x48070000, ap 32 28.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x70000 0x8>,
+ <0x70010 0x8>,
+ <0x70090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x70000 0x1000>;
+
+ i2c1: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@72000 { /* 0x48072000, ap 34 30.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x72000 0x8>,
+ <0x72010 0x8>,
+ <0x72090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x72000 0x1000>;
+
+ i2c2: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@76000 { /* 0x48076000, ap 39 38.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x76000 0x4>,
+ <0x76010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x76000 0x1000>;
+
+ /* No child device binding or driver in mainline */
+ };
+
+ target-module@78000 { /* 0x48078000, ap 41 1a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x78000 0x4>,
+ <0x78010 0x4>,
+ <0x78014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x78000 0x1000>;
+
+ elm: elm@0 {
+ compatible = "ti,am3352-elm";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@86000 { /* 0x48086000, ap 43 24.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x86000 0x4>,
+ <0x86010 0x4>,
+ <0x86014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x86000 0x1000>;
+
+ timer10: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@88000 { /* 0x48088000, ap 45 2e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x88000 0x4>,
+ <0x88010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x88000 0x1000>;
+
+ timer11: timer@0 {
+ compatible = "ti,omap4430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x91fe0 0x4>,
+ <0x91fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x90000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@96000 { /* 0x48096000, ap 37 26.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x9608c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x96000 0x1000>;
+
+ mcbsp4: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>; /* L4 Interconnect */
+ reg-names = "mpu";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 31>,
+ <&sdma 32>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@98000 { /* 0x48098000, ap 49 22.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x98000 0x4>,
+ <0x98010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x98000 0x1000>;
+
+ mcspi1: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+ };
+
+ target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9a000 0x4>,
+ <0x9a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9a000 0x1000>;
+
+ mcspi2: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+ };
+
+ target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9c000 0x4>,
+ <0x9c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+
+ mmc1: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+ };
+
+ target-module@9e000 { /* 0x4809e000, ap 55 48.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9e000 0x1000>;
+ };
+
+ target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+ };
+
+ target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x000a4000 0x00001000>,
+ <0x00001000 0x000a5000 0x00001000>;
+ };
+
+ des_target: target-module@a5000 { /* 0x480a5000 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa5030 0x4>,
+ <0xa5034 0x4>,
+ <0xa5038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa5000 0x00001000>;
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 117>, <&sdma 116>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x4000>;
+ };
+
+ target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xad000 0x4>,
+ <0xad010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xad000 0x1000>;
+
+ mmc3: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb0000 0x1000>;
+ };
+
+ target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xb2000 0x4>,
+ <0xb2014 0x4>,
+ <0xb2018 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ ti,no-reset-on-init;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb2000 0x1000>;
+
+ hdqw1w: 1w@0 {
+ compatible = "ti,omap3-1w";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb4000 0x4>,
+ <0xb4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
+ clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb4000 0x1000>;
+
+ mmc2: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb8000 0x4>,
+ <0xb8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb8000 0x1000>;
+
+ mcspi3: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xba000 0x4>,
+ <0xba010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xba000 0x1000>;
+
+ mcspi4: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd1000 0x4>,
+ <0xd1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd1000 0x1000>;
+
+ mmc4: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd5000 0x4>,
+ <0xd5010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd5000 0x1000>;
+
+ mmc5: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 59>, <&sdma 60>;
+ dma-names = "tx", "rx";
+ };
+ };
+ };
+
+ segment@200000 { /* 0x48200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
+ <0x00151000 0x00351000 0x001000>; /* ap 78 */
+
+ target-module@150000 { /* 0x48350000, ap 77 4c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x150000 0x8>,
+ <0x150010 0x8>,
+ <0x150090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
+ clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x150000 0x1000>;
+
+ i2c4: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common omap4 mcpdm configuration
+ *
+ * Only include this file if your board has pdmclk wired from the
+ * pmic to ABE as mcpdm uses an external clock for the module.
+ */
+
+&omap4_pmx_core {
+ mcpdm_pins: pinmux_mcpdm_pins {
+ pinctrl-single,pins = <
+ /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
+ OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+ /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
+ OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+ /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
+ OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)
+
+ /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
+ OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+ /* 0x4a10010e abe_clks.abe_clks ah26 */
+ OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ >;
+ };
+};
+
+&mcpdm_module {
+ /*
+ * McPDM pads must be muxed at the interconnect target module
+ * level as the module on the SoC needs external clock from
+ * the PMIC
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcpdm_pins>;
+ status = "okay";
+};
+
+&mcpdm {
+ clocks = <&twl6040>;
+ clock-names = "pdmclk";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include <dt-bindings/input/input.h>
+#include "elpida_ecb240abacn.dtsi"
+#include "omap4-mcpdm.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display0 = &dvi0;
+ display1 = &hdmi0;
+ ethernet = ðernet;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &led_wkgpio_pins
+ >;
+
+ heartbeat {
+ label = "pandaboard::status1";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc {
+ label = "pandaboard::status2";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ gpio_keys: gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &button_pins
+ >;
+
+ buttonS2 {
+ label = "button S2";
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */
+ linux,code = <BTN_0>;
+ wakeup-source;
+ };
+ };
+
+ sound: sound {
+ compatible = "ti,abe-twl6040";
+ ti,model = "PandaBoard";
+
+ ti,mclk-freq = <38400000>;
+
+ ti,mcpdm = <&mcpdm>;
+
+ ti,twl6040 = <&twl6040>;
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Ext Spk", "HFL",
+ "Ext Spk", "HFR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "HSMIC", "Headset Mic",
+ "Headset Mic", "Headset Mic Bias",
+ "AFML", "Line In",
+ "AFMR", "Line In";
+ };
+
+ /* HS USB Port 1 Power */
+ hsusb1_power: hsusb1_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ /*
+ * boot-on is required along with always-on as the
+ * regulator framework doesn't enable the regulator
+ * if boot-on is not there.
+ */
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
+ #phy-cells = <0>;
+ vcc-supply = <&hsusb1_power>;
+ clocks = <&auxclk3_ck>;
+ clock-names = "main_clk";
+ clock-frequency = <19200000>;
+ };
+
+ /* regulator for wl12xx on sdio5 */
+ wl12xx_vmmc: wl12xx_vmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_gpio>;
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ tfp410: encoder0 {
+ compatible = "ti,tfp410";
+ powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ dvi0: connector0 {
+ compatible = "dvi-connector";
+ label = "dvi";
+
+ digital;
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder1 {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
+ <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
+ <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector1 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+};
+
+&omap4_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &dss_dpi_pins
+ &tfp410_pins
+ &dss_hdmi_pins
+ &tpd12s015_pins
+ &hsusbb1_pins
+ >;
+
+ twl6040_pins: pinmux_twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
+ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
+ >;
+ };
+
+ mcbsp1_pins: pinmux_mcbsp1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+ OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+ OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
+ >;
+ };
+
+ dss_dpi_pins: pinmux_dss_dpi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */
+ OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */
+ OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */
+ OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */
+ OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */
+ OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */
+ OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */
+ OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */
+ OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */
+ OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */
+ OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */
+
+ OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */
+ OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */
+ OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */
+ OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */
+ OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */
+ OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */
+ OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */
+ OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */
+ OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */
+ OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */
+ OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */
+ OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */
+ OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */
+
+ OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */
+ OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */
+ OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */
+ >;
+ };
+
+ tfp410_pins: pinmux_tfp410_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */
+ >;
+ };
+
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
+ OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
+ >;
+ };
+
+ hsusbb1_pins: pinmux_hsusbb1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+ OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+ OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+ OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+ OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+ OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+ OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+ OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+ OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+ OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+ OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
+ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
+ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
+
+ i2c4_pins: pinmux_i2c4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
+ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
+ >;
+ };
+
+ /*
+ * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
+ * REVISIT: Are the pull-ups needed for GPIO 48 and 49?
+ */
+ wl12xx_gpio: pinmux_wl12xx_gpio {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
+ OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */
+ OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */
+ OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */
+ >;
+ };
+
+ /* wl12xx GPIO inputs and SDIO pins */
+ wl12xx_pins: pinmux_wl12xx_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
+ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
+ OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
+ OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
+ OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
+ OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
+ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
+ >;
+ };
+
+ button_pins: pinmux_button_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
+ OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ >;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ clock-frequency = <400000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ /* IRQ# = 7 */
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
+ };
+
+ twl6040: twl@4b {
+ compatible = "ti,twl6040";
+ #clock-cells = <0>;
+ reg = <0x4b>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&twl6040_pins>;
+
+ /* IRQ# = 119 */
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
+ ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
+
+ vio-supply = <&v1v8>;
+ v2v1-supply = <&v2v1>;
+ enable-active-high;
+ };
+};
+
+#include "twl6030.dtsi"
+#include "twl6030_omap4.dtsi"
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+
+ clock-frequency = <100000>;
+
+ /*
+ * Display monitor features are burnt in their EEPROM as EDID data.
+ * The EEPROM is connected as I2C slave device.
+ */
+ eeprom@50 {
+ compatible = "ti,eeprom";
+ reg = <0x50>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&mmc4 {
+ status = "disabled";
+};
+
+&mmc5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_pins>;
+ vmmc-supply = <&wl12xx_vmmc>;
+ interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x10e>;
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ /* gpio_53 with gpmc_ncs3 pad as wakeup */
+ interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&omap4_pmx_core 0x3a>;
+ interrupt-names = "irq", "wakeup";
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+&emif1 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&mcbsp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp1_pins>;
+ status = "okay";
+};
+
+&twl_usb_comparator {
+ usb-supply = <&vusb>;
+};
+
+&uart2 {
+ interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART2_RX>;
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART3_RX>;
+};
+
+&uart4 {
+ interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART4_RX>;
+};
+
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
+
+&usbhshost {
+ port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&dsi2 {
+ status = "ok";
+ vdd-supply = <&vcxio>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&vdac>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
+
+/ {
+ model = "TI OMAP4 PandaBoard-ES";
+ compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
+};
+
+/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
+&sound {
+ ti,model = "PandaBoardES";
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Ext Spk", "HFL",
+ "Ext Spk", "HFR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "AFML", "Line In",
+ "AFMR", "Line In";
+};
+
+/* PandaboardES has external pullups on SCL & SDA */
+&dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+};
+
+&omap4_pmx_core {
+ led_gpio_pins: gpio_led_pmx {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
+ >;
+ };
+
+ button_pins: pinmux_button_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
+ >;
+ };
+};
+
+&led_wkgpio_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ >;
+};
+
+&leds {
+ pinctrl-0 = <
+ &led_gpio_pins
+ &led_wkgpio_pins
+ >;
+
+ heartbeat {
+ gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+ };
+ mmc {
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&gpio_keys {
+ buttonS2 {
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */
+ };
+};
+
+&gpio1_target {
+ ti,no-reset-on-init;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
+
+/ {
+ model = "TI OMAP4 PandaBoard";
+ compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "omap4-sdp.dts"
+
+/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
+&dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
+#include "omap4-mcpdm.dtsi"
+
+/ {
+ model = "TI OMAP4 SDP board";
+ compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+
+ aliases {
+ display0 = &lcd0;
+ display1 = &lcd1;
+ display2 = &hdmi0;
+ };
+
+ vdd_eth: fixedregulator-vdd-eth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&enet_enable_gpio>;
+
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_ETH";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */
+ enable-active-high;
+ regulator-boot-on;
+ startup-delay-us = <25000>;
+ };
+
+ vbat: fixedregulator-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "VBAT";
+ regulator-min-microvolt = <3750000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ debug0 {
+ label = "omap4:green:debug0";
+ gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
+ };
+
+ debug1 {
+ label = "omap4:green:debug1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
+ };
+
+ debug2 {
+ label = "omap4:green:debug2";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
+ };
+
+ debug3 {
+ label = "omap4:green:debug3";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
+ };
+
+ debug4 {
+ label = "omap4:green:debug4";
+ gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
+ };
+
+ user1 {
+ label = "omap4:blue:user";
+ gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
+ };
+
+ user2 {
+ label = "omap4:red:user";
+ gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
+ };
+
+ user3 {
+ label = "omap4:green:user";
+ gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+ kpad {
+ label = "omap4::keypad";
+ pwms = <&twl_pwm 0 7812500>;
+ max-brightness = <127>;
+ };
+
+ charging {
+ label = "omap4:green:chrg";
+ pwms = <&twl_pwmled 0 7812500>;
+ max-brightness = <255>;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&twl_pwm 1 7812500>;
+ brightness-levels = <
+ 0 10 20 30 40
+ 50 60 70 80 90
+ 100 110 120 127
+ >;
+ default-brightness-level = <13>;
+ };
+
+ sound {
+ compatible = "ti,abe-twl6040";
+ ti,model = "SDP4430";
+
+ ti,jack-detection = <1>;
+ ti,mclk-freq = <38400000>;
+
+ ti,mcpdm = <&mcpdm>;
+ ti,dmic = <&dmic>;
+
+ ti,twl6040 = <&twl6040>;
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Earphone Spk", "EP",
+ "Ext Spk", "HFL",
+ "Ext Spk", "HFR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "Vibrator", "VIBRAL",
+ "Vibrator", "VIBRAR",
+ "HSMIC", "Headset Mic",
+ "Headset Mic", "Headset Mic Bias",
+ "MAINMIC", "Main Handset Mic",
+ "Main Handset Mic", "Main Mic Bias",
+ "SUBMIC", "Sub Handset Mic",
+ "Sub Handset Mic", "Main Mic Bias",
+ "AFML", "Line In",
+ "AFMR", "Line In",
+ "DMic", "Digital Mic",
+ "Digital Mic", "Digital Mic1 Bias";
+ };
+
+ /* regulator for wl12xx on sdio5 */
+ wl12xx_vmmc: wl12xx_vmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_gpio>;
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
+ <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
+ <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "c";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+};
+
+&omap4_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &dss_hdmi_pins
+ &tpd12s015_pins
+ >;
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
+ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
+ OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */
+ OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
+ OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+ >;
+ };
+
+ uart4_pins: pinmux_uart4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */
+ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */
+ >;
+ };
+
+ twl6040_pins: pinmux_twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
+ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
+ >;
+ };
+
+ dmic_pins: pinmux_dmic_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */
+ OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */
+ OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */
+ OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */
+ >;
+ };
+
+ mcbsp1_pins: pinmux_mcbsp1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+ OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+ OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
+ >;
+ };
+
+ mcbsp2_pins: pinmux_mcbsp2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
+ OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */
+ OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */
+ OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
+ >;
+ };
+
+ mcspi1_pins: pinmux_mcspi1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
+ OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
+ OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
+ OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
+ >;
+ };
+
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
+ OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
+ OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
+ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
+ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
+
+ i2c4_pins: pinmux_i2c4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
+ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
+ >;
+ };
+
+ /* wl12xx GPIO output for WLAN_EN */
+ wl12xx_gpio: pinmux_wl12xx_gpio {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */
+ >;
+ };
+
+ /* wl12xx GPIO inputs and SDIO pins */
+ wl12xx_pins: pinmux_wl12xx_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
+ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
+ OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
+ OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
+ OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
+ OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
+ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
+ >;
+ };
+
+ /* gpio_48 for ENET_ENABLE */
+ enet_enable_gpio: pinmux_enet_enable_gpio {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */
+ >;
+ };
+
+ ks8851_pins: pinmux_ks8851_pins {
+ pinctrl-single,pins = <
+ /* ENET_INT */
+ OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */
+ /*
+ * Misterious pin which makes the ethernet working
+ * The legacy board file requested this pin on boot
+ * (ETH_KS8851_QUART) and set it to high, similarly to
+ * the ENET_ENABLE pin.
+ * We could use gpio-hog to keep it high, but let's use
+ * it as a reset GPIO for ks8851.
+ */
+ OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */
+ >;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ clock-frequency = <400000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
+ };
+
+ twl6040: twl@4b {
+ compatible = "ti,twl6040";
+ #clock-cells = <0>;
+ reg = <0x4b>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&twl6040_pins>;
+
+ /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
+ ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
+
+ vio-supply = <&v1v8>;
+ v2v1-supply = <&v2v1>;
+ enable-active-high;
+
+ /* regulators for vibra motor */
+ vddvibl-supply = <&vbat>;
+ vddvibr-supply = <&vbat>;
+
+ vibra {
+ /* Vibra driver, motor resistance parameters */
+ ti,vibldrv-res = <8>;
+ ti,vibrdrv-res = <3>;
+ ti,viblmotor-res = <10>;
+ ti,vibrmotor-res = <10>;
+ };
+ };
+};
+
+#include "twl6030.dtsi"
+#include "twl6030_omap4.dtsi"
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+
+ clock-frequency = <400000>;
+
+ /*
+ * Temperature Sensor
+ * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+ */
+ tmp105@48 {
+ compatible = "ti,tmp105";
+ reg = <0x48>;
+ };
+
+ /*
+ * Ambient Light Sensor
+ * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
+ */
+ bh1780@29 {
+ compatible = "rohm,bh1780";
+ reg = <0x29>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+
+ clock-frequency = <400000>;
+
+ /*
+ * 3-Axis Digital Compass
+ * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+ */
+ hmc5843@1e {
+ compatible = "honeywell,hmc5843";
+ reg = <0x1e>;
+ };
+};
+
+&mcspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi1_pins>;
+
+ eth@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ks8851_pins>;
+
+ compatible = "ks8851";
+ spi-max-frequency = <24000000>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
+ vdd-supply = <&vdd_eth>;
+ reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vaux1>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&mmc4 {
+ status = "disabled";
+};
+
+&mmc5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_pins>;
+ vmmc-supply = <&wl12xx_vmmc>;
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1281";
+ reg = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&emif1 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&keypad {
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ linux,keymap = <0x00000012 /* KEY_E */
+ 0x00010013 /* KEY_R */
+ 0x00020014 /* KEY_T */
+ 0x00030066 /* KEY_HOME */
+ 0x0004003f /* KEY_F5 */
+ 0x000500f0 /* KEY_UNKNOWN */
+ 0x00060017 /* KEY_I */
+ 0x0007002a /* KEY_LEFTSHIFT */
+ 0x01000020 /* KEY_D*/
+ 0x01010021 /* KEY_F */
+ 0x01020022 /* KEY_G */
+ 0x010300e7 /* KEY_SEND */
+ 0x01040040 /* KEY_F6 */
+ 0x010500f0 /* KEY_UNKNOWN */
+ 0x01060025 /* KEY_K */
+ 0x0107001c /* KEY_ENTER */
+ 0x0200002d /* KEY_X */
+ 0x0201002e /* KEY_C */
+ 0x0202002f /* KEY_V */
+ 0x0203006b /* KEY_END */
+ 0x02040041 /* KEY_F7 */
+ 0x020500f0 /* KEY_UNKNOWN */
+ 0x02060034 /* KEY_DOT */
+ 0x0207003a /* KEY_CAPSLOCK */
+ 0x0300002c /* KEY_Z */
+ 0x0301004e /* KEY_KPLUS */
+ 0x03020030 /* KEY_B */
+ 0x0303003b /* KEY_F1 */
+ 0x03040042 /* KEY_F8 */
+ 0x030500f0 /* KEY_UNKNOWN */
+ 0x03060018 /* KEY_O */
+ 0x03070039 /* KEY_SPACE */
+ 0x04000011 /* KEY_W */
+ 0x04010015 /* KEY_Y */
+ 0x04020016 /* KEY_U */
+ 0x0403003c /* KEY_F2 */
+ 0x04040073 /* KEY_VOLUMEUP */
+ 0x040500f0 /* KEY_UNKNOWN */
+ 0x04060026 /* KEY_L */
+ 0x04070069 /* KEY_LEFT */
+ 0x0500001f /* KEY_S */
+ 0x05010023 /* KEY_H */
+ 0x05020024 /* KEY_J */
+ 0x0503003d /* KEY_F3 */
+ 0x05040043 /* KEY_F9 */
+ 0x05050072 /* KEY_VOLUMEDOWN */
+ 0x05060032 /* KEY_M */
+ 0x0507006a /* KEY_RIGHT */
+ 0x06000010 /* KEY_Q */
+ 0x0601001e /* KEY_A */
+ 0x06020031 /* KEY_N */
+ 0x0603009e /* KEY_BACK */
+ 0x0604000e /* KEY_BACKSPACE */
+ 0x060500f0 /* KEY_UNKNOWN */
+ 0x06060019 /* KEY_P */
+ 0x06070067 /* KEY_UP */
+ 0x07000094 /* KEY_PROG1 */
+ 0x07010095 /* KEY_PROG2 */
+ 0x070200ca /* KEY_PROG3 */
+ 0x070300cb /* KEY_PROG4 */
+ 0x0704003e /* KEY_F4 */
+ 0x070500f0 /* KEY_UNKNOWN */
+ 0x07060160 /* KEY_OK */
+ 0x0707006c>; /* KEY_DOWN */
+ linux,input-no-autorepeat;
+};
+
+&uart2 {
+ interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART2_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART3_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+ interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core OMAP4_UART4_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+};
+
+&mcbsp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp1_pins>;
+ status = "okay";
+};
+
+&mcbsp2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp2_pins>;
+ status = "okay";
+};
+
+&dmic {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dmic_pins>;
+ status = "okay";
+};
+
+&twl_usb_comparator {
+ usb-supply = <&vusb>;
+};
+
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
+
+&dss {
+ status = "ok";
+};
+
+&dsi1 {
+ status = "ok";
+ vdd-supply = <&vcxio>;
+
+ port {
+ dsi1_out_ep: endpoint {
+ remote-endpoint = <&lcd0_in>;
+ lanes = <0 1 2 3 4 5>;
+ };
+ };
+
+ lcd0: display {
+ compatible = "tpo,taal", "panel-dsi-cm";
+ label = "lcd0";
+
+ reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
+
+ port {
+ lcd0_in: endpoint {
+ remote-endpoint = <&dsi1_out_ep>;
+ };
+ };
+ };
+};
+
+&dsi2 {
+ status = "ok";
+ vdd-supply = <&vcxio>;
+
+ port {
+ dsi2_out_ep: endpoint {
+ remote-endpoint = <&lcd1_in>;
+ lanes = <0 1 2 3 4 5>;
+ };
+ };
+
+ lcd1: display {
+ compatible = "tpo,taal", "panel-dsi-cm";
+ label = "lcd1";
+
+ reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
+
+ port {
+ lcd1_in: endpoint {
+ remote-endpoint = <&dsi2_out_ep>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&vdac>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2020 Tero Kristo <t-kristo@ti.com>
+ */
+
+&l4_cfg {
+ segment@0 {
+ /* SCM Core */
+ target-module@2000 {
+ compatible = "simple-bus";
+ };
+
+ /* USB HS */
+ target-module@64000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+&l4_per {
+ segment@0 {
+ /* UART3 */
+ target-module@20000 {
+ compatible = "simple-bus";
+ };
+
+ /* I2C1 */
+ target-module@70000 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC1 */
+ target-module@9c000 {
+ compatible = "simple-bus";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/clock/omap4.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap4.h>
+
+/ {
+ compatible = "ti,omap4430", "ti,omap4";
+ interrupt-parent = <&wakeupgen>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&L2>;
+ reg = <0x0>;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&L2>;
+ reg = <0x1>;
+ };
+ };
+
+ /*
+ * Note that 4430 needs cross trigger interface (CTI) supported
+ * before we can configure the interrupts. This means sampling
+ * events are not supported for pmu. Note that 4460 does not use
+ * CTI, see also 4460.dtsi.
+ */
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ ti,hwmods = "debugss";
+ };
+
+ gic: interrupt-controller@48241000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48241000 0x1000>,
+ <0x48240100 0x0100>;
+ interrupt-parent = <&gic>;
+ };
+
+ L2: l2-cache-controller@48242000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x48242000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ local-timer@48240600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ clocks = <&mpu_periphclk>;
+ reg = <0x48240600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
+ interrupt-parent = <&gic>;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = "ti,omap4-wugen-mpu";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48281000 0x1000>;
+ interrupt-parent = <&gic>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap4-mpu";
+ ti,hwmods = "mpu";
+ sram = <&ocmcram>;
+ };
+
+ dsp {
+ compatible = "ti,omap3-c64";
+ };
+
+ iva {
+ compatible = "ti,ivahd";
+ ti,hwmods = "iva";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP4 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+ reg = <0x44000000 0x1000>,
+ <0x44800000 0x2000>,
+ <0x45000000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ l4_wkup: interconnect@4a300000 {
+ };
+
+ l4_cfg: interconnect@4a000000 {
+ };
+
+ l4_per: interconnect@48000000 {
+ };
+
+ l4_abe: interconnect@40100000 {
+ };
+
+ ocmcram: sram@40304000 {
+ compatible = "mmio-sram";
+ reg = <0x40304000 0xa000>; /* 40k */
+ };
+
+ gpmc: gpmc@50000000 {
+ compatible = "ti,omap4430-gpmc";
+ reg = <0x50000000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 4>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <4>;
+ ti,hwmods = "gpmc";
+ ti,no-idle-on-init;
+ clocks = <&l3_div_ck>;
+ clock-names = "fck";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ target-module@52000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "iss";
+ reg = <0x52000000 0x4>,
+ <0x52000010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-delay-us = <2>;
+ clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x52000000 0x1000000>;
+
+ /* No child device binding, driver in staging */
+ };
+
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
+ };
+
+ target-module@4012c000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x4012c000 0x4>,
+ <0x4012c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
+ <0x4902c000 0x4902c000 0x1000>; /* L3 */
+
+ /* No child device binding or driver in mainline */
+ };
+
+ dmm@4e000000 {
+ compatible = "ti,omap4-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
+ emif1: emif@4c000000 {
+ compatible = "ti,emif-4d";
+ reg = <0x4c000000 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "emif1";
+ ti,no-idle-on-init;
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ emif2: emif@4d000000 {
+ compatible = "ti,emif-4d";
+ reg = <0x4d000000 0x100>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "emif2";
+ ti,no-idle-on-init;
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ aes1_target: target-module@4b501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b501080 0x4>,
+ <0x4b501084 0x4>,
+ <0x4b501088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b501000 0x1000>;
+
+ aes1: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 111>, <&sdma 110>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ aes2_target: target-module@4b701000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b701080 0x4>,
+ <0x4b701084 0x4>,
+ <0x4b701088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b701000 0x1000>;
+
+ aes2: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 114>, <&sdma 113>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ sham_target: target-module@4b100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x4b100100 0x4>,
+ <0x4b100110 0x4>,
+ <0x4b100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap4-sham";
+ reg = <0 0x300>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 119>;
+ dma-names = "rx";
+ };
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ ti,tranxdone-status-mask = <0x80>;
+ clocks = <&sys_clkin_ck>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ status = "disabled";
+ };
+
+ abb_iva: regulator-abb-iva {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_iva";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ ti,tranxdone-status-mask = <0x80000000>;
+ clocks = <&sys_clkin_ck>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ status = "disabled";
+ };
+
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x2000000>;
+
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
+ };
+
+ /*
+ * DSS is only using l3 mapping without l4 as noted in the TRM
+ * "10.1.3 DSS Register Manual" for omap4460.
+ */
+ target-module@58000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000000 4>,
+ <0x58000014 4>;
+ reg-names = "rev", "syss";
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x58000000 0x1000000>;
+
+ dss: dss@0 {
+ compatible = "ti,omap4-dss";
+ reg = <0 0x80>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000000>;
+
+ target-module@1000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x1000 0x4>,
+ <0x1010 0x4>,
+ <0x1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x1000>;
+
+ dispc@0 {
+ compatible = "ti,omap4-dispc";
+ reg = <0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@2000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>,
+ <0x2014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x1000>;
+
+ rfbi: encoder@0 {
+ reg = <0 0x1000>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
+ clock-names = "fck", "ick";
+ };
+ };
+
+ target-module@3000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x3000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x3000 0x1000>;
+
+ venc: encoder@0 {
+ compatible = "ti,omap4-venc";
+ reg = <0 0x1000>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@4000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x1000>;
+
+ dsi1: encoder@0 {
+ compatible = "ti,omap4-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+
+ target-module@5000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5000 0x4>,
+ <0x5010 0x4>,
+ <0x5014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5000 0x1000>;
+
+ dsi2: encoder@0 {
+ compatible = "ti,omap4-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+
+ target-module@6000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x6000 0x4>,
+ <0x6010 0x4>;
+ reg-names = "rev", "sysc";
+ /*
+ * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
+ * but HDMI audio will fail with them.
+ */
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck", "dss_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x2000>;
+
+ hdmi: encoder@0 {
+ compatible = "ti,omap4-hdmi";
+ reg = <0 0x200>,
+ <0x200 0x100>,
+ <0x300 0x100>,
+ <0x400 0x1000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ dmas = <&sdma 76>;
+ dma-names = "audio_tx";
+ };
+ };
+ };
+ };
+ };
+};
+
+#include "omap4-l4.dtsi"
+#include "omap4-l4-abe.dtsi"
+#include "omap44xx-clocks.dtsi"
+
+&prm {
+ prm_tesla: prm@400 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_ivahd: prm@f00 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@1b00 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&prm_clocks {
+ bandgap_fclk: bandgap_fclk@1888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1888>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for OMAP443x SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "omap4.dtsi"
+
+/ {
+ cpus {
+ cpu0: cpu@0 {
+ /* OMAP443x variants OPP50-OPPNT */
+ operating-points = <
+ /* kHz uV */
+ 300000 1025000
+ 600000 1200000
+ 800000 1313000
+ 1008000 1375000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ };
+
+ ocp {
+ bandgap: bandgap@4a002260 {
+ reg = <0x4a002260 0x4
+ 0x4a00232C 0x4>;
+ compatible = "ti,omap4430-bandgap";
+
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ ocp {
+ abb_mpu: regulator-abb-mpu {
+ status = "okay";
+
+ reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>;
+ reg-names = "base-address", "int-address";
+
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0 0 0 0
+ 1200000 0 0 0 0 0
+ 1313000 0 0 0 0 0
+ 1375000 1 0 0 0 0
+ 1389000 1 0 0 0 0
+ >;
+ };
+
+ /* Default unused, just provide register info for record */
+ abb_iva: regulator-abb-iva {
+ reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>;
+ reg-names = "base-address", "int-address";
+ };
+
+ };
+
+};
+
+&cpu_thermal {
+ coefficients = <0 20000>;
+};
+
+/include/ "omap443x-clocks.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for OMAP4460 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include "omap4.dtsi"
+
+/ {
+ cpus {
+ /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
+ cpu0: cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 350000 1025000
+ 700000 1200000
+ 920000 1313000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "debugss";
+ };
+
+ thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ };
+
+ ocp {
+ bandgap: bandgap@4a002260 {
+ reg = <0x4a002260 0x4
+ 0x4a00232C 0x4
+ 0x4a002378 0x18>;
+ compatible = "ti,omap4460-bandgap";
+ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
+
+ #thermal-sensor-cells = <0>;
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ status = "okay";
+
+ reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
+ <0x4A002268 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address";
+
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0 0 0 0
+ 1200000 0 0 0 0 0
+ 1313000 0 0 0x100000 0x40000 0
+ 1375000 1 0 0 0 0
+ 1389000 1 0 0 0 0
+ >;
+ };
+
+ abb_iva: regulator-abb-iva {
+ status = "okay";
+
+ reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
+ <0x4A002268 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address";
+
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 950000 0 0 0 0 0
+ 1140000 0 0 0 0 0
+ 1291000 0 0 0x200000 0 0
+ 1375000 1 0 0 0 0
+ 1376000 1 0 0 0 0
+ >;
+ };
+ };
+
+};
+
+&cpu_thermal {
+ coefficients = <348 (-9301)>;
+};
+
+/* Only some L4 CFG interconnect ranges are different on 4460 */
+&l4_cfg_segment_300000 {
+ ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
+ <0x00040000 0x00340000 0x001000>, /* ap 68 */
+ <0x00020000 0x00320000 0x004000>, /* ap 71 */
+ <0x00024000 0x00324000 0x002000>, /* ap 72 */
+ <0x00026000 0x00326000 0x001000>, /* ap 73 */
+ <0x00027000 0x00327000 0x001000>, /* ap 74 */
+ <0x00028000 0x00328000 0x001000>, /* ap 75 */
+ <0x00029000 0x00329000 0x001000>, /* ap 76 */
+ <0x00030000 0x00330000 0x010000>, /* ap 77 */
+ <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
+ <0x0002c000 0x0032c000 0x004000>, /* ap 91 */
+ <0x00010000 0x00310000 0x008000>, /* ap 92 */
+ <0x00018000 0x00318000 0x004000>, /* ap 93 */
+ <0x0001c000 0x0031c000 0x002000>, /* ap 94 */
+ <0x0001e000 0x0031e000 0x002000>; /* ap 95 */
+};
+
+&l4_cfg_target_0 {
+ ranges = <0x00000000 0x00000000 0x00010000>,
+ <0x00010000 0x00010000 0x00008000>,
+ <0x00018000 0x00018000 0x00004000>,
+ <0x0001c000 0x0001c000 0x00002000>,
+ <0x0001e000 0x0001e000 0x00002000>,
+ <0x00020000 0x00020000 0x00004000>,
+ <0x00024000 0x00024000 0x00002000>,
+ <0x00026000 0x00026000 0x00001000>,
+ <0x00027000 0x00027000 0x00001000>,
+ <0x00028000 0x00028000 0x00001000>,
+ <0x00029000 0x00029000 0x00001000>,
+ <0x0002a000 0x0002a000 0x00002000>,
+ <0x0002c000 0x0002c000 0x00004000>,
+ <0x00030000 0x00030000 0x00010000>;
+};
+
+/include/ "omap446x-clocks.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&prm_clocks {
+ div_ts_ck: div_ts_ck@1888 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1888>;
+ ti,dividers = <8>, <16>, <32>;
+ };
+
+ bandgap_ts_fclk: bandgap_ts_fclk@1888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&div_ts_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1888>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&cm1_clocks {
+ extalt_clkin_ck: extalt_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <59000000>;
+ };
+
+ pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ pad_clks_ck: pad_clks_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0108>;
+ };
+
+ pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ slimbus_clk: slimbus_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x0108>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ };
+
+ virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ tie_low_clock_ck: tie_low_clock_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60motg_ck: xclk60motg_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ dpll_abe_ck: dpll_abe_ck@1e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+ reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+ };
+
+ dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x01f0>;
+ };
+
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ abe_clk: abe_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x0108>;
+ ti,index-power-of-two;
+ };
+
+
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f4>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x012c>;
+ };
+
+ dpll_core_ck: dpll_core_ck@120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+ reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+ };
+
+ dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+ };
+
+ dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0140>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_m2_ck: dpll_core_m2_ck@130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0130>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ ddrphy_ck: ddrphy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x013c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ div_core_ck: div_core_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x0100>;
+ ti,max-div = <2>;
+ };
+
+ div_iva_hs_clk: div_iva_hs_clk@1dc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x01dc>;
+ ti,index-power-of-two;
+ };
+
+ div_mpu_hs_clk: div_mpu_hs_clk@19c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x019c>;
+ ti,index-power-of-two;
+ };
+
+ dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0138>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dll_clk_div_ck: dll_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ ti,max-div = <31>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0134>;
+ };
+
+ dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0134>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
+ };
+
+ dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0144>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+ ti,bit-shift = <23>;
+ reg = <0x01ac>;
+ };
+
+ dpll_iva_ck: dpll_iva_ck@1a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+ reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <931200000>;
+ };
+
+ dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+ };
+
+ dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01b8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m4x2_ck>;
+ assigned-clock-rates = <465600000>;
+ };
+
+ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01bc>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m5x2_ck>;
+ assigned-clock-rates = <266100000>;
+ };
+
+ dpll_mpu_ck: dpll_mpu_ck@160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+ reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+ };
+
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0170>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ per_hs_clk_div_ck: per_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ l3_div_ck: l3_div_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&div_core_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <2>;
+ reg = <0x0100>;
+ };
+
+ l4_div_ck: l4_div_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <2>;
+ reg = <0x0100>;
+ };
+
+ lp_clk_div_ck: lp_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ mpu_periphclk: mpu_periphclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ ocp_abe_iclk: ocp_abe_iclk@528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
+ ti,bit-shift = <24>;
+ reg = <0x0528>;
+ ti,dividers = <2>, <1>;
+ };
+
+ per_abe_24m_fclk: per_abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
+&prm_clocks {
+ sys_clkin_ck: sys_clkin_ck@110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x0110>;
+ ti,index-starts-at-one;
+ };
+
+ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0108>;
+ };
+
+ abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ reg = <0x010c>;
+ };
+
+ dbgclk_mux_ck: dbgclk_mux_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+ reg = <0x0108>;
+ };
+
+ syc_clk_div_ck: syc_clk_div_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x0100>;
+ ti,max-div = <2>;
+ };
+
+ usim_ck: usim_ck@1858 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1858>;
+ ti,dividers = <14>, <18>;
+ };
+
+ usim_fclk: usim_fclk@1858 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&usim_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1858>;
+ };
+
+ trace_clk_div_ck: trace_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
+ };
+};
+
+&prm_clockdomains {
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+};
+
+&cm2_clocks {
+ per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x014c>;
+ };
+
+ dpll_per_ck: dpll_per_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+ reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+ };
+
+ dpll_per_m2_ck: dpll_per_m2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_x2_ck: dpll_per_x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x0150>;
+ };
+
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0154>;
+ };
+
+ dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
+ };
+
+ dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0160>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0164>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_usb_ck: dpll_usb_ck@180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+ reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+ };
+
+ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,clock-div = <1>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01b4>;
+ ti,clock-mult = <1>;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0190>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+ reg = <0x0100>;
+ };
+
+ func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_24mc_fclk: func_24mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ func_48m_fclk: func_48m_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x0108>;
+ ti,dividers = <4>, <8>;
+ };
+
+ func_48mc_fclk: func_48mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_64m_fclk: func_64m_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ reg = <0x0108>;
+ ti,dividers = <2>, <4>;
+ };
+
+ func_96m_fclk: func_96m_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x0108>;
+ ti,dividers = <2>, <4>;
+ };
+
+ init_60m_fclk: init_60m_fclk@104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x0104>;
+ ti,dividers = <1>, <8>;
+ };
+
+ per_abe_nc_fclk: per_abe_nc_fclk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x0108>;
+ ti,max-div = <2>;
+ };
+
+ sha2md5_fck: sha2md5_fck@15c8 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x15c8>;
+ };
+
+ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0640>;
+ };
+};
+
+&cm2_clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+};
+
+&scrm_clocks {
+ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_ck: auxclk0_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+ };
+
+ auxclk0_ck: auxclk0_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0310>;
+ };
+
+ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_ck: auxclk1_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+ };
+
+ auxclk1_ck: auxclk1_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0314>;
+ };
+
+ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_ck: auxclk2_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+ };
+
+ auxclk2_ck: auxclk2_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0318>;
+ };
+
+ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_ck: auxclk3_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+ };
+
+ auxclk3_ck: auxclk3_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x031c>;
+ };
+
+ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_ck: auxclk4_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+ };
+
+ auxclk4_ck: auxclk4_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0320>;
+ };
+
+ auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0324>;
+ };
+
+ auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0324>;
+ };
+
+ auxclk5_src_ck: auxclk5_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
+ };
+
+ auxclk5_ck: auxclk5_ck@324 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk5_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0324>;
+ };
+
+ auxclkreq0_ck: auxclkreq0_ck@210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0210>;
+ };
+
+ auxclkreq1_ck: auxclkreq1_ck@214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0214>;
+ };
+
+ auxclkreq2_ck: auxclkreq2_ck@218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0218>;
+ };
+
+ auxclkreq3_ck: auxclkreq3_ck@21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x021c>;
+ };
+
+ auxclkreq4_ck: auxclkreq4_ck@220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0220>;
+ };
+
+ auxclkreq5_ck: auxclkreq5_ck@224 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0224>;
+ };
+};
+
+&cm1 {
+ mpuss_cm: mpuss_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpuss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ tesla_cm: tesla_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ tesla_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x6c>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm2 {
+ l4_ao_cm: l4_ao_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ l4_ao_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_1_cm: l3_1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3_1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_2_cm: l3_2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3_2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ducati_cm: ducati_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ducati_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dma_cm: l3_dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ l3_dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_emif_cm: l3_emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ l3_emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ d2d_cm: d2d_cm@c00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xc00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xc00 0x100>;
+
+ d2d_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_cfg_cm: l4_cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4_cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_instr_cm: l3_instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3_instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x24>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ivahd_cm: ivahd_cm@f00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xf00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xf00 0x100>;
+
+ ivahd_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ iss_cm: iss_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x100>;
+
+ iss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dss_cm: l3_dss_cm@1100 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1100 0x100>;
+
+ l3_dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_gfx_cm: l3_gfx_cm@1200 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1200 0x100>;
+
+ l3_gfx_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_init_cm: l3_init_cm@1300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1300 0x100>;
+
+ l3_init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_per_cm: l4_per_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x200>;
+
+ l4_per_clkctrl: clock@20 {
+ compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
+ reg = <0x20 0x144>;
+ #clock-cells = <2>;
+ };
+
+ l4_secure_clkctrl: clock@1a0 {
+ compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
+ reg = <0x1a0 0x3c>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&prm {
+ l4_wkup_cm: l4_wkup_cm@1800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1800 0x100>;
+
+ l4_wkup_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emu_sys_cm: emu_sys_cm@1a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1a00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1a00 0x100>;
+
+ emu_sys_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "omap5.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ aliases {
+ display0 = &hdmi0;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ vmain: fixedregulator-vmain {
+ compatible = "regulator-fixed";
+ regulator-name = "vmain";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vsys_cobra: fixedregulator-vsys_cobra {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_cobra";
+ vin-supply = <&vmain>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vdds_1v8_main: fixedregulator-vdds_1v8_main {
+ compatible = "regulator-fixed";
+ regulator-name = "vdds_1v8_main";
+ vin-supply = <&smps7_reg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vmmcsd_fixed: fixedregulator-mmcsd {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ mmc3_pwrseq: sdhci0_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&clk32kgaudio>;
+ clock-names = "ext_clock";
+ };
+
+ vmmcsdio_fixed: fixedregulator-mmcsdio {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsdio_fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */
+ enable-active-high;
+ startup-delay-us = <70000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_pins>;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
+ clocks = <&auxclk1_ck>;
+ clock-names = "main_clk";
+ clock-frequency = <19200000>;
+ #phy-cells = <0>;
+ };
+
+ /* HS USB Host PHY on PORT 3 */
+ hsusb3_phy: hsusb3_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
+ #phy-cells = <0>;
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tpd12s015_pins>;
+
+ /* gpios defined in the board specific dts */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "b";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ sound: sound {
+ compatible = "ti,abe-twl6040";
+ ti,model = "omap5-uevm";
+
+ ti,jack-detection;
+ ti,mclk-freq = <19200000>;
+
+ ti,mcpdm = <&mcpdm>;
+
+ ti,twl6040 = <&twl6040>;
+
+ /* Audio routing */
+ ti,audio-routing =
+ "Headset Stereophone", "HSOL",
+ "Headset Stereophone", "HSOR",
+ "Line Out", "AUXL",
+ "Line Out", "AUXR",
+ "HSMIC", "Headset Mic",
+ "Headset Mic", "Headset Mic Bias",
+ "AFML", "Line In",
+ "AFMR", "Line In";
+ };
+};
+
+&gpio8 {
+ /* TI trees use GPIO instead of msecure, see also muxing */
+ p234 {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "gpio8_234/msecure";
+ };
+};
+
+&omap5_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &usbhost_pins
+ &led_gpio_pins
+ >;
+
+ twl6040_pins: pinmux_twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
+ >;
+ };
+
+ mcpdm_pins: pinmux_mcpdm_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
+ OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
+ OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
+ OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
+ OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
+ >;
+ };
+
+ mcbsp1_pins: pinmux_mcbsp1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
+ OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
+ OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
+ OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
+ >;
+ };
+
+ mcbsp2_pins: pinmux_mcbsp2_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
+ OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
+ OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
+ OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+ OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+ >;
+ };
+
+ mcspi2_pins: pinmux_mcspi2_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
+ OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
+ OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
+ OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
+ >;
+ };
+
+ mcspi3_pins: pinmux_mcspi3_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
+ OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
+ OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
+ OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
+ >;
+ };
+
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
+ OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
+ OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
+ OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
+ OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
+ OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
+ >;
+ };
+
+ wlan_pins: pinmux_wlan_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
+ >;
+ };
+
+ /* TI trees use GPIO mode; msecure mode does not work reliably? */
+ palmas_msecure_pins: palmas_msecure_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
+ >;
+ };
+
+ usbhost_pins: pinmux_usbhost_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
+ OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
+
+ OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
+ OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
+
+ OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
+ OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
+ >;
+ };
+
+ led_gpio_pins: pinmux_led_gpio_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
+ OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
+ OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
+ OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
+ OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
+ >;
+ };
+
+ uart5_pins: pinmux_uart5_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
+ OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
+ OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
+ OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
+ >;
+ };
+
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
+ OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
+ >;
+ };
+};
+
+&omap5_pmx_wkup {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &usbhost_wkup_pins
+ >;
+
+ palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
+ pinctrl-single,pins = <
+ /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+ OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
+ >;
+ };
+
+ usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
+ >;
+ };
+
+ wlcore_irq_pin: pinmux_wlcore_irq_pin {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
+ >;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&ldo9_reg>;
+ bus-width = <4>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ vmmc-supply = <&vmmcsdio_fixed>;
+ mmc-pwrseq = <&mmc3_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ cap-power-off-card;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ &omap5_pmx_core 0x16a>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlcore_irq_pin>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
+ ref-clock-frequency = <26000000>;
+ };
+};
+
+&mmc4 {
+ status = "disabled";
+};
+
+&mmc5 {
+ status = "disabled";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ clock-frequency = <400000>;
+
+ palmas: palmas@48 {
+ compatible = "ti,palmas";
+ /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
+ reg = <0x48>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,system-power-controller;
+ ti,mux-pad1 = <0xa1>;
+ ti,mux-pad2 = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
+
+ palmas_gpio: gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ extcon_usb3: palmas_usb {
+ compatible = "ti,palmas-usb-vid";
+ ti,enable-vbus-detection;
+ ti,enable-id-detection;
+ ti,wakeup;
+ id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ clk32kgaudio: palmas_clk32k@1 {
+ compatible = "ti,palmas-clk32kgaudio";
+ #clock-cells = <0>;
+ };
+
+ rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 IRQ_TYPE_NONE>;
+ ti,backup-battery-chargeable;
+ ti,backup-battery-charge-high-current;
+ };
+
+ gpadc: gpadc {
+ compatible = "ti,palmas-gpadc";
+ interrupts = <18 0
+ 16 0
+ 17 0>;
+ #io-channel-cells = <1>;
+ ti,channel0-current-microamp = <5>;
+ ti,channel3-current-microamp = <10>;
+ };
+
+ palmas_pmic {
+ compatible = "ti,palmas-pmic";
+ interrupt-parent = <&palmas>;
+ interrupts = <14 IRQ_TYPE_NONE>;
+ interrupt-names = "short-irq";
+
+ ti,ldo6-vibrator;
+
+ smps123-in-supply = <&vsys_cobra>;
+ smps45-in-supply = <&vsys_cobra>;
+ smps6-in-supply = <&vsys_cobra>;
+ smps7-in-supply = <&vsys_cobra>;
+ smps8-in-supply = <&vsys_cobra>;
+ smps9-in-supply = <&vsys_cobra>;
+ smps10_out2-in-supply = <&vsys_cobra>;
+ smps10_out1-in-supply = <&vsys_cobra>;
+ ldo1-in-supply = <&vsys_cobra>;
+ ldo2-in-supply = <&vsys_cobra>;
+ ldo3-in-supply = <&vdds_1v8_main>;
+ ldo4-in-supply = <&vdds_1v8_main>;
+ ldo5-in-supply = <&vsys_cobra>;
+ ldo6-in-supply = <&vdds_1v8_main>;
+ ldo7-in-supply = <&vsys_cobra>;
+ ldo8-in-supply = <&vsys_cobra>;
+ ldo9-in-supply = <&vmmcsd_fixed>;
+ ldoln-in-supply = <&vsys_cobra>;
+ ldousb-in-supply = <&vsys_cobra>;
+
+ regulators {
+ smps123_reg: smps123 {
+ /* VDD_OPP_MPU */
+ regulator-name = "smps123";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ /* VDD_OPP_MM */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ /* VDD_DDR3 - over VDD_SMPS6 */
+ regulator-name = "smps6";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps7_reg: smps7 {
+ /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps8_reg: smps8 {
+ /* VDD_OPP_CORE */
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps9_reg: smps9 {
+ /* VDDA_2v1_AUD over VDD_2v1 */
+ regulator-name = "smps9";
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ ti,smps-range = <0x80>;
+ };
+
+ smps10_out2_reg: smps10_out2 {
+ /* VBUS_5V_OTG */
+ regulator-name = "smps10_out2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps10_out1_reg: smps10_out1 {
+ /* VBUS_5V_OTG */
+ regulator-name = "smps10_out1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ ldo1_reg: ldo1 {
+ /* VDDAPHY_CAM: vdda_csiport */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo2_reg: ldo2 {
+ /* VCC_2V8_DISP: Does not go anywhere */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ /* Unused */
+ status = "disabled";
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDAPHY_MDM: vdda_lli */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ /* Only if Modem is used */
+ status = "disabled";
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDAPHY_DISP: vdda_dsiport/hdmi */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PHY: usb/sata/hdmi.. */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo6_reg: ldo6 {
+ /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7_reg: ldo7 {
+ /* VDD_VPP: vpp1 */
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ /* Only for efuse reprograming! */
+ status = "disabled";
+ };
+
+ ldo8_reg: ldo8 {
+ /* VDD_3v0: Does not go anywhere */
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ /* Unused */
+ status = "disabled";
+ };
+
+ ldo9_reg: ldo9 {
+ /* VCC_DV_SDIO: vdds_sdcard */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ regen3_reg: regen3 {
+ /* REGEN3 controls LDO9 supply to card */
+ regulator-name = "regen3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ palmas_power_button: palmas_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&palmas>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+ };
+
+ twl6040: twl@4b {
+ compatible = "ti,twl6040";
+ #clock-cells = <0>;
+ reg = <0x4b>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&twl6040_pins>;
+
+ /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
+
+ /* audpwron gpio defined in the board specific dts */
+
+ vio-supply = <&smps7_reg>;
+ v2v1-supply = <&smps9_reg>;
+ enable-active-high;
+
+ clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
+ clock-names = "clk32k", "mclk";
+ };
+};
+
+&mcpdm_module {
+ /* Module on the SoC needs external clock from the PMIC */
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcpdm_pins>;
+ status = "okay";
+};
+
+&mcpdm {
+ clocks = <&twl6040>;
+ clock-names = "pdmclk";
+};
+
+&mcbsp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp1_pins>;
+ status = "okay";
+};
+
+&mcbsp2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp2_pins>;
+ status = "okay";
+};
+
+&usbhshost {
+ port2-mode = "ehci-hsic";
+ port3-mode = "ehci-hsic";
+};
+
+&usbhsehci {
+ phys = <0 &hsusb2_phy &hsusb3_phy>;
+};
+
+&usb3 {
+ extcon = <&extcon_usb3>;
+ vbus-supply = <&smps10_out1_reg>;
+};
+
+&dwc3 {
+ extcon = <&extcon_usb3>;
+ dr_mode = "otg";
+};
+
+&mcspi1 {
+
+};
+
+&mcspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi2_pins>;
+};
+
+&mcspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi3_pins>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <&omap5_pmx_core 0x19c>;
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pins>;
+};
+
+&cpu0 {
+ cpu0-supply = <&smps123_reg>;
+};
+
+&dss {
+ status = "ok";
+};
+
+&hdmi {
+ status = "ok";
+
+ /* vdda-supply populated in board specific dts file */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_hdmi_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
--- /dev/null
+&l4_abe { /* 0x40100000 */
+ compatible = "ti,omap5-l4-abe", "simple-bus";
+ reg = <0x40100000 0x400>,
+ <0x40100400 0x400>;
+ reg-names = "la", "ap";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
+ <0x49000000 0x49000000 0x100000>;
+ segment@0 { /* 0x40100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges =
+ /* CPU to L4 ABE mapping */
+ <0x00000000 0x00000000 0x000400>, /* ap 0 */
+ <0x00000400 0x00000400 0x000400>, /* ap 1 */
+ <0x00022000 0x00022000 0x001000>, /* ap 2 */
+ <0x00023000 0x00023000 0x001000>, /* ap 3 */
+ <0x00024000 0x00024000 0x001000>, /* ap 4 */
+ <0x00025000 0x00025000 0x001000>, /* ap 5 */
+ <0x00026000 0x00026000 0x001000>, /* ap 6 */
+ <0x00027000 0x00027000 0x001000>, /* ap 7 */
+ <0x00028000 0x00028000 0x001000>, /* ap 8 */
+ <0x00029000 0x00029000 0x001000>, /* ap 9 */
+ <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
+ <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
+ <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
+ <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
+ <0x00030000 0x00030000 0x001000>, /* ap 14 */
+ <0x00031000 0x00031000 0x001000>, /* ap 15 */
+ <0x00032000 0x00032000 0x001000>, /* ap 16 */
+ <0x00033000 0x00033000 0x001000>, /* ap 17 */
+ <0x00038000 0x00038000 0x001000>, /* ap 18 */
+ <0x00039000 0x00039000 0x001000>, /* ap 19 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
+ <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
+ <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
+ <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
+ <0x00080000 0x00080000 0x010000>, /* ap 26 */
+ <0x00080000 0x00080000 0x001000>, /* ap 27 */
+ <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
+ <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
+ <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
+ <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
+ <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
+ <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
+
+ /* L3 to L4 ABE mapping */
+ <0x49000000 0x49000000 0x000400>, /* ap 0 */
+ <0x49000400 0x49000400 0x000400>, /* ap 1 */
+ <0x49022000 0x49022000 0x001000>, /* ap 2 */
+ <0x49023000 0x49023000 0x001000>, /* ap 3 */
+ <0x49024000 0x49024000 0x001000>, /* ap 4 */
+ <0x49025000 0x49025000 0x001000>, /* ap 5 */
+ <0x49026000 0x49026000 0x001000>, /* ap 6 */
+ <0x49027000 0x49027000 0x001000>, /* ap 7 */
+ <0x49028000 0x49028000 0x001000>, /* ap 8 */
+ <0x49029000 0x49029000 0x001000>, /* ap 9 */
+ <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
+ <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
+ <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
+ <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
+ <0x49030000 0x49030000 0x001000>, /* ap 14 */
+ <0x49031000 0x49031000 0x001000>, /* ap 15 */
+ <0x49032000 0x49032000 0x001000>, /* ap 16 */
+ <0x49033000 0x49033000 0x001000>, /* ap 17 */
+ <0x49038000 0x49038000 0x001000>, /* ap 18 */
+ <0x49039000 0x49039000 0x001000>, /* ap 19 */
+ <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
+ <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
+ <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
+ <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
+ <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
+ <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
+ <0x49080000 0x49080000 0x010000>, /* ap 26 */
+ <0x49080000 0x49080000 0x001000>, /* ap 27 */
+ <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
+ <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
+ <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
+ <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
+ <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
+ <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
+
+ target-module@22000 { /* 0x40122000, ap 2 02.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2208c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>,
+ <0x49022000 0x49022000 0x1000>;
+
+ mcbsp1: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49022000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 33>,
+ <&sdma 34>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@24000 { /* 0x40124000, ap 4 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2408c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>,
+ <0x49024000 0x49024000 0x1000>;
+
+ mcbsp2: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49024000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 17>,
+ <&sdma 18>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@26000 { /* 0x40126000, ap 6 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2608c 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>,
+ <0x49026000 0x49026000 0x1000>;
+
+ mcbsp3: mcbsp@0 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x0 0xff>, /* MPU private access */
+ <0x49026000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ ti,buffer-size = <128>;
+ dmas = <&sdma 19>,
+ <&sdma 20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ target-module@28000 { /* 0x40128000, ap 8 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>,
+ <0x49028000 0x49028000 0x1000>;
+ };
+
+ target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>,
+ <0x4902a000 0x4902a000 0x1000>;
+ };
+
+ target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2e000 0x4>,
+ <0x2e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2e000 0x1000>,
+ <0x4902e000 0x4902e000 0x1000>;
+
+ dmic: dmic@0 {
+ compatible = "ti,omap4-dmic";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x4902e000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 67>;
+ dma-names = "up_link";
+ status = "disabled";
+ };
+ };
+
+ target-module@30000 { /* 0x40130000, ap 14 0e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>,
+ <0x49030000 0x49030000 0x1000>;
+ };
+
+ mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>,
+ <0x49032000 0x49032000 0x1000>;
+
+ /* Must be only enabled for boards with pdmclk wired */
+ status = "disabled";
+
+ mcpdm: mcpdm@0 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 65>,
+ <&sdma 66>;
+ dma-names = "up_link", "dn_link";
+ };
+ };
+
+ target-module@38000 { /* 0x40138000, ap 18 12.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x38000 0x4>,
+ <0x38010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x1000>,
+ <0x49038000 0x49038000 0x1000>;
+
+ timer5: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x49038000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3a000 0x4>,
+ <0x3a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3a000 0x1000>,
+ <0x4903a000 0x4903a000 0x1000>;
+
+ timer6: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x4903a000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3c000 0x4>,
+ <0x3c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x1000>,
+ <0x4903c000 0x4903c000 0x1000>;
+
+ timer7: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x4903c000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ };
+ };
+
+ target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>,
+ <0x4903e000 0x4903e000 0x1000>;
+
+ timer8: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>,
+ <0x4903e000 0x80>;
+ clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@80000 { /* 0x40180000, ap 26 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>,
+ <0x49080000 0x49080000 0x10000>;
+ };
+
+ target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x10000>,
+ <0x490a0000 0x490a0000 0x10000>;
+ };
+
+ target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc0000 0x10000>,
+ <0x490c0000 0x490c0000 0x10000>;
+ };
+
+ target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xf1000 0x4>,
+ <0xf1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf1000 0x1000>,
+ <0x490f1000 0x490f1000 0x1000>;
+ };
+ };
+};
--- /dev/null
+&l4_cfg { /* 0x4a000000 */
+ compatible = "ti,omap5-l4-cfg", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
+ <0x00080000 0x4a080000 0x080000>, /* segment 1 */
+ <0x00100000 0x4a100000 0x080000>, /* segment 2 */
+ <0x00180000 0x4a180000 0x080000>, /* segment 3 */
+ <0x00200000 0x4a200000 0x080000>, /* segment 4 */
+ <0x00280000 0x4a280000 0x080000>, /* segment 5 */
+ <0x00300000 0x4a300000 0x080000>; /* segment 6 */
+
+ segment@0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00002000 0x00002000 0x001000>, /* ap 3 */
+ <0x00003000 0x00003000 0x001000>, /* ap 4 */
+ <0x00004000 0x00004000 0x001000>, /* ap 5 */
+ <0x00005000 0x00005000 0x001000>, /* ap 6 */
+ <0x00056000 0x00056000 0x001000>, /* ap 7 */
+ <0x00057000 0x00057000 0x001000>, /* ap 8 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
+ <0x00058000 0x00058000 0x001000>, /* ap 10 */
+ <0x00062000 0x00062000 0x001000>, /* ap 11 */
+ <0x00063000 0x00063000 0x001000>, /* ap 12 */
+ <0x00008000 0x00008000 0x002000>, /* ap 21 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
+ <0x00066000 0x00066000 0x001000>, /* ap 23 */
+ <0x00067000 0x00067000 0x001000>, /* ap 24 */
+ <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
+ <0x00060000 0x00060000 0x001000>, /* ap 70 */
+ <0x00064000 0x00064000 0x001000>, /* ap 71 */
+ <0x00065000 0x00065000 0x001000>, /* ap 72 */
+ <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
+ <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
+ <0x00070000 0x00070000 0x004000>, /* ap 79 */
+ <0x00074000 0x00074000 0x001000>, /* ap 80 */
+ <0x00075000 0x00075000 0x001000>, /* ap 81 */
+ <0x00076000 0x00076000 0x001000>, /* ap 82 */
+ <0x00020000 0x00020000 0x020000>, /* ap 109 */
+ <0x00040000 0x00040000 0x001000>, /* ap 110 */
+ <0x00059000 0x00059000 0x001000>; /* ap 111 */
+
+ target-module@2000 { /* 0x4a002000, ap 3 44.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ scm_core: scm@0 {
+ compatible = "ti,omap5-scm-core", "simple-bus";
+ reg = <0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x800>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ scm_padconf_core: scm@800 {
+ compatible = "ti,omap5-scm-padconf-core",
+ "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x800>;
+
+ omap5_pmx_core: pinmux@40 {
+ compatible = "ti,omap5-padconf",
+ "pinctrl-single";
+ reg = <0x40 0x01b6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
+ omap5_padconf_global: omap5_padconf_global@5a0 {
+ compatible = "syscon",
+ "simple-bus";
+ reg = <0x5a0 0xec>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5a0 0xec>;
+
+ pbias_regulator: pbias_regulator@60 {
+ compatible = "ti,pbias-omap5", "ti,pbias-omap";
+ reg = <0x60 0x4>;
+ syscon = <&omap5_padconf_global>;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name = "pbias_mmc_omap5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+ };
+ };
+
+ target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x4000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ cm_core_aon: cm_core_aon@0 {
+ compatible = "ti,omap5-cm-core-aon",
+ "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+
+ cm_core_aon_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_aon_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x8000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x2000>;
+
+ cm_core: cm_core@0 {
+ compatible = "ti,omap5-cm-core", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ cm_core_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@20000 { /* 0x4a020000, ap 109 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_otg_ss";
+ reg = <0x20000 0x4>,
+ <0x20010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x20000>;
+
+ usb3: omap_dwc3@0 {
+ compatible = "ti,dwc3";
+ reg = <0x0 0x10000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges = <0 0 0x20000>;
+ dwc3: dwc3@10000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ phys = <&usb2_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "peripheral";
+ };
+ };
+ };
+
+ target-module@56000 { /* 0x4a056000, ap 7 02.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x56000 0x4>,
+ <0x5602c 0x4>,
+ <0x56028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
+ clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x56000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <127>;
+ };
+ };
+
+ target-module@58000 { /* 0x4a058000, ap 10 06.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00058000 0x00001000>,
+ <0x00001000 0x00059000 0x00001000>,
+ <0x00002000 0x0005a000 0x00001000>,
+ <0x00003000 0x0005b000 0x00001000>;
+ };
+
+ target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5e000 0x2000>;
+ };
+
+ target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "usb_tll_hs";
+ reg = <0x62000 0x4>,
+ <0x62010 0x4>,
+ <0x62014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x62000 0x1000>;
+
+ usbhstll: usbhstll@0 {
+ compatible = "ti,usbhs-tll";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_host_hs";
+ reg = <0x64000 0x4>,
+ <0x64010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x64000 0x1000>;
+
+ usbhshost: usbhshost@0 {
+ compatible = "ti,usbhs-host";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ clocks = <&l3init_60m_fclk>,
+ <&xclk60mhsp1_ck>,
+ <&xclk60mhsp2_ck>;
+ clock-names = "refclk_60m_int",
+ "refclk_60m_ext_p1",
+ "refclk_60m_ext_p2";
+
+ usbhsohci: ohci@800 {
+ compatible = "ti,ohci-omap3";
+ reg = <0x800 0x400>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ remote-wakeup-connected;
+ };
+
+ usbhsehci: ehci@c00 {
+ compatible = "ti,ehci-omap";
+ reg = <0xc00 0x400>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x66000 0x4>,
+ <0x66010 0x4>,
+ <0x66014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
+ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp 1>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x1000>;
+
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
+ };
+
+ target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x70000 0x4000>;
+ };
+
+ target-module@75000 { /* 0x4a075000, ap 81 32.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x75000 0x1000>;
+ };
+ };
+
+ segment@80000 { /* 0x4a080000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
+ <0x0005a000 0x000da000 0x001000>, /* ap 14 */
+ <0x0005b000 0x000db000 0x001000>, /* ap 15 */
+ <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
+ <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
+ <0x0005e000 0x000de000 0x001000>, /* ap 18 */
+ <0x00060000 0x000e0000 0x001000>, /* ap 19 */
+ <0x00061000 0x000e1000 0x001000>, /* ap 20 */
+ <0x00074000 0x000f4000 0x001000>, /* ap 25 */
+ <0x00075000 0x000f5000 0x001000>, /* ap 26 */
+ <0x00076000 0x000f6000 0x001000>, /* ap 27 */
+ <0x00077000 0x000f7000 0x001000>, /* ap 28 */
+ <0x00036000 0x000b6000 0x001000>, /* ap 65 */
+ <0x00037000 0x000b7000 0x001000>, /* ap 66 */
+ <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
+ <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
+ <0x00000000 0x00080000 0x004000>, /* ap 83 */
+ <0x00004000 0x00084000 0x001000>, /* ap 84 */
+ <0x00005000 0x00085000 0x001000>, /* ap 85 */
+ <0x00006000 0x00086000 0x001000>, /* ap 86 */
+ <0x00007000 0x00087000 0x001000>, /* ap 87 */
+ <0x00008000 0x00088000 0x001000>, /* ap 88 */
+ <0x00010000 0x00090000 0x004000>, /* ap 89 */
+ <0x00014000 0x00094000 0x001000>, /* ap 90 */
+ <0x00015000 0x00095000 0x001000>, /* ap 91 */
+ <0x00016000 0x00096000 0x001000>, /* ap 92 */
+ <0x00017000 0x00097000 0x001000>, /* ap 93 */
+ <0x00018000 0x00098000 0x001000>, /* ap 94 */
+ <0x00020000 0x000a0000 0x004000>, /* ap 95 */
+ <0x00024000 0x000a4000 0x001000>, /* ap 96 */
+ <0x00025000 0x000a5000 0x001000>, /* ap 97 */
+ <0x00026000 0x000a6000 0x001000>, /* ap 98 */
+ <0x00027000 0x000a7000 0x001000>, /* ap 99 */
+ <0x00028000 0x000a8000 0x001000>; /* ap 100 */
+
+ target-module@0 { /* 0x4a080000, ap 83 28.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x0 0x4>,
+ <0x10 0x4>,
+ <0x14 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x00004000>,
+ <0x00004000 0x00004000 0x00001000>,
+ <0x00005000 0x00005000 0x00001000>,
+ <0x00006000 0x00006000 0x00001000>,
+ <0x00007000 0x00007000 0x00001000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x20>;
+ };
+
+ usb2_phy: usb2phy@4000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4000 0x7c>;
+ syscon-phy-power = <&scm_conf 0x300>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
+ clock-names = "wkupclk", "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb3_phy: usb3phy@4400 {
+ compatible = "ti,omap-usb3";
+ reg = <0x4400 0x80>,
+ <0x4800 0x64>,
+ <0x4c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ syscon-phy-power = <&scm_conf 0x370>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&sys_clkin>,
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
+ clock-names = "wkupclk",
+ "sysclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ target-module@10000 { /* 0x4a090000, ap 89 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x10000 0x4>,
+ <0x10010 0x4>,
+ <0x10014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x00004000>,
+ <0x00004000 0x00014000 0x00001000>,
+ <0x00005000 0x00015000 0x00001000>,
+ <0x00006000 0x00016000 0x00001000>,
+ <0x00007000 0x00017000 0x00001000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x20>;
+ };
+
+ sata_phy: phy@6000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x6000 0x80>, /* phy_rx */
+ <0x6400 0x64>, /* phy_tx */
+ <0x6800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ syscon-phy-power = <&scm_conf 0x374>;
+ clocks = <&sys_clkin>,
+ <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
+ clock-names = "sysclk", "refclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00020000 0x00004000>,
+ <0x00004000 0x00024000 0x00001000>,
+ <0x00005000 0x00025000 0x00001000>,
+ <0x00006000 0x00026000 0x00001000>,
+ <0x00007000 0x00027000 0x00001000>;
+ };
+
+ target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+ };
+
+ target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4d000 0x1000>;
+ };
+
+ target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+ };
+
+ target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+ };
+
+ target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+ };
+
+ target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+ };
+
+ target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x74000 0x4>,
+ <0x74010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
+ clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x74000 0x1000>;
+
+ mailbox: mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ mbox_ipu: mbox_ipu {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ mbox_dsp: mbox_dsp {
+ ti,mbox-tx = <3 0 0>;
+ ti,mbox-rx = <2 0 0>;
+ };
+ };
+ };
+
+ target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x76000 0x4>,
+ <0x76010 0x4>,
+ <0x76014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
+ clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x76000 0x1000>;
+
+ hwspinlock: spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+ };
+
+ segment@100000 { /* 0x4a100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
+ <0x00003000 0x00103000 0x001000>, /* ap 60 */
+ <0x00008000 0x00108000 0x001000>, /* ap 61 */
+ <0x00009000 0x00109000 0x001000>, /* ap 62 */
+ <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
+ <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
+ <0x00040000 0x00140000 0x010000>, /* ap 101 */
+ <0x00050000 0x00150000 0x001000>; /* ap 102 */
+
+ target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@8000 { /* 0x4a108000, ap 61 26.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+ };
+
+ target-module@40000 { /* 0x4a140000, ap 101 16.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x10000>;
+ };
+ };
+
+ segment@180000 { /* 0x4a180000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@200000 { /* 0x4a200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
+ <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
+ <0x00006000 0x00206000 0x001000>, /* ap 33 */
+ <0x00007000 0x00207000 0x001000>, /* ap 34 */
+ <0x00004000 0x00204000 0x001000>, /* ap 35 */
+ <0x00005000 0x00205000 0x001000>, /* ap 36 */
+ <0x00012000 0x00212000 0x001000>, /* ap 37 */
+ <0x00013000 0x00213000 0x001000>, /* ap 38 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
+ <0x00010000 0x00210000 0x001000>, /* ap 41 */
+ <0x00011000 0x00211000 0x001000>, /* ap 42 */
+ <0x00016000 0x00216000 0x001000>, /* ap 43 */
+ <0x00017000 0x00217000 0x001000>, /* ap 44 */
+ <0x00014000 0x00214000 0x001000>, /* ap 45 */
+ <0x00015000 0x00215000 0x001000>, /* ap 46 */
+ <0x00018000 0x00218000 0x001000>, /* ap 47 */
+ <0x00019000 0x00219000 0x001000>, /* ap 48 */
+ <0x00020000 0x00220000 0x001000>, /* ap 49 */
+ <0x00021000 0x00221000 0x001000>, /* ap 50 */
+ <0x00026000 0x00226000 0x001000>, /* ap 51 */
+ <0x00027000 0x00227000 0x001000>, /* ap 52 */
+ <0x00028000 0x00228000 0x001000>, /* ap 53 */
+ <0x00029000 0x00229000 0x001000>, /* ap 54 */
+ <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
+ <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
+ <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
+ <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
+ <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
+ <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
+ <0x00024000 0x00224000 0x001000>, /* ap 75 */
+ <0x00025000 0x00225000 0x001000>, /* ap 76 */
+ <0x00002000 0x00202000 0x001000>, /* ap 103 */
+ <0x00003000 0x00203000 0x001000>, /* ap 104 */
+ <0x00008000 0x00208000 0x001000>, /* ap 105 */
+ <0x00009000 0x00209000 0x001000>, /* ap 106 */
+ <0x00022000 0x00222000 0x001000>, /* ap 107 */
+ <0x00023000 0x00223000 0x001000>; /* ap 108 */
+
+ target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@4000 { /* 0x4a204000, ap 35 46.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x1000>;
+ };
+
+ target-module@8000 { /* 0x4a208000, ap 105 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+ };
+
+ target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+ };
+
+ target-module@10000 { /* 0x4a210000, ap 41 56.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x1000>;
+ };
+
+ target-module@12000 { /* 0x4a212000, ap 37 52.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x12000 0x1000>;
+ };
+
+ target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module@16000 { /* 0x4a216000, ap 43 42.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x16000 0x1000>;
+ };
+
+ target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x1000>;
+ };
+
+ target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1a000 0x1000>;
+ };
+
+ target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1c000 0x1000>;
+ };
+
+ target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e000 0x1000>;
+ };
+
+ target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+ };
+
+ target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+ };
+
+ target-module@24000 { /* 0x4a224000, ap 75 48.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+ };
+
+ target-module@26000 { /* 0x4a226000, ap 51 24.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+ };
+
+ target-module@28000 { /* 0x4a228000, ap 53 38.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>;
+ };
+
+ target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+ };
+ };
+
+ segment@280000 { /* 0x4a280000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@300000 { /* 0x4a300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&l4_per { /* 0x48000000 */
+ compatible = "ti,omap5-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
+ <0x00200000 0x48200000 0x200000>; /* segment 1 */
+
+ segment@0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x000400>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00020000 0x00020000 0x001000>, /* ap 3 */
+ <0x00021000 0x00021000 0x001000>, /* ap 4 */
+ <0x00032000 0x00032000 0x001000>, /* ap 5 */
+ <0x00033000 0x00033000 0x001000>, /* ap 6 */
+ <0x00034000 0x00034000 0x001000>, /* ap 7 */
+ <0x00035000 0x00035000 0x001000>, /* ap 8 */
+ <0x00036000 0x00036000 0x001000>, /* ap 9 */
+ <0x00037000 0x00037000 0x001000>, /* ap 10 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
+ <0x00055000 0x00055000 0x001000>, /* ap 13 */
+ <0x00056000 0x00056000 0x001000>, /* ap 14 */
+ <0x00057000 0x00057000 0x001000>, /* ap 15 */
+ <0x00058000 0x00058000 0x001000>, /* ap 16 */
+ <0x00059000 0x00059000 0x001000>, /* ap 17 */
+ <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
+ <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
+ <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
+ <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
+ <0x00060000 0x00060000 0x001000>, /* ap 23 */
+ <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
+ <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
+ <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
+ <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
+ <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
+ <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
+ <0x00070000 0x00070000 0x001000>, /* ap 30 */
+ <0x00071000 0x00071000 0x001000>, /* ap 31 */
+ <0x00072000 0x00072000 0x001000>, /* ap 32 */
+ <0x00073000 0x00073000 0x001000>, /* ap 33 */
+ <0x00061000 0x00061000 0x001000>, /* ap 34 */
+ <0x00053000 0x00053000 0x001000>, /* ap 35 */
+ <0x00054000 0x00054000 0x001000>, /* ap 36 */
+ <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
+ <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
+ <0x00078000 0x00078000 0x001000>, /* ap 39 */
+ <0x00079000 0x00079000 0x001000>, /* ap 40 */
+ <0x00086000 0x00086000 0x001000>, /* ap 41 */
+ <0x00087000 0x00087000 0x001000>, /* ap 42 */
+ <0x00088000 0x00088000 0x001000>, /* ap 43 */
+ <0x00089000 0x00089000 0x001000>, /* ap 44 */
+ <0x00051000 0x00051000 0x001000>, /* ap 45 */
+ <0x00052000 0x00052000 0x001000>, /* ap 46 */
+ <0x00098000 0x00098000 0x001000>, /* ap 47 */
+ <0x00099000 0x00099000 0x001000>, /* ap 48 */
+ <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
+ <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
+ <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
+ <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
+ <0x00068000 0x00068000 0x001000>, /* ap 53 */
+ <0x00069000 0x00069000 0x001000>, /* ap 54 */
+ <0x00090000 0x00090000 0x002000>, /* ap 55 */
+ <0x00092000 0x00092000 0x001000>, /* ap 56 */
+ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
+ <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
+ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
+ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
+ <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
+ <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
+ <0x00066000 0x00066000 0x001000>, /* ap 63 */
+ <0x00067000 0x00067000 0x001000>, /* ap 64 */
+ <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
+ <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
+ <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
+ <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
+ <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
+ <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
+ <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
+ <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
+ <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
+ <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
+ <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
+ <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
+ <0x00001400 0x00001400 0x000400>, /* ap 77 */
+ <0x00001800 0x00001800 0x000400>, /* ap 78 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
+ <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
+ <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
+ <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
+ <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
+ <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
+
+ target-module@20000 { /* 0x48020000, ap 3 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x20050 0x4>,
+ <0x20054 0x4>,
+ <0x20058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ uart3: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@32000 { /* 0x48032000, ap 5 3e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@34000 { /* 0x48034000, ap 7 46.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x34000 0x4>,
+ <0x34010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x1000>;
+
+ timer3: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@36000 { /* 0x48036000, ap 9 4e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x36000 0x4>,
+ <0x36010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+
+ timer4: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ timer9: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@51000 { /* 0x48051000, ap 45 2e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x51000 0x4>,
+ <0x51010 0x4>,
+ <0x51114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x51000 0x1000>;
+
+ gpio7: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@53000 { /* 0x48053000, ap 35 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53000 0x4>,
+ <0x53010 0x4>,
+ <0x53114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53000 0x1000>;
+
+ gpio8: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@55000 { /* 0x48055000, ap 13 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55000 0x4>,
+ <0x55010 0x4>,
+ <0x55114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@57000 { /* 0x48057000, ap 15 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x57000 0x4>,
+ <0x57010 0x4>,
+ <0x57114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x57000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@59000 { /* 0x48059000, ap 17 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x59000 0x4>,
+ <0x59010 0x4>,
+ <0x59114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+
+ gpio4: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5b000 0x4>,
+ <0x5b010 0x4>,
+ <0x5b114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ gpio5: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5d000 0x4>,
+ <0x5d010 0x4>,
+ <0x5d114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
+ <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+
+ gpio6: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@60000 { /* 0x48060000, ap 23 24.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x60000 0x8>,
+ <0x60010 0x8>,
+ <0x60090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+
+ i2c3: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@66000 { /* 0x48066000, ap 63 4c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x66050 0x4>,
+ <0x66054 0x4>,
+ <0x66058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x1000>;
+
+ uart5: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@68000 { /* 0x48068000, ap 53 54.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x68050 0x4>,
+ <0x68054 0x4>,
+ <0x68058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x68000 0x1000>;
+
+ uart6: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6a050 0x4>,
+ <0x6a054 0x4>,
+ <0x6a058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6a000 0x1000>;
+
+ uart1: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6c050 0x4>,
+ <0x6c054 0x4>,
+ <0x6c058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6c000 0x1000>;
+
+ uart2: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x6e050 0x4>,
+ <0x6e054 0x4>,
+ <0x6e058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6e000 0x1000>;
+
+ uart4: serial@0 {
+ compatible = "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ };
+ };
+
+ target-module@70000 { /* 0x48070000, ap 30 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x70000 0x8>,
+ <0x70010 0x8>,
+ <0x70090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x70000 0x1000>;
+
+ i2c1: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@72000 { /* 0x48072000, ap 32 1c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x72000 0x8>,
+ <0x72010 0x8>,
+ <0x72090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x72000 0x1000>;
+
+ i2c2: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@78000 { /* 0x48078000, ap 39 12.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x78000 0x1000>;
+ };
+
+ target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x7a000 0x8>,
+ <0x7a010 0x8>,
+ <0x7a090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7a000 0x1000>;
+
+ i2c4: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x7c000 0x8>,
+ <0x7c010 0x8>,
+ <0x7c090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7c000 0x1000>;
+
+ i2c5: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@86000 { /* 0x48086000, ap 41 5e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x86000 0x4>,
+ <0x86010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x86000 0x1000>;
+
+ timer10: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@88000 { /* 0x48088000, ap 43 66.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x88000 0x4>,
+ <0x88010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x88000 0x1000>;
+
+ timer11: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ };
+ };
+
+ rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x91fe0 0x4>,
+ <0x91fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x90000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@98000 { /* 0x48098000, ap 47 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x98000 0x4>,
+ <0x98010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x98000 0x1000>;
+
+ mcspi1: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+ };
+
+ target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9a000 0x4>,
+ <0x9a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9a000 0x1000>;
+
+ mcspi2: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+ };
+
+ target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x9c000 0x4>,
+ <0x9c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+
+ mmc1: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+ };
+
+ target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+ };
+
+ target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x000a4000 0x00001000>,
+ <0x00001000 0x000a5000 0x00001000>;
+ };
+
+ target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x4000>;
+ };
+
+ target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xad000 0x4>,
+ <0xad010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xad000 0x1000>;
+
+ mmc3: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb2000 0x1000>;
+ };
+
+ target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb4000 0x4>,
+ <0xb4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb4000 0x1000>;
+
+ mmc2: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xb8000 0x4>,
+ <0xb8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb8000 0x1000>;
+
+ mcspi3: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xba000 0x4>,
+ <0xba010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xba000 0x1000>;
+
+ mcspi4: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+
+ target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd1000 0x4>,
+ <0xd1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd1000 0x1000>;
+
+ mmc4: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd5000 0x4>,
+ <0xd5010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd5000 0x1000>;
+
+ mmc5: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ ti,needs-special-reset;
+ dmas = <&sdma 59>, <&sdma 60>;
+ dma-names = "tx", "rx";
+ };
+ };
+ };
+
+ segment@200000 { /* 0x48200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&l4_wkup { /* 0x4ae00000 */
+ compatible = "ti,omap5-l4-wkup", "simple-bus";
+ reg = <0x4ae00000 0x800>,
+ <0x4ae00800 0x800>,
+ <0x4ae01000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
+ <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
+ <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
+
+ segment@0 { /* 0x4ae00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00006000 0x00006000 0x002000>, /* ap 3 */
+ <0x00008000 0x00008000 0x001000>, /* ap 4 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
+ <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
+ <0x00004000 0x00004000 0x001000>, /* ap 17 */
+ <0x00005000 0x00005000 0x001000>, /* ap 18 */
+ <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
+ <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
+
+ target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "counter_32k";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x0 0x40>;
+ };
+ };
+
+ target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x6000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x2000>;
+
+ prm: prm@0 {
+ compatible = "ti,omap5-prm", "simple-bus";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xa000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+
+ scrm: scrm@0 {
+ compatible = "ti,omap5-scrm";
+ reg = <0x0 0x1000>;
+
+ scrm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scrm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xc000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ omap5_pmx_wkup: pinmux@840 {
+ compatible = "ti,omap5-padconf",
+ "pinctrl-single";
+ reg = <0x840 0x003c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
+ omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 {
+ compatible = "ti,omap5-scm-wkup-pad-conf",
+ "simple-bus";
+ reg = <0xda0 0x60>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x60>;
+
+ scm_wkup_pad_conf: scm_conf@0 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x0 0x60>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x60>;
+
+ scm_wkup_pad_conf_clocks: clocks@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+ };
+ };
+
+ segment@10000 { /* 0x4ae10000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
+ <0x00001000 0x00011000 0x001000>, /* ap 6 */
+ <0x00004000 0x00014000 0x001000>, /* ap 7 */
+ <0x00005000 0x00015000 0x001000>, /* ap 8 */
+ <0x00008000 0x00018000 0x001000>, /* ap 9 */
+ <0x00009000 0x00019000 0x001000>, /* ap 10 */
+ <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
+ <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
+
+ target-module@0 { /* 0x4ae10000, ap 5 10.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x0 0x4>,
+ <0x10 0x4>,
+ <0x114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
+ <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ gpio1: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ ti,gpio-always-on;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ wdt2: wdt@0 {
+ compatible = "ti,omap5-wdt", "ti,omap3-wdt";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer1";
+ reg = <0x8000 0x4>,
+ <0x8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-alwon;
+ };
+ };
+
+ target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xc000 0x4>,
+ <0xc010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
+ clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+
+ keypad: keypad@0 {
+ compatible = "ti,omap4-keypad";
+ reg = <0x0 0x400>;
+ };
+ };
+ };
+
+ segment@20000 { /* 0x4ae20000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
+ <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
+ <0x00000000 0x00020000 0x001000>, /* ap 21 */
+ <0x00001000 0x00021000 0x001000>, /* ap 22 */
+ <0x00002000 0x00022000 0x001000>, /* ap 23 */
+ <0x00003000 0x00023000 0x001000>, /* ap 24 */
+ <0x00007000 0x00027000 0x000400>, /* ap 25 */
+ <0x00008000 0x00028000 0x000800>, /* ap 26 */
+ <0x00009000 0x00029000 0x000100>, /* ap 27 */
+ <0x00008800 0x00028800 0x000200>, /* ap 28 */
+ <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
+
+ target-module@0 { /* 0x4ae20000, ap 21 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+ };
+
+ target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00006000 0x00001000>,
+ <0x00001000 0x00007000 0x00000400>,
+ <0x00002000 0x00008000 0x00000800>,
+ <0x00002800 0x00008800 0x00000200>,
+ <0x00002a00 0x00008a00 0x00000100>,
+ <0x00003000 0x00009000 0x00000100>;
+ };
+ };
+};
* Based on "dra7.dtsi"
*/
+#ifdef CONFIG_DRA7XX
/{
chosen {
tick-timer = &timer2;
&i2c1 {
u-boot,dm-spl;
};
+
+#else /* OMAP54XX */
+&l4_cfg {
+ segment@0 {
+ /* SCM Core */
+ target-module@2000 {
+ compatible = "simple-bus";
+ };
+
+ /* USB HS */
+ target-module@64000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+&l4_per {
+ segment@0 {
+ /* UART3 */
+ target-module@20000 {
+ compatible = "simple-bus";
+ };
+
+ /* I2C1 */
+ target-module@70000 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC1 */
+ target-module@9c000 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC2 */
+ target-module@b4000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/dts-v1/;
+
+#include "omap5-board-common.dtsi"
+
+/ {
+ model = "TI OMAP5 uEVM board";
+ compatible = "ti,omap5-uevm", "ti,omap5";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
+ };
+
+ aliases {
+ ethernet = ðernet;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1 {
+ label = "omap5:blue:usr1";
+ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ evm_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&evm_keys_pins>;
+
+ #address-cells = <7>;
+ #size-cells = <0>;
+
+ btn1 {
+ label = "BTN1";
+ linux,code = <169>;
+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
+ wakeup-source;
+ autorepeat;
+ debounce-interval = <50>;
+ };
+ };
+
+ evm_leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "omap5:red:led";
+ gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "omap5:green:led";
+ gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "omap5:blue:led";
+ gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "omap5:green:led1";
+ gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led5 {
+ label = "omap5:green:led2";
+ gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+
+ led6 {
+ label = "omap5:green:led3";
+ gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led7 {
+ label = "omap5:green:led4";
+ gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+
+ led8 {
+ label = "omap5:green:led5";
+ gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+};
+
+&hdmi {
+ vdda-supply = <&ldo4_reg>;
+};
+
+&i2c1 {
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+
+ clock-frequency = <400000>;
+
+ gpio9: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+
+ cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */
+};
+
+&omap5_pmx_core {
+ evm_keys_pins: pinmux_evm_keys_gpio_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
+ >;
+ };
+
+ i2c5_pins: pinmux_i2c5_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */
+ OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */
+ >;
+ };
+};
+
+&tpd12s015 {
+ gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
+ <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
+ <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
+};
+
+&twl6040 {
+ ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
+};
+
+&twl6040_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
+ >;
+};
+
+&usbhsehci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@2 {
+ compatible = "usb424,3503";
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ethernet: usbether@3 {
+ compatible = "usb424,9730";
+ reg = <3>;
+ };
+};
+
+&wlcore {
+ compatible = "ti,wl1837";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on "omap4.dtsi"
+ */
+
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap5.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ compatible = "ti,omap5";
+ interrupt-parent = <&wakeupgen>;
+ chosen { };
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ i2c4 = &i2c5;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1500000 1250000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1500000 1250000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ #include "omap5-gpu-thermal.dtsi"
+ #include "omap5-core-thermal.dtsi"
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ /* PPI secure/nonsecure IRQ */
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0 0x48211000 0 0x1000>,
+ <0 0x48212000 0 0x2000>,
+ <0 0x48214000 0 0x2000>,
+ <0 0x48216000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0 0x48281000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap4-mpu";
+ ti,hwmods = "mpu";
+ sram = <&ocmcram>;
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP3 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap5-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xc0000000>;
+ dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
+ ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+ reg = <0 0x44000000 0 0x2000>,
+ <0 0x44800000 0 0x3000>,
+ <0 0x45000000 0 0x4000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ l4_wkup: interconnect@4ae00000 {
+ };
+
+ l4_cfg: interconnect@4a000000 {
+ };
+
+ l4_per: interconnect@48000000 {
+ };
+
+ l4_abe: interconnect@40100000 {
+ };
+
+ ocmcram: sram@40300000 {
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x20000>; /* 128k */
+ };
+
+ gpmc: gpmc@50000000 {
+ compatible = "ti,omap4430-gpmc";
+ reg = <0x50000000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 4>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <4>;
+ ti,hwmods = "gpmc";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
+ };
+
+ dmm@4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
+ emif1: emif@4c000000 {
+ compatible = "ti,emif-4d5";
+ ti,hwmods = "emif1";
+ ti,no-idle-on-init;
+ phy-type = <2>; /* DDR PHY type: Intelli PHY */
+ reg = <0x4c000000 0x400>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ emif2: emif@4d000000 {
+ compatible = "ti,emif-4d5";
+ ti,hwmods = "emif2";
+ ti,no-idle-on-init;
+ phy-type = <2>; /* DDR PHY type: Intelli PHY */
+ reg = <0x4d000000 0x400>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ bandgap: bandgap@4a0021e0 {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ compatible = "ti,omap5430-bandgap";
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ /* OCP2SCP3 */
+ sata: sata@4a141100 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
+ ti,hwmods = "sata";
+ ports-implemented = <0x1>;
+ };
+
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x2000000>;
+
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
+ };
+
+ target-module@58000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000000 4>,
+ <0x58000014 4>;
+ reg-names = "rev", "syss";
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x58000000 0x1000000>;
+
+ dss: dss@0 {
+ compatible = "ti,omap5-dss";
+ reg = <0 0x80>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000000>;
+
+ target-module@1000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x1000 0x4>,
+ <0x1010 0x4>,
+ <0x1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x1000>;
+
+ dispc@0 {
+ compatible = "ti,omap5-dispc";
+ reg = <0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@2000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>,
+ <0x2014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x1000>;
+
+ rfbi: encoder@0 {
+ compatible = "ti,omap5-rfbi";
+ reg = <0 0x100>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
+ clock-names = "fck", "ick";
+ };
+ };
+
+ target-module@5000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5000 0x4>,
+ <0x5010 0x4>,
+ <0x5014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5000 0x1000>;
+
+ dsi1: encoder@0 {
+ compatible = "ti,omap5-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x40>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@9000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x9000 0x4>,
+ <0x9010 0x4>,
+ <0x9014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x9000 0x1000>;
+
+ dsi2: encoder@0 {
+ compatible = "ti,omap5-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x40>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@40000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck", "dss_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40000 0x40000>;
+
+ hdmi: encoder@0 {
+ compatible = "ti,omap5-hdmi";
+ reg = <0 0x200>,
+ <0x200 0x80>,
+ <0x300 0x80>,
+ <0x20000 0x19000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ dmas = <&sdma 76>;
+ dma-names = "audio_tx";
+ };
+ };
+ };
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
+ <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address", "ldo-address";
+ ti,tranxdone-status-mask = <0x80>;
+ /* LDOVBBMPU_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMPU_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1060000 0 0x0 0 0x02000000 0x01F00000
+ 1250000 0 0x4 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_mm: regulator-abb-mm {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mm";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
+ <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address", "ldo-address";
+ ti,tranxdone-status-mask = <0x80000000>;
+ /* LDOVBBMM_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMM_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0x0 0 0x02000000 0x01F00000
+ 1120000 0 0x4 0 0x02000000 0x01F00000
+ >;
+ };
+ };
+};
+
+&cpu_thermal {
+ polling-delay = <500>; /* milliseconds */
+ coefficients = <65 (-1791)>;
+};
+
+#include "omap5-l4.dtsi"
+#include "omap54xx-clocks.dtsi"
+
+&gpu_thermal {
+ coefficients = <117 (-2992)>;
+};
+
+&core_thermal {
+ coefficients = <0 2000>;
+};
+
+#include "omap5-l4-abe.dtsi"
+#include "omap54xx-clocks.dtsi"
+
+&prm {
+ prm_dsp: prm@400 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_iva: prm@1200 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1200 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@1c00 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1c00 0x100>;
+ #reset-cells = <1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+&cm_core_aon_clocks {
+ pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ pad_clks_ck: pad_clks_ck@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0108>;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ slimbus_clk: slimbus_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x0108>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ };
+
+ virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+ };
+
+ dpll_abe_ck: dpll_abe_ck@1e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+ };
+
+ dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ };
+
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ };
+
+ abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ abe_clk: abe_clk@108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x0108>;
+ ti,index-power-of-two;
+ };
+
+ abe_iclk: abe_iclk@528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x0528>;
+ ti,dividers = <2>, <1>;
+ };
+
+ abe_lp_clk_div: abe_lp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x01f4>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_byp_mux: dpll_core_byp_mux@12c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x012c>;
+ };
+
+ dpll_core_ck: dpll_core_ck@120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
+ reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+ };
+
+ dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+ };
+
+ dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ c2c_fclk: c2c_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h21x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ c2c_iclk: c2c_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&c2c_fclk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0138>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x013c>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0140>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0144>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m2_ck: dpll_core_m2_ck@130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ reg = <0x0130>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0134>;
+ ti,index-starts-at-one;
+ };
+
+ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x01ac>;
+ };
+
+ dpll_iva_ck: dpll_iva_ck@1a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
+ reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <1165000000>;
+ };
+
+ dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+ };
+
+ dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x01b8>;
+ ti,index-starts-at-one;
+ assigned-clocks = <&dpll_iva_h11x2_ck>;
+ assigned-clock-rates = <465920000>;
+ };
+
+ dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x01bc>;
+ ti,index-starts-at-one;
+ assigned-clocks = <&dpll_iva_h12x2_ck>;
+ assigned-clock-rates = <388300000>;
+ };
+
+ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_mpu_ck: dpll_mpu_ck@160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap5-mpu-dpll-clock";
+ clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+ };
+
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ reg = <0x0170>;
+ ti,index-starts-at-one;
+ };
+
+ per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ l3_iclk_div: l3_iclk_div@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,max-div = <2>;
+ ti,bit-shift = <4>;
+ reg = <0x100>;
+ clocks = <&dpll_core_h12x2_ck>;
+ ti,index-power-of-two;
+ };
+
+ gpu_l3_iclk: gpu_l3_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l4_root_clk_div: l4_root_clk_div@100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,max-div = <2>;
+ ti,bit-shift = <8>;
+ reg = <0x100>;
+ clocks = <&l3_iclk_div>;
+ ti,index-power-of-two;
+ };
+
+ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x0560>;
+ };
+
+ aess_fclk: aess_fclk@528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ ti,max-div = <2>;
+ reg = <0x0528>;
+ };
+
+ mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x0540>;
+ };
+
+ mcasp_gfclk: mcasp_gfclk@540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x0540>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+&prm_clocks {
+ sys_clkin: sys_clkin@110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x0110>;
+ ti,index-starts-at-one;
+ };
+
+ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x0108>;
+ };
+
+ abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x010c>;
+ };
+
+ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dss_syc_gfclk_div: dss_syc_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+ reg = <0x0108>;
+ };
+
+ l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+};
+
+&cm_core_clocks {
+
+ dpll_per_byp_mux: dpll_per_byp_mux@14c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x014c>;
+ };
+
+ dpll_per_ck: dpll_per_ck@140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
+ reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+ };
+
+ dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ };
+
+ dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x0164>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m2_ck: dpll_per_m2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_unipro1_ck: dpll_unipro1_ck@200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+ };
+
+ dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro1_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro1_ck>;
+ ti,max-div = <127>;
+ reg = <0x0210>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
+ };
+
+ dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro2_ck>;
+ ti,max-div = <127>;
+ reg = <0x01d0>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x018c>;
+ };
+
+ dpll_usb_ck: dpll_usb_ck@180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
+ reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+ };
+
+ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ reg = <0x0190>;
+ ti,index-starts-at-one;
+ };
+
+ func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l3init_60m_fclk: l3init_60m_fclk@104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x0104>;
+ ti,dividers = <1>, <8>;
+ };
+
+ iss_ctrlclk: iss_ctrlclk@1320 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_96m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x1320>;
+ };
+
+ lli_txphy_clk: lli_txphy_clk@f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x0f20>;
+ };
+
+ lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_m2_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x0f20>;
+ };
+
+ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0640>;
+ };
+
+ fdif_fclk: fdif_fclk@1328 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <2>;
+ reg = <0x1328>;
+ };
+
+ gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1520>;
+ };
+
+ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x1520>;
+ };
+
+ hsi_fclk: hsi_fclk@1638 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <2>;
+ reg = <0x1638>;
+ };
+};
+
+&cm_core_clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+};
+
+&scrm_clocks {
+ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0310>;
+ };
+
+ auxclk0_src_ck: auxclk0_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+ };
+
+ auxclk0_ck: auxclk0_ck@310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0310>;
+ };
+
+ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0314>;
+ };
+
+ auxclk1_src_ck: auxclk1_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+ };
+
+ auxclk1_ck: auxclk1_ck@314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0314>;
+ };
+
+ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0318>;
+ };
+
+ auxclk2_src_ck: auxclk2_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+ };
+
+ auxclk2_ck: auxclk2_ck@318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0318>;
+ };
+
+ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x031c>;
+ };
+
+ auxclk3_src_ck: auxclk3_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+ };
+
+ auxclk3_ck: auxclk3_ck@31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x031c>;
+ };
+
+ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_core_m3x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0320>;
+ };
+
+ auxclk4_src_ck: auxclk4_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+ };
+
+ auxclk4_ck: auxclk4_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <16>;
+ reg = <0x0320>;
+ };
+
+ auxclkreq0_ck: auxclkreq0_ck@210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0210>;
+ };
+
+ auxclkreq1_ck: auxclkreq1_ck@214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0214>;
+ };
+
+ auxclkreq2_ck: auxclkreq2_ck@218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0218>;
+ };
+
+ auxclkreq3_ck: auxclkreq3_ck@21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x021c>;
+ };
+};
+
+&cm_core_aon {
+ mpu_cm: mpu_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dsp_cm: dsp_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ dsp_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x64>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm_core {
+ l3main1_cm: l3main1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3main1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3main2_cm: l3main2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3main2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ipu_cm: ipu_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ipu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dma_cm: dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emif_cm: emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4cfg_cm: l4cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3instr_cm: l3instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4per_cm: l4per_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x200>;
+
+ l4per_clkctrl: clock@20 {
+ compatible = "ti,clkctrl-l4per", "ti,clkctrl";
+ reg = <0x20 0x15c>;
+ #clock-cells = <2>;
+ };
+
+ l4sec_clkctrl: clock@1a0 {
+ compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
+ reg = <0x1a0 0x3c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dss_cm: dss_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x100>;
+
+ dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ gpu_cm: gpu_cm@1500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1500 0x100>;
+
+ gpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3init_cm: l3init_cm@1600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1600 0x100>;
+
+ l3init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&prm {
+ wkupaon_cm: wkupaon_cm@1900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1900 0x100>;
+
+ wkupaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&scm_wkup_pad_conf_clocks {
+ fref_xtal_ck: fref_xtal_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin>;
+ ti,bit-shift = <28>;
+ reg = <0x14>;
+ };
+};
/{
soc {
u-boot,dm-pre-reloc;
+
+ gmac: ethernet@e0220000 {
+ compatible = "actions,s700-ethernet";
+ reg = <0 0xe0220000 0 0x2000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ local-mac-address = [ 00 18 fe 66 66 66 ];
+ clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>;
+ clock-names = "ethernet", "rmii_ref";
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
};
};
atmel,nb-banks = <2>;
};
- ep10: endpoint@10 {
+ ep10: endpoint@a {
reg = <10>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep11: endpoint@11 {
+ ep11: endpoint@b {
reg = <11>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep12: endpoint@12 {
+ ep12: endpoint@c {
reg = <12>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep13: endpoint@13 {
+ ep13: endpoint@d {
reg = <13>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep14: endpoint@14 {
+ ep14: endpoint@e {
reg = <14>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep15: endpoint@15 {
+ ep15: endpoint@f {
reg = <15>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep10: endpoint@10 {
+ ep10: endpoint@a {
reg = <10>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep11: endpoint@11 {
+ ep11: endpoint@b {
reg = <11>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep12: endpoint@12 {
+ ep12: endpoint@c {
reg = <12>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep13: endpoint@13 {
+ ep13: endpoint@d {
reg = <13>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep14: endpoint@14 {
+ ep14: endpoint@e {
reg = <14>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep15: endpoint@15 {
+ ep15: endpoint@f {
reg = <15>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
&bsec {
- u-boot,dm-pre-proper;
+ u-boot,dm-pre-reloc;
};
&clk_csi {
u-boot,dm-pre-reloc;
};
+&cpu0_opp_table {
+ u-boot,dm-spl;
+ opp-650000000 {
+ u-boot,dm-spl;
+ };
+ opp-800000000 {
+ u-boot,dm-spl;
+ };
+};
+
&gpioa {
u-boot,dm-pre-reloc;
};
clock-frequency = <650000000>;
device_type = "cpu";
reg = <0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
};
};
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
+ part_number_otp: part_number_otp@4 {
+ reg = <0x4 0x1>;
+ };
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
- u-boot,dm-pre-reloc;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
- u-boot,dm-pre-reloc;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
};
};
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
- u-boot,dm-pre-reloc;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
- u-boot,dm-pre-reloc;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
status = "okay";
};
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rgmii_pins_a>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+&twl {
+ compatible = "ti,twl6030";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <11>;
+ };
+
+ vaux1: regulator-vaux1 {
+ compatible = "ti,twl6030-vaux1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vaux2: regulator-vaux2 {
+ compatible = "ti,twl6030-vaux2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vaux3: regulator-vaux3 {
+ compatible = "ti,twl6030-vaux3";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vmmc: regulator-vmmc {
+ compatible = "ti,twl6030-vmmc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vpp: regulator-vpp {
+ compatible = "ti,twl6030-vpp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ vusim: regulator-vusim {
+ compatible = "ti,twl6030-vusim";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vdac: regulator-vdac {
+ compatible = "ti,twl6030-vdac";
+ };
+
+ vana: regulator-vana {
+ compatible = "ti,twl6030-vana";
+ };
+
+ vcxio: regulator-vcxio {
+ compatible = "ti,twl6030-vcxio";
+ regulator-always-on;
+ };
+
+ vusb: regulator-vusb {
+ compatible = "ti,twl6030-vusb";
+ };
+
+ v1v8: regulator-v1v8 {
+ compatible = "ti,twl6030-v1v8";
+ regulator-always-on;
+ };
+
+ v2v1: regulator-v2v1 {
+ compatible = "ti,twl6030-v2v1";
+ regulator-always-on;
+ };
+
+ twl_usb_comparator: usb-comparator {
+ compatible = "ti,twl6030-usb";
+ interrupts = <4>, <10>;
+ };
+
+ twl_pwm: pwm {
+ /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */
+ compatible = "ti,twl6030-pwm";
+ #pwm-cells = <2>;
+ };
+
+ twl_pwmled: pwmled {
+ /* provides one PWM (id 0 for Charging indicator LED) */
+ compatible = "ti,twl6030-pwmled";
+ #pwm-cells = <2>;
+ };
+
+ gpadc {
+ compatible = "ti,twl6030-gpadc";
+ interrupts = <3>;
+ #io-channel-cells = <1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&twl {
+ /*
+ * On most OMAP4 platforms, the twl6030 IRQ line is connected
+ * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is
+ * connected to the fref_clk0_out.sys_drm_msecure line.
+ * Therefore, configure the defaults for the SYS_NIRQ1 and
+ * fref_clk0_out.sys_drm_msecure pins here.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &twl6030_pins
+ &twl6030_wkup_pins
+ >;
+};
+
+&omap4_pmx_wkup {
+ twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
+ >;
+ };
+};
+
+&omap4_pmx_core {
+ twl6030_pins: pinmux_twl6030_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
+ >;
+ };
+};
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
- * (C) Copyright 2019, Xilinx, Inc.
+ * (C) Copyright 2019 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <156250000>;
- clock-output-names = "si570_hsdp_clk";
+ clock-output-names = "si570_zsfp_clk";
};
};
i2c@6 { /* USER_SI570_1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
- si570_user1_clk: clock-generator@5d { /* u205 */
+ si570_user1: clock-generator@5d { /* u205 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5f>;
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- si570_ddr_dimm2: clock-generator@60 { /* u3 */
+ si570_lpddr4clk2: clock-generator@60 { /* u3 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
- si570_lpddr4: clock-generator@60 { /* u4 */
+ si570_lpddr4clk1: clock-generator@60 { /* u4 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x60>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
- spi-max-frequency = <10000000>;
+ spi-max-frequency = <108000000>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Topic XDP (Xilinx Drone Platform)
+ *
+ * (C) Copyright 2016, Topic Embedded Products BV
+ * Mike Looijmans <mike.looijmans@topic.nl>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "Topic Miamimp ZynqMP XDP v1r1";
+ compatible = "topic,miamimp-xdp-v1r1", "topic,miamimp-xdp",
+ "topic,miamimp", "xlnx,zynqmp";
+
+ aliases {
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ flash@0 {
+ compatible = "st,m25p80", "n25q256a";
+ m25p,fast-read;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <166000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ is-dual = <1>;
+ partition@0 {
+ label = "qspi-boot-bin";
+ reg = <0x00000 0x60000>;
+ };
+ partition@60000 {
+ label = "qspi-u-boot-itb";
+ reg = <0x60000 0x100000>;
+ };
+ partition@160000 {
+ label = "qspi-u-boot-env";
+ reg = <0x160000 0x20000>;
+ };
+ partition@200000 {
+ label = "qspi-rootfs";
+ reg = <0x200000 0x1e00000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* eMMC device */
+&sdhci0 {
+ status = "okay";
+ non-removable;
+ disable-wp; /* We don't have a write-protect detection */
+ bus-width = <8>;
+ xlnx,mio_bank = <0>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ xlnx,mio_bank = <1>;
+ disable-wp; /* We don't have a write-protect detection */
+ bus-width = <4>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
#define CMU_CVBSPLL 0x00B8
#define CMU_SSTSCLK 0x00C0
+#define CMU_DEVCLKEN1_ETH BIT(23)
+
+#define GPIO_MFP_PWM (0xE01B0000)
+#define MFP_CTL0 (GPIO_MFP_PWM + 0x40)
+#define MFP_CTL1 (GPIO_MFP_PWM + 0x44)
+#define MFP_CTL2 (GPIO_MFP_PWM + 0x48)
+#define MFP_CTL3 (GPIO_MFP_PWM + 0x4C)
+
#endif
#define CMU_TVOUTPLLDEBUG0 (0x00EC)
#define CMU_TVOUTPLLDEBUG1 (0x00FC)
+#define CMU_DEVCLKEN1_ETH BIT(22)
+#define CLK_ETHERNET CLK_ETH_MAC
+#define CMU_ETHERNETPLL CMU_ASSISTPLL
+
#endif
gd_t *gd_ptr;
#ifdef CONFIG_ARM64
- /*
- * Make will already error that reserving x18 is not supported at the
- * time of writing, clang: error: unknown argument: '-ffixed-x18'
- */
__asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr));
#else
__asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr));
static inline unsigned int current_el(void)
{
- unsigned int el;
+ unsigned long el;
+
asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
- return el >> 2;
+ return 3 & (el >> 2);
}
static inline unsigned int get_sctlr(void)
{
- unsigned int el, val;
+ unsigned int el;
+ unsigned long val;
el = current_el();
if (el == 1)
return val;
}
-static inline void set_sctlr(unsigned int val)
+static inline void set_sctlr(unsigned long val)
{
unsigned int el;
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
+obj-y += bdinfo.o
obj-y += sections.o
obj-y += stack.o
ifdef CONFIG_CPU_V7M
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ARM-specific information for the 'bd' command
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void arch_print_bdinfo(void)
+{
+ bd_t *bd = gd->bd;
+
+ bdinfo_print_num("arch_number", bd->bi_arch_number);
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
+ bdinfo_print_num("Secure ram",
+ gd->arch.secure_ram &
+ MEM_RESERVE_SECURE_ADDR_MASK);
+ }
+#endif
+#ifdef CONFIG_RESV_RAM
+ if (gd->arch.resv_ram)
+ bdinfo_print_num("Reserved ram", gd->arch.resv_ram);
+#endif
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ bdinfo_print_num("TLB addr", gd->arch.tlb_addr);
+#endif
+ bdinfo_print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
+ bdinfo_print_num("sp start ", gd->start_addr_sp);
+ /*
+ * TODO: Currently only support for davinci SOC's is added.
+ * Remove this check once all the board implement this.
+ */
+#ifdef CONFIG_CLOCKS
+ printf("ARM frequency = %ld MHz\n", bd->bi_arm_freq);
+ printf("DSP frequency = %ld MHz\n", bd->bi_dsp_freq);
+ printf("DDR frequency = %ld MHz\n", bd->bi_ddr_freq);
+#endif
+#ifdef CONFIG_BOARD_TYPES
+ printf("Board Type = %ld\n", gd->board_type);
+#endif
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
+ CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
+}
#ifndef __AT91RM9200_H__
#define __AT91RM9200_H__
-#define CONFIG_AT91_GPIO /* and require always gpio features */
-
/* Periperial Identifiers */
#define ATMEL_ID_SYS 1 /* System Peripheral */
struct mmc_config cfg;
};
+#define DAVINCI_MAX_BLOCKS (32)
+struct davinci_mmc_plat {
+ struct davinci_mmc_regs *reg_base; /* Register base address */
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
#endif /* _SDMMC_DEFS_H */
config CSF_SIZE
hex "Maximum size for Command Sequence File (CSF) binary"
+ depends on IMX_HAB
+ default 0x2000 if ARCH_IMX8M
default 0x2060
help
Define the maximum size for Command Sequence File (CSF) binary
/*
* Secure boot support
*/
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
-source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/am335x/Kconfig"
#include <asm/mach-types.h>
#include <asm/psci.h>
+#define DMM_INTERLEAVE_PER_CH_CFG 0xe0290028
+
DECLARE_GLOBAL_DATA_PTR;
+unsigned int owl_get_ddrcap(void)
+{
+ unsigned int val, cap;
+
+ /* ddr capacity register initialized by ddr driver
+ * in early bootloader
+ */
+#if defined(CONFIG_MACH_S700)
+ val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0x7;
+ cap = (val + 1) * 256;
+#elif defined(CONFIG_MACH_S900)
+ val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0xf;
+ cap = 64 * (1 << val);
+#endif
+
+ return cap;
+}
+
/*
* dram_init - sets uboots idea of sdram size
*/
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = owl_get_ddrcap() * 1024 * 1024;
return 0;
}
#ifdef CONFIG_FPGA
void socfpga_fpga_add(void *fpga_desc);
#else
-inline void socfpga_fpga_add(void *fpga_desc) {}
+static inline void socfpga_fpga_add(void *fpga_desc) {}
#endif
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
if ARCH_STM32MP
config SPL
- select SPL_BOARD_INIT
select SPL_CLK
select SPL_DM
select SPL_DM_SEQ_ALIAS
select STM32_RESET
select STM32_SERIAL
select SYS_ARCH_TIMER
+ imply CMD_NVEDIT_INFO
imply SYSRESET_PSCI if TFABOOT
imply SYSRESET_SYSCON if !TFABOOT
help
obj-y += cpu.o
obj-y += dram_init.o
obj-y += syscon.o
+obj-y += bsec.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog/
-obj-y += bsec.o
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_TFABOOT) += boot_params.o
#include <log.h>
#include <misc.h>
#include <asm/io.h>
+#include <asm/arch/bsec.h>
#include <asm/arch/stm32mp1_smc.h>
#include <linux/arm-smccc.h>
#include <linux/iopoll.h>
#define BSEC_OTP_WRDATA_OFF 0x008
#define BSEC_OTP_STATUS_OFF 0x00C
#define BSEC_OTP_LOCK_OFF 0x010
+#define BSEC_DENABLE_OFF 0x014
#define BSEC_DISTURBED_OFF 0x01C
#define BSEC_ERROR_OFF 0x034
#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
#define BSEC_MODE_PROGFAIL_MASK 0x10
#define BSEC_MODE_PWR_MASK 0x20
+/* DENABLE Register */
+#define BSEC_DENABLE_DBGSWENABLE BIT(10)
+
/*
* OTP Lock services definition
* Value must corresponding to the bit number in the register
return 0;
}
-#ifndef CONFIG_TFABOOT
static int stm32mp_bsec_probe(struct udevice *dev)
{
+#if !defined(CONFIG_TFABOOT) && !defined(CONFIG_SPL_BUILD)
int otp;
struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
- /* update unlocked shadow for OTP cleared by the rom code */
+ /*
+ * update unlocked shadow for OTP cleared by the rom code
+ * only executed in U-Boot proper when TF-A is not used
+ */
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
if (!bsec_read_SR_lock(plat->base, otp))
bsec_shadow_register(plat->base, otp);
+#endif
return 0;
}
-#endif
static const struct udevice_id stm32mp_bsec_ids[] = {
{ .compatible = "st,stm32mp15-bsec" },
.ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata),
.ops = &stm32mp_bsec_ops,
-#ifndef CONFIG_TFABOOT
.probe = stm32mp_bsec_probe,
-#endif
};
+
+bool bsec_dbgswenable(void)
+{
+ struct udevice *dev;
+ struct stm32mp_bsec_platdata *plat;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec), &dev);
+ if (ret || !dev) {
+ pr_debug("bsec driver not available\n");
+ return false;
+ }
+
+ plat = dev_get_platdata(dev);
+ if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
+ return true;
+
+ return false;
+}
bool result;
/* USB download gadget for STM32 Programmer */
char product[128];
+ char name[SOC_NAME_SIZE];
+ get_soc_name(name);
snprintf(product, sizeof(product),
- "USB download gadget@Device ID /0x%03X, @Revision ID /0x%04X",
- get_cpu_dev(), get_cpu_rev());
+ "USB download gadget@Device ID /0x%03X, @Revision ID /0x%04X, @Name /%s,",
+ get_cpu_dev(), get_cpu_rev(), name);
g_dnl_set_product(product);
if (stm32prog_data->phase == PHASE_FLASHLAYOUT) {
#include <misc.h>
#include <net.h>
#include <asm/io.h>
+#include <asm/arch/bsec.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
{
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
- /* Freeze IWDG2 if Cortex-A7 is in debug mode */
- setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+ /*
+ * Freeze IWDG2 if Cortex-A7 is in debug mode
+ * done in TF-A for TRUSTED boot and
+ * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
+ */
+ if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable())
+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
}
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
static u32 read_idc(void)
{
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+ /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
+ if (bsec_dbgswenable()) {
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
- return readl(DBGMCU_IDC);
+ return readl(DBGMCU_IDC);
+ }
+
+ if (CONFIG_IS_ENABLED(STM32MP15x))
+ return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
+ else
+ return 0x0;
}
u32 get_cpu_dev(void)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+/* check self hosted debug status = BSEC_DENABLE.DBGSWENABLE */
+bool bsec_dbgswenable(void);
u32 get_bootmode(void);
int setup_mac_address(void);
+
+/* board power management : configure vddcore according OPP */
+void board_vddcore_init(u32 voltage_mv);
select MISC
select OF_CONTROL
select SPI
- select VIDCONSOLE_AS_LCD if DM_VIDEO
imply CMD_DM
imply CRC32_VERIFY
{
/*
* This function performs multiple checks on the same values with
- * security implications, so create snapshots with ACCESS_ONCE() to
+ * security implications, so create snapshots with READ_ONCE() to
* ensure that these checks use the same values.
*/
- uint32_t w_count = ACCESS_ONCE(ch->w_count);
- uint32_t r_count = ACCESS_ONCE(ch->r_count);
+ uint32_t w_count = READ_ONCE(ch->w_count);
+ uint32_t r_count = READ_ONCE(ch->r_count);
/*
* Perform an over-full check to prevent denial of service attacks where
* Invalid cases where the counters indicate that the queue is over
* capacity also appear full.
*/
- return (ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count)) >=
+ return (READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count)) >=
ivc->nframes;
}
static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc)
{
- ACCESS_ONCE(ivc->rx_channel->r_count) =
- ACCESS_ONCE(ivc->rx_channel->r_count) + 1;
+ WRITE_ONCE(ivc->rx_channel->r_count,
+ READ_ONCE(ivc->rx_channel->r_count) + 1);
if (ivc->r_pos == ivc->nframes - 1)
ivc->r_pos = 0;
static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc)
{
- ACCESS_ONCE(ivc->tx_channel->w_count) =
- ACCESS_ONCE(ivc->tx_channel->w_count) + 1;
+ WRITE_ONCE(ivc->tx_channel->w_count,
+ READ_ONCE(ivc->tx_channel->w_count) + 1);
if (ivc->w_pos == ivc->nframes - 1)
ivc->w_pos = 0;
* comment in tegra_ivc_channel_empty() for an explanation about
* special over-full considerations.
*/
- return ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count);
+ return READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count);
}
int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame)
/* Copy the receiver's state out of shared memory. */
offset = offsetof(struct tegra_ivc_channel_header, w_count);
tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset);
- peer_state = ACCESS_ONCE(ivc->rx_channel->state);
+ peer_state = READ_ONCE(ivc->rx_channel->state);
if (peer_state == ivc_state_sync) {
/*
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := m68k-elf-
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
PLATFORM_CPPFLAGS += -D__M68K__
## if the user asked for it
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o
+obj-y += bdinfo.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += interrupts.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PPC-specific information for the 'bd' command
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void arch_print_bdinfo(void)
+{
+ bd_t *bd = gd->bd;
+
+#if defined(CONFIG_SYS_INIT_RAM_ADDR)
+ bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
+ bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
+#endif
+ bdinfo_print_mhz("busfreq", bd->bi_busfreq);
+#if defined(CONFIG_SYS_MBAR)
+ bdinfo_print_num("mbar", bd->bi_mbar_base);
+#endif
+ bdinfo_print_mhz("cpufreq", bd->bi_intfreq);
+ if (IS_ENABLED(CONFIG_PCI))
+ bdinfo_print_mhz("pcifreq", bd->bi_pcifreq);
+#ifdef CONFIG_EXTRA_CLOCK
+ bdinfo_print_mhz("flbfreq", bd->bi_flbfreq);
+ bdinfo_print_mhz("inpfreq", bd->bi_inpfreq);
+ bdinfo_print_mhz("vcofreq", bd->bi_vcofreq);
+#endif
+}
# (C) Copyright 2004 Atmark Techno, Inc.
# Yasushi SHOJI <yashi@atmark-techno.com>
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := mb-
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := nds32le-linux-
-endif
-
CONFIG_STANDALONE_LOAD_ADDR = 0x300000
LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/nds32.lds
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
#include <asm/u-boot-nds32.h>
-
-typedef struct bd_info {
- unsigned long bi_arch_number; /* unique id for this board */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- unsigned long bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned char bi_enetaddr[6];
-
- struct /* RAM configuration */
- {
- unsigned long start;
- unsigned long size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
-} bd_t;
-
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_NDS32
# Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := nios2-elf-
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000
PLATFORM_CPPFLAGS += -D__NIOS2__
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := ppc_8xx-
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
LDFLAGS_FINAL += --gc-sections
LDFLAGS_FINAL += --bss-plt
bool "Support socrates"
select ARCH_MPC8544
-config TARGET_B4420QDS
- bool "Support B4420QDS"
- select ARCH_B4420
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
-config TARGET_B4860QDS
- bool "Support B4860QDS"
- select ARCH_B4860
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- select FSL_DDR_INTERACTIVE if !SPL_BUILD
- imply PANIC_HANG
-
-config TARGET_BSC9131RDB
- bool "Support BSC9131RDB"
- select ARCH_BSC9131
- select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
-
-config TARGET_BSC9132QDS
- bool "Support BSC9132QDS"
- select ARCH_BSC9132
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
- select FSL_DDR_INTERACTIVE
-
-config TARGET_C29XPCIE
- bool "Support C29XPCIE"
- select ARCH_C29X
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select SUPPORT_TPL
- select PHYS_64BIT
- imply PANIC_HANG
-
config TARGET_P3041DS
bool "Support P3041DS"
select PHYS_64BIT
imply CMD_SATA
imply PANIC_HANG
-config TARGET_MPC8536DS
- bool "Support MPC8536DS"
- select ARCH_MPC8536
-# Use DDR3 controller with DDR2 DIMMs on this board
- select SYS_FSL_DDRC_GEN3
- imply CMD_SATA
- imply FSL_SATA
-
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
select ARCH_MPC8541
imply CMD_SATA
imply PANIC_HANG
-config TARGET_P1022DS
- bool "Support P1022DS"
- select ARCH_P1022
- select SUPPORT_SPL
- select SUPPORT_TPL
- imply CMD_SATA
- imply FSL_SATA
-
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1023
imply CMD_SATA
imply SATA_SIL
-config TARGET_P1_TWR
- bool "Support p1_twr"
- select ARCH_P1025
-
config TARGET_P2041RDB
bool "Support P2041RDB"
select ARCH_P2041
select ARCH_QEMU_E500
select PHYS_64BIT
-config TARGET_T1024QDS
- bool "Support T1024QDS"
- select ARCH_T1024
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- imply CMD_EEPROM
- imply CMD_SATA
- imply FSL_SATA
-
config TARGET_T1023RDB
bool "Support T1023RDB"
select ARCH_T1023
imply CMD_EEPROM
imply PANIC_HANG
-config TARGET_T1040QDS
- bool "Support T1040QDS"
- select ARCH_T1040
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select PHYS_64BIT
- select FSL_DDR_INTERACTIVE
- imply CMD_EEPROM
- imply CMD_SATA
- imply PANIC_HANG
-
config TARGET_T1040RDB
bool "Support T1040RDB"
select ARCH_T1040
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
-config TARGET_T4160QDS
- bool "Support T4160QDS"
- select ARCH_T4160
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- imply CMD_SATA
- imply PANIC_HANG
-
config TARGET_T4160RDB
bool "Support T4160RDB"
select ARCH_T4160
select PHYS_64BIT
imply PANIC_HANG
-config TARGET_T4240QDS
- bool "Support T4240QDS"
- select ARCH_T4240
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
- imply CMD_SATA
- imply PANIC_HANG
-
config TARGET_T4240RDB
bool "Support T4240RDB"
select ARCH_T4240
Defines divider of platform clock(clock input to
eLBC controller).
-source "board/freescale/b4860qds/Kconfig"
-source "board/freescale/bsc9131rdb/Kconfig"
-source "board/freescale/bsc9132qds/Kconfig"
-source "board/freescale/c29xpcie/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
-source "board/freescale/mpc8536ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8544ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
-source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
-source "board/freescale/p1_twr/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t102xqds/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
-source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
-source "board/freescale/t4qds/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"
endif
endif
+obj-y += bdinfo.o
+
ifdef MINIMAL
obj-y += cache.o time.o
ifndef CONFIG_TIMER
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PPC-specific information for the 'bd' command
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_detail(void)
+{
+ /* Please define board_detail() for your PPC platform */
+}
+
+void arch_print_bdinfo(void)
+{
+ bd_t *bd = gd->bd;
+
+#if defined(CONFIG_SYS_INIT_RAM_ADDR)
+ bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
+ bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
+#endif
+ bdinfo_print_mhz("busfreq", bd->bi_busfreq);
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
+ bdinfo_print_num("immr_base", bd->bi_immr_base);
+#endif
+ bdinfo_print_num("bootflags", bd->bi_bootflags);
+ bdinfo_print_mhz("intfreq", bd->bi_intfreq);
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+ if (IS_ENABLED(CONFIG_PHYS_64BIT))
+ puts("addressing = 36-bit\n");
+ else
+ puts("addressing = 32-bit\n");
+#endif
+ board_detail();
+#if defined(CONFIG_CPM2)
+ bdinfo_print_mhz("cpmfreq", bd->bi_cpmfreq);
+ bdinfo_print_mhz("vco", bd->bi_vco);
+ bdinfo_print_mhz("sccfreq", bd->bi_sccfreq);
+ bdinfo_print_mhz("brgfreq", bd->bi_brgfreq);
+#endif
+}
config TARGET_SIFIVE_FU540
bool "Support SiFive FU540 Board"
+config TARGET_SIPEED_MAIX
+ bool "Support Sipeed Maix Board"
+
endchoice
config SYS_ICACHE_OFF
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
+source "board/sipeed/maix/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
config SHOW_REGS
bool "Show registers on unhandled exception"
+config RISCV_PRIV_1_9
+ bool "Use version 1.9 of the RISC-V priviledged specification"
+ help
+ Older versions of the RISC-V priviledged specification had
+ separate counter enable CSRs for each privilege mode. Writing
+ to the unified mcounteren CSR on a processor implementing the
+ old specification will result in an illegal instruction
+ exception. In addition to counter CSR changes, the way virtual
+ memory is configured was also changed.
+
config STACK_SIZE_SHIFT
int
default 14
* Enable perf counters for cycle, time,
* and instret counters only
*/
+#ifdef CONFIG_RISCV_PRIV_1_9
+ csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+ csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
/* Disable paging */
if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9
+ csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
csr_write(CSR_SATP, 0);
+#endif
}
+#ifdef CONFIG_SMP
+ ret = riscv_init_ipi();
+ if (ret)
+ return ret;
+#endif
+
return 0;
}
#else
li t0, SIE_SSIE
#endif
+ /* Clear any pending IPIs */
+ csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0
#endif
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
targets += $(dtb-y)
/ {
aliases {
+ cpu1 = &cpu1;
+ cpu2 = &cpu2;
+ cpu3 = &cpu3;
+ cpu4 = &cpu4;
spi0 = &qspi0;
spi2 = &qspi2;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "k210.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Sipeed Maix Bit 2.0";
+ compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210";
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&mic>;
+ };
+ };
+
+ mic: mic {
+ #sound-dai-cells = <0>;
+ compatible = "memsensing,msm61s4030h0";
+ status = "disabled";
+ };
+};
+
+&uarths0 {
+ status = "okay";
+};
+
+&i2s0 {
+ #sound-dai-cells = <1>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <dt-bindings/mfd/k210-sysctl.h>
+#include <dt-bindings/reset/k210-sysctl.h>
+
+/ {
+ /*
+ * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
+ * wide, and the upper half of all addresses is ignored.
+ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "kendryte,k210";
+
+ aliases {
+ dma0 = &dmac0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1_0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ pinctrl0 = &fpioa;
+ serial0 = &uarths0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ timer0 = &timer0;
+ timer1 = &timer1;
+ timer2 = &timer2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <7800000>;
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+ reg = <0>;
+ riscv,isa = "rv64imafdgc";
+ mmu-type = "sv39";
+ i-cache-block-size = <64>;
+ i-cache-size = <0x8000>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x8000>;
+ clocks = <&sysclk K210_CLK_CPU>;
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+ reg = <1>;
+ riscv,isa = "rv64imafdgc";
+ mmu-type = "sv39";
+ i-cache-block-size = <64>;
+ i-cache-size = <0x8000>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x8000>;
+ clocks = <&sysclk K210_CLK_CPU>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
+
+ sram: memory@80000000 {
+ device_type = "memory";
+ compatible = "kendryte,k210-sram";
+ reg = <0x80000000 0x400000>,
+ <0x80400000 0x200000>,
+ <0x80600000 0x200000>;
+ reg-names = "sram0", "sram1", "airam";
+ clocks = <&sysclk K210_CLK_SRAM0>,
+ <&sysclk K210_CLK_SRAM1>,
+ <&sysclk K210_CLK_PLL1>;
+ clock-names = "sram0", "sram1", "airam";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ai_reserved: ai@80600000 {
+ reg = <0x80600000 0x200000>;
+ reusable;
+ };
+ };
+
+ clocks {
+ in0: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "kendryte,k210-soc", "simple-bus";
+ ranges;
+ interrupt-parent = <&plic0>;
+
+ debug0: debug@0 {
+ compatible = "kendryte,k210-debug", "riscv,debug";
+ reg = <0x0 0x1000>;
+ };
+
+ rom0: nvmem@1000 {
+ reg = <0x1000 0x1000>;
+ read-only;
+ };
+
+ clint0: interrupt-controller@2000000 {
+ #interrupt-cells = <1>;
+ compatible = "kendryte,k210-clint", "riscv,clint0";
+ reg = <0x2000000 0xC000>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
+ clocks = <&sysclk K210_CLK_CPU>;
+ };
+
+ plic0: interrupt-controller@C000000 {
+ #interrupt-cells = <1>;
+ compatible = "kendryte,k210-plic", "riscv,plic0";
+ reg = <0xC000000 0x4000000>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
+ <&cpu1_intc 9>, <&cpu1_intc 11>;
+ riscv,ndev = <65>;
+ riscv,max-priority = <7>;
+ };
+
+ uarths0: serial@38000000 {
+ compatible = "kendryte,k210-uarths", "sifive,uart0";
+ reg = <0x38000000 0x1000>;
+ interrupts = <33>;
+ clocks = <&sysclk K210_CLK_CPU>;
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@38001000 {
+ #interrupt-cells = <2>;
+ #gpio-cells = <2>;
+ compatible = "kendryte,k210-gpiohs", "sifive,gpio0";
+ reg = <0x38001000 0x1000>;
+ interrupt-controller;
+ interrupts = <34 35 36 37 38 39 40 41
+ 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57
+ 58 59 60 61 62 63 64 65>;
+ gpio-controller;
+ ngpios = <32>;
+ status = "disabled";
+ };
+
+ kpu0: kpu@40800000 {
+ compatible = "kendryte,k210-kpu";
+ reg = <0x40800000 0xc00000>;
+ interrupts = <25>;
+ clocks = <&sysclk K210_CLK_AI>;
+ memory-region = <&ai_reserved>;
+ status = "disabled";
+ };
+
+ fft0: fft@42000000 {
+ compatible = "kendryte,k210-fft";
+ reg = <0x42000000 0x400000>;
+ interrupts = <26>;
+ clocks = <&sysclk K210_CLK_FFT>;
+ resets = <&sysrst K210_RST_FFT>;
+ status = "disabled";
+ };
+
+ dmac0: dma-controller@50000000 {
+ compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a";
+ reg = <0x50000000 0x1000>;
+ interrupts = <27 28 29 30 31 32>;
+ clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&sysrst K210_RST_DMA>;
+ dma-channels = <6>;
+ snps,dma-masters = <2>;
+ snps,data-width = <5>;
+ snps,block-size = <0x400000 0x400000 0x400000
+ 0x400000 0x400000 0x400000>;
+ snps,axi-max-burst-len = <256>;
+ status = "disabled";
+ };
+
+ apb0: bus@50200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "kendryte,k210-apb", "simple-pm-bus";
+ ranges;
+ clocks = <&sysclk K210_CLK_APB0>;
+
+ gpio1: gpio-controller@50200000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "kendryte,k210-gpio",
+ "snps,dw-apb-gpio";
+ reg = <0x50200000 0x80>;
+ clocks = <&sysclk K210_CLK_GPIO>;
+ resets = <&sysrst K210_RST_GPIO>;
+ status = "disabled";
+
+ gpio1_0: gpio1@0 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ interrupt-controller;
+ interrupts = <23>;
+ gpio-controller;
+ snps,nr-gpios = <8>;
+ };
+ };
+
+ uart1: serial@50210000 {
+ compatible = "kendryte,k210-uart",
+ "snps,dw-apb-uart";
+ reg = <0x50210000 0x100>;
+ interrupts = <11>;
+ clocks = <&sysclk K210_CLK_UART1>;
+ resets = <&sysrst K210_RST_UART1>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ dcd-override;
+ dsr-override;
+ cts-override;
+ ri-override;
+ status = "disabled";
+ };
+
+ uart2: serial@50220000 {
+ compatible = "kendryte,k210-uart",
+ "snps,dw-apb-uart";
+ reg = <0x50220000 0x100>;
+ interrupts = <12>;
+ clocks = <&sysclk K210_CLK_UART2>;
+ resets = <&sysrst K210_RST_UART2>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ dcd-override;
+ dsr-override;
+ cts-override;
+ ri-override;
+ status = "disabled";
+ };
+
+ uart3: serial@50230000 {
+ compatible = "kendryte,k210-uart",
+ "snps,dw-apb-uart";
+ reg = <0x50230000 0x100>;
+ interrupts = <13>;
+ clocks = <&sysclk K210_CLK_UART3>;
+ resets = <&sysrst K210_RST_UART3>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ dcd-override;
+ dsr-override;
+ cts-override;
+ ri-override;
+ status = "disabled";
+ };
+
+ spi2: spi@50240000 {
+ compatible = "kendryte,k120-spislave",
+ "snps,dw-apb-ssi";
+ spi-slave;
+ reg = <0x50240000 0x100>;
+ interrupts = <2>;
+ clocks = <&sysclk K210_CLK_SPI2>;
+ resets = <&sysrst K210_RST_SPI2>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ i2s0: i2s@50250000 {
+ compatible = "kendryte,k210-i2s",
+ "snps,designware-i2s";
+ reg = <0x50250000 0x200>;
+ interrupts = <5>;
+ clocks = <&sysclk K210_CLK_I2S0>;
+ clock-names = "i2sclk";
+ resets = <&sysrst K210_RST_I2S0>;
+ status = "disabled";
+ };
+
+ apu0: sound@520250200 {
+ compatible = "kendryte,k210-apu";
+ reg = <0x50250200 0x200>;
+ status = "disabled";
+ };
+
+ i2s1: i2s@50260000 {
+ compatible = "kendryte,k210-i2s",
+ "snps,designware-i2s";
+ reg = <0x50260000 0x200>;
+ interrupts = <6>;
+ clocks = <&sysclk K210_CLK_I2S1>;
+ clock-names = "i2sclk";
+ resets = <&sysrst K210_RST_I2S1>;
+ status = "disabled";
+ };
+
+ i2s2: i2s@50270000 {
+ compatible = "kendryte,k210-i2s",
+ "snps,designware-i2s";
+ reg = <0x50270000 0x200>;
+ interrupts = <7>;
+ clocks = <&sysclk K210_CLK_I2S2>;
+ clock-names = "i2sclk";
+ resets = <&sysrst K210_RST_I2S2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@50280000 {
+ compatible = "kendryte,k210-i2c",
+ "snps,designware-i2c";
+ reg = <0x50280000 0x100>;
+ interrupts = <8>;
+ clocks = <&sysclk K210_CLK_I2C0>;
+ resets = <&sysrst K210_RST_I2C0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@50290000 {
+ compatible = "kendryte,k210-i2c",
+ "snps,designware-i2c";
+ reg = <0x50290000 0x100>;
+ interrupts = <9>;
+ clocks = <&sysclk K210_CLK_I2C1>;
+ resets = <&sysrst K210_RST_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@502A0000 {
+ compatible = "kendryte,k210-i2c",
+ "snps,designware-i2c";
+ reg = <0x502A0000 0x100>;
+ interrupts = <10>;
+ clocks = <&sysclk K210_CLK_I2C2>;
+ resets = <&sysrst K210_RST_I2C2>;
+ status = "disabled";
+ };
+
+ fpioa: pinmux@502B0000 {
+ compatible = "kendryte,k210-fpioa";
+ reg = <0x502B0000 0x100>;
+ clocks = <&sysclk K210_CLK_FPIOA>;
+ resets = <&sysrst K210_RST_FPIOA>;
+ status = "disabled";
+ };
+
+ sha256: sha256@502C0000 {
+ compatible = "kendryte,k210-sha256";
+ reg = <0x502C0000 0x100>;
+ clocks = <&sysclk K210_CLK_SHA>;
+ resets = <&sysrst K210_RST_SHA>;
+ status = "disabled";
+ };
+
+ timer0: timer@502D0000 {
+ compatible = "kendryte,k210-timer",
+ "snps,dw-apb-timer";
+ reg = <0x502D0000 0x100>;
+ interrupts = <14 15>;
+ clocks = <&sysclk K210_CLK_TIMER0>;
+ clock-names = "timer";
+ resets = <&sysrst K210_RST_TIMER0>;
+ status = "disabled";
+ };
+
+ timer1: timer@502E0000 {
+ compatible = "kendryte,k210-timer",
+ "snps,dw-apb-timer";
+ reg = <0x502E0000 0x100>;
+ interrupts = <16 17>;
+ clocks = <&sysclk K210_CLK_TIMER1>;
+ clock-names = "timer";
+ resets = <&sysrst K210_RST_TIMER1>;
+ status = "disabled";
+ };
+
+ timer2: timer@502F0000 {
+ compatible = "kendryte,k210-timer",
+ "snps,dw-apb-timer";
+ reg = <0x502F0000 0x100>;
+ interrupts = <18 19>;
+ clocks = <&sysclk K210_CLK_TIMER2>;
+ clock-names = "timer";
+ resets = <&sysrst K210_RST_TIMER2>;
+ status = "disabled";
+ };
+ };
+
+ apb1: bus@50400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "kendryte,k210-apb", "simple-pm-bus";
+ ranges;
+ clocks = <&sysclk K210_CLK_APB1>;
+
+ wdt0: watchdog@50400000 {
+ compatible = "kendryte,k210-wdt", "snps,dw-wdt";
+ reg = <0x50400000 0x100>;
+ interrupts = <21>;
+ clocks = <&sysclk K210_CLK_WDT0>;
+ resets = <&sysrst K210_RST_WDT0>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@50410000 {
+ compatible = "kendryte,k210-wdt", "snps,dw-wdt";
+ reg = <0x50410000 0x100>;
+ interrupts = <22>;
+ clocks = <&sysclk K210_CLK_WDT1>;
+ resets = <&sysrst K210_RST_WDT1>;
+ status = "disabled";
+ };
+
+ otp0: nvmem@50420000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "kendryte,k210-otp";
+ reg = <0x50420000 0x100>,
+ <0x88000000 0x20000>;
+ reg-names = "reg", "mem";
+ clocks = <&sysclk K210_CLK_ROM>;
+ resets = <&sysrst K210_RST_ROM>;
+ read-only;
+ status = "disabled";
+
+ /* Bootloader */
+ firmware@00000 {
+ reg = <0x00000 0xC200>;
+ };
+
+ /*
+ * config string as described in RISC-V
+ * privileged spec 1.9
+ */
+ config-1-9@1c000 {
+ reg = <0x1C000 0x1000>;
+ };
+
+ /*
+ * Device tree containing only registers,
+ * interrupts, and cpus
+ */
+ fdt@1d000 {
+ reg = <0x1D000 0x2000>;
+ };
+
+ /* CPU/ROM credits */
+ credits@1f000 {
+ reg = <0x1F000 0x1000>;
+ };
+ };
+
+ dvp0: camera@50430000 {
+ compatible = "kendryte,k210-dvp";
+ reg = <0x50430000 0x100>;
+ interrupts = <24>;
+ clocks = <&sysclk K210_CLK_DVP>;
+ resets = <&sysrst K210_RST_DVP>;
+ status = "disabled";
+ };
+
+ sysctl: syscon@50440000 {
+ compatible = "kendryte,k210-sysctl",
+ "syscon", "simple-mfd";
+ reg = <0x50440000 0x100>;
+ reg-io-width = <4>;
+
+ sysclk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "kendryte,k210-clk";
+ clocks = <&in0>;
+ };
+
+ sysrst: reset-controller {
+ compatible = "kendryte,k210-rst",
+ "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&sysctl>;
+ offset = <K210_SYSCTL_PERI_RESET>;
+ mask = <0x27FFFFFF>;
+ assert-high = <1>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&sysctl>;
+ offset = <K210_SYSCTL_SOFT_RESET>;
+ mask = <1>;
+ value = <1>;
+ };
+ };
+
+ aes0: aes@50450000 {
+ compatible = "kendryte,k210-aes";
+ reg = <0x50450000 0x100>;
+ clocks = <&sysclk K210_CLK_AES>;
+ resets = <&sysrst K210_RST_AES>;
+ status = "disabled";
+ };
+
+ rtc: rtc@50460000 {
+ compatible = "kendryte,k210-rtc";
+ reg = <0x50460000 0x100>;
+ clocks = <&in0>;
+ resets = <&sysrst K210_RST_RTC>;
+ interrupts = <20>;
+ status = "disabled";
+ };
+ };
+
+ apb2: bus@52000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "kendryte,k210-apb", "simple-pm-bus";
+ ranges;
+ clocks = <&sysclk K210_CLK_APB2>;
+
+ spi0: spi@52000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "kendryte,k210-spi",
+ "snps,dw-apb-ssi";
+ reg = <0x52000000 0x100>;
+ interrupts = <1>;
+ clocks = <&sysclk K210_CLK_SPI0>;
+ clock-names = "ssi_clk";
+ resets = <&sysrst K210_RST_SPI0>;
+ spi-max-frequency = <25000000>;
+ num-cs = <4>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi1: spi@53000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "kendryte,k210-spi",
+ "snps,dw-apb-ssi";
+ reg = <0x53000000 0x100>;
+ interrupts = <2>;
+ clocks = <&sysclk K210_CLK_SPI1>;
+ clock-names = "ssi_clk";
+ resets = <&sysrst K210_RST_SPI1>;
+ spi-max-frequency = <25000000>;
+ num-cs = <4>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi3: spi@54000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "kendryte,k210-spi",
+ "snps,dw-apb-ssi";
+ reg = <0x54000000 0x200>;
+ interrupts = <4>;
+ clocks = <&sysclk K210_CLK_SPI3>;
+ clock-names = "ssi_clk";
+ resets = <&sysrst K210_RST_SPI3>;
+ /* Could possibly go up to 200 MHz */
+ spi-max-frequency = <100000000>;
+ num-cs = <4>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+ };
+ };
+};
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_PUM _AC(0x00040000, UL) /* Protect User Memory Access */
+#else
#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
+#endif
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF _AC(0x00000000, UL)
#define SR_XS_CLEAN _AC(0x00010000, UL)
#define SR_XS_DIRTY _AC(0x00018000, UL)
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_VM _AC(0x1F000000, UL) /* Virtualization Management */
+#define SR_VM_MODE_BARE _AC(0x00000000, UL) /* No translation or protection */
+#define SR_VM_MODE_BB _AC(0x01000000, UL) /* Single base-and-bound */
+/* Separate instruction and data base-and-bound */
+#define SR_VM_MODE_BBID _AC(0x02000000, UL)
+#ifndef CONFIG_64BIT
+#define SR_VM_MODE_32 _AC(0x08000000, UL)
+#define SR_VM_MODE SR_VM_MODE_32
+#else
+#define SR_VM_MODE_39 _AC(0x09000000, UL)
+#define SR_VM_MODE_48 _AC(0x0A000000, UL)
+#define SR_VM_MODE SR_VM_MODE_39
+#endif
+#endif
+
#ifndef CONFIG_64BIT
#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
#else
#endif
/* SATP flags */
+#ifndef CONFIG_RISCV_PRIV_1_9
#ifndef CONFIG_64BIT
#define SATP_PPN _AC(0x003FFFFF, UL)
#define SATP_MODE_32 _AC(0x80000000, UL)
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
#define SATP_MODE SATP_MODE_39
#endif
+#endif
/* SCAUSE */
#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
#define CSR_SCAUSE 0x142
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_SPTBR 0x180
+#else
#define CSR_SATP 0x180
+#endif
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHCOUNTEREN 0x322
+#else
#define CSR_MCOUNTEREN 0x306
+#endif
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_MBASE 0x380
+#define CSR_MBOUND 0x381
+#define CSR_MIBASE 0x382
+#define CSR_MIBOUND 0x383
+#define CSR_MDBASE 0x384
+#define CSR_MDBOUND 0x385
+#endif
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define __ASM_GBL_DATA_H
#include <asm/smp.h>
+#include <asm/u-boot.h>
+#include <compiler.h>
/* Architecture-specific global data */
struct arch_global_data {
*/
int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
+/**
+ * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
+ *
+ * Platform code must provide this function. This function is called once after
+ * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
+ * before this function is called.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int riscv_init_ipi(void);
+
+/**
+ * riscv_send_ipi() - Send inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of receiving hart
+ * @return 0 if OK, -ve on error
+ */
+int riscv_send_ipi(int hart);
+
+/**
+ * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be cleared
+ * @return 0 if OK, -ve on error
+ */
+int riscv_clear_ipi(int hart);
+
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ * 1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+int riscv_get_ipi(int hart, int *pending);
+
#endif
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
#include <asm/u-boot-riscv.h>
-
-typedef struct bd_info {
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- unsigned long bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned char bi_enetaddr[6];
-
- struct /* RAM configuration */
- {
- unsigned long start;
- unsigned long size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
-} bd_t;
-
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_RISCV
#define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
DECLARE_GLOBAL_DATA_PTR;
-static int init_plic(void);
-
-#define PLIC_BASE_GET(void) \
- do { \
- long *ret; \
- \
- if (!gd->arch.plic) { \
- ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
- if (IS_ERR(ret)) \
- return PTR_ERR(ret); \
- gd->arch.plic = ret; \
- init_plic(); \
- } \
- } while (0)
static int enable_ipi(int hart)
{
return -ENODEV;
}
-int riscv_send_ipi(int hart)
+int riscv_init_ipi(void)
{
- unsigned int ipi;
+ long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
+
+ if (IS_ERR(ret))
+ return PTR_ERR(ret);
+ gd->arch.plic = ret;
+
+ return init_plic();
+}
- PLIC_BASE_GET();
+int riscv_send_ipi(int hart)
+{
+ unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
- ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
{
u32 source_id;
- PLIC_BASE_GET();
-
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
int riscv_get_ipi(int hart, int *pending)
{
- PLIC_BASE_GET();
-
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
*pending = !!(*pending & SEND_IPI_TO_HART(hart));
#include <command.h>
#include <hang.h>
+#ifndef CONFIG_SYSRESET
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
printf("resetting ...\n");
return 0;
}
+#endif
#include <asm/encoding.h>
#include <asm/sbi.h>
+int riscv_init_ipi(void)
+{
+ return 0;
+}
+
int riscv_send_ipi(int hart)
{
ulong mask;
DECLARE_GLOBAL_DATA_PTR;
-#define CLINT_BASE_GET(void) \
- do { \
- long *ret; \
- \
- if (!gd->arch.clint) { \
- ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \
- if (IS_ERR(ret)) \
- return PTR_ERR(ret); \
- gd->arch.clint = ret; \
- } \
- } while (0)
-
int riscv_get_time(u64 *time)
{
- CLINT_BASE_GET();
-
*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
return 0;
int riscv_set_timecmp(int hart, u64 cmp)
{
- CLINT_BASE_GET();
-
writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
return 0;
}
-int riscv_send_ipi(int hart)
+int riscv_init_ipi(void)
{
- CLINT_BASE_GET();
+ long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
+
+ if (IS_ERR(ret))
+ return PTR_ERR(ret);
+ gd->arch.clint = ret;
+
+ return 0;
+}
+int riscv_send_ipi(int hart)
+{
writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
int riscv_clear_ipi(int hart)
{
- CLINT_BASE_GET();
-
writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
int riscv_get_ipi(int hart, int *pending)
{
- CLINT_BASE_GET();
-
*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
DECLARE_GLOBAL_DATA_PTR;
-/**
- * riscv_send_ipi() - Send inter-processor interrupt (IPI)
- *
- * Platform code must provide this function.
- *
- * @hart: Hart ID of receiving hart
- * @return 0 if OK, -ve on error
- */
-extern int riscv_send_ipi(int hart);
-
-/**
- * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
- *
- * Platform code must provide this function.
- *
- * @hart: Hart ID of hart to be cleared
- * @return 0 if OK, -ve on error
- */
-extern int riscv_clear_ipi(int hart);
-
-/**
- * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
- *
- * Platform code must provide this function.
- *
- * @hart: Hart ID of hart to be checked
- * @pending: Pointer to variable with result of the check,
- * 1 if IPI is pending, 0 otherwise
- * @return 0 if OK, -ve on error
- */
-extern int riscv_get_ipi(int hart, int *pending);
-
static int send_ipi_many(struct ipi_data *ipi, int wait)
{
ofnode node, cpus;
*/
ret = riscv_clear_ipi(hart);
if (ret) {
- pr_err("Cannot clear IPI of hart %ld\n", hart);
+ pr_err("Cannot clear IPI of hart %ld (error %d)\n", hart, ret);
return;
}
int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait)
{
- int ret = 0;
- struct ipi_data ipi;
-
- ipi.addr = addr;
- ipi.arg0 = arg0;
- ipi.arg1 = arg1;
-
- ret = send_ipi_many(&ipi, wait);
+ struct ipi_data ipi = {
+ .addr = addr,
+ .arg0 = arg0,
+ .arg1 = arg1,
+ };
- return ret;
+ return send_ipi_many(&ipi, wait);
}
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
- remoteproc1 = &rproc_1;
- remoteproc2 = &rproc_2;
+ remoteproc0 = &rproc_1;
+ remoteproc1 = &rproc_2;
rtc0 = &rtc_0;
rtc1 = &rtc_1;
spi0 = "/spi@0";
hub {
compatible = "usb-hub";
usb,device-class = <9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
hub-emul {
compatible = "sandbox,usb-hub";
#address-cells = <1>;
};
};
+
+ usbstor@1 {
+ reg = <1>;
+ };
+ usbstor@3 {
+ reg = <3>;
+ };
};
};
mdio: mdio-test {
compatible = "sandbox,mdio";
};
+
+ pm-bus-test {
+ compatible = "simple-pm-bus";
+ clocks = <&clk_sandbox 4>;
+ power-domains = <&pwrdom 1>;
+ };
+
+ resetc2: syscon-reset {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&syscon0>;
+ offset = <1>;
+ mask = <0x27FFFFFF>;
+ assert-high = <0>;
+ };
+
+ syscon-reset-test {
+ compatible = "sandbox,misc_sandbox";
+ resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
+ reset-names = "valid", "no_mask", "out_of_range";
+ };
};
#include "sandbox_pmic.dtsi"
SANDBOX_CLK_ID_I2C,
SANDBOX_CLK_ID_UART1,
SANDBOX_CLK_ID_UART2,
+ SANDBOX_CLK_ID_BUS,
SANDBOX_CLK_ID_COUNT,
};
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := sh4-linux-
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000
ifeq ($(CPU),sh2)
LDFLAGS_STANDALONE += -EB
# Copyright 2019 Google LLC
obj-$(CONFIG_SPL_BUILD) += cpu_spl.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += cpu_common.o
obj-y += punit.o
obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
obj-y += fsp_m.o
endif
endif
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-CROSS_COMPILE ?= i386-linux-
-
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START)
LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC)
*/
static inline int atomic_read(const atomic_t *v)
{
- return ACCESS_ONCE((v)->counter);
+ return READ_ONCE((v)->counter);
}
/**
obj-y += interrupts.o
obj-y += lpc-uclass.o
obj-y += mpspec.o
-obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
obj-y += northbridge-uclass.o
obj-$(CONFIG_I8259_PIC) += i8259.o
obj-$(CONFIG_I8254_TIMER) += i8254.o
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
endif
obj-$(CONFIG_USE_HOB) += hob.o
+ifndef CONFIG_TPL_BUILD
+obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
obj-$(CONFIG_HAVE_FSP) += fsp/
obj-$(CONFIG_FSP_VERSION1) += fsp1/
obj-$(CONFIG_FSP_VERSION2) += fsp2/
+endif
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TPL_BUILD
* For IGD, it seems to be always on BAR2.
*/
vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
+ gd->fb_base = vesa->phys_base_ptr;
ret = vbe_setup_video_priv(vesa, uc_priv, plat);
if (ret)
mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
mtrr_commit(true);
- printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
- vesa->bits_per_pixel);
+ printf("%dx%dx%d @ %x\n", uc_priv->xsize, uc_priv->ysize,
+ vesa->bits_per_pixel, vesa->phys_base_ptr);
return 0;
# (C) Copyright 2007 - 2013 Tensilica, Inc.
# (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
-CROSS_COMPILE ?= xtensa-linux-
PLATFORM_CPPFLAGS += -D__XTENSA__ -mlongcalls -mforce-no-pic \
-ffunction-sections -fdata-sections
JUNO_RESET_STATUS_PHY | \
JUNO_RESET_STATUS_RC)
-void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
- unsigned long trsl_addr, int window_size,
- int trsl_param)
+static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
+ unsigned long trsl_addr, int window_size,
+ int trsl_param)
{
/* X3PCI_ATR_SRC_ADDR_LOW:
- bit 0: enable entry,
((u64)1) << window_size, trsl_param);
}
-void xr3pci_setup_atr(void)
+static void xr3pci_setup_atr(void)
{
/* setup PCIe to CPU address translation tables */
unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
}
-void xr3pci_init(void)
+static void xr3pci_init(void)
{
u32 val;
int timeout = 200;
void vexpress64_pcie_init(void)
{
+ /* Initialise and configure the PCIe host bridge. */
xr3pci_init();
+
+ /* Register the now ECAM complaint PCIe host controller with U-Boot. */
+ pci_init();
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
+#ifndef CONFIG_DM_ETH
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
+#endif
return rc;
}
-setenv stdout serial,vga
+setenv stdout serial,vidconsole
echo "check U-Boot" ;
setenv offset 0x400
if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
return 0;
}
+int ipu_displays_init(void)
+{
+ return board_video_skip();
+}
+
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
.platdata = &serial_pdata,
};
+static const struct davinci_mmc_plat mmc_platdata = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .cfg = {
+ .f_min = 200000,
+ .f_max = 25000000,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .host_caps = MMC_MODE_4BIT,
+ .b_max = DAVINCI_MAX_BLOCKS,
+ .name = "da830-mmc",
+ },
+};
U_BOOT_DEVICE(omapl138_mmc) = {
.name = "davinci_mmc",
+ .platdata = &mmc_platdata,
};
void spl_board_init(void)
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
-ifdef CONFIG_SPL_BUILD
-obj-y += ../../st/stm32mp1/spl.o
-endif
-
-obj-y += ../../st/stm32mp1/board.o board.o
+obj-y += ../../st/common/stpmic1.o board.o
obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += ../../st/common/stm32mp_mtdparts.o
obj-$(CONFIG_SET_DFU_ALT_INFO) += ../../st/common/stm32mp_dfu.o
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <watchdog.h>
+#include "../../st/common/stpmic1.h"
/* SYSCFG registers */
#define SYSCFG_BOOTR 0x00
static u8 brdcode __section("data");
static u8 ddr3code __section("data");
static u8 somcode __section("data");
+static u32 opp_voltage_mv __section(".data");
static void board_get_coding_straps(void)
{
return -EINVAL;
}
+void board_vddcore_init(u32 voltage_mv)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ opp_voltage_mv = voltage_mv;
+}
+
int board_early_init_f(void)
{
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ stpmic1_init(opp_voltage_mv);
board_get_coding_straps();
return 0;
/* board dependent setup after realloc */
int board_init(void)
{
- struct udevice *dev;
-
/* address of boot parameters */
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
- /* probe all PINCTRL for hog */
- for (uclass_first_device(UCLASS_PINCTRL, &dev);
- dev;
- uclass_next_device(&dev)) {
- pr_debug("probe pincontrol = %s\n", dev->name);
- }
+ if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
+ gpio_hog_probe_all();
board_key_check();
PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
#else
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif
/*
+++ /dev/null
-if TARGET_B4860QDS || TARGET_B4420QDS
-
-config SYS_BOARD
- default "b4860qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "B4860QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-B4860QDS BOARD
-M: Ashish Kumar <ashish.kumar@nxp.com>
-S: Maintained
-F: board/freescale/b4860qds/
-F: include/configs/B4860QDS.h
-F: configs/B4420QDS_defconfig
-F: configs/B4420QDS_NAND_defconfig
-F: configs/B4420QDS_SPIFLASH_defconfig
-F: configs/B4860QDS_defconfig
-F: configs/B4860QDS_NAND_defconfig
-F: configs/B4860QDS_SPIFLASH_defconfig
-F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
-
-B4860QDS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/B4860QDS_SECURE_BOOT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += b4860qds.o
-obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o
-obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "../common/idt8t49n222a_serdes_clk.h"
-#include "../common/zm7300.h"
-#include "b4860qds.h"
-#include "b4860qds_qixis.h"
-#include "b4860qds_crossbar_con.h"
-
-#define CLK_MUX_SEL_MASK 0x4
-#define ETH_PHY_CLK_OUT 0x4
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *const freq[] = {"100", "125", "156.25", "161.13",
- "122.88", "122.88", "122.88"};
- int clock;
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw >= 0x8 && sw <= 0xE)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n" at the end */
- printf(" on %s", qixis_read_time(buf));
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference Clocks: ");
- sw = QIXIS_READ(brdcfg[2]);
- clock = (sw >> 5) & 7;
- printf("Bank1=%sMHz ", freq[clock]);
- sw = QIXIS_READ(brdcfg[4]);
- clock = (sw >> 6) & 3;
- printf("Bank2=%sMHz\n", freq[clock]);
-
- return 0;
-}
-
-int select_i2c_ch_pca(u8 ch)
-{
- int ret;
-
- /* Selecting proper channel via PCA*/
- ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
- if (ret) {
- printf("PCA: failed to select proper channel.\n");
- return ret;
- }
-
- return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
-#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
-
-static inline int read_voltage(void)
-{
- int i, ret, voltage_read = 0;
- u16 vol_mon;
-
- for (i = 0; i < NUM_READINGS; i++) {
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
- if (ret) {
- printf("VID: failed to read core voltage\n");
- return ret;
- }
- if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
- printf("VID: Core voltage sensor error\n");
- return -1;
- }
- debug("VID: bus voltage reads 0x%04x\n", vol_mon);
- /* LSB = 4mv */
- voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
- udelay(WAIT_FOR_ADC);
- }
- /* calculate the average */
- voltage_read /= NUM_READINGS;
-
- return voltage_read;
-}
-
-static int adjust_vdd(ulong vdd_override)
-{
- int re_enable = disable_interrupts();
- ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 fusesr;
- u8 vid;
- int vdd_target, vdd_last;
- int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
- int ret;
- unsigned int orig_i2c_speed;
- unsigned long vdd_string_override;
- char *vdd_string;
- static const uint16_t vdd[32] = {
- 0, /* unused */
- 9875, /* 0.9875V */
- 9750,
- 9625,
- 9500,
- 9375,
- 9250,
- 9125,
- 9000,
- 8875,
- 8750,
- 8625,
- 8500,
- 8375,
- 8250,
- 8125,
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 10375,
- 10500,
- 10625,
- 10750,
- 10875,
- 11000,
- 0, /* reserved */
- };
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
-
- ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- printf("VID: I2c failed to switch channel\n");
- ret = -1;
- goto exit;
- }
-
- /* get the voltage ID from fuse status register */
- fusesr = in_be32(&gur->dcfg_fusesr);
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_VID_MASK;
- if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
- }
- vdd_target = vdd[vid];
- debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
- vid, vdd_target/10);
-
- /* check override variable for overriding VDD */
- vdd_string = env_get("b4qds_vdd_mv");
- if (vdd_override == 0 && vdd_string &&
- !strict_strtoul(vdd_string, 10, &vdd_string_override))
- vdd_override = vdd_string_override;
- if (vdd_override >= 819 && vdd_override <= 1212) {
- vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
- } else if (vdd_override != 0) {
- printf("Invalid value.\n");
- }
-
- if (vdd_target == 0) {
- printf("VID: VID not used\n");
- ret = 0;
- goto exit;
- }
-
- /*
- * Read voltage monitor to check real voltage.
- * Voltage monitor LSB is 4mv.
- */
- vdd_last = read_voltage();
- if (vdd_last < 0) {
- printf("VID: abort VID adjustment\n");
- ret = -1;
- goto exit;
- }
-
- debug("VID: Core voltage is at %d mV\n", vdd_last);
- ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
- if (ret) {
- printf("VID: I2c failed to switch channel to DPM\n");
- ret = -1;
- goto exit;
- }
-
- /* Round up to the value of step of Voltage regulator */
- voltage = roundup(vdd_target, ZM_STEP);
- debug("VID: rounded up voltage = %d\n", voltage);
-
- /* lower the speed to 100kHz to access ZM7300 device */
- debug("VID: Setting bus speed to 100KHz if not already set\n");
- orig_i2c_speed = i2c_get_bus_speed();
- if (orig_i2c_speed != 100000)
- i2c_set_bus_speed(100000);
-
- /* Read the existing level on board, if equal to requsted one,
- no need to re-set */
- existing_voltage = zm_read_voltage();
-
- /* allowing the voltage difference of one step 0.0125V acceptable */
- if ((existing_voltage >= voltage) &&
- (existing_voltage < (voltage + ZM_STEP))) {
- debug("VID: voltage already set as requested,returning\n");
- ret = existing_voltage;
- goto out;
- }
- debug("VID: Changing voltage for board from %dmV to %dmV\n",
- existing_voltage/10, voltage/10);
-
- if (zm_disable_wp() < 0) {
- ret = -1;
- goto out;
- }
- /* Change Voltage: the change is done through all the steps in the
- way, to avoid reset to the board due to power good signal fail
- in big voltage change gap jump.
- */
- if (existing_voltage > voltage) {
- temp_voltage = existing_voltage - ZM_STEP;
- while (temp_voltage >= voltage) {
- ret = zm_write_voltage(temp_voltage);
- if (ret == temp_voltage) {
- temp_voltage -= ZM_STEP;
- } else {
- /* ZM7300 device failed to set
- * the voltage */
- printf
- ("VID:Stepping down vol failed:%dmV\n",
- temp_voltage/10);
- ret = -1;
- goto out;
- }
- }
- } else {
- temp_voltage = existing_voltage + ZM_STEP;
- while (temp_voltage < (voltage + ZM_STEP)) {
- ret = zm_write_voltage(temp_voltage);
- if (ret == temp_voltage) {
- temp_voltage += ZM_STEP;
- } else {
- /* ZM7300 device failed to set
- * the voltage */
- printf
- ("VID:Stepping up vol failed:%dmV\n",
- temp_voltage/10);
- ret = -1;
- goto out;
- }
- }
- }
-
- if (zm_enable_wp() < 0)
- ret = -1;
-
- /* restore the speed to 400kHz */
-out: debug("VID: Restore the I2C bus speed to %dKHz\n",
- orig_i2c_speed/1000);
- i2c_set_bus_speed(orig_i2c_speed);
- if (ret < 0)
- goto exit;
-
- ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- printf("VID: I2c failed to switch channel\n");
- ret = -1;
- goto exit;
- }
- vdd_last = read_voltage();
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- if (vdd_last > 0)
- printf("VID: Core voltage %d mV\n", vdd_last);
- else
- ret = -1;
-
-exit:
- if (re_enable)
- enable_interrupts();
- return ret;
-}
-
-int configure_vsc3316_3308(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned int num_vsc16_con, num_vsc08_con;
- u32 serdes1_prtcl, serdes2_prtcl;
- int ret;
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
-
- serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- if (!serdes1_prtcl) {
- printf("SERDES1 is not enabled\n");
- return 0;
- }
- serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- if (!serdes2_prtcl) {
- printf("SERDES2 is not enabled\n");
- return 0;
- }
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
- switch (serdes1_prtcl) {
- case 0x29:
- case 0x2a:
- case 0x2C:
- case 0x2D:
- case 0x2E:
- /*
- * Configuration:
- * SERDES: 1
- * Lanes: A,B: SGMII
- * Lanes: C,D,E,F,G,H: CPRI
- */
- debug("Configuring crossbar to use onboard SGMII PHYs:"
- "srds_prctl:%x\n", serdes1_prtcl);
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_4sfp_sgmii_12_56,
- num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_4sfp_sgmii_12_56,
- num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
-
- case 0x01:
- case 0x02:
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x07:
- case 0x08:
- case 0x09:
- case 0x0A:
- case 0x0B:
- case 0x0C:
- case 0x2F:
- case 0x30:
- case 0x32:
- case 0x33:
- case 0x34:
- case 0x39:
- case 0x3A:
- case 0x3C:
- case 0x3D:
- case 0x5C:
- case 0x5D:
- /*
- * Configuration:
- * SERDES: 1
- * Lanes: A,B: AURORA
- * Lanes: C,d: SGMII
- * Lanes: E,F,G,H: CPRI
- */
- debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
- " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_sfp_sgmii_aurora,
- num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_sfp_sgmii_aurora,
- num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
-
-#ifdef CONFIG_ARCH_B4420
- case 0x17:
- case 0x18:
- /*
- * Configuration:
- * SERDES: 1
- * Lanes: A,B,C,D: SGMII
- * Lanes: E,F,G,H: CPRI
- */
- debug("Configuring crossbar to use onboard SGMII PHYs:"
- "srds_prctl:%x\n", serdes1_prtcl);
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_sgmii_lane_cd, num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_sgmii_lane_cd, num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
-#endif
-
- case 0x3E:
- case 0x0D:
- case 0x0E:
- case 0x12:
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_sfp, num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_sfp, num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
- default:
- printf("WARNING:VSC crossbars programming not supported for:%x"
- " SerDes1 Protocol.\n", serdes1_prtcl);
- return -1;
- }
-
- num_vsc08_con = NUM_CON_VSC3308;
- /* Configure VSC3308 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3308);
- switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
- case 0x9d:
-#endif
- case 0x9E:
- case 0x9A:
- case 0x98:
- case 0x48:
- case 0x49:
- case 0x4E:
- case 0x79:
- case 0x7A:
- if (!ret) {
- ret = vsc3308_config(VSC3308_TX_ADDRESS,
- vsc08_tx_amc, num_vsc08_con);
- if (ret)
- return ret;
- ret = vsc3308_config(VSC3308_RX_ADDRESS,
- vsc08_rx_amc, num_vsc08_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
- case 0x80:
- case 0x81:
- case 0x82:
- case 0x83:
- case 0x84:
- case 0x85:
- case 0x86:
- case 0x87:
- case 0x88:
- case 0x89:
- case 0x8a:
- case 0x8b:
- case 0x8c:
- case 0x8d:
- case 0x8e:
- case 0xb1:
- case 0xb2:
- if (!ret) {
- /*
- * Extract hwconfig from environment since environment
- * is not setup properly yet
- */
- env_get_f("hwconfig", buffer, sizeof(buffer));
- buf = buffer;
-
- if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
- "sfp_amc", "sfp", buf)) {
-#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
- /* change default VSC3308 for XFI erratum */
- ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
- vsc08_tx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-
- ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
- vsc08_rx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-#else
- ret = vsc3308_config(VSC3308_TX_ADDRESS,
- vsc08_tx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-
- ret = vsc3308_config(VSC3308_RX_ADDRESS,
- vsc08_rx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-#endif
- } else {
- ret = vsc3308_config(VSC3308_TX_ADDRESS,
- vsc08_tx_amc, num_vsc08_con);
- if (ret)
- return ret;
-
- ret = vsc3308_config(VSC3308_RX_ADDRESS,
- vsc08_rx_amc, num_vsc08_con);
- if (ret)
- return ret;
- }
-
- } else {
- return ret;
- }
- break;
- default:
- printf("WARNING:VSC crossbars programming not supported for: %x"
- " SerDes2 Protocol.\n", serdes2_prtcl);
- return -1;
- }
-
- return 0;
-}
-
-static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
-{
- u32 rst_err;
-
- /* Steps For SerDes PLLs reset and reconfiguration
- * or PLL power-up procedure
- */
- debug("CALIBRATE PLL:%d\n", pll_num);
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- SRDS_RSTCTL_SDRST_B);
- udelay(10);
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
- udelay(10);
- setbits_be32(&srds_regs->bank[pll_num].rstctl,
- SRDS_RSTCTL_RST);
- setbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
-
- udelay(20);
-
- /* Check whether PLL has been locked or not */
- rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
- SRDS_RSTCTL_RSTERR;
- rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
- debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
- if (rst_err)
- return rst_err;
-
- return rst_err;
-}
-
-static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
-{
- int ret = 0;
- u32 fcap, dcbias, bcap, pllcr1, pllcr0;
-
- if (calibrate_pll(srds_regs, pll_num)) {
- /* STEP 1 */
- /* Read fcap, dcbias and bcap value */
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_FCAP;
- fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
- bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_BCAP_EN;
- bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
- setbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_DCBIAS;
- dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
- debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
- bcap, fcap, dcbias);
- if (fcap == 0 && bcap == 1) {
- /* Step 3 */
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_EN);
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_OVD);
- if (calibrate_pll(srds_regs, pll_num)) {
- /*save the fcap, dcbias and bcap values*/
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
- & SRDS_PLLSR2_FCAP;
- fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
- bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
- & SRDS_PLLSR2_BCAP_EN;
- bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
- setbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- dcbias = in_be32
- (&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_DCBIAS;
- dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
-
- /* Step 4*/
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BYP_CAL);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_EN);
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_OVD);
- /* change the fcap and dcbias to the saved
- * values from Step 3 */
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_PLL_FCAP);
- pllcr1 = (in_be32
- (&srds_regs->bank[pll_num].pllcr1)|
- (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr1,
- pllcr1);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OVRD);
- pllcr0 = (in_be32
- (&srds_regs->bank[pll_num].pllcr0)|
- (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr0,
- pllcr0);
- ret = calibrate_pll(srds_regs, pll_num);
- if (ret)
- return ret;
- } else {
- goto out;
- }
- } else { /* Step 5 */
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- udelay(10);
- /* Change the fcap, dcbias, and bcap to the
- * values from Step 1 */
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BYP_CAL);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_PLL_FCAP);
- pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
- (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr1,
- pllcr1);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OVRD);
- pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
- (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr0,
- pllcr0);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_EN);
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_OVD);
- ret = calibrate_pll(srds_regs, pll_num);
- if (ret)
- return ret;
- }
- }
-out:
- return 0;
-}
-
-static int check_serdes_pll_locks(void)
-{
- serdes_corenet_t *srds1_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- serdes_corenet_t *srds2_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
- int i, ret1, ret2;
-
- debug("\nSerDes1 Lock check\n");
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- ret1 = check_pll_locks(srds1_regs, i);
- if (ret1) {
- printf("SerDes1, PLL:%d didnt lock\n", i);
- return ret1;
- }
- }
- debug("\nSerDes2 Lock check\n");
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- ret2 = check_pll_locks(srds2_regs, i);
- if (ret2) {
- printf("SerDes2, PLL:%d didnt lock\n", i);
- return ret2;
- }
- }
-
- return 0;
-}
-
-int config_serdes1_refclks(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 serdes1_prtcl, lane;
- unsigned int flag_sgmii_aurora_prtcl = 0;
- int i;
- int ret = 0;
-
- serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- if (!serdes1_prtcl) {
- printf("SERDES1 is not enabled\n");
- return -1;
- }
- serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
- /* To prevent generation of reset request from SerDes
- * while changing the refclks, By setting SRDS_RST_MSK bit,
- * SerDes reset event cannot cause a reset request
- */
- setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
- /* Reconfigure IDT idt8t49n222a device for CPRI to work
- * For this SerDes1's Refclk1 and refclk2 need to be set
- * to 122.88MHz
- */
- switch (serdes1_prtcl) {
- case 0x29:
- case 0x2A:
- case 0x2C:
- case 0x2D:
- case 0x2E:
- case 0x01:
- case 0x02:
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x07:
- case 0x08:
- case 0x09:
- case 0x0A:
- case 0x0B:
- case 0x0C:
- case 0x2F:
- case 0x30:
- case 0x32:
- case 0x33:
- case 0x34:
- case 0x39:
- case 0x3A:
- case 0x3C:
- case 0x3D:
- case 0x5C:
- case 0x5D:
- debug("Configuring idt8t49n222a for CPRI SerDes clks:"
- " for srds_prctl:%x\n", serdes1_prtcl);
- ret = select_i2c_ch_pca(I2C_CH_IDT);
- if (!ret) {
- ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
- SERDES_REFCLK_122_88,
- SERDES_REFCLK_122_88, 0);
- if (ret) {
- printf("IDT8T49N222A configuration failed.\n");
- goto out;
- } else
- debug("IDT8T49N222A configured.\n");
- } else {
- goto out;
- }
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- /* Change SerDes1's Refclk1 to 125MHz for on board
- * SGMIIs or Aurora to work
- */
- for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes_get_prtcl
- (0, serdes1_prtcl, lane);
- switch (lane_prtcl) {
- case SGMII_FM1_DTSEC1:
- case SGMII_FM1_DTSEC2:
- case SGMII_FM1_DTSEC3:
- case SGMII_FM1_DTSEC4:
- case SGMII_FM1_DTSEC5:
- case SGMII_FM1_DTSEC6:
- case AURORA:
- flag_sgmii_aurora_prtcl++;
- break;
- default:
- break;
- }
- }
-
- if (flag_sgmii_aurora_prtcl)
- QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
-
- /* Steps For SerDes PLLs reset and reconfiguration after
- * changing SerDes's refclks
- */
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- debug("For PLL%d reset and reconfiguration after"
- " changing refclks\n", i+1);
- clrbits_be32(&srds_regs->bank[i].rstctl,
- SRDS_RSTCTL_SDRST_B);
- udelay(10);
- clrbits_be32(&srds_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
- udelay(10);
- setbits_be32(&srds_regs->bank[i].rstctl,
- SRDS_RSTCTL_RST);
- setbits_be32(&srds_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- }
- break;
- default:
- printf("WARNING:IDT8T49N222A configuration not"
- " supported for:%x SerDes1 Protocol.\n",
- serdes1_prtcl);
- }
-
-out:
- /* Clearing SRDS_RST_MSK bit as now
- * SerDes reset event can cause a reset request
- */
- clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
- return ret;
-}
-
-int config_serdes2_refclks(void)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *srds2_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
- u32 serdes2_prtcl;
- int ret = 0;
- int i;
-
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- if (!serdes2_prtcl) {
- debug("SERDES2 is not enabled\n");
- return -ENODEV;
- }
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
- /* To prevent generation of reset request from SerDes
- * while changing the refclks, By setting SRDS_RST_MSK bit,
- * SerDes reset event cannot cause a reset request
- */
- setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
- /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
- * For this SerDes2's Refclk1 need to be set to 100MHz
- */
- switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
- case 0x9d:
-#endif
- case 0x9E:
- case 0x9A:
- /* fallthrough */
- case 0xb1:
- case 0xb2:
- debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
- serdes2_prtcl);
- ret = select_i2c_ch_pca(I2C_CH_IDT);
- if (!ret) {
- ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
- SERDES_REFCLK_100,
- SERDES_REFCLK_156_25, 0);
- if (ret) {
- printf("IDT8T49N222A configuration failed.\n");
- goto out;
- } else
- debug("IDT8T49N222A configured.\n");
- } else {
- goto out;
- }
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- /* Steps For SerDes PLLs reset and reconfiguration after
- * changing SerDes's refclks
- */
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- clrbits_be32(&srds2_regs->bank[i].rstctl,
- SRDS_RSTCTL_SDRST_B);
- udelay(10);
- clrbits_be32(&srds2_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
- udelay(10);
- setbits_be32(&srds2_regs->bank[i].rstctl,
- SRDS_RSTCTL_RST);
- setbits_be32(&srds2_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
-
- udelay(10);
- }
- break;
- default:
- printf("IDT configuration not supported for:%x S2 Protocol.\n",
- serdes2_prtcl);
- }
-
-out:
- /* Clearing SRDS_RST_MSK bit as now
- * SerDes reset event can cause a reset request
- */
- clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
- return ret;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
- int ret;
- u32 svr = SVR_SOC_VER(get_svr());
-
- /* Create law for MAPLE only for personalities having MAPLE */
- if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
- (svr == SVR_B4420) || (svr == SVR_B4220)) {
- set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
- LAW_TRGT_IF_MAPLE);
- }
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0) < 0)
- printf("Warning: Adjusting core voltage failed\n");
-
- /* SerDes1 refclks need to be set again, as default clks
- * are not suitable for CPRI and onboard SGMIIs to work
- * simultaneously.
- * This function will set SerDes1's Refclk1 and refclk2
- * as per SerDes1 protocols
- */
- if (config_serdes1_refclks())
- printf("SerDes1 Refclks couldn't set properly.\n");
- else
- printf("SerDes1 Refclks have been set.\n");
-
- /* SerDes2 refclks need to be set again, as default clks
- * are not suitable for PCIe SATA to work
- * This function will set SerDes2's Refclk1 and refclk2
- * for SerDes2 protocols having PCIe in them
- * for PCIe SATA to work
- */
- ret = config_serdes2_refclks();
- if (!ret)
- printf("SerDes2 Refclks have been set.\n");
- else if (ret == -ENODEV)
- printf("SerDes disable, Refclks couldn't change.\n");
- else
- printf("SerDes2 Refclk reconfiguring failed.\n");
-
-#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
- defined(CONFIG_SYS_FSL_ERRATUM_A006475)
- /* Rechecking the SerDes locks after all SerDes configurations
- * are done, As SerDes PLLs may not lock reliably at 5 G VCO
- * and at cold temperatures.
- * Following sequence ensure the proper locking of SerDes PLLs.
- */
- if (SVR_MAJ(get_svr()) == 1) {
- if (check_serdes_pll_locks())
- printf("SerDes plls still not locked properly.\n");
- else
- printf("SerDes plls have been locked well.\n");
- }
-#endif
-
- /* Configure VSC3316 and VSC3308 crossbar switches */
- if (configure_vsc3316_3308())
- printf("VSC:failed to configure VSC3316/3308.\n");
- else
- printf("VSC:VSC3316/3308 successfully configured.\n");
-
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((sysclk_conf & 0x0C) >> 2) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (ddrclk_conf & 0x03) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-static int serdes_refclock(u8 sw, u8 sdclk)
-{
- unsigned int clock;
- int ret = -1;
- u8 brdcfg4;
-
- if (sdclk == 1) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
- return SRDS_PLLCR0_RFCK_SEL_125;
- else
- clock = (sw >> 5) & 7;
- } else
- clock = (sw >> 6) & 3;
-
- switch (clock) {
- case 0:
- ret = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- ret = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 2:
- ret = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- case 3:
- ret = SRDS_PLLCR0_RFCK_SEL_161_13;
- break;
- case 4:
- case 5:
- case 6:
- ret = SRDS_PLLCR0_RFCK_SEL_122_88;
- break;
- default:
- ret = -1;
- break;
- }
-
- return ret;
-}
-
-#define NUM_SRDS_BANKS 2
-
-int misc_init_r(void)
-{
- u8 sw;
- serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 actual[NUM_SRDS_BANKS];
- unsigned int i;
- int clock;
-
- sw = QIXIS_READ(brdcfg[2]);
- clock = serdes_refclock(sw, 1);
- if (clock >= 0)
- actual[0] = clock;
- else
- printf("Warning: SDREFCLK1 switch setting is unsupported\n");
-
- sw = QIXIS_READ(brdcfg[4]);
- clock = serdes_refclock(sw, 2);
- if (clock >= 0)
- actual[1] = clock;
- else
- printf("Warning: SDREFCLK2 switch setting unsupported\n");
-
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 pllcr0 = srds_regs->bank[i].pllcr0;
- u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES bank %u expects reference clock"
- " %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
- fdt_fixup_fman_ethernet(blob);
-#endif
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-/*
- * Dump board switch settings.
- * The bits that cannot be read/sampled via some FPGA or some
- * registers, they will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
- int i;
- u8 sw[5];
-
- /*
- * Any bit with 1 means that bit cannot be reverse engineered.
- * It will be displayed as _ in binary format.
- */
- static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
- char buf[10];
- u8 brdcfg[16], dutcfg[16];
-
- for (i = 0; i < 16; i++) {
- brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
- dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
- }
-
- sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
- (brdcfg[9] & 0x08);
- sw[1] = ((dutcfg[1] & 0x01) << 7) | \
- ((dutcfg[2] & 0x07) << 4) | \
- ((dutcfg[6] & 0x10) >> 1) | \
- ((dutcfg[6] & 0x80) >> 5) | \
- ((dutcfg[1] & 0x40) >> 5) | \
- (dutcfg[6] & 0x01);
- sw[2] = dutcfg[0];
- sw[3] = 0;
- sw[4] = ((brdcfg[1] & 0x30) << 2) | \
- ((brdcfg[1] & 0xc0) >> 2) | \
- (brdcfg[1] & 0x0f);
-
- puts("DIP switch settings:\n");
- for (i = 0; i < 5; i++) {
- printf("SW%d = 0b%s (0x%02x)\n",
- i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CROSSBAR_CONNECTIONS_H__
-#define __CROSSBAR_CONNECTIONS_H__
-
-#define NUM_CON_VSC3316 8
-#define NUM_CON_VSC3308 4
-
-static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
- {5, 11}, {4, 5}, {2, 6}, {12, 9} };
-
-static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
- {7, 8}, {9, 0}, {2, 14}, {12, 15},
- {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
- {7, 8}, {9, 0}, {5, 14}, {4, 15},
- {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
- {7, 8}, {9, 0}, {5, 14},
- {4, 15}, {2, 12}, {12, 13} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
- {11, 11}, {5, 10}, {6, 3}, {9, 12} };
-
-static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
- {7, 8}, {1, 9}, {14, 3}, {15, 12},
- {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
- {7, 8}, {1, 9}, {14, 11}, {15, 10},
- {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
- {7, 8}, {1, 9}, {14, 11},
- {15, 10}, {13, 3}, {12, 12} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
-
-static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
-
-static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
-
-static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __B4860QDS_QIXIS_H__
-#define __B4860QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for B4860QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* CLK */
-#define QIXIS_CLK_66 0x0
-#define QIXIS_CLK_100 0x1
-#define QIXIS_CLK_125 0x2
-#define QIXIS_CLK_133 0x3
-
-#define QIXIS_SRDS1CLK_122 0x5a
-#define QIXIS_SRDS1CLK_125 0x5e
-
-/* SGMII */
-#define PHY_BASE_ADDR 0x18
-#define PORT_NUM 0x04
-#define REGNUM 0x00
-#endif
+++ /dev/null
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
+++ /dev/null
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x2A_0x98
-140e0018 0f001218 00000000 00000000
-54980000 9000a000 e8104000 a9000000
-01000000 00000000 00000000 0001b1f8
-00000000 14000020 00000000 00000011
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <fsl_ddr.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 2147483648u,
- .capacity = 4294967296u,
- .primary_sdram_width = 64,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 1,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2, /* ECC */
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1071,
- .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
- .taa_ps = 13910,
- .twr_ps = 15000,
- .trcd_ps = 13910,
- .trrd_ps = 6000,
- .trp_ps = 13910,
- .tras_ps = 34000,
- .trc_ps = 48910,
- .trfc_ps = 260000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 35000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "RAW timing DDR";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
- */
- {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
- {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
- {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
- {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
- {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
- {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x3e;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
- unsigned int dbw_cap_adj[])
-{
- int i, j;
- unsigned long long total_mem, current_mem_base, total_ctlr_mem;
- unsigned long long rank_density, ctlr_density = 0;
-
- current_mem_base = 0ull;
- total_mem = 0;
- /*
- * This board has soldered DDR chips. DDRC1 has two rank.
- * DDRC2 has only one rank.
- * Assigning DDRC2 to lower address and DDRC1 to higher address.
- */
- if (pinfo->memctl_opts[0].memctl_interleaving) {
- rank_density = pinfo->dimm_params[0][0].rank_density >>
- dbw_cap_adj[0];
- ctlr_density = rank_density;
-
- debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
- rank_density, ctlr_density);
- for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
- switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
- case FSL_DDR_CACHE_LINE_INTERLEAVING:
- case FSL_DDR_PAGE_INTERLEAVING:
- case FSL_DDR_BANK_INTERLEAVING:
- case FSL_DDR_SUPERBANK_INTERLEAVING:
- total_ctlr_mem = 2 * ctlr_density;
- break;
- default:
- panic("Unknown interleaving mode");
- }
- pinfo->common_timing_params[i].base_address =
- current_mem_base;
- pinfo->common_timing_params[i].total_mem =
- total_ctlr_mem;
- total_mem = current_mem_base + total_ctlr_mem;
- debug("ctrl %d base 0x%llx\n", i, current_mem_base);
- debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
- }
- } else {
- /*
- * Simple linear assignment if memory
- * controllers are not interleaved.
- */
- for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
- total_ctlr_mem = 0;
- pinfo->common_timing_params[i].base_address =
- current_mem_base;
- for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
- /* Compute DIMM base addresses. */
- unsigned long long cap =
- pinfo->dimm_params[i][j].capacity;
- pinfo->dimm_params[i][j].base_address =
- current_mem_base;
- debug("ctrl %d dimm %d base 0x%llx\n",
- i, j, current_mem_base);
- current_mem_base += cap;
- total_ctlr_mem += cap;
- }
- debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
- pinfo->common_timing_params[i].total_mem =
- total_ctlr_mem;
- total_mem += total_ctlr_mem;
- }
- }
- debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
-
- return total_mem;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Author: Sandeep Kumar Singh <sandeep@freescale.com>
- */
-
-/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
-
-/*
- * This file handles the board muxing between the Fman Ethernet MACs and
- * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
- * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
- * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
- * one Fman device on B4860. The SERDES configuration is used to determine
- * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
- * to which PHYs. So for a given Fman MAC, there is one and only PHY it
- * connects to. MACs cannot be routed to PHYs dynamically. This configuration
- * is done at boot time by reading SERDES protocol from RCW.
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#include "../common/ngpixis.h"
-#include "../common/fman.h"
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-#define EMI_NONE 0xFFFFFFFF
-
-#ifdef CONFIG_FMAN_ENET
-
-/*
- * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
- * lane at index is mapped to slot number n. A value of '0' will mean
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 1, 1, 1, 1,
- 0, 0, 0, 0
-};
-
-/*
- * This function initializes the lane_to_slot[] array. It reads RCW to check
- * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
- * lane_to_slot[] accordingly
- */
-static void initialize_lane_to_slot(void)
-{
- unsigned int serdes2_prtcl;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Initializing lane to slot: Serdes2 protocol: %x\n",
- serdes2_prtcl);
-
- switch (serdes2_prtcl) {
- case 0x17:
- case 0x18:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: SGMII
- * Lanes: E,F: Aur
- * Lanes: G,H: SRIO
- */
- case 0x91:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B: SGMII
- * Lanes: C,D: SRIO2
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x93:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: SGMII
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x98:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: XAUI2
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x9a:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B: PCI
- * Lanes: C,D: SGMII
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x9e:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: PCI
- * Lanes: E,F,G,H: XAUI2
- */
- case 0xb1:
- case 0xb2:
- case 0x8c:
- case 0x8d:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: PCI
- * Lanes: E,F: SGMII 3&4
- * Lanes: G,H: XFI
- */
- case 0xc2:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B: SGMII
- * Lanes: C,D: SRIO2
- * Lanes: E,F,G,H: XAUI2
- */
- lane_to_slot[12] = 2;
- lane_to_slot[13] = lane_to_slot[12];
- lane_to_slot[14] = lane_to_slot[12];
- lane_to_slot[15] = lane_to_slot[12];
- break;
-
- default:
- printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- break;
- }
- return;
-}
-
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info memac_mdio_info;
- struct memac_mdio_info tg_memac_mdio_info;
- unsigned int i;
- unsigned int serdes1_prtcl, serdes2_prtcl;
- int qsgmii;
- struct mii_dev *bus;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- if (!serdes1_prtcl) {
- printf("SERDES1 is not enabled\n");
- return 0;
- }
- serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- if (!serdes2_prtcl) {
- printf("SERDES2 is not enabled\n");
- return 0;
- }
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
- printf("Initializing Fman\n");
-
- initialize_lane_to_slot();
-
- memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
- memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fm_memac_mdio_init(bis, &memac_mdio_info);
-
- tg_memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the real 10G MDIO bus */
- fm_memac_mdio_init(bis, &tg_memac_mdio_info);
-
- /*
- * Program the two on board DTSEC PHY addresses assuming that they are
- * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
- * 6 to on board SGMII phys
- */
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-
- switch (serdes1_prtcl) {
- case 0x29:
- case 0x2a:
- /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
- debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5,
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- break;
-#ifdef CONFIG_ARCH_B4420
- case 0x17:
- case 0x18:
- /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
- debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- /* Fixing Serdes clock by programming FPGA register */
- QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- break;
-#endif
- default:
- printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
- switch (serdes2_prtcl) {
- case 0x17:
- case 0x18:
- debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1,
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
- break;
- case 0x48:
- case 0x49:
- debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1,
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
- break;
- case 0xb1:
- case 0xb2:
- case 0x8c:
- case 0x8d:
- debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
- /*
- * XFI does not need a PHY to work, but to make U-Boot
- * happy, assign a fake PHY address for a XFI port.
- */
- fm_info_set_phy_address(FM1_10GEC1, 0);
- fm_info_set_phy_address(FM1_10GEC2, 1);
- break;
- case 0x98:
- /* XAUI in Slot1 and Slot2 */
- debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC1,
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2,
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- break;
- case 0x9E:
- /* XAUI in Slot2 */
- debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2,
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- break;
- default:
- printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- break;
- }
-
- /*set PHY address for QSGMII Riser Card on slot2*/
- bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
-
- if (qsgmii) {
- switch (serdes2_prtcl) {
- case 0xb2:
- case 0x8d:
- fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- int idx = i - FM1_10GEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name
- (DEFAULT_FM_TGEC_MDIO_NAME));
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: TGEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- int phy;
- char alias[32];
- struct fixed_link f_link;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
- prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- phy = fm_info_get_phy_address(port);
-
- sprintf(alias, "phy_sgmii_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, alias);
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
- /* check if it's XFI interface for 10g */
- switch (prtcl2) {
- case 0x80:
- case 0x81:
- case 0x82:
- case 0x83:
- case 0x84:
- case 0x85:
- case 0x86:
- case 0x87:
- case 0x88:
- case 0x89:
- case 0x8a:
- case 0x8b:
- case 0x8c:
- case 0x8d:
- case 0x8e:
- case 0xb1:
- case 0xb2:
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
-
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link,
- sizeof(f_link));
- break;
- case 0x98: /* XAUI interface */
- strcpy(alias, "phy_xaui_slot1");
- fdt_status_okay_by_alias(fdt, alias);
-
- strcpy(alias, "phy_xaui_slot2");
- fdt_status_okay_by_alias(fdt, alias);
- break;
- case 0x9e: /* XAUI interface */
- case 0x9a:
- case 0x93:
- case 0x91:
- strcpy(alias, "phy_xaui_slot1");
- fdt_status_okay_by_alias(fdt, alias);
- break;
- case 0x97: /* XAUI interface */
- case 0xc3:
- strcpy(alias, "phy_xaui_slot2");
- fdt_status_okay_by_alias(fdt, alias);
- break;
- default:
- break;
- }
- }
-}
-
-/*
- * Set status to disabled for unused ethernet node
- */
-void fdt_fixup_board_enet(void *fdt)
-{
- int i;
- char alias[32];
-
- for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_NONE:
- sprintf(alias, "ethernet%u", i);
- fdt_status_disabled_by_alias(fdt, alias);
- break;
- default:
- break;
- }
- }
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((sysclk_conf & 0x0C) >> 2) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (ddrclk_conf & 0x03) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, uart_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- uart_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- uart_clk / 16 / CONFIG_BAUDRATE);
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
- env_relocate();
-#else
- /* relocate environment function pointers etc. */
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#endif
-
- i2c_init_all();
-
- puts("\n\n");
-
- dram_init();
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_boot();
-#endif
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
- /*
- * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
- * space is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_64K, 1),
-#endif
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_4K, 1),
-
- /*
- * *I*G - SRIO
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for SRIO2.
- */
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
- /* *I*G* - SRIO1 */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
- /* *I*G* - SRIO2 */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
- /*
- * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
- * fetching ucode and ENV from master
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 17, BOOKE_PAGESZ_1M, 1),
-#endif
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 17, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_BSC9131RDB
-
-config SYS_BOARD
- default "bsc9131rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "BSC9131RDB"
-
-endif
+++ /dev/null
-BSC9131RDB BOARD
-M: Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S: Maintained
-F: board/freescale/bsc9131rdb/
-F: include/configs/BSC9131RDB.h
-F: configs/BSC9131RDB_NAND_defconfig
-F: configs/BSC9131RDB_NAND_SYSCLK100_defconfig
-F: configs/BSC9131RDB_SPIFLASH_defconfig
-F: configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2011-2012 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-obj-y += bsc9131rdb.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
-- BSC9131 is integrated device that targets Femto base station market.
- It combines Power Architecture e500v2 and DSP StarCore SC3850 core
- technologies with MAPLE-B2F baseband acceleration processing elements.
-- It's MAPLE disabled personality is called 9231.
-
-The BSC9131 SoC includes the following function and features:
-. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
- L2 cache
-. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
-. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
- Processing (MAPLE-B2F)
-. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
- Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
- and CRC algorithms
-. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
- Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
- operations
-. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
- ECC, up to 400-MHz clock/800 MHz data rate
-. Dedicated security engine featuring trusted boot
-. DMA controller
-. OCNDMA with four bidirectional channels
-. Interfaces
-. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
- including IEEE 1588. v2 hardware support and virtualization (eTSEC)
-. eTSEC 1 supports RGMII/RMII
-. eTSEC 2 supports RGMII
-. High-speed USB 2.0 host and device controller with ULPI interface
-. Enhanced secure digital (SD/MMC) host controller (eSDHC)
-. Antenna interface controller (AIC), supporting three industry standard
- JESD207/three custom ADI RF interfaces (two dual port and one single port)
- and three MAXIM's MaxPHY serial interfaces
-. ADI lanes support both full duplex FDD support and half duplex TDD support
-. Universal Subscriber Identity Module (USIM) interface that facilitates
- communication to SIM cards or Eurochip pre-paid phone cards
-. TDM with one TDM port
-. Two DUART, four eSPI, and two I2C controllers
-. Integrated Flash memory controller (IFC)
-. TDM with 256 channels
-. GPIO
-. Sixteen 32-bit timers
-
-The e500 core subsystem within the Power Architecture consists of the following:
-. 32-Kbyte L1 instruction cache
-. 32-Kbyte L1 data cache
-. 256-Kbyte L2 cache/L2 memory/L2 stash
-. programmable interrupt controller (PIC)
-. Debug support
-. Timers
-
-The SC3850 core subsystem consists of the following:
-. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
-. 32 Kbyte 8-way level 1 data cache (L1 DCache)
-. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
-. Memory management unit (MMU)
-. Enhanced programmable interrupt controller (EPIC)
-. Debug and profiling unit (DPU)
-. Two 32-bit timers
-
-BSC9131RDB board Overview
--------------------------
- 1Gbyte DDR3 (on board DDR)
- 128Mbyte 2K page size NAND Flash
- 256 Kbit M24256 I2C EEPROM
- 128 Mbit SPI Flash memory
- USB-ULPI
- eTSEC1: Connected to RGMII PHY
- eTSEC2: Connected to RGMII PHY
- DUART interface: supports one UARTs up to 115200 bps for console display
- USIM connector
-
-Frequency Combinations Supported
---------------------------------
-Core MHz/CCB MHz/DDR(MT/s)
-1. 1000/500/800
-2. 800/400/667
-
-Boot Methods Supported
------------------------
-1. NAND Flash
-2. SPI Flash
-
-Default Boot Method
---------------------
-NAND boot
-
-Building U-Boot
---------------
-To build the U-Boot for BSC9131RDB:
-1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
- make BSC9131RDB_NAND
-2. NAND Flash with sysclk 100MHz(J16 on RDB open)
- make BSC9131RDB_NAND_SYSCLK100
-3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
- make BSC9131RDB_SPIFLASH
-4. SPI Flash with sysclk 100MHz(J16 on RDB open)
- make BSC9131RDB_SPIFLASH_SYSCLK100
-
-Memory map
------------
- 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
- 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
- 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
- 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
- 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
- 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
- 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
- 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
- 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
- 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
-
-DDR Memory map
----------------
- 0x0000_0000 0x36FF_FFFF Memory passed onto Linux
- 0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
- 0x3800_0000 0x4FFF_FFFF DSP Private area
-
- Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
- data communcation between PowerPC and DSP core.
- Rest is PowerPC private area.
-
-Flashing Images
----------------
-To place a new U-Boot image in the NAND flash and then boot
-with that new image temporarily, use this:
- tftp 1000000 u-boot-nand.bin
- nand erase 0 100000
- nand write 1000000 0 100000
- reset
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp c00000 bsc9131rdb.dtb
- bootm 1000000 2000000 c00000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <flash.h>
-#include <netdev.h>
-
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
- setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
-
- clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
- setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
- MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
- setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
- clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
- MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
- MPC85xx_PMUXCR_IFC_AD_GPIO |
- MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
-
- return 0;
-}
-
-int checkboard(void)
-{
- struct cpu_type *cpu;
-
- cpu = gd->arch.cpu;
- printf("Board: %sRDB\n", cpu->name);
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-static const struct node_info nodes[] = {
- { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
-};
-#endif
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
- fsl_fdt_fixup_dr_usb(blob, bd);
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_DRAM_SIZE 1024
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {0, 0, NULL}
-};
-
-unsigned long get_sdram_size(void)
-{
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
-}
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0) {
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
- }
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
- LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-
- return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/* Micron MT41J256M8HX-15E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1870,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
- LAW_TRGT_IF_DSP_CCSR),
- SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
- LAW_TRGT_IF_OCN_DSP),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-static void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
- /* Set, but do not enable the memory */
- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* Initialize the DDR3 */
- sdram_init();
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
- SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR (PA) */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* CCSRBAR (DSP) */
- SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
- CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1M, 1)
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_BSC9132QDS
-
-config SYS_BOARD
- default "bsc9132qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "BSC9132QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-BSC9132QDS BOARD
-M: Naveen Burmi <naveen.burmi@nxp.com>
-S: Maintained
-F: board/freescale/bsc9132qds/
-F: include/configs/BSC9132QDS.h
-F: configs/BSC9132QDS_NAND_DDRCLK100_defconfig
-F: configs/BSC9132QDS_NAND_DDRCLK133_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK100_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK133_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
-
-BSC9132QDS_NAND_DDRCLK100_SECURE BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-obj-y += bsc9132qds.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
- The BSC9132 is a highly integrated device that targets the evolving
- Microcell, Picocell, and Enterprise-Femto base station market subsegments.
-
- The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
- core technologies with MAPLE-B2P baseband acceleration processing elements
- to address the need for a high performance, low cost, integrated solution
- that handles all required processing layers without the need for an
- external device except for an RF transceiver or, in a Micro base station
- configuration, a host device that handles the L3/L4 and handover between
- sectors.
-
- The BSC9132 SoC includes the following function and features:
- - Power Architecture subsystem including two e500 processors with
- 512-Kbyte shared L2 cache
- - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
- cache
- - 32 Kbyte of shared M3 memory
- - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
- Processing (MAPLE-B2P)
- - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
- ECC), up to 1333 MHz data rate
- - Dedicated security engine featuring trusted boot
- - Two DMA controllers
- - OCNDMA with four bidirectional channels
- - SysDMA with sixteen bidirectional channels
- - Interfaces
- - Four-lane SerDes PHY
- - PCI Express controller complies with the PEX Specification-Rev 2.0
- - Two Common Public Radio Interface (CPRI) controller lanes
- - High-speed USB 2.0 host and device controller with ULPI interface
- - Enhanced secure digital (SD/MMC) host controller (eSDHC)
- - Antenna interface controller (AIC), supporting four industry
- standard JESD207/four custom ADI RF interfaces
- - ADI lanes support both full duplex FDD support & half duplex TDD
- - Universal Subscriber Identity Module (USIM) interface that
- facilitates communication to SIM cards or Eurochip pre-paid phone
- cards
- - Two DUART, two eSPI, and two I2C controllers
- - Integrated Flash memory controller (IFC)
- - GPIO
- - Sixteen 32-bit timers
-
-The SC3850 core subsystem consists of the following:
- - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
- - 32 KB, 8-way, level 1 data cache (L1 DCache)
- - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
- - Memory management unit (MMU)
- - Global interrupt controller ( GIC)
- - Debug and profiling unit (DPU)
- - Two 32-bit quad timers
-
-BSC9132QDS board Overview
--------------------------
- 2Gbyte DDR3 (on board DDR), Dual Ranki
- 32Mbyte 16bit NOR flash
- 128Mbyte 2K page size NAND Flash
- 256 Kbit M24256 I2C EEPROM
- 128 Mbit SPI Flash memory
- SD slot
- USB-ULPI
- eTSEC1: Connected to SGMII PHY
- eTSEC2: Connected to SGMII PHY
- PCIe
- CPRI
- SerDes
- I2C RTC
- DUART interface: supports one UARTs up to 115200 bps for console display
-
-Frequency Combinations Supported
---------------------------------
-Core MHz/CCB MHz/DDR(MT/s)
-1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
- (SYSCLK = 100MHz, DDRCLK = 100MHz)
-2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
- (SYSCLK = 100MHz, DDRCLK = 133MHz)
-
-Boot Methods Supported
------------------------
-1. NOR Flash
-2. NAND Flash
-3. SD Card
-4. SPI flash
-
-Default Boot Method
---------------------
-NOR boot
-
-Building U-Boot
---------------
-To build the U-Boot for BSC9132QDS:
-1. NOR Flash
- make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
- make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
-2. NAND Flash : It is currently not supported
-3. SPI Flash
- make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
- make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
-4. SD Card
- make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
- make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
-
-Memory map
------------
- 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
- 0x8000_0000 0x8FFF_FFFF NOR Flash 256M
- 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
- 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
- 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
- 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
- 0xC000_0000 0xC000_7FFF M3 Memory 32K
- 0xC001_0000 0xC001_FFFF PCI Express I/O 64K
- 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
- 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
- 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
- 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
- 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
- 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
- 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
- 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
-
-Flashing Images
----------------
-To place a new U-Boot image in the NAND flash and then boot
-with that new image temporarily, use this:
- tftp 1000000 u-boot-nand.bin
- nand erase 0 100000
- nand write 1000000 0 100000
- reset
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp c00000 bsc9132qds.dtb
- bootm 1000000 2000000 c00000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <flash.h>
-
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#endif
-
-#include "../common/qixis.h"
-DECLARE_GLOBAL_DATA_PTR;
-
-
-int board_early_init_f(void)
-{
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-
- setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-
- return 0;
-}
-
-void board_config_serdes_mux(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-
- switch (srds_cfg) {
- /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 22:
- case 23:
- case 24:
- case 25:
- case 26:
- QIXIS_WRITE_I2C(brdcfg[4], 0x03);
- break;
-
- /* PEX(1) PEX(2) SGMII1 CPRI 1 */
- case 6:
- case 7:
- case 8:
- case 9:
- case 10:
- case 27:
- case 28:
- case 29:
- case 30:
- case 31:
- QIXIS_WRITE_I2C(brdcfg[4], 0x01);
- break;
-
- /* PEX(1) PEX(2) SGMII1 SGMII2 */
- case 11:
- case 32:
- QIXIS_WRITE_I2C(brdcfg[4], 0x00);
- break;
-
- /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 33:
- case 34:
- case 35:
- case 36:
- case 37:
- QIXIS_WRITE_I2C(brdcfg[4], 0x07);
- break;
-
- /* PEX(1) SGMII2 SGMII1 CPRI 1 */
- case 17:
- case 18:
- case 19:
- case 20:
- case 21:
- case 38:
- case 39:
- case 40:
- case 41:
- case 42:
- QIXIS_WRITE_I2C(brdcfg[4], 0x05);
- break;
-
- /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
- case 43:
- case 44:
- case 45:
- case 46:
- case 47:
- QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
- break;
-
-
- default:
- break;
- }
-}
-
-/* Configure DSP DDR controller */
-void dsp_ddr_configure(void)
-{
- /*
- *There are separate DDR-controllers for DSP and PowerPC side DDR.
- *copy the ddr controller settings from PowerPC side DDR controller
- *to the DSP DDR controller as connected DDR memories are similar.
- */
- struct ccsr_ddr __iomem *pa_ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- struct ccsr_ddr temp_ddr;
- struct ccsr_ddr __iomem *dsp_ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
-
- memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
- temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
- temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
- memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
- dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);
-
- set_tlb(1, flashbase + 0x4000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
-#endif
- board_config_serdes_mux();
- dsp_ddr_configure();
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
-int checkboard(void)
-{
- struct cpu_type *cpu;
- u8 sw;
-
- cpu = gd->arch.cpu;
- printf("Board: %sQDS\n", cpu->name);
-
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
- QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- printf("IFC chip select:");
- switch (sw) {
- case 0:
- printf("NOR\n");
- break;
- case 2:
- printf("Promjet\n");
- break;
- case 4:
- printf("NAND\n");
- break;
- default:
- printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
- break;
- }
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-
-#endif
-
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- #ifdef CONFIG_PCI
- pci_eth_init(bis);
- #endif
-
- return 0;
-}
-
-#define USBMUX_SEL_MASK 0xc0
-#define USBMUX_SEL_UART2 0xc0
-#define USBMUX_SEL_USB 0x40
-#define SPIMUX_SEL_UART3 0x80
-#define GPS_MUX_SEL_GPS 0x40
-
-#define TSEC_1588_CLKIN_MASK 0x03
-#define CON_XCVR_REF_CLK 0x00
-
-int misc_init_r(void)
-{
- u8 val;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 porbmsr = in_be32(&gur->porbmsr);
- u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
-
- /*Configure 1588 clock-in source from RF Card*/
- val = QIXIS_READ_I2C(brdcfg[5]);
- QIXIS_WRITE_I2C(brdcfg[5],
- (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
-
- if (hwconfig("uart2") && hwconfig("usb1")) {
- printf("UART2 and USB cannot work together on the board\n");
- printf("Remove one from hwconfig and reset\n");
- } else {
- if (hwconfig("uart2")) {
- val = QIXIS_READ_I2C(brdcfg[5]);
- QIXIS_WRITE_I2C(brdcfg[5],
- (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
- clrbits_be32(&gur->pmuxcr3,
- MPC85xx_PMUXCR3_USB_SEL_MASK);
- setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
- } else {
- /* By default USB should be selected.
- * Programming FPGA to select USB. */
- val = QIXIS_READ_I2C(brdcfg[5]);
- QIXIS_WRITE_I2C(brdcfg[5],
- (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
- }
-
- }
-
- if (hwconfig("sim")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SPI) {
-
- val = QIXIS_READ_I2C(brdcfg[3]);
- QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
- clrbits_be32(&gur->pmuxcr,
- MPC85xx_PMUXCR0_SIM_SEL_MASK);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
- }
- }
-
- if (hwconfig("uart3")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SDHC) {
-
- /* UART3 and SPI1 (Flashes) are muxed together */
- val = QIXIS_READ_I2C(brdcfg[3]);
- QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
- clrbits_be32(&gur->pmuxcr3,
- MPC85xx_PMUXCR3_UART3_SEL_MASK);
- setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
-
- /* MUX to select UART3 connection to J24 header
- * or to GPS */
- val = QIXIS_READ_I2C(brdcfg[6]);
- if (hwconfig("gps"))
- QIXIS_WRITE_I2C(brdcfg[6],
- (val | GPS_MUX_SEL_GPS));
- else
- QIXIS_WRITE_I2C(brdcfg[6],
- (val & ~(GPS_MUX_SEL_GPS)));
- }
- }
- return 0;
-}
-
-void fdt_del_node_compat(void *blob, const char *compatible)
-{
- int err;
- int off = fdt_node_offset_by_compatible(blob, -1, compatible);
- if (off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- compatible, fdt_strerror(off));
- return;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- compatible, fdt_strerror(err));
- }
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-static const struct node_info nodes[] = {
- { "cfi-flash", MTD_DEV_TYPE_NOR, },
- { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
-};
-#endif
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- #if defined(CONFIG_PCI)
- FT_FSL_PCI_SETUP;
- #endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 porbmsr = in_be32(&gur->porbmsr);
- u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
-
- if (!(hwconfig("uart2") && hwconfig("usb1"))) {
- /* If uart2 is there in hwconfig remove usb node from
- * device tree */
-
- if (hwconfig("uart2")) {
- /* remove dts usb node */
- fdt_del_node_compat(blob, "fsl-usb2-dr");
- } else {
- fsl_fdt_fixup_dr_usb(blob, bd);
- fdt_del_node_and_alias(blob, "serial2");
- }
- }
-
- if (hwconfig("uart3")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SDHC)
- /* Delete SPI node from the device tree */
- fdt_del_node_and_alias(blob, "spi1");
- } else
- fdt_del_node_and_alias(blob, "serial3");
-
- if (hwconfig("sim")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SPI) {
-
- /* remove dts sdhc node */
- fdt_del_node_compat(blob, "fsl,esdhc");
- } else if (romloc == PORBMSR_ROMLOC_SDHC) {
-
- /* remove dts sim node */
- fdt_del_node_compat(blob, "fsl,sim-v1.0");
- printf("SIM & SDHC can't work together on the board");
- printf("\nRemove sim from hwconfig and reset\n");
- }
- }
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {1060, 1333, &ddr_cfg_regs_1333},
- {0, 0, NULL}
-};
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
- LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-
- return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/* Micron MT41J512M8_187E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1870,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_FPGA_BASE_PHYS
- SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-#endif
- SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
- LAW_TRGT_IF_DSP_CCSR),
- SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M,
- LAW_TRGT_IF_OCN_DSP),
- SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K,
- LAW_TRGT_IF_CLASS_DSP),
- SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G,
- LAW_TRGT_IF_CLASS_DSP)
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-#if CONFIG_DDR_CLK_FREQ == 100000000
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-#elif CONFIG_DDR_CLK_FREQ == 133000000
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-#else
- puts("Not a valid DDR Freq Found! Please Reset\n");
-#endif
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* Initialize the DDR3 */
- sdram_init();
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
- SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR (PA) */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* CCSRBAR (DSP) */
- SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
- CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
- MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 3, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64K, 1),
-#endif
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_FPGA_BASE
- /* *I*G - Board FPGA */
- SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_C29XPCIE
-
-config SYS_BOARD
- default "c29xpcie"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "C29XPCIE"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-C29XPCIE BOARD
-M: Po Liu <po.liu@nxp.com>
-S: Maintained
-F: board/freescale/c29xpcie/
-F: include/configs/C29XPCIE.h
-F: configs/C29XPCIE_defconfig
-F: configs/C29XPCIE_NAND_defconfig
-F: configs/C29XPCIE_SPIFLASH_defconfig
-F: configs/C29XPCIE_NOR_SECBOOT_defconfig
-F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-
-MINIMAL=
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-obj-y += c29xpcie.o
-obj-y += cpld.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
-=========
-C29XPCIE board is a series of Freescale PCIe add-in cards to perform
-as public key crypto accelerator or secure key management module.
-It includes C293PCIE board, C293PCIE board and C291PCIE board.
-The Freescale C29x family is a high performance crypto co-processor.
-It combines a single e500v2 core with necessary SEC engines.
-(maximum core frequency 1000/1200 MHz).
-
-The C29xPCIE board features are as follows:
-Memory subsystem:
- - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- - 64 Mbyte NOR flash single-chip memory
- - 4 Gbyte NAND flash memory
- - 1 Mbit AT24C1024 I2C EEPROM
- - 16 Mbyte SPI memory
-
-Interfaces:
- - 10/100/1000 BaseT Ethernet ports:
- - eTSEC1, RGMII: one 10/100/1000 port
- - eTSEC2, RGMII: one 10/100/1000 port
- - DUART interface:
- - DUART interface: supports two UARTs up to 115200 bps for
- console display
-
-Board connectors:
- - Mini-ITX power supply connector
- - JTAG/COP for debugging
-
-Physical Memory Map on C29xPCIE
-===============================
-Address Start Address End Memory type
-0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
-0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
-0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
-0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
-0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
-0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
-0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
-
-Serial Port Configuration on C29xPCIE
-=====================================
-Configure the serial port of the attached computer with the following values:
- -Data rate: 115200 bps
- -Number of data bits: 8
- -Parity: None
- -Number of Stop bits: 1
- -Flow Control: Hardware/None
-
-Settings of DIP-switch
-======================
- SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
- SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
-Note: 1 stands for 'off', 0 stands for 'on'
-
-Build and program U-Boot to NOR flash
-==================================
-1. Build u-boot.bin image example:
- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
- make C293PCIE
-
-2. Program u-boot.bin into NOR flash
- => tftp $loadaddr $uboot
- => protect off eff40000 +$filesize
- => erase eff40000 +$filesize
- => cp.b $loadaddr eff40000 $filesize
-
-3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
-
-Alternate NOR bank
-==================
-There are four banks in C29XPCIE board, example to change bank booting:
-1. Program u-boot.bin into alternate NOR bank
- => tftp $loadaddr $uboot
- => protect off e9f40000 +$filesize
- => erase e9f40000 +$filesize
- => cp.b $loadaddr e9f40000 $filesize
-
-2. Switch to alternate NOR bank
- => cpld_cmd reset altbank [bank]
- - [bank] bank value select 1-4
- - bank 1 on the flash 0x0000000~0x0ffffff
- - bank 2 on the flash 0x1000000~0x1ffffff
- - bank 3 on the flash 0x2000000~0x2ffffff
- - bank 4 on the flash 0x3000000~0x3ffffff
- or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
-
-Build and program U-Boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
- make C29xPCIE_SPIFLASH_config; make
- Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
-
-2. Program u-boot-spi.bin into SPI flash
- => tftp $loadaddr $uboot-spi
- => sf erase 0 100000
- => sf write $loadaddr 0 $filesize
-
-3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <pci.h>
-#include <fsl_ifc.h>
-#include <asm/fsl_pci.h>
-
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- printf("Board: %sPCIe, ", cpu->name);
- printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-
- /* Clock configuration to access CPLD using IFC(GPCM) */
- setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 1; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- /* Register 1G MDIO bus */
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_del_sec(void *blob, int offset)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
- CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
- + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
- fdt_del_node(blob, nodeoff);
- offset++;
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
- struct cpu_type *cpu;
-
- cpu = gd->arch.cpu;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
-#if defined(CONFIG_PCI)
- FT_FSL_PCI_SETUP;
-#endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
- if (cpu->soc_ver == SVR_C291)
- fdt_del_sec(blob, 1);
- else if (cpu->soc_ver == SVR_C292)
- fdt_del_sec(blob, 2);
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2013 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- * Po Liu <Po.Liu@freescale.com>
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
- * CPLD register map
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#include "cpld.h"
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(u8 banksel)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- u8 reg11;
-
- reg11 = in_8(&cpld_data->flhcsr);
-
- switch (banksel) {
- case 1:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
- break;
- case 2:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
- break;
- case 3:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
- break;
- case 4:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
- break;
- default:
- printf("Invalid value! [1-4]\n");
- return;
- }
-
- udelay(100);
- do_reset(NULL, 0, 0, NULL);
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
- cpld_set_altbank(4);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
- printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
- printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
- printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
- printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
- printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
- printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
- printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
- printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
- printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
- printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
- printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
- printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
- printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
- printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
- printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
- putc('\n');
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
- unsigned char value;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (!strcmp(argv[2], "altbank") && argv[3]) {
- value = (u8)simple_strtoul(argv[3], NULL, 16);
- cpld_set_altbank(value);
- } else if (!argv[2])
- cpld_set_defbank();
- else
- cmd_usage(cmdtp);
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
- "Reset the board using the CPLD sequencer",
- "reset - hard reset to default bank 4\n"
- "cpld_cmd reset altbank [bank]- reset to alternate bank\n"
- " - [bank] bank value select 1-4\n"
- " - bank 1 on the flash 0x0000000~0x0ffffff\n"
- " - bank 2 on the flash 0x1000000~0x1ffffff\n"
- " - bank 3 on the flash 0x2000000~0x2ffffff\n"
- " - bank 4 on the flash 0x3000000~0x3ffffff\n"
-#ifdef DEBUG
- "cpld_cmd dump - display the CPLD registers\n"
-#endif
- );
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2013 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
- * Po Liu <Po.Liu@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
- u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
- u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
- u8 hwver; /* 0x2 - Hardware Version Register */
- u8 cpldver; /* 0x3 - Software Version Register */
- u8 res[12];
- u8 rstcon; /* 0x10 - Reset control register */
- u8 flhcsr; /* 0x11 - Flash control and status Register */
- u8 wdcsr; /* 0x12 - Watchdog control and status Register */
- u8 wdkick; /* 0x13 - Watchdog kick Register */
- u8 fancsr; /* 0x14 - Fan control and status Register */
- u8 ledcsr; /* 0x15 - LED control and status Register */
- u8 misccsr; /* 0x16 - Misc control and status Register */
- u8 bootor; /* 0x17 - Boot configure override Register */
- u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
- u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
- u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
- u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
-};
-
-#define CPLD_BANKSEL_EN 0x02
-#define CPLD_BANKSEL_MASK 0x3f
-#define CPLD_SELECT_BANK1 0xc0
-#define CPLD_SELECT_BANK2 0x80
-#define CPLD_SELECT_BANK3 0x40
-#define CPLD_SELECT_BANK4 0x00
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-#include "cpld.h"
-
-#define C29XPCIE_HARDWARE_REVA 0x40
-/*
- * Micron MT41J128M16HA-15E
- * */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 536870912u,
- .capacity = 536870912u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1650,
- .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
- .taa_ps = 14050,
- .twr_ps = 15000,
- .trcd_ps = 13500,
- .trrd_ps = 75000,
- .trp_ps = 13500,
- .tras_ps = 40000,
- .trc_ps = 49500,
- .trfc_ps = 160000,
- .twtr_ps = 75000,
- .trtp_ps = 75000,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- int i;
-
- popts->clk_adjust = 4;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 4;
- popts->half_strength_driver_enable = 1;
- popts->bstopre = 0x3cf;
- popts->quad_rank_present = 1;
- popts->rtt_override = 1;
- popts->rtt_override_value = 1;
- popts->dynamic_power = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x4;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
- popts->ecc_mode = 0;
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
-
-void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
-{
- int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
- sizeof(generic_spd_eeprom_t));
-
- if (ret) {
- printf("DDR: failed to read SPD from address %u\n",
- i2c_address);
- memset(spd, 0, sizeof(generic_spd_eeprom_t));
- }
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
- LAW_TRGT_IF_PLATFORM_SRAM),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
- /* relocate environment function pointers etc. */
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("TPL\n");
-#else
- puts("SPL\n");
-#endif
-
- nand_boot();
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot...\n");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("SPL\n");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 1, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256K, 1),
-#endif
-#endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_64K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
- CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
- CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
- CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 9, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_MPC8536DS
-
-config SYS_BOARD
- default "mpc8536ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8536DS"
-
-endif
+++ /dev/null
-MPC8536DS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8536ds/
-F: include/configs/MPC8536DS.h
-F: configs/MPC8536DS_defconfig
-F: configs/MPC8536DS_36BIT_defconfig
-F: configs/MPC8536DS_SDCARD_defconfig
-F: configs/MPC8536DS_SPIFLASH_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8536ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview:
-=========
-
-The MPC8536E integrates a PowerPC processor core with system logic
-required for imaging, networking, and communications applications.
-
-Boot from NAND:
-===============
-
-The MPC8536E is capable of booting from NAND flash which uses the image
-u-boot-nand.bin. This image contains two parts: a first stage image(also
-call 4K NAND loader and a second stage image. The former is appended to
-the latter to produce u-boot-nand.bin.
-
-The bootup process can be divided into two stages: the first stage will
-configure the L2SRAM, then copy the second stage image to L2SRAM and jump
-to it. The second stage image is to configure all the hardware and boot up
-to U-Boot command line.
-
-The 4K NAND loader's code comes from the corresponding nand_spl directory,
-along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
-is mainly used to shrink the code size to the 4K size limitation.
-
-The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
-second stage image. It's set in the board config file when boot from NAND
-is selected.
-
-Build and boot steps
---------------------
-
-1. Building image
- make MPC8536DS_NAND_config
- make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
- SW2[5-8] = 1011
- SW9[1-3] = 101
- Note: 1 stands for 'on', 0 stands for 'off'
-
-3. Flash image
- tftp 1000000 u-boot-nand.bin
- nand erase 0 a0000
- nand write 1000000 0 a0000
-
-Boot from On-chip ROM:
-======================
-
-The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
-and boot from eSPI. When power on, the porcessor excutes the ROM code to
-initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
-the memory device that interfaced to the controller, such as the SDCard or
-SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
-
-The memory device should contain a specific data structure with control word
-and config word at the fixed address. The config word direct the process how
-to config the memory device, and the control word direct the processor where
-to find the image on the memory device, or where copy the main image to. The
-user can use any method to store the data structure to the memory device, only
-if store it on the assigned address.
-
-Build and boot steps
---------------------
-
-For boot from eSDHC:
-1. Build image
- make MPC8536DS_SDCARD_config
- make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
- SW2[5-8] = 0111
- SW3[1] = 0
- SW8[7] = 0 - The on-board SD/MMC slot is active
- SW8[7] = 1 - The externel SD/MMC slot is active
-
-3. Put image to SDCard
- Put the follwing info at the assigned address on the SDCard:
-
- Offset | Data | Description
- --------------------------------------------------------
- | 0x40-0x43 | 0x424F4F54 | BOOT signature |
- --------------------------------------------------------
- | 0x48-0x4B | 0x00080000 | u-boot.bin's size |
- --------------------------------------------------------
- | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
- --------------------------------------------------------
- | 0x58-0x5B | 0xF8F80000 | Target Address |
- -------------------------------------------------------
- | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address |
- --------------------------------------------------------
- | 0x68-0x6B | 0x6 | Number of Config Addr/Data |
- --------------------------------------------------------
- | 0x80-0x83 | 0xFF720100 | Config Addr 1 |
- | 0x84-0x87 | 0xF8F80000 | Config Data 1 |
- --------------------------------------------------------
- | 0x88-0x8b | 0xFF720e44 | Config Addr 2 |
- | 0x8c-0x8f | 0x0000000C | Config Data 2 |
- --------------------------------------------------------
- | 0x90-0x93 | 0xFF720000 | Config Addr 3 |
- | 0x94-0x97 | 0x80010000 | Config Data 3 |
- --------------------------------------------------------
- | 0x98-0x9b | 0xFF72e40c | Config Addr 4 |
- | 0x9c-0x9f | 0x00000040 | Config Data 4 |
- --------------------------------------------------------
- | 0xa0-0xa3 | 0x40000001 | Config Addr 5 |
- | 0xa4-0xa7 | 0x00000100 | Config Data 5 |
- --------------------------------------------------------
- | 0xa8-0xab | 0x80000001 | Config Addr 6 |
- | 0xac-0xaf | 0x80000001 | Config Data 6 |
- --------------------------------------------------------
- | ...... |
- --------------------------------------------------------
- | 0x???????? | u-boot.bin |
- --------------------------------------------------------
-
- then insert the SDCard to the active slot to boot up.
-
-For boot from eSPI:
-1. Build image
- make MPC8536DS_SPIFLASH_config
- make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
- SW2[5-8] = 0110
-
-3. Put image to SPI flash
- Put the info in the above table onto the SPI flash, then
- boot up.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-
- /*
- * For wake up arp feature, we need enable auto self refresh
- */
- popts->auto_self_refresh_en = 1;
- popts->sr_it = 0x6;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <spd.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <spd_sdram.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-#include <sata.h>
-
-#include "../common/sgmii_riser.h"
-
-int board_early_init_f (void)
-{
-#ifdef CONFIG_MMC
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-
- /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
- * however, this erratum only applies to MPC8536 Rev1.0.
- * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
- if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
- (SVR_MIN(get_svr()) >= 0x1))
- || (SVR_MAJ(get_svr() & 0x7) > 0x1))
- setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
-#endif
- return 0;
-}
-
-int checkboard (void)
-{
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf("Board: MPC8536DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
- case PIXIS_VBOOT_LBMAP_NOR0:
- puts ("vBank: 0\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR1:
- puts ("vBank: 1\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR2:
- puts ("vBank: 2\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR3:
- puts ("vBank: 3\n");
- break;
- case PIXIS_VBOOT_LBMAP_PJET:
- puts ("Promjet\n");
- break;
- case PIXIS_VBOOT_LBMAP_NAND:
- puts ("NAND\n");
- break;
- }
-
- return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
- uint d_init;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-
-#if defined (CONFIG_DDR_ECC)
- ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
- ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
- ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
- udelay(1000);
- }
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- return 512 * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr;
- u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
- int first_free_busno;
-
- first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- porpllsr = in_be32(&gur->porpllsr);
-
- pci_speed = 66666000;
- pci_32 = 1;
- pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33333000) ? "33" :
- (pci_speed == 66666000) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter",
- pci_info.regs);
-
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 1; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].phyaddr = 0;
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].phyaddr = 1;
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
-#ifdef CONFIG_FSL_SGMII_RISER
- if (is_serdes_configured(SGMII_TSEC1) ||
- is_serdes_configured(SGMII_TSEC3)) {
- fsl_sgmii_riser_init(tsec_info, num);
- }
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-#ifdef CONFIG_HAS_FSL_MPH_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256K, 1),
-
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_P1022DS
-
-config SYS_BOARD
- default "p1022ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P1022DS"
-
-endif
+++ /dev/null
-P1022DS BOARD
-M: Timur Tabi <timur@tabi.org>
-S: Maintained
-F: board/freescale/p1022ds/
-F: include/configs/P1022DS.h
-F: configs/P1022DS_defconfig
-F: configs/P1022DS_36BIT_defconfig
-F: configs/P1022DS_36BIT_NAND_defconfig
-F: configs/P1022DS_36BIT_SDCARD_defconfig
-F: configs/P1022DS_36BIT_SPIFLASH_defconfig
-F: configs/P1022DS_NAND_defconfig
-F: configs/P1022DS_SDCARD_defconfig
-F: configs/P1022DS_SPIFLASH_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2010 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-obj-y += p1022ds.o
-obj-y += ddr.o
-obj-$(CONFIG_FSL_DIU_FB) += diu.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
-P1022ds is a Low End Dual core platform supporting the P1022 processor
-of QorIQ series. P1022 is an e500 based dual core SOC.
-
-
-Pin Multiplex(hwconfig setting)
--------------------------------
-Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
-via hwconfig, i.e:
-'setenv hwconfig usb2' to enable USB2 and disable eTsec2
-'setenv hwconfig tdm' to enable TDM and disable Audio
-'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
- and disable TDM
-'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
-'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
- is 11MHz), disable eTsec2 and TDM
-
-Warning: TDM and AUDIO can not enable simultaneous !
-and AUDIO codec clock sources only setting as 11MHz or 12MHz !
-'setenv hwconfig 'audclk:12;tdm' --- error !
-'setenv hwconfig 'audclk:11;tdm' --- error !
-'setenv hwconfig 'audclk:10' --- error !
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust; /* Range: 0-8 */
- u32 cpo; /* Range: 2-31 */
- u32 write_data_delay; /* Range: 0-6 */
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {1, 549, 5, 31, 3, 0},
- {1, 850, 5, 31, 5, 0},
- {2, 549, 5, 31, 3, 0},
- {2, 850, 5, 31, 5, 0},
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- unsigned long ddr_freq;
- unsigned int i;
-
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /* set odt_rd_cfg and odt_wr_cfg. */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
- }
-
- pbsp = dimm0;
- /*
- * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- popts->half_strength_driver_enable = 1;
-
- /* Per AN4039, enable ZQ calibration. */
- popts->zq_en = 1;
-
- /*
- * For wake-up on ARP, we need auto self refresh enabled
- */
- popts->auto_self_refresh_en = 1;
- popts->sr_it = 0xb;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Authors: Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include "../common/ngpixis.h"
-#include <fsl_diu_fb.h>
-
-/* The CTL register is called 'csr' in the ngpixis_t structure */
-#define PX_CTL_ALTACC 0x80
-
-#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
-#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
-#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
-#define PX_BRDCFG0_ELBC_DIU 0x02
-
-#define PX_BRDCFG1_DVIEN 0x80
-#define PX_BRDCFG1_DFPEN 0x40
-#define PX_BRDCFG1_BACKLIGHT 0x20
-
-#define PMUXCR_ELBCDIU_MASK 0xc0000000
-#define PMUXCR_ELBCDIU_NOR16 0x80000000
-#define PMUXCR_ELBCDIU_DIU 0x40000000
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F 0x10000000
-#define AD_ALPHA_C_SHIFT 25
-#define AD_BLUE_C_SHIFT 23
-#define AD_GREEN_C_SHIFT 21
-#define AD_RED_C_SHIFT 19
-#define AD_PIXEL_S_SHIFT 16
-#define AD_COMP_3_SHIFT 12
-#define AD_COMP_2_SHIFT 8
-#define AD_COMP_1_SHIFT 4
-#define AD_COMP_0_SHIFT 0
-
-/*
- * Variables used by the DIU/LBC switching code. It's safe to makes these
- * global, because the DIU requires DDR, so we'll only run this code after
- * relocation.
- */
-static u8 px_brdcfg0;
-static u32 pmuxcr;
-static void *lbc_lcs0_ba;
-static void *lbc_lcs1_ba;
-static u32 old_br0, old_or0, old_br1, old_or1;
-static u32 new_br0, new_or0, new_br1, new_or1;
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned long speed_ccb, temp;
- u32 pixval;
-
- speed_ccb = get_bus_freq(0);
- temp = 1000000000 / pixclock;
- temp *= 1000;
- pixval = speed_ccb / temp;
- debug("DIU pixval = %u\n", pixval);
-
- /* Modify PXCLK in GUTS CLKDVDR */
- temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
- out_be32(&gur->clkdvdr, temp); /* turn off clock */
- out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- const char *name;
- u32 pixel_format;
- u8 temp;
- phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
-
- /*
- * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
- * otherwise writes to these addresses won't actually appear on the
- * local bus, and so the PIXIS won't see them.
- *
- * In FCM mode, writes go to the NAND controller, which does not pass
- * them to the localbus directly. So we force BR0 and BR1 into GPCM
- * mode, since we don't care about what's behind the localbus any
- * more. However, we save those registers first, so that we can
- * restore them when necessary.
- */
- new_br0 = old_br0 = get_lbc_br(0);
- new_br1 = old_br1 = get_lbc_br(1);
- new_or0 = old_or0 = get_lbc_or(0);
- new_or1 = old_or1 = get_lbc_or(1);
-
- /*
- * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
- * force the values to simple 32KB GPCM windows with the most
- * conservative timing.
- */
- if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
- new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
- new_or0 = OR_AM_32KB | 0xFF7;
- set_lbc_br(0, new_br0);
- set_lbc_or(0, new_or0);
- }
- if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
- new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
- new_or1 = OR_AM_32KB | 0xFF7;
- set_lbc_br(1, new_br1);
- set_lbc_or(1, new_or1);
- }
-
- /*
- * Determine the physical addresses for Chip Selects 0 and 1. The
- * BR0/BR1 registers contain the truncated physical addresses for the
- * chip selects, mapped via the localbus LAW. Since the BRx registers
- * only contain the lower 32 bits of the address, we have to determine
- * the upper 4 bits some other way. The proper way is to scan the LAW
- * table looking for a matching localbus address. Instead, we cheat.
- * We know that the upper bits are 0 for 32-bit addressing, or 0xF for
- * 36-bit addressing.
- */
-#ifdef CONFIG_PHYS_64BIT
- phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
- phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
-#else
- phys0 = old_br0 & old_or0 & BR_BA;
- phys1 = old_br1 & old_or1 & BR_BA;
-#endif
-
- /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
- lbc_lcs0_ba = map_physmem(phys0, 1, 0);
- lbc_lcs1_ba = map_physmem(phys1, 1, 0);
-
- pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
- (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
- (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
- (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
- (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
- temp = in_8(&pixis->brdcfg1);
-
- if (strncmp(port, "lvds", 4) == 0) {
- /* Single link LVDS */
- temp &= ~PX_BRDCFG1_DVIEN;
- /*
- * LVDS also needs backlight enabled, otherwise the display
- * will be blank.
- */
- temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
- name = "Single-Link LVDS";
- } else { /* DVI */
- /* Enable the DVI port, disable the DFP and the backlight */
- temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
- temp |= PX_BRDCFG1_DVIEN;
- name = "DVI";
- }
-
- printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
- out_8(&pixis->brdcfg1, temp);
-
- /*
- * Enable PIXIS indirect access mode. This is a hack that allows us to
- * access PIXIS registers even when the LBC pins have been muxed to the
- * DIU.
- */
- setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
- /*
- * Route the LAD pins to the DIU. This will disable access to the eLBC,
- * which means we won't be able to read/write any NOR flash addresses!
- */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
- px_brdcfg0 = in_8(lbc_lcs1_ba);
- out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
- in_8(lbc_lcs1_ba);
-
- /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
- clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
- pmuxcr = in_be32(&gur->pmuxcr);
-
- return fsl_diu_init(xres, yres, pixel_format, 0);
-}
-
-/*
- * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
- *
- * On the Freescale P1022, the DIU video signal and the LBC address/data lines
- * share the same pins, which means that when the DIU is active (e.g. the
- * console is on the DVI display), NOR flash cannot be accessed. So we use the
- * weak accessor feature of the CFI flash code to temporarily switch the pin
- * mux from DIU to LBC whenever we want to read or write flash. This has a
- * significant performance penalty, but it's the only way to make it work.
- *
- * There are two muxes: one on the chip, and one on the board. The chip mux
- * controls whether the pins are used for the DIU or the LBC, and it is
- * set via PMUXCR. The board mux controls whether those signals go to
- * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
- */
-static int set_mux_to_lbc(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Switch the muxes only if they're currently set to DIU mode */
- if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
- PMUXCR_ELBCDIU_NOR16) {
- /*
- * In DIU mode, the PIXIS can only be accessed indirectly
- * since we can't read/write the LBC directly.
- */
- /* Set the board mux to LBC. This will disable the display. */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
- out_8(lbc_lcs1_ba, px_brdcfg0);
- in_8(lbc_lcs1_ba);
-
- /* Disable indirect PIXIS mode */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
- clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
-
- /* Set the chip mux to LBC mode, so that writes go to flash. */
- out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
- PMUXCR_ELBCDIU_NOR16);
- in_be32(&gur->pmuxcr);
-
- /* Restore the BR0 and BR1 settings */
- set_lbc_br(0, old_br0);
- set_lbc_or(0, old_or0);
- set_lbc_br(1, old_br1);
- set_lbc_or(1, old_or1);
-
- return 1;
- }
-
- return 0;
-}
-
-/*
- * set_mux_to_diu - re-enable the DIU muxing
- *
- * This function restores the chip and board muxing to point to the DIU.
- */
-static void set_mux_to_diu(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Set BR0 and BR1 to GPCM mode */
- set_lbc_br(0, new_br0);
- set_lbc_or(0, new_or0);
- set_lbc_br(1, new_br1);
- set_lbc_or(1, new_or1);
-
- /* Enable indirect PIXIS mode */
- setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
- /* Set the board mux to DIU. This will enable the display. */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
- out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
- in_8(lbc_lcs1_ba);
-
- /* Set the chip mux to DIU mode. */
- out_be32(&gur->pmuxcr, pmuxcr);
- in_be32(&gur->pmuxcr);
-}
-
-/*
- * pixis_read - board-specific function to read from the PIXIS
- *
- * This function overrides the generic pixis_read() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-u8 pixis_read(unsigned int reg)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Use indirect mode if the mux is currently set to DIU mode */
- if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
- PMUXCR_ELBCDIU_NOR16) {
- out_8(lbc_lcs0_ba, reg);
- return in_8(lbc_lcs1_ba);
- } else {
- void *p = (void *)PIXIS_BASE;
-
- return in_8(p + reg);
- }
-}
-
-/*
- * pixis_write - board-specific function to write to the PIXIS
- *
- * This function overrides the generic pixis_write() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-void pixis_write(unsigned int reg, u8 value)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Use indirect mode if the mux is currently set to DIU mode */
- if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
- PMUXCR_ELBCDIU_NOR16) {
- out_8(lbc_lcs0_ba, reg);
- out_8(lbc_lcs1_ba, value);
- /* Do a read-back to ensure the write completed */
- in_8(lbc_lcs1_ba);
- } else {
- void *p = (void *)PIXIS_BASE;
-
- out_8(p + reg, value);
- }
-}
-
-void pixis_bank_reset(void)
-{
- /*
- * For some reason, a PIXIS bank reset does not work if the PIXIS is
- * in indirect mode, so switch to direct mode first.
- */
- set_mux_to_lbc();
-
- out_8(&pixis->vctl, 0);
- out_8(&pixis->vctl, 1);
-
- while (1);
-}
-
-#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-void flash_write8(u8 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writeb(value, addr);
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode.
- * set_mux_to_diu() includes a sync that will ensure the
- * __raw_readb() completes before it switches the mux.
- */
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write16(u16 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writew(value, addr);
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode.
- * set_mux_to_diu() includes a sync that will ensure the
- * __raw_readb() completes before it switches the mux.
- */
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write32(u32 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writel(value, addr);
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode.
- * set_mux_to_diu() includes a sync that will ensure the
- * __raw_readb() completes before it switches the mux.
- */
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write64(u64 value, void *addr)
-{
- int sw = set_mux_to_lbc();
- uint32_t *p = addr;
-
- /*
- * There is no __raw_writeq(), so do the write manually. We don't trust
- * the compiler, so we use inline assembly.
- */
- __asm__ __volatile__(
- "stw%U0%X0 %2,%0;\n"
- "stw%U1%X1 %3,%1;\n"
- : "=m" (*p), "=m" (*(p + 1))
- : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
-
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode. We
- * read addr+4 because we just wrote to addr+4, so that's how we
- * maintain execution order. set_mux_to_diu() includes a sync
- * that will ensure the __raw_readb() completes before it
- * switches the mux.
- */
- __raw_readb(addr + 4);
- set_mux_to_diu();
- }
-}
-
-u8 flash_read8(void *addr)
-{
- u8 ret;
-
- int sw = set_mux_to_lbc();
-
- ret = __raw_readb(addr);
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-u16 flash_read16(void *addr)
-{
- u16 ret;
-
- int sw = set_mux_to_lbc();
-
- ret = __raw_readw(addr);
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-u32 flash_read32(void *addr)
-{
- u32 ret;
-
- int sw = set_mux_to_lbc();
-
- ret = __raw_readl(addr);
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-u64 flash_read64(void *addr)
-{
- u64 ret;
-
- int sw = set_mux_to_lbc();
-
- /* There is no __raw_readq(), so do the read manually */
- ret = *(volatile u64 *)addr;
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <hwconfig.h>
-
-#include "../common/ngpixis.h"
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, 0x1000);
-#ifdef CONFIG_SYS_RAMBOOT
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
- /* Set the pin muxing to enable ETSEC2. */
- clrbits_be32(&gur->pmuxcr2, 0x001F8000);
-
- /* Enable the SPI */
- clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-
- return 0;
-}
-
-int checkboard(void)
-{
- u8 sw;
-
- printf("Board: P1022DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
- sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
-
- switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
- case 0:
- printf ("vBank: %u\n", ((sw & 0x30) >> 4));
- break;
- case 1:
- printf ("NAND\n");
- break;
- case 2:
- case 3:
- puts ("Promjet\n");
- break;
- }
-
- return 0;
-}
-
-#define CONFIG_TFP410_I2C_ADDR 0x38
-
-/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
-
-/* Route the I2C1 pins to the SSI port instead. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
-
-/* Choose the 12.288Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
-
-/* Choose the 11.2896Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
-
-/* Connect to USB2 */
-#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
-/* Connect to TFM bus */
-#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
-/* Connect to SPI */
-#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
-
-int misc_init_r(void)
-{
- u8 temp;
- const char *audclk;
- size_t arglen;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- /* For DVI, enable the TFP410 Encoder. */
-
- temp = 0xBF;
- if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
- return -1;
- if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
- return -1;
- debug("DVI Encoder Read: 0x%02x\n", temp);
-
- temp = 0x10;
- if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
- return -1;
- if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
- return -1;
- debug("DVI Encoder Read: 0x%02x\n",temp);
-
- /* Enable the USB2 in PMUXCR2 and FGPA */
- if (hwconfig("usb2")) {
- clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
- MPC85xx_PMUXCR2_USB);
- setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
- }
-
- /* tdm and audio can not enable simultaneous*/
- if (hwconfig("tdm") && hwconfig("audclk")){
- printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
- return -1;
- }
-
- /* Enable the TDM in PMUXCR and FGPA */
- if (hwconfig("tdm")) {
- clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
- MPC85xx_PMUXCR_TDM);
- setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
- /* TDM need some configration option by SPI */
- clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
- MPC85xx_PMUXCR_SPI);
- setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
- }
-
- /*
- * Enable the reference clock for the WM8776 codec, and route the MUX
- * pins for SSI. The default is the 12.288 MHz clock
- */
-
- if (hwconfig("audclk")) {
- temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
- CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
- temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
-
- audclk = hwconfig_arg("audclk", &arglen);
- /* Check the first two chars only */
- if (audclk && (strncmp(audclk, "11", 2) == 0))
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
- else
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
- setbits_8(&pixis->brdcfg1, temp);
- }
-
- return 0;
-}
-
-/*
- * A list of PCI and SATA slots
- */
-enum slot_id {
- SLOT_PCIE1 = 1,
- SLOT_PCIE2,
- SLOT_PCIE3,
- SLOT_PCIE4,
- SLOT_PCIE5,
- SLOT_SATA1,
- SLOT_SATA2
-};
-
-/*
- * This array maps the slot identifiers to their names on the P1022DS board.
- */
-static const char *slot_names[] = {
- [SLOT_PCIE1] = "Slot 1",
- [SLOT_PCIE2] = "Slot 2",
- [SLOT_PCIE3] = "Slot 3",
- [SLOT_PCIE4] = "Slot 4",
- [SLOT_PCIE5] = "Mini-PCIe",
- [SLOT_SATA1] = "SATA 1",
- [SLOT_SATA2] = "SATA 2",
-};
-
-/*
- * This array maps a given SERDES configuration and SERDES device to the PCI or
- * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
- */
-static u8 serdes_dev_slot[][SATA2 + 1] = {
- [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
- [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
- [PCIE2] = SLOT_PCIE5 },
- [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
- [PCIE2] = SLOT_PCIE3,
- [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
- [PCIE2] = SLOT_PCIE3 },
- [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
- [PCIE2] = SLOT_PCIE3,
- [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x1c] = { [PCIE1] = SLOT_PCIE1,
- [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
- [0x1f] = { [PCIE1] = SLOT_PCIE1 },
-};
-
-
-/*
- * Returns the name of the slot to which the PCIe or SATA controller is
- * connected
- */
-const char *board_serdes_name(enum srds_prtcl device)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- u32 pordevsr = in_be32(&gur->pordevsr);
- unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- enum slot_id slot = serdes_dev_slot[srds_cfg][device];
- const char *name = slot_names[slot];
-
- if (name)
- return name;
- else
- return "Nothing";
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-/*
- * Initialize on-board and/or PCI Ethernet devices
- *
- * Returns:
- * <0, error
- * 0, no ethernet devices found
- * >0, number of ethernet devices initialized
- */
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- unsigned int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-/**
- * ft_codec_setup - fix up the clock-frequency property of the codec node
- *
- * Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option. If audclk is not specified, then don't write anything
- * to the device tree, because it means that the codec clock is disabled.
- */
-static void ft_codec_setup(void *blob, const char *compatible)
-{
- const char *audclk;
- size_t arglen;
- u32 freq;
-
- audclk = hwconfig_arg("audclk", &arglen);
- if (audclk) {
- if (strncmp(audclk, "11", 2) == 0)
- freq = 11289600;
- else
- freq = 12288000;
-
- do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
- freq, 1);
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- /* Update the WM8776 node's clock frequency property */
- ft_codec_setup(blob, "wlf,wm8776");
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/ngpixis.h"
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const u32 sysclk_tbl[] = {
- 66666000, 7499900, 83332500, 8999900,
- 99999000, 11111000, 12499800, 13333200
-};
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, sys_clk, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- /* Enable the SPI */
- clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-#endif
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#else
- env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-
-
-const static u32 sysclk_tbl[] = {
- 66666000, 7499900, 83332500, 8999900,
- 99999000, 11111000, 12499800, 13333200
-};
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, sys_clk, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
- /* for FPGA */
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0,
- CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* **** - eSDHC/eSPI/NAND boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
- /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_NAND_BASE
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16K, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_P1_TWR
-
-config SYS_BOARD
- default "p1_twr"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "p1_twr"
-
-endif
+++ /dev/null
-P1_TWR BOARD
-M: Xiaobo Xie <xiaobo.xie@nxp.com>
-S: Maintained
-F: board/freescale/p1_twr/
-F: include/configs/p1_twr.h
-F: configs/TWR-P1025_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-
-obj-y += p1_twr.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-/* Fixed sdram init -- doesn't use serial presence detect. */
-phys_size_t fixed_sdram(void)
-{
- sys_info_t sysinfo;
- char buf[32];
- size_t ddr_size;
- fsl_ddr_cfg_regs_t ddr_cfg_regs = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
-#endif
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
- .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
- };
-
- get_sys_info(&sysinfo);
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freq_ddrbus));
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return ddr_size;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_lbc.h>
-#include <asm/mp.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <ioports.h>
-#include <asm/fsl_serdes.h>
-#include <netdev.h>
-
-#define SYSCLK_64 64000000
-#define SYSCLK_66 66666666
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
- unsigned int cpdat_val = 0;
-
- /* Set-up up pin muxing based on board switch settings */
- cpdat_val = par_io[1].cpdat;
-
- /* Check switch setting for SYSCLK select (PB3) */
- if (cpdat_val & 0x10000000)
- return SYSCLK_64;
- else
- return SYSCLK_66;
-
- return 0;
-}
-
-#ifdef CONFIG_QE
-
-#define PCA_IOPORT_I2C_ADDR 0x23
-#define PCA_IOPORT_OUTPUT_CMD 0x2
-#define PCA_IOPORT_CFG_CMD 0x6
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-
-#ifdef CONFIG_TWR_P1025
- /* GPIO */
- {1, 0, 1, 0, 0},
- {1, 18, 1, 0, 0},
-
- /* GPIO for switch options */
- {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
- {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
- {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
- {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
-
- /* QE_MUX_MDC */
- {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
-
- /* QE_MUX_MDIO */
- {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
-
- /* UCC_1_MII */
- {0, 23, 2, 0, 2}, /* CLK12 */
- {0, 24, 2, 0, 1}, /* CLK9 */
- {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
- {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
- {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
- {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
- {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
- {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
- {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
- {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
- {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
- {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
- {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
- {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
- {0, 17, 2, 0, 2}, /* ENET1_CRS */
- {0, 16, 2, 0, 2}, /* ENET1_COL */
-
- /* UCC_5_RMII */
- {1, 11, 2, 0, 1}, /* CLK13 */
- {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
- {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
- {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
- {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
- {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
- {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
- {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
-
- /* TDMA - clock option is configured in OS based on board setting */
- {1, 23, 2, 0, 2}, /* TDMA_TXD */
- {1, 25, 2, 0, 2}, /* TDMA_RXD */
- {1, 26, 1, 0, 2}, /* TDMA_SYNC */
-#endif
-
- {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
-};
-#endif
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
-
- /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-
- return 0;
-}
-
-int checkboard(void)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u8 boot_status;
-
- printf("Board: %s\n", CONFIG_BOARDNAME);
-
- boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
- puts("rom_loc: ");
- if (boot_status == PORBMSR_ROMLOC_NOR)
- puts("nor flash");
- else if (boot_status == PORBMSR_ROMLOC_SDHC)
- puts("sd");
- else
- puts("unknown");
- puts("\n");
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- ccsr_gur_t *gur __attribute__((unused)) =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- printf("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
-#if defined(CONFIG_UEC_ETH)
- /* QE0 and QE3 need to be exposed for UCC1
- * and UCC5 Eth mode (in PMUXCR register).
- * Currently QE/LBC muxed pins assumed to be
- * LBC for U-Boot and PMUXCR updated by OS if required */
-
- uec_standard_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_QE)
-static void fdt_board_fixup_qe_pins(void *blob)
-{
- int node;
-
- if (!hwconfig("qe")) {
- /* For QE and eLBC pins multiplexing,
- * When don't use QE function, remove
- * qe node from dt blob.
- */
- node = fdt_path_offset(blob, "/qe");
- if (node >= 0)
- fdt_del_node(blob, node);
- } else {
- /* For TWR Peripheral Modules - TWR-SER2
- * board only can support Signal Port MII,
- * so delete one UEC node when use MII port.
- */
- if (hwconfig("mii"))
- node = fdt_path_offset(blob, "/qe/ucc@2400");
- else
- node = fdt_path_offset(blob, "/qe/ucc@2000");
- if (node >= 0)
- fdt_del_node(blob, node);
- }
-
- return;
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_QE
- do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
- sizeof("okay"), 0);
-#endif
-#if defined(CONFIG_TWR_P1025)
- fdt_board_fixup_qe_pins(blob);
-#endif
- fsl_fdt_fixup_dr_usb(blob, bd);
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
- /* W**G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI memory 1.5G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O effective: 192K */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#endif
-
-#ifdef CONFIG_SYS_RAMBOOT
- /* *I*G - eSDHC boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
*/
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
SECURE_BOOT
#endif
+++ /dev/null
-if TARGET_T1024QDS
-
-config SYS_BOARD
- default "t102xqds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T102xQDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-T102XQDS BOARD
-#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/t102xqds/
-F: include/configs/T102xQDS.h
-F: configs/T1024QDS_defconfig
-F: configs/T1024QDS_NAND_defconfig
-F: configs/T1024QDS_SDCARD_defconfig
-F: configs/T1024QDS_SPIFLASH_defconfig
-F: configs/T1024QDS_DDR4_defconfig
-F: configs/T1024QDS_SECURE_BOOT_defconfig
-F: configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += t102xqds.o
-obj-y += eth_t102xqds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-T1024 SoC Overview
-------------------
-The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
-combines two or one 64-bit Power Architecture e5500 core respectively with high
-performance datapath acceleration logic, and network peripheral bus interfaces
-required for networking and telecommunications. This processor can be used in
-applications such as enterprise WLAN access points, routers, switches, firewall
-and other packet processing intensive small enterprise and branch office appliances,
-and general-purpose embedded computing. Its high level of integration offers
-significant performance benefits and greatly helps to simplify board design.
-
-
-The T1024 SoC includes the following function and features:
-- two e5500 cores, each with a private 256 KB L2 cache
- - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
- - Three levels of instructions: User, supervisor, and hypervisor
- - Independent boot and reset
- - Secure boot capability
-- 256 KB shared L3 CoreNet platform cache (CPC)
-- Interconnect CoreNet platform
- - CoreNet coherency manager supporting coherent and noncoherent transactions
- with prioritization and bandwidth allocation amongst CoreNet endpoints
- - 150 Gbps coherent read bandwidth
-- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
-- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
- - Packet parsing, classification, and distribution
- - Queue management for scheduling, packet sequencing, and congestion management
- - Cryptography Acceleration (SEC 5.x)
- - IEEE 1588 support
- - Hardware buffer management for buffer allocation and deallocation
- - MACSEC on DPAA-based Ethernet ports
-- Ethernet interfaces
- - Four 1 Gbps Ethernet controllers
-- Parallel Ethernet interfaces
- - Two RGMII interfaces
-- High speed peripheral interfaces
- - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
- - One SATA controller supporting 1.5 and 3.0 Gb/s operation
- - One QSGMII interface
- - Four SGMII interface supporting 1000 Mbps
- - Three SGMII interfaces supporting up to 2500 Mbps
- - 10GbE XFI or 10Base-KR interface
-- Additional peripheral interfaces
- - Two USB 2.0 controllers with integrated PHY
- - SD/eSDHC/eMMC
- - eSPI controller
- - Four I2C controllers
- - Four UARTs
- - Four GPIO controllers
- - Integrated flash controller (IFC)
- - LCD interface (DIU) with 12 bit dual data rate
-- Multicore programmable interrupt controller (PIC)
-- Two 8-channel DMA engines
-- Single source clocking implementation
-- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-- QUICC Engine block
- - 32-bit RISC controller for flexible support of the communications peripherals
- - Serial DMA channel for receive and transmit on all serial channels
- - Two universal communication controllers, supporting TDM, HDLC, and UART
-
-T1023 Personality
-------------------
-T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
-unavailable deep sleep. Rest of the blocks are almost same as T1024.
-Differences between T1024 and T1023
-Feature T1024 T1023
-QUICC Engine: yes no
-DIU: yes no
-Deep Sleep: yes no
-I2C controller: 4 3
-DDR: 64-bit 32-bit
-IFC: 32-bit 28-bit
-
-
-T1024QDS board Overview
------------------------
-- SERDES Connections
- 4 lanes supporting the following:
- - PCI Express: supports Gen 1 and Gen 2
- - SGMII 1G and SGMII 2.5G
- - QSGMII
- - XFI
- - SATA 2.0
- - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
- - Aurora debug with dedicated connectors.
-- DDR Controller
- - Supports up to 1600 MTPS data-rate.
- - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
- - Supports Single-, dual- or quad-rank DIMMs
- - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
-- IFC/Local Bus
- - NAND Flash: 8-bit, async, up to 2GB
- - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- - NOR devices support 8 virtual banks
- - Socketed to allow alternate devices
- - GASIC: Simple (minimal) target within QIXIS FPGA
- - PromJET rapid memory download support
- - IFC Debug/Development card
-- Ethernet
- - Two on-board RGMII 10M/100M/1G ethernet ports.
- - One QSGMII interface
- - Four SGMII interface supporting 1Gbps
- - Three SGMII interfaces supporting 2.5Gbps
- - one 10Gbps XFI or 10Base-KR interface
-- QIXIS System Logic FPGA
- - Manages system power and reset sequencing.
- - Manages the configurations of DUT, board, and clock for dynamic shmoo.
- - Collects V-I-T data in background for code/power profiling.
- - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
- - General fault monitoring and logging.
- - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
-- Clocks
- - System and DDR clock (SYSCLK, DDRCLK).
- - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
- - Software programmable in 1 MHz increments from 1-200 MHz.
- - SERDES clocks
- - Provides clocks to SerDes blocks and slots.
- - 100 MHz, 125 MHz and 156.25 MHz options.
- - Spread-spectrum option for 100 MHz.
-- Power Supplies
- - Dedicated PMBus regulator for VDD and VDDC.
- - Adjustable from 0.7V to 1.3V at 35A
- - VDD can be disabled independanty from VDDC for “deep sleep”.
- - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
- - VTT/MVREF automatically track operating voltage.
- - Dedicated 2.5V VPP supply.
- - Dedicated regulators/filters for AVDD supplies.
- - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
-- Video
- - DIU supports video up to 1280x1024x32 bpp.
- - Chrontel CH7201 for HDMI connection.
- - TI DS90C387R for direct LCD connection.
- - Raw (not encoded) video connector for testing or other encoders.
-- USB
- - Supports two USB 2.0 ports with integrated PHYs.
- - Two type A ports with 5V@1.5A per port.
- - Second port can be converted to OTG mini-AB.
-- SDHC
- For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
- - upport for optional clock feedback paths.
- - Support for optional high-speed voltage translation direction controls.
- - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
- - Support for eMMC memory devices.
-- SPI
- -On-board support of 3 different devices and sizes.
-- Other IO
- - Two Serial ports
- - ProfiBus port
- - Four I2C ports
-
-
-Memory map on T1024QDS
-----------------------
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
-0x0_0000_0000 0x0_ffff_ffff DDR 4GB
-
-
-128MB NOR Flash memory Map
---------------------------
-Start Address End Address Definition Max size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-SerDes clock vs DIP-switch settings
------------------------------------
-SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4]
-0x6F 100MHz 125MHz 1101
-0xD6 100MHz 100MHz 1111
-0x99 156.25MHz 100MHz 1011
-
-
-T1024 Clock frequency
-----------------------
-BIN Core DDR Platform FMan
-Bin1: 1400MHz 1600MT/s 400MHz 700MHz
-Bin2: 1200MHz 1600MT/s 400MHz 600MHz
-Bin3: 1000MHz 1600MT/s 400MHz 500MHz
-
-
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
- a. build NOR boot image
- $ make T1024QDS_defconfig (For DDR3L, by default)
- or make T1024QDS_D4_defconfig (For DDR4)
- $ make
- b. program u-boot.bin image to NOR flash
- => tftp 1000000 u-boot.bin
- => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
-
- Switching between default bank0 and alternate bank4 on NOR flash
- To change boot source to vbank4:
- via software: run command 'qixis_reset altbank' in U-Boot.
- via DIP-switch: set SW6[1:4] = '0100'
-
- To change boot source to vbank0:
- via software: run command 'qixis_reset' in U-Boot.
- via DIP-Switch: set SW6[1:4] = '0000'
-
-2. NAND Boot:
- a. build PBL image for NAND boot
- $ make T1024QDS_NAND_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to NAND flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => nand erase 0 $filesize
- => nand write 1000000 0 $filesize
- set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
-
-3. SPI Boot:
- a. build PBL image for SPI boot
- $ make T1024QDS_SPIFLASH_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to SPI flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => sf probe 0
- => sf erase 0 f0000
- => sf write 1000000 0 $filesize
- set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
- a. build PBL image for SD boot
- $ make T1024QDS_SDCARD_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to SD/MMC card
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => mmc write 1000000 8 0x800
- => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
- => mmc write 1000000 0x820 80
- set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
-
-DIU/QE-TDM/SDXC settings
--------------------
-a) For TDM Riser: set pin_mux=tdm in hwconfig
-b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
-c) For HDMI(DVI): set pin_mux=hdmi in hwconfig
-d) For LCD(DFP): set pin_mux=lcd in hwconfig
-e) For SDXC: set adaptor=sdxc in hwconfig
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area | Address |
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB) |
--------------------------------------------------
-|GD, BD | 0xFFFC8000 (4KB) |
--------------------------------------------------
-|ENV | 0xFFFC9000 (8KB) |
--------------------------------------------------
-|HEAP | 0xFFFCB000 (30KB) |
--------------------------------------------------
-|STACK | 0xFFFD8000 (22KB) |
--------------------------------------------------
-|U-Boot SPL | 0xFFFD8000 (160KB) |
--------------------------------------------------
-
-NAND Flash memory Map on T1024QDS
--------------------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x100000 0x15FFFF U-Boot env 8KB
-0x160000 0x17FFFF FMAN Ucode 128KB
-0x180000 0x19FFFF QE Firmware 128KB
-
-
-SD Card memory Map on T1024QDS
-----------------------------------------------------
-Block #blocks Definition Size
-0x008 2048 U-Boot img 1MB
-0x800 0016 U-Boot env 8KB
-0x820 0256 FMAN Ucode 128KB
-0x920 0256 QE Firmware 128KB
-
-
-SPI Flash memory Map on T1024QDS
-----------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB
-0x100000 0x101FFF U-Boot env 8KB
-0x110000 0x12FFFF FMAN Ucode 128KB
-0x130000 0x14FFFF QE Firmware 128KB
-
-
-For more details, please refer to T1024QDS Reference Manual and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * datarate_mhz_high values need to be in ascending order
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
-#if defined(CONFIG_SYS_FSL_DDR4)
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
-#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
-#else
-#error DDR type not defined
-#endif
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- struct cpu_type *cpu = gd->arch.cpu;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust according to the board ddr freqency and n_banks
- * specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found\n");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
- debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
- debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * rtt and rtt_wr override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-#else
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x5f;
-#endif
-
- /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
- * set DDR bus width to 32bit for T1023
- */
- if (cpu->soc_ver == SVR_T1023)
- popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-
-#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
- /* for DDR bus 32bit test on T1024 */
- popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
- void __iomem *qixis_base = (void *)QIXIS_BASE;
-
- /* does not provide HW signals for power management */
- clrbits_8(qixis_base + 0x21, 0x2);
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
- fsl_dp_resume();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t102xqds_qixis.h"
-
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII1 0
-#define EMI1_RGMII2 1
-#define EMI1_SLOT1 2
-#define EMI1_SLOT2 3
-#define EMI1_SLOT3 4
-#define EMI1_SLOT4 5
-#define EMI1_SLOT5 6
-#define EMI2 7
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
- "T1024QDS_MDIO_RGMII1",
- "T1024QDS_MDIO_RGMII2",
- "T1024QDS_MDIO_SLOT1",
- "T1024QDS_MDIO_SLOT2",
- "T1024QDS_MDIO_SLOT3",
- "T1024QDS_MDIO_SLOT4",
- "T1024QDS_MDIO_SLOT5",
- "T1024QDS_MDIO_10GC",
- "NULL",
-};
-
-/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
-static u8 lane_to_slot[] = {2, 3, 4, 5};
-
-static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name;
-
- if (muxval > EMI2)
- return NULL;
-
- name = t1024qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-struct t1024qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void t1024qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
-
- if (muxval < 7) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t1024qds_mdio *priv = bus->priv;
-
- t1024qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t1024qds_mdio *priv = bus->priv;
-
- t1024qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t1024qds_mdio_reset(struct mii_dev *bus)
-{
- struct t1024qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t1024qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t1024qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate t1024qds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate t1024qds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t1024qds_mdio_read;
- bus->write = t1024qds_mdio_write;
- bus->reset = t1024qds_mdio_reset;
- strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
- return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- struct fixed_link f_link;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
- if (port == FM1_DTSEC3) {
- fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "rgmii");
- fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
- }
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- if (port == FM1_DTSEC1) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii_vsc8234_phy_s5");
- } else if (port == FM1_DTSEC2) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii_vsc8234_phy_s4");
- }
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
- if (port == FM1_DTSEC3) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii_aqr105_phy_s3");
- }
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
- switch (port) {
- case FM1_DTSEC1:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
- break;
- case FM1_DTSEC2:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
- break;
- case FM1_DTSEC3:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
- break;
- case FM1_DTSEC4:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
- break;
- default:
- break;
- }
- fdt_delprop(fdt, offset, "phy-connection-type");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "qsgmii");
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
- /* XFI interface */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for XFI */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}
-
-/*
- * This function reads RCW to check if Serdes1{A:D} is configured
- * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- switch (srds_s1) {
- case 0x46:
- case 0x47:
- lane_to_slot[1] = 2;
- break;
- default:
- break;
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- initialize_lane_to_slot();
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
-
- switch (srds_s1) {
- case 0xd5:
- case 0xd6:
- /* QSGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, 0x8);
- fm_info_set_phy_address(FM1_DTSEC2, 0x9);
- fm_info_set_phy_address(FM1_DTSEC3, 0xa);
- fm_info_set_phy_address(FM1_DTSEC4, 0xb);
- break;
- case 0x95:
- case 0x99:
- /*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks the
- * XAUI card is used for the XFI MAC, which will cause error.
- */
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x6f:
- /* SGMII in Slot3, Slot4, Slot5 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x7f:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
- break;
- case 0x47:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x77:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
- break;
- case 0x5a:
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x6a:
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x5b:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x6b:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- default:
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_SGMII) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_2500_FM1_DTSEC1 + idx);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_A);
- }
-
- if (lane < 0)
- break;
-
- slot = lane_to_slot[lane];
- debug("FM1@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
-
- switch (slot) {
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 5:
- mdio_mux[i] = EMI1_SLOT5;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- if (i == FM1_DTSEC3)
- mdio_mux[i] = EMI1_RGMII2;
- else if (i == FM1_DTSEC4)
- mdio_mux[i] = EMI1_RGMII1;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- idx = i - FM1_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XFI_FM1_MAC1 + idx);
- if (lane < 0)
- break;
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/qixis.h"
-#include "t102xqds_qixis.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
- /*
- * There is T1040 SoC issue where NOR, FPGA are inaccessible during
- * NAND boot because IFC signals > IFC_AD7 are not enabled.
- * This workaround changes RCW source to make all signals enabled.
- */
- u32 porsr1, pinctl;
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
-#endif
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#if defined(CONFIG_SPL_MMC_BOOT)
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
- puts("\nNAND boot...\n");
-#endif
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
+++ /dev/null
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 e8104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
+++ /dev/null
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
+++ /dev/null
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 68104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
+++ /dev/null
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 58104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "t102xqds.h"
-#include "t102xqds_qixis.h"
-#include "../common/sleep.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- char buf[64];
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *const freq[] = {"100", "125", "156.25", "100.0"};
- int clock;
- u8 sw = QIXIS_READ(arch);
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
- printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
-#ifdef CONFIG_SDCARD
- puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
- puts("SPI\n");
-#else
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("PromJet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else if (sw == 0x15)
- printf("IFC Card\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-#endif
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n" at the end */
- printf(" on %s", qixis_read_time(buf));
-
- puts("SERDES Reference: ");
- sw = QIXIS_READ(brdcfg[2]);
- clock = (sw >> 6) & 3;
- printf("Clock1=%sMHz ", freq[clock]);
- clock = (sw >> 4) & 3;
- printf("Clock2=%sMHz\n", freq[clock]);
-
- return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-static int board_mux_lane_to_slot(void)
-{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1;
- u8 brdcfg9;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-
- brdcfg9 = QIXIS_READ(brdcfg[9]);
- QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
-
- switch (srds_prtcl_s1) {
- case 0:
- /* SerDes1 is not enabled */
- break;
- case 0xd5:
- case 0x5b:
- case 0x6b:
- case 0x77:
- case 0x6f:
- case 0x7f:
- QIXIS_WRITE(brdcfg[12], 0x8c);
- break;
- case 0x40:
- QIXIS_WRITE(brdcfg[12], 0xfc);
- break;
- case 0xd6:
- case 0x5a:
- case 0x6a:
- case 0x56:
- QIXIS_WRITE(brdcfg[12], 0x88);
- break;
- case 0x47:
- QIXIS_WRITE(brdcfg[12], 0xcc);
- break;
- case 0x46:
- QIXIS_WRITE(brdcfg[12], 0xc8);
- break;
- case 0x95:
- case 0x99:
- brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
- QIXIS_WRITE(brdcfg[9], brdcfg9);
- QIXIS_WRITE(brdcfg[12], 0x8c);
- break;
- case 0x116:
- QIXIS_WRITE(brdcfg[12], 0x00);
- break;
- case 0x115:
- case 0x119:
- case 0x129:
- case 0x12b:
- /* Aurora, PCIe, SGMII, SATA */
- QIXIS_WRITE(brdcfg[12], 0x04);
- break;
- default:
- printf("WARNING: unsupported for SerDes Protocol %d\n",
- srds_prtcl_s1);
- return -1;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_ARCH_T1024
-static void board_mux_setup(void)
-{
- u8 brdcfg15;
-
- brdcfg15 = QIXIS_READ(brdcfg[15]);
- brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
-
- if (hwconfig_arg_cmp("pin_mux", "tdm")) {
- /* Route QE_TDM multiplexed signals to TDM Riser slot */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
- QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
- QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
- ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
- } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
- /* to UCC (ProfiBus) interface */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
- } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
- /* to DVI (HDMI) encoder */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
- } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
- /* to DFP (LCD) encoder */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
- BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
- }
-
- if (hwconfig_arg_cmp("adaptor", "sdxc"))
- /* Route SPI_CS multiplexed signals to SD slot */
- QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
- ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
-}
-#endif
-
-void board_retimer_ds125df111_init(void)
-{
- u8 reg;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int ret, bus_num = 0;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret)
- goto failed;
-
- /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
- reg = I2C_MUX_CH7;
- dm_i2c_write(dev, 0, ®, 1);
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
- 1, &dev);
- if (ret)
- goto failed;
-
- reg = I2C_MUX_CH5;
- dm_i2c_write(dev, 0, ®, 1);
-
- /* Access to Control/Shared register */
- ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
- 1, &dev);
- if (ret)
- goto failed;
- reg = 0x0;
- dm_i2c_write(dev, 0xff, ®, 1);
-
- /* Read device revision and ID */
- dm_i2c_read(dev, 1, ®, 1);
- debug("Retimer version id = 0x%x\n", reg);
-
- /* Enable Broadcast */
- reg = 0x0c;
- dm_i2c_write(dev, 0xff, ®, 1);
-
- /* Reset Channel Registers */
- dm_i2c_read(dev, 0, ®, 1);
- reg |= 0x4;
- dm_i2c_write(dev, 0, ®, 1);
-
- /* Enable override divider select and Enable Override Output Mux */
- dm_i2c_read(dev, 9, ®, 1);
- reg |= 0x24;
- dm_i2c_write(dev, 9, ®, 1);
-
- /* Select VCO Divider to full rate (000) */
- dm_i2c_read(dev, 0x18, ®, 1);
- reg &= 0x8f;
- dm_i2c_write(dev, 0x18, ®, 1);
-
- /* Select active PFD MUX input as re-timed data (001) */
- dm_i2c_read(dev, 0x1e, ®, 1);
- reg &= 0x3f;
- reg |= 0x20;
- dm_i2c_write(dev, 0x1e, ®, 1);
-
- /* Set data rate as 10.3125 Gbps */
- reg = 0x0;
- dm_i2c_write(dev, 0x60, ®, 1);
- reg = 0xb2;
- dm_i2c_write(dev, 0x61, ®, 1);
- reg = 0x90;
- dm_i2c_write(dev, 0x62, ®, 1);
- reg = 0xb3;
- dm_i2c_write(dev, 0x63, ®, 1);
- reg = 0xcd;
- dm_i2c_write(dev, 0x64, ®, 1);
- return;
-
-failed:
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return;
-#else
- /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
- reg = I2C_MUX_CH7;
- i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
- reg = I2C_MUX_CH5;
- i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
-
- /* Access to Control/Shared register */
- reg = 0x0;
- i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
-
- /* Read device revision and ID */
- i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
- debug("Retimer version id = 0x%x\n", reg);
-
- /* Enable Broadcast */
- reg = 0x0c;
- i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
-
- /* Reset Channel Registers */
- i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
- reg |= 0x4;
- i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
-
- /* Enable override divider select and Enable Override Output Mux */
- i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
- reg |= 0x24;
- i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
-
- /* Select VCO Divider to full rate (000) */
- i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
- reg &= 0x8f;
- i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
-
- /* Select active PFD MUX input as re-timed data (001) */
- i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
- reg &= 0x3f;
- reg |= 0x20;
- i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
-
- /* Set data rate as 10.3125 Gbps */
- reg = 0x0;
- i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
- reg = 0xb2;
- i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
- reg = 0x90;
- i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
- reg = 0xb3;
- i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
- reg = 0xcd;
- i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
-#endif
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
- board_mux_lane_to_slot();
- board_retimer_ds125df111_init();
-
- /* Increase IO drive strength to address FCS error on RGMII */
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_64:
- return 64000000;
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-#define NUM_SRDS_PLL 2
-int misc_init_r(void)
-{
-#ifdef CONFIG_ARCH_T1024
- board_mux_setup();
-#endif
- return 0;
-}
-
-void fdt_fixup_spi_mux(void *blob)
-{
- int nodeoff = 0;
-
- if (hwconfig_arg_cmp("pin_mux", "tdm")) {
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "eon,en25s64")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
- } else {
- /* remove tdm node */
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "maxim,ds26522")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
- fdt_fixup_fman_ethernet(blob);
-#endif
- fdt_fixup_board_enet(blob);
-#endif
- fdt_fixup_spi_mux(blob);
-
- return 0;
-}
-
-void qixis_dump_switch(void)
-{
- int i, nr_of_cfgsw;
-
- QIXIS_WRITE(cms[0], 0x00);
- nr_of_cfgsw = QIXIS_READ(cms[1]);
-
- puts("DIP switch settings dump:\n");
- for (i = 1; i <= nr_of_cfgsw; i++) {
- QIXIS_WRITE(cms[0], i);
- printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __T102x_QDS_H__
-#define __T102x_QDS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch, int bus_num);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1024QDS_QIXIS_H__
-#define __T1024QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T1024/T1023 QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
-#define BRDCFG5_IMX_MASK 0xC0
-#define BRDCFG5_IMX_DIU 0x80
-
-#define BRDCFG5_SPIRTE_MASK 0x07
-#define BRDCFG5_SPIRTE_TDM 0x01
-#define BRDCFG5_SPIRTE_SDHC 0x02
-#define BRDCFG9_XFI_TX_DISABLE 0x10
-
-/* BRDCFG13[0:5] TDM configuration and setup */
-#define BRDCFG13_TDM_MASK 0xfc
-#define BRDCFG13_TDM_INTERFACE 0x37
-#define BRDCFG13_HDLC_LOOPBACK 0x29
-#define BRDCFG13_TDM_LOOPBACK 0x31
-
-/* BRDCFG15[3] controls LCD Panel Powerdown */
-#define BRDCFG15_LCDFM 0x20
-#define BRDCFG15_LCDPD 0x10
-#define BRDCFG15_LCDPD_MASK 0x10
-#define BRDCFG15_LCDPD_ENABLED 0x00
-
-/* BRDCFG15[6:7] controls DIU MUX selction*/
-#define BRDCFG15_DIUSEL_MASK 0x03
-#define BRDCFG15_DIUSEL_HDMI 0x00
-#define BRDCFG15_DIUSEL_LCD 0x01
-#define BRDCFG15_DIUSEL_UCC 0x02
-#define BRDCFG15_DIUSEL_TDM 0x03
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-#define QIXIS_SYSCLK_64 0x8
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-
-#define QIXIS_SRDS1CLK_122 0x5a
-#define QIXIS_SRDS1CLK_125 0x5e
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
- * SRAM is at 0xfffc0000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 12, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 13, BOOKE_PAGESZ_1G, 1)
-#endif
- /* entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so if needed more, will use entry 16 later.
- */
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_T1040QDS
-
-config SYS_BOARD
- default "t1040qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T1040QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-T1040QDS BOARD
-M: Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S: Maintained
-F: board/freescale/t1040qds/
-F: include/configs/T1040QDS.h
-F: configs/T1040QDS_defconfig
-F: configs/T1040QDS_DDR4_defconfig
-
-T1040QDS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T1040QDS_SECURE_BOOT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y += t1040qds.o
-obj-y += ddr.o
-obj-$(CONFIG_PCI) += pci.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += eth.o
-obj-y += diu.o
+++ /dev/null
-Overview
---------
-The T1040QDS is a Freescale reference board that hosts the T1040 SoC
-(and variants).
-
-T1040 SoC Overview
-------------------
-The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
-processor cores with high-performance data path acceleration architecture
-and network peripheral interfaces required for networking & telecommunications.
-
-The T1040/T1042 SoC includes the following function and features:
-
- - Four e5500 cores, each with a private 256 KB L2 cache
- - 256 KB shared L3 CoreNet platform cache (CPC)
- - Interconnect CoreNet platform
- - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- for the following functions:
- - Packet parsing, classification, and distribution
- - Queue management for scheduling, packet sequencing, and congestion
- management
- - Cryptography Acceleration (SEC 5.0)
- - RegEx Pattern Matching Acceleration (PME 2.2)
- - IEEE Std 1588 support
- - Hardware buffer management for buffer allocation and deallocation
- - Ethernet interfaces
- - Integrated 8-port Gigabit Ethernet switch (T1040 only)
- - Four 1 Gbps Ethernet controllers
- - Two RGMII interfaces or one RGMII and one MII interfaces
- - High speed peripheral interfaces
- - Four PCI Express 2.0 controllers running at up to 5 GHz
- - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
- - Upto two QSGMII interface
- - Upto six SGMII interface supporting 1000 Mbps
- - One SGMII interface supporting upto 2500 Mbps
- - Additional peripheral interfaces
- - Two USB 2.0 controllers with integrated PHY
- - SD/eSDHC/eMMC
- - eSPI controller
- - Four I2C controllers
- - Four UARTs
- - Four GPIO controllers
- - Integrated flash controller (IFC)
- - LCD and HDMI interface (DIU) with 12 bit dual data rate
- - TDM interface
- - Multicore programmable interrupt controller (PIC)
- - Two 8-channel DMA engines
- - Single source clocking implementation
- - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-
- T1040QDS board Overview
- -----------------------
- - SERDES Connections, 8 lanes supporting:
- — PCI Express: supporting Gen 1 and Gen 2;
- — SGMII
- — QSGMII
- — SATA 2.0
- — Aurora debug with dedicated connectors (T1040 only)
- - DDR Controller
- - Supports rates of up to 1600 MHz data-rate
- - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- -IFC/Local Bus
- - NAND flash: 8-bit, async, up to 2GB.
- - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- - GASIC: Simple (minimal) target within Qixis FPGA
- - PromJET rapid memory download support
- - Ethernet
- - Two on-board RGMII 10/100/1G ethernet ports.
- - PHY #0 remains powered up during deep-sleep (T1040 only)
- - QIXIS System Logic FPGA
- - Clocks
- - System and DDR clock (SYSCLK, “DDRCLK”)
- - SERDES clocks
- - Power Supplies
- - Video
- - DIU supports video at up to 1280x1024x32bpp
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- — Two type A ports with 5V@1.5A per port.
- — Second port can be converted to OTG mini-AB
- - SDHC
- - SDHC port connects directly to an adapter card slot, featuring:
- - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
- — Supporting eMMC memory devices
- - SPI
- - On-board support of 3 different devices and sizes
- - Other IO
- - Two Serial ports
- - ProfiBus port
- - Four I2C ports
-
-Memory map on T1040QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
-0x0_0000_0000 0x0_ffff_ffff DDR 2GB
-
-
-NOR Flash memory Map on T1040QDS
---------------------------------
- Start End Definition Size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to T1040QDS
-
-1. U-Boot environment variable hwconfig
- The default hwconfig is:
- hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
- dr_mode=host,phy_type=utmi
- Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
- fsl_fman_ucode_t1040.bin
-
-3. Switching to alternate bank
- Commands for switching to alternate bank.
-
- 1. To change from vbank0 to vbank4
- => qixis_reset altbank (it will boot using vbank4)
-
- 2.To change from vbank4 to vbank0
- => qixis reset (it will boot using vbank0)
-
-T1040 Personality
---------------------
-
-T1022 Personality
---------------------
-T1022 is a reduced personality of T1040 with less core/clusters.
-
-T1042 Personality
---------------------
-T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
-Ethernet switch. Rest of the blocks are same as T1040
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found\n");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * rtt and rtt_wr override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x69;
-#else
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
- void __iomem *qixis_base = (void *)QIXIS_BASE;
-
- /* does not provide HW signals for power management */
- clrbits_8(qixis_base + 0x21, 0x2);
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....using SPD\n");
-
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
- fsl_dp_resume();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
-#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
-#else
-#error DDR type not defined
-#endif
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include <fsl_diu_fb.h>
-#include "../common/qixis.h"
-#include "../common/diu_ch7301.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F 0x10000000
-#define AD_ALPHA_C_SHIFT 25
-#define AD_BLUE_C_SHIFT 23
-#define AD_GREEN_C_SHIFT 21
-#define AD_RED_C_SHIFT 19
-#define AD_PIXEL_S_SHIFT 16
-#define AD_COMP_3_SHIFT 12
-#define AD_COMP_2_SHIFT 8
-#define AD_COMP_1_SHIFT 4
-#define AD_COMP_0_SHIFT 0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
- unsigned long speed_ccb, temp;
- u32 pixval;
- int ret = 0;
- speed_ccb = get_bus_freq(0);
- temp = 1000000000 / pixclock;
- temp *= 1000;
- pixval = speed_ccb / temp;
-
- /* Program HDMI encoder */
- /* Switch channel to DIU */
- select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
-
- /* Set dispaly encoder */
- ret = diu_set_dvi_encoder(temp);
- if (ret) {
- puts("Failed to set DVI encoder\n");
- return;
- }
-
- /* Switch channel to default */
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
- /* Program pixel clock */
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
- ((pixval << PXCK_BITS_START) & PXCK_MASK));
- /* enable clock*/
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
- ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
- u32 pixel_format;
- u8 sw;
-
- /*Route I2C4 to DIU system as HSYNC/VSYNC*/
- sw = QIXIS_READ(brdcfg[5]);
- QIXIS_WRITE(brdcfg[5],
- ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
-
- /*Configure Display ouput port as HDMI*/
- sw = QIXIS_READ(brdcfg[15]);
- QIXIS_WRITE(brdcfg[15],
- ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
- | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
-
- pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
- (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
- (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
- (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
- (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
- printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
-
-
- return fsl_diu_init(xres, yres, pixel_format, 0);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY connected to
- * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
- * PHY or by the standard four-port SGMII riser card (VSC).
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-#include <vsc9953.h>
-
-#include "../common/fman.h"
-#include "../common/qixis.h"
-
-#include "t1040qds_qixis.h"
-
-#ifdef CONFIG_FMAN_ENET
- /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
- * Bank 1 -> Lanes A, B, C, D
- * Bank 2 -> Lanes E, F, G, H
- */
-
- /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
- * means that the mapping must be determined dynamically, or that the lane
- * maps to something other than a board slot.
- */
-static u8 lane_to_slot[] = {
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
- * housed.
- */
-static int riser_phy_addr[] = {
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/* Slot2 does not have EMI connections */
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII0 0
-#define EMI1_RGMII1 1
-#define EMI1_SLOT1 2
-#define EMI1_SLOT3 3
-#define EMI1_SLOT4 4
-#define EMI1_SLOT5 5
-#define EMI1_SLOT6 6
-#define EMI1_SLOT7 7
-#define EMI2 8
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
- "T1040_QDS_MDIO0",
- "T1040_QDS_MDIO1",
- "T1040_QDS_MDIO2",
- "T1040_QDS_MDIO3",
- "T1040_QDS_MDIO4",
- "T1040_QDS_MDIO5",
- "T1040_QDS_MDIO6",
- "T1040_QDS_MDIO7",
-};
-
-struct t1040_qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = t1040_qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-static void t1040_qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
- if (muxval <= 7) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t1040_qds_mdio *priv = bus->priv;
-
- t1040_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t1040_qds_mdio *priv = bus->priv;
-
- t1040_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t1040_qds_mdio_reset(struct mii_dev *bus)
-{
- struct t1040_qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t1040_qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate t1040_qds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate t1040_qds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t1040_qds_mdio_read;
- bus->write = t1040_qds_mdio_write;
- bus->reset = t1040_qds_mdio_reset;
- strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the T1040QDS board the mapping is controlled by ?? register.
- */
-static void initialize_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
- >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- QIXIS_WRITE(cms[0], 0x07);
-
- switch (serdes1_prtcl) {
- case 0x60:
- case 0x66:
- case 0x67:
- case 0x69:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 6;
- lane_to_slot[3] = 5;
- break;
- case 0x86:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- break;
- case 0x87:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- lane_to_slot[7] = 7;
- break;
- case 0x89:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- lane_to_slot[6] = 7;
- lane_to_slot[7] = 7;
- break;
- case 0x8d:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- lane_to_slot[5] = 3;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0x8F:
- case 0x85:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 6;
- lane_to_slot[3] = 5;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0xA5:
- lane_to_slot[1] = 7;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0xA7:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 6;
- lane_to_slot[3] = 5;
- lane_to_slot[7] = 7;
- break;
- case 0xAA:
- lane_to_slot[1] = 7;
- lane_to_slot[6] = 7;
- lane_to_slot[7] = 7;
- break;
- case 0x40:
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- break;
- default:
- printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- phy_interface_t intf = fm_info_get_enet_if(port);
- char phy[16];
-
- /* The RGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_RGMII) {
- sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
-
- /* The SGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_SGMII) {
- int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
- + port);
- u8 slot;
- if (lane < 0)
- return;
- slot = lane_to_slot[lane];
- if (slot) {
- /* Slot housing a SGMII riser card */
- sprintf(phy, "phy_s%x_%02x", slot,
- (fm_info_get_phy_address(port - FM1_DTSEC1)-
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- int i, lane, idx;
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
-
- switch (mdio_mux[i]) {
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- break;
- case EMI1_SLOT5:
- fdt_status_okay_by_alias(fdt, "emi1_slot5");
- break;
- case EMI1_SLOT6:
- fdt_status_okay_by_alias(fdt, "emi1_slot6");
- break;
- case EMI1_SLOT7:
- fdt_status_okay_by_alias(fdt, "emi1_slot7");
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- if (i == FM1_DTSEC4)
- fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
-
- if (i == FM1_DTSEC5)
- fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
- break;
- default:
- break;
- }
- }
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-static void set_brdcfg9_for_gtx_clk(void)
-{
- u8 brdcfg9;
- brdcfg9 = QIXIS_READ(brdcfg[9]);
-/* Initializing EPHY2 clock to RGMII mode */
- brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
- brdcfg9 |= (BRDCFG9_EPHY2_VAL);
- QIXIS_WRITE(brdcfg[9], brdcfg9);
-}
-
-void t1040_handle_phy_interface_sgmii(int i)
-{
- int lane, idx, slot;
- idx = i - FM1_DTSEC1;
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
-
- if (lane < 0)
- return;
- slot = lane_to_slot[lane];
-
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 3:
- if (FM1_DTSEC4 == i)
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- if (FM1_DTSEC5 == i)
- fm_info_set_phy_address(i, riser_phy_addr[1]);
-
- mdio_mux[i] = EMI1_SLOT3;
-
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 5:
- /* Slot housing a SGMII riser card? */
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- mdio_mux[i] = EMI1_SLOT5;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 6:
- /* Slot housing a SGMII riser card? */
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- mdio_mux[i] = EMI1_SLOT6;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 7:
- if (FM1_DTSEC1 == i)
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- if (FM1_DTSEC2 == i)
- fm_info_set_phy_address(i, riser_phy_addr[1]);
- if (FM1_DTSEC3 == i)
- fm_info_set_phy_address(i, riser_phy_addr[2]);
- if (FM1_DTSEC5 == i)
- fm_info_set_phy_address(i, riser_phy_addr[3]);
-
- mdio_mux[i] = EMI1_SLOT7;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-void t1040_handle_phy_interface_rgmii(int i)
-{
- fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
- CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
- EMI1_RGMII0;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info memac_mdio_info;
- unsigned int i;
-#ifdef CONFIG_VSC9953
- int lane;
- int phy_addr;
- phy_interface_t phy_int;
- struct mii_dev *bus;
-#endif
-
- printf("Initializing Fman\n");
- set_brdcfg9_for_gtx_clk();
-
- initialize_lane_to_slot();
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
- memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fm_memac_mdio_init(bis, &memac_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
-
- /*
- * Program on board RGMII PHY addresses. If the SGMII Riser
- * card used, we'll override the PHY address later. For any DTSEC that
- * is RGMII, we'll also override its PHY address later. We assume that
- * DTSEC4 and DTSEC5 are used for RGMII.
- */
- fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_QSGMII:
- fm_info_set_mdio(i, NULL);
- break;
- case PHY_INTERFACE_MODE_SGMII:
- t1040_handle_phy_interface_sgmii(i);
- break;
-
- case PHY_INTERFACE_MODE_RGMII:
- /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
- t1040_handle_phy_interface_rgmii(i);
- break;
- default:
- break;
- }
- }
-
-#ifdef CONFIG_VSC9953
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- lane = -1;
- phy_addr = 0;
- phy_int = PHY_INTERFACE_MODE_NONE;
- switch (i) {
- case 0:
- case 1:
- case 2:
- case 3:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
- /* PHYs connected over QSGMII */
- if (lane >= 0) {
- phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
- i;
- phy_int = PHY_INTERFACE_MODE_QSGMII;
- break;
- }
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_SW1_MAC1 + i);
-
- if (lane < 0)
- break;
-
- /* PHYs connected over QSGMII */
- if (i != 3 || lane_to_slot[lane] == 7)
- phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
- + i;
- else
- phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
- phy_int = PHY_INTERFACE_MODE_SGMII;
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
- /* PHYs connected over QSGMII */
- if (lane >= 0) {
- phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
- i - 4;
- phy_int = PHY_INTERFACE_MODE_QSGMII;
- break;
- }
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_SW1_MAC1 + i);
- /* PHYs connected over SGMII */
- if (lane >= 0) {
- phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
- + i - 3;
- phy_int = PHY_INTERFACE_MODE_SGMII;
- }
- break;
- case 8:
- if (serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1) < 0)
- /* FM1@DTSEC1 is connected to SW1@PORT8 */
- vsc9953_port_enable(i);
- break;
- case 9:
- if (serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC2) < 0) {
- /* Enable L2 On MAC2 using SCFG */
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)
- CONFIG_SYS_MPC85xx_SCFG;
-
- out_be32(&scfg->esgmiiselcr,
- in_be32(&scfg->esgmiiselcr) |
- (0x80000000));
- vsc9953_port_enable(i);
- }
- break;
- }
-
- if (lane >= 0) {
- bus = mii_dev_for_muxval(lane_to_slot[lane]);
- vsc9953_port_info_set_mdio(i, bus);
- vsc9953_port_enable(i);
- }
- vsc9953_port_info_set_phy_address(i, phy_addr);
- vsc9953_port_info_set_phy_int(i, phy_int);
- }
-
-#endif
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
+++ /dev/null
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cf0 00000000
-09000cf4 fffc0000
-09000cf8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
+++ /dev/null
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0a10000c 0c000000 00000000 00000000
-66000002 00000000 fc027000 01000000
-00000000 00000000 00000000 00030810
-00000000 03fc500f 00000000 00000000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/sleep.h"
-#include "../common/qixis.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *const freq[] = {"100", "125", "156.25", "161.13",
- "122.88", "122.88", "122.88"};
- int clock;
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("PromJet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else if (sw == 0x15)
- printf("IFCCard\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n" at the end */
- printf(" on %s", qixis_read_time(buf));
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference: ");
- sw = QIXIS_READ(brdcfg[2]);
- clock = (sw >> 6) & 3;
- printf("Clock1=%sMHz ", freq[clock]);
- clock = (sw >> 4) & 3;
- printf("Clock2=%sMHz\n", freq[clock]);
-
- return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-static void qe_board_setup(void)
-{
- u8 brdcfg15, brdcfg9;
-
- if (hwconfig("qe") && hwconfig("tdm")) {
- brdcfg15 = QIXIS_READ(brdcfg[15]);
- /*
- * TDMRiser uses QE-TDM
- * Route QE_TDM signals to TDM Riser slot
- */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
- } else if (hwconfig("qe") && hwconfig("uart")) {
- brdcfg15 = QIXIS_READ(brdcfg[15]);
- brdcfg9 = QIXIS_READ(brdcfg[9]);
- /*
- * Route QE_TDM signals to UCC
- * ProfiBus controlled by UCC3
- */
- brdcfg15 &= 0xfc;
- QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
- QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
- }
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_64:
- return 64000000;
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-#define NUM_SRDS_BANKS 2
-int misc_init_r(void)
-{
- u8 sw;
- serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 actual[NUM_SRDS_BANKS] = { 0 };
- int i;
-
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- unsigned int clock = (sw >> (6 - 2 * i)) & 3;
- switch (clock) {
- case 0:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 2:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- }
- }
-
- puts("SerDes1");
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 pllcr0 = srds_regs->bank[i].pllcr0;
- u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
- i + 1, serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- qe_board_setup();
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
- fdt_fixup_fman_ethernet(blob);
-#endif
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-void qixis_dump_switch(void)
-{
- int i, nr_of_cfgsw;
-
- QIXIS_WRITE(cms[0], 0x00);
- nr_of_cfgsw = QIXIS_READ(cms[1]);
-
- puts("DIP switch settings dump:\n");
- for (i = 1; i <= nr_of_cfgsw; i++) {
- QIXIS_WRITE(cms[0], i);
- printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
- }
-}
-
-int board_need_mem_reset(void)
-{
- return 1;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __T1040_QDS_H__
-#define __T1040_QDS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch, int bus_bum);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1040QDS_QIXIS_H__
-#define __T1040QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T1040QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
-#define BRDCFG5_IMX_MASK 0xC0
-#define BRDCFG5_IMX_DIU 0x80
-
-/* BRDCFG9[2] controls EPHY2 Clock */
-#define BRDCFG9_EPHY2_MASK 0x20
-#define BRDCFG9_EPHY2_VAL 0x00
-
-/* BRDCFG15[3] controls LCD Panel Powerdown*/
-#define BRDCFG15_LCDPD_MASK 0x10
-#define BRDCFG15_LCDPD_ENABLED 0x00
-
-/* BRDCFG15[6:7] controls DIU MUX selction*/
-#define BRDCFG15_DIUSEL_MASK 0x03
-#define BRDCFG15_DIUSEL_HDMI 0x00
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-#define QIXIS_SYSCLK_64 0x8
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-
-#define QIXIS_SRDS1CLK_122 0x5a
-#define QIXIS_SRDS1CLK_125 0x5e
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
- * SRAM is at 0xfffc0000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_T4160QDS || TARGET_T4240QDS
-
-config SYS_BOARD
- default "t4qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T4240QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-T4QDS BOARD
-#M: Shaohui Xie <Shaohui.Xie@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/t4qds/
-F: include/configs/T4240QDS.h
-F: configs/T4160QDS_defconfig
-F: configs/T4160QDS_NAND_defconfig
-F: configs/T4160QDS_SDCARD_defconfig
-F: configs/T4240QDS_defconfig
-F: configs/T4240QDS_NAND_defconfig
-F: configs/T4240QDS_SDCARD_defconfig
-F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
-
-T4160QDS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T4160QDS_SECURE_BOOT_defconfig
-F: configs/T4240QDS_SECURE_BOOT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-$(CONFIG_TARGET_T4160QDS) += t4240qds.o eth.o
-obj-$(CONFIG_TARGET_T4240QDS) += t4240qds.o eth.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
-The T4240QDS is a high-performance computing evaluation, development and test
-platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
-optimized to support the high-bandwidth DDR3 memory ports, as well as the
-highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
-
-Board Features
- SERDES Connections
- 32 lanes grouped into four 8-lane banks
- Two “front side” banks dedicated to Ethernet
- - High-speed crosspoint switch fabric on selected lanes
- - Two PCI Express slots with side-band connector supporting
- - SGMII
- - XAUI
- - HiGig
- - I-pass connectors allow board-to-board and loopback support
- Two “back side” banks dedicated to other protocols
- - High-speed crosspoint switch fabric on all lanes
- - Four PCI Express slots with side-band connector supporting
- - PCI Express 3.0
- - SATA 2.0
- - SRIO 2.0
- - Supports 4X Aurora debug with two connectors
- DDR Controllers
- Three independant 64-bit DDR3 controllers
- Supports rates of 1866 up to 2133 MHz data-rate
- Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
- DDR power supplies 1.5V to all devices with automatic tracking of VTT.
- Power software-switchable to 1.35V if software detects all DDR3LP devices.
- MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
- 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
- increases by 1 clock.
-
- IFC/Local Bus
- NAND flash: 8-bit, async or sync, up to 2GB.
- NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- - NOR devices support 16 virtual banks
- GASIC: Minimal target within Qixis FPGA
- PromJET rapid memory download support
- Address demultiplexing handled within FPGA.
- - Flexible demux allows 8 or 16 bit evaluation.
- IFC Debug/Development card
- - Support for 32-bit devices
- Ethernet
- Support two on-board RGMII 10/100/1G ethernet ports.
- SGMII and XAUI support via SERDES block (see above).
- 1588 support via Symmetricom board.
- QIXIS System Logic FPGA
- Manages system power and reset sequencing
- Manages DUT, board, clock, etc. configuration for dynamic shmoo
- Collects V-I-T data in background for code/power profiling.
- Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
- General fault monitoring and logging
- Runs from ATX “hot” power rails allowing operation while system is off.
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
- - Software selectable in 1MHz increments from 1-200MHz.
- SERDES clocks
- - Provides clocks to all SerDes blocks and slots
- - 100, 125 and 156.25 MHz
- Power Supplies
- Dedicated regulators for VDD
- - Adjustable from (0.7V to 1.3V at 80A
- - Regulators can be controlled by VID and/or software
- Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
- - VTT/MVREF automatically track operating voltage
- Dedicated regulators/filters for AVDD supplies
- Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
- USB
- Supports two USB 2.0 ports with integrated PHYs
- - One type A, one type micro-AB with 1.0A power per port.
- Other IO
- eSDHC/MMC
- - SDHC card slot
- eSPI port
- - High-speed serial flash
- Two Serial port
- Four I2C ports
- XFI
- XFI is supported on T4QDS-XFI board which removed slot3 and routed
- four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
- direct attach cable(copper), the copper cable is used to emulate
- 10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
- another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
- will fixup the dtb accordingly.
- It's used as: fsl_10gkr_copper:<10g_mac_name>
- The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
- do not have to be coexist in hwconfig. If a MAC is listed in the env
- "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
- will be used by default.
- for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in
- hwconfig, then both four XFI ports will use copper cable.
- set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
-
-Memory map
-----------
-The addresses in brackets are physical addresses.
-
-0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
-0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
-0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
-0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
-0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
-0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
-0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
-0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
-0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
-0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
-
-The physical address of the last (boot page translation) varies with the actual DDR size.
-
-Voltage ID and VDD override
---------------------
-T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage
-accordingly. The voltage can also be override by command vdd_override. The
-syntax is
-
-vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
-
-Upon success, the actual voltage will be read back. The value is checked
-for safety and any invalid value will not adjust the voltage.
-
-Another way to override VDD is to use environmental variable, in case of using
-command is too late for some debugging. The syntax is
-
-setenv t4240qds_vdd_mv <voltage in mV>
-saveenv
-reset
-
-The override voltage takes effect when booting.
-
-Note: voltage adjustment needs to be done step by step. Changing voltage too
-rapidly may cause current surge. The voltage stepping is done by software.
-Users can set the final voltage directly.
-
-2-stage NAND/SD boot loader
--------------------------------
-PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
-SPL further initialise DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area | Address |
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB) |
--------------------------------------------------
-|GD, BD | 0xFFFC8000 (4KB) |
--------------------------------------------------
-|ENV | 0xFFFC9000 (8KB) |
--------------------------------------------------
-|HEAP | 0xFFFCB000 (50KB) |
--------------------------------------------------
-|STACK | 0xFFFD8000 (22KB) |
--------------------------------------------------
-|U-Boot SPL | 0xFFFD8000 (160KB) |
--------------------------------------------------
-
-NAND Flash memory Map on T4QDS
---------------------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB
-0x140000 0x15FFFF U-Boot env 128KB
-0x160000 0x17FFFF FMAN Ucode 128KB
-
-Micro SD Card memory Map on T4QDS
-----------------------------------------------------
-Block #blocks Definition Size
-0x008 2048 U-Boot img 1MB
-0x800 0016 U-Boot env 8KB
-0x820 0128 FMAN ucode 64KB
-
-Switch Settings: (ON is 1, OFF is 0)
-===============
-NAND boot SW setting:
-SW1[1:8] = 10000010
-SW2[1.1] = 0
-SW6[1:4] = 1001
-
-SD boot SW setting:
-SW1[1:8] = 00100000
-SW2[1.1] = 0
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[0];
- else
- pbsp = udimms[0];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x63;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....using SPD\n");
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
- {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
-};
-
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include <linux/libfdt.h>
-
-#include "t4240qds_qixis.h"
-
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII 0
-#define EMI1_SLOT1 1
-#define EMI1_SLOT2 2
-#define EMI1_SLOT3 3
-#define EMI1_SLOT4 4
-#define EMI1_SLOT5 5
-#define EMI1_SLOT7 7
-#define EMI2 8
-/* Slot6 and Slot8 do not have EMI connections */
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char *mdio_names[] = {
- "T4240QDS_MDIO0",
- "T4240QDS_MDIO1",
- "T4240QDS_MDIO2",
- "T4240QDS_MDIO3",
- "T4240QDS_MDIO4",
- "T4240QDS_MDIO5",
- "NULL",
- "T4240QDS_MDIO7",
- "T4240QDS_10GC",
-};
-
-static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
-static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
-static u8 slot_qsgmii_phyaddr[5][4] = {
- {0, 0, 0, 0},/* not used, to make index match slot No. */
- {0, 1, 2, 3},
- {4, 5, 6, 7},
- {8, 9, 0xa, 0xb},
- {0xc, 0xd, 0xe, 0xf},
-};
-static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
-
-static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = t4240qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-struct t4240qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void t4240qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
- if ((muxval < 6) || (muxval == 7)) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t4240qds_mdio *priv = bus->priv;
-
- t4240qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t4240qds_mdio *priv = bus->priv;
-
- t4240qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t4240qds_mdio_reset(struct mii_dev *bus)
-{
- struct t4240qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t4240qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t4240qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate T4240QDS MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate T4240QDS private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t4240qds_mdio_read;
- bus->write = t4240qds_mdio_write;
- bus->reset = t4240qds_mdio_reset;
- strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
-{
- int interface = fm_info_get_enet_if(port);
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
- prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- if (interface == PHY_INTERFACE_MODE_SGMII ||
- interface == PHY_INTERFACE_MODE_QSGMII) {
- switch (port) {
- case FM1_DTSEC1:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy21");
- break;
- case FM1_DTSEC2:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy22");
- break;
- case FM1_DTSEC3:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy23");
- break;
- case FM1_DTSEC4:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy24");
- break;
- case FM1_DTSEC6:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy12");
- break;
- case FM1_DTSEC9:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy14");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii4");
- break;
- case FM1_DTSEC10:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy13");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii3");
- break;
- case FM2_DTSEC1:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy41");
- break;
- case FM2_DTSEC2:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy42");
- break;
- case FM2_DTSEC3:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy43");
- break;
- case FM2_DTSEC4:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy44");
- break;
- case FM2_DTSEC6:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy32");
- break;
- case FM2_DTSEC9:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy34");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii12");
- break;
- case FM2_DTSEC10:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy33");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii11");
- break;
- default:
- break;
- }
- } else if (interface == PHY_INTERFACE_MODE_XGMII &&
- ((prtcl2 == 55) || (prtcl2 == 57))) {
- /*
- * if the 10G is XFI, check hwconfig to see what is the
- * media type, there are two types, fiber or copper,
- * fix the dtb accordingly.
- */
- int media_type = 0;
- struct fixed_link f_link;
- char lane_mode[20] = {"10GBASE-KR"};
- char buf[32] = "serdes-2,";
- int off;
-
- switch (port) {
- case FM1_10GEC1:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi1");
- sprintf(buf, "%s%s%s", buf, "lane-a,",
- (char *)lane_mode);
- }
- break;
- case FM1_10GEC2:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi2");
- sprintf(buf, "%s%s%s", buf, "lane-b,",
- (char *)lane_mode);
- }
- break;
- case FM2_10GEC1:
- if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi3");
- sprintf(buf, "%s%s%s", buf, "lane-d,",
- (char *)lane_mode);
- }
- break;
- case FM2_10GEC2:
- if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi4");
- sprintf(buf, "%s%s%s", buf, "lane-c,",
- (char *)lane_mode);
- }
- break;
- default:
- return;
- }
-
- if (!media_type) {
- /* fixed-link is used for XFI fiber cable */
- fdt_delprop(blob, offset, "phy-handle");
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- fdt_setprop(blob, offset, "fixed-link", &f_link,
- sizeof(f_link));
- } else {
- /* set property for copper cable */
- off = fdt_node_offset_by_compat_reg(blob,
- "fsl,fman-memac-mdio", pa + 0x1000);
- fdt_setprop_string(blob, off, "lane-instance", buf);
- }
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- int i;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
- prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- switch (mdio_mux[i]) {
- case EMI1_SLOT1:
- fdt_status_okay_by_alias(fdt, "emi1_slot1");
- break;
- case EMI1_SLOT2:
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- break;
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- break;
- case EMI1_SLOT4:
- fdt_status_okay_by_alias(fdt, "emi1_slot4");
- break;
- default:
- break;
- }
- break;
- case PHY_INTERFACE_MODE_XGMII:
- /* check if it's XFI interface for 10g */
- if ((prtcl2 == 55) || (prtcl2 == 57)) {
- if (i == FM1_10GEC1 && hwconfig_sub(
- "fsl_10gkr_copper", "fm1_10g1"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio1");
- if (i == FM1_10GEC2 && hwconfig_sub(
- "fsl_10gkr_copper", "fm1_10g2"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio2");
- if (i == FM2_10GEC1 && hwconfig_sub(
- "fsl_10gkr_copper", "fm2_10g1"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio3");
- if (i == FM2_10GEC2 && hwconfig_sub(
- "fsl_10gkr_copper", "fm2_10g2"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio4");
- break;
- }
- switch (i) {
- case FM1_10GEC1:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
- break;
- case FM1_10GEC2:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
- break;
- case FM2_10GEC1:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
- break;
- case FM2_10GEC2:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- }
-}
-
-static void initialize_qsgmiiphy_fix(void)
-{
- int i;
- unsigned short reg;
-
- for (i = 1; i <= 4; i++) {
- /*
- * Try to read if a SGMII card is used, we do it slot by slot.
- * if a SGMII PHY address is valid on a slot, then we mark
- * all ports on the slot, then fix the PHY address for the
- * marked port when doing dtb fixup.
- */
- if (miiphy_read(mdio_names[i],
- SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
- debug("Slot%d PHY ID register 2 read failed\n", i);
- continue;
- }
-
- debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
-
- if (reg == 0xFFFF) {
- /* No physical device present at this address */
- continue;
- }
-
- switch (i) {
- case 1:
- qsgmiiphy_fix[FM1_DTSEC5] = 1;
- qsgmiiphy_fix[FM1_DTSEC6] = 1;
- qsgmiiphy_fix[FM1_DTSEC9] = 1;
- qsgmiiphy_fix[FM1_DTSEC10] = 1;
- slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- case 2:
- qsgmiiphy_fix[FM1_DTSEC1] = 1;
- qsgmiiphy_fix[FM1_DTSEC2] = 1;
- qsgmiiphy_fix[FM1_DTSEC3] = 1;
- qsgmiiphy_fix[FM1_DTSEC4] = 1;
- slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- case 3:
- qsgmiiphy_fix[FM2_DTSEC5] = 1;
- qsgmiiphy_fix[FM2_DTSEC6] = 1;
- qsgmiiphy_fix[FM2_DTSEC9] = 1;
- qsgmiiphy_fix[FM2_DTSEC10] = 1;
- slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- case 4:
- qsgmiiphy_fix[FM2_DTSEC1] = 1;
- qsgmiiphy_fix[FM2_DTSEC2] = 1;
- qsgmiiphy_fix[FM2_DTSEC3] = 1;
- qsgmiiphy_fix[FM2_DTSEC4] = 1;
- slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- default:
- break;
- }
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
- t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
- initialize_qsgmiiphy_fix();
-
- switch (srds_prtcl_s1) {
- case 1:
- case 2:
- case 4:
- /* XAUI/HiGig in Slot1 and Slot2 */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
- break;
- case 27:
- case 28:
- case 35:
- case 36:
- /* SGMII in Slot1 and Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
- fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
- fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
- fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
- fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
- fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
- fm_info_set_phy_address(FM1_DTSEC9,
- slot_qsgmii_phyaddr[1][3]);
- fm_info_set_phy_address(FM1_DTSEC10,
- slot_qsgmii_phyaddr[1][2]);
- }
- break;
- case 37:
- case 38:
- fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
- fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
- fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
- fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
- fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
- fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
- fm_info_set_phy_address(FM1_DTSEC9,
- slot_qsgmii_phyaddr[1][2]);
- fm_info_set_phy_address(FM1_DTSEC10,
- slot_qsgmii_phyaddr[1][3]);
- }
- break;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
- fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
- fm_info_set_phy_address(FM1_DTSEC10,
- slot_qsgmii_phyaddr[1][2]);
- fm_info_set_phy_address(FM1_DTSEC9,
- slot_qsgmii_phyaddr[1][3]);
- }
- fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
- fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
- fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
- fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
- break;
- default:
- puts("Invalid SerDes1 protocol for T4240QDS\n");
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_QSGMII) {
- if (idx <= 3)
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_A);
- else
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_B);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
- idx + 1, slot);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- debug("FM1@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- }
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /* FM1 DTSEC5 routes to RGMII with EC2 */
- debug("FM1@DTSEC%u is RGMII at address %u\n",
- idx + 1, 2);
- if (i == FM1_DTSEC5)
- fm_info_set_phy_address(i, 2);
- mdio_mux[i] = EMI1_RGMII;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- idx = i - FM1_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
- /* A fake PHY address to make U-Boot happy */
- fm_info_set_phy_address(i, i);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XAUI_FM1_MAC9 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- }
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- switch (srds_prtcl_s2) {
- case 1:
- case 2:
- case 4:
- /* XAUI/HiGig in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
- break;
- case 6:
- case 7:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 21:
- case 22:
- case 23:
- case 24:
- case 25:
- case 26:
- /* XAUI/HiGig in Slot3, SGMII in Slot4 */
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- case 27:
- case 28:
- case 35:
- case 36:
- /* SGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
- fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
- fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
- fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
- break;
- case 37:
- case 38:
- /* QSGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
- fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
- fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
- fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
- break;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
- fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
- fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
- fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
- /* QSGMII in Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- case 49:
- case 50:
- case 51:
- case 52:
- case 53:
- case 54:
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- case 55:
- case 57:
- /* XFI in Slot3, SGMII in Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- default:
- puts("Invalid SerDes2 protocol for T4240QDS\n");
- break;
- }
-
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- idx = i - FM2_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_QSGMII) {
- if (idx <= 3)
- lane = serdes_get_first_lane(FSL_SRDS_2,
- QSGMII_FM2_A);
- else
- lane = serdes_get_first_lane(FSL_SRDS_2,
- QSGMII_FM2_B);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
- idx + 1, slot);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_2,
- SGMII_FM2_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- debug("FM2@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- }
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- switch (slot) {
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /*
- * If DTSEC5 is RGMII, then it's routed via via EC1 to
- * the first on-board RGMII port. If DTSEC6 is RGMII,
- * then it's routed via via EC2 to the second on-board
- * RGMII port.
- */
- debug("FM2@DTSEC%u is RGMII at address %u\n",
- idx + 1, i == FM2_DTSEC5 ? 1 : 2);
- fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
- mdio_mux[i] = EMI1_RGMII;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
- idx = i - FM2_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
- /* A fake PHY address to make U-Boot happy */
- fm_info_set_phy_address(i, i);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_2,
- XAUI_FM2_MAC9 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- }
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-#endif /* CONFIG_SYS_NUM_FMAN */
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include "../common/qixis.h"
-#include "t4240qds_qixis.h"
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifdef CONFIG_SPL_NAND_BOOT
- u32 porsr1, pinctl;
-#endif
-
-#ifdef CONFIG_SPL_NAND_BOOT
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
-#endif
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
- puts("\nNAND boot...\n");
-#endif
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
-
- printf("Board: %sEMU\n", cpu->name);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <linux/delay.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "t4qds.h"
-#include "t4240qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
- {8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
- {10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
- {10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
- {8, 9}, {9, 8}, {14, 1}, {15, 0} };
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- unsigned int i;
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("Promjet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n" at the end */
- printf(" on %s", qixis_read_time(buf));
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference Clocks: ");
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < MAX_SERDES; i++) {
- static const char * const freq[] = {
- "100", "125", "156.25", "161.1328125"};
- unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-
- printf("SERDES%u=%sMHz ", i+1, freq[clock]);
- }
- puts("\n");
-
- return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
-#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
-
-static inline int read_voltage(void)
-{
- int i, ret, voltage_read = 0;
- u16 vol_mon;
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int bus_num = 0;
-#endif
-
- for (i = 0; i < NUM_READINGS; i++) {
-#ifdef CONFIG_DM_I2C
- ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_read(dev,
- I2C_VOL_MONITOR_BUS_V_OFFSET,
- (void *)&vol_mon, 2);
-#else
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
-#endif
- if (ret) {
- printf("VID: failed to read core voltage\n");
- return ret;
- }
- if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
- printf("VID: Core voltage sensor error\n");
- return -1;
- }
- debug("VID: bus voltage reads 0x%04x\n", vol_mon);
- /* LSB = 4mv */
- voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
- udelay(WAIT_FOR_ADC);
- }
- /* calculate the average */
- voltage_read /= NUM_READINGS;
-
- return voltage_read;
-}
-
-/*
- * We need to calculate how long before the voltage starts to drop or increase
- * It returns with the loop count. Each loop takes several readings (532us)
- */
-static inline int wait_for_voltage_change(int vdd_last)
-{
- int timeout, vdd_current;
-
- vdd_current = read_voltage();
- /* wait until voltage starts to drop */
- for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
- timeout < 100; timeout++) {
- vdd_current = read_voltage();
- }
- if (timeout >= 100) {
- printf("VID: Voltage adjustment timeout\n");
- return -1;
- }
- return timeout;
-}
-
-/*
- * argument 'wait' is the time we know the voltage difference can be measured
- * this function keeps reading the voltage until it is stable
- */
-static inline int wait_for_voltage_stable(int wait)
-{
- int timeout, vdd_current, vdd_last;
-
- vdd_last = read_voltage();
- udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
- /* wait until voltage is stable */
- vdd_current = read_voltage();
- for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
- timeout < 100; timeout++) {
- vdd_last = vdd_current;
- udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
- vdd_current = read_voltage();
- }
- if (timeout >= 100) {
- printf("VID: Voltage adjustment timeout\n");
- return -1;
- }
-
- return vdd_current;
-}
-
-static inline int set_voltage(u8 vid)
-{
- int wait, vdd_last;
-
- vdd_last = read_voltage();
- QIXIS_WRITE(brdcfg[6], vid);
- wait = wait_for_voltage_change(vdd_last);
- if (wait < 0)
- return -1;
- debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
- wait = wait ? wait : 1;
-
- vdd_last = wait_for_voltage_stable(wait);
- if (vdd_last < 0)
- return -1;
- debug("VID: Current voltage is %d mV\n", vdd_last);
-
- return vdd_last;
-}
-
-
-static int adjust_vdd(ulong vdd_override)
-{
- int re_enable = disable_interrupts();
- ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 fusesr;
- u8 vid, vid_current;
- int vdd_target, vdd_current, vdd_last;
- int ret;
- unsigned long vdd_string_override;
- char *vdd_string;
- static const uint16_t vdd[32] = {
- 0, /* unused */
- 9875, /* 0.9875V */
- 9750,
- 9625,
- 9500,
- 9375,
- 9250,
- 9125,
- 9000,
- 8875,
- 8750,
- 8625,
- 8500,
- 8375,
- 8250,
- 8125,
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 10375,
- 10500,
- 10625,
- 10750,
- 10875,
- 11000,
- 0, /* reserved */
- };
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
-
- ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
- if (ret) {
- debug("VID: I2c failed to switch channel\n");
- ret = -1;
- goto exit;
- }
-
- /* get the voltage ID from fuse status register */
- fusesr = in_be32(&gur->dcfg_fusesr);
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_VID_MASK;
- if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
- }
- vdd_target = vdd[vid];
-
- /* check override variable for overriding VDD */
- vdd_string = env_get("t4240qds_vdd_mv");
- if (vdd_override == 0 && vdd_string &&
- !strict_strtoul(vdd_string, 10, &vdd_string_override))
- vdd_override = vdd_string_override;
- if (vdd_override >= 819 && vdd_override <= 1212) {
- vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
- } else if (vdd_override != 0) {
- printf("Invalid value.\n");
- }
-
- if (vdd_target == 0) {
- debug("VID: VID not used\n");
- ret = 0;
- goto exit;
- } else {
- /* round up and divice by 10 to get a value in mV */
- vdd_target = DIV_ROUND_UP(vdd_target, 10);
- debug("VID: vid = %d mV\n", vdd_target);
- }
-
- /*
- * Check current board VID setting
- * Voltage regulator support output to 6.250mv step
- * The highes voltage allowed for this board is (vid=0x40) 1.21250V
- * the lowest is (vid=0x7f) 0.81875V
- */
- vid_current = QIXIS_READ(brdcfg[6]);
- vdd_current = 121250 - (vid_current - 0x40) * 625;
- debug("VID: Current vid setting is (0x%x) %d mV\n",
- vid_current, vdd_current/100);
-
- /*
- * Read voltage monitor to check real voltage.
- * Voltage monitor LSB is 4mv.
- */
- vdd_last = read_voltage();
- if (vdd_last < 0) {
- printf("VID: Could not read voltage sensor abort VID adjustment\n");
- ret = -1;
- goto exit;
- }
- debug("VID: Core voltage is at %d mV\n", vdd_last);
- /*
- * Adjust voltage to at or 8mV above target.
- * Each step of adjustment is 6.25mV.
- * Stepping down too fast may cause over current.
- */
- while (vdd_last > 0 && vid_current < 0x80 &&
- vdd_last > (vdd_target + 8)) {
- vid_current++;
- vdd_last = set_voltage(vid_current);
- }
- /*
- * Check if we need to step up
- * This happens when board voltage switch was set too low
- */
- while (vdd_last > 0 && vid_current >= 0x40 &&
- vdd_last < vdd_target + 2) {
- vid_current--;
- vdd_last = set_voltage(vid_current);
- }
- if (vdd_last > 0)
- printf("VID: Core voltage %d mV\n", vdd_last);
- else
- ret = -1;
-
-exit:
- if (re_enable)
- enable_interrupts();
- return ret;
-}
-
-/* Configure Crossbar switches for Front-Side SerDes Ports */
-int config_frontside_crossbar_vsc3316(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
- int ret;
-
- ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
- if (ret)
- return ret;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- switch (srds_prtcl_s1) {
- case 37:
- case 38:
- /* swap first lane and third lane on slot1 */
- vsc3316_fsm1_tx[0][1] = 14;
- vsc3316_fsm1_tx[6][1] = 0;
- vsc3316_fsm1_rx[1][1] = 2;
- vsc3316_fsm1_rx[6][1] = 13;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- /* swap first lane and third lane on slot2 */
- vsc3316_fsm1_tx[2][1] = 8;
- vsc3316_fsm1_tx[4][1] = 6;
- vsc3316_fsm1_rx[2][1] = 10;
- vsc3316_fsm1_rx[5][1] = 5;
- default:
- ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
- if (ret)
- return ret;
- break;
- }
-
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- switch (srds_prtcl_s2) {
- case 37:
- case 38:
- /* swap first lane and third lane on slot3 */
- vsc3316_fsm2_tx[2][1] = 11;
- vsc3316_fsm2_tx[5][1] = 4;
- vsc3316_fsm2_rx[2][1] = 9;
- vsc3316_fsm2_rx[4][1] = 7;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- case 49:
- case 50:
- case 51:
- case 52:
- case 53:
- case 54:
- /* swap first lane and third lane on slot4 */
- vsc3316_fsm2_tx[6][1] = 3;
- vsc3316_fsm2_tx[1][1] = 12;
- vsc3316_fsm2_rx[0][1] = 1;
- vsc3316_fsm2_rx[6][1] = 15;
- default:
- ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
- if (ret)
- return ret;
- break;
- }
-
- return 0;
-}
-
-int config_backside_crossbar_mux(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s3, srds_prtcl_s4;
- u8 brdcfg;
-
- srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
- srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
- switch (srds_prtcl_s3) {
- case 0:
- /* SerDes3 is not enabled */
- break;
- case 1:
- case 2:
- case 9:
- case 10:
- /* SD3(0:7) => SLOT5(0:7) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD3MX_MASK;
- brdcfg |= BRDCFG12_SD3MX_SLOT5;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 17:
- case 18:
- case 19:
- case 20:
- /* SD3(4:7) => SLOT6(0:3) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD3MX_MASK;
- brdcfg |= BRDCFG12_SD3MX_SLOT6;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- default:
- printf("WARNING: unsupported for SerDes3 Protocol %d\n",
- srds_prtcl_s3);
- return -1;
- }
-
- srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
- srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
- switch (srds_prtcl_s4) {
- case 0:
- /* SerDes4 is not enabled */
- break;
- case 1:
- case 2:
- /* 10b, SD4(0:7) => SLOT7(0:7) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD4MX_MASK;
- brdcfg |= BRDCFG12_SD4MX_SLOT7;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- /* x1b, SD4(4:7) => SLOT8(0:3) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD4MX_MASK;
- brdcfg |= BRDCFG12_SD4MX_SLOT8;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- case 9:
- case 10:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 18:
- /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD4MX_MASK;
- brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- default:
- printf("WARNING: unsupported for SerDes4 Protocol %d\n",
- srds_prtcl_s4);
- return -1;
- }
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /* Disable remote I2C connection to qixis fpga */
- QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0))
- printf("Warning: Adjusting core voltage failed.\n");
-
- /* Configure board SERDES ports crossbar */
- config_frontside_crossbar_vsc3316();
- config_backside_crossbar_mux();
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
- /* use accurate clock measurement */
- int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
- int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
- u32 val;
-
- val = freq * base;
- if (val) {
- debug("SYS Clock measurement is: %d\n", val);
- return val;
- } else {
- printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
- }
-#endif
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
- /* use accurate clock measurement */
- int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
- int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
- u32 val;
-
- val = freq * base;
- if (val) {
- debug("DDR Clock measurement is: %d\n", val);
- return val;
- } else {
- printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
- }
-#endif
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-int misc_init_r(void)
-{
- u8 sw;
- void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- serdes_corenet_t *srds_regs;
- u32 actual[MAX_SERDES];
- u32 pllcr0, expected;
- unsigned int i;
-
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < MAX_SERDES; i++) {
- unsigned int clock = (sw >> (6 - 2 * i)) & 3;
- switch (clock) {
- case 0:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 2:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- case 3:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
- break;
- }
- }
-
- for (i = 0; i < MAX_SERDES; i++) {
- srds_regs = srds_base + i * 0x1000;
- pllcr0 = srds_regs->bank[0].pllcr0;
- expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
- i + 1, serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
- fdt_fixup_fman_ethernet(blob);
-#endif
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-/*
- * This function is called by bdinfo to print detail board information.
- * As an exmaple for future board, we organize the messages into
- * several sections. If applicable, the message is in the format of
- * <name> = <value>
- * It should aligned with normal output of bdinfo command.
- *
- * Voltage: Core, DDR and another configurable voltages
- * Clock : Critical clocks which are not printed already
- * RCW : RCW source if not printed already
- * Misc : Other important information not in above catagories
- */
-void board_detail(void)
-{
- int i;
- u8 brdcfg[16], dutcfg[16], rst_ctl;
- int vdd, rcwsrc;
- static const char * const clk[] = {"66.67", "100", "125", "133.33"};
-
- for (i = 0; i < 16; i++) {
- brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
- dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
- }
-
- /* Voltage secion */
- if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
- vdd = read_voltage();
- if (vdd > 0)
- printf("Core voltage= %d mV\n", vdd);
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
- }
-
- printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
-
- /* clock section */
- printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
- clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
-
- /* RCW section */
- rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
- puts("RCW source = ");
- switch (rcwsrc) {
- case 0x017:
- case 0x01f:
- puts("8-bit NOR\n");
- break;
- case 0x027:
- case 0x02F:
- puts("16-bit NOR\n");
- break;
- case 0x040:
- puts("SDHC/eMMC\n");
- break;
- case 0x044:
- puts("SPI 16-bit addressing\n");
- break;
- case 0x045:
- puts("SPI 24-bit addressing\n");
- break;
- case 0x048:
- puts("I2C normal addressing\n");
- break;
- case 0x049:
- puts("I2C extended addressing\n");
- break;
- case 0x108:
- case 0x109:
- case 0x10a:
- case 0x10b:
- puts("8-bit NAND, 2KB\n");
- break;
- default:
- if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
- puts("Hard-coded RCW\n");
- else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
- puts("8-bit NAND, 4KB\n");
- else
- puts("unknown\n");
- break;
- }
-
- /* Misc section */
- rst_ctl = QIXIS_READ(rst_ctl);
- puts("HRESET_REQ = ");
- switch (rst_ctl & 0x30) {
- case 0x00:
- puts("Ignored\n");
- break;
- case 0x10:
- puts("Assert HRESET\n");
- break;
- case 0x30:
- puts("Reset system\n");
- break;
- default:
- puts("N/A\n");
- break;
- }
-}
-
-/*
- * Reverse engineering switch settings.
- * Some bits cannot be figured out. They will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
- int i;
- u8 sw[9];
-
- /*
- * Any bit with 1 means that bit cannot be reverse engineered.
- * It will be displayed as _ in binary format.
- */
- static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
- char buf[10];
- u8 brdcfg[16], dutcfg[16];
-
- for (i = 0; i < 16; i++) {
- brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
- dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
- }
-
- sw[0] = dutcfg[0];
- sw[1] = (dutcfg[1] << 0x07) |
- ((dutcfg[12] & 0xC0) >> 1) |
- ((dutcfg[11] & 0xE0) >> 3) |
- ((dutcfg[6] & 0x80) >> 6) |
- ((dutcfg[1] & 0x80) >> 7);
- sw[2] = ((brdcfg[1] & 0x0f) << 4) |
- ((brdcfg[1] & 0x30) >> 2) |
- ((brdcfg[1] & 0x40) >> 5) |
- ((brdcfg[1] & 0x80) >> 7);
- sw[3] = brdcfg[2];
- sw[4] = ((dutcfg[2] & 0x01) << 7) |
- ((dutcfg[2] & 0x06) << 4) |
- ((~QIXIS_READ(present)) & 0x10) |
- ((brdcfg[3] & 0x80) >> 4) |
- ((brdcfg[3] & 0x01) << 2) |
- ((brdcfg[6] == 0x62) ? 3 :
- ((brdcfg[6] == 0x5a) ? 2 :
- ((brdcfg[6] == 0x5e) ? 1 : 0)));
- sw[5] = ((brdcfg[0] & 0x0f) << 4) |
- ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
- ((brdcfg[0] & 0x40) >> 5);
- sw[6] = (brdcfg[11] & 0x20) |
- ((brdcfg[5] & 0x02) << 3);
- sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
- ((brdcfg[5] & 0x10) << 2);
- sw[8] = ((brdcfg[12] & 0x08) << 4) |
- ((brdcfg[12] & 0x03) << 5);
-
- puts("DIP switch (reverse-engineering)\n");
- for (i = 0; i < 9; i++) {
- printf("SW%d = 0b%s (0x%02x)\n",
- i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
- }
-}
-
-static int do_vdd_adjust(struct cmd_tbl *cmdtp,
- int flag, int argc,
- char *const argv[])
-{
- ulong override;
-
- if (argc < 2)
- return CMD_RET_USAGE;
- if (!strict_strtoul(argv[1], 10, &override))
- adjust_vdd(override); /* the value is checked by callee */
- else
- return CMD_RET_USAGE;
-
- return 0;
-}
-
-U_BOOT_CMD(
- vdd_override, 2, 0, do_vdd_adjust,
- "Override VDD",
- "- override with the voltage specified in mV, eg. 1050"
-);
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T4020QDS_QIXIS_H__
-#define __T4020QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T4020QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
-
-#define BRDCFG12_SD3EN_MASK 0x20
-#define BRDCFG12_SD3MX_MASK 0x08
-#define BRDCFG12_SD3MX_SLOT5 0x08
-#define BRDCFG12_SD3MX_SLOT6 0x00
-#define BRDCFG12_SD4EN_MASK 0x04
-#define BRDCFG12_SD4MX_MASK 0x03
-#define BRDCFG12_SD4MX_SLOT7 0x02
-#define BRDCFG12_SD4MX_SLOT8 0x01
-#define BRDCFG12_SD4MX_AURO_SATA 0x00
-#endif
+++ /dev/null
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 e8020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
+++ /dev/null
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
+++ /dev/null
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 68020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
- /*
- * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
- * space is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
- /*
- * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
- * fetching ucode and ENV from master
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 18, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 19, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
DECLARE_GLOBAL_DATA_PTR;
/* FIXME gpio code here need to handle through DM_GPIO */
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
vinco_spi0_hw_init();
#endif
}
break;
case OMAP_TAG_UART:
- if (!t->u.uart.enabled_uarts)
+ if (t->u.uart.enabled_uarts)
serial_was_console_enabled = 1;
break;
case OMAP_TAG_SERIAL_CONSOLE:
/*
* Secure boot support
*/
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif
imply SMP
imply MISC
imply SIFIVE_OTP
- imply SYSRESET
- imply SYSRESET_GPIO
endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+ default "maix"
+
+config SYS_VENDOR
+ default "sipeed"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "sipeed-maix"
+
+config SYS_TEXT_BASE
+ default 0x80000000
+
+config DEFAULT_DEVICE_TREE
+ default "k210-maix-bit"
+
+config NR_CPUS
+ default 2
+
+config NR_DRAM_BANKS
+ default 3
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select GENERIC_RISCV
+ select RISCV_PRIV_1_9
+ imply SMP
+ imply DM_SERIAL
+ imply SIFIVE_SERIAL
+ imply SIFIVE_CLINT
+ imply POWER_DOMAIN
+ imply SIMPLE_PM_BUS
+ imply CLK_CCF
+ imply CLK_COMPOSITE_CCF
+ imply CLK_K210
+ imply DM_RESET
+ imply RESET_SYSCON
+ imply SYSRESET
+ imply SYSRESET_SYSCON
+endif
--- /dev/null
+Sipeed Maix BOARD
+M: Sean Anderson <seanga2@gmail.com>
+S: Maintained
+F: arch/riscv/dts/k210.dtsi
+F: arch/riscv/dts/k210-maix-bit.dts
+F: board/sipeed/maix/
+F: configs/sipeed_maix_bitm_defconfig
+F: doc/board/sipeed/
+F: include/configs/sipeed-maix.h
+F: include/dt-bindings/*/k210-sysctl.h
+F: test/dm/k210_pll.c
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y += maix.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_SDRAM_SIZE;
+}
+
+int board_init(void)
+{
+ int ret, i;
+ const char * const banks[] = { "sram0", "sram1", "airam" };
+ ofnode memory;
+ struct clk clk;
+
+ /* Enable RAM clocks */
+ memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram");
+ if (ofnode_equal(memory, ofnode_null()))
+ return -ENOENT;
+
+ for (i = 0; i < ARRAY_SIZE(banks); i++) {
+ ret = clk_get_by_name_nodev(memory, banks[i], &clk);
+ if (ret)
+ continue;
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
config MTDPARTS_NOR0_TEE
string "mtd tee partitions for nor0"
- default "256k(teeh),256k(teed),256k(teex)"
+ default "256k(teeh),512k(teed),256k(teex)"
depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
help
This define the tee partitions added in mtparts dynamically
depends on ARCH_STM32MP && SET_DFU_ALT_INFO
help
This defines the partitions of ram used to build dfu dynamically.
+
+config TYPEC_STUSB160X
+ tristate "STMicroelectronics STUSB160X Type-C controller driver"
+ depends on DM_I2C
+ help
+ Say Y if your system has STMicroelectronics STUSB160X Type-C port
+ controller.
#
obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
+obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
ifeq ($(CONFIG_ARCH_STM32MP),y)
obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += stm32mp_mtdparts.o
obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
endif
+
+obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/stpmic1.h>
+
+int board_ddr_power_init(enum ddr_type ddr_type)
+{
+ struct udevice *dev;
+ bool buck3_at_1800000v = false;
+ int ret;
+ u32 buck2;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmic1), &dev);
+ if (ret)
+ /* No PMIC on board */
+ return 0;
+
+ switch (ddr_type) {
+ case STM32MP_DDR3:
+ /* VTT = Set LDO3 to sync mode */
+ ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMIC1_LDO3_MODE;
+ ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+ ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+
+ ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+
+ /* VDD_DDR = Set BUCK2 to 1.35V */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_VOUT_MASK,
+ STPMIC1_BUCK2_1350000V);
+ if (ret < 0)
+ return ret;
+
+ /* Enable VDD_DDR = BUCK2 */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VREF */
+ ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+ STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VTT = LDO3 */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ break;
+
+ case STM32MP_LPDDR2_16:
+ case STM32MP_LPDDR2_32:
+ case STM32MP_LPDDR3_16:
+ case STM32MP_LPDDR3_32:
+ /*
+ * configure VDD_DDR1 = LDO3
+ * Set LDO3 to 1.8V
+ * + bypass mode if BUCK3 = 1.8V
+ * + normal mode if BUCK3 != 1.8V
+ */
+ ret = pmic_reg_read(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
+ if (ret < 0)
+ return ret;
+
+ if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
+ buck3_at_1800000v = true;
+
+ ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMIC1_LDO3_MODE;
+ ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+ ret |= STPMIC1_LDO3_1800000;
+ if (buck3_at_1800000v)
+ ret |= STPMIC1_LDO3_MODE;
+
+ ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+
+ /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
+ switch (ddr_type) {
+ case STM32MP_LPDDR2_32:
+ case STM32MP_LPDDR3_32:
+ buck2 = STPMIC1_BUCK2_1250000V;
+ break;
+ default:
+ case STM32MP_LPDDR2_16:
+ case STM32MP_LPDDR3_16:
+ buck2 = STPMIC1_BUCK2_1200000V;
+ break;
+ }
+
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_VOUT_MASK,
+ buck2);
+ if (ret < 0)
+ return ret;
+
+ /* Enable VDD_DDR1 = LDO3 */
+ ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VDD_DDR2 =BUCK2 */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VREF */
+ ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+ STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ break;
+
+ default:
+ break;
+ };
+
+ return 0;
+}
+
+static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
+{
+ u32 value;
+
+ /* VDDCORE= STMPCI1 BUCK1 ramp=+25mV, 5 => 725mV, 36 => 1500mV */
+ value = ((voltage_mv - 725) / 25) + 5;
+ if (value < 5)
+ value = 5;
+ if (value > 36)
+ value = 36;
+
+ return pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK1),
+ STPMIC1_BUCK_VOUT_MASK,
+ STPMIC1_BUCK_VOUT(value));
+}
+
+/* early init of PMIC */
+void stpmic1_init(u32 voltage_mv)
+{
+ struct udevice *dev;
+
+ if (uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmic1), &dev))
+ return;
+
+ /* update VDDCORE = BUCK1 */
+ if (voltage_mv)
+ stmpic_buck1_set(dev, voltage_mv);
+
+ /* Keep vdd on during the reset cycle */
+ pmic_clrsetbits(dev,
+ STPMIC1_BUCKS_MRST_CR,
+ STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
+ STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+
+ /* Check if debug is enabled to program PMIC according to the bit */
+ if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
+ printf("Keep debug unit ON\n");
+
+ pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
+ STPMIC1_MRST_BUCK_DEBUG,
+ STPMIC1_MRST_BUCK_DEBUG);
+
+ if (STPMIC1_MRST_LDO_DEBUG)
+ pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
+ STPMIC1_MRST_LDO_DEBUG,
+ STPMIC1_MRST_LDO_DEBUG);
+ }
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+void stpmic1_init(u32 voltage_mv);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * STMicroelectronics STUSB Type-C controller driver
+ * based on Linux drivers/usb/typec/stusb160x.c
+ *
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+
+/* REGISTER */
+#define STUSB160X_CC_CONNECTION_STATUS 0x0E
+
+/* STUSB160X_CC_CONNECTION_STATUS bitfields */
+#define STUSB160X_CC_ATTACH BIT(0)
+
+int stusb160x_cable_connected(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_I2C_GENERIC,
+ DM_GET_DRIVER(stusb160x),
+ &dev);
+ if (ret < 0)
+ return ret;
+
+ ret = dm_i2c_reg_read(dev, STUSB160X_CC_CONNECTION_STATUS);
+ if (ret < 0)
+ return 0;
+
+ return ret & STUSB160X_CC_ATTACH;
+}
+
+static const struct udevice_id stusb160x_ids[] = {
+ { .compatible = "st,stusb1600" },
+ {}
+};
+
+U_BOOT_DRIVER(stusb160x) = {
+ .name = "stusb160x",
+ .id = UCLASS_I2C_GENERIC,
+ .of_match = stusb160x_ids,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020, STMicroelectronics
+ */
+
+#ifdef CONFIG_TYPEC_STUSB160X
+int stusb160x_cable_connected(void);
+#else
+int stusb160x_cable_connected(void) { return -ENODEV; }
+#endif
else
obj-y += stm32mp1.o
endif
-
-obj-y += board.o
*/
#include <common.h>
-#include <dm.h>
#include <asm/io.h>
-#include <asm/arch/ddr.h>
#include <linux/bitops.h>
#include <linux/delay.h>
-#include <power/pmic.h>
-#include <power/stpmic1.h>
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
#endif
}
#endif
-
-#ifdef CONFIG_PMIC_STPMIC1
-int board_ddr_power_init(enum ddr_type ddr_type)
-{
- struct udevice *dev;
- bool buck3_at_1800000v = false;
- int ret;
- u32 buck2;
-
- ret = uclass_get_device_by_driver(UCLASS_PMIC,
- DM_GET_DRIVER(pmic_stpmic1), &dev);
- if (ret)
- /* No PMIC on board */
- return 0;
-
- switch (ddr_type) {
- case STM32MP_DDR3:
- /* VTT = Set LDO3 to sync mode */
- ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
- if (ret < 0)
- return ret;
-
- ret &= ~STPMIC1_LDO3_MODE;
- ret &= ~STPMIC1_LDO12356_VOUT_MASK;
- ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
-
- ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- ret);
- if (ret < 0)
- return ret;
-
- /* VDD_DDR = Set BUCK2 to 1.35V */
- ret = pmic_clrsetbits(dev,
- STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
- STPMIC1_BUCK_VOUT_MASK,
- STPMIC1_BUCK2_1350000V);
- if (ret < 0)
- return ret;
-
- /* Enable VDD_DDR = BUCK2 */
- ret = pmic_clrsetbits(dev,
- STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
- STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- /* Enable VREF */
- ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
- STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- /* Enable VTT = LDO3 */
- ret = pmic_clrsetbits(dev,
- STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- break;
-
- case STM32MP_LPDDR2_16:
- case STM32MP_LPDDR2_32:
- case STM32MP_LPDDR3_16:
- case STM32MP_LPDDR3_32:
- /*
- * configure VDD_DDR1 = LDO3
- * Set LDO3 to 1.8V
- * + bypass mode if BUCK3 = 1.8V
- * + normal mode if BUCK3 != 1.8V
- */
- ret = pmic_reg_read(dev,
- STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
- if (ret < 0)
- return ret;
-
- if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
- buck3_at_1800000v = true;
-
- ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
- if (ret < 0)
- return ret;
-
- ret &= ~STPMIC1_LDO3_MODE;
- ret &= ~STPMIC1_LDO12356_VOUT_MASK;
- ret |= STPMIC1_LDO3_1800000;
- if (buck3_at_1800000v)
- ret |= STPMIC1_LDO3_MODE;
-
- ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- ret);
- if (ret < 0)
- return ret;
-
- /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
- switch (ddr_type) {
- case STM32MP_LPDDR2_32:
- case STM32MP_LPDDR3_32:
- buck2 = STPMIC1_BUCK2_1250000V;
- break;
- default:
- case STM32MP_LPDDR2_16:
- case STM32MP_LPDDR3_16:
- buck2 = STPMIC1_BUCK2_1200000V;
- break;
- }
-
- ret = pmic_clrsetbits(dev,
- STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
- STPMIC1_BUCK_VOUT_MASK,
- buck2);
- if (ret < 0)
- return ret;
-
- /* Enable VDD_DDR1 = LDO3 */
- ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- /* Enable VDD_DDR2 =BUCK2 */
- ret = pmic_clrsetbits(dev,
- STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
- STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- /* Enable VREF */
- ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
- STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- break;
-
- default:
- break;
- };
-
- return 0;
-}
-#endif
#include <config.h>
#include <common.h>
-#include <spl.h>
-#include <dm.h>
-#include <ram.h>
+#include <init.h>
#include <asm/io.h>
-#include <power/pmic.h>
-#include <power/stpmic1.h>
-#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include "../common/stpmic1.h"
-void spl_board_init(void)
+/* board early initialisation in board_f: need to use global variable */
+static u32 opp_voltage_mv __section(".data");
+
+void board_vddcore_init(u32 voltage_mv)
+{
+ if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER_SUPPORT))
+ opp_voltage_mv = voltage_mv;
+}
+
+int board_early_init_f(void)
+{
+ if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER_SUPPORT))
+ stpmic1_init(opp_voltage_mv);
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
{
- /* Keep vdd on during the reset cycle */
-#if defined(CONFIG_PMIC_STPMIC1) && defined(CONFIG_SPL_POWER_SUPPORT)
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_PMIC,
- DM_GET_DRIVER(pmic_stpmic1), &dev);
- if (!ret)
- pmic_clrsetbits(dev,
- STPMIC1_BUCKS_MRST_CR,
- STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
- STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
-
- /* Check if debug is enabled to program PMIC according to the bit */
- if ((readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) && !ret) {
- printf("Keep debug unit ON\n");
-
- pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
- STPMIC1_MRST_BUCK_DEBUG,
- STPMIC1_MRST_BUCK_DEBUG);
-
- if (STPMIC1_MRST_LDO_DEBUG)
- pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
- STPMIC1_MRST_LDO_DEBUG,
- STPMIC1_MRST_LDO_DEBUG);
- }
+#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
+
+#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
+#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
+
+ /* UART4 clock enable */
+ setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+
+#define GPIOG_BASE 0x50008000
+ /* GPIOG clock enable */
+ writel(BIT(6), RCC_MP_AHB4ENSETR);
+ /* GPIO configuration for ST boards: Uart4 TX = G11 */
+ writel(0xffbfffff, GPIOG_BASE + 0x00);
+ writel(0x00006000, GPIOG_BASE + 0x24);
+#else
+
+#error("CONFIG_DEBUG_UART_BASE: not supported value")
+
#endif
}
+#endif
#include <power/regulator.h>
#include <usb/dwc2_udc.h>
+#include "../../st/common/stusb160x.h"
+
/* SYSCFG registers */
#define SYSCFG_BOOTR 0x00
#define SYSCFG_PMCSETR 0x04
#define USB_START_LOW_THRESHOLD_UV 1230000
#define USB_START_HIGH_THRESHOLD_UV 2150000
+int board_early_init_f(void)
+{
+ /* nothing to do, only used in SPL */
+ return 0;
+}
+
int checkboard(void)
{
int ret;
}
#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-
-/* STMicroelectronics STUSB1600 Type-C controller */
-#define STUSB1600_CC_CONNECTION_STATUS 0x0E
-
-/* STUSB1600_CC_CONNECTION_STATUS bitfields */
-#define STUSB1600_CC_ATTACH BIT(0)
-
-static int stusb1600_init(struct udevice **dev_stusb1600)
-{
- ofnode node;
- struct udevice *dev, *bus;
- int ret;
- u32 chip_addr;
-
- *dev_stusb1600 = NULL;
-
- /* if node stusb1600 is present, means DK1 or DK2 board */
- node = ofnode_by_compatible(ofnode_null(), "st,stusb1600");
- if (!ofnode_valid(node))
- return -ENODEV;
-
- ret = ofnode_read_u32(node, "reg", &chip_addr);
- if (ret)
- return -EINVAL;
-
- ret = uclass_get_device_by_ofnode(UCLASS_I2C, ofnode_get_parent(node),
- &bus);
- if (ret) {
- printf("bus for stusb1600 not found\n");
- return -ENODEV;
- }
-
- ret = dm_i2c_probe(bus, chip_addr, 0, &dev);
- if (!ret)
- *dev_stusb1600 = dev;
-
- return ret;
-}
-
-static int stusb1600_cable_connected(struct udevice *dev)
-{
- u8 status;
-
- if (dm_i2c_read(dev, STUSB1600_CC_CONNECTION_STATUS, &status, 1))
- return 0;
-
- return status & STUSB1600_CC_ATTACH;
-}
-
#include <usb/dwc2_udc.h>
int g_dnl_board_usb_cable_connected(void)
{
- struct udevice *stusb1600;
struct udevice *dwc2_udc_otg;
int ret;
- if (!stusb1600_init(&stusb1600))
- return stusb1600_cable_connected(stusb1600);
+ /* if typec stusb160x is present, means DK1 or DK2 board */
+ ret = stusb160x_cable_connected();
+ if (ret >= 0)
+ return ret;
ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
DM_GET_DRIVER(dwc2_udc_otg),
/* board dependent setup after realloc */
int board_init(void)
{
- struct udevice *dev;
-
/* address of boot parameters */
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
- /* probe all PINCTRL for hog */
- for (uclass_first_device(UCLASS_PINCTRL, &dev);
- dev;
- uclass_next_device(&dev)) {
- pr_debug("probe pincontrol = %s\n", dev->name);
- }
+ if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
+ gpio_hog_probe_all();
board_key_check();
F: arch/arm/dts/imx6q-tbs2910.dts
F: board/tbs/tbs2910/
F: configs/tbs2910_defconfig
+F: doc/board/tbs/
F: include/configs/tbs2910.h
S: Maintained
F: board/ti/am335x/
F: include/configs/am335x_evm.h
-F: configs/am335x_boneblack_defconfig
F: configs/am335x_boneblack_vboot_defconfig
F: configs/am335x_evm_defconfig
-F: configs/am335x_evm_usbspl_defconfig
.slaves = 2,
.slave_data = slave_data,
.ale_entries = 1024,
- .bd_ram_ofs = 0x2000,
.mac_control = 0x20,
.active_slave = 0,
.mdio_base = 0x4a101000,
#define board_is_am571x_idk() board_ti_is("AM571IDK")
#define board_is_bbai() board_ti_is("BBONE-AI")
+#define board_is_ti_idk() board_is_am574x_idk() || \
+ board_is_am572x_idk() || \
+ board_is_am571x_idk()
+
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
-/* GPIO 7_11 */
-#define GPIO_DDR_VTT_EN 203
+#define GPIO_DDR_VTT_EN GPIO_TO_PIN(7, 11)
/* Touch screen controller to identify the LCD */
#define OSD_TS_FT_BUS_ADDRESS 0
struct udevice *dev;
/* Only valid for IDKs */
- if (board_is_x15() || board_is_am572x_evm() || board_is_bbai())
+ if (!board_is_ti_idk())
return;
/* Only AM571x IDK has gpio control detect.. so check that */
}
#if defined(CONFIG_TI_SECURE_DEVICE)
- /* Make HW RNG reserved for secure world use */
- ret = fdt_disable_node(blob, "/interconnect@100000/trng@4e10000");
+ /* Make Crypto HW reserved for secure world use */
+ ret = fdt_disable_node(blob, "/interconnect@100000/crypto@4E00000");
if (ret)
- printf("%s: disabling TRGN failed %d\n", __func__, ret);
+ printf("%s: disabling SA2UL failed %d\n", __func__, ret);
#endif
return 0;
if (name)
env_set("board_name", name);
- else if (ep->name)
+ else if (strlen(ep->name) != 0)
env_set("board_name", ep->name);
else
env_set("board_name", unknown);
- if (ep->version)
+ if (strlen(ep->version) != 0)
env_set("board_rev", ep->version);
else
env_set("board_rev", unknown);
- if (ep->serial)
+ if (strlen(ep->serial) != 0)
env_set("board_serial", ep->serial);
else
env_set("board_serial", unknown);
if (name)
env_set("board_name", name);
- else if (ep->name)
+ else if (strlen(ep->name) != 0)
env_set("board_name", ep->name);
else
env_set("board_name", unknown);
- if (ep->version)
+ if (strlen(ep->version) != 0)
env_set("board_rev", ep->version);
else
env_set("board_rev", unknown);
- if (ep->software_revision)
+ if (strlen(ep->software_revision) != 0)
env_set("board_software_revision", ep->software_revision);
else
env_set("board_software_revision", unknown);
- if (ep->serial)
+ if (strlen(ep->serial) != 0)
env_set("board_serial", ep->serial);
else
env_set("board_serial", unknown);
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
+#include <serial.h>
#include <tca642x.h>
#include <usb.h>
#include <linux/delay.h>
return 0;
}
-int board_eth_init(bd_t *bis)
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
return 0;
}
+#endif /* CONFIG_SPL_OS_BOOT */
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
-static void enable_host_clocks(void)
+int board_eth_init(bd_t *bis)
{
- int auxclk;
- int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
- OPTFCLKEN_HSIC480M_P3_CLK |
- OPTFCLKEN_HSIC60M_P2_CLK |
- OPTFCLKEN_HSIC480M_P2_CLK |
- OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
- /* Enable port 2 and 3 clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
- /* Enable port 2 and 3 usb host ports tll clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
- (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
-#ifdef CONFIG_USB_XHCI_OMAP
- /* Enable the USB OTG Super speed clocks */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
- (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
-#endif
-
- auxclk = readl((*prcm)->scrm_auxclk1);
- /* Request auxilary clock */
- auxclk |= AUXCLK_ENABLE_MASK;
- writel(auxclk, (*prcm)->scrm_auxclk1);
+ return 0;
}
-#endif
/**
* @brief misc_init_r - Configure EVM board specific configurations
}
#endif
-#ifdef CONFIG_USB_EHCI_HCD
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
- .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- int ret;
-
- enable_host_clocks();
-
- ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
- if (ret < 0) {
- puts("Failed to initialize ehci\n");
- return ret;
- }
-
- return 0;
-}
-
-int ehci_hcd_stop(void)
-{
- return omap_ehci_hcd_stop();
-}
-
-void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
-{
- /* The LAN9730 needs to be reset after the port power has been set. */
- if (port == 3) {
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
- udelay(10);
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
- }
-}
-#endif
-
#ifdef CONFIG_USB_XHCI_OMAP
/**
* @brief board_usb_init - Configure EVM board specific configurations
ret = palmas_enable_ss_ldo();
#endif
- enable_host_clocks();
-
return 0;
}
#endif
#include <init.h>
#include <log.h>
#include <net.h>
+#include <serial.h>
#include <asm/mach-types.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include "panda_mux_data.h"
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
#define PANDA_ULPI_PHY_TYPE_GPIO 182
#define PANDA_BOARD_ID_1_GPIO 101
#define PANDA_ES_BOARD_ID_1_GPIO 48
return 0;
}
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
int board_eth_init(bd_t *bis)
{
return 0;
#endif
#endif
-#ifdef CONFIG_USB_EHCI_HCD
-
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- int ret;
- unsigned int utmi_clk;
-
- /* Now we can enable our port clocks */
- utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
- utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
- setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
-
- ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-#endif
-
/*
* get_board_rev() - get board revision
*/
#include <init.h>
#include <net.h>
#include <twl6030.h>
+#include <serial.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#endif
#endif
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
/*
* get_board_rev() - get board revision
*/
+++ /dev/null
-if TARGET_TI814X_EVM
-
-config SYS_BOARD
- default "ti814x"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "ti814x_evm"
-
-endif
+++ /dev/null
-TI814X BOARD
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-F: board/ti/ti814x/
-F: include/configs/ti814x_evm.h
-F: configs/ti814x_evm_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-
-ifdef CONFIG_SPL_BUILD
-obj-y := mux.o
-endif
-
-obj-y += evm.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * evm.c
- *
- * Board functions for TI814x EVM
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <cpsw.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <net.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include "evm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-static const struct cmd_control evm_ddr2_cctrl_data = {
- .cmd0csratio = 0x80,
- .cmd0iclkout = 0x00,
-
- .cmd1csratio = 0x80,
- .cmd1iclkout = 0x00,
-
- .cmd2csratio = 0x80,
- .cmd2iclkout = 0x00,
-};
-
-static const struct emif_regs evm_ddr2_emif0_regs = {
- .sdram_config = 0x40801ab2,
- .ref_ctrl = 0x10000c30,
- .sdram_tim1 = 0x0aaaf552,
- .sdram_tim2 = 0x043631d2,
- .sdram_tim3 = 0x00000327,
- .emif_ddr_phy_ctlr_1 = 0x00000007
-};
-
-static const struct emif_regs evm_ddr2_emif1_regs = {
- .sdram_config = 0x40801ab2,
- .ref_ctrl = 0x10000c30,
- .sdram_tim1 = 0x0aaaf552,
- .sdram_tim2 = 0x043631d2,
- .sdram_tim3 = 0x00000327,
- .emif_ddr_phy_ctlr_1 = 0x00000007
-};
-
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
- .dmm_lisa_map_0 = 0x00000000,
- .dmm_lisa_map_1 = 0x00000000,
- .dmm_lisa_map_2 = 0x806c0300,
- .dmm_lisa_map_3 = 0x806c0300,
-};
-
-static const struct ddr_data evm_ddr2_data = {
- .datardsratio0 = ((0x35<<10) | (0x35<<0)),
- .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
- .datawiratio0 = ((0<<10) | (0<<0)),
- .datagiratio0 = ((0<<10) | (0<<0)),
- .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
- .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
-};
-
-void set_uart_mux_conf(void)
-{
- /* Set UART pins */
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- /* Set MMC pins */
- enable_mmc1_pin_mux();
-
- /* Set Ethernet pins */
- enable_enet_pin_mux();
-}
-
-void sdram_init(void)
-{
- config_dmm(&evm_lisa_map_regs);
-
- config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
- &evm_ddr2_emif0_regs, 0);
- config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
- &evm_ddr2_emif1_regs, 1);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- return 0;
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(1, 0, 0, -1, -1);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x50,
- .sliver_reg_ofs = 0x700,
- .phy_addr = 1,
- },
- {
- .slave_reg_ofs = 0x90,
- .sliver_reg_ofs = 0x740,
- .phy_addr = 0,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x100,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0x600,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x28,
- .hw_stats_reg_ofs = 0x400,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_1,
-};
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- else
- printf("Unable to read MAC address. Set <ethaddr>\n");
- }
-
- return cpsw_register(&cpsw_data);
-}
+++ /dev/null
-#ifndef _EVM_H
-#define _EVM_H
-
-void enable_uart0_pin_mux(void);
-void enable_mmc1_pin_mux(void);
-void enable_enet_pin_mux(void);
-
-#endif /* _EVM_H */
+++ /dev/null
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "evm.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
- {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
- {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
- {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
- {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
- {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
- {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
- {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
- {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
- {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */
- {-1},
-};
-
-static struct module_pin_mux enet_pin_mux[] = {
- {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
- {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
- {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
- {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
- {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
- {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
- {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
- {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
- {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
- {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
- {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
- {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
- {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
- {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
- {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
- {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
- {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
- {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
- {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
- {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
- {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
- {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
- {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
- {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
- {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
- {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
- {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_mmc1_pin_mux(void)
-{
- configure_module_pin_mux(mmc1_pin_mux);
-}
-
-void enable_enet_pin_mux(void)
-{
- configure_module_pin_mux(enet_pin_mux);
-}
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100800U),
EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U),
EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U),
- EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U),
+ EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100800U),
EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U),
EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U),
EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
* Toradex Colibri PXA270 Support
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ * Copyright (C) 2016-2019 Marcel Ziswiler <marcel.ziswiler@toradex.com>
*/
#include <common.h>
#include <asm/arch/regs-uart.h>
#include <asm/io.h>
#include <dm/platdata.h>
+#include <dm/platform_data/pxa_mmc_gen.h>
#include <dm/platform_data/serial_pxa.h>
#include <netdev.h>
#include <serial.h>
/* arch number of Toradex Colibri PXA270 */
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
- /* adress of boot parameters */
+ /* address of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
return 0;
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+ writel(readl(UHCRHDB) | (0x7 << 17), UHCRHDB);
/* enable port 2 */
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
udelay(10);
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
}
#endif
#endif
#ifdef CONFIG_CMD_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
int board_mmc_init(bd_t *bis)
{
pxa_mmc_register(0);
return 0;
}
+#else /* !CONFIG_IS_ENABLED(DM_MMC) */
+static const struct pxa_mmc_plat mmc_platdata = {
+ .base = (struct pxa_mmc_regs *)MMC0_BASE,
+};
+
+U_BOOT_DEVICE(pxa_mmcs) = {
+ .name = "pxa_mmc",
+ .platdata = &mmc_platdata,
+};
+#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
#endif
static const struct pxa_serial_platdata serial_platdata = {
status = zynq_decrypt_load(part_load_addr,
part_img_len,
part_dst_addr,
- part_data_len);
+ part_data_len,
+ BIT_NONE);
if (status != 0) {
printf("DECRYPTION_FAIL\n");
return -1;
char *endp;
u32 srcaddr, srclen, dstaddr, dstlen;
int status;
+ u8 imgtype = BIT_NONE;
if (argc < 5 && argc > cmdtp->maxargs)
return CMD_RET_USAGE;
- srcaddr = simple_strtoul(argv[2], &endp, 16);
- if (*argv[2] == 0 || *endp != 0)
- return CMD_RET_USAGE;
- srclen = simple_strtoul(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- return CMD_RET_USAGE;
- dstaddr = simple_strtoul(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- return CMD_RET_USAGE;
- dstlen = simple_strtoul(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- return CMD_RET_USAGE;
+ if (argc == 5) {
+ if (!strcmp("load", argv[2]))
+ imgtype = BIT_FULL;
+ else if (!strcmp("loadp", argv[2]))
+ imgtype = BIT_PARTIAL;
+ else
+ return CMD_RET_USAGE;
+
+ srcaddr = simple_strtoul(argv[3], &endp, 16);
+ if (*argv[3] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ srclen = simple_strtoul(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+
+ dstaddr = 0xFFFFFFFF;
+ dstlen = srclen;
+ } else {
+ srcaddr = simple_strtoul(argv[2], &endp, 16);
+ if (*argv[2] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ srclen = simple_strtoul(argv[3], &endp, 16);
+ if (*argv[3] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ dstaddr = simple_strtoul(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ dstlen = simple_strtoul(argv[5], &endp, 16);
+ if (*argv[5] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ }
/*
* Roundup source and destination lengths to
if (dstlen % 4)
dstlen = roundup(dstlen, 4);
- status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2);
+ status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
+ dstlen >> 2, imgtype);
if (status != 0)
return CMD_RET_FAILURE;
" - Decrypts the encrypted image present in source\n"
" address and places the decrypted image at\n"
" destination address\n"
+ "aes load <srcaddr> <srclen>\n"
+ "aes loadp <srcaddr> <srclen>\n"
+ " if operation type is load or loadp, it loads the encrypted\n"
+ " full or partial bitstream on to PL respectively.\n"
#endif
;
#endif
}
#endif
+static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 addr, size;
+
+ if (argc != cmdtp->maxargs)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ size = simple_strtoul(argv[3], NULL, 16);
+ flush_dcache_range((ulong)addr, (ulong)(addr + size));
+
+ zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr,
+ (size_t)size);
+
+ return 0;
+}
+
static struct cmd_tbl cmd_zynqmp_sub[] = {
U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""),
+ U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""),
U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""),
U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""),
#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
" to be initialized. Supported modes will be\n"
" lock(0)/split(1)\n"
#endif
+ "zynqmp pmufw address size - load PMU FW configuration object\n"
;
#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010602U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02013C00U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF18030C, 0x00070007U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000300U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000C02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000600U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000103U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011802U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000C00U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000202U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000402U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x1A000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x023FEF1EU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x02A00F1EU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x01001FFFU);
+ psu_mask_write(0xFF180144, 0x02A00F1EU, 0x02A00F1EU);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FFFFFFU);
+ psu_mask_write(0xFF180160, 0x01FFFFFFU, 0x01FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFF7FFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0007FFF9U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x03FEDFBFU);
+ psu_mask_write(0xFF18017C, 0x01FFFFFFU, 0x01FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x01FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FFFFF4U);
+ psu_mask_write(0xFF180404, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+ psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+ psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+ psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+ mask_delay(1);
+ psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF0000U);
+ mask_delay(5);
+ psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+ psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+ psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+ psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+
+ mask_delay(1);
+ psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+ mask_delay(5);
+ psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+ psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+ psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U);
+ psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U);
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+ psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+ psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+ psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+ psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+ psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+ psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+ psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+ psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+ psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+ psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+ psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+ psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+ psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+ psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000082U);
+ psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+ psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U);
+ psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+ psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+ psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+ psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x000001FFU, 0x00000106U);
+ psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+ psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+ psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U);
+ psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+ psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+ psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+ psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U);
+ psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+ psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD380000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD3B0000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD380014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD3B0014, 0x00000003U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+ >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+ if (!pll_locked)
+ return 0;
+
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return 0;
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ int cur_R006_tREFPRD;
+
+ cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+ int count = 0;
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ xil_printf("#SERDES initialization timed out\n\r");
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if (p_code >= 0x26 && p_code <= 0x3C)
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if (n_code >= 0x26 && n_code <= 0x3C)
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if (i_code >= 0xC && i_code <= 0x12)
+ match_ical_code[i_code - 0xc] += 1;
+
+ if (r_code >= 0x6 && r_code <= 0xC)
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+static void psu_init_sdio_pinmux(void)
+{
+ if (Xil_In32(0xFF0A0064U) & (1U << 19)) {
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+
+ psu_mask_write(0xFF18030C, 0x00040000U, 0x00040000U);
+
+ psu_mask_write(0xFF180320, 0x33843384U, 0x02801284U);
+ } else {
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ }
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_peripherals_pre_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ psu_init_sdio_pinmux();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
multiboot = readl(&csu_base->multi_boot);
- printf("Multiboot:\t%x\n", multiboot);
+ printf("Multiboot:\t%d\n", multiboot);
return 0;
}
+#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
+#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
+
int board_init(void)
{
#if defined(CONFIG_ZYNQMP_FIRMWARE)
printf("EL Level:\tEL%d\n", current_el());
+ /* Bug in ROM sets wrong value in this register */
+ writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
+
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
!defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
defined(CONFIG_SPL_BUILD))
help
Load an S-Record file over serial line
+config CMD_LSBLK
+ depends on BLK
+ bool "lsblk - list block drivers and devices"
+ help
+ Print list of available block device drivers, and for each, the list
+ of known block devices.
+
config CMD_MMC
bool "mmc"
help
obj-$(CONFIG_CMD_LICENSE) += license.o
obj-y += load.o
obj-$(CONFIG_CMD_LOG) += log.o
+obj-$(CONFIG_CMD_LSBLK) += lsblk.o
obj-$(CONFIG_ID_EEPROM) += mac.o
obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
obj-$(CONFIG_CMD_MEMORY) += mem.o
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Implements the 'bd' command to show board information
+ *
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-/*
- * Boot support
- */
#include <common.h>
#include <command.h>
#include <env.h>
#include <net.h>
#include <vsprintf.h>
#include <asm/cache.h>
-#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-__maybe_unused void print_cpu_word_size(void)
-{
- printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
-}
-
-__maybe_unused
-static void print_num(const char *name, ulong value)
+void bdinfo_print_num(const char *name, ulong value)
{
printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value);
}
-__maybe_unused
static void print_eth(int idx)
{
char name[10], *val;
printf("%-12s= %s\n", name, val);
}
-#ifndef CONFIG_DM_ETH
-__maybe_unused
-static void print_eths(void)
-{
- struct eth_device *dev;
- int i = 0;
-
- do {
- dev = eth_get_dev_by_index(i);
- if (dev) {
- printf("eth%dname = %s\n", i, dev->name);
- print_eth(i);
- i++;
- }
- } while (dev);
-
- printf("current eth = %s\n", eth_get_name());
- printf("ip_addr = %s\n", env_get("ipaddr"));
-}
-#endif
-
-__maybe_unused
static void print_lnum(const char *name, unsigned long long value)
{
printf("%-12s= 0x%.8llX\n", name, value);
}
-__maybe_unused
-static void print_mhz(const char *name, unsigned long hz)
+void bdinfo_print_mhz(const char *name, unsigned long hz)
{
char buf[32];
printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
}
-
-static inline void print_bi_boot_params(const bd_t *bd)
-{
- print_num("boot_params", (ulong)bd->bi_boot_params);
-}
-
-static inline void print_bi_mem(const bd_t *bd)
-{
-#if defined(CONFIG_SH)
- print_num("mem start ", (ulong)bd->bi_memstart);
- print_lnum("mem size ", (u64)bd->bi_memsize);
-#elif defined(CONFIG_ARC)
- print_num("mem start", (ulong)bd->bi_memstart);
- print_lnum("mem size", (u64)bd->bi_memsize);
-#else
- print_num("memstart", (ulong)bd->bi_memstart);
- print_lnum("memsize", (u64)bd->bi_memsize);
-#endif
-}
-
-static inline void print_bi_dram(const bd_t *bd)
+static void print_bi_dram(const bd_t *bd)
{
#ifdef CONFIG_NR_DRAM_BANKS
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
- print_num("DRAM bank", i);
- print_num("-> start", bd->bi_dram[i].start);
- print_num("-> size", bd->bi_dram[i].size);
+ bdinfo_print_num("DRAM bank", i);
+ bdinfo_print_num("-> start", bd->bi_dram[i].start);
+ bdinfo_print_num("-> size", bd->bi_dram[i].size);
}
}
#endif
}
-static inline void print_bi_flash(const bd_t *bd)
-{
-#if defined(CONFIG_MICROBLAZE) || defined(CONFIG_SH)
- print_num("flash start ", (ulong)bd->bi_flashstart);
- print_num("flash size ", (ulong)bd->bi_flashsize);
- print_num("flash offset ", (ulong)bd->bi_flashoffset);
-
-#elif defined(CONFIG_NIOS2)
- print_num("flash start", (ulong)bd->bi_flashstart);
- print_num("flash size", (ulong)bd->bi_flashsize);
- print_num("flash offset", (ulong)bd->bi_flashoffset);
-#else
- print_num("flashstart", (ulong)bd->bi_flashstart);
- print_num("flashsize", (ulong)bd->bi_flashsize);
- print_num("flashoffset", (ulong)bd->bi_flashoffset);
-#endif
-}
-
-static inline void print_eth_ip_addr(void)
+__weak void arch_print_bdinfo(void)
{
-#if defined(CONFIG_CMD_NET)
- print_eth(0);
-#if defined(CONFIG_HAS_ETH1)
- print_eth(1);
-#endif
-#if defined(CONFIG_HAS_ETH2)
- print_eth(2);
-#endif
-#if defined(CONFIG_HAS_ETH3)
- print_eth(3);
-#endif
-#if defined(CONFIG_HAS_ETH4)
- print_eth(4);
-#endif
-#if defined(CONFIG_HAS_ETH5)
- print_eth(5);
-#endif
- printf("IP addr = %s\n", env_get("ipaddr"));
-#endif
-}
-
-static inline void print_baudrate(void)
-{
-#if defined(CONFIG_PPC)
- printf("baudrate = %6u bps\n", gd->baudrate);
-#else
- printf("baudrate = %u bps\n", gd->baudrate);
-#endif
-}
-
-static inline void __maybe_unused print_std_bdinfo(const bd_t *bd)
-{
- print_bi_boot_params(bd);
- print_bi_mem(bd);
- print_bi_flash(bd);
- print_eth_ip_addr();
- print_baudrate();
-}
-
-#if defined(CONFIG_PPC)
-void __weak board_detail(void)
-{
- /* Please define board_detail() for your platform */
}
int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
bd_t *bd = gd->bd;
#ifdef DEBUG
- print_num("bd address", (ulong)bd);
-#endif
- print_bi_mem(bd);
- print_bi_flash(bd);
- print_num("sramstart", bd->bi_sramstart);
- print_num("sramsize", bd->bi_sramsize);
-#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
- print_num("immr_base", bd->bi_immr_base);
-#endif
- print_num("bootflags", bd->bi_bootflags);
-#if defined(CONFIG_CPM2)
- print_mhz("vco", bd->bi_vco);
- print_mhz("sccfreq", bd->bi_sccfreq);
- print_mhz("brgfreq", bd->bi_brgfreq);
-#endif
- print_mhz("intfreq", bd->bi_intfreq);
-#if defined(CONFIG_CPM2)
- print_mhz("cpmfreq", bd->bi_cpmfreq);
+ bdinfo_print_num("bd address", (ulong)bd);
#endif
- print_mhz("busfreq", bd->bi_busfreq);
-
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
- puts("addressing = 36-bit\n");
-#else
- puts("addressing = 32-bit\n");
-#endif
-#endif
-
- print_eth_ip_addr();
- print_baudrate();
- print_num("relocaddr", gd->relocaddr);
- board_detail();
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_NIOS2)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_dram(bd);
- print_bi_flash(bd);
-
-#if defined(CONFIG_SYS_SRAM_BASE)
- print_num ("sram start", (ulong)bd->bi_sramstart);
- print_num ("sram size", (ulong)bd->bi_sramsize);
-#endif
-
- print_eth_ip_addr();
- print_baudrate();
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_MICROBLAZE)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_dram(bd);
- print_bi_flash(bd);
-#if defined(CONFIG_SYS_SRAM_BASE)
- print_num("sram start ", (ulong)bd->bi_sramstart);
- print_num("sram size ", (ulong)bd->bi_sramsize);
-#endif
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
- print_eths();
-#endif
- print_baudrate();
- print_num("relocaddr", gd->relocaddr);
- print_num("reloc off", gd->reloc_off);
- print_num("fdt_blob", (ulong)gd->fdt_blob);
- print_num("new_fdt", (ulong)gd->new_fdt);
- print_num("fdt_size", (ulong)gd->fdt_size);
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_M68K)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_mem(bd);
- print_bi_flash(bd);
-#if defined(CONFIG_SYS_INIT_RAM_ADDR)
- print_num("sramstart", (ulong)bd->bi_sramstart);
- print_num("sramsize", (ulong)bd->bi_sramsize);
-#endif
-#if defined(CONFIG_SYS_MBAR)
- print_num("mbar", bd->bi_mbar_base);
-#endif
- print_mhz("cpufreq", bd->bi_intfreq);
- print_mhz("busfreq", bd->bi_busfreq);
-#ifdef CONFIG_PCI
- print_mhz("pcifreq", bd->bi_pcifreq);
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
- print_mhz("flbfreq", bd->bi_flbfreq);
- print_mhz("inpfreq", bd->bi_inpfreq);
- print_mhz("vcofreq", bd->bi_vcofreq);
-#endif
- print_eth_ip_addr();
- print_baudrate();
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_MIPS)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- print_std_bdinfo(gd->bd);
- print_num("relocaddr", gd->relocaddr);
- print_num("reloc off", gd->reloc_off);
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_ARM)
-
-static int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_num("arch_number", bd->bi_arch_number);
- print_bi_boot_params(bd);
+ bdinfo_print_num("boot_params", (ulong)bd->bi_boot_params);
print_bi_dram(bd);
-
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
- print_num("Secure ram",
- gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
+ bdinfo_print_num("memstart", (ulong)bd->bi_memstart);
+ print_lnum("memsize", (u64)bd->bi_memsize);
+ bdinfo_print_num("flashstart", (ulong)bd->bi_flashstart);
+ bdinfo_print_num("flashsize", (ulong)bd->bi_flashsize);
+ bdinfo_print_num("flashoffset", (ulong)bd->bi_flashoffset);
+ printf("baudrate = %u bps\n", gd->baudrate);
+ bdinfo_print_num("relocaddr", gd->relocaddr);
+ bdinfo_print_num("reloc off", gd->reloc_off);
+ printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
+ if (IS_ENABLED(CONFIG_CMD_NET)) {
+ printf("current eth = %s\n", eth_get_name());
+ print_eth(0);
+ printf("IP addr = %s\n", env_get("ipaddr"));
}
-#endif
-#ifdef CONFIG_RESV_RAM
- if (gd->arch.resv_ram)
- print_num("Reserved ram", gd->arch.resv_ram);
-#endif
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
- print_eths();
-#endif
- print_baudrate();
-#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
- print_num("TLB addr", gd->arch.tlb_addr);
-#endif
- print_num("relocaddr", gd->relocaddr);
- print_num("reloc off", gd->reloc_off);
- print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
- print_num("sp start ", gd->start_addr_sp);
+ bdinfo_print_num("fdt_blob", (ulong)gd->fdt_blob);
+ bdinfo_print_num("new_fdt", (ulong)gd->new_fdt);
+ bdinfo_print_num("fdt_size", (ulong)gd->fdt_size);
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
- print_num("FB base ", gd->fb_base);
-#endif
- /*
- * TODO: Currently only support for davinci SOC's is added.
- * Remove this check once all the board implement this.
- */
-#ifdef CONFIG_CLOCKS
- printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
- printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
- printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
-#endif
-#ifdef CONFIG_BOARD_TYPES
- printf("Board Type = %ld\n", gd->board_type);
-#endif
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
- printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
- CONFIG_VAL(SYS_MALLOC_F_LEN));
+ bdinfo_print_num("FB base ", gd->fb_base);
#endif
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
- print_num("multi_dtb_fit", (ulong)gd->multi_dtb_fit);
-#endif
- if (gd->fdt_blob)
- print_num("fdt_blob", (ulong)gd->fdt_blob);
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_SH)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_mem(bd);
- print_bi_flash(bd);
- print_eth_ip_addr();
- print_baudrate();
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_X86)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_boot_params(bd);
-
- print_bi_dram(bd);
-
- print_num("relocaddr", gd->relocaddr);
- print_num("reloc off", gd->reloc_off);
-#if defined(CONFIG_CMD_NET)
- print_eth_ip_addr();
- print_mhz("ethspeed", bd->bi_ethspeed);
-#endif
- print_baudrate();
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_SANDBOX)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_boot_params(bd);
- print_bi_dram(bd);
- print_eth_ip_addr();
-
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
- print_num("FB base ", gd->fb_base);
+ bdinfo_print_num("multi_dtb_fit", (ulong)gd->multi_dtb_fit);
#endif
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_NDS32)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_num("arch_number", bd->bi_arch_number);
- print_bi_boot_params(bd);
- print_bi_dram(bd);
- print_eth_ip_addr();
- print_baudrate();
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_RISCV)
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_boot_params(bd);
- print_bi_dram(bd);
- print_num("relocaddr", gd->relocaddr);
- print_num("reloc off", gd->reloc_off);
- print_eth_ip_addr();
- print_baudrate();
- print_cpu_word_size();
+ arch_print_bdinfo();
return 0;
}
-#elif defined(CONFIG_ARC)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_mem(bd);
- print_eth_ip_addr();
- print_baudrate();
- print_cpu_word_size();
-
- return 0;
-}
-
-#elif defined(CONFIG_XTENSA)
-
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- print_std_bdinfo(gd->bd);
- return 0;
-}
-
-#else
- #error "a case for this architecture does not exist!"
-#endif
-
-/* -------------------------------------------------------------------- */
-
U_BOOT_CMD(
bdinfo, 1, 1, do_bdinfo,
"print Board Info structure",
return 0;
}
+static int do_dm_dump_driver_compat(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ dm_dump_driver_compat();
+
+ return 0;
+}
+
+static int do_dm_dump_static_driver_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ dm_dump_static_driver_info();
+
+ return 0;
+}
+
static struct cmd_tbl test_commands[] = {
U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""),
U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""),
U_BOOT_CMD_MKENT(devres, 1, 1, do_dm_dump_devres, "", ""),
U_BOOT_CMD_MKENT(drivers, 1, 1, do_dm_dump_drivers, "", ""),
+ U_BOOT_CMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat, "", ""),
+ U_BOOT_CMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info, "", ""),
};
static __maybe_unused void dm_reloc(void)
"tree Dump driver model tree ('*' = activated)\n"
"dm uclass Dump list of instances for each uclass\n"
"dm devres Dump list of device resources for each device\n"
- "dm drivers Dump list of drivers and their compatible strings"
+ "dm drivers Dump list of drivers with uclass and instances\n"
+ "dm compat Dump list of drivers with compatibility strings\n"
+ "dm static Dump list of drivers with static platform data"
);
"fstype <interface> <dev>:<part> <varname>\n"
"- set environment variable to filesystem type\n"
);
+
+static int do_fstypes_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_fs_types(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ fstypes, 1, 1, do_fstypes_wrapper,
+ "List supported filesystem types", ""
+);
static int do_log_level(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- if (argc > 1)
- gd->default_log_level = simple_strtol(argv[1], NULL, 10);
- else
+ if (argc > 1) {
+ long log_level = simple_strtol(argv[1], NULL, 10);
+
+ if (log_level < 0 || log_level > _LOG_MAX_LEVEL) {
+ printf("Only log levels <= %d are supported\n",
+ _LOG_MAX_LEVEL);
+ return CMD_RET_FAILURE;
+ }
+ gd->default_log_level = log_level;
+ } else {
printf("Default log level: %d\n", gd->default_log_level);
+ }
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020
+ * Niel Fourie, DENX Software Engineering, lusus@denx.de.
+ */
+
+#include <common.h>
+#include <dm.h>
+
+static int do_lsblk(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct driver *d = ll_entry_start(struct driver, driver);
+ const int n_ents = ll_entry_count(struct driver, driver);
+ struct driver *entry;
+ struct udevice *udev;
+ struct uclass *uc;
+ struct blk_desc *desc;
+ int ret, i;
+
+ ret = uclass_get(UCLASS_BLK, &uc);
+ if (ret) {
+ puts("Could not get BLK uclass.\n");
+ return CMD_RET_FAILURE;
+ }
+ puts("Block Driver Devices\n");
+ puts("-----------------------------\n");
+ for (entry = d; entry < d + n_ents; entry++) {
+ if (entry->id != UCLASS_BLK)
+ continue;
+ i = 0;
+ printf("%-20.20s", entry->name);
+ uclass_foreach_dev(udev, uc) {
+ if (udev->driver != entry)
+ continue;
+ desc = dev_get_uclass_platdata(udev);
+ printf("%c %s %u", i ? ',' : ':',
+ blk_get_if_type_name(desc->if_type),
+ desc->devnum);
+ i++;
+ }
+ if (!i)
+ puts(": <none>");
+ puts("\n");
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(lsblk, 1, 0, do_lsblk, "list block drivers and devices",
+ "- display list of block device drivers and attached block devices"
+);
env_set("netmask", tmp);
}
+#ifdef CONFIG_CMD_BOOTP
if (net_hostname[0])
env_set("hostname", net_hostname);
+#endif
+#ifdef CONFIG_CMD_BOOTP
if (net_root_path[0])
env_set("rootpath", net_root_path);
+#endif
if (net_ip.s_addr) {
ip_to_string(net_ip, tmp);
env_set("dnsip2", tmp);
}
#endif
+#ifdef CONFIG_CMD_BOOTP
if (net_nis_domain[0])
env_set("domain", net_nis_domain);
+#endif
#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET)
if (net_ntp_time_offset) {
/* evaluate whether environment can be persisted */
if (eval_flags & ENV_INFO_IS_PERSISTED) {
-#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
printf("Environment can be persisted\n");
eval_results |= ENV_INFO_IS_PERSISTED;
#else
return do_part_info(argc, argv, CMD_PART_INFO_NUMBER);
}
+static int do_part_types(int argc, char * const argv[])
+{
+ struct part_driver *drv = ll_entry_start(struct part_driver,
+ part_driver);
+ const int n_ents = ll_entry_count(struct part_driver, part_driver);
+ struct part_driver *entry;
+ int i = 0;
+
+ puts("Supported partition tables");
+
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ printf("%c %s", i ? ',' : ':', entry->name);
+ i++;
+ }
+ if (!i)
+ puts(": <none>");
+ puts("\n");
+ return CMD_RET_SUCCESS;
+}
+
static int do_part(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
return do_part_size(argc - 2, argv + 2);
else if (!strcmp(argv[1], "number"))
return do_part_number(argc - 2, argv + 2);
-
+ else if (!strcmp(argv[1], "types"))
+ return do_part_types(argc - 2, argv + 2);
return CMD_RET_USAGE;
}
" part can be either partition number or partition name\n"
"part number <interface> <dev> <part> <varname>\n"
" - set environment variable to the partition number using the partition name\n"
- " part must be specified as partition name"
+ " part must be specified as partition name\n"
+ "part types\n"
+ " - list supported partition table types"
);
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
-#ifdef CONFIG_DM_SPI_FLASH
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
struct udevice *new, *bus_dev;
int ret;
#else
return -1;
}
-#ifdef CONFIG_DM_SPI_FLASH
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
/* Remove the old device, otherwise probe will just be a nop */
ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new);
if (!ret) {
struct spi_slave *slave;
int ret = 0;
-#ifdef CONFIG_DM_SPI
+#if CONFIG_IS_ENABLED(DM_SPI)
char name[30], *str;
struct udevice *dev;
goto done;
ret = spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END);
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
/* We don't get an error code in this case */
if (ret)
ret = -EIO;
}
done:
spi_release_bus(slave);
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
spi_free_slave(slave);
#endif
discarded if not needed. Logging supports various categories and
levels of severity.
-config SPL_LOG
- bool "Enable logging support in SPL"
- depends on LOG
- help
- This enables support for logging of status and debug messages. These
- can be displayed on the console, recorded in a memory buffer, or
- discarded if not needed. Logging supports various categories and
- levels of severity.
-
-config TPL_LOG
- bool "Enable logging support in TPL"
- depends on LOG
- help
- This enables support for logging of status and debug messages. These
- can be displayed on the console, recorded in a memory buffer, or
- discarded if not needed. Logging supports various categories and
- levels of severity.
+if LOG
config LOG_MAX_LEVEL
int "Maximum log level to record"
- depends on LOG
- default 5
+ default 6
+ range 0 9
help
This selects the maximum log level that will be recorded. Any value
higher than this will be ignored. If possible log statements below
8 - debug content
9 - debug hardware I/O
-config SPL_LOG_MAX_LEVEL
- int "Maximum log level to record in SPL"
- depends on SPL_LOG
- default 3
+config LOG_DEFAULT_LEVEL
+ int "Default logging level to display"
+ default LOG_MAX_LEVEL
+ range 0 LOG_MAX_LEVEL
help
- This selects the maximum log level that will be recorded. Any value
- higher than this will be ignored. If possible log statements below
- this level will be discarded at build time. Levels:
+ This is the default logging level set when U-Boot starts. It can
+ be adjusted later using the 'log level' command. Note that setting
+ this to a value above LOG_MAX_LEVEL will be ineffective, since the
+ higher levels are not compiled in to U-Boot.
0 - emergency
1 - alert
8 - debug content
9 - debug hardware I/O
-config TPL_LOG_MAX_LEVEL
- int "Maximum log level to record in TPL"
- depends on TPL_LOG
+config LOG_CONSOLE
+ bool "Allow log output to the console"
+ default y
+ help
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
+config LOG_SYSLOG
+ bool "Log output to syslog server"
+ depends on NET
+ help
+ Enables a log driver which broadcasts log records via UDP port 514
+ to syslog servers.
+
+config SPL_LOG
+ bool "Enable logging support in SPL"
+ depends on LOG
+ help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+if SPL_LOG
+
+config SPL_LOG_MAX_LEVEL
+ int "Maximum log level to record in SPL"
+ depends on SPL_LOG
default 3
+ range 0 9
help
This selects the maximum log level that will be recorded. Any value
higher than this will be ignored. If possible log statements below
8 - debug content
9 - debug hardware I/O
-config LOG_DEFAULT_LEVEL
- int "Default logging level to display"
- default 6
+config SPL_LOG_CONSOLE
+ bool "Allow log output to the console in SPL"
+ default y
help
- This is the default logging level set when U-Boot starts. It can
- be adjusted later using the 'log level' command. Note that setting
- this to a value above LOG_MAX_LEVEL will be ineffective, since the
- higher levels are not compiled in to U-Boot.
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
+endif
+
+config TPL_LOG
+ bool "Enable logging support in TPL"
+ depends on LOG
+ help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+if TPL_LOG
+
+config TPL_LOG_MAX_LEVEL
+ int "Maximum log level to record in TPL"
+ depends on TPL_LOG
+ default 3
+ range 0 9
+ help
+ This selects the maximum log level that will be recorded. Any value
+ higher than this will be ignored. If possible log statements below
+ this level will be discarded at build time. Levels:
0 - emergency
1 - alert
8 - debug content
9 - debug hardware I/O
-config LOG_CONSOLE
- bool "Allow log output to the console"
- depends on LOG
- default y
- help
- Enables a log driver which writes log records to the console.
- Generally the console is the serial port or LCD display. Only the
- log message is shown - other details like level, category, file and
- line number are omitted.
-
-config SPL_LOG_CONSOLE
- bool "Allow log output to the console in SPL"
- depends on SPL_LOG
- default y
- help
- Enables a log driver which writes log records to the console.
- Generally the console is the serial port or LCD display. Only the
- log message is shown - other details like level, category, file and
- line number are omitted.
-
config TPL_LOG_CONSOLE
bool "Allow log output to the console in TPL"
- depends on TPL_LOG
default y
help
Enables a log driver which writes log records to the console.
log message is shown - other details like level, category, file and
line number are omitted.
-config LOG_SYSLOG
- bool "Log output to syslog server"
- depends on LOG && NET
- help
- Enables a log driver which broadcasts log records via UDP port 514
- to syslog servers.
-
-config LOG_TEST
- bool "Provide a test for logging"
- depends on LOG && UNIT_TEST
- default y if SANDBOX
- help
- This enables a 'log test' command to test logging. It is normally
- executed from a pytest and simply outputs logging information
- in various different ways to test that the logging system works
- correctly with various settings.
+endif
config LOG_ERROR_RETURN
bool "Log all functions which return an error"
- depends on LOG
help
When an error is returned in U-Boot it is sometimes difficult to
figure out the root cause. For example, reading from SPI flash may
You can add log_ret() to all functions which return an error code.
+config LOG_TEST
+ bool "Provide a test for logging"
+ depends on UNIT_TEST
+ default y if SANDBOX
+ help
+ This enables a 'log test' command to test logging. It is normally
+ executed from a pytest and simply outputs logging information
+ in various different ways to test that the logging system works
+ correctly with various settings.
+
+endif
+
endmenu
config SUPPORT_RAW_INITRD
* will be relocated with other data.
*/
if (gd->fdt_blob) {
- gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+ gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
if (gd->new_fdt) {
- memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
+ memcpy(gd->new_fdt, gd->fdt_blob, fdt_totalsize(gd->fdt_blob));
gd->fdt_blob = gd->new_fdt;
}
#endif
/* kept around for legacy kernels only ... ignore the next section */
eth_env_get_enetaddr("ethaddr", bd->bi_enetaddr);
-#ifdef CONFIG_HAS_ETH1
- eth_env_get_enetaddr("eth1addr", bd->bi_enet1addr);
-#endif
-#ifdef CONFIG_HAS_ETH2
- eth_env_get_enetaddr("eth2addr", bd->bi_enet2addr);
-#endif
-#ifdef CONFIG_HAS_ETH3
- eth_env_get_enetaddr("eth3addr", bd->bi_enet3addr);
-#endif
-#ifdef CONFIG_HAS_ETH4
- eth_env_get_enetaddr("eth4addr", bd->bi_enet4addr);
-#endif
-#ifdef CONFIG_HAS_ETH5
- eth_env_get_enetaddr("eth5addr", bd->bi_enet5addr);
-#endif
+
return 0;
}
#endif /* CONFIG_CMD_NET */
dev = stdio_get_by_name(name);
#ifdef CONFIG_VIDCONSOLE_AS_LCD
- if (!dev && !strcmp(name, "lcd"))
+ if (!dev && !strcmp(name, CONFIG_VIDCONSOLE_AS_NAME))
dev = stdio_get_by_name("vidconsole");
#endif
stdio_print_current_devices();
#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
#ifdef CONFIG_VIDCONSOLE_AS_LCD
- if (strstr(stdoutname, "lcd"))
- printf("Warning: Please change 'lcd' to 'vidconsole' in stdout/stderr environment vars\n");
+ if (strstr(stdoutname, CONFIG_VIDCONSOLE_AS_NAME))
+ printf("Warning: Please change '%s' to 'vidconsole' in stdout/stderr environment vars\n",
+ CONFIG_VIDCONSOLE_AS_NAME);
#endif
#ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#include <u-boot/crc.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
#include <u-boot/md5.h>
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
}
#endif
+#if defined(CONFIG_SHA384)
+static int hash_init_sha384(struct hash_algo *algo, void **ctxp)
+{
+ sha512_context *ctx = malloc(sizeof(sha512_context));
+ sha384_starts(ctx);
+ *ctxp = ctx;
+ return 0;
+}
+
+static int hash_update_sha384(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size, int is_last)
+{
+ sha384_update((sha512_context *)ctx, buf, size);
+ return 0;
+}
+
+static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void
+ *dest_buf, int size)
+{
+ if (size < algo->digest_size)
+ return -1;
+
+ sha384_finish((sha512_context *)ctx, dest_buf);
+ free(ctx);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SHA512)
+static int hash_init_sha512(struct hash_algo *algo, void **ctxp)
+{
+ sha512_context *ctx = malloc(sizeof(sha512_context));
+ sha512_starts(ctx);
+ *ctxp = ctx;
+ return 0;
+}
+
+static int hash_update_sha512(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size, int is_last)
+{
+ sha512_update((sha512_context *)ctx, buf, size);
+ return 0;
+}
+
+static int hash_finish_sha512(struct hash_algo *algo, void *ctx, void
+ *dest_buf, int size)
+{
+ if (size < algo->digest_size)
+ return -1;
+
+ sha512_finish((sha512_context *)ctx, dest_buf);
+ free(ctx);
+ return 0;
+}
+#endif
+
+
static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp)
{
uint16_t *ctx = malloc(sizeof(uint16_t));
#endif
},
#endif
+#ifdef CONFIG_SHA384
+ {
+ .name = "sha384",
+ .digest_size = SHA384_SUM_LEN,
+ .chunk_size = CHUNKSZ_SHA384,
+ .hash_func_ws = sha384_csum_wd,
+ .hash_init = hash_init_sha384,
+ .hash_update = hash_update_sha384,
+ .hash_finish = hash_finish_sha384,
+ },
+#endif
+#ifdef CONFIG_SHA512
+ {
+ .name = "sha512",
+ .digest_size = SHA512_SUM_LEN,
+ .chunk_size = CHUNKSZ_SHA512,
+ .hash_func_ws = sha512_csum_wd,
+ .hash_init = hash_init_sha512,
+ .hash_update = hash_update_sha512,
+ .hash_finish = hash_finish_sha512,
+ },
+#endif
{
.name = "crc16-ccitt",
.digest_size = 2,
/* Try to minimize code size for boards that don't want much hashing */
#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM) || \
- defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH)
+ defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH) || \
+ defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
#define multi_hash() 1
#else
#define multi_hash() 0
#include <u-boot/md5.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
/*****************************************************************************/
/* New uImage format routines */
sha256_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA256);
*value_len = SHA256_SUM_LEN;
+ } else if (IMAGE_ENABLE_SHA384 && strcmp(algo, "sha384") == 0) {
+ sha384_csum_wd((unsigned char *)data, data_len,
+ (unsigned char *)value, CHUNKSZ_SHA384);
+ *value_len = SHA384_SUM_LEN;
+ } else if (IMAGE_ENABLE_SHA512 && strcmp(algo, "sha512") == 0) {
+ sha512_csum_wd((unsigned char *)data, data_len,
+ (unsigned char *)value, CHUNKSZ_SHA512);
+ *value_len = SHA512_SUM_LEN;
} else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
*value_len = 16;
.calculate_sign = EVP_sha256,
#endif
.calculate = hash_calculate,
- }
+ },
+#ifdef CONFIG_SHA384
+ {
+ .name = "sha384",
+ .checksum_len = SHA384_SUM_LEN,
+ .der_len = SHA384_DER_LEN,
+ .der_prefix = sha384_der_prefix,
+#if IMAGE_ENABLE_SIGN
+ .calculate_sign = EVP_sha384,
+#endif
+ .calculate = hash_calculate,
+ },
+#endif
+#ifdef CONFIG_SHA512
+ {
+ .name = "sha512",
+ .checksum_len = SHA512_SUM_LEN,
+ .der_len = SHA512_DER_LEN,
+ .der_prefix = sha512_der_prefix,
+#if IMAGE_ENABLE_SIGN
+ .calculate_sign = EVP_sha512,
+#endif
+ .calculate = hash_calculate,
+ },
+#endif
};
#include <lzma/LzmaTypes.h>
#include <lzma/LzmaDec.h>
#include <lzma/LzmaTools.h>
+#include <linux/zstd.h>
#ifdef CONFIG_CMD_BDI
extern int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
{ IH_COMP_LZMA, "lzma", "lzma compressed", },
{ IH_COMP_LZO, "lzo", "lzo compressed", },
{ IH_COMP_LZ4, "lz4", "lz4 compressed", },
+ { IH_COMP_ZSTD, "zstd", "zstd compressed", },
{ -1, "", "", },
};
break;
}
#endif /* CONFIG_LZ4 */
+#ifdef CONFIG_ZSTD
+ case IH_COMP_ZSTD: {
+ size_t size = unc_len;
+ ZSTD_DStream *dstream;
+ ZSTD_inBuffer in_buf;
+ ZSTD_outBuffer out_buf;
+ void *workspace;
+ size_t wsize;
+
+ wsize = ZSTD_DStreamWorkspaceBound(image_len);
+ workspace = malloc(wsize);
+ if (!workspace) {
+ debug("%s: cannot allocate workspace of size %zu\n", __func__,
+ wsize);
+ return -1;
+ }
+
+ dstream = ZSTD_initDStream(image_len, workspace, wsize);
+ if (!dstream) {
+ printf("%s: ZSTD_initDStream failed\n", __func__);
+ return ZSTD_getErrorCode(ret);
+ }
+
+ in_buf.src = image_buf;
+ in_buf.pos = 0;
+ in_buf.size = image_len;
+
+ out_buf.dst = load_buf;
+ out_buf.pos = 0;
+ out_buf.size = size;
+
+ while (1) {
+ size_t ret;
+
+ ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
+ if (ZSTD_isError(ret)) {
+ printf("%s: ZSTD_decompressStream error %d\n", __func__,
+ ZSTD_getErrorCode(ret));
+ return ZSTD_getErrorCode(ret);
+ }
+
+ if (in_buf.pos >= image_len || !ret)
+ break;
+ }
+
+ image_len = out_buf.pos;
+
+ break;
+ }
+#endif /* CONFIG_ZSTD */
default:
printf("Unimplemented compression type %d\n", comp);
return -ENOSYS;
secure as it is possible (with a brute-force attack) to adjust the
image while still retaining the same MD5 hash value. For secure
applications where images may be changed maliciously, you should
- consider SHA1 or SHA256.
+ consider SHA256 or SHA384.
config SPL_SHA1_SUPPORT
bool "Support SHA1"
image contents have not been corrupted or maliciously altered.
While SHA1 is fairly secure it is coming to the end of its life
due to the expanding computing power available to brute-force
- attacks. For more security, consider SHA256.
+ attacks. For more security, consider SHA256 or SHA384.
config SPL_SHA256_SUPPORT
bool "Support SHA256"
help
Enable this to support SHA256 in FIT images within SPL. A SHA256
checksum is a 256-bit (32-byte) hash value used to check that the
- image contents have not been corrupted. SHA256 is recommended for
- use in secure applications since (as at 2016) there is no known
- feasible attack that could produce a 'collision' with differing
- input data. Use this for the highest security. Note that only the
- SHA256 variant is supported: SHA512 and others are not currently
- supported in U-Boot.
+ image contents have not been corrupted.
+
+config SPL_SHA384_SUPPORT
+ bool "Support SHA384"
+ depends on SPL_FIT
+ select SHA384
+ select SHA512_ALGO
+ help
+ Enable this to support SHA384 in FIT images within SPL. A SHA384
+ checksum is a 384-bit (48-byte) hash value used to check that the
+ image contents have not been corrupted. Use this for the highest
+ security.
+
+config SPL_SHA512_SUPPORT
+ bool "Support SHA512"
+ depends on SPL_FIT
+ select SHA512
+ select SHA512_ALGO
+ help
+ Enable this to support SHA512 in FIT images within SPL. A SHA512
+ checksum is a 512-bit (64-byte) hash value used to check that the
+ image contents have not been corrupted.
config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
help
Enable support for SPI DM drivers in SPL.
+config SPL_DM_SPI_FLASH
+ bool "Support SPI DM FLASH drivers in SPL"
+ help
+ Enable support for SPI DM flash drivers in SPL.
+
endif
if SPL_UBI
config SPL_UBI_LOAD_BY_VOLNAME
SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
tables as per JESD216 standard in SPL.
+config SPL_SPI_FLASH_MTD
+ bool "Support for SPI flash MTD drivers in SPL"
+ help
+ Enable support for SPI flash MTD drivers in SPL.
+
config SPL_SPI_LOAD
bool "Support loading from SPI flash"
help
Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for
details.
+config TPL_DM_SPI
+ bool "Support SPI DM drivers in TPL"
+ help
+ Enable support for SPI DM drivers in TPL.
+
+config TPL_DM_SPI_FLASH
+ bool "Support SPI DM FLASH drivers in TPL"
+ help
+ Enable support for SPI DM flash drivers in TPL.
+
config TPL_YMODEM_SUPPORT
bool "Support loading using Ymodem"
depends on TPL_SERIAL_SUPPORT
invalidate_icache_all();
#ifdef CONFIG_SPL_SMP
+ /* Initialize the IPI before we use it */
+ ret = riscv_init_ipi();
+ if (ret)
+ hang();
+
/*
* Start OpenSBI on all secondary harts and wait for acknowledgment.
*
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x8FF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x8FF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x100000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_OF_LIBFDT=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
+CONFIG_EEPRO100=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xf8f40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xf8f40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xF0000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
+CONFIG_EEPRO100=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1_TWR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:256k(vsc7385-firmware),256k(dtb),5632k(kernel),57856k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SATA_SIL3114=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_LED is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50"
CONFIG_CMD_NAND=y
# CONFIG_CMD_SPI is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_TIME is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
CONFIG_AM43XX=y
CONFIG_ENV_OFFSET_REDUND=0x120000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI,QSPI_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP54XX=y
CONFIG_TARGET_AM57XX_EVM=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
+CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_AB_SELECT=y
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_PMIC is not set
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_AB_SELECT=y
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_PMIC is not set
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x40306D50
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
+CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_USB_GADGET=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_AB_SELECT=y
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_PMIC is not set
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_PROMPT="Apalis TK1 # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DNS=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x10040000
+CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MII=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x10040000
+CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MII=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ATMEL_HLCD=y
CONFIG_LCD=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ATMEL_HLCD=y
CONFIG_LCD=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ATMEL_HLCD=y
CONFIG_LCD=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
+CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_BAV_VERSION=1
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_BAV_VERSION=2
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter passphrase to stop autoboot, booting in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="123"
# CONFIG_CMD_ELF is not set
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=600
CONFIG_TARGET_BRSMARC1=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_TYPES=y
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_AM335X_LCD=y
CONFIG_LCD=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
CONFIG_CI_UDC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0x1110000
CONFIG_SYS_MALLOC_F_LEN=0x3d00
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0xfef10000
CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
CONFIG_NR_DRAM_BANKS=8
CONFIG_INTEL_CAR_CQOS=y
CONFIG_X86_OFFSET_U_BOOT=0xffe00000
CONFIG_X86_OFFSET_SPL=0xffe80000
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral"
CONFIG_BOOTSTAGE=y
CONFIG_SPL_BOOTSTAGE=y
CONFIG_TPL_BOOTSTAGE=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_PCI=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_HUSH_PARSER=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral"
# CONFIG_NET is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_LOG=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0xfffd0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI=y
CONFIG_SPL_PCH_SUPPORT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0xffe70000
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_X86_OFFSET_U_BOOT=0xfff00000
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BLOBLIST_ADDR=0xff7c0000
CONFIG_HANDOFF=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI=y
CONFIG_SPL_PCH_SUPPORT=y
CONFIG_TPL_PCI=y
CONFIG_TPL_PCH_SUPPORT=y
+CONFIG_TPL_DM_SPI=y
+CONFIG_TPL_DM_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_REGMAP=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x40300350
CONFIG_AM43XX=y
CONFIG_TARGET_CM_T43=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-cm-t43"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am437x-cm-t43"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_DM=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_ENV_ADDR=0x80000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_PXA_MMC_GENERIC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
+CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot => "
CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"
+CONFIG_ETH_DESIGNWARE_S700=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_MTD=y
# CONFIG_CMD_SF is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_TIME is not set
# CONFIG_CMD_EXT4 is not set
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
# CONFIG_CMD_SF is not set
# CONFIG_CMD_SPI is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_TIME is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.2"
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_GPT is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_TIME is not set
# CONFIG_CMD_EXT4 is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_BOOTP_NTPSERVER=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x40306D50
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_USB_GADGET=y
CONFIG_BOOTP_DNS2=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_MTD_UBI_BEB_LIMIT=22
CONFIG_MT7628_ETH=y
CONFIG_PHY=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
CONFIG_WDT=y
CONFIG_VIDEO_IPUV3=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=6000
CONFIG_IMX_WATCHDOG=y
+CONFIG_BCH=y
# CONFIG_EFI_LOADER is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_RZA1=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="ignore_loglevel"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_AT91_GPIO=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HWECC=y
CONFIG_PHYLIB=y
+CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200n8"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
CONFIG_SPL_DMA=y
CONFIG_SPL_MMC_TINY=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_SD_BOOT=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_EEPRO100=y
CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_EEPRO100=y
CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_EEPRO100=y
CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_EEPRO100=y
CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_TARGET_K2G_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
# CONFIG_CMD_GPT is not set
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_GPT is not set
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_MT7628_ETH=y
CONFIG_PHY=y
CONFIG_MT76X8_USB_PHY=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=3
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
CONFIG_USB=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPL_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPL_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPL_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPL_DM_SPIy=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPI_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PCNET=y
CONFIG_PCI=y
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_TARGET_MALTA=y
+CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS64_R2=y
CONFIG_MISC_INIT_R=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PCNET=y
CONFIG_PCI=y
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PCNET=y
CONFIG_PCI=y
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_TARGET_MALTA=y
+CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PCNET=y
CONFIG_PCI=y
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="jr2 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_MSCC_JR2_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="luton # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_MSCC_LUTON_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="ocelot # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_MSCC_OCELOT_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="serval # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_MSCC_SERVAL_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="servalt # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_MSCC_SERVALT_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_MT7628_ETH=y
-# CONFIG_SPECIFY_CONSOLE_INDEX is not set
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
CONFIG_LZMA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_VIDEO_IPUV3=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=8000
CONFIG_IMX_WATCHDOG=y
+CONFIG_BCH=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vga; setenv stderr serial,vga; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
+CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_PANDA=y
+CONFIG_DEFAULT_DEVICE_TREE="omap4-panda"
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap4-panda.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+# CONFIG_SPI is not set
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_ETH=y
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_SDP4430=y
+CONFIG_DEFAULT_DEVICE_TREE="omap4-sdp"
CONFIG_CMD_BAT=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap4-sdp.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
# CONFIG_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+# CONFIG_SPI is not set
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_USB_GADGET=y
# CONFIG_REGEX is not set
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_ETH=y
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP54XX=y
CONFIG_TARGET_OMAP5_UEVM=y
+CONFIG_DEFAULT_DEVICE_TREE="omap5-uevm"
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_AHCI=y
CONFIG_SCSI_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+# CONFIG_SPI is not set
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_ETH=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_USB_MUSB_DA8XX=y
CONFIG_USB_MUSB_PIO_ONLY=y
CONFIG_USB_STORAGE=y
-# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_WOL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_PING=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_AT91_GPIO=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_DM_SPI=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_ENV_SIZE=0x40000
CONFIG_MAX_CPUS=2
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0xfffd0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_X86_OFFSET_U_BOOT=0xfff00000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_ROM=y
CONFIG_FIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI=y
CONFIG_SPL_PCH_SUPPORT=y
CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_ENV_SIZE=0x6000
CONFIG_ENV_OFFSET=0x460000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x6000
CONFIG_ENV_OFFSET=0x460000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROCKPRO64_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
+CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=8
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
+CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=8
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
CONFIG_CMD_USB=y
CONFIG_CMD_AXI=y
CONFIG_CMD_AB_SELECT=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_PCAP=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_SYSCON=y
CONFIG_DEVRES=y
CONFIG_DEBUG_DEVRES=y
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
CONFIG_AXI=y
CONFIG_DM_RESET=y
CONFIG_SANDBOX_RESET=y
CONFIG_DM_RNG=y
+CONFIG_RNG_SANDBOX=y
+CONFIG_RESET_SYSCON=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_TARGET_SIPEED_MAIX=y
+CONFIG_ARCH_RV64I=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+# CONFIG_NET is not set
+# CONFIG_INPUT is not set
+# CONFIG_DM_ETH is not set
+# CONFIG_EFI_LOADER is not set
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
+CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PHYLIB=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_SPL_FS_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_FIT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_TARGET_SOCFPGA_IS1=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id=\"idq,regbank\""
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_ENV_OFFSET_REDUND=0xF0000
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_OPTIMIZE_INLINING=y
+CONFIG_SPL_OPTIMIZE_INLINING=y
CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon"
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
CONFIG_ENV_OFFSET_REDUND=0x110000
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=5
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_OFFSET=0x280000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_CMD_STM32PROG=y
+CONFIG_TYPEC_STUSB160X=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_ARMV7_VIRT is not set
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_FASTBOOT_USB_DEV=1
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_DM_I2C=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x4000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_ARMV7_VIRT is not set
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
CONFIG_KS8851_MLL=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x4000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_ARMV7_VIRT is not set
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
-CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
CONFIG_PHY=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_CMD_STM32PROG=y
+CONFIG_TYPEC_STUSB160X=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_FASTBOOT_USB_DEV=1
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_DM_I2C=y
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_STMARK2=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/bin/init devtmpfs.mount=1"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
+CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc rescan; if run bootcmd_up1; then run bootcmd_up2; else run bootcmd_mmc || run distro_bootcmd; fi"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="imx6q-tbs2910.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Matrix U-Boot> "
+# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_SYS_MEMTEST_END=0x2f400000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_I2C_EDID=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_CMD_VIDCONSOLE is not set
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+# CONFIG_VIDEO_ANSI is not set
+# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_GZIP is not set
CONFIG_OF_LIBFDT_ASSUME_MASK=0xff
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0x40300000
-CONFIG_TI814X=y
-CONFIG_TARGET_TI814X_EVM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ET1011C=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_DM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
+CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_DATE is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_ENV_SIZE=0x8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_ENV_SIZE=0x8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_ENV_SIZE=0x8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_OF_BOARD=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_CMD_PCI=y
+CONFIG_LIBATA=y
+CONFIG_SATA_SIL=y
+CONFIG_CMD_SATA=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xBFC0000
# CONFIG_MMC is not set
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFF80000
+CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFF80000
+CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x47F80000
+CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_AT91_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk rw noinitrd mem=64M rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_AT91_GPIO=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_ATMEL_USART=y
CONFIG_LZMA=y
CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_AT91_GPIO=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_ATMEL_USART=y
CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
CONFIG_PCI_MVEBU=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
CONFIG_DM_GPIO=y
+CONFIG_DEFINE_TCM_OCM_MMAP=y
CONFIG_COUNTER_FREQUENCY=62500000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_CMD_DFU=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_CMD_UBI=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_XILINX_GMII2RGMII=y
CONFIG_PHY_FIXED=y
CONFIG_ENV_SIZE=0x190
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x0
The following options are used to enable logging at compile time:
CONFIG_LOG - Enables the logging system
- CONFIG_MAX_LOG_LEVEL - Max log level to build (anything higher is compiled
+ CONFIG_LOG_MAX_LEVEL - Max log level to build (anything higher is compiled
out)
CONFIG_LOG_CONSOLE - Enable writing log records to the console
If CONFIG_LOG is not set, then no logging will be available.
-The above have SPL versions also, e.g. CONFIG_SPL_MAX_LOG_LEVEL.
+The above have SPL and TPL versions also, e.g. CONFIG_SPL_LOG_MAX_LEVEL and
+CONFIG_TPL_LOG_MAX_LEVEL.
Temporary logging within a single file
the appended kernel image will be booted using some generated and some
stored ATAGs (see boot order).
+For generating combined image of u-boot and kernel there is a simple script
+called u-boot-gen-combined. It is available in following repository:
+
+ https://github.com/pali/u-boot-maemo
+
There is support for hardware watchdog. Hardware watchdog is started by
NOLO so u-boot must kick watchdog to prevent reboot device (but not very
often, max every 2 seconds). There is also support for framebuffer display
renesas/index
rockchip/index
sifive/index
+ sipeed/index
st/index
+ tbs/index
toradex/index
xilinx/index
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sipeed
+======
+
+.. toctree::
+ :maxdepth: 2
+
+ maix
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+
+Maix Bit
+========
+
+Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
+a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
+neural network processing and other "ai" tasks. This includes a "KPU" neural
+network processor, an audio processor supporting beamforming reception, and a
+digital video port supporting capture and output at VGA resolution. Other
+peripherals include 8M of SRAM (accessible with and without caching); remappable
+pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
+and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash;
+on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
+ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but
+the boards are fairly similar.
+
+Documentation for Maix boards is available from
+`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
+Documentation for the Kendryte K210 is available from
+`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware
+details are rather lacking, so most technical reference has been taken from the
+`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_.
+
+Build and boot steps
+--------------------
+
+To build u-boot, run
+
+.. code-block:: none
+
+ make sipeed_maix_bitm_defconfig
+ make CROSS_COMPILE=<your cross compile prefix>
+
+To flash u-boot to a maix bit, run
+
+.. code-block:: none
+
+ kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin
+
+Boot output should look like the following:
+
+.. code-block:: none
+
+ U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
+
+ DRAM: 8 MiB
+ In: serial@38000000
+ Out: serial@38000000
+ Err: serial@38000000
+ =>
+
+Loading Images
+^^^^^^^^^^^^^^
+
+To load a kernel, transfer it over serial.
+
+.. code-block:: none
+
+ => loady 80000000 1500000
+ ## Switch baudrate to 1500000 bps and press ENTER ...
+
+ *** baud: 1500000
+
+ *** baud: 1500000 ***
+ ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps...
+ C
+ *** file: loader.bin
+ $ sz -vv loader.bin
+ Sending: loader.bin
+ Bytes Sent:2478208 BPS:72937
+ Sending:
+ Ymodem sectors/kbytes sent: 0/ 0k
+ Transfer complete
+
+ *** exit status: 0 ***
+ ## Total Size = 0x0025d052 = 2478162 Bytes
+ ## Switch baudrate to 115200 bps and press ESC ...
+
+ *** baud: 115200
+
+ *** baud: 115200 ***
+ =>
+
+Running Programs
+^^^^^^^^^^^^^^^^
+
+Binaries
+""""""""
+
+To run a bare binary, use the ``go`` command:
+
+.. code-block:: none
+
+ => loady
+ ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
+ C
+ *** file: ./examples/standalone/hello_world.bin
+ $ sz -vv ./examples/standalone/hello_world.bin
+ Sending: hello_world.bin
+ Bytes Sent: 4864 BPS:649
+ Sending:
+ Ymodem sectors/kbytes sent: 0/ 0k
+ Transfer complete
+
+ *** exit status: 0 ***
+ (CAN) packets, 5 retries
+ ## Total Size = 0x000012f8 = 4856 Bytes
+ => go 80000000
+ ## Starting application at 0x80000000 ...
+ Example expects ABI version 9
+ Actual U-Boot ABI version 9
+ Hello World
+ argc = 1
+ argv[0] = "80000000"
+ argv[1] = "<NULL>"
+ Hit any key to exit ...
+
+Legacy Images
+"""""""""""""
+
+To run legacy images, use the ``bootm`` command:
+
+.. code-block:: none
+
+ $ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 80000000 -e 80000000 -d examples/standalone/hello_world.bin hello_world.img
+ Image Name:
+ Created: Thu Mar 5 12:04:10 2020
+ Image Type: RISC-V U-Boot Standalone Program (uncompressed)
+ Data Size: 4856 Bytes = 4.74 KiB = 0.00 MiB
+ Load Address: 80000000
+ Entry Point: 80000000
+
+ $ picocom -b 115200 /dev/ttyUSB0i
+ => loady
+ ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
+ C
+ *** file: hello_world.img
+ $ sz -vv hello_world.img
+ Sending: hello_world.img
+ Bytes Sent: 4992 BPS:665
+ Sending:
+ Ymodem sectors/kbytes sent: 0/ 0k
+ Transfer complete
+
+ *** exit status: 0 ***
+ CAN) packets, 3 retries
+ ## Total Size = 0x00001338 = 4920 Bytes
+ => bootm
+ ## Booting kernel from Legacy Image at 80000000 ...
+ Image Name:
+ Image Type: RISC-V U-Boot Standalone Program (uncompressed)
+ Data Size: 4856 Bytes = 4.7 KiB
+ Load Address: 80000000
+ Entry Point: 80000000
+ Verifying Checksum ... OK
+ Loading Standalone Program
+ Example expects ABI version 9
+ Actual U-Boot ABI version 9
+ Hello World
+ argc = 0
+ argv[0] = "<NULL>"
+ Hit any key to exit ...
+
+Over- and Under-clocking
+------------------------
+
+To change the clock speed of the K210, you will need to enable
+``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a
+section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following:
+
+.. code-block:: none
+
+ &sysclk {
+ assigned-clocks = <&sysclk K210_CLK_PLL0>;
+ assigned-clock-rates = <800000000>;
+ };
+
+There are three PLLs on the K210: PLL0 is the parent of most of the components,
+including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
+PLL2 is the parent of the sound processing devices. Note that child clocks of
+PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is
+running at 800 MHz, then the CPU will run at 400 MHz. This is the example given
+above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz.
+
+It is possible to set PLL2's parent to PLL0. The plls are more accurate when
+converting between similar frequencies. This makes it easier to get an accurate
+frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz.
+On this device, the I2S serial clock runs at 64 times the sample rate.
+Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If
+PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's
+default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This
+results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If,
+instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of
+2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136
+yields a serial clock of about 2.8228 MHz. This results in a sample rate of
+44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the
+following example:
+
+.. code-block:: none
+
+ &sysclk {
+ assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>;
+ assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>;
+ assigned-clock-rates = <390000000>, <383846400>;
+ };
+
+There are a couple of quirks to the PLLs. First, there are more frequency ratios
+just above and below 1.0, but there is a small gap around 1.0. To be explicit,
+if the input frequency is 100 MHz, it would be impossible to have an output of
+99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO,
+so higher input/output frequencies will be less accurate than lower ones.
+
+Technical Details
+-----------------
+
+Boot Sequence
+^^^^^^^^^^^^^
+
+1. ``RESET`` pin is deasserted.
+2. Both harts begin executing at ``0x00001000``.
+3. Both harts jump to firmware at ``0x88000000``.
+4. One hart is chosen as a boot hart.
+5. Firmware reads value of pin ``IO_16`` (ISP).
+
+ * If the pin is low, enter ISP mode. This mode allows loading data to ram,
+ writing it to flash, and booting from specific addresses.
+ * If the pin is high, continue boot.
+6. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``.
+
+ * If byte 0 is 1, the next stage is decrypted using the built-in AES
+ accelerator and the one-time programmable, 128-bit AES key.
+ * Bytes 1 to 4 hold the length of the next stage.
+ * The SHA-256 sum of the next stage is automatically calculated, and verified
+ against the 32 bytes following the next stage.
+7. The boot hart sends an IPI to the other hart telling it to jump to the next
+ stage.
+8. The boot hart jumps to ``0x80000000``.
+
+Memory Map
+^^^^^^^^^^
+
+========== ========= ===========
+Address Size Description
+========== ========= ===========
+0x00000000 0x1000 debug
+0x00001000 0x1000 rom
+0x02000000 0xC000 clint
+0x0C000000 0x4000000 plic
+0x38000000 0x1000 uarths
+0x38001000 0x1000 gpiohs
+0x40000000 0x400000 sram0 (non-cached)
+0x40400000 0x200000 sram1 (non-cached)
+0x40600000 0x200000 airam (non-cached)
+0x40800000 0xC00000 kpu
+0x42000000 0x400000 fft
+0x50000000 0x1000 dmac
+0x50200000 0x200000 apb0
+0x50200000 0x80 gpio
+0x50210000 0x100 uart0
+0x50220000 0x100 uart1
+0x50230000 0x100 uart2
+0x50240000 0x100 spi slave
+0x50250000 0x200 i2s0
+0x50250200 0x200 apu
+0x50260000 0x200 i2s1
+0x50270000 0x200 i2s2
+0x50280000 0x100 i2c0
+0x50290000 0x100 i2c1
+0x502A0000 0x100 i2c2
+0x502B0000 0x100 fpioa
+0x502C0000 0x100 sha256
+0x502D0000 0x100 timer0
+0x502E0000 0x100 timer1
+0x502F0000 0x100 timer2
+0x50400000 0x200000 apb1
+0x50400000 0x100 wdt0
+0x50410000 0x100 wdt1
+0x50420000 0x100 otp control
+0x50430000 0x100 dvp
+0x50440000 0x100 sysctl
+0x50450000 0x100 aes
+0x50460000 0x100 rtc
+0x52000000 0x4000000 apb2
+0x52000000 0x100 spi0
+0x53000000 0x100 spi1
+0x54000000 0x200 spi3
+0x80000000 0x400000 sram0 (cached)
+0x80400000 0x200000 sram1 (cached)
+0x80600000 0x200000 airam (cached)
+0x88000000 0x20000 otp
+0x88000000 0xC200 firmware
+0x8801C000 0x1000 riscv priv spec 1.9 config
+0x8801D000 0x2000 flattened device tree (contains only addresses and
+ interrupts)
+0x8801f000 0x1000 credits
+========== ========= ===========
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+TBS
+===
+
+.. toctree::
+ :maxdepth: 2
+
+ tbs2910
--- /dev/null
+TBS2910 Matrix ARM miniPC
+=========================
+
+Building
+--------
+To build u-boot for the TBS2910 Matrix ARM miniPC, you can use the following
+procedure:
+
+First add the ARM toolchain to your PATH
+
+Then setup the ARCH and cross compilation environment variables.
+
+When this is done you can then build u-boot for the TBS2910 Matrix ARM miniPC
+with the following commands:
+
+.. code-block:: none
+
+ make mrproper
+ make tbs2910_defconfig
+ make
+
+Once the build is complete, you can find the resulting image as u-boot.imx in
+the current directory.
+
+UART
+----
+The UART voltage is at 3.3V and its settings are 115200bps 8N1
+
+BOOT/UPDATE boot switch:
+------------------------
+The BOOT/UPDATE switch (SW11) is connected to the BOOT_MODE0 and
+BOOT_MODE1 SoC pins. It has "BOOT" and "UPDATE" markings both on
+the PCB and on the plastic case.
+
+When set to the "UPDATE" position, the SoC will use the "Boot From Fuses"
+configuration, and since BT_FUSE_SEL is 0, this makes the SOC jump to serial
+downloader.
+
+When set in the "BOOT" position, the SoC will use the "Internal boot"
+configuration, and since BT_FUSE_SEL is 0, it will then use the GPIO pins
+for the boot configuration.
+
+SW6 binary DIP switch array on the PCB revision 2.1:
+----------------------------------------------------
+On that PCB revision, SW6 has 8 positions.
+
+Switching a position to ON sets the corresponding
+register to 1.
+
+See the following table for a correspondence between the switch positions and
+registers:
+
+=============== ============
+Switch position Register
+=============== ============
+1 BOOT_CFG2[3]
+2 BOOT_CFG2[4]
+3 BOOT_CFG2[5]
+4 BOOT_CFG2[6]
+5 BOOT_CFG1[4]
+6 BOOT_CFG1[5]
+7 BOOT_CFG1[6]
+8 BOOT_CFG1[7]
+=============== ============
+
+For example:
+
+ - To boot from the eMMC: 1:ON , 2:ON, 3:ON, 4:OFF, 5:OFF, 6:ON, 7:ON, 8:OFF
+ - To boot from the microSD slot: 1: ON, 2: OFF, 3: OFF, 4: OFF, 5:OFF, 6:OFF,
+ 7:ON, 8:OFF
+ - To boot from the SD slot: 1: OFF, 2: ON, 3: OFF, 4: OFF, 5:OFF, 6:OFF, 7:ON,
+ 8:OFF
+ - To boot from SATA: 1: OFF, 2: OFF, 3: OFF, 4: OFF, 5:OFF, 6:ON, 7:OFF, 8:OFF
+
+You can refer to the BOOT_CFG registers in the I.MX6Q reference manual for
+additional details.
+
+SW6 binary DIP switch array on the PCB revision 2.3:
+----------------------------------------------------
+On that PCB revision, SW6 has only 4 positions.
+
+Switching a position to ON sets the corresponding
+register to 1.
+
+See the following table for a correspondence between the switch positions and
+registers:
+
+=============== ============
+Switch position Register
+=============== ============
+1 BOOT_CFG2[3]
+2 BOOT_CFG2[4]
+3 BOOT_CFG2[5]
+4 BOOT_CFG1[5]
+=============== ============
+
+For example:
+
+- To boot from the eMMC: 1:ON, 2:ON, 3:ON, 4:ON
+- To boot from the microSD slot: 1:ON, 2:OFF, 3:OFF, 4:OFF
+- To boot from the SD slot: 1:OFF, 2:ON, 3:OFF, 4:OFF
+
+You can refer to the BOOT_CFG registers in the I.MX6Q reference manual for
+additional details.
+
+Loading u-boot from USB:
+------------------------
+If you need to load u-boot from USB, you can use the following instructions:
+
+First build imx_usb_loader, as we will need it to load u-boot from USB. This
+can be done with the following commands:
+
+.. code-block:: none
+
+ git clone git://github.com/boundarydevices/imx_usb_loader.git
+ cd imx_usb_loader
+ make
+
+This will create the resulting imx_usb binary.
+
+When this is done, you can copy the u-boot.imx image that you built earlier
+in in the imx_usb_loader directory.
+
+You will then need to power off the TBS2910 Matrix ARM miniPC and make sure that
+the boot switch is set to "UPDATE"
+
+Once this is done you can connect an USB cable between the computer that will
+run imx_usb and the TBS2910 Matrix ARM miniPC.
+
+If you also need to access the u-boot console, you will also need to connect an
+UART cable between the computer running imx_usb and the TBS2910 Matrix ARM
+miniPC.
+
+Once everything is connected you can finally power on the TBS2910 Matrix ARM
+miniPC. The SoC will then jump to the serial download and wait for you.
+
+Finlay, you can load u-boot through USB with with the following command:
+
+.. code-block:: none
+
+ sudo ./imx_usb -v u-boot.imx
+
+The u-boot boot messages will then appear in the serial console.
+
+Install u-boot on the eMMC:
+---------------------------
+To install u-boot on the eMMC, you first need to boot the TBS2910 Matrix ARM
+miniPC.
+
+Once booted, you can flash u-boot.imx to mmcblk0boot0 with the
+following commands:
+
+.. code-block:: none
+
+ sudo echo 0 >/sys/block/mmcblk0boot0/force_ro
+ sudo dd if=u-boot.imx of=/dev/mmcblk0boot0 bs=1k seek=1; sync
+
+Note that the eMMC card node may vary, so adjust this as needed.
+
+Once the new u-boot version is installed, to boot on it you then need to power
+off the TBS2910 Matrix ARM miniPC.
+
+Once it is off, you need make sure that the boot switch is set to "BOOT" and
+that the SW6 switch is set to boot on the eMMC as described in the previous
+sections.
+
+If you also need to access the u-boot console, you will also need to connect an
+UART cable between the computer running imx_usb and the TBS2910 Matrix ARM
+miniPC.
+
+You can then power up the TBS2910 Matrix ARM miniPC and U-Boot messages will
+appear in the serial console.
+
+Booting a distribution:
+-----------------------
+When booting on the TBS2910 Matrix ARM miniPC, by default U-Boot will first try
+to boot from hardcoded offsets from the start of the eMMC. This is for
+compatibility with the stock GNU/Linux distribution.
+
+If that fails it will then try to boot from several interfaces using
+'distro_bootcmd': It will first try to boot from the microSD slot, then the
+SD slot, then the internal eMMC, then the SATA interface and finally the USB
+interface. For more information on how to configure your distribution to boot,
+see 'README.distro'.
+
+Links:
+------
+ - https://www.tbsdtv.com/download/document/tbs2910/TBS2910-Matrix-ARM-mini-PC-SCH_rev2.1.pdf
+ - The schematics for the revision 2.1 of the TBS2910 Matrix ARM miniPC.
+ - https://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf - The
+ SoC reference manual for additional details on the BOOT_CFG registers.
"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
bootmode strings at runtime.
+Flashing
+--------
+
+SD Card
+^^^^^^^
+
+To write an image that boots from a SD card first create a FAT32 partition
+and a FAT32 filesystem on the SD card::
+
+ sudo fdisk /dev/sdx
+ sudo mkfs.vfat -F 32 /dev/sdx1
+
+Mount the SD card and copy the SPL and U-Boot to the root directory of the
+SD card::
+
+ sudo mount -t vfat /dev/sdx1 /mnt
+ sudo cp spl/boot.bin /mnt
+ sudo cp u-boot.img /mnt
+
Mainline status
---------------
:maxdepth: 2
crash_dumps
+ logging
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2017 Simon Glass <sjg@chromium.org>
+
+Logging in U-Boot
+=================
+
+Introduction
+------------
+
+U-Boot's internal operation involves many different steps and actions. From
+setting up the board to displaying a start-up screen to loading an Operating
+System, there are many component parts each with many actions.
+
+Most of the time this internal detail is not useful. Displaying it on the
+console would delay booting (U-Boot's primary purpose) and confuse users.
+
+But for digging into what is happening in a particular area, or for debugging
+a problem it is often useful to see what U-Boot is doing in more detail than
+is visible from the basic console output.
+
+U-Boot's logging feature aims to satisfy this goal for both users and
+developers.
+
+
+Logging levels
+--------------
+
+There are a number logging levels available, in increasing order of verbosity:
+
+* LOGL_EMERG - Printed before U-Boot halts
+* LOGL_ALERT - Indicates action must be taken immediate or U-Boot will crash
+* LOGL_CRIT - Indicates a critical error that will cause boot failure
+* LOGL_ERR - Indicates an error that may cause boot failure
+* LOGL_WARNING - Warning about an unexpected condition
+* LOGL_NOTE - Important information about progress
+* LOGL_INFO - Information about normal boot progress
+* LOGL_DEBUG - Debug information (useful for debugging a driver or subsystem)
+* LOGL_DEBUG_CONTENT - Debug message showing full message content
+* LOGL_DEBUG_IO - Debug message showing hardware I/O access
+
+
+Logging category
+----------------
+
+Logging can come from a wide variety of places within U-Boot. Each log message
+has a category which is intended to allow messages to be filtered according to
+their source.
+
+The following main categories are defined:
+
+* LOGC_NONE - Unknown category (e.g. a debug() statement)
+* UCLASS\_... - Related to a particular uclass (e.g. UCLASS_USB)
+* LOGC_ARCH - Related to architecture-specific code
+* LOGC_BOARD - Related to board-specific code
+* LOGC_CORE - Related to core driver-model support
+* LOGC_DT - Related to device tree control
+* LOGC_EFI - Related to EFI implementation
+
+
+Enabling logging
+----------------
+
+The following options are used to enable logging at compile time:
+
+* CONFIG_LOG - Enables the logging system
+* CONFIG_LOG_MAX_LEVEL - Max log level to build (anything higher is compiled
+ out)
+* CONFIG_LOG_CONSOLE - Enable writing log records to the console
+
+If CONFIG_LOG is not set, then no logging will be available.
+
+The above have SPL and TPL versions also, e.g. CONFIG_SPL_LOG_MAX_LEVEL and
+CONFIG_TPL_LOG_MAX_LEVEL.
+
+
+Temporary logging within a single file
+--------------------------------------
+
+Sometimes it is useful to turn on logging just in one file. You can use this
+
+.. code-block:: c
+
+ #define LOG_DEBUG
+
+to enable building in of all logging statements in a single file. Put it at
+the top of the file, before any #includes.
+
+To actually get U-Boot to output this you need to also set the default logging
+level - e.g. set CONFIG_LOG_DEFAULT_LEVEL to 7 (LOGL_DEBUG) or more. Otherwise
+debug output is suppressed and will not be generated.
+
+
+Convenience functions
+---------------------
+
+A number of convenience functions are available to shorten the code needed
+for logging:
+
+* log_err(_fmt...)
+* log_warning(_fmt...)
+* log_notice(_fmt...)
+* log_info(_fmt...)
+* log_debug(_fmt...)
+* log_content(_fmt...)
+* log_io(_fmt...)
+
+With these the log level is implicit in the name. The category is set by
+LOG_CATEGORY, which you can only define once per file, above all #includes, e.g.
+
+.. code-block:: c
+
+ #define LOG_CATEGORY LOGC_ALLOC
+
+Remember that all uclasses IDs are log categories too.
+
+
+Log command
+-----------
+
+The 'log' command provides access to several features:
+
+* level - access the default log level
+* format - access the console log format
+* rec - output a log record
+* test - run tests
+
+Type 'help log' for details.
+
+
+Using DEBUG
+-----------
+
+U-Boot has traditionally used a #define called DEBUG to enable debugging on a
+file-by-file basis. The debug() macro compiles to a printf() statement if
+DEBUG is enabled, and an empty statement if not.
+
+With logging enabled, debug() statements are interpreted as logging output
+with a level of LOGL_DEBUG and a category of LOGC_NONE.
+
+The logging facilities are intended to replace DEBUG, but if DEBUG is defined
+at the top of a file, then it takes precedence. This means that debug()
+statements will result in output to the console and this output will not be
+logged.
+
+
+Logging destinations
+--------------------
+
+If logging information goes nowhere then it serves no purpose. U-Boot provides
+several possible determinations for logging information, all of which can be
+enabled or disabled independently:
+
+* console - goes to stdout
+* syslog - broadcast RFC 3164 messages to syslog servers on UDP port 514
+
+The syslog driver sends the value of environmental variable 'log_hostname' as
+HOSTNAME if available.
+
+
+Log format
+----------
+
+You can control the log format using the 'log format' command. The basic
+format is::
+
+ LEVEL.category,file.c:123-func() message
+
+In the above, file.c:123 is the filename where the log record was generated and
+func() is the function name. By default ('log format default') only the
+function name and message are displayed on the console. You can control which
+fields are present, but not the field order.
+
+
+Filters
+-------
+
+Filters are attached to log drivers to control what those drivers emit. Only
+records that pass through the filter make it to the driver.
+
+Filters can be based on several criteria:
+
+* maximum log level
+* in a set of categories
+* in a set of files
+
+If no filters are attached to a driver then a default filter is used, which
+limits output to records with a level less than CONFIG_MAX_LOG_LEVEL.
+
+
+Logging statements
+------------------
+
+The main logging function is:
+
+.. code-block:: c
+
+ log(category, level, format_string, ...)
+
+Also debug() and error() will generate log records - these use LOG_CATEGORY
+as the category, so you should #define this right at the top of the source
+file to ensure the category is correct.
+
+You can also define CONFIG_LOG_ERROR_RETURN to enable the log_ret() macro. This
+can be used whenever your function returns an error value:
+
+.. code-block:: c
+
+ return log_ret(uclass_first_device(UCLASS_MMC, &dev));
+
+This will write a log record when an error code is detected (a value < 0). This
+can make it easier to trace errors that are generated deep in the call stack.
+
+
+Code size
+---------
+
+Code size impact depends largely on what is enabled. The following numbers are
+generated by 'buildman -S' for snow, which is a Thumb-2 board (all units in
+bytes)::
+
+ This series: adds bss +20.0 data +4.0 rodata +4.0 text +44.0
+ CONFIG_LOG: bss -52.0 data +92.0 rodata -635.0 text +1048.0
+ CONFIG_LOG_MAX_LEVEL=7: bss +188.0 data +4.0 rodata +49183.0 text +98124.0
+
+The last option turns every debug() statement into a logging call, which
+bloats the code hugely. The advantage is that it is then possible to enable
+all logging within U-Boot.
+
+
+To Do
+-----
+
+There are lots of useful additions that could be made. None of the below is
+implemented! If you do one, please add a test in test/py/tests/test_log.py
+
+Convenience functions to support setting the category:
+
+* log_arch(level, format_string, ...) - category LOGC_ARCH
+* log_board(level, format_string, ...) - category LOGC_BOARD
+* log_core(level, format_string, ...) - category LOGC_CORE
+* log_dt(level, format_string, ...) - category LOGC_DT
+
+More logging destinations:
+
+* device - goes to a device (e.g. serial)
+* buffer - recorded in a memory buffer
+
+Convert debug() statements in the code to log() statements
+
+Support making printf() emit log statements at L_INFO level
+
+Convert error() statements in the code to log() statements
+
+Figure out what to do with BUG(), BUG_ON() and warn_non_spl()
+
+Figure out what to do with assert()
+
+Add a way to browse log records
+
+Add a way to record log records for browsing using an external tool
+
+Add commands to add and remove filters
+
+Add commands to add and remove log devices
+
+Allow sharing of printf format strings in log records to reduce storage size
+for large numbers of log records
+
+Add a command-line option to sandbox to set the default logging level
+
+Convert core driver model code to use logging
+
+Convert uclasses to use logging with the correct category
+
+Consider making log() calls emit an automatic newline, perhaps with a logn()
+function to avoid that
+
+Passing log records through to linux (e.g. via device tree /chosen)
+
+Provide a command to access the number of log records generated, and the
+number dropped due to them being generated before the log system was ready.
+
+Add a printf() format string pragma so that log statements are checked properly
+
+Enhance the log console driver to show level / category / file / line
+information
+
+Add a command to add new log records and delete existing records.
+
+Provide additional log() functions - e.g. logc() to specify the category
--- /dev/null
+Simple Power-Managed Bus
+========================
+
+A Simple Power-Managed Bus is a transparent bus that doesn't need a real
+driver, as it's typically initialized by the boot loader.
+
+However, its bus controller is part of a PM domain, or under the control of a
+functional clock. Hence, the bus controller's PM domain and/or clock must be
+enabled for child devices connected to the bus (either on-SoC or externally)
+to function.
+
+While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
+in the Devicetree Specification, it is not an extension of "simple-bus".
+
+
+Required properties:
+ - compatible: Must contain at least "simple-pm-bus".
+ Must not contain "simple-bus".
+ It's recommended to let this be preceded by one or more
+ vendor-specific compatible values.
+ - #address-cells, #size-cells, ranges: Must describe the mapping between
+ parent address and child address spaces.
+
+Optional platform-specific properties for clock or PM domain control (at least
+one of them is required):
+ - clocks: Must contain a reference to the functional clock(s),
+ - power-domains: Must contain a reference to the PM domain.
+Please refer to the binding documentation for the clock and/or PM domain
+providers for more details.
+
+
+Example:
+
+ bsc: bus@fec10000 {
+ compatible = "renesas,bsc-sh73a0", "renesas,bsc",
+ "simple-pm-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x20000000>;
+ reg = <0xfec10000 0x400>;
+ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&zb_clk>;
+ power-domains = <&pd_a4s>;
+ };
are listed with associated reg 0 to 3.
PLLx is off when the associated node is absent or deactivated.
+ For PLL1, when the node is absent, the frequency of the OPP node is used
+ to compute the PLL setting (see compatible "operating-points-v2" in
+ opp/opp.txt for details).
+
Here are the available properties for each PLL node:
- compatible: should be "st,stm32mp1-pll"
--- /dev/null
+Kendryte K210 Sysctl
+
+This binding describes the K210 sysctl device, which contains many miscellaneous
+registers controlling system functionality. This node is a register map and can
+be reference by other bindings which need a phandle to the K210 sysctl regmap.
+
+Required properties:
+- compatible: should be
+ "kendryte,k210-sysctl", "syscon", "simple-mfd"
+- reg: address and length of the sysctl registers
+- reg-io-width: must be <4>
+
+Clock sub-node
+
+This node is a binding for the clock tree driver
+
+Required properties:
+- compatible: should be "kendryte,k210-clk"
+- clocks: phandle to the "in0" external oscillator
+- #clock-cells: must be <1>
+
+Example:
+sysctl: syscon@50440000 {
+ compatible = "kendryte,k210-sysctl", "syscon", "simple-mfd";
+ reg = <0x50440000 0x100>;
+ reg-io-width = <4>;
+
+ sysclk: clock-controller {
+ compatible = "kendryte,k210-clk";
+ clocks = <&in0>;
+ #clock-cells = <1>;
+ };
+};
--- /dev/null
+Generic SYSCON mapped register reset driver
+
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset and
+shifted by the reset specifier/
+
+To assert a reset on some device, the equivalent of the following operation is
+performed, where reset_id is the reset specifier from the device's resets
+property.
+
+ if (BIT(reset_id) & mask)
+ regmap[offset][reset_id] = assert-high;
+
+Required properties:
+- compatible: should contain "syscon-reset"
+- #reset-cells: must be 1
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+
+Optional properties:
+- mask: accept only the reset specifiers defined by the mask (32 bit)
+- assert-high: Bit to write when asserting a reset. Defaults to 1.
+
+Default will be little endian mode, 32 bit access only.
+
+Example:
+
+ reset-controller {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&sysctl>;
+ offset = <0x20>;
+ mask = <0x27FFFFFF>;
+ assert-high = <0>;
+ };
xhci_usb (UCLASS_USB)
flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by USB bus
- sata (UCLASS_SATA)
+ sata (UCLASS_AHCI)
flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by SATA bus
flash (UCLASS_FLASH_STORAGE) - no parent data/methods (not on a bus)
bus device, regardless of its own views on the matter.
The uclass for the device can also contain data private to that uclass.
-But note that each device on the bus may be a memeber of a different
+But note that each device on the bus may be a member of a different
uclass, and this data has nothing to do with the child data for each child
on the bus. It is the bus' uclass that controls the child with respect to
the bus.
Introduction:
=============
-This documentation entry describes the Common Clock Framework [CCF]
-port from Linux kernel (v5.1.12) to U-Boot.
+This documentation entry describes the Common Clock Framework [CCF] port from
+Linux kernel (v5.1.12) to U-Boot.
-This code is supposed to bring CCF to IMX based devices (imx6q, imx7
-imx8). Moreover, it also provides some common clock code, which would
-allow easy porting of CCF Linux code to other platforms.
+This code is supposed to bring CCF to IMX based devices (imx6q, imx7 imx8).
+Moreover, it also provides some common clock code, which would allow easy
+porting of CCF Linux code to other platforms.
Design decisions:
=================
-* U-Boot's driver model [DM] for clk differs from Linux CCF. The most
- notably difference is the lack of support for hierarchical clocks and
- "clock as a manager driver" (single clock DTS node acts as a starting
- point for all other clocks).
+* U-Boot's driver model [DM] for clk differs from Linux CCF. The most notably
+ difference is the lack of support for hierarchical clocks and "clock as a
+ manager driver" (single clock DTS node acts as a starting point for all other
+ clocks).
-* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE
- is not set (no need for recursive access).
+* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE is
+ not set (no need for recursive access).
-* On purpose the "manager" clk driver (clk-imx6q.c) is not using large
- table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = ....
- Instead we use udevice's linked list for the same class (UCLASS_CLK).
+* On purpose the "manager" clk driver (clk-imx6q.c) is not using large table to
+ store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = .... Instead we
+ use udevice's linked list for the same class (UCLASS_CLK).
Rationale:
----------
- When porting the code as is from Linux, one would need ~1KiB of RAM to
- store it. This is way too much if we do plan to use this driver in SPL.
+ When porting the code as is from Linux, one would need ~1KiB of RAM to store
+ it. This is way too much if we do plan to use this driver in SPL.
* The "central" structure of this patch series is struct udevice and its
uclass_priv field contains the struct clk pointer (to the originally created
one).
-* Up till now U-Boot's driver model (DM) CLK operates on udevice (main
- access to clock is by udevice ops)
- In the CCF the access to struct clk (embodying pointer to *dev) is
- possible via dev_get_clk_ptr() (it is a wrapper on dev_get_uclass_priv()).
-
* To keep things simple the struct udevice's uclass_priv pointer is used to
store back pointer to corresponding struct clk. However, it is possible to
modify clk-uclass.c file and add there struct uc_clk_priv, which would have
setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the
uclass_priv stores the pointer to struct clk.
+* Non-CCF clocks do not have a pointer to a clock in clk->dev->priv. In the case
+ of composite clocks, clk->dev->priv may not match clk. Drivers should always
+ use the struct clk which is passed to them, and not clk->dev->priv.
+
* It is advised to add common clock code (like already added rate and flags) to
the struct clk, which is a top level description of the clock.
* U-Boot's driver model already provides the facility to automatically allocate
- (via private_alloc_size) device private data (accessible via dev->priv).
- It may look appealing to use this feature to allocate private structures for
- CCF clk devices e.g. divider (struct clk_divider *divider) for IMX6Q clock.
+ (via private_alloc_size) device private data (accessible via dev->priv). It
+ may look appealing to use this feature to allocate private structures for CCF
+ clk devices e.g. divider (struct clk_divider *divider) for IMX6Q clock.
The above feature had not been used for following reasons:
- The original CCF Linux kernel driver is the "manager" for clocks - it
* I've added the clk_get_parent(), which reads parent's dev->uclass_priv to
provide parent's struct clk pointer. This seems the easiest way to get
- child/parent relationship for struct clk in U-Boot's udevice based clocks.
+ child/parent relationship for struct clk in U-Boot's udevice based clocks. In
+ the future arbitrary parents may be supported by adding a get_parent function
+ to clk_ops.
* Linux's CCF 'struct clk_core' corresponds to U-Boot's udevice in 'struct clk'.
Clock IP block agnostic flags from 'struct clk_core' (e.g. NOCACHE) have been
- moved from this struct one level up to 'struct clk'.
+ moved from this struct one level up to 'struct clk'. Many flags are
+ unimplemented at the moment.
* For tests the new ./test/dm/clk_ccf.c and ./drivers/clk/clk_sandbox_ccf.c
files have been introduced. The latter setups the CCF clock structure for
- sandbox by reusing, if possible, generic clock primitives - like divier
- and mux. The former file provides code to tests this setup.
+ sandbox by reusing, if possible, generic clock primitives - like divier and
+ mux. The former file provides code to tests this setup.
For sandbox new CONFIG_SANDBOX_CLK_CCF Kconfig define has been introduced.
- All new primitives added for new architectures must have corresponding test
- in the two aforementioned files.
-
+ All new primitives added for new architectures must have corresponding test in
+ the two aforementioned files.
Testing (sandbox):
==================
#include "sata_sil.h"
+#ifdef CONFIG_DM_PCI
+#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
+#else
#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
+#endif
/* just compatible ahci_ops */
struct sil_ops {
/* Save the private struct to block device struct */
#if !CONFIG_IS_ENABLED(BLK)
sata_dev_desc[dev].priv = (void *)sata;
+ sata->devno = sata_info.devno;
#else
priv->sil_sata_desc[dev] = sata;
priv->port_num = dev;
+#ifdef CONFIG_DM_PCI
+ sata->devno = uc_dev->parent;
+#else
+ sata->devno = sata_info.devno;
+#endif /* CONFIG_DM_PCI */
#endif
sata->id = dev;
sata->port = port;
- sata->devno = sata_info.devno;
sprintf(sata->name, "SATA#%d", dev);
sil_cmd_soft_reset(sata);
tmp = readl(port + PORT_SSTATUS);
u16 pio;
u16 mwdma;
u16 udma;
- pci_dev_t devno;
+#ifdef CONFIG_DM_PCI
+ struct udevice *devno;
+#else
+ pci_dev_t devno;
+#endif
int wcache;
int flush;
int flush_ext;
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
+source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_K210) += kendryte/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
struct clk *mux = composite->mux;
- return clk_mux_get_parent(mux);
+ if (mux)
+ return clk_mux_get_parent(mux);
+ else
+ return 0;
}
static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk *mux = composite->mux;
- return mux_ops->set_parent(mux, parent);
+ if (mux && mux_ops)
+ return mux_ops->set_parent(mux, parent);
+ else
+ return -ENOTSUPP;
}
static unsigned long clk_composite_recalc_rate(struct clk *clk)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *rate = composite->rate;
- return rate_ops->get_rate(rate);
+ if (rate && rate_ops)
+ return rate_ops->get_rate(rate);
+ else
+ return clk_get_parent_rate(clk);
}
static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *clk_rate = composite->rate;
- return rate_ops->set_rate(clk_rate, rate);
+ if (rate && rate_ops)
+ return rate_ops->set_rate(clk_rate, rate);
+ else
+ return clk_get_rate(clk);
}
static int clk_composite_enable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
- return gate_ops->enable(gate);
+ if (gate && gate_ops)
+ return gate_ops->enable(gate);
+ else
+ return 0;
}
static int clk_composite_disable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
- gate_ops->disable(gate);
-
- return 0;
+ if (gate && gate_ops)
+ return gate_ops->disable(gate);
+ else
+ return 0;
}
-struct clk_ops clk_composite_ops = {
- /* This will be set according to clk_register_composite */
-};
-
struct clk *clk_register_composite(struct device *dev, const char *name,
const char * const *parent_names,
int num_parents, struct clk *mux,
struct clk *clk;
struct clk_composite *composite;
int ret;
- struct clk_ops *composite_ops = &clk_composite_ops;
+
+ if (!num_parents || (num_parents != 1 && !mux))
+ return ERR_PTR(-EINVAL);
composite = kzalloc(sizeof(*composite), GFP_KERNEL);
if (!composite)
if (mux && mux_ops) {
composite->mux = mux;
composite->mux_ops = mux_ops;
- if (mux_ops->set_parent)
- composite_ops->set_parent = clk_composite_set_parent;
mux->data = (ulong)composite;
}
clk = ERR_PTR(-EINVAL);
goto err;
}
- composite_ops->get_rate = clk_composite_recalc_rate;
-
- /* .set_rate requires either .round_rate or .determine_rate */
- if (rate_ops->set_rate)
- composite_ops->set_rate = clk_composite_set_rate;
composite->rate = rate;
composite->rate_ops = rate_ops;
composite->gate = gate;
composite->gate_ops = gate_ops;
- composite_ops->enable = clk_composite_enable;
- composite_ops->disable = clk_composite_disable;
gate->data = (ulong)composite;
}
goto err;
}
+ if (composite->mux)
+ composite->mux->dev = clk->dev;
+ if (composite->rate)
+ composite->rate->dev = clk->dev;
+ if (composite->gate)
+ composite->gate->dev = clk->dev;
+
return clk;
err:
return clk;
}
+static const struct clk_ops clk_composite_ops = {
+ .set_parent = clk_composite_set_parent,
+ .get_rate = clk_composite_recalc_rate,
+ .set_rate = clk_composite_set_rate,
+ .enable = clk_composite_enable,
+ .disable = clk_composite_disable,
+};
+
U_BOOT_DRIVER(clk_composite) = {
.name = UBOOT_DM_CLK_COMPOSITE,
.id = UCLASS_CLK,
static ulong clk_divider_recalc_rate(struct clk *clk)
{
- struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_divider *divider = to_clk_divider(clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned int val;
static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
{
- struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_divider *divider = to_clk_divider(clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
int value;
u32 val;
static ulong clk_factor_recalc_rate(struct clk *clk)
{
- struct clk_fixed_factor *fix =
- to_clk_fixed_factor(dev_get_clk_ptr(clk->dev));
+ struct clk_fixed_factor *fix = to_clk_fixed_factor(clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned long long int rate;
*/
static void clk_gate_endisable(struct clk *clk, int enable)
{
- struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_gate *gate = to_clk_gate(clk);
int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
u32 reg;
int clk_gate_is_enabled(struct clk *clk)
{
- struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_gate *gate = to_clk_gate(clk);
u32 reg;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
unsigned int val)
{
- struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_mux *mux = to_clk_mux(clk);
int num_parents = mux->num_parents;
if (table) {
u8 clk_mux_get_parent(struct clk *clk)
{
- struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_mux *mux = to_clk_mux(clk);
u32 val;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
static int clk_fetch_parent_index(struct clk *clk,
struct clk *parent)
{
- struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_mux *mux = to_clk_mux(clk);
int i;
static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
{
- struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
- dev_get_clk_ptr(clk->dev) : clk);
+ struct clk_mux *mux = to_clk_mux(clk);
int index;
u32 val;
u32 reg;
return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
- index > 0, clk);
+ index, clk);
}
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
index, &args);
return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
- index > 0, clk);
+ index, clk);
}
int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
int ret;
ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
- index > 0, &args);
+ index, &args);
return clk_get_by_index_tail(ret, node, &args, "clocks",
- index > 0, clk);
+ index, clk);
}
int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/iopoll.h>
+#include <asm/arch/sys_proto.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
};
#ifdef STM32MP1_CLOCK_TREE_INIT
+
/* define characteristic of PLL according type */
+#define DIVM_MIN 0
+#define DIVM_MAX 63
#define DIVN_MIN 24
+#define DIVP_MIN 0
+#define DIVP_MAX 127
+#define FRAC_MAX 8192
+
+#define PLL1600_VCO_MIN 800000000
+#define PLL1600_VCO_MAX 1600000000
+
static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
[PLL_800] = {
.refclk_min = 4,
}
#ifdef STM32MP1_CLOCK_TREE_INIT
+
+bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
+{
+ unsigned int id;
+
+ switch (opp_id) {
+ case 1:
+ case 2:
+ id = opp_id;
+ break;
+ default:
+ id = 1; /* default value */
+ break;
+ }
+
+ switch (cpu_type) {
+ case CPU_STM32MP157Fxx:
+ case CPU_STM32MP157Dxx:
+ case CPU_STM32MP153Fxx:
+ case CPU_STM32MP153Dxx:
+ case CPU_STM32MP151Fxx:
+ case CPU_STM32MP151Dxx:
+ return true;
+ default:
+ return id == 1;
+ }
+}
+
+__weak void board_vddcore_init(u32 voltage_mv)
+{
+}
+
+/*
+ * gets OPP parameters (frequency in KHz and voltage in mV) from
+ * an OPP table subnode. Platform HW support capabilities are also checked.
+ * Returns 0 on success and a negative FDT error code on failure.
+ */
+static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
+ u32 *freq_khz, u32 *voltage_mv)
+{
+ u32 opp_hw;
+ u64 read_freq_64;
+ u32 read_voltage_32;
+
+ *freq_khz = 0;
+ *voltage_mv = 0;
+
+ opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
+ if (opp_hw)
+ if (!stm32mp1_supports_opp(opp_hw, cpu_type))
+ return -FDT_ERR_BADVALUE;
+
+ read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
+ 1000ULL;
+ read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
+ 1000U;
+
+ if (!read_voltage_32 || !read_freq_64)
+ return -FDT_ERR_NOTFOUND;
+
+ /* Frequency value expressed in KHz must fit on 32 bits */
+ if (read_freq_64 > U32_MAX)
+ return -FDT_ERR_BADVALUE;
+
+ /* Millivolt value must fit on 16 bits */
+ if (read_voltage_32 > U16_MAX)
+ return -FDT_ERR_BADVALUE;
+
+ *freq_khz = (u32)read_freq_64;
+ *voltage_mv = read_voltage_32;
+
+ return 0;
+}
+
+/*
+ * parses OPP table in DT and finds the parameters for the
+ * highest frequency supported by the HW platform.
+ * Returns 0 on success and a negative FDT error code on failure.
+ */
+int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
+{
+ ofnode node, subnode;
+ int ret;
+ u32 freq = 0U, voltage = 0U;
+ u32 cpu_type = get_cpu_type();
+
+ node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
+ if (!ofnode_valid(node))
+ return -FDT_ERR_NOTFOUND;
+
+ ofnode_for_each_subnode(subnode, node) {
+ unsigned int read_freq;
+ unsigned int read_voltage;
+
+ ret = stm32mp1_get_opp(cpu_type, subnode,
+ &read_freq, &read_voltage);
+ if (ret)
+ continue;
+
+ if (read_freq > freq) {
+ freq = read_freq;
+ voltage = read_voltage;
+ }
+ }
+
+ if (!freq || !voltage)
+ return -FDT_ERR_NOTFOUND;
+
+ *freq_hz = (u64)1000U * freq;
+ board_vddcore_init(voltage);
+
+ return 0;
+}
+
+static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
+ u32 *pllcfg, u32 *fracv)
+{
+ u32 post_divm;
+ u32 input_freq;
+ u64 output_freq;
+ u64 freq;
+ u64 vco;
+ u32 divm, divn, divp, frac;
+ int i, ret;
+ u32 diff;
+ u32 best_diff = U32_MAX;
+
+ /* PLL1 is 1600 */
+ const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
+ const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
+ const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
+
+ ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
+ if (ret) {
+ debug("PLL1 OPP configuration not found (%d).\n", ret);
+ return ret;
+ }
+
+ switch (clksrc) {
+ case CLK_PLL12_HSI:
+ input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case CLK_PLL12_HSE:
+ input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ default:
+ return -EINTR;
+ }
+
+ /* Following parameters have always the same value */
+ pllcfg[PLLCFG_Q] = 0;
+ pllcfg[PLLCFG_R] = 0;
+ pllcfg[PLLCFG_O] = PQR(1, 0, 0);
+
+ for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
+ post_divm = (u32)(input_freq / (divm + 1));
+ if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
+ continue;
+
+ for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
+ freq = output_freq * (divm + 1) * (divp + 1);
+ divn = (u32)((freq / input_freq) - 1);
+ if (divn < DIVN_MIN || divn > DIVN_MAX)
+ continue;
+
+ frac = (u32)(((freq * FRAC_MAX) / input_freq) -
+ ((divn + 1) * FRAC_MAX));
+ /* 2 loops to refine the fractional part */
+ for (i = 2; i != 0; i--) {
+ if (frac > FRAC_MAX)
+ break;
+
+ vco = (post_divm * (divn + 1)) +
+ ((post_divm * (u64)frac) /
+ FRAC_MAX);
+ if (vco < (PLL1600_VCO_MIN / 2) ||
+ vco > (PLL1600_VCO_MAX / 2)) {
+ frac++;
+ continue;
+ }
+ freq = vco / (divp + 1);
+ if (output_freq < freq)
+ diff = (u32)(freq - output_freq);
+ else
+ diff = (u32)(output_freq - freq);
+ if (diff < best_diff) {
+ pllcfg[PLLCFG_M] = divm;
+ pllcfg[PLLCFG_N] = divn;
+ pllcfg[PLLCFG_P] = divp;
+ *fracv = frac;
+
+ if (diff == 0)
+ return 0;
+
+ best_diff = diff;
+ }
+ frac++;
+ }
+ }
+ }
+
+ if (best_diff == U32_MAX)
+ return -1;
+
+ return 0;
+}
+
static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
u32 mask_on)
{
unsigned int clksrc[CLKSRC_NB];
unsigned int clkdiv[CLKDIV_NB];
unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
- ofnode plloff[_PLL_NB];
- int ret, len;
- uint i;
+ unsigned int pllfracv[_PLL_NB];
+ unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
+ bool pllcfg_valid[_PLL_NB];
+ bool pllcsg_set[_PLL_NB];
+ int ret;
+ int i, len;
int lse_css = 0;
const u32 *pkcs_cell;
/* check mandatory field in each pll */
for (i = 0; i < _PLL_NB; i++) {
char name[12];
+ ofnode node;
sprintf(name, "st,pll@%d", i);
- plloff[i] = dev_read_subnode(dev, name);
- if (!ofnode_valid(plloff[i]))
- continue;
- ret = ofnode_read_u32_array(plloff[i], "cfg",
- pllcfg[i], PLLCFG_NB);
- if (ret < 0) {
- debug("field cfg invalid: error %d\n", ret);
- return -FDT_ERR_NOTFOUND;
+ node = dev_read_subnode(dev, name);
+ pllcfg_valid[i] = ofnode_valid(node);
+ pllcsg_set[i] = false;
+ if (pllcfg_valid[i]) {
+ debug("DT for PLL %d @ %s\n", i, name);
+ ret = ofnode_read_u32_array(node, "cfg",
+ pllcfg[i], PLLCFG_NB);
+ if (ret < 0) {
+ debug("field cfg invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+ pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
+
+ ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
+ PLLCSG_NB);
+ if (!ret) {
+ pllcsg_set[i] = true;
+ } else if (ret != -FDT_ERR_NOTFOUND) {
+ debug("invalid csg node for pll@%d res=%d\n",
+ i, ret);
+ return ret;
+ }
+ } else if (i == _PLL1) {
+ /* use OPP for PLL1 for A7 CPU */
+ debug("DT for PLL %d with OPP\n", i);
+ ret = stm32mp1_pll1_opp(priv,
+ clksrc[CLKSRC_PLL12],
+ pllcfg[i],
+ &pllfracv[i]);
+ if (ret) {
+ debug("PLL %d with OPP error = %d\n", i, ret);
+ return ret;
+ }
+ pllcfg_valid[i] = true;
}
}
/* configure and start PLLs */
debug("configure PLLs\n");
for (i = 0; i < _PLL_NB; i++) {
- u32 fracv;
- u32 csg[PLLCSG_NB];
-
- debug("configure PLL %d @ %d\n", i,
- ofnode_to_offset(plloff[i]));
- if (!ofnode_valid(plloff[i]))
+ if (!pllcfg_valid[i])
continue;
-
- fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
- pll_config(priv, i, pllcfg[i], fracv);
- ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
- if (!ret) {
- pll_csg(priv, i, csg);
- } else if (ret != -FDT_ERR_NOTFOUND) {
- debug("invalid csg node for pll@%d res=%d\n", i, ret);
- return ret;
- }
+ debug("configure PLL %d\n", i);
+ pll_config(priv, i, pllcfg[i], pllfracv[i]);
+ if (pllcsg_set[i])
+ pll_csg(priv, i, pllcsg[i]);
pll_start(priv, i);
}
/* wait and start PLLs ouptut when ready */
for (i = 0; i < _PLL_NB; i++) {
- if (!ofnode_valid(plloff[i]))
+ if (!pllcfg_valid[i])
continue;
debug("output PLL %d\n", i);
pll_output(priv, i, pllcfg[i][PLLCFG_O]);
/* clock tree init is done only one time, before relocation */
if (!(gd->flags & GD_FLG_RELOC))
result = stm32mp1_clktree(dev);
+ if (result)
+ printf("clock tree initialization failed (%d)\n", result);
#endif
#ifndef CONFIG_SPL_BUILD
struct versal_clock *clk;
};
-static ulong alt_ref_clk;
static ulong pl_alt_ref_clk;
static ulong ref_clk;
printf("\n ****** VERSAL CLOCKS *****\n");
- printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n",
- alt_ref_clk, pl_alt_ref_clk, ref_clk);
+ printf("pl_alt_ref_clk:%ld ref_clk:%ld\n", pl_alt_ref_clk, ref_clk);
for (i = 0; i < clock_max_idx; i++) {
debug("%s\n", clock[i].clk_name);
ret = versal_get_clock_type(i, &type);
debug("%s\n", __func__);
- ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk);
- if (ret < 0)
- return -EINVAL;
-
ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
dev, &pl_alt_ref_clk);
if (ret < 0)
static int clk_gate2_enable(struct clk *clk)
{
- struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+ struct clk_gate2 *gate = to_clk_gate2(clk);
u32 reg;
reg = readl(gate->reg);
static int clk_gate2_disable(struct clk *clk)
{
- struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+ struct clk_gate2 *gate = to_clk_gate2(clk);
u32 reg;
reg = readl(gate->reg);
clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
base = dev_read_addr_ptr(dev);
- if (base == (void *)FDT_ADDR_T_NONE)
+ if (!base)
return -EINVAL;
clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
--- /dev/null
+config CLK_K210
+ bool "Clock support for Kendryte K210"
+ depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF
+ help
+ This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+ bool "Enable setting the Kendryte K210 PLL rate"
+ depends on CLK_K210
+ help
+ Add functionality to calculate new rates for K210 PLLs. Enabling this
+ feature adds around 1K to U-Boot's final size.
--- /dev/null
+obj-y += bypass.o clk.o pll.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_CLK
+#include <kendryte/bypass.h>
+
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <log.h>
+
+#define CLK_K210_BYPASS "k210_clk_bypass"
+
+/*
+ * This is a small driver to do a software bypass of a clock if hardware bypass
+ * is not working. I have tried to write this in a generic fashion, so that it
+ * could be potentially broken out of the kendryte code at some future date.
+ *
+ * Say you have the following clock configuration
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ * ^
+ * /|
+ * / |
+ * / |
+ * / |
+ * / |
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * But the pll does not have a bypass, so when you configure the pll, the
+ * configuration needs to change to look like
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ * ^
+ * |\
+ * | \
+ * | \
+ * | \
+ * | \
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
+ * creating the child clocks, set their parent to the bypass clock. After
+ * creating all the children, call k210_bypass_setchildren().
+ */
+
+static int k210_bypass_dobypass(struct k210_bypass *bypass)
+{
+ int ret, i;
+
+ /*
+ * If we already have saved parents, then the children are already
+ * bypassed
+ */
+ if (bypass->child_count && bypass->saved_parents[0])
+ return 0;
+
+ for (i = 0; i < bypass->child_count; i++) {
+ struct clk *child = bypass->children[i];
+ struct clk *parent = clk_get_parent(child);
+
+ if (IS_ERR(parent)) {
+ for (; i; i--)
+ bypass->saved_parents[i] = NULL;
+ return PTR_ERR(parent);
+ }
+ bypass->saved_parents[i] = parent;
+ }
+
+ for (i = 0; i < bypass->child_count; i++) {
+ struct clk *child = bypass->children[i];
+
+ ret = clk_set_parent(child, bypass->alt);
+ if (ret) {
+ for (; i; i--)
+ clk_set_parent(bypass->children[i],
+ bypass->saved_parents[i]);
+ for (i = 0; i < bypass->child_count; i++)
+ bypass->saved_parents[i] = NULL;
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int k210_bypass_unbypass(struct k210_bypass *bypass)
+{
+ int err, ret, i;
+
+ if (!bypass->child_count && !bypass->saved_parents[0]) {
+ log_warning("Cannot unbypass children; dobypass not called first\n");
+ return 0;
+ }
+
+ ret = 0;
+ for (i = 0; i < bypass->child_count; i++) {
+ err = clk_set_parent(bypass->children[i],
+ bypass->saved_parents[i]);
+ if (err)
+ ret = err;
+ bypass->saved_parents[i] = NULL;
+ }
+ return ret;
+}
+
+static ulong k210_bypass_get_rate(struct clk *clk)
+{
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+ const struct clk_ops *ops = bypass->bypassee_ops;
+
+ if (ops->get_rate)
+ return ops->get_rate(bypass->bypassee);
+ else
+ return clk_get_parent_rate(bypass->bypassee);
+}
+
+static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret;
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+ const struct clk_ops *ops = bypass->bypassee_ops;
+
+ /* Don't bother bypassing if we aren't going to set the rate */
+ if (!ops->set_rate)
+ return k210_bypass_get_rate(clk);
+
+ ret = k210_bypass_dobypass(bypass);
+ if (ret)
+ return ret;
+
+ ret = ops->set_rate(bypass->bypassee, rate);
+ if (ret < 0)
+ return ret;
+
+ return k210_bypass_unbypass(bypass);
+}
+
+static int k210_bypass_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+ const struct clk_ops *ops = bypass->bypassee_ops;
+
+ if (ops->set_parent)
+ return ops->set_parent(bypass->bypassee, parent);
+ else
+ return -ENOTSUPP;
+}
+
+/*
+ * For these next two functions, do the bypassing even if there is no
+ * en-/-disable function, since the bypassing itself can be observed in between
+ * calls.
+ */
+static int k210_bypass_enable(struct clk *clk)
+{
+ int ret;
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+ const struct clk_ops *ops = bypass->bypassee_ops;
+
+ ret = k210_bypass_dobypass(bypass);
+ if (ret)
+ return ret;
+
+ if (ops->enable)
+ ret = ops->enable(bypass->bypassee);
+ else
+ ret = 0;
+ if (ret)
+ return ret;
+
+ return k210_bypass_unbypass(bypass);
+}
+
+static int k210_bypass_disable(struct clk *clk)
+{
+ int ret;
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+ const struct clk_ops *ops = bypass->bypassee_ops;
+
+ ret = k210_bypass_dobypass(bypass);
+ if (ret)
+ return ret;
+
+ if (ops->disable)
+ return ops->disable(bypass->bypassee);
+ else
+ return 0;
+}
+
+static const struct clk_ops k210_bypass_ops = {
+ .get_rate = k210_bypass_get_rate,
+ .set_rate = k210_bypass_set_rate,
+ .set_parent = k210_bypass_set_parent,
+ .enable = k210_bypass_enable,
+ .disable = k210_bypass_disable,
+};
+
+int k210_bypass_set_children(struct clk *clk, struct clk **children,
+ size_t child_count)
+{
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+
+ kfree(bypass->saved_parents);
+ if (child_count) {
+ bypass->saved_parents =
+ kcalloc(child_count, sizeof(struct clk *), GFP_KERNEL);
+ if (!bypass->saved_parents)
+ return -ENOMEM;
+ }
+ bypass->child_count = child_count;
+ bypass->children = children;
+
+ return 0;
+}
+
+struct clk *k210_register_bypass_struct(const char *name,
+ const char *parent_name,
+ struct k210_bypass *bypass)
+{
+ int ret;
+ struct clk *clk;
+
+ clk = &bypass->clk;
+
+ ret = clk_register(clk, CLK_K210_BYPASS, name, parent_name);
+ if (ret)
+ return ERR_PTR(ret);
+
+ bypass->bypassee->dev = clk->dev;
+ return clk;
+}
+
+struct clk *k210_register_bypass(const char *name, const char *parent_name,
+ struct clk *bypassee,
+ const struct clk_ops *bypassee_ops,
+ struct clk *alt)
+{
+ struct clk *clk;
+ struct k210_bypass *bypass;
+
+ bypass = kzalloc(sizeof(*bypass), GFP_KERNEL);
+ if (!bypass)
+ return ERR_PTR(-ENOMEM);
+
+ bypass->bypassee = bypassee;
+ bypass->bypassee_ops = bypassee_ops;
+ bypass->alt = alt;
+
+ clk = k210_register_bypass_struct(name, parent_name, bypass);
+ if (IS_ERR(clk))
+ kfree(bypass);
+ return clk;
+}
+
+U_BOOT_DRIVER(k210_bypass) = {
+ .name = CLK_K210_BYPASS,
+ .id = UCLASS_CLK,
+ .ops = &k210_bypass_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+#include <kendryte/clk.h>
+
+#include <asm/io.h>
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <dt-bindings/mfd/k210-sysctl.h>
+#include <dm.h>
+#include <log.h>
+#include <mapmem.h>
+
+#include <kendryte/bypass.h>
+#include <kendryte/pll.h>
+
+/* All methods are delegated to CCF clocks */
+
+static ulong k210_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, &c);
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, &c);
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, &c);
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, &p);
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int k210_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, &c);
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int k210_clk_enable(struct clk *clk)
+{
+ return k210_clk_endisable(clk, true);
+}
+
+static int k210_clk_disable(struct clk *clk)
+{
+ return k210_clk_endisable(clk, false);
+}
+
+static const struct clk_ops k210_clk_ops = {
+ .set_rate = k210_clk_set_rate,
+ .get_rate = k210_clk_get_rate,
+ .set_parent = k210_clk_set_parent,
+ .enable = k210_clk_enable,
+ .disable = k210_clk_disable,
+};
+
+/* Parents for muxed clocks */
+static const char * const generic_sels[] = { "in0_half", "pll0_half" };
+/* The first clock is in0, which is filled in by k210_clk_probe */
+static const char *aclk_sels[] = { NULL, "pll0_half" };
+static const char *pll2_sels[] = { NULL, "pll0", "pll1" };
+
+/*
+ * All parameters for different sub-clocks are collected into parameter arrays.
+ * These parameters are then initialized by the clock which uses them during
+ * probe. To save space, ids are automatically generated for each sub-clock by
+ * using an enum. Instead of storing a parameter struct for each clock, even for
+ * those clocks which don't use a particular type of sub-clock, we can just
+ * store the parameters for the clocks which need them.
+ *
+ * So why do it like this? Arranging all the sub-clocks together makes it very
+ * easy to find bugs in the code.
+ */
+
+#define DIV(id, off, shift, width) DIV_FLAGS(id, off, shift, width, 0)
+#define DIV_LIST \
+ DIV_FLAGS(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, \
+ CLK_DIVIDER_POWER_OF_TWO) \
+ DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3) \
+ DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3) \
+ DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3) \
+ DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4) \
+ DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4) \
+ DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4) \
+ DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4) \
+ DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4) \
+ DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8) \
+ DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8) \
+ DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8) \
+ DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8) \
+ DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8) \
+ DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8) \
+ DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8) \
+ DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16) \
+ DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16) \
+ DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16) \
+ DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8) \
+ DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8) \
+ DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8) \
+ DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8) \
+ DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8) \
+ DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8) \
+ DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8) \
+ DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8)
+
+#define _DIVIFY(id) K210_CLK_DIV_##id
+#define DIVIFY(id) _DIVIFY(id)
+
+enum k210_div_ids {
+#define DIV_FLAGS(id, ...) DIVIFY(id),
+ DIV_LIST
+#undef DIV_FLAGS
+};
+
+struct k210_div_params {
+ u8 off;
+ u8 shift;
+ u8 width;
+ u8 flags;
+};
+
+static const struct k210_div_params k210_divs[] = {
+#define DIV_FLAGS(id, _off, _shift, _width, _flags) \
+ [DIVIFY(id)] = { \
+ .off = (_off), \
+ .shift = (_shift), \
+ .width = (_width), \
+ .flags = (_flags), \
+ },
+ DIV_LIST
+#undef DIV_FLAGS
+};
+
+#undef DIV
+#undef DIV_LIST
+
+#define GATE_LIST \
+ GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \
+ GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \
+ GATE(K210_CLK_SRAM1, K210_SYSCTL_EN_CENT, 2) \
+ GATE(K210_CLK_APB0, K210_SYSCTL_EN_CENT, 3) \
+ GATE(K210_CLK_APB1, K210_SYSCTL_EN_CENT, 4) \
+ GATE(K210_CLK_APB2, K210_SYSCTL_EN_CENT, 5) \
+ GATE(K210_CLK_ROM, K210_SYSCTL_EN_PERI, 0) \
+ GATE(K210_CLK_DMA, K210_SYSCTL_EN_PERI, 1) \
+ GATE(K210_CLK_AI, K210_SYSCTL_EN_PERI, 2) \
+ GATE(K210_CLK_DVP, K210_SYSCTL_EN_PERI, 3) \
+ GATE(K210_CLK_FFT, K210_SYSCTL_EN_PERI, 4) \
+ GATE(K210_CLK_GPIO, K210_SYSCTL_EN_PERI, 5) \
+ GATE(K210_CLK_SPI0, K210_SYSCTL_EN_PERI, 6) \
+ GATE(K210_CLK_SPI1, K210_SYSCTL_EN_PERI, 7) \
+ GATE(K210_CLK_SPI2, K210_SYSCTL_EN_PERI, 8) \
+ GATE(K210_CLK_SPI3, K210_SYSCTL_EN_PERI, 9) \
+ GATE(K210_CLK_I2S0, K210_SYSCTL_EN_PERI, 10) \
+ GATE(K210_CLK_I2S1, K210_SYSCTL_EN_PERI, 11) \
+ GATE(K210_CLK_I2S2, K210_SYSCTL_EN_PERI, 12) \
+ GATE(K210_CLK_I2C0, K210_SYSCTL_EN_PERI, 13) \
+ GATE(K210_CLK_I2C1, K210_SYSCTL_EN_PERI, 14) \
+ GATE(K210_CLK_I2C2, K210_SYSCTL_EN_PERI, 15) \
+ GATE(K210_CLK_UART1, K210_SYSCTL_EN_PERI, 16) \
+ GATE(K210_CLK_UART2, K210_SYSCTL_EN_PERI, 17) \
+ GATE(K210_CLK_UART3, K210_SYSCTL_EN_PERI, 18) \
+ GATE(K210_CLK_AES, K210_SYSCTL_EN_PERI, 19) \
+ GATE(K210_CLK_FPIOA, K210_SYSCTL_EN_PERI, 20) \
+ GATE(K210_CLK_TIMER0, K210_SYSCTL_EN_PERI, 21) \
+ GATE(K210_CLK_TIMER1, K210_SYSCTL_EN_PERI, 22) \
+ GATE(K210_CLK_TIMER2, K210_SYSCTL_EN_PERI, 23) \
+ GATE(K210_CLK_WDT0, K210_SYSCTL_EN_PERI, 24) \
+ GATE(K210_CLK_WDT1, K210_SYSCTL_EN_PERI, 25) \
+ GATE(K210_CLK_SHA, K210_SYSCTL_EN_PERI, 26) \
+ GATE(K210_CLK_OTP, K210_SYSCTL_EN_PERI, 27) \
+ GATE(K210_CLK_RTC, K210_SYSCTL_EN_PERI, 29)
+
+#define _GATEIFY(id) K210_CLK_GATE_##id
+#define GATEIFY(id) _GATEIFY(id)
+
+enum k210_gate_ids {
+#define GATE(id, ...) GATEIFY(id),
+ GATE_LIST
+#undef GATE
+};
+
+struct k210_gate_params {
+ u8 off;
+ u8 bit_idx;
+};
+
+static const struct k210_gate_params k210_gates[] = {
+#define GATE(id, _off, _idx) \
+ [GATEIFY(id)] = { \
+ .off = (_off), \
+ .bit_idx = (_idx), \
+ },
+ GATE_LIST
+#undef GATE
+};
+
+#undef GATE_LIST
+
+#define MUX(id, reg, shift, width) \
+ MUX_PARENTS(id, generic_sels, reg, shift, width)
+#define MUX_LIST \
+ MUX_PARENTS(K210_CLK_PLL2, pll2_sels, K210_SYSCTL_PLL2, 26, 2) \
+ MUX_PARENTS(K210_CLK_ACLK, aclk_sels, K210_SYSCTL_SEL0, 0, 1) \
+ MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \
+ MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \
+ MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \
+ MUX(K210_CLK_TIMER2, K210_SYSCTL_SEL0, 15, 1)
+
+#define _MUXIFY(id) K210_CLK_MUX_##id
+#define MUXIFY(id) _MUXIFY(id)
+
+enum k210_mux_ids {
+#define MUX_PARENTS(id, ...) MUXIFY(id),
+ MUX_LIST
+#undef MUX_PARENTS
+ K210_CLK_MUX_NONE,
+};
+
+struct k210_mux_params {
+ const char *const *parent_names;
+ u8 num_parents;
+ u8 off;
+ u8 shift;
+ u8 width;
+};
+
+static const struct k210_mux_params k210_muxes[] = {
+#define MUX_PARENTS(id, parents, _off, _shift, _width) \
+ [MUXIFY(id)] = { \
+ .parent_names = (const char * const *)(parents), \
+ .num_parents = ARRAY_SIZE(parents), \
+ .off = (_off), \
+ .shift = (_shift), \
+ .width = (_width), \
+ },
+ MUX_LIST
+#undef MUX_PARENTS
+};
+
+#undef MUX
+#undef MUX_LIST
+
+struct k210_pll_params {
+ u8 off;
+ u8 lock_off;
+ u8 shift;
+ u8 width;
+};
+
+static const struct k210_pll_params k210_plls[] = {
+#define PLL(_off, _shift, _width) { \
+ .off = (_off), \
+ .lock_off = K210_SYSCTL_PLL_LOCK, \
+ .shift = (_shift), \
+ .width = (_width), \
+}
+ [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
+ [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
+ [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
+#undef PLL
+};
+
+#define COMP(id) \
+ COMP_FULL(id, MUXIFY(id), DIVIFY(id), GATEIFY(id))
+#define COMP_NOMUX(id) \
+ COMP_FULL(id, K210_CLK_MUX_NONE, DIVIFY(id), GATEIFY(id))
+#define COMP_LIST \
+ COMP(K210_CLK_SPI3) \
+ COMP(K210_CLK_TIMER0) \
+ COMP(K210_CLK_TIMER1) \
+ COMP(K210_CLK_TIMER2) \
+ COMP_NOMUX(K210_CLK_SRAM0) \
+ COMP_NOMUX(K210_CLK_SRAM1) \
+ COMP_NOMUX(K210_CLK_ROM) \
+ COMP_NOMUX(K210_CLK_DVP) \
+ COMP_NOMUX(K210_CLK_APB0) \
+ COMP_NOMUX(K210_CLK_APB1) \
+ COMP_NOMUX(K210_CLK_APB2) \
+ COMP_NOMUX(K210_CLK_AI) \
+ COMP_NOMUX(K210_CLK_I2S0) \
+ COMP_NOMUX(K210_CLK_I2S1) \
+ COMP_NOMUX(K210_CLK_I2S2) \
+ COMP_NOMUX(K210_CLK_WDT0) \
+ COMP_NOMUX(K210_CLK_WDT1) \
+ COMP_NOMUX(K210_CLK_SPI0) \
+ COMP_NOMUX(K210_CLK_SPI1) \
+ COMP_NOMUX(K210_CLK_SPI2) \
+ COMP_NOMUX(K210_CLK_I2C0) \
+ COMP_NOMUX(K210_CLK_I2C1) \
+ COMP_NOMUX(K210_CLK_I2C2)
+
+#define _COMPIFY(id) K210_CLK_COMP_##id
+#define COMPIFY(id) _COMPIFY(id)
+
+enum k210_comp_ids {
+#define COMP_FULL(id, ...) COMPIFY(id),
+ COMP_LIST
+#undef COMP_FULL
+};
+
+struct k210_comp_params {
+ u8 mux;
+ u8 div;
+ u8 gate;
+};
+
+static const struct k210_comp_params k210_comps[] = {
+#define COMP_FULL(id, _mux, _div, _gate) \
+ [COMPIFY(id)] = { \
+ .mux = (_mux), \
+ .div = (_div), \
+ .gate = (_gate), \
+ },
+ COMP_LIST
+#undef COMP_FULL
+};
+
+#undef COMP
+#undef COMP_ID
+#undef COMP_NOMUX
+#undef COMP_NOMUX_ID
+#undef COMP_LIST
+
+static struct clk *k210_bypass_children = {
+ NULL,
+};
+
+/* Helper functions to create sub-clocks */
+static struct clk_mux *k210_create_mux(const struct k210_mux_params *params,
+ void *base)
+{
+ struct clk_mux *mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+
+ if (!mux)
+ return mux;
+
+ mux->reg = base + params->off;
+ mux->mask = BIT(params->width) - 1;
+ mux->shift = params->shift;
+ mux->parent_names = params->parent_names;
+ mux->num_parents = params->num_parents;
+
+ return mux;
+}
+
+static struct clk_divider *k210_create_div(const struct k210_div_params *params,
+ void *base)
+{
+ struct clk_divider *div = kzalloc(sizeof(*div), GFP_KERNEL);
+
+ if (!div)
+ return div;
+
+ div->reg = base + params->off;
+ div->shift = params->shift;
+ div->width = params->width;
+ div->flags = params->flags;
+
+ return div;
+}
+
+static struct clk_gate *k210_create_gate(const struct k210_gate_params *params,
+ void *base)
+{
+ struct clk_gate *gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+
+ if (!gate)
+ return gate;
+
+ gate->reg = base + params->off;
+ gate->bit_idx = params->bit_idx;
+
+ return gate;
+}
+
+static struct k210_pll *k210_create_pll(const struct k210_pll_params *params,
+ void *base)
+{
+ struct k210_pll *pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+
+ if (!pll)
+ return pll;
+
+ pll->reg = base + params->off;
+ pll->lock = base + params->lock_off;
+ pll->shift = params->shift;
+ pll->width = params->width;
+
+ return pll;
+}
+
+/* Create all sub-clocks, and then register the composite clock */
+static struct clk *k210_register_comp(const struct k210_comp_params *params,
+ void *base, const char *name,
+ const char *parent)
+{
+ const char *const *parent_names;
+ int num_parents;
+ struct clk *comp;
+ const struct clk_ops *mux_ops;
+ struct clk_mux *mux;
+ struct clk_divider *div;
+ struct clk_gate *gate;
+
+ if (params->mux == K210_CLK_MUX_NONE) {
+ if (!parent)
+ return ERR_PTR(-EINVAL);
+
+ mux_ops = NULL;
+ mux = NULL;
+ parent_names = &parent;
+ num_parents = 1;
+ } else {
+ mux_ops = &clk_mux_ops;
+ mux = k210_create_mux(&k210_muxes[params->mux], base);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ parent_names = mux->parent_names;
+ num_parents = mux->num_parents;
+ }
+
+ div = k210_create_div(&k210_divs[params->div], base);
+ if (!div) {
+ comp = ERR_PTR(-ENOMEM);
+ goto cleanup_mux;
+ }
+
+ gate = k210_create_gate(&k210_gates[params->gate], base);
+ if (!gate) {
+ comp = ERR_PTR(-ENOMEM);
+ goto cleanup_div;
+ }
+
+ comp = clk_register_composite(NULL, name, parent_names, num_parents,
+ &mux->clk, mux_ops,
+ &div->clk, &clk_divider_ops,
+ &gate->clk, &clk_gate_ops, 0);
+ if (IS_ERR(comp))
+ goto cleanup_gate;
+ return comp;
+
+cleanup_gate:
+ free(gate);
+cleanup_div:
+ free(div);
+cleanup_mux:
+ if (mux)
+ free(mux);
+ return comp;
+}
+
+static bool probed;
+
+static int k210_clk_probe(struct udevice *dev)
+{
+ int ret;
+ const char *in0;
+ struct clk *in0_clk, *bypass;
+ struct clk_mux *mux;
+ struct clk_divider *div;
+ struct k210_pll *pll;
+ void *base;
+
+ /*
+ * Only one instance of this driver allowed. This prevents weird bugs
+ * when the driver fails part-way through probing. Some clocks will
+ * already have been registered, and re-probing will register them
+ * again, creating a bunch of duplicates. Better error-handling/cleanup
+ * could fix this, but it's Probably Not Worth It (TM).
+ */
+ if (probed)
+ return -ENOTSUPP;
+
+ base = dev_read_addr_ptr(dev_get_parent(dev));
+ if (!base)
+ return -EINVAL;
+
+ in0_clk = kzalloc(sizeof(*in0_clk), GFP_KERNEL);
+ if (!in0_clk)
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 0, in0_clk);
+ if (ret)
+ return ret;
+ in0 = in0_clk->dev->name;
+
+ probed = true;
+
+ aclk_sels[0] = in0;
+ pll2_sels[0] = in0;
+
+ /*
+ * All PLLs have a broken bypass, but pll0 has the CPU downstream, so we
+ * need to manually reparent it whenever we configure pll0
+ */
+ pll = k210_create_pll(&k210_plls[0], base);
+ if (pll) {
+ bypass = k210_register_bypass("pll0", in0, &pll->clk,
+ &k210_pll_ops, in0_clk);
+ clk_dm(K210_CLK_PLL0, bypass);
+ } else {
+ return -ENOMEM;
+ }
+
+ {
+ const struct k210_pll_params *params = &k210_plls[1];
+
+ clk_dm(K210_CLK_PLL1,
+ k210_register_pll("pll1", in0, base + params->off,
+ base + params->lock_off, params->shift,
+ params->width));
+ }
+
+ /* PLL2 is muxed, so set up a composite clock */
+ mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base);
+ pll = k210_create_pll(&k210_plls[2], base);
+ if (!mux || !pll) {
+ free(mux);
+ free(pll);
+ } else {
+ clk_dm(K210_CLK_PLL2,
+ clk_register_composite(NULL, "pll2", pll2_sels,
+ ARRAY_SIZE(pll2_sels),
+ &mux->clk, &clk_mux_ops,
+ &pll->clk, &k210_pll_ops,
+ &pll->clk, &k210_pll_ops, 0));
+ }
+
+ /* Half-frequency clocks for "even" dividers */
+ clk_dm(K210_CLK_IN0_H, k210_clk_half("in0_half", in0));
+ clk_dm(K210_CLK_PLL0_H, k210_clk_half("pll0_half", "pll0"));
+ clk_dm(K210_CLK_PLL2_H, k210_clk_half("pll2_half", "pll2"));
+
+ /* ACLK has no gate */
+ mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_ACLK)], base);
+ div = k210_create_div(&k210_divs[DIVIFY(K210_CLK_ACLK)], base);
+ if (!mux || !div) {
+ free(mux);
+ free(div);
+ } else {
+ struct clk *aclk =
+ clk_register_composite(NULL, "aclk", aclk_sels,
+ ARRAY_SIZE(aclk_sels),
+ &mux->clk, &clk_mux_ops,
+ &div->clk, &clk_divider_ops,
+ NULL, NULL, 0);
+ clk_dm(K210_CLK_ACLK, aclk);
+ if (!IS_ERR(aclk)) {
+ k210_bypass_children = aclk;
+ k210_bypass_set_children(bypass,
+ &k210_bypass_children, 1);
+ }
+ }
+
+#define REGISTER_COMP(id, name) \
+ clk_dm(id, \
+ k210_register_comp(&k210_comps[COMPIFY(id)], base, name, NULL))
+ REGISTER_COMP(K210_CLK_SPI3, "spi3");
+ REGISTER_COMP(K210_CLK_TIMER0, "timer0");
+ REGISTER_COMP(K210_CLK_TIMER1, "timer1");
+ REGISTER_COMP(K210_CLK_TIMER2, "timer2");
+#undef REGISTER_COMP
+
+ /* Dividing clocks, no mux */
+#define REGISTER_COMP_NOMUX(id, name, parent) \
+ clk_dm(id, \
+ k210_register_comp(&k210_comps[COMPIFY(id)], base, name, parent))
+ REGISTER_COMP_NOMUX(K210_CLK_SRAM0, "sram0", "aclk");
+ REGISTER_COMP_NOMUX(K210_CLK_SRAM1, "sram1", "aclk");
+ REGISTER_COMP_NOMUX(K210_CLK_ROM, "rom", "aclk");
+ REGISTER_COMP_NOMUX(K210_CLK_DVP, "dvp", "aclk");
+ REGISTER_COMP_NOMUX(K210_CLK_APB0, "apb0", "aclk");
+ REGISTER_COMP_NOMUX(K210_CLK_APB1, "apb1", "aclk");
+ REGISTER_COMP_NOMUX(K210_CLK_APB2, "apb2", "aclk");
+ REGISTER_COMP_NOMUX(K210_CLK_AI, "ai", "pll1");
+ REGISTER_COMP_NOMUX(K210_CLK_I2S0, "i2s0", "pll2_half");
+ REGISTER_COMP_NOMUX(K210_CLK_I2S1, "i2s1", "pll2_half");
+ REGISTER_COMP_NOMUX(K210_CLK_I2S2, "i2s2", "pll2_half");
+ REGISTER_COMP_NOMUX(K210_CLK_WDT0, "wdt0", "in0_half");
+ REGISTER_COMP_NOMUX(K210_CLK_WDT1, "wdt1", "in0_half");
+ REGISTER_COMP_NOMUX(K210_CLK_SPI0, "spi0", "pll0_half");
+ REGISTER_COMP_NOMUX(K210_CLK_SPI1, "spi1", "pll0_half");
+ REGISTER_COMP_NOMUX(K210_CLK_SPI2, "spi2", "pll0_half");
+ REGISTER_COMP_NOMUX(K210_CLK_I2C0, "i2c0", "pll0_half");
+ REGISTER_COMP_NOMUX(K210_CLK_I2C1, "i2c1", "pll0_half");
+ REGISTER_COMP_NOMUX(K210_CLK_I2C2, "i2c2", "pll0_half");
+#undef REGISTER_COMP_NOMUX
+
+ /* Dividing clocks */
+#define REGISTER_DIV(id, name, parent) do {\
+ const struct k210_div_params *params = &k210_divs[DIVIFY(id)]; \
+ clk_dm(id, \
+ clk_register_divider(NULL, name, parent, 0, base + params->off, \
+ params->shift, params->width, 0)); \
+} while (false)
+ REGISTER_DIV(K210_CLK_I2S0_M, "i2s0_m", "pll2_half");
+ REGISTER_DIV(K210_CLK_I2S1_M, "i2s1_m", "pll2_half");
+ REGISTER_DIV(K210_CLK_I2S2_M, "i2s2_m", "pll2_half");
+#undef REGISTER_DIV
+
+ /* Gated clocks */
+#define REGISTER_GATE(id, name, parent) do { \
+ const struct k210_gate_params *params = &k210_gates[GATEIFY(id)]; \
+ clk_dm(id, \
+ clk_register_gate(NULL, name, parent, 0, base + params->off, \
+ params->bit_idx, 0, NULL)); \
+} while (false)
+ REGISTER_GATE(K210_CLK_CPU, "cpu", "aclk");
+ REGISTER_GATE(K210_CLK_DMA, "dma", "aclk");
+ REGISTER_GATE(K210_CLK_FFT, "fft", "aclk");
+ REGISTER_GATE(K210_CLK_GPIO, "gpio", "apb0");
+ REGISTER_GATE(K210_CLK_UART1, "uart1", "apb0");
+ REGISTER_GATE(K210_CLK_UART2, "uart2", "apb0");
+ REGISTER_GATE(K210_CLK_UART3, "uart3", "apb0");
+ REGISTER_GATE(K210_CLK_FPIOA, "fpioa", "apb0");
+ REGISTER_GATE(K210_CLK_SHA, "sha", "apb0");
+ REGISTER_GATE(K210_CLK_AES, "aes", "apb1");
+ REGISTER_GATE(K210_CLK_OTP, "otp", "apb1");
+ REGISTER_GATE(K210_CLK_RTC, "rtc", in0);
+#undef REGISTER_GATE
+
+ return 0;
+}
+
+static const struct udevice_id k210_clk_ids[] = {
+ { .compatible = "kendryte,k210-clk" },
+ { },
+};
+
+U_BOOT_DRIVER(k210_clk) = {
+ .name = "k210_clk",
+ .id = UCLASS_CLK,
+ .of_match = k210_clk_ids,
+ .ops = &k210_clk_ops,
+ .probe = k210_clk_probe,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+#define LOG_CATEGORY UCLASS_CLK
+#include <kendryte/pll.h>
+
+#include <asm/io.h>
+/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
+#include <div64.h>
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <log.h>
+#include <serial.h>
+
+#define CLK_K210_PLL "k210_clk_pll"
+
+#ifdef CONFIG_CLK_K210_SET_RATE
+static int k210_pll_enable(struct clk *clk);
+static int k210_pll_disable(struct clk *clk);
+
+/*
+ * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
+ * General-Purpose PLL. The logical layout of the PLL with internal feedback is
+ * approximately the following:
+ *
+ * +---------------+
+ * |reference clock|
+ * +---------------+
+ * |
+ * v
+ * +--+
+ * |/r|
+ * +--+
+ * |
+ * v
+ * +-------------+
+ * |divided clock|
+ * +-------------+
+ * |
+ * v
+ * +--------------+
+ * |phase detector|<---+
+ * +--------------+ |
+ * | |
+ * v +--------------+
+ * +---+ |feedback clock|
+ * |VCO| +--------------+
+ * +---+ ^
+ * | +--+ |
+ * +--->|/f|---+
+ * | +--+
+ * v
+ * +---+
+ * |/od|
+ * +---+
+ * |
+ * v
+ * +------+
+ * |output|
+ * +------+
+ *
+ * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
+ * the effect of the division by f is to multiply the input frequency. The
+ * equation for the output rate is
+ * rate = (rate_in * f) / (r * od).
+ * Moving knowns to one side of the equation, we get
+ * rate / rate_in = f / (r * od)
+ * Rearranging slightly,
+ * abs_error = abs((rate / rate_in) - (f / (r * od))).
+ * To get relative, error, we divide by the expected ratio
+ * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
+ * Simplifying,
+ * error = abs(1 - f / (r * od)) / (rate / rate_in)
+ * error = abs(1 - (f * rate_in) / (r * od * rate))
+ * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
+ * error = abs((f * inv_ratio) / (r * od) - 1)
+ * This is the error used in evaluating parameters.
+ *
+ * r and od are four bits each, while f is six bits. Because r and od are
+ * multiplied together, instead of the full 256 values possible if both bits
+ * were used fully, there are only 97 distinct products. Combined with f, there
+ * are 6208 theoretical settings for the PLL. However, most of these settings
+ * can be ruled out immediately because they do not have the correct ratio.
+ *
+ * In addition to the constraint of approximating the desired ratio, parameters
+ * must also keep internal pll frequencies within acceptable ranges. The divided
+ * clock's minimum and maximum frequencies have a ratio of around 128. This
+ * leaves fairly substantial room to work with, especially since the only
+ * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
+ * of 5, which is considerably more restrictive.
+ *
+ * The r and od factors are stored in a table. This is to make it easy to find
+ * the next-largest product. Some products have multiple factorizations, but
+ * only when one factor has at least a 2.5x ratio to the factors of the other
+ * factorization. This is because any smaller ratio would not make a difference
+ * when ensuring the VCO's frequency is within spec.
+ *
+ * Throughout the calculation function, fixed point arithmetic is used. Because
+ * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
+ * 32.32 fixed-point numbers are used to represent ratios. In general, to
+ * implement division, the numerator is first multiplied by 2^32. This gives a
+ * result where the whole number part is in the upper 32 bits, and the fraction
+ * is in the lower 32 bits.
+ *
+ * In general, rounding is done to the closest integer. This helps find the best
+ * approximation for the ratio. Rounding in one direction (e.g down) could cause
+ * the function to miss a better ratio with one of the parameters increased by
+ * one.
+ */
+
+/*
+ * The factors table was generated with the following python code:
+ *
+ * def p(x, y):
+ * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
+ *
+ * factors = {}
+ * for i in range(1, 17):
+ * for j in range(1, 17):
+ * fs = factors.get(i*j) or []
+ * if fs == [] or all([
+ * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
+ * for (x, y) in fs]):
+ * fs.append((i, j))
+ * factors[i*j] = fs
+ *
+ * for k, l in sorted(factors.items()):
+ * for v in l:
+ * print("PACK(%s, %s)," % v)
+ */
+#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
+#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
+#define UNPACK_OD(val) (((val) & 0xF) + 1)
+static const u8 factors[] = {
+ PACK(1, 1),
+ PACK(1, 2),
+ PACK(1, 3),
+ PACK(1, 4),
+ PACK(1, 5),
+ PACK(1, 6),
+ PACK(1, 7),
+ PACK(1, 8),
+ PACK(1, 9),
+ PACK(3, 3),
+ PACK(1, 10),
+ PACK(1, 11),
+ PACK(1, 12),
+ PACK(3, 4),
+ PACK(1, 13),
+ PACK(1, 14),
+ PACK(1, 15),
+ PACK(3, 5),
+ PACK(1, 16),
+ PACK(4, 4),
+ PACK(2, 9),
+ PACK(2, 10),
+ PACK(3, 7),
+ PACK(2, 11),
+ PACK(2, 12),
+ PACK(5, 5),
+ PACK(2, 13),
+ PACK(3, 9),
+ PACK(2, 14),
+ PACK(2, 15),
+ PACK(2, 16),
+ PACK(3, 11),
+ PACK(5, 7),
+ PACK(3, 12),
+ PACK(3, 13),
+ PACK(4, 10),
+ PACK(3, 14),
+ PACK(4, 11),
+ PACK(3, 15),
+ PACK(3, 16),
+ PACK(7, 7),
+ PACK(5, 10),
+ PACK(4, 13),
+ PACK(6, 9),
+ PACK(5, 11),
+ PACK(4, 14),
+ PACK(4, 15),
+ PACK(7, 9),
+ PACK(4, 16),
+ PACK(5, 13),
+ PACK(6, 11),
+ PACK(5, 14),
+ PACK(6, 12),
+ PACK(5, 15),
+ PACK(7, 11),
+ PACK(6, 13),
+ PACK(5, 16),
+ PACK(9, 9),
+ PACK(6, 14),
+ PACK(8, 11),
+ PACK(6, 15),
+ PACK(7, 13),
+ PACK(6, 16),
+ PACK(7, 14),
+ PACK(9, 11),
+ PACK(10, 10),
+ PACK(8, 13),
+ PACK(7, 15),
+ PACK(9, 12),
+ PACK(10, 11),
+ PACK(7, 16),
+ PACK(9, 13),
+ PACK(8, 15),
+ PACK(11, 11),
+ PACK(9, 14),
+ PACK(8, 16),
+ PACK(10, 13),
+ PACK(11, 12),
+ PACK(9, 15),
+ PACK(10, 14),
+ PACK(11, 13),
+ PACK(9, 16),
+ PACK(10, 15),
+ PACK(11, 14),
+ PACK(12, 13),
+ PACK(10, 16),
+ PACK(11, 15),
+ PACK(12, 14),
+ PACK(13, 13),
+ PACK(11, 16),
+ PACK(12, 15),
+ PACK(13, 14),
+ PACK(12, 16),
+ PACK(13, 15),
+ PACK(14, 14),
+ PACK(13, 16),
+ PACK(14, 15),
+ PACK(14, 16),
+ PACK(15, 15),
+ PACK(15, 16),
+ PACK(16, 16),
+};
+
+TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
+ struct k210_pll_config *best)
+{
+ int i;
+ s64 error, best_error;
+ u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
+ u64 max_r;
+ u64 r, f, od;
+
+ /*
+ * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
+ * VCO frequency. These are not the same limits as below because od can
+ * reduce the output frequency by 16.
+ */
+ if (rate > 1750000000 || rate < 21250000)
+ return -EINVAL;
+
+ /* Similar restrictions on the input rate */
+ if (rate_in > 1750000000 || rate_in < 13300000)
+ return -EINVAL;
+
+ ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
+ inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
+ /* Can't increase by more than 64 or reduce by more than 256 */
+ if (rate > rate_in && ratio > (64ULL << 32))
+ return -EINVAL;
+ else if (rate <= rate_in && inv_ratio > (256ULL << 32))
+ return -EINVAL;
+
+ /*
+ * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
+ * MHz. There is no minimum, since the only way to get a higher input
+ * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
+ * cannot output frequencies greater than 1.75 GHz, the minimum would
+ * never be greater than one.
+ */
+ max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
+
+ /* Variables get immediately incremented, so start at -1th iteration */
+ i = -1;
+ f = 0;
+ r = 0;
+ od = 0;
+ best_error = S64_MAX;
+ error = best_error;
+ /* do-while here so we always try at least one ratio */
+ do {
+ /*
+ * Whether we swapped r and od while enforcing frequency limits
+ */
+ bool swapped = false;
+ u64 last_od = od;
+ u64 last_r = r;
+
+ /*
+ * Try the next largest value for f (or r and od) and
+ * recalculate the other parameters based on that
+ */
+ if (rate > rate_in) {
+ /*
+ * Skip factors of the same product if we already tried
+ * out that product
+ */
+ do {
+ i++;
+ r = UNPACK_R(factors[i]);
+ od = UNPACK_OD(factors[i]);
+ } while (i + 1 < ARRAY_SIZE(factors) &&
+ r * od == last_r * last_od);
+
+ /* Round close */
+ f = (r * od * ratio + BIT(31)) >> 32;
+ if (f > 64)
+ f = 64;
+ } else {
+ u64 tmp = ++f * inv_ratio;
+ bool round_up = !!(tmp & BIT(31));
+ u32 goal = (tmp >> 32) + round_up;
+ u32 err, last_err;
+
+ /* Get the next r/od pair in factors */
+ while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
+ i++;
+ r = UNPACK_R(factors[i]);
+ od = UNPACK_OD(factors[i]);
+ }
+
+ /*
+ * This is a case of double rounding. If we rounded up
+ * above, we need to round down (in cases of ties) here.
+ * This prevents off-by-one errors resulting from
+ * choosing X+2 over X when X.Y rounds up to X+1 and
+ * there is no r * od = X+1. For the converse, when X.Y
+ * is rounded down to X, we should choose X+1 over X-1.
+ */
+ err = abs(r * od - goal);
+ last_err = abs(last_r * last_od - goal);
+ if (last_err < err || (round_up && last_err == err)) {
+ i--;
+ r = last_r;
+ od = last_od;
+ }
+ }
+
+ /*
+ * Enforce limits on internal clock frequencies. If we
+ * aren't in spec, try swapping r and od. If everything is
+ * in-spec, calculate the relative error.
+ */
+ while (true) {
+ /*
+ * Whether the intermediate frequencies are out-of-spec
+ */
+ bool out_of_spec = false;
+
+ if (r > max_r) {
+ out_of_spec = true;
+ } else {
+ /*
+ * There is no way to only divide once; we need
+ * to examine the frequency with and without the
+ * effect of od.
+ */
+ u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
+
+ if (vco > 1750000000 || vco < 340000000)
+ out_of_spec = true;
+ }
+
+ if (out_of_spec) {
+ if (!swapped) {
+ u64 tmp = r;
+
+ r = od;
+ od = tmp;
+ swapped = true;
+ continue;
+ } else {
+ /*
+ * Try looking ahead to see if there are
+ * additional factors for the same
+ * product.
+ */
+ if (i + 1 < ARRAY_SIZE(factors)) {
+ u64 new_r, new_od;
+
+ i++;
+ new_r = UNPACK_R(factors[i]);
+ new_od = UNPACK_OD(factors[i]);
+ if (r * od == new_r * new_od) {
+ r = new_r;
+ od = new_od;
+ swapped = false;
+ continue;
+ }
+ i--;
+ }
+ break;
+ }
+ }
+
+ error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
+ /* The lower 16 bits are spurious */
+ error = abs((error - BIT(32))) >> 16;
+
+ if (error < best_error) {
+ best->r = r;
+ best->f = f;
+ best->od = od;
+ best_error = error;
+ }
+ break;
+ }
+ } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
+
+ if (best_error == S64_MAX)
+ return -EINVAL;
+
+ log_debug("best error %lld\n", best_error);
+ return 0;
+}
+
+static ulong k210_pll_set_rate(struct clk *clk, ulong rate)
+{
+ int err;
+ long long rate_in = clk_get_parent_rate(clk);
+ struct k210_pll_config config = {};
+ struct k210_pll *pll = to_k210_pll(clk);
+ u32 reg;
+
+ if (rate_in < 0)
+ return rate_in;
+
+ log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n",
+ rate, rate_in);
+ err = k210_pll_calc_config(rate, rate_in, &config);
+ if (err)
+ return err;
+ log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
+
+ /*
+ * Don't use clk_disable as it might not actually disable the pll due to
+ * refcounting
+ */
+ k210_pll_disable(clk);
+
+ reg = readl(pll->reg);
+ reg &= ~K210_PLL_CLKR
+ & ~K210_PLL_CLKF
+ & ~K210_PLL_CLKOD
+ & ~K210_PLL_BWADJ;
+ reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
+ | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
+ | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
+ | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
+ writel(reg, pll->reg);
+
+ err = k210_pll_enable(clk);
+ if (err)
+ return err;
+
+ serial_setbrg();
+ return clk_get_rate(clk);
+}
+#endif /* CONFIG_CLK_K210_SET_RATE */
+
+static ulong k210_pll_get_rate(struct clk *clk)
+{
+ long long rate_in = clk_get_parent_rate(clk);
+ struct k210_pll *pll = to_k210_pll(clk);
+ u64 r, f, od;
+ u32 reg = readl(pll->reg);
+
+ if (rate_in < 0 || (reg & K210_PLL_BYPASS))
+ return rate_in;
+
+ if (!(reg & K210_PLL_PWRD))
+ return 0;
+
+ r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
+ f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
+ od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
+
+ return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
+}
+
+/*
+ * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
+ * slip before retrying
+ */
+static void k210_pll_waitfor_lock(struct k210_pll *pll)
+{
+ u32 mask = GENMASK(pll->width - 1, 0) << pll->shift;
+
+ while (true) {
+ u32 reg = readl(pll->lock);
+
+ if ((reg & mask) == mask)
+ break;
+
+ reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
+ writel(reg, pll->lock);
+ }
+}
+
+/* Adapted from sysctl_pll_enable */
+static int k210_pll_enable(struct clk *clk)
+{
+ struct k210_pll *pll = to_k210_pll(clk);
+ u32 reg = readl(pll->reg);
+
+ if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET))
+ return 0;
+
+ reg |= K210_PLL_PWRD;
+ writel(reg, pll->reg);
+
+ /* Ensure reset is low before asserting it */
+ reg &= ~K210_PLL_RESET;
+ writel(reg, pll->reg);
+ reg |= K210_PLL_RESET;
+ writel(reg, pll->reg);
+ nop();
+ nop();
+ reg &= ~K210_PLL_RESET;
+ writel(reg, pll->reg);
+
+ k210_pll_waitfor_lock(pll);
+
+ reg &= ~K210_PLL_BYPASS;
+ writel(reg, pll->reg);
+
+ return 0;
+}
+
+static int k210_pll_disable(struct clk *clk)
+{
+ struct k210_pll *pll = to_k210_pll(clk);
+ u32 reg = readl(pll->reg);
+
+ /*
+ * Bypassing before powering off is important so child clocks don't stop
+ * working. This is especially important for pll0, the indirect parent
+ * of the cpu clock.
+ */
+ reg |= K210_PLL_BYPASS;
+ writel(reg, pll->reg);
+
+ reg &= ~K210_PLL_PWRD;
+ writel(reg, pll->reg);
+ return 0;
+}
+
+const struct clk_ops k210_pll_ops = {
+ .get_rate = k210_pll_get_rate,
+#ifdef CONFIG_CLK_K210_SET_RATE
+ .set_rate = k210_pll_set_rate,
+#endif
+ .enable = k210_pll_enable,
+ .disable = k210_pll_disable,
+};
+
+struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
+ struct k210_pll *pll)
+{
+ int ret;
+ struct clk *clk = &pll->clk;
+
+ ret = clk_register(clk, CLK_K210_PLL, name, parent_name);
+ if (ret)
+ return ERR_PTR(ret);
+ return clk;
+}
+
+struct clk *k210_register_pll(const char *name, const char *parent_name,
+ void __iomem *reg, void __iomem *lock, u8 shift,
+ u8 width)
+{
+ struct clk *clk;
+ struct k210_pll *pll;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+ pll->reg = reg;
+ pll->lock = lock;
+ pll->shift = shift;
+ pll->width = width;
+
+ clk = k210_register_pll_struct(name, parent_name, pll);
+ if (IS_ERR(clk))
+ kfree(pll);
+ return clk;
+}
+
+U_BOOT_DRIVER(k210_pll) = {
+ .name = CLK_K210_PLL,
+ .id = UCLASS_CLK,
+ .ops = &k210_pll_ops,
+};
/* Enable UART3 interface clock */
setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
break;
+ case CLK_RMII_REF:
+ case CLK_ETHERNET:
+ setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
+ setbits_le32(priv->base + CMU_ETHERNETPLL, 5);
+ break;
default:
return -EINVAL;
}
/* Disable UART3 interface clock */
clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
break;
+ case CLK_RMII_REF:
+ case CLK_ETHERNET:
+ clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
+ break;
default:
return -EINVAL;
}
#define CMU_DEVCLKEN1_UART5 BIT(21)
#define CMU_DEVCLKEN1_UART3 BIT(11)
-#define CMU_DEVCLKEN1_ETH_S700 BIT(23)
-
#endif
Supports the 'simple-bus' driver, which is used on some systems
in SPL.
+config SIMPLE_PM_BUS
+ bool "Support simple-pm-bus driver"
+ depends on DM && OF_CONTROL && CLK && POWER_DOMAIN
+ help
+ Supports the 'simple-pm-bus' driver, which is used for busses that
+ have power domains and/or clocks which need to be enabled before use.
+
config OF_TRANSLATE
bool "Translate addresses using fdt_translate_address"
depends on DM && OF_CONTROL
obj-$(CONFIG_DEVRES) += devres.o
obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o
obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o
+obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
obj-$(CONFIG_DM) += dump.o
obj-$(CONFIG_$(SPL_TPL_)REGMAP) += regmap.o
obj-$(CONFIG_$(SPL_TPL_)SYSCON) += syscon-uclass.o
}
}
-void dm_dump_drivers(void)
+void dm_dump_driver_compat(void)
{
struct driver *d = ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
printf("%-20.20s %s\n", "", match->compatible);
}
}
+
+void dm_dump_drivers(void)
+{
+ struct driver *d = ll_entry_start(struct driver, driver);
+ const int n_ents = ll_entry_count(struct driver, driver);
+ struct driver *entry;
+ struct udevice *udev;
+ struct uclass *uc;
+ int i;
+
+ puts("Driver uid uclass Devices\n");
+ puts("----------------------------------------------------------\n");
+
+ for (entry = d; entry < d + n_ents; entry++) {
+ uclass_get(entry->id, &uc);
+
+ printf("%-25.25s %-3.3d %-20.20s ", entry->name, entry->id,
+ uc ? uc->uc_drv->name : "<no uclass>");
+
+ if (!uc) {
+ puts("\n");
+ continue;
+ }
+
+ i = 0;
+ uclass_foreach_dev(udev, uc) {
+ if (udev->driver != entry)
+ continue;
+ if (i)
+ printf("%-51.51s", "");
+
+ printf("%-25.25s\n", udev->name);
+ i++;
+ }
+ if (!i)
+ puts("<none>\n");
+ }
+}
+
+void dm_dump_static_driver_info(void)
+{
+ struct driver_info *drv = ll_entry_start(struct driver_info,
+ driver_info);
+ const int n_ents = ll_entry_count(struct driver_info, driver_info);
+ struct driver_info *entry;
+
+ puts("Driver Address\n");
+ puts("---------------------------------\n");
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ printf("%-25.25s @%08lx\n", entry->name,
+ (ulong)map_to_sysmem(entry->platdata));
+ }
+}
{
fdt_addr_t addr = dev_read_addr(dev);
- return (addr == FDT_ADDR_T_NONE) ? NULL : map_sysmem(addr, 0);
+ return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
}
void *dev_remap_addr(const struct udevice *dev)
{
ofnode node = dev_ofnode(dev);
const char *uc_name = dev->uclass->uc_drv->name;
- int ret;
+ int ret = -ENOTSUPP;
if (ofnode_is_np(node)) {
ret = of_alias_get_id(ofnode_to_np(node), uc_name);
if (ret >= 0)
*devnump = ret;
} else {
+#if CONFIG_IS_ENABLED(OF_CONTROL)
ret = fdtdec_get_alias_seq(gd->fdt_blob, uc_name,
ofnode_to_offset(node), devnump);
+#endif
}
return ret;
}
range = &map->ranges[range_num];
- ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
-
if (offset + val_len > range->size) {
debug("%s: offset/size combination invalid\n", __func__);
return -ERANGE;
}
+ ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
+
switch (val_len) {
case REGMAP_SIZE_8:
*((u8 *)valp) = __read_8(ptr, map->endianness);
}
range = &map->ranges[range_num];
- ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
-
if (offset + val_len > range->size) {
debug("%s: offset/size combination invalid\n", __func__);
return -ERANGE;
}
+ ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE);
+
switch (val_len) {
case REGMAP_SIZE_8:
__write_8(ptr, val, map->endianness);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+
+/*
+ * Power domains are taken care of by driver_probe, so we just have to enable
+ * clocks
+ */
+static int simple_pm_bus_probe(struct udevice *dev)
+{
+ int ret;
+ struct clk_bulk *bulk = dev_get_priv(dev);
+
+ ret = clk_get_bulk(dev, bulk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(bulk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ clk_release_bulk(bulk);
+ return ret;
+ }
+ return 0;
+}
+
+static int simple_pm_bus_remove(struct udevice *dev)
+{
+ int ret;
+ struct clk_bulk *bulk = dev_get_priv(dev);
+
+ ret = clk_release_bulk(bulk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+ return ret;
+ else
+ return 0;
+}
+
+static const struct udevice_id simple_pm_bus_ids[] = {
+ { .compatible = "simple-pm-bus" },
+ { }
+};
+
+U_BOOT_DRIVER(simple_pm_bus_drv) = {
+ .name = "simple_pm_bus",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = simple_pm_bus_ids,
+ .probe = simple_pm_bus_probe,
+ .remove = simple_pm_bus_remove,
+ .priv_auto_alloc_size = sizeof(struct clk_bulk),
+ .flags = DM_FLAG_PRE_RELOC,
+};
int uclass_resolve_seq(struct udevice *dev)
{
+ struct uclass *uc = dev->uclass;
+ struct uclass_driver *uc_drv = uc->uc_drv;
struct udevice *dup;
- int seq;
+ int seq = 0;
int ret;
assert(dev->seq == -1);
- ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, dev->req_seq,
- false, &dup);
+ ret = uclass_find_device_by_seq(uc_drv->id, dev->req_seq, false, &dup);
if (!ret) {
dm_warn("Device '%s': seq %d is in use by '%s'\n",
dev->name, dev->req_seq, dup->name);
return ret;
}
- for (seq = 0; seq < DM_MAX_SEQ; seq++) {
- ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, seq,
- false, &dup);
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS) &&
+ (uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS)) {
+ /*
+ * dev_read_alias_highest_id() will return -1 if there no
+ * alias. Thus we can always add one.
+ */
+ seq = dev_read_alias_highest_id(uc_drv->name) + 1;
+ }
+
+ for (; seq < DM_MAX_SEQ; seq++) {
+ ret = uclass_find_device_by_seq(uc_drv->id, seq, false, &dup);
if (ret == -ENODEV)
break;
if (ret)
if (!ops->get_info)
return -ENOSYS;
+ /* Init cpu_info to 0 */
+ memset(info, 0, sizeof(struct cpu_info));
+
return ops->get_info(dev, info);
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
*/
+#include <clk.h>
#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <linux/bitops.h>
+#include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR;
static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
{
+ int ret;
+ struct clk clk;
const char *mmu;
+ u32 i_cache_size;
+ u32 d_cache_size;
+
+ /* First try getting the frequency from the assigned clock */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret) {
+ ret = clk_get_rate(&clk);
+ if (!IS_ERR_VALUE(ret))
+ info->cpu_freq = ret;
+ clk_free(&clk);
+ }
- dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
+ if (!info->cpu_freq)
+ dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
mmu = dev_read_string(dev, "mmu-type");
- if (!mmu)
+ if (mmu)
info->features |= BIT(CPU_FEAT_MMU);
+ /* check if I cache is present */
+ ret = dev_read_u32(dev, "i-cache-size", &i_cache_size);
+ if (ret)
+ /* if not found check if d-cache is present */
+ ret = dev_read_u32(dev, "d-cache-size", &d_cache_size);
+
+ /* if either I or D cache is present set L1 cache feature */
+ if (!ret)
+ info->features |= BIT(CPU_FEAT_L1_CACHE);
+
return 0;
}
return 0;
}
+static int riscv_cpu_probe(struct udevice *dev)
+{
+ int ret = 0;
+ struct clk clk;
+
+ /* Get a clock if it exists */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return 0;
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret == -ENOSYS || ret == -ENOTSUPP)
+ return 0;
+ else
+ return ret;
+}
+
static const struct cpu_ops riscv_cpu_ops = {
.get_desc = riscv_cpu_get_desc,
.get_info = riscv_cpu_get_info,
.id = UCLASS_CPU,
.of_match = riscv_cpu_ids,
.bind = riscv_cpu_bind,
+ .probe = riscv_cpu_probe,
.ops = &riscv_cpu_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#define PMUFW_PAYLOAD_ARG_CNT 8
+#define XST_PM_NO_ACCESS 2002L
+
struct zynqmp_power {
struct mbox_chan tx_chan;
struct mbox_chan rx_chan;
PM_SET_CONFIGURATION,
(u32)((u64)cfg_obj)
};
- u32 response;
+ u32 response = 0;
int err;
printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
err = send_req(request, ARRAY_SIZE(request), &response, 1);
+ if (err == XST_PM_NO_ACCESS) {
+ printf("PMUFW no permission to change config object\n");
+ return;
+ }
+
if (err)
- panic("Cannot load PMUFW configuration object (%d)\n", err);
- if (response != 0)
- panic("PMUFW returned 0x%08x status!\n", response);
+ printf("Cannot load PMUFW configuration object (%d)\n", err);
+
+ if (response)
+ printf("PMUFW returned 0x%08x status!\n", response);
+
+ if ((err || response) && IS_ENABLED(CONFIG_SPL_BUILD))
+ panic("PMUFW config object loading failed in EL3\n");
}
static int zynqmp_power_probe(struct udevice *dev)
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
buf_hi, 0, ret_payload);
if (ret)
- puts("PL FPGA LOAD fail\n");
+ printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
return ret;
}
buf_hi, (u32)bsize, 0, ret_payload);
if (ret)
- puts("PL FPGA LOAD fail\n");
+ printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
return ret;
}
#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
#define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
+#define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
- if (bstype != BIT_PARTIAL) {
+ if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
zynq_slcr_devcfg_disable();
/* Setting PCFG_PROG_B signal to high */
* Load the encrypted image from src addr and decrypt the image and
* place it back the decrypted image into dstaddr.
*/
-int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
+int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
+ u8 bstype)
{
+ u32 isr_status, ts;
+
if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
printf("%s: src and dst addr should be > 1M\n",
__func__);
return FPGA_FAIL;
}
- if (zynq_dma_xfer_init(BIT_NONE)) {
+ /* Check AES engine is enabled */
+ if (!(readl(&devcfg_base->ctrl) &
+ DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
+ printf("%s: AES engine is not enabled\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ if (zynq_dma_xfer_init(bstype)) {
printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
return FPGA_FAIL;
}
* Flush destination address range only if image is not
* bitstream.
*/
- flush_dcache_range((u32)dstaddr, (u32)dstaddr +
- roundup(dstlen << 2, ARCH_DMA_MINALIGN));
+ if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
+ flush_dcache_range((u32)dstaddr, (u32)dstaddr +
+ roundup(dstlen << 2, ARCH_DMA_MINALIGN));
if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
return FPGA_FAIL;
- writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
- &devcfg_base->ctrl);
+ if (bstype == BIT_FULL) {
+ isr_status = readl(&devcfg_base->int_sts);
+ /* Check FPGA configuration completion */
+ ts = get_timer(0);
+ while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ printf("%s: Timeout wait for FPGA to config\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(&devcfg_base->int_sts);
+ }
+ printf("%s: FPGA config done\n", __func__);
+ zynq_slcr_devcfg_enable();
+ }
return FPGA_SUCCESS;
}
is a mechanism providing automatic GPIO request and config-
uration as part of the gpio-controller's driver probe function.
+config DM_GPIO_LOOKUP_LABEL
+ bool "Enable searching for gpio labelnames"
+ depends on DM_GPIO
+ help
+ This option enables searching for gpio names in
+ the defined gpio labels, if the search for the
+ gpio bank name failed. This makes sense if you use
+ different gpios on different hardware versions
+ for the same functionality in board code.
+
+config SPL_DM_GPIO_LOOKUP_LABEL
+ bool "Enable searching for gpio labelnames"
+ depends on DM_GPIO && SPL_DM && SPL_GPIO_SUPPORT
+ help
+ This option enables searching for gpio names in
+ the defined gpio labels, if the search for the
+ gpio bank name failed. This makes sense if you use
+ different gpios on different hardware versions
+ for the same functionality in board code.
+
config ALTERA_PIO
bool "Altera PIO driver"
depends on DM_GPIO
config AT91_GPIO
bool "AT91 PIO GPIO driver"
- depends on DM_GPIO
default n
help
Say yes here to select AT91 PIO GPIO driver. AT91 PIO
return ret ? ret : -ENOENT;
}
+#if CONFIG_IS_ENABLED(DM_GPIO_LOOKUP_LABEL)
+/**
+ * dm_gpio_lookup_label() - look for name in gpio device
+ *
+ * search in uc_priv, if there is a gpio with labelname same
+ * as name.
+ *
+ * @name: name which is searched
+ * @uc_priv: gpio_dev_priv pointer.
+ * @offset: gpio offset within the device
+ * @return: 0 if found, -ENOENT if not.
+ */
+static int dm_gpio_lookup_label(const char *name,
+ struct gpio_dev_priv *uc_priv, ulong *offset)
+{
+ int len;
+ int i;
+
+ *offset = -1;
+ len = strlen(name);
+ for (i = 0; i < uc_priv->gpio_count; i++) {
+ if (!uc_priv->name[i])
+ continue;
+ if (!strncmp(name, uc_priv->name[i], len)) {
+ *offset = i;
+ return 0;
+ }
+ }
+ return -ENOENT;
+}
+#else
+static int
+dm_gpio_lookup_label(const char *name, struct gpio_dev_priv *uc_priv,
+ ulong *offset)
+{
+ return -ENOENT;
+}
+#endif
+
int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc)
{
struct gpio_dev_priv *uc_priv = NULL;
if (!strict_strtoul(name + len, 10, &offset))
break;
}
+
+ /*
+ * if we did not found a gpio through its bank
+ * name, we search for a valid gpio label.
+ */
+ if (!dm_gpio_lookup_label(name, uc_priv, &offset))
+ break;
}
if (!dev)
#endif
-static inline int get_gpio_index(int gpio)
-{
- return gpio & 0x1f;
-}
-
int gpio_is_valid(int gpio)
{
return (gpio >= 0) && (gpio < OMAP_MAX_GPIO);
}
#if !CONFIG_IS_ENABLED(DM_GPIO)
+static inline int get_gpio_index(int gpio)
+{
+ return gpio & 0x1f;
+}
static inline const struct gpio_bank *get_gpio_bank(int gpio)
{
#include <linux/errno.h>
#include <linux/io.h>
-#define MODE_BITS(gpio_pin) (gpio_pin * 2)
+#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
#define MODE_BITS_MASK 3
-#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
+#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
+
+#define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
+#define PUPD_MASK 3
+
+#define OTYPE_BITS(gpio_pin) (gpio_pin)
+#define OTYPE_MSK 1
+
+static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
+ int idx,
+ int mode)
+{
+ int bits_index;
+ int mask;
+
+ bits_index = MODE_BITS(idx);
+ mask = MODE_BITS_MASK << bits_index;
+
+ clrsetbits_le32(®s->moder, mask, mode << bits_index);
+}
+
+static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
+{
+ return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
+}
+
+static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
+ int idx,
+ enum stm32_gpio_otype otype)
+{
+ int bits;
+
+ bits = OTYPE_BITS(idx);
+ clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
+}
+
+static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
+ int idx)
+{
+ return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
+}
+
+static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
+ int idx,
+ enum stm32_gpio_pupd pupd)
+{
+ int bits;
+
+ bits = PUPD_BITS(idx);
+ clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
+}
+
+static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
+ int idx)
+{
+ return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
+}
/*
* convert gpio offset to gpio index taking into account gpio holes
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
- int bits_index;
- int mask;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
- bits_index = MODE_BITS(idx);
- mask = MODE_BITS_MASK << bits_index;
-
- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
return 0;
}
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
- int bits_index;
- int mask;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
- bits_index = MODE_BITS(idx);
- mask = MODE_BITS_MASK << bits_index;
-
- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
writel(BSRR_BIT(idx, value), ®s->bsrr);
return GPIOF_FUNC;
}
+static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
+ ulong flags)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int idx;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ if (flags & GPIOD_IS_OUT) {
+ int value = GPIOD_FLAGS_OUTPUT(flags);
+
+ if (flags & GPIOD_OPEN_DRAIN)
+ stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
+ else
+ stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
+ writel(BSRR_BIT(idx, value), ®s->bsrr);
+
+ } else if (flags & GPIOD_IS_IN) {
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
+ if (flags & GPIOD_PULL_UP)
+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
+ else if (flags & GPIOD_PULL_DOWN)
+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
+ }
+
+ return 0;
+}
+
+static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
+ ulong *flags)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int idx;
+ ulong dir_flags = 0;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ switch (stm32_gpio_get_moder(regs, idx)) {
+ case STM32_GPIO_MODE_OUT:
+ dir_flags |= GPIOD_IS_OUT;
+ if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
+ dir_flags |= GPIOD_OPEN_DRAIN;
+ if (readl(®s->idr) & BIT(idx))
+ dir_flags |= GPIOD_IS_OUT_ACTIVE;
+ break;
+ case STM32_GPIO_MODE_IN:
+ dir_flags |= GPIOD_IS_IN;
+ switch (stm32_gpio_get_pupd(regs, idx)) {
+ case STM32_GPIO_PUPD_UP:
+ dir_flags |= GPIOD_PULL_UP;
+ break;
+ case STM32_GPIO_PUPD_DOWN:
+ dir_flags |= GPIOD_PULL_DOWN;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ *flags = dir_flags;
+
+ return 0;
+}
+
static const struct dm_gpio_ops gpio_stm32_ops = {
.direction_input = stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.get_value = stm32_gpio_get_value,
.set_value = stm32_gpio_set_value,
.get_function = stm32_gpio_get_function,
+ .set_dir_flags = stm32_gpio_set_dir_flags,
+ .get_dir_flags = stm32_gpio_get_dir_flags,
};
static int gpio_stm32_probe(struct udevice *dev)
config ARM_PL180_MMCI
bool "ARM AMBA Multimedia Card Interface and compatible support"
- depends on DM_MMC && OF_CONTROL
help
This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card
Interface (PL180, PL181 and compatible) support.
If unsure, say N.
+config PXA_MMC_GENERIC
+ bool "Support for MMC controllers on PXA"
+ help
+ This selects MMC controllers on PXA.
+ If you are on a PXA architecture, say Y here.
+
+ If unsure, say N.
+
config MMC_OMAP_HS
bool "TI OMAP High Speed Multimedia Card Interface support"
select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR
#include <asm-generic/gpio.h>
#include <linux/delay.h>
-#define DAVINCI_MAX_BLOCKS (32)
#define WATCHDOG_COUNT (100000)
#define get_val(addr) REG(addr)
struct gpio_desc cd_gpio; /* Card Detect GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
};
-
-struct davinci_mmc_plat
-{
- struct mmc_config cfg;
- struct mmc mmc;
-};
#endif
/* Set davinci clock prescalar value based on the required clock in HZ */
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct davinci_mmc_plat *plat = dev_get_platdata(dev);
struct davinci_mmc_priv *priv = dev_get_priv(dev);
- struct mmc_config *cfg = &plat->cfg;
-#ifdef CONFIG_SPL_BUILD
- int ret;
-#endif
-
- cfg->f_min = 200000;
- cfg->f_max = 25000000;
- cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
- cfg->b_max = DAVINCI_MAX_BLOCKS;
- cfg->name = "da830-mmc";
- priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
+ priv->reg_base = plat->reg_base;
priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
-
#if CONFIG_IS_ENABLED(DM_GPIO)
/* These GPIOs are optional */
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
-
upriv->mmc = &plat->mmc;
-#ifdef CONFIG_SPL_BUILD
- /*
- * FIXME This is a temporary workaround to enable the driver model in
- * SPL on omapl138-lcdk. For some reason the bind() callback is not
- * being called in SPL for MMC which breaks the mmc boot - the hack
- * is to call mmc_bind() from probe(). We also don't have full DT
- * support in SPL, hence the hard-coded base register address.
- */
- priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
- ret = mmc_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-#endif
-
return davinci_dm_mmc_init(dev);
}
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int davinci_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg = &plat->cfg;
+
+ plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
+ cfg->f_min = 200000;
+ cfg->f_max = 25000000;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
+ cfg->b_max = DAVINCI_MAX_BLOCKS;
+ cfg->name = "da830-mmc";
+
+ return 0;
+}
+
static const struct udevice_id davinci_mmc_ids[] = {
{ .compatible = "ti,da830-mmc" },
{},
};
-
+#endif
U_BOOT_DRIVER(davinci_mmc_drv) = {
.name = "davinci_mmc",
.id = UCLASS_MMC,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = davinci_mmc_ids,
+ .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
+ .ofdata_to_platdata = davinci_mmc_ofdata_to_platdata,
+#endif
#if CONFIG_BLK
.bind = davinci_mmc_bind,
#endif
.probe = davinci_mmc_probe,
.ops = &davinci_mmc_ops,
- .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+ .flags = DM_FLAG_PRE_RELOC,
+#endif
};
#endif
if (err)
return err;
- /* The internal partition reset to user partition(0) at every CMD0*/
+ /* The internal partition reset to user partition(0) at every CMD0 */
mmc_get_blk_desc(mmc)->hwpart = 0;
/* Test for SD version 2 */
return (struct omap_hsmmc_data *)mmc->priv;
#endif
}
+
+#if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
{
#if CONFIG_IS_ENABLED(DM_MMC)
return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
#endif
}
+#endif
#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
static int omap_mmc_setup_gpio_in(int gpio, const char *label)
/*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
+ * Modified to add driver model (DM) support
+ * Copyright (C) 2019 Marcel Ziswiler <marcel@ziswiler.com>
+ *
* Loosely based on the old code and Linux's PXA MMC driver
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/pxa_mmc_gen.h>
#include <malloc.h>
#include <mmc.h>
}
static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- uint32_t cmdat)
+ uint32_t cmdat)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
- uint32_t a, b, c;
+ u32 a, b, c;
int i;
int stat;
/*
* Linux says:
- * Did I mention this is Sick. We always need to
+ * Did I mention this is Sick. We always need to
* discard the upper 8 bits of the first 16-bit word.
*/
a = readl(®s->res) & 0xffff;
}
/* The command response didn't arrive */
- if (stat & MMC_STAT_TIME_OUT_RESPONSE)
+ if (stat & MMC_STAT_TIME_OUT_RESPONSE) {
return -ETIMEDOUT;
- else if (stat & MMC_STAT_RES_CRC_ERROR
- && cmd->resp_type & MMC_RSP_CRC) {
-#ifdef PXAMMC_CRC_SKIP
- if (cmd->resp_type & MMC_RSP_136
- && cmd->response[0] & (1 << 31))
+ } else if (stat & MMC_STAT_RES_CRC_ERROR &&
+ cmd->resp_type & MMC_RSP_CRC) {
+#ifdef PXAMMC_CRC_SKIP
+ if (cmd->resp_type & MMC_RSP_136 &&
+ cmd->response[0] & (1 << 31))
printf("Ignoring CRC, this may be dangerous!\n");
else
#endif
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
- uint32_t len;
- uint32_t *buf = (uint32_t *)data->dest;
+ u32 len;
+ u32 *buf = (uint32_t *)data->dest;
int size;
int ret;
/* Read data into the buffer */
while (size--)
*buf++ = readl(®s->rxfifo);
-
}
if (readl(®s->stat) & MMC_STAT_ERRORS)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
- uint32_t len;
- uint32_t *buf = (uint32_t *)data->src;
+ u32 len;
+ u32 *buf = (uint32_t *)data->src;
int size;
int ret;
return 0;
}
-static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static int pxa_mmc_send_cmd_common(struct pxa_mmc_priv *priv, struct mmc *mmc,
+ struct mmc_cmd *cmd, struct mmc_data *data)
{
- struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
- uint32_t cmdat = 0;
+ u32 cmdat = 0;
int ret;
/* Stop the controller */
return 0;
}
-static int pxa_mmc_set_ios(struct mmc *mmc)
+static int pxa_mmc_set_ios_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
{
- struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
- uint32_t tmp;
- uint32_t pxa_mmc_clock;
+ u32 tmp;
+ u32 pxa_mmc_clock;
if (!mmc->clock) {
pxa_mmc_stop_clock(mmc);
return 0;
}
-static int pxa_mmc_init(struct mmc *mmc)
+static int pxa_mmc_init_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
{
- struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
/* Make sure the clock are stopped */
/* Mask all interrupts */
writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
- ®s->i_mask);
+ ®s->i_mask);
+
return 0;
}
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int pxa_mmc_init(struct mmc *mmc)
+{
+ struct pxa_mmc_priv *priv = mmc->priv;
+
+ return pxa_mmc_init_common(priv, mmc);
+}
+
+static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct pxa_mmc_priv *priv = mmc->priv;
+
+ return pxa_mmc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int pxa_mmc_set_ios(struct mmc *mmc)
+{
+ struct pxa_mmc_priv *priv = mmc->priv;
+
+ return pxa_mmc_set_ios_common(priv, mmc);
+}
+
static const struct mmc_ops pxa_mmc_ops = {
.send_cmd = pxa_mmc_request,
.set_ios = pxa_mmc_set_ios,
{
struct mmc *mmc;
struct pxa_mmc_priv *priv;
- uint32_t reg;
+ u32 reg;
int ret = -ENOMEM;
priv = malloc(sizeof(struct pxa_mmc_priv));
default:
ret = -EINVAL;
printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
- card_index);
+ card_index);
goto err1;
}
#endif
mmc = mmc_create(&pxa_mmc_cfg, priv);
- if (mmc == NULL)
+ if (!mmc)
goto err1;
return 0;
err0:
return ret;
}
+#else /* !CONFIG_IS_ENABLED(DM_MMC) */
+static int pxa_mmc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg = &plat->cfg;
+ struct mmc *mmc = &plat->mmc;
+ struct pxa_mmc_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ upriv->mmc = mmc;
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ cfg->f_max = PXAMMC_MAX_SPEED;
+ cfg->f_min = PXAMMC_MIN_SPEED;
+ cfg->host_caps = PXAMMC_HOST_CAPS;
+ cfg->name = dev->name;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->priv = priv;
+
+ priv->regs = plat->base;
+
+#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
+ reg = readl(CKEN);
+ reg |= CKEN12_MMC;
+ writel(reg, CKEN);
+#else /* PXA3xx */
+ reg = readl(CKENA);
+ reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
+ writel(reg, CKENA);
+#endif
+
+ return pxa_mmc_init_common(priv, mmc);
+}
+
+static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+ struct pxa_mmc_priv *priv = dev_get_priv(dev);
+
+ return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
+}
+
+static int pxa_mmc_set_ios(struct udevice *dev)
+{
+ struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+ struct pxa_mmc_priv *priv = dev_get_priv(dev);
+
+ return pxa_mmc_set_ios_common(priv, &plat->mmc);
+}
+
+static const struct dm_mmc_ops pxa_mmc_ops = {
+ .get_cd = NULL,
+ .send_cmd = pxa_mmc_send_cmd,
+ .set_ios = pxa_mmc_set_ios,
+};
+
+#if CONFIG_IS_ENABLED(BLK)
+static int pxa_mmc_bind(struct udevice *dev)
+{
+ struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+#endif
+
+U_BOOT_DRIVER(pxa_mmc) = {
+#if CONFIG_IS_ENABLED(BLK)
+ .bind = pxa_mmc_bind,
+#endif
+ .id = UCLASS_MMC,
+ .name = "pxa_mmc",
+ .ops = &pxa_mmc_ops,
+ .priv_auto_alloc_size = sizeof(struct pxa_mmc_priv),
+ .probe = pxa_mmc_probe,
+};
+#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
#include <sdhci.h>
#include <zynqmp_tap_delay.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct arasan_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)DM_SPI_FLASH) += sf-uclass.o
spi-nor-y := sf_probe.o spi-nor-ids.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPI_FLASH) += spi-nor.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
-obj-$(CONFIG_$(SPL_)SPI_FLASH_MTD) += sf_mtd.o
+obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
return ret;
}
-#ifndef CONFIG_DM_SPI_FLASH
+#if !CONFIG_IS_ENABLED(DM_SPI_FLASH)
struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
used on devices with SPI support you can reprogram the EEPROM from
U-Boot.
+config EEPRO100
+ bool "Intel PRO/100 82557/82559/82559ER Fast Ethernet support"
+ help
+ This driver supports Intel(R) PRO/100 82557/82559/82559ER fast
+ ethernet family of adapters.
+
config ETH_SANDBOX
depends on DM_ETH && SANDBOX
default y
Altera system manager to correctly interface with the PHY.
This code handles those SoC specifics.
+config ETH_DESIGNWARE_S700
+ bool "Actins S700 glue driver for Synopsys Designware Ethernet MAC"
+ depends on DM_ETH && ETH_DESIGNWARE
+ help
+ This provides glue layer to use Synopsys Designware Ethernet MAC
+ present on Actions S700 SoC.
+
config ETHOC
bool "OpenCores 10/100 Mbps Ethernet MAC"
help
help
Enable support of the Media-Independent Interface (MII)
+config PCNET
+ bool "AMD PCnet series Ethernet controller driver"
+ help
+ This driver supports AMD PCnet series fast ethernet family of
+ PCI chipsets/adapters.
+
config RTL8139
bool "Realtek 8139 series Ethernet controller driver"
help
obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
+obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
.data = (ulong)&eqos_tegra186_config
},
{
- .compatible = "snps,dwmac-4.20a",
+ .compatible = "st,stm32mp1-dwmac",
.data = (ulong)&eqos_stm32_config
},
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
+ *
+ * Actions DWMAC specific glue layer
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <clk.h>
+#include <phy.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include "designware.h"
+#include <asm/arch-owl/regs_s700.h>
+#include <linux/bitops.h>
+
+/* pin control for MAC */
+#define RMII_TXD01_MFP_CTL0 (0x0 << 16)
+#define RMII_RXD01_MFP_CTL0 (0x0 << 8)
+#define RMII_TXEN_TXER_MFP_CTL0 (0x0 << 13)
+#define RMII_REF_CLK_MFP_CTL0 (0x0 << 6)
+#define CLKO_25M_EN_MFP_CTL3 BIT(30)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void dwmac_board_setup(void)
+{
+ clrbits_le32(MFP_CTL0, (RMII_TXD01_MFP_CTL0 | RMII_RXD01_MFP_CTL0 |
+ RMII_TXEN_TXER_MFP_CTL0 | RMII_REF_CLK_MFP_CTL0));
+
+ setbits_le32(MFP_CTL3, CLKO_25M_EN_MFP_CTL3);
+}
+
+static int dwmac_s700_probe(struct udevice *dev)
+{
+ dwmac_board_setup();
+
+ /* This is undocumented, phy interface select register */
+ writel(0x4, 0xe024c0a0);
+
+ return designware_eth_probe(dev);
+}
+
+static int dwmac_s700_ofdata_to_platdata(struct udevice *dev)
+{
+ return designware_eth_ofdata_to_platdata(dev);
+}
+
+static const struct udevice_id dwmac_s700_ids[] = {
+ {.compatible = "actions,s700-ethernet"},
+ { }
+};
+
+U_BOOT_DRIVER(dwmac_s700) = {
+ .name = "dwmac_s700",
+ .id = UCLASS_ETH,
+ .of_match = dwmac_s700_ids,
+ .ofdata_to_platdata = dwmac_s700_ofdata_to_platdata,
+ .probe = dwmac_s700_probe,
+ .ops = &designware_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
*/
#include <common.h>
+#include <asm/io.h>
+#include <cpu_func.h>
#include <malloc.h>
+#include <miiphy.h>
#include <net.h>
#include <netdev.h>
-#include <asm/io.h>
#include <pci.h>
-#include <miiphy.h>
#include <linux/delay.h>
-#undef DEBUG
-
- /* Ethernet chip registers.
- */
-#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
-#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
-#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
-#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
-#define SCBPointer 4 /* General purpose pointer. */
-#define SCBPort 8 /* Misc. commands and operands. */
-#define SCBflash 12 /* Flash memory control. */
-#define SCBeeprom 14 /* EEPROM memory control. */
-#define SCBCtrlMDI 16 /* MDI interface control. */
-#define SCBEarlyRx 20 /* Early receive byte count. */
-#define SCBGenControl 28 /* 82559 General Control Register */
-#define SCBGenStatus 29 /* 82559 General Status register */
-
- /* 82559 SCB status word defnitions
- */
+/* Ethernet chip registers. */
+#define SCB_STATUS 0 /* Rx/Command Unit Status *Word* */
+#define SCB_INT_ACK_BYTE 1 /* Rx/Command Unit STAT/ACK byte */
+#define SCB_CMD 2 /* Rx/Command Unit Command *Word* */
+#define SCB_INTR_CTL_BYTE 3 /* Rx/Command Unit Intr.Control Byte */
+#define SCB_POINTER 4 /* General purpose pointer. */
+#define SCB_PORT 8 /* Misc. commands and operands. */
+#define SCB_FLASH 12 /* Flash memory control. */
+#define SCB_EEPROM 14 /* EEPROM memory control. */
+#define SCB_CTRL_MDI 16 /* MDI interface control. */
+#define SCB_EARLY_RX 20 /* Early receive byte count. */
+#define SCB_GEN_CONTROL 28 /* 82559 General Control Register */
+#define SCB_GEN_STATUS 29 /* 82559 General Status register */
+
+/* 82559 SCB status word defnitions */
#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
#define SCB_STATUS_FR 0x4000 /* frame received */
#define SCB_STATUS_CNA 0x2000 /* CU left active state */
#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
- /* System control block commands
- */
+/* System control block commands */
/* CU Commands */
#define CU_NOP 0x0000
#define CU_START 0x0010
#define CU_STATUS_MASK 0x00C0
#define RU_STATUS_MASK 0x003C
-#define RU_STATUS_IDLE (0<<2)
-#define RU_STATUS_SUS (1<<2)
-#define RU_STATUS_NORES (2<<2)
-#define RU_STATUS_READY (4<<2)
-#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
-#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
-#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
+#define RU_STATUS_IDLE (0 << 2)
+#define RU_STATUS_SUS (1 << 2)
+#define RU_STATUS_NORES (2 << 2)
+#define RU_STATUS_READY (4 << 2)
+#define RU_STATUS_NO_RBDS_SUS ((1 << 2) | (8 << 2))
+#define RU_STATUS_NO_RBDS_NORES ((2 << 2) | (8 << 2))
+#define RU_STATUS_NO_RBDS_READY ((4 << 2) | (8 << 2))
- /* 82559 Port interface commands.
- */
+/* 82559 Port interface commands. */
#define I82559_RESET 0x00000000 /* Software reset */
#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
#define I82559_SELECTIVE_RESET 0x00000002
#define I82559_DUMP 0x00000003
#define I82559_DUMP_WAKEUP 0x00000007
- /* 82559 Eeprom interface.
- */
+/* 82559 Eeprom interface. */
#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
#define EE_CS 0x02 /* EEPROM chip select. */
#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
#define EE_CMD_BITS 3
#define EE_DATA_BITS 16
- /* The EEPROM commands include the alway-set leading bit.
- */
-#define EE_EWENB_CMD (4 << addr_len)
-#define EE_WRITE_CMD (5 << addr_len)
-#define EE_READ_CMD (6 << addr_len)
-#define EE_ERASE_CMD (7 << addr_len)
-
- /* Receive frame descriptors.
- */
-struct RxFD {
- volatile u16 status;
- volatile u16 control;
- volatile u32 link; /* struct RxFD * */
- volatile u32 rx_buf_addr; /* void * */
- volatile u32 count;
-
- volatile u8 data[PKTSIZE_ALIGN];
+/* The EEPROM commands include the alway-set leading bit. */
+#define EE_EWENB_CMD(addr_len) (4 << (addr_len))
+#define EE_WRITE_CMD(addr_len) (5 << (addr_len))
+#define EE_READ_CMD(addr_len) (6 << (addr_len))
+#define EE_ERASE_CMD(addr_len) (7 << (addr_len))
+
+/* Receive frame descriptors. */
+struct eepro100_rxfd {
+ u16 status;
+ u16 control;
+ u32 link; /* struct eepro100_rxfd * */
+ u32 rx_buf_addr; /* void * */
+ u32 count;
+
+ u8 data[PKTSIZE_ALIGN];
};
#define RFD_STATUS_C 0x8000 /* completion of received frame */
#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
#define RFD_RX_TCO 0x0001 /* TCO indication */
- /* Transmit frame descriptors
- */
-struct TxFD { /* Transmit frame descriptor set. */
- volatile u16 status;
- volatile u16 command;
- volatile u32 link; /* void * */
- volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
- volatile s32 count;
-
- volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
- volatile s32 tx_buf_size0; /* Length of Tx frame. */
- volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
- volatile s32 tx_buf_size1; /* Length of Tx frame. */
+/* Transmit frame descriptors */
+struct eepro100_txfd { /* Transmit frame descriptor set. */
+ u16 status;
+ u16 command;
+ u32 link; /* void * */
+ u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
+ s32 count;
+
+ u32 tx_buf_addr0; /* void *, frame to be transmitted. */
+ s32 tx_buf_size0; /* Length of Tx frame. */
+ u32 tx_buf_addr1; /* void *, frame to be transmitted. */
+ s32 tx_buf_size1; /* Length of Tx frame. */
};
-#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
-#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
-#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
-#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
-#define TxCB_CMD_S 0x4000 /* suspend on completion */
-#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
+#define TXCB_CMD_TRANSMIT 0x0004 /* transmit command */
+#define TXCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
+#define TXCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
+#define TXCB_CMD_I 0x2000 /* generate interrupt on completion */
+#define TXCB_CMD_S 0x4000 /* suspend on completion */
+#define TXCB_CMD_EL 0x8000 /* last command block in CBL */
-#define TxCB_COUNT_MASK 0x3fff
-#define TxCB_COUNT_EOF 0x8000
+#define TXCB_COUNT_MASK 0x3fff
+#define TXCB_COUNT_EOF 0x8000
- /* The Speedo3 Rx and Tx frame/buffer descriptors.
- */
-struct descriptor { /* A generic descriptor. */
- volatile u16 status;
- volatile u16 command;
- volatile u32 link; /* struct descriptor * */
+/* The Speedo3 Rx and Tx frame/buffer descriptors. */
+struct descriptor { /* A generic descriptor. */
+ u16 status;
+ u16 command;
+ u32 link; /* struct descriptor * */
unsigned char params[0];
};
#define CONFIG_SYS_STATUS_C 0x8000
#define CONFIG_SYS_STATUS_OK 0x2000
- /* Misc.
- */
+/* Misc. */
#define NUM_RX_DESC PKTBUFSRX
-#define NUM_TX_DESC 1 /* Number of TX descriptors */
+#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define TOUT_LOOP 1000000
-static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
-static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
-static int rx_next; /* RX descriptor ring pointer */
-static int tx_next; /* TX descriptor ring pointer */
-static int tx_threshold;
-
/*
* The parameters for a CmdConfigure operation.
* There are so many options that it would be difficult to document
0x31, 0x05,
};
-static void init_rx_ring (struct eth_device *dev);
-static void purge_tx_ring (struct eth_device *dev);
-
-static void read_hw_addr (struct eth_device *dev, bd_t * bis);
-
-static int eepro100_init (struct eth_device *dev, bd_t * bis);
-static int eepro100_send(struct eth_device *dev, void *packet, int length);
-static int eepro100_recv (struct eth_device *dev);
-static void eepro100_halt (struct eth_device *dev);
+struct eepro100_priv {
+ /* RX descriptor ring */
+ struct eepro100_rxfd rx_ring[NUM_RX_DESC];
+ /* TX descriptor ring */
+ struct eepro100_txfd tx_ring[NUM_TX_DESC];
+ /* RX descriptor ring pointer */
+ int rx_next;
+ u16 rx_stat;
+ /* TX descriptor ring pointer */
+ int tx_next;
+ int tx_threshold;
+#ifdef CONFIG_DM_ETH
+ struct udevice *devno;
+#else
+ struct eth_device dev;
+ pci_dev_t devno;
+#endif
+ char *name;
+ void __iomem *iobase;
+ u8 *enetaddr;
+};
-#if defined(CONFIG_E500)
-#define bus_to_phys(a) (a)
-#define phys_to_bus(a) (a)
+#if defined(CONFIG_DM_ETH)
+#define bus_to_phys(dev, a) dm_pci_mem_to_phys((dev), (a))
+#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
+#elif defined(CONFIG_E500)
+#define bus_to_phys(dev, a) (a)
+#define phys_to_bus(dev, a) (a)
#else
-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+#define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a))
+#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
#endif
-static inline int INW (struct eth_device *dev, u_long addr)
+static int INW(struct eepro100_priv *priv, u_long addr)
{
- return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
+ return le16_to_cpu(readw(addr + priv->iobase));
}
-static inline void OUTW (struct eth_device *dev, int command, u_long addr)
+static void OUTW(struct eepro100_priv *priv, int command, u_long addr)
{
- *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
+ writew(cpu_to_le16(command), addr + priv->iobase);
}
-static inline void OUTL (struct eth_device *dev, int command, u_long addr)
+static void OUTL(struct eepro100_priv *priv, int command, u_long addr)
{
- *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
+ writel(cpu_to_le32(command), addr + priv->iobase);
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-static inline int INL (struct eth_device *dev, u_long addr)
+static int INL(struct eepro100_priv *priv, u_long addr)
{
- return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
+ return le32_to_cpu(readl(addr + priv->iobase));
}
-static int get_phyreg (struct eth_device *dev, unsigned char addr,
- unsigned char reg, unsigned short *value)
+static int get_phyreg(struct eepro100_priv *priv, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
- int cmd;
int timeout = 50;
+ int cmd;
/* read requested data */
cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
- OUTL (dev, cmd, SCBCtrlMDI);
+ OUTL(priv, cmd, SCB_CTRL_MDI);
do {
udelay(1000);
- cmd = INL (dev, SCBCtrlMDI);
+ cmd = INL(priv, SCB_CTRL_MDI);
} while (!(cmd & (1 << 28)) && (--timeout));
if (timeout == 0)
return -1;
- *value = (unsigned short) (cmd & 0xffff);
+ *value = (unsigned short)(cmd & 0xffff);
return 0;
}
-static int set_phyreg (struct eth_device *dev, unsigned char addr,
- unsigned char reg, unsigned short value)
+static int set_phyreg(struct eepro100_priv *priv, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
- int cmd;
int timeout = 50;
+ int cmd;
/* write requested data */
cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
- OUTL (dev, cmd | value, SCBCtrlMDI);
+ OUTL(priv, cmd | value, SCB_CTRL_MDI);
- while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
+ while (!(INL(priv, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
udelay(1000);
if (timeout == 0)
return 0;
}
-/* Check if given phyaddr is valid, i.e. there is a PHY connected.
+/*
+ * Check if given phyaddr is valid, i.e. there is a PHY connected.
* Do this by checking model value field from ID2 register.
*/
-static struct eth_device* verify_phyaddr (const char *devname,
- unsigned char addr)
+static int verify_phyaddr(struct eepro100_priv *priv, unsigned char addr)
{
- struct eth_device *dev;
- unsigned short value;
- unsigned char model;
-
- dev = eth_get_dev_by_name(devname);
- if (dev == NULL) {
- printf("%s: no such device\n", devname);
- return NULL;
- }
+ unsigned short value, model;
+ int ret;
/* read id2 register */
- if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
- printf("%s: mii read timeout!\n", devname);
- return NULL;
+ ret = get_phyreg(priv, addr, MII_PHYSID2, &value);
+ if (ret) {
+ printf("%s: mii read timeout!\n", priv->name);
+ return ret;
}
/* get model */
- model = (unsigned char)((value >> 4) & 0x003f);
-
- if (model == 0) {
- printf("%s: no PHY at address %d\n", devname, addr);
- return NULL;
+ model = (value >> 4) & 0x003f;
+ if (!model) {
+ printf("%s: no PHY at address %d\n", priv->name, addr);
+ return -EINVAL;
}
- return dev;
+ return 0;
}
static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
int reg)
{
+ struct eepro100_priv *priv = bus->priv;
unsigned short value = 0;
- struct eth_device *dev;
+ int ret;
- dev = verify_phyaddr(bus->name, addr);
- if (dev == NULL)
- return -1;
+ ret = verify_phyaddr(priv, addr);
+ if (ret)
+ return ret;
- if (get_phyreg(dev, addr, reg, &value) != 0) {
+ ret = get_phyreg(priv, addr, reg, &value);
+ if (ret) {
printf("%s: mii read timeout!\n", bus->name);
- return -1;
+ return ret;
}
return value;
static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
- struct eth_device *dev;
+ struct eepro100_priv *priv = bus->priv;
+ int ret;
- dev = verify_phyaddr(bus->name, addr);
- if (dev == NULL)
- return -1;
+ ret = verify_phyaddr(priv, addr);
+ if (ret)
+ return ret;
- if (set_phyreg(dev, addr, reg, value) != 0) {
+ ret = set_phyreg(priv, addr, reg, value);
+ if (ret) {
printf("%s: mii write timeout!\n", bus->name);
- return -1;
+ return ret;
}
return 0;
}
-
#endif
-/* Wait for the chip get the command.
-*/
-static int wait_for_eepro100 (struct eth_device *dev)
+static void init_rx_ring(struct eepro100_priv *priv)
{
+ struct eepro100_rxfd *rx_ring = priv->rx_ring;
int i;
- for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
- if (i >= TOUT_LOOP) {
- return 0;
- }
+ for (i = 0; i < NUM_RX_DESC; i++) {
+ rx_ring[i].status = 0;
+ rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
+ cpu_to_le16 (RFD_CONTROL_S) : 0;
+ rx_ring[i].link =
+ cpu_to_le32(phys_to_bus(priv->devno,
+ (u32)&rx_ring[(i + 1) %
+ NUM_RX_DESC]));
+ rx_ring[i].rx_buf_addr = 0xffffffff;
+ rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
}
- return 1;
+ flush_dcache_range((unsigned long)rx_ring,
+ (unsigned long)rx_ring +
+ (sizeof(*rx_ring) * NUM_RX_DESC));
+
+ priv->rx_next = 0;
}
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
- {}
-};
+static void purge_tx_ring(struct eepro100_priv *priv)
+{
+ struct eepro100_txfd *tx_ring = priv->tx_ring;
+
+ priv->tx_next = 0;
+ priv->tx_threshold = 0x01208000;
+ memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
-int eepro100_initialize (bd_t * bis)
+ flush_dcache_range((unsigned long)tx_ring,
+ (unsigned long)tx_ring +
+ (sizeof(*tx_ring) * NUM_TX_DESC));
+}
+
+/* Wait for the chip get the command. */
+static int wait_for_eepro100(struct eepro100_priv *priv)
{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- u32 iobase, status;
- int idx = 0;
+ int i;
- while (1) {
- /* Find PCI device
- */
- if ((devno = pci_find_devices (supported, idx++)) < 0) {
- break;
- }
+ for (i = 0; INW(priv, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
+ if (i >= TOUT_LOOP)
+ return 0;
+ }
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
- iobase &= ~0xf;
+ return 1;
+}
-#ifdef DEBUG
- printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
- iobase);
-#endif
+static int eepro100_txcmd_send(struct eepro100_priv *priv,
+ struct eepro100_txfd *desc)
+{
+ u16 rstat;
+ int i = 0;
- pci_write_config_dword (devno,
- PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ flush_dcache_range((unsigned long)desc,
+ (unsigned long)desc + sizeof(*desc));
- /* Check if I/O accesses and Bus Mastering are enabled.
- */
- pci_read_config_dword (devno, PCI_COMMAND, &status);
- if (!(status & PCI_COMMAND_MEMORY)) {
- printf ("Error: Can not enable MEM access.\n");
- continue;
- }
+ if (!wait_for_eepro100(priv))
+ return -ETIMEDOUT;
- if (!(status & PCI_COMMAND_MASTER)) {
- printf ("Error: Can not enable Bus Mastering.\n");
- continue;
- }
+ OUTL(priv, phys_to_bus(priv->devno, (u32)desc), SCB_POINTER);
+ OUTW(priv, SCB_M | CU_START, SCB_CMD);
- dev = (struct eth_device *) malloc (sizeof *dev);
- if (!dev) {
- printf("eepro100: Can not allocate memory\n");
+ while (true) {
+ invalidate_dcache_range((unsigned long)desc,
+ (unsigned long)desc + sizeof(*desc));
+ rstat = le16_to_cpu(desc->status);
+ if (rstat & CONFIG_SYS_STATUS_C)
break;
+
+ if (i++ >= TOUT_LOOP) {
+ printf("%s: Tx error buffer not ready\n", priv->name);
+ return -EINVAL;
}
- memset(dev, 0, sizeof(*dev));
+ }
- sprintf (dev->name, "i82559#%d", card_number);
- dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
- dev->iobase = bus_to_phys (iobase);
- dev->init = eepro100_init;
- dev->halt = eepro100_halt;
- dev->send = eepro100_send;
- dev->recv = eepro100_recv;
+ invalidate_dcache_range((unsigned long)desc,
+ (unsigned long)desc + sizeof(*desc));
+ rstat = le16_to_cpu(desc->status);
- eth_register (dev);
-
-#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
- /* register mii command access routines */
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = eepro100_miiphy_read;
- mdiodev->write = eepro100_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
+ if (!(rstat & CONFIG_SYS_STATUS_OK)) {
+ printf("TX error status = 0x%08X\n", rstat);
+ return -EIO;
+ }
- card_number++;
+ return 0;
+}
- /* Set the latency timer for value.
- */
- pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
+/* SROM Read. */
+static int read_eeprom(struct eepro100_priv *priv, int location, int addr_len)
+{
+ unsigned short retval = 0;
+ int read_cmd = location | EE_READ_CMD(addr_len);
+ int i;
- udelay(10 * 1000);
+ OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
+ OUTW(priv, EE_ENB, SCB_EEPROM);
+
+ /* Shift the read command bits out. */
+ for (i = 12; i >= 0; i--) {
+ short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
- read_hw_addr (dev, bis);
+ OUTW(priv, EE_ENB | dataval, SCB_EEPROM);
+ udelay(1);
+ OUTW(priv, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
+ udelay(1);
}
+ OUTW(priv, EE_ENB, SCB_EEPROM);
- return card_number;
+ for (i = 15; i >= 0; i--) {
+ OUTW(priv, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
+ udelay(1);
+ retval = (retval << 1) |
+ !!(INW(priv, SCB_EEPROM) & EE_DATA_READ);
+ OUTW(priv, EE_ENB, SCB_EEPROM);
+ udelay(1);
+ }
+
+ /* Terminate the EEPROM access. */
+ OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
+ return retval;
}
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+static int eepro100_initialize_mii(struct eepro100_priv *priv)
+{
+ /* register mii command access routines */
+ struct mii_dev *mdiodev;
+ int ret;
+
+ mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+
+ strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
+ mdiodev->read = eepro100_miiphy_read;
+ mdiodev->write = eepro100_miiphy_write;
+ mdiodev->priv = priv;
+
+ ret = mdio_register(mdiodev);
+ if (ret < 0) {
+ mdio_free(mdiodev);
+ return ret;
+ }
-static int eepro100_init (struct eth_device *dev, bd_t * bis)
+ return 0;
+}
+#else
+static int eepro100_initialize_mii(struct eepro100_priv *priv)
{
- int i, status = -1;
- int tx_cur;
- struct descriptor *ias_cmd, *cfg_cmd;
+ return 0;
+}
+#endif
- /* Reset the ethernet controller
- */
- OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
- udelay(20);
+static struct pci_device_id supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER) },
+ { }
+};
- OUTL (dev, I82559_RESET, SCBPort);
- udelay(20);
+static void eepro100_get_hwaddr(struct eepro100_priv *priv)
+{
+ u16 sum = 0;
+ int i, j;
+ int addr_len = read_eeprom(priv, 0, 6) == 0xffff ? 8 : 6;
- if (!wait_for_eepro100 (dev)) {
- printf ("Error: Can not reset ethernet controller.\n");
- goto Done;
- }
- OUTL (dev, 0, SCBPointer);
- OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
+ for (j = 0, i = 0; i < 0x40; i++) {
+ u16 value = read_eeprom(priv, i, addr_len);
- if (!wait_for_eepro100 (dev)) {
- printf ("Error: Can not reset ethernet controller.\n");
- goto Done;
+ sum += value;
+ if (i < 3) {
+ priv->enetaddr[j++] = value;
+ priv->enetaddr[j++] = value >> 8;
+ }
}
- OUTL (dev, 0, SCBPointer);
- OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
-
- /* Initialize Rx and Tx rings.
- */
- init_rx_ring (dev);
- purge_tx_ring (dev);
-
- /* Tell the adapter where the RX ring is located.
- */
- if (!wait_for_eepro100 (dev)) {
- printf ("Error: Can not reset ethernet controller.\n");
- goto Done;
+
+ if (sum != 0xBABA) {
+ memset(priv->enetaddr, 0, ETH_ALEN);
+ debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
+ priv->name, sum);
}
+}
- OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
- OUTW (dev, SCB_M | RUC_START, SCBCmd);
+static int eepro100_init_common(struct eepro100_priv *priv)
+{
+ struct eepro100_rxfd *rx_ring = priv->rx_ring;
+ struct eepro100_txfd *tx_ring = priv->tx_ring;
+ struct eepro100_txfd *ias_cmd, *cfg_cmd;
+ int ret, status = -1;
+ int tx_cur;
- /* Send the Configure frame */
- tx_cur = tx_next;
- tx_next = ((tx_next + 1) % NUM_TX_DESC);
+ /* Reset the ethernet controller */
+ OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
+ udelay(20);
- cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
- cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
- cfg_cmd->status = 0;
- cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+ OUTL(priv, I82559_RESET, SCB_PORT);
+ udelay(20);
- memcpy (cfg_cmd->params, i82558_config_cmd,
- sizeof (i82558_config_cmd));
+ if (!wait_for_eepro100(priv)) {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto done;
+ }
+ OUTL(priv, 0, SCB_POINTER);
+ OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
- if (!wait_for_eepro100 (dev)) {
- printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
- goto Done;
+ if (!wait_for_eepro100(priv)) {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto done;
}
+ OUTL(priv, 0, SCB_POINTER);
+ OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
- OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
- OUTW (dev, SCB_M | CU_START, SCBCmd);
+ /* Initialize Rx and Tx rings. */
+ init_rx_ring(priv);
+ purge_tx_ring(priv);
- for (i = 0;
- !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
- i++) {
- if (i >= TOUT_LOOP) {
- printf ("%s: Tx error buffer not ready\n", dev->name);
- goto Done;
- }
+ /* Tell the adapter where the RX ring is located. */
+ if (!wait_for_eepro100(priv)) {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto done;
}
- if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
- printf ("TX error status = 0x%08X\n",
- le16_to_cpu (tx_ring[tx_cur].status));
- goto Done;
- }
+ /* RX ring cache was already flushed in init_rx_ring() */
+ OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[priv->rx_next]),
+ SCB_POINTER);
+ OUTW(priv, SCB_M | RUC_START, SCB_CMD);
- /* Send the Individual Address Setup frame
- */
- tx_cur = tx_next;
- tx_next = ((tx_next + 1) % NUM_TX_DESC);
+ /* Send the Configure frame */
+ tx_cur = priv->tx_next;
+ priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
- ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
- ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
- ias_cmd->status = 0;
- ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+ cfg_cmd = &tx_ring[tx_cur];
+ cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
+ CONFIG_SYS_CMD_CONFIGURE);
+ cfg_cmd->status = 0;
+ cfg_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
+ (u32)&tx_ring[priv->tx_next]));
- memcpy (ias_cmd->params, dev->enetaddr, 6);
+ memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd,
+ sizeof(i82558_config_cmd));
- /* Tell the adapter where the TX ring is located.
- */
- if (!wait_for_eepro100 (dev)) {
- printf ("Error: Can not reset ethernet controller.\n");
- goto Done;
+ ret = eepro100_txcmd_send(priv, cfg_cmd);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
+ goto done;
}
- OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
- OUTW (dev, SCB_M | CU_START, SCBCmd);
+ /* Send the Individual Address Setup frame */
+ tx_cur = priv->tx_next;
+ priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
- for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
- i++) {
- if (i >= TOUT_LOOP) {
- printf ("%s: Tx error buffer not ready\n",
- dev->name);
- goto Done;
- }
- }
+ ias_cmd = &tx_ring[tx_cur];
+ ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
+ CONFIG_SYS_CMD_IAS);
+ ias_cmd->status = 0;
+ ias_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
+ (u32)&tx_ring[priv->tx_next]));
+
+ memcpy(((struct descriptor *)ias_cmd)->params, priv->enetaddr, 6);
- if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
- printf ("TX error status = 0x%08X\n",
- le16_to_cpu (tx_ring[tx_cur].status));
- goto Done;
+ ret = eepro100_txcmd_send(priv, ias_cmd);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("Error: Can not reset ethernet controller.\n");
+ goto done;
}
status = 0;
- Done:
+done:
return status;
}
-static int eepro100_send(struct eth_device *dev, void *packet, int length)
+static int eepro100_send_common(struct eepro100_priv *priv,
+ void *packet, int length)
{
- int i, status = -1;
+ struct eepro100_txfd *tx_ring = priv->tx_ring;
+ struct eepro100_txfd *desc;
+ int ret, status = -1;
int tx_cur;
if (length <= 0) {
- printf ("%s: bad packet size: %d\n", dev->name, length);
- goto Done;
- }
-
- tx_cur = tx_next;
- tx_next = (tx_next + 1) % NUM_TX_DESC;
-
- tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
- TxCB_CMD_SF |
- TxCB_CMD_S |
- TxCB_CMD_EL );
- tx_ring[tx_cur].status = 0;
- tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
- tx_ring[tx_cur].link =
- cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
- tx_ring[tx_cur].tx_desc_addr =
- cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
- tx_ring[tx_cur].tx_buf_addr0 =
- cpu_to_le32 (phys_to_bus ((u_long) packet));
- tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
-
- if (!wait_for_eepro100 (dev)) {
- printf ("%s: Tx error ethernet controller not ready.\n",
- dev->name);
- goto Done;
- }
-
- /* Send the packet.
- */
- OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
- OUTW (dev, SCB_M | CU_START, SCBCmd);
-
- for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
- i++) {
- if (i >= TOUT_LOOP) {
- printf ("%s: Tx error buffer not ready\n", dev->name);
- goto Done;
- }
+ printf("%s: bad packet size: %d\n", priv->name, length);
+ goto done;
}
- if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
- printf ("TX error status = 0x%08X\n",
- le16_to_cpu (tx_ring[tx_cur].status));
- goto Done;
+ tx_cur = priv->tx_next;
+ priv->tx_next = (priv->tx_next + 1) % NUM_TX_DESC;
+
+ desc = &tx_ring[tx_cur];
+ desc->command = cpu_to_le16(TXCB_CMD_TRANSMIT | TXCB_CMD_SF |
+ TXCB_CMD_S | TXCB_CMD_EL);
+ desc->status = 0;
+ desc->count = cpu_to_le32(priv->tx_threshold);
+ desc->link = cpu_to_le32(phys_to_bus(priv->devno,
+ (u32)&tx_ring[priv->tx_next]));
+ desc->tx_desc_addr = cpu_to_le32(phys_to_bus(priv->devno,
+ (u32)&desc->tx_buf_addr0));
+ desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus(priv->devno,
+ (u_long)packet));
+ desc->tx_buf_size0 = cpu_to_le32(length);
+
+ ret = eepro100_txcmd_send(priv, &tx_ring[tx_cur]);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: Tx error ethernet controller not ready.\n",
+ priv->name);
+ goto done;
}
status = length;
- Done:
+done:
return status;
}
-static int eepro100_recv (struct eth_device *dev)
+static int eepro100_recv_common(struct eepro100_priv *priv, uchar **packetp)
{
- u16 status, stat;
- int rx_prev, length = 0;
-
- stat = INW (dev, SCBStatus);
- OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
+ struct eepro100_rxfd *rx_ring = priv->rx_ring;
+ struct eepro100_rxfd *desc;
+ int length;
+ u16 status;
+
+ priv->rx_stat = INW(priv, SCB_STATUS);
+ OUTW(priv, priv->rx_stat & SCB_STATUS_RNR, SCB_STATUS);
+
+ desc = &rx_ring[priv->rx_next];
+ invalidate_dcache_range((unsigned long)desc,
+ (unsigned long)desc + sizeof(*desc));
+ status = le16_to_cpu(desc->status);
+
+ if (!(status & RFD_STATUS_C))
+ return 0;
+
+ /* Valid frame status. */
+ if (status & RFD_STATUS_OK) {
+ /* A valid frame received. */
+ length = le32_to_cpu(desc->count) & 0x3fff;
+ /* Pass the packet up to the protocol layers. */
+ *packetp = desc->data;
+ return length;
+ }
- for (;;) {
- status = le16_to_cpu (rx_ring[rx_next].status);
+ /* There was an error. */
+ printf("RX error status = 0x%08X\n", status);
+ return -EINVAL;
+}
- if (!(status & RFD_STATUS_C)) {
- break;
- }
+static void eepro100_free_pkt_common(struct eepro100_priv *priv)
+{
+ struct eepro100_rxfd *rx_ring = priv->rx_ring;
+ struct eepro100_rxfd *desc;
+ int rx_prev;
- /* Valid frame status.
- */
- if ((status & RFD_STATUS_OK)) {
- /* A valid frame received.
- */
- length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
-
- /* Pass the packet up to the protocol
- * layers.
- */
- net_process_received_packet((u8 *)rx_ring[rx_next].data,
- length);
- } else {
- /* There was an error.
- */
- printf ("RX error status = 0x%08X\n", status);
- }
+ desc = &rx_ring[priv->rx_next];
- rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
- rx_ring[rx_next].status = 0;
- rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
+ desc->control = cpu_to_le16(RFD_CONTROL_S);
+ desc->status = 0;
+ desc->count = cpu_to_le32(PKTSIZE_ALIGN << 16);
+ flush_dcache_range((unsigned long)desc,
+ (unsigned long)desc + sizeof(*desc));
- rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
- rx_ring[rx_prev].control = 0;
+ rx_prev = (priv->rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
+ desc = &rx_ring[rx_prev];
+ desc->control = 0;
+ flush_dcache_range((unsigned long)desc,
+ (unsigned long)desc + sizeof(*desc));
- /* Update entry information.
- */
- rx_next = (rx_next + 1) % NUM_RX_DESC;
- }
+ /* Update entry information. */
+ priv->rx_next = (priv->rx_next + 1) % NUM_RX_DESC;
- if (stat & SCB_STATUS_RNR) {
+ if (!(priv->rx_stat & SCB_STATUS_RNR))
+ return;
- printf ("%s: Receiver is not ready, restart it !\n", dev->name);
+ printf("%s: Receiver is not ready, restart it !\n", priv->name);
- /* Reinitialize Rx ring.
- */
- init_rx_ring (dev);
+ /* Reinitialize Rx ring. */
+ init_rx_ring(priv);
- if (!wait_for_eepro100 (dev)) {
- printf ("Error: Can not restart ethernet controller.\n");
- goto Done;
- }
-
- OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
- OUTW (dev, SCB_M | RUC_START, SCBCmd);
+ if (!wait_for_eepro100(priv)) {
+ printf("Error: Can not restart ethernet controller.\n");
+ return;
}
- Done:
- return length;
+ /* RX ring cache was already flushed in init_rx_ring() */
+ OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[priv->rx_next]),
+ SCB_POINTER);
+ OUTW(priv, SCB_M | RUC_START, SCB_CMD);
}
-static void eepro100_halt (struct eth_device *dev)
+static void eepro100_halt_common(struct eepro100_priv *priv)
{
- /* Reset the ethernet controller
- */
- OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
+ /* Reset the ethernet controller */
+ OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
udelay(20);
- OUTL (dev, I82559_RESET, SCBPort);
+ OUTL(priv, I82559_RESET, SCB_PORT);
udelay(20);
- if (!wait_for_eepro100 (dev)) {
- printf ("Error: Can not reset ethernet controller.\n");
- goto Done;
+ if (!wait_for_eepro100(priv)) {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto done;
}
- OUTL (dev, 0, SCBPointer);
- OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
+ OUTL(priv, 0, SCB_POINTER);
+ OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
- if (!wait_for_eepro100 (dev)) {
- printf ("Error: Can not reset ethernet controller.\n");
- goto Done;
+ if (!wait_for_eepro100(priv)) {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto done;
}
- OUTL (dev, 0, SCBPointer);
- OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
+ OUTL(priv, 0, SCB_POINTER);
+ OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
- Done:
+done:
return;
}
- /* SROM Read.
- */
-static int read_eeprom (struct eth_device *dev, int location, int addr_len)
+#ifndef CONFIG_DM_ETH
+static int eepro100_init(struct eth_device *dev, bd_t *bis)
{
- unsigned short retval = 0;
- int read_cmd = location | EE_READ_CMD;
- int i;
+ struct eepro100_priv *priv =
+ container_of(dev, struct eepro100_priv, dev);
- OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
- OUTW (dev, EE_ENB, SCBeeprom);
+ return eepro100_init_common(priv);
+}
- /* Shift the read command bits out. */
- for (i = 12; i >= 0; i--) {
- short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+static void eepro100_halt(struct eth_device *dev)
+{
+ struct eepro100_priv *priv =
+ container_of(dev, struct eepro100_priv, dev);
- OUTW (dev, EE_ENB | dataval, SCBeeprom);
- udelay(1);
- OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
- udelay(1);
- }
- OUTW (dev, EE_ENB, SCBeeprom);
+ eepro100_halt_common(priv);
+}
- for (i = 15; i >= 0; i--) {
- OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
- udelay(1);
- retval = (retval << 1) |
- ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
- OUTW (dev, EE_ENB, SCBeeprom);
- udelay(1);
- }
+static int eepro100_send(struct eth_device *dev, void *packet, int length)
+{
+ struct eepro100_priv *priv =
+ container_of(dev, struct eepro100_priv, dev);
- /* Terminate the EEPROM access. */
- OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
- return retval;
+ return eepro100_send_common(priv, packet, length);
}
-#ifdef CONFIG_EEPRO100_SROM_WRITE
-int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
-{
- unsigned short dataval;
- int enable_cmd = 0x3f | EE_EWENB_CMD;
- int write_cmd = location | EE_WRITE_CMD;
- int i;
- unsigned long datalong, tmplong;
-
- OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
- udelay(1);
- OUTW(dev, EE_ENB, SCBeeprom);
-
- /* Shift the enable command bits out. */
- for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
- {
- dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
- OUTW(dev, EE_ENB | dataval, SCBeeprom);
- udelay(1);
- OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
- udelay(1);
- }
-
- OUTW(dev, EE_ENB, SCBeeprom);
- udelay(1);
- OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
- udelay(1);
- OUTW(dev, EE_ENB, SCBeeprom);
-
-
- /* Shift the write command bits out. */
- for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
- {
- dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
- OUTW(dev, EE_ENB | dataval, SCBeeprom);
- udelay(1);
- OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
- udelay(1);
- }
-
- /* Write the data */
- datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
-
- for (i = 0; i< EE_DATA_BITS; i++)
- {
- /* Extract and move data bit to bit DI */
- dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
-
- OUTW(dev, EE_ENB | dataval, SCBeeprom);
- udelay(1);
- OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
- udelay(1);
- OUTW(dev, EE_ENB | dataval, SCBeeprom);
- udelay(1);
-
- datalong = datalong << 1; /* Adjust significant data bit*/
- }
-
- /* Finish up command (toggle CS) */
- OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
- udelay(1); /* delay for more than 250 ns */
- OUTW(dev, EE_ENB, SCBeeprom);
-
- /* Wait for programming ready (D0 = 1) */
- tmplong = 10;
- do
- {
- dataval = INW(dev, SCBeeprom);
- if (dataval & EE_DATA_READ)
- break;
- udelay(10000);
- }
- while (-- tmplong);
-
- if (tmplong == 0)
- {
- printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
- return -1;
- }
-
- /* Terminate the EEPROM access. */
- OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
-
- return 0;
+static int eepro100_recv(struct eth_device *dev)
+{
+ struct eepro100_priv *priv =
+ container_of(dev, struct eepro100_priv, dev);
+ uchar *packet;
+ int ret;
+
+ ret = eepro100_recv_common(priv, &packet);
+ if (ret > 0)
+ net_process_received_packet(packet, ret);
+ if (ret)
+ eepro100_free_pkt_common(priv);
+
+ return ret;
}
-#endif
-static void init_rx_ring (struct eth_device *dev)
+int eepro100_initialize(bd_t *bis)
{
- int i;
+ struct eepro100_priv *priv;
+ struct eth_device *dev;
+ int card_number = 0;
+ u32 iobase, status;
+ pci_dev_t devno;
+ int idx = 0;
+ int ret;
- for (i = 0; i < NUM_RX_DESC; i++) {
- rx_ring[i].status = 0;
- rx_ring[i].control =
- (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
- rx_ring[i].link =
- cpu_to_le32 (phys_to_bus
- ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
- rx_ring[i].rx_buf_addr = 0xffffffff;
- rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
+ while (1) {
+ /* Find PCI device */
+ devno = pci_find_devices(supported, idx++);
+ if (devno < 0)
+ break;
+
+ pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
+ iobase &= ~0xf;
+
+ debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
+ iobase);
+
+ pci_write_config_dword(devno, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Check if I/O accesses and Bus Mastering are enabled. */
+ pci_read_config_dword(devno, PCI_COMMAND, &status);
+ if (!(status & PCI_COMMAND_MEMORY)) {
+ printf("Error: Can not enable MEM access.\n");
+ continue;
+ }
+
+ if (!(status & PCI_COMMAND_MASTER)) {
+ printf("Error: Can not enable Bus Mastering.\n");
+ continue;
+ }
+
+ priv = calloc(1, sizeof(*priv));
+ if (!priv) {
+ printf("eepro100: Can not allocate memory\n");
+ break;
+ }
+ dev = &priv->dev;
+
+ sprintf(dev->name, "i82559#%d", card_number);
+ priv->name = dev->name;
+ /* this have to come before bus_to_phys() */
+ priv->devno = devno;
+ priv->iobase = (void __iomem *)bus_to_phys(devno, iobase);
+ priv->enetaddr = dev->enetaddr;
+
+ dev->init = eepro100_init;
+ dev->halt = eepro100_halt;
+ dev->send = eepro100_send;
+ dev->recv = eepro100_recv;
+
+ eth_register(dev);
+
+ ret = eepro100_initialize_mii(priv);
+ if (ret) {
+ eth_unregister(dev);
+ free(priv);
+ return ret;
+ }
+
+ card_number++;
+
+ /* Set the latency timer for value. */
+ pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
+
+ udelay(10 * 1000);
+
+ eepro100_get_hwaddr(priv);
}
- rx_next = 0;
+ return card_number;
}
-static void purge_tx_ring (struct eth_device *dev)
+#else /* DM_ETH */
+static int eepro100_start(struct udevice *dev)
{
- int i;
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eepro100_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
- tx_next = 0;
- tx_threshold = 0x01208000;
+ return eepro100_init_common(priv);
+}
- for (i = 0; i < NUM_TX_DESC; i++) {
- tx_ring[i].status = 0;
- tx_ring[i].command = 0;
- tx_ring[i].link = 0;
- tx_ring[i].tx_desc_addr = 0;
- tx_ring[i].count = 0;
+static void eepro100_stop(struct udevice *dev)
+{
+ struct eepro100_priv *priv = dev_get_priv(dev);
- tx_ring[i].tx_buf_addr0 = 0;
- tx_ring[i].tx_buf_size0 = 0;
- tx_ring[i].tx_buf_addr1 = 0;
- tx_ring[i].tx_buf_size1 = 0;
- }
+ eepro100_halt_common(priv);
}
-static void read_hw_addr (struct eth_device *dev, bd_t * bis)
+static int eepro100_send(struct udevice *dev, void *packet, int length)
{
- u16 sum = 0;
- int i, j;
- int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
+ struct eepro100_priv *priv = dev_get_priv(dev);
+ int ret;
- for (j = 0, i = 0; i < 0x40; i++) {
- u16 value = read_eeprom (dev, i, addr_len);
+ ret = eepro100_send_common(priv, packet, length);
- sum += value;
- if (i < 3) {
- dev->enetaddr[j++] = value;
- dev->enetaddr[j++] = value >> 8;
- }
- }
+ return ret ? 0 : -ETIMEDOUT;
+}
- if (sum != 0xBABA) {
- memset (dev->enetaddr, 0, ETH_ALEN);
-#ifdef DEBUG
- printf ("%s: Invalid EEPROM checksum %#4.4x, "
- "check settings before activating this device!\n",
- dev->name, sum);
-#endif
+static int eepro100_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct eepro100_priv *priv = dev_get_priv(dev);
+
+ return eepro100_recv_common(priv, packetp);
+}
+
+static int eepro100_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct eepro100_priv *priv = dev_get_priv(dev);
+
+ eepro100_free_pkt_common(priv);
+
+ return 0;
+}
+
+static int eepro100_read_rom_hwaddr(struct udevice *dev)
+{
+ struct eepro100_priv *priv = dev_get_priv(dev);
+
+ eepro100_get_hwaddr(priv);
+
+ return 0;
+}
+
+static int eepro100_bind(struct udevice *dev)
+{
+ static int card_number;
+ char name[16];
+
+ sprintf(name, "eepro100#%u", card_number++);
+
+ return device_set_name(dev, name);
+}
+
+static int eepro100_probe(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eepro100_priv *priv = dev_get_priv(dev);
+ u16 command, status;
+ u32 iobase;
+ int ret;
+
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
+ iobase &= ~0xf;
+
+ debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", iobase);
+
+ priv->devno = dev;
+ priv->enetaddr = plat->enetaddr;
+ priv->iobase = (void __iomem *)bus_to_phys(dev, iobase);
+
+ command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ dm_pci_write_config16(dev, PCI_COMMAND, command);
+ dm_pci_read_config16(dev, PCI_COMMAND, &status);
+ if ((status & command) != command) {
+ printf("eepro100: Couldn't enable IO access or Bus Mastering\n");
+ return -EINVAL;
}
+
+ ret = eepro100_initialize_mii(priv);
+ if (ret)
+ return ret;
+
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
+
+ return 0;
}
+
+static const struct eth_ops eepro100_ops = {
+ .start = eepro100_start,
+ .send = eepro100_send,
+ .recv = eepro100_recv,
+ .stop = eepro100_stop,
+ .free_pkt = eepro100_free_pkt,
+ .read_rom_hwaddr = eepro100_read_rom_hwaddr,
+};
+
+U_BOOT_DRIVER(eth_eepro100) = {
+ .name = "eth_eepro100",
+ .id = UCLASS_ETH,
+ .bind = eepro100_bind,
+ .probe = eepro100_probe,
+ .ops = &eepro100_ops,
+ .priv_auto_alloc_size = sizeof(struct eepro100_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+U_BOOT_PCI_DEVICE(eth_eepro100, supported);
+#endif
addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
-#ifdef CONFIG_DM_SPI_FLASH
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
struct udevice *new;
/* speed and mode will be read from DT */
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
-#ifdef CONFIG_DM_SPI_FLASH
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
struct udevice *new;
/* speed and mode will be read from DT */
#include <common.h>
#include <cpu_func.h>
+#include <dm.h>
#include <log.h>
+#include <dm.h>
#include <malloc.h>
+#include <memalign.h>
#include <net.h>
#include <netdev.h>
#include <asm/cache.h>
struct pcnet_rx_head rx_ring[RX_RING_SIZE];
struct pcnet_tx_head tx_ring[TX_RING_SIZE];
struct pcnet_init_block init_block;
-};
+} __aligned(ARCH_DMA_MINALIGN);
-typedef struct pcnet_priv {
- struct pcnet_uncached_priv *uc;
+struct pcnet_priv {
+ struct pcnet_uncached_priv ucp;
/* Receive Buffer space */
- unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
+ unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
+ struct pcnet_uncached_priv *uc;
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev;
+ const char *name;
+#else
+ pci_dev_t dev;
+ char *name;
+#endif
+ void __iomem *iobase;
+ u8 *enetaddr;
+ u16 status;
int cur_rx;
int cur_tx;
-} pcnet_priv_t;
-
-static pcnet_priv_t *lp;
+};
/* Offsets from base I/O address for WIO mode */
#define PCNET_RDP 0x10
#define PCNET_RESET 0x14
#define PCNET_BDP 0x16
-static u16 pcnet_read_csr(struct eth_device *dev, int index)
+static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
{
- void __iomem *base = (void __iomem *)dev->iobase;
-
- writew(index, base + PCNET_RAP);
- return readw(base + PCNET_RDP);
+ writew(index, lp->iobase + PCNET_RAP);
+ return readw(lp->iobase + PCNET_RDP);
}
-static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
+static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
{
- void __iomem *base = (void __iomem *)dev->iobase;
-
- writew(index, base + PCNET_RAP);
- writew(val, base + PCNET_RDP);
+ writew(index, lp->iobase + PCNET_RAP);
+ writew(val, lp->iobase + PCNET_RDP);
}
-static u16 pcnet_read_bcr(struct eth_device *dev, int index)
+static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
{
- void __iomem *base = (void __iomem *)dev->iobase;
-
- writew(index, base + PCNET_RAP);
- return readw(base + PCNET_BDP);
+ writew(index, lp->iobase + PCNET_RAP);
+ return readw(lp->iobase + PCNET_BDP);
}
-static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
+static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
{
- void __iomem *base = (void __iomem *)dev->iobase;
-
- writew(index, base + PCNET_RAP);
- writew(val, base + PCNET_BDP);
+ writew(index, lp->iobase + PCNET_RAP);
+ writew(val, lp->iobase + PCNET_BDP);
}
-static void pcnet_reset(struct eth_device *dev)
+static void pcnet_reset(struct pcnet_priv *lp)
{
- void __iomem *base = (void __iomem *)dev->iobase;
-
- readw(base + PCNET_RESET);
+ readw(lp->iobase + PCNET_RESET);
}
-static int pcnet_check(struct eth_device *dev)
+static int pcnet_check(struct pcnet_priv *lp)
{
- void __iomem *base = (void __iomem *)dev->iobase;
-
- writew(88, base + PCNET_RAP);
- return readw(base + PCNET_RAP) == 88;
+ writew(88, lp->iobase + PCNET_RAP);
+ return readw(lp->iobase + PCNET_RAP) == 88;
}
-static int pcnet_init (struct eth_device *dev, bd_t * bis);
-static int pcnet_send(struct eth_device *dev, void *packet, int length);
-static int pcnet_recv (struct eth_device *dev);
-static void pcnet_halt (struct eth_device *dev);
-static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
-
-static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
- void *addr)
+static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
{
- pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
void *virt_addr = addr;
- return pci_virt_to_mem(devbusfn, virt_addr);
+#ifdef CONFIG_DM_ETH
+ return dm_pci_virt_to_mem(lp->dev, virt_addr);
+#else
+ return pci_virt_to_mem(lp->dev, virt_addr);
+#endif
}
static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
{}
};
-
-int pcnet_initialize(bd_t *bis)
-{
- pci_dev_t devbusfn;
- struct eth_device *dev;
- u16 command, status;
- int dev_nr = 0;
- u32 bar;
-
- PCNET_DEBUG1("\npcnet_initialize...\n");
-
- for (dev_nr = 0;; dev_nr++) {
-
- /*
- * Find the PCnet PCI device(s).
- */
- devbusfn = pci_find_devices(supported, dev_nr);
- if (devbusfn < 0)
- break;
-
- /*
- * Allocate and pre-fill the device structure.
- */
- dev = (struct eth_device *)malloc(sizeof(*dev));
- if (!dev) {
- printf("pcnet: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
- dev->priv = (void *)(unsigned long)devbusfn;
- sprintf(dev->name, "pcnet#%d", dev_nr);
-
- /*
- * Setup the PCI device.
- */
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
- dev->iobase = pci_mem_to_phys(devbusfn, bar);
- dev->iobase &= ~0xf;
-
- PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
- dev->name, devbusfn, (unsigned long)dev->iobase);
-
- command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- pci_write_config_word(devbusfn, PCI_COMMAND, command);
- pci_read_config_word(devbusfn, PCI_COMMAND, &status);
- if ((status & command) != command) {
- printf("%s: Couldn't enable IO access or Bus Mastering\n",
- dev->name);
- free(dev);
- continue;
- }
-
- pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
-
- /*
- * Probe the PCnet chip.
- */
- if (pcnet_probe(dev, bis, dev_nr) < 0) {
- free(dev);
- continue;
- }
-
- /*
- * Setup device structure and register the driver.
- */
- dev->init = pcnet_init;
- dev->halt = pcnet_halt;
- dev->send = pcnet_send;
- dev->recv = pcnet_recv;
-
- eth_register(dev);
- }
-
- udelay(10 * 1000);
-
- return dev_nr;
-}
-
-static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
+static int pcnet_probe_common(struct pcnet_priv *lp)
{
int chip_version;
char *chipname;
-
-#ifdef PCNET_HAS_PROM
int i;
-#endif
/* Reset the PCnet controller */
- pcnet_reset(dev);
+ pcnet_reset(lp);
/* Check if register access is working */
- if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
- printf("%s: CSR register access check failed\n", dev->name);
+ if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
+ printf("%s: CSR register access check failed\n", lp->name);
return -1;
}
/* Identify the chip */
- chip_version =
- pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
+ chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
if ((chip_version & 0xfff) != 0x003)
return -1;
chip_version = (chip_version >> 12) & 0xffff;
break;
default:
printf("%s: PCnet version %#x not supported\n",
- dev->name, chip_version);
+ lp->name, chip_version);
return -1;
}
PCNET_DEBUG1("AMD %s\n", chipname);
-#ifdef PCNET_HAS_PROM
/*
* In most chips, after a chip reset, the ethernet address is read from
* the station address PROM at the base address and programmed into the
for (i = 0; i < 3; i++) {
unsigned int val;
- val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
+ val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
/* There may be endianness issues here. */
- dev->enetaddr[2 * i] = val & 0x0ff;
- dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
+ lp->enetaddr[2 * i] = val & 0x0ff;
+ lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
}
-#endif /* PCNET_HAS_PROM */
return 0;
}
-static int pcnet_init(struct eth_device *dev, bd_t *bis)
+static int pcnet_init_common(struct pcnet_priv *lp)
{
struct pcnet_uncached_priv *uc;
int i, val;
unsigned long addr;
- PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
+ PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
/* Switch pcnet to 32bit mode */
- pcnet_write_bcr(dev, 20, 2);
+ pcnet_write_bcr(lp, 20, 2);
/* Set/reset autoselect bit */
- val = pcnet_read_bcr(dev, 2) & ~2;
+ val = pcnet_read_bcr(lp, 2) & ~2;
val |= 2;
- pcnet_write_bcr(dev, 2, val);
+ pcnet_write_bcr(lp, 2, val);
/* Enable auto negotiate, setup, disable fd */
- val = pcnet_read_bcr(dev, 32) & ~0x98;
+ val = pcnet_read_bcr(lp, 32) & ~0x98;
val |= 0x20;
- pcnet_write_bcr(dev, 32, val);
+ pcnet_write_bcr(lp, 32, val);
/*
* Enable NOUFLO on supported controllers, with the transmit
* slower devices. Controllers which do not support NOUFLO will
* simply be left with a larger transmit FIFO threshold.
*/
- val = pcnet_read_bcr(dev, 18);
+ val = pcnet_read_bcr(lp, 18);
val |= 1 << 11;
- pcnet_write_bcr(dev, 18, val);
- val = pcnet_read_csr(dev, 80);
+ pcnet_write_bcr(lp, 18, val);
+ val = pcnet_read_csr(lp, 80);
val |= 0x3 << 10;
- pcnet_write_csr(dev, 80, val);
-
- /*
- * We only maintain one structure because the drivers will never
- * be used concurrently. In 32bit mode the RX and TX ring entries
- * must be aligned on 16-byte boundaries.
- */
- if (lp == NULL) {
- addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
- addr = (addr + 0xf) & ~0xf;
- lp = (pcnet_priv_t *)addr;
-
- addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
- sizeof(*lp->uc));
- flush_dcache_range(addr, addr + sizeof(*lp->uc));
- addr = (unsigned long)map_physmem(addr,
- roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
- MAP_NOCACHE);
- lp->uc = (struct pcnet_uncached_priv *)addr;
-
- addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
- sizeof(*lp->rx_buf));
- flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
- lp->rx_buf = (void *)addr;
- }
+ pcnet_write_csr(lp, 80, val);
uc = lp->uc;
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
+ addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
uc->rx_ring[i].base = cpu_to_le32(addr);
uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
uc->rx_ring[i].status = cpu_to_le16(0x8000);
PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
for (i = 0; i < 6; i++) {
- lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
+ lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
}
uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
- addr = pcnet_virt_to_mem(dev, uc->rx_ring);
+ addr = pcnet_virt_to_mem(lp, uc->rx_ring);
uc->init_block.rx_ring = cpu_to_le32(addr);
- addr = pcnet_virt_to_mem(dev, uc->tx_ring);
+ addr = pcnet_virt_to_mem(lp, uc->tx_ring);
uc->init_block.tx_ring = cpu_to_le32(addr);
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
* Tell the controller where the Init Block is located.
*/
barrier();
- addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
- pcnet_write_csr(dev, 1, addr & 0xffff);
- pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
+ addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
+ pcnet_write_csr(lp, 1, addr & 0xffff);
+ pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
- pcnet_write_csr(dev, 4, 0x0915);
- pcnet_write_csr(dev, 0, 0x0001); /* start */
+ pcnet_write_csr(lp, 4, 0x0915);
+ pcnet_write_csr(lp, 0, 0x0001); /* start */
/* Wait for Init Done bit */
for (i = 10000; i > 0; i--) {
- if (pcnet_read_csr(dev, 0) & 0x0100)
+ if (pcnet_read_csr(lp, 0) & 0x0100)
break;
udelay(10);
}
if (i <= 0) {
- printf("%s: TIMEOUT: controller init failed\n", dev->name);
- pcnet_reset(dev);
+ printf("%s: TIMEOUT: controller init failed\n", lp->name);
+ pcnet_reset(lp);
return -1;
}
/*
* Finally start network controller operation.
*/
- pcnet_write_csr(dev, 0, 0x0002);
+ pcnet_write_csr(lp, 0, 0x0002);
return 0;
}
-static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
+static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
{
int i, status;
u32 addr;
}
if (i <= 0) {
printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
- dev->name, lp->cur_tx, status);
+ lp->name, lp->cur_tx, status);
pkt_len = 0;
goto failure;
}
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
- addr = pcnet_virt_to_mem(dev, packet);
+ addr = pcnet_virt_to_mem(lp, packet);
writew(-pkt_len, &entry->length);
writel(0, &entry->misc);
writel(addr, &entry->base);
writew(0x8300, &entry->status);
/* Trigger an immediate send poll. */
- pcnet_write_csr(dev, 0, 0x0008);
+ pcnet_write_csr(lp, 0, 0x0008);
failure:
if (++lp->cur_tx >= TX_RING_SIZE)
return pkt_len;
}
-static int pcnet_recv (struct eth_device *dev)
+static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
{
struct pcnet_rx_head *entry;
unsigned char *buf;
int pkt_len = 0;
- u16 status, err_status;
-
- while (1) {
- entry = &lp->uc->rx_ring[lp->cur_rx];
- /*
- * If we own the next entry, it's a new packet. Send it up.
- */
- status = readw(&entry->status);
- if ((status & 0x8000) != 0)
- break;
- err_status = status >> 8;
-
- if (err_status != 0x03) { /* There was an error. */
- printf("%s: Rx%d", dev->name, lp->cur_rx);
- PCNET_DEBUG1(" (status=0x%x)", err_status);
- if (err_status & 0x20)
- printf(" Frame");
- if (err_status & 0x10)
- printf(" Overflow");
- if (err_status & 0x08)
- printf(" CRC");
- if (err_status & 0x04)
- printf(" Fifo");
- printf(" Error\n");
- status &= 0x03ff;
-
- } else {
- pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
- if (pkt_len < 60) {
- printf("%s: Rx%d: invalid packet length %d\n",
- dev->name, lp->cur_rx, pkt_len);
- } else {
- buf = (*lp->rx_buf)[lp->cur_rx];
- invalidate_dcache_range((unsigned long)buf,
- (unsigned long)buf + pkt_len);
- net_process_received_packet(buf, pkt_len);
- PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
- lp->cur_rx, pkt_len, buf);
- }
- }
+ u16 err_status;
- status |= 0x8000;
- writew(status, &entry->status);
+ entry = &lp->uc->rx_ring[lp->cur_rx];
+ /*
+ * If we own the next entry, it's a new packet. Send it up.
+ */
+ lp->status = readw(&entry->status);
+ if ((lp->status & 0x8000) != 0)
+ return 0;
+ err_status = lp->status >> 8;
+
+ if (err_status != 0x03) { /* There was an error. */
+ printf("%s: Rx%d", lp->name, lp->cur_rx);
+ PCNET_DEBUG1(" (status=0x%x)", err_status);
+ if (err_status & 0x20)
+ printf(" Frame");
+ if (err_status & 0x10)
+ printf(" Overflow");
+ if (err_status & 0x08)
+ printf(" CRC");
+ if (err_status & 0x04)
+ printf(" Fifo");
+ printf(" Error\n");
+ lp->status &= 0x03ff;
+ return 0;
+ }
- if (++lp->cur_rx >= RX_RING_SIZE)
- lp->cur_rx = 0;
+ pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
+ if (pkt_len < 60) {
+ printf("%s: Rx%d: invalid packet length %d\n",
+ lp->name, lp->cur_rx, pkt_len);
+ return 0;
}
+
+ *bufp = lp->rx_buf[lp->cur_rx];
+ invalidate_dcache_range((unsigned long)*bufp,
+ (unsigned long)*bufp + pkt_len);
+
+ PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
+ lp->cur_rx, pkt_len, buf);
+
return pkt_len;
}
-static void pcnet_halt(struct eth_device *dev)
+static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
+{
+ struct pcnet_rx_head *entry;
+
+ entry = &lp->uc->rx_ring[lp->cur_rx];
+
+ lp->status |= 0x8000;
+ writew(lp->status, &entry->status);
+
+ if (++lp->cur_rx >= RX_RING_SIZE)
+ lp->cur_rx = 0;
+}
+
+static void pcnet_halt_common(struct pcnet_priv *lp)
{
int i;
- PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
+ PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
/* Reset the PCnet controller */
- pcnet_reset(dev);
+ pcnet_reset(lp);
/* Wait for Stop bit */
for (i = 1000; i > 0; i--) {
- if (pcnet_read_csr(dev, 0) & 0x4)
+ if (pcnet_read_csr(lp, 0) & 0x4)
break;
udelay(10);
}
if (i <= 0)
- printf("%s: TIMEOUT: controller reset failed\n", dev->name);
+ printf("%s: TIMEOUT: controller reset failed\n", lp->name);
+}
+
+#ifndef CONFIG_DM_ETH
+static int pcnet_init(struct eth_device *dev, bd_t *bis)
+{
+ struct pcnet_priv *lp = dev->priv;
+
+ return pcnet_init_common(lp);
+}
+
+static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
+{
+ struct pcnet_priv *lp = dev->priv;
+
+ return pcnet_send_common(lp, packet, pkt_len);
+}
+
+static int pcnet_recv(struct eth_device *dev)
+{
+ struct pcnet_priv *lp = dev->priv;
+ uchar *packet;
+ int ret;
+
+ ret = pcnet_recv_common(lp, &packet);
+ if (ret > 0)
+ net_process_received_packet(packet, ret);
+ if (ret)
+ pcnet_free_pkt_common(lp, ret);
+
+ return ret;
+}
+
+static void pcnet_halt(struct eth_device *dev)
+{
+ struct pcnet_priv *lp = dev->priv;
+
+ pcnet_halt_common(lp);
+}
+
+int pcnet_initialize(bd_t *bis)
+{
+ pci_dev_t devbusfn;
+ struct eth_device *dev;
+ struct pcnet_priv *lp;
+ u16 command, status;
+ int dev_nr = 0;
+ u32 bar;
+
+ PCNET_DEBUG1("\n%s...\n", __func__);
+
+ for (dev_nr = 0; ; dev_nr++) {
+ /*
+ * Find the PCnet PCI device(s).
+ */
+ devbusfn = pci_find_devices(supported, dev_nr);
+ if (devbusfn < 0)
+ break;
+
+ /*
+ * Allocate and pre-fill the device structure.
+ */
+ dev = calloc(1, sizeof(*dev));
+ if (!dev) {
+ printf("pcnet: Can not allocate memory\n");
+ break;
+ }
+
+ /*
+ * We only maintain one structure because the drivers will
+ * never be used concurrently. In 32bit mode the RX and TX
+ * ring entries must be aligned on 16-byte boundaries.
+ */
+ lp = malloc_cache_aligned(sizeof(*lp));
+ lp->uc = map_physmem((phys_addr_t)&lp->ucp,
+ sizeof(lp->ucp), MAP_NOCACHE);
+ lp->dev = devbusfn;
+ flush_dcache_range((unsigned long)lp,
+ (unsigned long)lp + sizeof(*lp));
+ dev->priv = lp;
+ sprintf(dev->name, "pcnet#%d", dev_nr);
+ lp->name = dev->name;
+ lp->enetaddr = dev->enetaddr;
+
+ /*
+ * Setup the PCI device.
+ */
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
+ lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
+
+ PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
+ lp->name, devbusfn, lp->iobase);
+
+ command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ pci_write_config_word(devbusfn, PCI_COMMAND, command);
+ pci_read_config_word(devbusfn, PCI_COMMAND, &status);
+ if ((status & command) != command) {
+ printf("%s: Couldn't enable IO access or Bus Mastering\n",
+ lp->name);
+ free(dev);
+ continue;
+ }
+
+ pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
+
+ /*
+ * Probe the PCnet chip.
+ */
+ if (pcnet_probe_common(lp) < 0) {
+ free(dev);
+ continue;
+ }
+
+ /*
+ * Setup device structure and register the driver.
+ */
+ dev->init = pcnet_init;
+ dev->halt = pcnet_halt;
+ dev->send = pcnet_send;
+ dev->recv = pcnet_recv;
+
+ eth_register(dev);
+ }
+
+ udelay(10 * 1000);
+
+ return dev_nr;
+}
+#else /* DM_ETH */
+static int pcnet_start(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+ return pcnet_init_common(priv);
+}
+
+static void pcnet_stop(struct udevice *dev)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ pcnet_halt_common(priv);
+}
+
+static int pcnet_send(struct udevice *dev, void *packet, int length)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = pcnet_send_common(priv, packet, length);
+
+ return ret ? 0 : -ETIMEDOUT;
}
+
+static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ return pcnet_recv_common(priv, packetp);
+}
+
+static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ pcnet_free_pkt_common(priv, length);
+
+ return 0;
+}
+
+static int pcnet_bind(struct udevice *dev)
+{
+ static int card_number;
+ char name[16];
+
+ sprintf(name, "pcnet#%u", card_number++);
+
+ return device_set_name(dev, name);
+}
+
+static int pcnet_probe(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct pcnet_priv *lp = dev_get_priv(dev);
+ u16 command, status;
+ u32 iobase;
+ int ret;
+
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
+ iobase &= ~0xf;
+
+ lp->uc = map_physmem((phys_addr_t)&lp->ucp,
+ sizeof(lp->ucp), MAP_NOCACHE);
+ lp->dev = dev;
+ lp->name = dev->name;
+ lp->enetaddr = plat->enetaddr;
+ lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
+
+ flush_dcache_range((unsigned long)lp,
+ (unsigned long)lp + sizeof(*lp));
+
+ command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ dm_pci_write_config16(dev, PCI_COMMAND, command);
+ dm_pci_read_config16(dev, PCI_COMMAND, &status);
+ if ((status & command) != command) {
+ printf("%s: Couldn't enable IO access or Bus Mastering\n",
+ lp->name);
+ return -EINVAL;
+ }
+
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
+
+ ret = pcnet_probe_common(lp);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct eth_ops pcnet_ops = {
+ .start = pcnet_start,
+ .send = pcnet_send,
+ .recv = pcnet_recv,
+ .stop = pcnet_stop,
+ .free_pkt = pcnet_free_pkt,
+};
+
+U_BOOT_DRIVER(eth_pcnet) = {
+ .name = "eth_pcnet",
+ .id = UCLASS_ETH,
+ .bind = pcnet_bind,
+ .probe = pcnet_probe,
+ .ops = &pcnet_ops,
+ .priv_auto_alloc_size = sizeof(struct pcnet_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
+};
+
+U_BOOT_PCI_DEVICE(eth_pcnet, supported);
+#endif
Default n, which means that the PHY state is not changed. To work
around the issues, change this setting to y.
+config RTL8201F_PHY_S700_RMII_TIMINGS
+ bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
+ depends on PHY_REALTEK
+ help
+ This provides an option to configure specific timing requirements (needed
+ for proper PHY operations) for the PHY module present on ACTION SEMI S700
+ based cubieboard7. Exact timing requiremnets seems to be SoC specific
+ (and it's undocumented) that comes from vendor code itself.
+
config PHY_SMSC
bool "Microchip(SMSC) Ethernet PHYs support"
config PHY_TI
bool "Texas Instruments Ethernet PHYs support"
+ ---help---
+ Adds PHY registration support for TI PHYs.
+
+config PHY_TI_DP83867
+ select PHY_TI
+ bool "Texas Instruments Ethernet DP83867 PHY support"
+ ---help---
+ Adds support for the TI DP83867 1Gbit PHY.
+
+config PHY_TI_GENERIC
+ select PHY_TI
+ bool "Texas Instruments Generic Ethernet PHYs support"
+ ---help---
+ Adds support for Generic TI PHYs that don't need special handling but
+ the PHY name is associated with a PHY ID.
config PHY_VITESSE
bool "Vitesse Ethernet PHYs support"
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
-obj-$(CONFIG_PHY_TI) += dp83867.o
+obj-$(CONFIG_PHY_TI) += ti_phy_init.o
+obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o
obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
#include <dm.h>
#include <dt-bindings/net/ti-dp83867.h>
+#include "ti_phy_init.h"
/* TI DP83867 */
#define DP83867_DEVADDR 0x1f
.shutdown = &genphy_shutdown,
};
-int phy_ti_init(void)
+int phy_dp83867_init(void)
{
phy_register(&DP83867_driver);
return 0;
.shutdown = &genphy_shutdown,
};
+static int ksz8061_config(struct phy_device *phydev)
+{
+ return phy_write(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
+}
+
+static struct phy_driver KSZ8061_driver = {
+ .name = "Micrel KSZ8061",
+ .uid = 0x00221570,
+ .mask = 0xfffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &ksz8061_config,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static int ksz8081_config(struct phy_device *phydev)
{
int ret;
phy_register(&KSZ804_driver);
phy_register(&KSZ8031_driver);
phy_register(&KSZ8051_driver);
+ phy_register(&KSZ8061_driver);
phy_register(&KSZ8081_driver);
phy_register(&KS8721_driver);
phy_register(&ksz8895_driver);
uint phy_mask,
phy_interface_t interface)
{
- int i;
struct phy_device *phydev;
-
+ int devad[] = {
+ /* Clause-22 */
+ MDIO_DEVAD_NONE,
+ /* Clause-45 */
+ MDIO_MMD_PMAPMD,
+ MDIO_MMD_WIS,
+ MDIO_MMD_PCS,
+ MDIO_MMD_PHYXS,
+ MDIO_MMD_VEND1,
+ };
+ int i, devad_cnt;
+
+ devad_cnt = sizeof(devad)/sizeof(int);
phydev = search_for_existing_phy(bus, phy_mask, interface);
if (phydev)
return phydev;
- /* Try Standard (ie Clause 22) access */
- /* Otherwise we have to try Clause 45 */
- for (i = 0; i < 5; i++) {
+ /* try different access clauses */
+ for (i = 0; i < devad_cnt; i++) {
phydev = create_phy_by_mask(bus, phy_mask,
- i ? i : MDIO_DEVAD_NONE, interface);
+ devad[i], interface);
if (IS_ERR(phydev))
return NULL;
if (phydev)
#define PHY_RTL8211x_FORCE_MASTER BIT(1)
#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
+#define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4)
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
#define MIIM_RTL8211F_RX_DELAY 0x8
#define MIIM_RTL8211F_LCR 0x10
+#define RTL8201F_RMSR 0x10
+
+#define RMSR_RX_TIMING_SHIFT BIT(2)
+#define RMSR_RX_TIMING_MASK GENMASK(7, 4)
+#define RMSR_RX_TIMING_VAL 0x4
+#define RMSR_TX_TIMING_SHIFT BIT(3)
+#define RMSR_TX_TIMING_MASK GENMASK(11, 8)
+#define RMSR_TX_TIMING_VAL 0x5
+
static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
int devaddr, int regnum)
{
return 0;
}
+static int rtl8210f_probe(struct phy_device *phydev)
+{
+#ifdef CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS
+ phydev->flags |= PHY_RTL8201F_S700_RMII_TIMINGS;
+#endif
+
+ return 0;
+}
+
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
{
return 0;
}
+/* RealTek RTL8201F */
+static int rtl8201f_config(struct phy_device *phydev)
+{
+ unsigned int reg;
+
+ if (phydev->flags & PHY_RTL8201F_S700_RMII_TIMINGS) {
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
+ 7);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR);
+ reg &= ~(RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK);
+ /* Set the needed Rx/Tx Timings for proper PHY operation */
+ reg |= (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT)
+ | (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT);
+ phy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
+ 0);
+ }
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static int rtl8211f_config(struct phy_device *phydev)
{
u16 reg;
.writeext = &rtl8211f_phy_extwrite,
};
+/* Support for RTL8201F PHY */
+static struct phy_driver RTL8201F_driver = {
+ .name = "RealTek RTL8201F 10/100Mbps Ethernet",
+ .uid = 0x1cc816,
+ .mask = 0xffffff,
+ .features = PHY_BASIC_FEATURES,
+ .probe = &rtl8210f_probe,
+ .config = &rtl8201f_config,
+ .startup = &rtl8211e_startup,
+ .shutdown = &genphy_shutdown,
+};
+
int phy_realtek_init(void)
{
phy_register(&RTL8211B_driver);
phy_register(&RTL8211E_driver);
phy_register(&RTL8211F_driver);
phy_register(&RTL8211DN_driver);
+ phy_register(&RTL8201F_driver);
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI Generic PHY Init to register any TI Ethernet PHYs
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright (C) 2019-20 Texas Instruments Inc.
+ */
+
+#include <phy.h>
+#include "ti_phy_init.h"
+
+#ifdef CONFIG_PHY_TI_GENERIC
+static struct phy_driver dp83822_driver = {
+ .name = "TI DP83822",
+ .uid = 0x2000a240,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83826nc_driver = {
+ .name = "TI DP83826NC",
+ .uid = 0x2000a110,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83826c_driver = {
+ .name = "TI DP83826C",
+ .uid = 0x2000a130,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825s_driver = {
+ .name = "TI DP83825S",
+ .uid = 0x2000a140,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825i_driver = {
+ .name = "TI DP83825I",
+ .uid = 0x2000a150,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825m_driver = {
+ .name = "TI DP83825M",
+ .uid = 0x2000a160,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver dp83825cs_driver = {
+ .name = "TI DP83825CS",
+ .uid = 0x2000a170,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+#endif /* CONFIG_PHY_TI_GENERIC */
+
+int phy_ti_init(void)
+{
+#ifdef CONFIG_PHY_TI_DP83867
+ phy_dp83867_init();
+#endif
+
+#ifdef CONFIG_PHY_TI_GENERIC
+ phy_register(&dp83822_driver);
+ phy_register(&dp83825s_driver);
+ phy_register(&dp83825i_driver);
+ phy_register(&dp83825m_driver);
+ phy_register(&dp83825cs_driver);
+ phy_register(&dp83826c_driver);
+ phy_register(&dp83826nc_driver);
+#endif
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * TI Generic Ethernet PHY
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright (C) 2019-20 Texas Instruments Inc.
+ */
+
+#ifndef _TI_GEN_PHY_H
+#define _TI_GEN_PHY_H
+
+int phy_dp83867_init(void);
+
+#endif /* _TI_GEN_PHY_H */
#include <common.h>
#include <cpu_func.h>
+#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <net.h>
#define DEBUG_TX 0 /* set to 1 to enable debug code */
#define DEBUG_RX 0 /* set to 1 to enable debug code */
-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+#ifdef CONFIG_DM_ETH
+#define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
+#define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
+#else
+#define bus_to_phys(devno, a) pci_mem_to_phys((pci_dev_t)(devno), (a))
+#define phys_to_bus(devno, a) pci_phys_to_mem((pci_dev_t)(devno), (a))
+#endif
/* Symbolic offsets to registers. */
/* Ethernet hardware address. */
#define RTL_STS_RXBADALIGN BIT(1)
#define RTL_STS_RXSTATUSOK BIT(0)
-static unsigned int cur_rx, cur_tx;
-static int ioaddr;
+struct rtl8139_priv {
+#ifndef CONFIG_DM_ETH
+ struct eth_device dev;
+ pci_dev_t devno;
+#else
+ struct udevice *devno;
+#endif
+ unsigned int rxstatus;
+ unsigned int cur_rx;
+ unsigned int cur_tx;
+ unsigned long ioaddr;
+ unsigned char enetaddr[6];
+};
/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
#define EE_READ_CMD 6
#define EE_ERASE_CMD 7
-static void rtl8139_eeprom_delay(uintptr_t regbase)
+static void rtl8139_eeprom_delay(struct rtl8139_priv *priv)
{
/*
* Delay between EEPROM clock transitions.
* No extra delay is needed with 33MHz PCI, but 66MHz may change this.
*/
- inl(regbase + RTL_REG_CFG9346);
+ inl(priv->ioaddr + RTL_REG_CFG9346);
}
-static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len)
+static int rtl8139_read_eeprom(struct rtl8139_priv *priv,
+ unsigned int location, unsigned int addr_len)
{
unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
- uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346;
+ uintptr_t ee_addr = priv->ioaddr + RTL_REG_CFG9346;
unsigned int retval = 0;
u8 dataval;
int i;
outb(EE_ENB & ~EE_CS, ee_addr);
outb(EE_ENB, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
outb(EE_ENB | dataval, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
}
outb(EE_ENB, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
for (i = 16; i > 0; i--) {
outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
retval <<= 1;
retval |= inb(ee_addr) & EE_DATA_READ;
outb(EE_ENB, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
}
/* Terminate the EEPROM access. */
outb(~EE_CS, ee_addr);
- rtl8139_eeprom_delay(ioaddr);
+ rtl8139_eeprom_delay(priv);
return retval;
}
(RX_FIFO_THRESH << 13) |
(RX_DMA_BURST << 8);
-static void rtl8139_set_rx_mode(struct eth_device *dev)
+static void rtl8139_set_rx_mode(struct rtl8139_priv *priv)
{
/* !IFF_PROMISC */
unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
RTL_REG_RXCONFIG_ACCEPTMULTICAST |
RTL_REG_RXCONFIG_ACCEPTMYPHYS;
- outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
+ outl(rtl8139_rx_config | rx_mode, priv->ioaddr + RTL_REG_RXCONFIG);
- outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0);
- outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4);
+ outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 0);
+ outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 4);
}
-static void rtl8139_hw_reset(struct eth_device *dev)
+static void rtl8139_hw_reset(struct rtl8139_priv *priv)
{
u8 reg;
int i;
- outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
+ outb(RTL_REG_CHIPCMD_CMDRESET, priv->ioaddr + RTL_REG_CHIPCMD);
/* Give the chip 10ms to finish the reset. */
for (i = 0; i < 100; i++) {
- reg = inb(ioaddr + RTL_REG_CHIPCMD);
+ reg = inb(priv->ioaddr + RTL_REG_CHIPCMD);
if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
break;
}
}
-static void rtl8139_reset(struct eth_device *dev)
+static void rtl8139_reset(struct rtl8139_priv *priv)
{
int i;
- cur_rx = 0;
- cur_tx = 0;
+ priv->cur_rx = 0;
+ priv->cur_tx = 0;
- rtl8139_hw_reset(dev);
+ rtl8139_hw_reset(priv);
for (i = 0; i < ETH_ALEN; i++)
- outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
+ outb(priv->enetaddr[i], priv->ioaddr + RTL_REG_MAC0 + i);
/* Must enable Tx/Rx before setting transfer thresholds! */
outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
- ioaddr + RTL_REG_CHIPCMD);
+ priv->ioaddr + RTL_REG_CHIPCMD);
/* accept no frames yet! */
- outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
- outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG);
+ outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
+ outl((TX_DMA_BURST << 8) | 0x03000000, priv->ioaddr + RTL_REG_TXCONFIG);
/*
* The Linux driver changes RTL_REG_CONFIG1 here to use a different
debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
- outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
+ outl(phys_to_bus(priv->devno, (int)rx_ring), priv->ioaddr + RTL_REG_RXBUF);
/*
* If we add multicast support, the RTL_REG_MAR0 register would have
* unicast.
*/
outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
- ioaddr + RTL_REG_CHIPCMD);
+ priv->ioaddr + RTL_REG_CHIPCMD);
- outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
+ outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
/* Start the chip's Tx and Rx process. */
- outl(0, ioaddr + RTL_REG_RXMISSED);
+ outl(0, priv->ioaddr + RTL_REG_RXMISSED);
- rtl8139_set_rx_mode(dev);
+ rtl8139_set_rx_mode(priv);
/* Disable all known interrupts by setting the interrupt mask. */
- outw(0, ioaddr + RTL_REG_INTRMASK);
+ outw(0, priv->ioaddr + RTL_REG_INTRMASK);
}
-static int rtl8139_send(struct eth_device *dev, void *packet, int length)
+static int rtl8139_send_common(struct rtl8139_priv *priv,
+ void *packet, int length)
{
unsigned int len = length;
unsigned long txstatus;
unsigned int status;
int i = 0;
- ioaddr = dev->iobase;
-
memcpy(tx_buffer, packet, length);
debug_cond(DEBUG_TX, "sending %d bytes\n", len);
tx_buffer[len++] = '\0';
flush_cache((unsigned long)tx_buffer, length);
- outl(phys_to_bus((unsigned long)tx_buffer),
- ioaddr + RTL_REG_TXADDR0 + cur_tx * 4);
+ outl(phys_to_bus(priv->devno, (unsigned long)tx_buffer),
+ priv->ioaddr + RTL_REG_TXADDR0 + priv->cur_tx * 4);
outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
- ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
+ priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
do {
- status = inw(ioaddr + RTL_REG_INTRSTATUS);
+ status = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
/*
* Only acknlowledge interrupt sources we can properly
* handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
*/
status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
RTL_REG_INTRSTATUS_PCIERR;
- outw(status, ioaddr + RTL_REG_INTRSTATUS);
+ outw(status, priv->ioaddr + RTL_REG_INTRSTATUS);
if (status)
break;
udelay(10);
} while (i++ < RTL_TIMEOUT);
- txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
+ txstatus = inl(priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
debug_cond(DEBUG_TX,
"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
10 * i, status, txstatus);
- rtl8139_reset(dev);
+ rtl8139_reset(priv);
return 0;
}
- cur_tx = (cur_tx + 1) % NUM_TX_DESC;
+ priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC;
debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
status, txstatus);
return length;
}
-static int rtl8139_recv(struct eth_device *dev)
+static int rtl8139_recv_common(struct rtl8139_priv *priv, unsigned char *rxdata,
+ uchar **packetp)
{
const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
RTL_REG_INTRSTATUS_RXOVERFLOW |
RTL_REG_INTRSTATUS_RXOK;
unsigned int rx_size, rx_status;
unsigned int ring_offs;
- unsigned int status;
int length = 0;
- ioaddr = dev->iobase;
-
- if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
+ if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
return 0;
- status = inw(ioaddr + RTL_REG_INTRSTATUS);
+ priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
/* See below for the rest of the interrupt acknowledges. */
- outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS);
+ outw(priv->rxstatus & ~rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
- debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status);
+ debug_cond(DEBUG_RX, "%s: int %hX ", __func__, priv->rxstatus);
- ring_offs = cur_rx % RX_BUF_LEN;
+ ring_offs = priv->cur_rx % RX_BUF_LEN;
/* ring_offs is guaranteed being 4-byte aligned */
rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
rx_size = rx_status >> 16;
(rx_size > ETH_FRAME_LEN + 4)) {
printf("rx error %hX\n", rx_status);
/* this clears all interrupts still pending */
- rtl8139_reset(dev);
+ rtl8139_reset(priv);
return 0;
}
/* Received a good packet */
length = rx_size - 4; /* no one cares about the FCS */
if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
- unsigned char rxdata[RX_BUF_LEN];
int semi_count = RX_BUF_LEN - ring_offs - 4;
memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
memcpy(&rxdata[semi_count], rx_ring,
rx_size - 4 - semi_count);
- net_process_received_packet(rxdata, length);
+ *packetp = rxdata;
debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
semi_count, rx_size - 4 - semi_count);
} else {
- net_process_received_packet(rx_ring + ring_offs + 4, length);
+ *packetp = rx_ring + ring_offs + 4;
debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
}
+
+ return length;
+}
+
+static int rtl8139_free_pkt_common(struct rtl8139_priv *priv, unsigned int len)
+{
+ const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
+ RTL_REG_INTRSTATUS_RXOVERFLOW |
+ RTL_REG_INTRSTATUS_RXOK;
+ unsigned int rx_size = len + 4;
+
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
- cur_rx = ROUND(cur_rx + rx_size + 4, 4);
- outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
+ priv->cur_rx = ROUND(priv->cur_rx + rx_size + 4, 4);
+ outw(priv->cur_rx - 16, priv->ioaddr + RTL_REG_RXBUFPTR);
/*
* See RTL8139 Programming Guide V0.1 for the official handling of
* Rx overflow situations. The document itself contains basically
* no usable information, except for a few exception handling rules.
*/
- outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS);
+ outw(priv->rxstatus & rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
- return length;
+ return 0;
}
-static int rtl8139_init(struct eth_device *dev, bd_t *bis)
+static int rtl8139_init_common(struct rtl8139_priv *priv)
{
- unsigned short *ap = (unsigned short *)dev->enetaddr;
- int addr_len, i;
u8 reg;
- ioaddr = dev->iobase;
-
/* Bring the chip out of low-power mode. */
- outb(0x00, ioaddr + RTL_REG_CONFIG1);
+ outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
- addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6;
- for (i = 0; i < 3; i++)
- *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len));
-
- rtl8139_reset(dev);
+ rtl8139_reset(priv);
- reg = inb(ioaddr + RTL_REG_MEDIASTATUS);
+ reg = inb(priv->ioaddr + RTL_REG_MEDIASTATUS);
if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
printf("Cable not connected or other link failure\n");
return -1;
return 0;
}
-static void rtl8139_stop(struct eth_device *dev)
+static void rtl8139_stop_common(struct rtl8139_priv *priv)
{
- ioaddr = dev->iobase;
+ rtl8139_hw_reset(priv);
+}
- rtl8139_hw_reset(dev);
+static void rtl8139_get_hwaddr(struct rtl8139_priv *priv)
+{
+ unsigned short *ap = (unsigned short *)priv->enetaddr;
+ int i, addr_len;
+
+ /* Bring the chip out of low-power mode. */
+ outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
+
+ addr_len = rtl8139_read_eeprom(priv, 0, 8) == 0x8129 ? 8 : 6;
+ for (i = 0; i < 3; i++)
+ *ap++ = le16_to_cpu(rtl8139_read_eeprom(priv, i + 7, addr_len));
}
-static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
- int join)
+static void rtl8139_name(char *str, int card_number)
{
- return 0;
+ sprintf(str, "RTL8139#%u", card_number);
}
static struct pci_device_id supported[] = {
- { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 },
- { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 },
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139) },
+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139) },
{ }
};
+#ifndef CONFIG_DM_ETH
+static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
+ int join)
+{
+ return 0;
+}
+
+static int rtl8139_init(struct eth_device *dev, bd_t *bis)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+
+ return rtl8139_init_common(priv);
+}
+
+static void rtl8139_stop(struct eth_device *dev)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+
+ return rtl8139_stop_common(priv);
+}
+
+static int rtl8139_send(struct eth_device *dev, void *packet, int length)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+
+ return rtl8139_send_common(priv, packet, length);
+}
+
+static int rtl8139_recv(struct eth_device *dev)
+{
+ struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
+ unsigned char rxdata[RX_BUF_LEN];
+ uchar *packet;
+ int ret;
+
+ ret = rtl8139_recv_common(priv, rxdata, &packet);
+ if (ret) {
+ net_process_received_packet(packet, ret);
+ rtl8139_free_pkt_common(priv, ret);
+ }
+
+ return ret;
+}
+
int rtl8139_initialize(bd_t *bis)
{
+ struct rtl8139_priv *priv;
struct eth_device *dev;
int card_number = 0;
pci_dev_t devno;
debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
- dev = (struct eth_device *)malloc(sizeof(*dev));
- if (!dev) {
+ priv = calloc(1, sizeof(*priv));
+ if (!priv) {
printf("Can not allocate memory of rtl8139\n");
break;
}
- memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "RTL8139#%d", card_number);
+ priv->devno = devno;
+ priv->ioaddr = (unsigned long)bus_to_phys(devno, iobase);
+
+ dev = &priv->dev;
+
+ rtl8139_name(dev->name, card_number);
- dev->priv = (void *)devno;
- dev->iobase = (int)bus_to_phys(iobase);
+ dev->iobase = priv->ioaddr; /* Non-DM compatibility */
dev->init = rtl8139_init;
dev->halt = rtl8139_stop;
dev->send = rtl8139_send;
dev->recv = rtl8139_recv;
dev->mcast = rtl8139_bcast_addr;
+ rtl8139_get_hwaddr(priv);
+
+ /* Non-DM compatibility */
+ memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
+
eth_register(dev);
card_number++;
return card_number;
}
+#else /* DM_ETH */
+static int rtl8139_start(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+ return rtl8139_init_common(priv);
+}
+
+static void rtl8139_stop(struct udevice *dev)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ rtl8139_stop_common(priv);
+}
+
+static int rtl8139_send(struct udevice *dev, void *packet, int length)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = rtl8139_send_common(priv, packet, length);
+
+ return ret ? 0 : -ETIMEDOUT;
+}
+
+static int rtl8139_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+ static unsigned char rxdata[RX_BUF_LEN];
+
+ return rtl8139_recv_common(priv, rxdata, packetp);
+}
+
+static int rtl8139_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ rtl8139_free_pkt_common(priv, length);
+
+ return 0;
+}
+
+static int rtl8139_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+ rtl8139_reset(priv);
+
+ return 0;
+}
+
+static int rtl8139_read_rom_hwaddr(struct udevice *dev)
+{
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+
+ rtl8139_get_hwaddr(priv);
+
+ return 0;
+}
+
+static int rtl8139_bind(struct udevice *dev)
+{
+ static int card_number;
+ char name[16];
+
+ rtl8139_name(name, card_number++);
+
+ return device_set_name(dev, name);
+}
+
+static int rtl8139_probe(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct rtl8139_priv *priv = dev_get_priv(dev);
+ u32 iobase;
+
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
+ iobase &= ~0xf;
+
+ debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
+
+ priv->devno = dev;
+ priv->ioaddr = (unsigned long)bus_to_phys(dev, iobase);
+
+ rtl8139_get_hwaddr(priv);
+ memcpy(plat->enetaddr, priv->enetaddr, sizeof(priv->enetaddr));
+
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
+
+ return 0;
+}
+
+static const struct eth_ops rtl8139_ops = {
+ .start = rtl8139_start,
+ .send = rtl8139_send,
+ .recv = rtl8139_recv,
+ .stop = rtl8139_stop,
+ .free_pkt = rtl8139_free_pkt,
+ .write_hwaddr = rtl8139_write_hwaddr,
+ .read_rom_hwaddr = rtl8139_read_rom_hwaddr,
+};
+
+U_BOOT_DRIVER(eth_rtl8139) = {
+ .name = "eth_rtl8139",
+ .id = UCLASS_ETH,
+ .bind = rtl8139_bind,
+ .probe = rtl8139_probe,
+ .ops = &rtl8139_ops,
+ .priv_auto_alloc_size = sizeof(struct rtl8139_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
+#endif
/*_TBICSRBit*/
TBILinkOK = 0x02000000,
+
+ /* FuncEvent/Misc */
+ RxDv_Gated_En = 0x80000,
};
static struct {
return ret;
}
+ /*
+ * WAR for DHCP failure after rebooting from kernel.
+ * Clear RxDv_Gated_En bit which was set by kernel driver.
+ * Without this, U-Boot can't get an IP via DHCP.
+ * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
+ * the r8169.c kernel driver.
+ */
+
+ u32 val = RTL_R32(FuncEvent);
+ debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
+ val &= ~RxDv_Gated_En;
+ RTL_W32(FuncEvent, val);
+
return 0;
}
printf(DRIVERNAME ": MAC %pM\n", m);
}
+static bool smc911x_read_mac_address(struct smc911x_priv *priv)
+{
+ u32 addrh, addrl;
+
+ /* address is obtained from optional eeprom */
+ addrh = smc911x_get_mac_csr(priv, ADDRH);
+ addrl = smc911x_get_mac_csr(priv, ADDRL);
+ if (addrl == 0xffffffff && addrh == 0x0000ffff)
+ return false;
+
+ priv->enetaddr[0] = addrl;
+ priv->enetaddr[1] = addrl >> 8;
+ priv->enetaddr[2] = addrl >> 16;
+ priv->enetaddr[3] = addrl >> 24;
+ priv->enetaddr[4] = addrh;
+ priv->enetaddr[5] = addrh >> 8;
+
+ return true;
+}
+
static int smc911x_eth_phy_read(struct smc911x_priv *priv,
u8 phy, u8 reg, u16 *val)
{
int smc911x_initialize(u8 dev_num, int base_addr)
{
- unsigned long addrl, addrh;
struct smc911x_priv *priv;
int ret;
goto err_detect;
}
- addrh = smc911x_get_mac_csr(priv, ADDRH);
- addrl = smc911x_get_mac_csr(priv, ADDRL);
- if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
- /* address is obtained from optional eeprom */
- priv->enetaddr[0] = addrl;
- priv->enetaddr[1] = addrl >> 8;
- priv->enetaddr[2] = addrl >> 16;
- priv->enetaddr[3] = addrl >> 24;
- priv->enetaddr[4] = addrh;
- priv->enetaddr[5] = addrh >> 8;
+ if (smc911x_read_mac_address(priv))
memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
- }
priv->dev.init = smc911x_init;
priv->dev.halt = smc911x_halt;
return ret ? ret : -EAGAIN;
}
+static int smc911x_read_rom_hwaddr(struct udevice *dev)
+{
+ struct smc911x_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ if (!smc911x_read_mac_address(priv))
+ return -ENODEV;
+
+ memcpy(pdata->enetaddr, priv->enetaddr, sizeof(pdata->enetaddr));
+
+ return 0;
+}
+
static int smc911x_bind(struct udevice *dev)
{
return device_set_name(dev, dev->name);
static int smc911x_probe(struct udevice *dev)
{
struct smc911x_priv *priv = dev_get_priv(dev);
- unsigned long addrh, addrl;
int ret;
/* Try to detect chip. Will fail if not present. */
if (ret)
return ret;
- addrh = smc911x_get_mac_csr(priv, ADDRH);
- addrl = smc911x_get_mac_csr(priv, ADDRL);
- if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
- /* address is obtained from optional eeprom */
- priv->enetaddr[0] = addrl;
- priv->enetaddr[1] = addrl >> 8;
- priv->enetaddr[2] = addrl >> 16;
- priv->enetaddr[3] = addrl >> 24;
- priv->enetaddr[4] = addrh;
- priv->enetaddr[5] = addrh >> 8;
- }
+ smc911x_read_rom_hwaddr(dev);
return 0;
}
.send = smc911x_send,
.recv = smc911x_recv,
.stop = smc911x_stop,
+ .read_rom_hwaddr = smc911x_read_rom_hwaddr,
};
static const struct udevice_id smc911x_ids[] = {
#include <cpsw.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
+#include <linux/compiler.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
}
#define DEFINE_ALE_FIELD(name, start, bits) \
-static inline int cpsw_ale_get_##name(u32 *ale_entry) \
+static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry) \
{ \
return cpsw_ale_get_field(ale_entry, start, bits); \
} \
-static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
+static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
{ \
cpsw_ale_set_field(ale_entry, start, bits, value); \
}
static int axiemac_phy_init(struct udevice *dev)
{
u16 phyreg;
- u32 i, ret;
+ int i;
+ u32 ret;
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
struct phy_device *phydev;
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
#ifdef CONFIG_ARM64
+ if (priv->phydev->phy_id != PHY_FIXED_ID)
writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
®s->pcscntrl);
+ else
+ writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ ®s->pcscntrl);
#endif
}
int rockchip_pcie_phy_get(struct udevice *dev);
-inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
+static inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
{
return pcie->phy;
}
-inline
-struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
+static inline struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
{
return (struct rockchip_pcie_phy_ops *)phy->ops;
}
#include <linux/err.h>
#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT BIT(0)
+#define OMAP_USB2_DISABLE_CHG_DET BIT(1)
#define OMAP_DEV_PHY_PD BIT(0)
#define OMAP_USB2_PHY_PD BIT(28)
#define AM654_USB2_VBUS_DET_EN BIT(5)
#define AM654_USB2_VBUSVALID_DET_EN BIT(4)
+#define USB2PHY_CHRG_DET 0x14
+#define USB2PHY_USE_CHG_DET_REG BIT(29)
+#define USB2PHY_DIS_CHG_DET BIT(28)
+
DECLARE_GLOBAL_DATA_PTR;
struct omap_usb2_phy {
writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1);
}
+ if (priv->flags & OMAP_USB2_DISABLE_CHG_DET) {
+ val = readl(priv->phy_base + USB2PHY_CHRG_DET);
+ val |= USB2PHY_USE_CHG_DET_REG | USB2PHY_DIS_CHG_DET;
+ writel(val, priv->phy_base + USB2PHY_CHRG_DET);
+ }
+
return 0;
}
if (!data)
return -EINVAL;
- if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
- priv->phy_base = dev_read_addr_ptr(dev);
+ priv->phy_base = dev_read_addr_ptr(dev);
- if (!priv->phy_base)
- return -EINVAL;
+ if (!priv->phy_base)
+ return -EINVAL;
+
+ if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT)
priv->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
- }
+
+ /*
+ * AM654x PG1.0 has a silicon bug that D+ is pulled high after
+ * POR, which could cause enumeration failure with some USB hubs.
+ * Disabling the USB2_PHY Charger Detect function will put D+
+ * into the normal state.
+ *
+ * Using property "ti,dis-chg-det-quirk" in the DT usb2-phy node
+ * to enable this workaround for AM654x PG1.0.
+ */
+ if (dev_read_bool(dev, "ti,dis-chg-det-quirk"))
+ priv->flags |= OMAP_USB2_DISABLE_CHG_DET;
regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-phy-power");
if (!IS_ERR(regmap)) {
}
priv->base_reg = dev_read_addr_ptr(dev);
- if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
+ if (!priv->base_reg) {
debug("%s: Failed to get base address\n", __func__);
return -EINVAL;
}
int ret;
priv->base = dev_read_addr_ptr(dev);
- if (priv->base == (void *)FDT_ADDR_T_NONE)
+ if (!priv->base)
return -EINVAL;
priv->soc = soc;
return dm_i2c_reg_write(dev_get_parent(dev), offset, val);
}
-static int stmfx_gpio_get(struct udevice *dev, unsigned int offset)
+static int stmfx_read_reg(struct udevice *dev, u8 reg_base, uint offset)
{
- u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
+ u8 reg = reg_base + get_reg(offset);
u32 mask = get_mask(offset);
int ret;
ret = stmfx_read(dev, reg);
+ if (ret < 0)
+ return ret;
return ret < 0 ? ret : !!(ret & mask);
}
+static int stmfx_write_reg(struct udevice *dev, u8 reg_base, uint offset,
+ uint val)
+{
+ u8 reg = reg_base + get_reg(offset);
+ u32 mask = get_mask(offset);
+ int ret;
+
+ ret = stmfx_read(dev, reg);
+ if (ret < 0)
+ return ret;
+ ret = (ret & ~mask) | (val ? mask : 0);
+
+ return stmfx_write(dev, reg, ret);
+}
+
+static int stmfx_conf_set_pupd(struct udevice *dev, unsigned int offset,
+ uint pupd)
+{
+ return stmfx_write_reg(dev, STMFX_REG_GPIO_PUPD, offset, pupd);
+}
+
+static int stmfx_conf_get_pupd(struct udevice *dev, unsigned int offset)
+{
+ return stmfx_read_reg(dev, STMFX_REG_GPIO_PUPD, offset);
+}
+
+static int stmfx_conf_set_type(struct udevice *dev, unsigned int offset,
+ uint type)
+{
+ return stmfx_write_reg(dev, STMFX_REG_GPIO_TYPE, offset, type);
+}
+
+static int stmfx_conf_get_type(struct udevice *dev, unsigned int offset)
+{
+ return stmfx_read_reg(dev, STMFX_REG_GPIO_TYPE, offset);
+}
+
+static int stmfx_gpio_get(struct udevice *dev, unsigned int offset)
+{
+ return stmfx_read_reg(dev, STMFX_REG_GPIO_STATE, offset);
+}
+
static int stmfx_gpio_set(struct udevice *dev, unsigned int offset, int value)
{
u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
static int stmfx_gpio_get_function(struct udevice *dev, unsigned int offset)
{
- u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
- u32 mask = get_mask(offset);
- int ret;
-
- ret = stmfx_read(dev, reg);
+ int ret = stmfx_read_reg(dev, STMFX_REG_GPIO_DIR, offset);
if (ret < 0)
return ret;
/* On stmfx, gpio pins direction is (0)input, (1)output. */
- return ret & mask ? GPIOF_OUTPUT : GPIOF_INPUT;
+ return ret ? GPIOF_OUTPUT : GPIOF_INPUT;
}
static int stmfx_gpio_direction_input(struct udevice *dev, unsigned int offset)
{
- u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
- u32 mask = get_mask(offset);
- int ret;
+ return stmfx_write_reg(dev, STMFX_REG_GPIO_DIR, offset, 0);
+}
- ret = stmfx_read(dev, reg);
+static int stmfx_gpio_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ int ret = stmfx_gpio_set(dev, offset, value);
if (ret < 0)
return ret;
- ret &= ~mask;
+ return stmfx_write_reg(dev, STMFX_REG_GPIO_DIR, offset, 1);
+}
- return stmfx_write(dev, reg, ret & ~mask);
+static int stmfx_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
+ ulong flags)
+{
+ int ret = -ENOTSUPP;
+
+ if (flags & GPIOD_IS_OUT) {
+ if (flags & GPIOD_OPEN_SOURCE)
+ return -ENOTSUPP;
+ if (flags & GPIOD_OPEN_DRAIN)
+ ret = stmfx_conf_set_type(dev, offset, 0);
+ else /* PUSH-PULL */
+ ret = stmfx_conf_set_type(dev, offset, 1);
+ if (ret)
+ return ret;
+ ret = stmfx_gpio_direction_output(dev, offset,
+ GPIOD_FLAGS_OUTPUT(flags));
+ } else if (flags & GPIOD_IS_IN) {
+ ret = stmfx_gpio_direction_input(dev, offset);
+ if (ret)
+ return ret;
+ if (flags & GPIOD_PULL_UP) {
+ ret = stmfx_conf_set_type(dev, offset, 1);
+ if (ret)
+ return ret;
+ ret = stmfx_conf_set_pupd(dev, offset, 1);
+ } else if (flags & GPIOD_PULL_DOWN) {
+ ret = stmfx_conf_set_type(dev, offset, 1);
+ if (ret)
+ return ret;
+ ret = stmfx_conf_set_pupd(dev, offset, 0);
+ }
+ }
+
+ return ret;
}
-static int stmfx_gpio_direction_output(struct udevice *dev,
- unsigned int offset, int value)
+static int stmfx_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
+ ulong *flags)
{
- u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
- u32 mask = get_mask(offset);
+ ulong dir_flags = 0;
int ret;
- ret = stmfx_gpio_set(dev, offset, value);
- if (ret < 0)
- return ret;
-
- ret = stmfx_read(dev, reg);
- if (ret < 0)
- return ret;
+ if (stmfx_gpio_get_function(dev, offset) == GPIOF_OUTPUT) {
+ dir_flags |= GPIOD_IS_OUT;
+ ret = stmfx_conf_get_type(dev, offset);
+ if (ret < 0)
+ return ret;
+ if (ret == 0)
+ dir_flags |= GPIOD_OPEN_DRAIN;
+ /* 1 = push-pull (default), open source not supported */
+ ret = stmfx_gpio_get(dev, offset);
+ if (ret < 0)
+ return ret;
+ if (ret)
+ dir_flags |= GPIOD_IS_OUT_ACTIVE;
+ } else {
+ dir_flags |= GPIOD_IS_IN;
+ ret = stmfx_conf_get_type(dev, offset);
+ if (ret < 0)
+ return ret;
+ if (ret == 1) {
+ ret = stmfx_conf_get_pupd(dev, offset);
+ if (ret < 0)
+ return ret;
+ if (ret == 1)
+ dir_flags |= GPIOD_PULL_UP;
+ else
+ dir_flags |= GPIOD_PULL_DOWN;
+ }
+ }
+ *flags = dir_flags;
- return stmfx_write(dev, reg, ret | mask);
+ return 0;
}
static int stmfx_gpio_probe(struct udevice *dev)
.get_function = stmfx_gpio_get_function,
.direction_input = stmfx_gpio_direction_input,
.direction_output = stmfx_gpio_direction_output,
+ .set_dir_flags = stmfx_gpio_set_dir_flags,
+ .get_dir_flags = stmfx_gpio_get_dir_flags,
};
U_BOOT_DRIVER(stmfx_gpio) = {
{ "output-low", PIN_CONFIG_OUTPUT, 0 },
};
-static int stmfx_pinctrl_set_pupd(struct udevice *dev,
- unsigned int pin, u32 pupd)
-{
- u8 reg = STMFX_REG_GPIO_PUPD + get_reg(pin);
- u32 mask = get_mask(pin);
- int ret;
-
- ret = stmfx_read(dev, reg);
- if (ret < 0)
- return ret;
- ret = (ret & ~mask) | (pupd ? mask : 0);
-
- return stmfx_write(dev, reg, ret);
-}
-
-static int stmfx_pinctrl_set_type(struct udevice *dev,
- unsigned int pin, u32 type)
-{
- u8 reg = STMFX_REG_GPIO_TYPE + get_reg(pin);
- u32 mask = get_mask(pin);
- int ret;
-
- ret = stmfx_read(dev, reg);
- if (ret < 0)
- return ret;
- ret = (ret & ~mask) | (type ? mask : 0);
-
- return stmfx_write(dev, reg, ret);
-}
-
static int stmfx_pinctrl_conf_set(struct udevice *dev, unsigned int pin,
unsigned int param, unsigned int arg)
{
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_DRIVE_PUSH_PULL:
- ret = stmfx_pinctrl_set_type(dev, pin, 0);
+ ret = stmfx_conf_set_type(dev, pin, 0);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
- ret = stmfx_pinctrl_set_type(dev, pin, 1);
+ ret = stmfx_conf_set_type(dev, pin, 1);
if (ret)
return ret;
- ret = stmfx_pinctrl_set_pupd(dev, pin, 0);
+ ret = stmfx_conf_set_pupd(dev, pin, 0);
break;
case PIN_CONFIG_BIAS_PULL_UP:
- ret = stmfx_pinctrl_set_type(dev, pin, 1);
+ ret = stmfx_conf_set_type(dev, pin, 1);
if (ret)
return ret;
- ret = stmfx_pinctrl_set_pupd(dev, pin, 1);
+ ret = stmfx_conf_set_pupd(dev, pin, 1);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- ret = stmfx_pinctrl_set_type(dev, pin, 1);
+ ret = stmfx_conf_set_type(dev, pin, 1);
break;
case PIN_CONFIG_OUTPUT:
ret = stmfx_gpio_direction_output(plat->gpio, pin, arg);
return pin_name;
}
+static const char *stmfx_pinctrl_get_pin_conf(struct udevice *dev,
+ unsigned int pin, int func)
+{
+ int pupd, type;
+
+ type = stmfx_conf_get_type(dev, pin);
+ if (type < 0)
+ return "";
+
+ if (func == GPIOF_OUTPUT) {
+ if (type)
+ return "drive-open-drain";
+ else
+ return ""; /* default: push-pull*/
+ }
+ if (!type)
+ return ""; /* default: bias-disable*/
+
+ pupd = stmfx_conf_get_pupd(dev, pin);
+ if (pupd < 0)
+ return "";
+
+ if (pupd)
+ return "bias-pull-up";
+ else
+ return "bias-pull-down";
+}
+
static int stmfx_pinctrl_get_pin_muxing(struct udevice *dev,
unsigned int selector,
char *buf, int size)
if (func < 0)
return func;
- snprintf(buf, size, "%s", func == GPIOF_INPUT ? "input" : "output");
+ snprintf(buf, size, "%s ", func == GPIOF_INPUT ? "input" : "output");
+
+ strncat(buf, stmfx_pinctrl_get_pin_conf(dev, selector, func), size);
return 0;
}
"alt function",
};
+static const char * const pinmux_output[] = {
+ [STM32_GPIO_PUPD_NO] = "bias-disable",
+ [STM32_GPIO_PUPD_UP] = "bias-pull-up",
+ [STM32_GPIO_PUPD_DOWN] = "bias-pull-down",
+};
+
+static const char * const pinmux_input[] = {
+ [STM32_GPIO_OTYPE_PP] = "drive-push-pull",
+ [STM32_GPIO_OTYPE_OD] = "drive-open-drain",
+};
+
static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
int size)
{
struct udevice *gpio_dev;
+ struct stm32_gpio_priv *priv;
const char *label;
int mode;
int af_num;
unsigned int gpio_idx;
+ u32 pupd, otype;
/* look up for the bank which owns the requested pin */
gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
return -ENODEV;
mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
-
dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
selector, gpio_idx, mode);
+ priv = dev_get_priv(gpio_dev);
switch (mode) {
snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
break;
case GPIOF_OUTPUT:
+ pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) &
+ PUPD_MASK;
+ snprintf(buf, size, "%s %s %s",
+ pinmux_mode[mode], pinmux_output[pupd],
+ label ? label : "");
+ break;
case GPIOF_INPUT:
- snprintf(buf, size, "%s %s",
- pinmux_mode[mode], label ? label : "");
+ otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
+ snprintf(buf, size, "%s %s %s",
+ pinmux_mode[mode], pinmux_input[otype],
+ label ? label : "");
break;
}
u32 val;
int ret;
- clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ | STM32_ENVR,
- enable ? STM32_ENVR : STM32_HIZ);
+ if (enable && !(readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR)) {
+ /*
+ * There maybe an overshoot:
+ * - when disabling, then re-enabling vrefbuf too quickly
+ * - or upon platform reset as external capacitor maybe slow
+ * discharging (VREFBUF is HiZ at reset by default).
+ * So force active discharge (HiZ=0) for 1ms before enabling.
+ */
+ clrbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ);
+ udelay(1000);
+ }
+
+ clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR,
+ enable ? STM32_ENVR : 0);
if (!enable)
return 0;
#define ADDR_INVALID 0xFFFFFFFF
+#define PATTERN_DEFAULT "-"
+
DECLARE_GLOBAL_DATA_PTR;
static int get_bufsize(char *string, int argc, char *argv[], int arg_nb,
- size_t *bufsize, size_t default_size)
+ size_t *bufsize, size_t default_size, size_t min_size)
{
unsigned long value;
arg_nb, argv[arg_nb]);
return -1;
}
- if (value > STM32_DDR_SIZE || value == 0) {
- sprintf(string, "invalid size %s", argv[arg_nb]);
+ if (value > STM32_DDR_SIZE || value < min_size) {
+ sprintf(string, "invalid size %s (min=%d)",
+ argv[arg_nb], min_size);
return -1;
}
- if (value & 0x3) {
- sprintf(string, "unaligned size %s",
- argv[arg_nb]);
+ if (value & (min_size - 1)) {
+ sprintf(string, "unaligned size %s (min=%d)",
+ argv[arg_nb], min_size);
return -1;
}
*bufsize = value;
unsigned long value;
if (argc > arg_nb) {
+ if (!strcmp(argv[arg_nb], PATTERN_DEFAULT)) {
+ *pattern = default_pattern;
+ return 0;
+ }
if (strict_strtoul(argv[arg_nb], 16, &value) < 0) {
sprintf(string, "invalid %d parameter %s",
arg_nb, argv[arg_nb]);
u32 bufsize;
u32 error;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, STM32_DDR_SIZE, 4))
return TEST_ERROR;
if (!is_power_of_2(bufsize)) {
sprintf(string, "size 0x%x is not a power of 2",
if (get_addr(string, argc, argv, 1, &addr))
return TEST_ERROR;
+ printf("running at 0x%08x length 0x%x\n", addr, bufsize);
error = (u32)addressbus((u32 *)addr, bufsize);
if (error) {
sprintf(string, "0x%x: error for address 0x%x",
size_t bufsize;
u32 error;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4))
return TEST_ERROR;
if (get_addr(string, argc, argv, 1, &addr))
return TEST_ERROR;
u32 error = 0;
u32 data;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4))
return TEST_ERROR;
if (get_addr(string, argc, argv, 1, &addr))
return TEST_ERROR;
u32 error = 0;
unsigned int seed;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 8 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 8))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
int i;
enum test_result res = TEST_PASSED;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 128))
return TEST_ERROR;
if (get_pattern(string, argc, argv, 1, &pattern, 0xFFFFFFFF))
return TEST_ERROR;
enum test_result res = TEST_PASSED, pattern_res;
int i, bus_width;
const u32 **patterns;
- u32 bufsize;
+ u32 bufsize, addr;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 128))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 1, &addr))
return TEST_ERROR;
switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
}
printf("running test pattern at 0x%08x length 0x%x width = %d\n",
- STM32_DDR_BASE, bufsize, bus_width);
+ addr, bufsize, bus_width);
patterns =
(const u32 **)(bus_width == 16 ? patterns_x16 : patterns_x32);
for (i = 0; i < NB_PATTERN; i++) {
printf("test data pattern %s:", patterns_comments[i]);
- pattern_res = test_loop(patterns[i], (u32 *)STM32_DDR_BASE,
- bufsize);
+ pattern_res = test_loop(patterns[i], (u32 *)addr, bufsize);
if (pattern_res != TEST_PASSED) {
printf("Failed\n");
return pattern_res;
u32 checkboard[2] = {0x55555555, 0xAAAAAAAA};
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 8))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
u32 bufsize, nb_loop, loop = 0, addr, value;
int i;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
u32 bufsize, nb_loop, loop = 0, addr, value;
int i;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
u32 bufsize, nb_loop, loop = 0, addr, value;
int i;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
u32 bufsize, nb_loop, loop = 0, addr, bitspread[4];
int i, j;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 32))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
u32 bitflip[4];
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 32))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
char *string, int argc, char *argv[])
{
enum test_result res = TEST_PASSED, result;
- int i, nb_error = 0;
+ int i, j, nb_error = 0, len;
u32 loop = 0, nb_loop;
+ int argc_test;
+ char *argv_test[4];
+ char loop_string[] = "1";
+ char pattern_string[] = PATTERN_DEFAULT;
+ u32 *addr;
if (get_nb_loop(string, argc, argv, 0, &nb_loop, 1))
return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, (u32 *)&addr))
+ return TEST_ERROR;
+
while (!nb_error) {
/* execute all the test except the lasts which are infinite */
for (i = 1; i < test_nb - NB_TEST_INFINITE; i++) {
+ argc_test = 0;
+ j = 0;
+ len = strlen(test[i].usage);
+ if (argc > 1 && j < len &&
+ !strncmp("[size]", &test[i].usage[j], 6)) {
+ argv_test[argc_test++] = argv[1];
+ j += 7;
+ }
+ if (argc > 2) {
+ if (j < len &&
+ !strncmp("[loop]", &test[i].usage[j], 6)) {
+ argv_test[argc_test++] = loop_string;
+ j += 7;
+ }
+ if (j < len &&
+ !strncmp("[pattern]", &test[i].usage[j],
+ 9)) {
+ argv_test[argc_test++] = pattern_string;
+ j += 10;
+ }
+ if (j < len &&
+ !strncmp("[addr]", &test[i].usage[j], 6)) {
+ argv_test[argc_test++] = argv[2];
+ j += 7;
+ }
+ }
printf("execute %d:%s\n", (int)i, test[i].name);
- result = test[i].fct(ctl, phy, string, 0, NULL);
+ result = test[i].fct(ctl, phy, string,
+ argc_test, argv_test);
printf("result %d:%s = ", (int)i, test[i].name);
if (result != TEST_PASSED) {
nb_error++;
****************************************************************/
const struct test_desc test[] = {
- {test_all, "All", "[loop]", "Execute all tests", 1 },
+ {test_all, "All", "[loop] [size] [addr]", "Execute all tests", 3 },
{test_databus, "Simple DataBus", "[addr]",
"Verifies each data line by walking 1 on fixed address",
1
"Verifies r/w and memcopy(burst for pseudo random value.",
3
},
- {test_freq_pattern, "FrequencySelectivePattern", "[size]",
+ {test_freq_pattern, "FrequencySelectivePattern", "[size] [addr]",
"write & test patterns: Mostly Zero, Mostly One and F/n",
- 1
+ 2
},
{test_blockseq, "BlockSequential", "[size] [loop] [addr]",
"test incremental pattern",
help
Support for reset controller on i.MX7/8 SoCs.
+config RESET_SYSCON
+ bool "Enable generic syscon reset driver support"
+ depends on DM_RESET
+ help
+ Support generic syscon mapped register reset devices.
endmenu
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+struct syscon_reset_priv {
+ struct regmap *regmap;
+ uint offset;
+ uint mask;
+ bool assert_high;
+};
+
+static int syscon_reset_request(struct reset_ctl *rst)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+ if (BIT(rst->id) & priv->mask)
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static int syscon_reset_assert(struct reset_ctl *rst)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+ return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+ priv->assert_high ? BIT(rst->id) : 0);
+}
+
+static int syscon_reset_deassert(struct reset_ctl *rst)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+ return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+ priv->assert_high ? 0 : BIT(rst->id));
+}
+
+static const struct reset_ops syscon_reset_ops = {
+ .request = syscon_reset_request,
+ .rst_assert = syscon_reset_assert,
+ .rst_deassert = syscon_reset_deassert,
+};
+
+int syscon_reset_probe(struct udevice *dev)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(dev);
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
+ if (IS_ERR(priv->regmap))
+ return -ENODEV;
+
+ priv->offset = dev_read_u32_default(dev, "offset", 0);
+ priv->mask = dev_read_u32_default(dev, "mask", 0);
+ priv->assert_high = dev_read_u32_default(dev, "assert-high", true);
+
+ return 0;
+}
+
+static const struct udevice_id syscon_reset_ids[] = {
+ { .compatible = "syscon-reset" },
+ { },
+};
+
+U_BOOT_DRIVER(syscon_reset) = {
+ .name = "syscon_reset",
+ .id = UCLASS_RESET,
+ .of_match = syscon_reset_ids,
+ .probe = syscon_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct syscon_reset_priv),
+ .ops = &syscon_reset_ops,
+};
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# There are many options which enable SPI, so make this library available
-ifdef CONFIG_DM_SPI
+ifdef CONFIG_$(SPL_TPL_)DM_SPI
obj-y += spi-uclass.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
-obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
* eSPI controller driver.
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
* Author: Mingkai Hu (Mingkai.hu@freescale.com)
+ * Chuanhua Han (chuanhua.han@nxp.com)
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/immap_85xx.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <dm/platform_data/fsl_espi.h>
struct fsl_spi_slave {
struct spi_slave slave;
ccsr_espi_t *espi;
+ u32 speed_hz;
+ unsigned int cs;
unsigned int div16;
unsigned int pm;
int tx_timeout;
#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
#define US_PER_SECOND 1000000UL
+/* default SCK frequency, unit: HZ */
+#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000
+
#define ESPI_MAX_CS_NUM 4
#define ESPI_FIFO_WIDTH_BIT 32
#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct fsl_spi_slave *fsl;
- sys_info_t sysinfo;
- unsigned long spibrg = 0;
- unsigned long spi_freq = 0;
- unsigned char pm = 0;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
- if (!fsl)
- return NULL;
-
- fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
- fsl->mode = mode;
- fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
-
- /* Set eSPI BRG clock source */
- get_sys_info(&sysinfo);
- spibrg = sysinfo.freq_systembus / 2;
- fsl->div16 = 0;
- if ((spibrg / max_hz) > 32) {
- fsl->div16 = ESPI_CSMODE_DIV16;
- pm = spibrg / (max_hz * 16 * 2);
- if (pm > 16) {
- pm = 16;
- debug("Requested speed is too low: %d Hz, %ld Hz "
- "is used.\n", max_hz, spibrg / (32 * 16));
- }
- } else
- pm = spibrg / (max_hz * 2);
- if (pm)
- pm--;
- fsl->pm = pm;
-
- if (fsl->div16)
- spi_freq = spibrg / ((pm + 1) * 2 * 16);
- else
- spi_freq = spibrg / ((pm + 1) * 2);
-
- /* set tx_timeout to 10 times of one espi FIFO entry go out */
- fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
- * 10), spi_freq);
-
- return &fsl->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- free(fsl);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
+void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
ccsr_espi_t *espi = fsl->espi;
- unsigned char pm = fsl->pm;
- unsigned int cs = slave->cs;
- unsigned int mode = fsl->mode;
- unsigned int div16 = fsl->div16;
- int i;
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
-
- /* Enable eSPI interface */
- out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
- | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
-
- out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
- out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */
-
- /* Init CS mode interface */
- for (i = 0; i < ESPI_MAX_CS_NUM; i++)
- out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
-
- out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
- ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
- | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
- | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
-
- /* Set eSPI BRG clock source */
- out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
- | ESPI_CSMODE_PM(pm) | div16);
-
- /* Set eSPI mode */
- if (mode & SPI_CPHA)
- out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
- | ESPI_CSMODE_CP_BEGIN_EDGCLK);
- if (mode & SPI_CPOL)
- out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
- | ESPI_CSMODE_CI_INACTIVEHIGH);
-
- /* Character bit order: msb first */
- out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
- | ESPI_CSMODE_REV_MSB_FIRST);
-
- /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
- out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
- | ESPI_CSMODE_LEN(7));
+ unsigned int com = 0;
+ size_t data_len = fsl->data_len;
- return 0;
+ com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
+ com |= ESPI_COM_CS(cs);
+ com |= ESPI_COM_TRANLEN(data_len - 1);
+ out_be32(&espi->com, com);
}
-void spi_release_bus(struct spi_slave *slave)
+void fsl_spi_cs_deactivate(struct spi_slave *slave)
{
+ struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+ ccsr_espi_t *espi = fsl->espi;
+ /* clear the RXCNT and TXCNT */
+ out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
+ out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
}
static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
}
-static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
+static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
+ unsigned int bytes)
{
ccsr_espi_t *espi = fsl->espi;
unsigned int tmpdin, rx_times;
return bytes;
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
- void *data_in, unsigned long flags)
+void espi_release_bus(struct fsl_spi_slave *fsl)
{
- struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+ /* Disable the SPI hardware */
+ out_be32(&fsl->espi->mode,
+ in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
+}
+
+int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
+ const void *data_out, void *data_in, unsigned long flags)
+{
+ struct spi_slave *slave = &fsl->slave;
ccsr_espi_t *espi = fsl->espi;
unsigned int event, rx_bytes;
const void *dout = NULL;
max_tran_len = fsl->max_transfer_length;
switch (flags) {
case SPI_XFER_BEGIN:
- cmd_len = fsl->cmd_len = data_len;
+ cmd_len = data_len;
+ fsl->cmd_len = cmd_len;
memcpy(cmd_buf, data_out, cmd_len);
return 0;
case 0:
case SPI_XFER_END:
if (bitlen == 0) {
- spi_cs_deactivate(slave);
+ fsl_spi_cs_deactivate(slave);
return 0;
}
buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
num_bytes = (tran_len + cmd_len) % 4;
fsl->data_len = tran_len + cmd_len;
- spi_cs_activate(slave);
+ fsl_spi_cs_activate(slave, cs);
/* Clear all eSPI events */
out_be32(&espi->event , 0xffffffff);
*(int *)buffer += tran_len;
}
}
- spi_cs_deactivate(slave);
+ fsl_spi_cs_deactivate(slave);
}
free(buffer);
return 0;
}
+void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs)
+{
+ ccsr_espi_t *espi = fsl->espi;
+ unsigned char pm = fsl->pm;
+ unsigned int mode = fsl->mode;
+ unsigned int div16 = fsl->div16;
+ int i;
+
+ /* Enable eSPI interface */
+ out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
+ | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
+
+ out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
+ out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */
+
+ /* Init CS mode interface */
+ for (i = 0; i < ESPI_MAX_CS_NUM; i++)
+ out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
+
+ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
+ ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
+ | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
+ | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
+
+ /* Set eSPI BRG clock source */
+ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+ | ESPI_CSMODE_PM(pm) | div16);
+
+ /* Set eSPI mode */
+ if (mode & SPI_CPHA)
+ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+ | ESPI_CSMODE_CP_BEGIN_EDGCLK);
+ if (mode & SPI_CPOL)
+ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+ | ESPI_CSMODE_CI_INACTIVEHIGH);
+
+ /* Character bit order: msb first */
+ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+ | ESPI_CSMODE_REV_MSB_FIRST);
+
+ /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
+ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+ | ESPI_CSMODE_LEN(7));
+}
+
+void espi_setup_slave(struct fsl_spi_slave *fsl)
+{
+ unsigned int max_hz;
+ sys_info_t sysinfo;
+ unsigned long spibrg = 0;
+ unsigned long spi_freq = 0;
+ unsigned char pm = 0;
+
+ max_hz = fsl->speed_hz;
+
+ get_sys_info(&sysinfo);
+ spibrg = sysinfo.freq_systembus / 2;
+ fsl->div16 = 0;
+ if ((spibrg / max_hz) > 32) {
+ fsl->div16 = ESPI_CSMODE_DIV16;
+ pm = spibrg / (max_hz * 16 * 2);
+ if (pm > 16) {
+ pm = 16;
+ debug("max_hz is too low: %d Hz, %ld Hz is used.\n",
+ max_hz, spibrg / (32 * 16));
+ }
+ } else {
+ pm = spibrg / (max_hz * 2);
+ }
+ if (pm)
+ pm--;
+ fsl->pm = pm;
+
+ if (fsl->div16)
+ spi_freq = spibrg / ((pm + 1) * 2 * 16);
+ else
+ spi_freq = spibrg / ((pm + 1) * 2);
+
+ /* set tx_timeout to 10 times of one espi FIFO entry go out */
+ fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
+ * 10), spi_freq);/* Set eSPI BRG clock source */
+}
+
+#if !CONFIG_IS_ENABLED(DM_SPI)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs < ESPI_MAX_CS_NUM;
}
-void spi_cs_activate(struct spi_slave *slave)
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct fsl_spi_slave *fsl;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
+ if (!fsl)
+ return NULL;
+
+ fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ fsl->mode = mode;
+ fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
+ fsl->speed_hz = max_hz;
+
+ espi_setup_slave(fsl);
+
+ return &fsl->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = fsl->espi;
- unsigned int com = 0;
- size_t data_len = fsl->data_len;
- com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
- com |= ESPI_COM_CS(slave->cs);
- com |= ESPI_COM_TRANLEN(data_len - 1);
- out_be32(&espi->com, com);
+ free(fsl);
}
-void spi_cs_deactivate(struct spi_slave *slave)
+int spi_claim_bus(struct spi_slave *slave)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = fsl->espi;
- /* clear the RXCNT and TXCNT */
- out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
- out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
+ espi_claim_bus(fsl, slave->cs);
+
+ return 0;
}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+
+ espi_release_bus(fsl);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
+
+ return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags);
+}
+#else
+static void __espi_set_speed(struct fsl_spi_slave *fsl)
+{
+ espi_setup_slave(fsl);
+
+ /* Set eSPI BRG clock source */
+ out_be32(&fsl->espi->csmode[fsl->cs],
+ in_be32(&fsl->espi->csmode[fsl->cs])
+ | ESPI_CSMODE_PM(fsl->pm) | fsl->div16);
+}
+
+static void __espi_set_mode(struct fsl_spi_slave *fsl)
+{
+ /* Set eSPI mode */
+ if (fsl->mode & SPI_CPHA)
+ out_be32(&fsl->espi->csmode[fsl->cs],
+ in_be32(&fsl->espi->csmode[fsl->cs])
+ | ESPI_CSMODE_CP_BEGIN_EDGCLK);
+ if (fsl->mode & SPI_CPOL)
+ out_be32(&fsl->espi->csmode[fsl->cs],
+ in_be32(&fsl->espi->csmode[fsl->cs])
+ | ESPI_CSMODE_CI_INACTIVEHIGH);
+}
+
+static int fsl_espi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+ espi_claim_bus(fsl, fsl->cs);
+
+ return 0;
+}
+
+static int fsl_espi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+ espi_release_bus(fsl);
+
+ return 0;
+}
+
+static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+ return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);
+}
+
+static int fsl_espi_set_speed(struct udevice *bus, uint speed)
+{
+ struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+ debug("%s speed %u\n", __func__, speed);
+ fsl->speed_hz = speed;
+
+ __espi_set_speed(fsl);
+
+ return 0;
+}
+
+static int fsl_espi_set_mode(struct udevice *bus, uint mode)
+{
+ struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+ debug("%s mode %u\n", __func__, mode);
+ fsl->mode = mode;
+
+ __espi_set_mode(fsl);
+
+ return 0;
+}
+
+static int fsl_espi_child_pre_probe(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct udevice *bus = dev->parent;
+ struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+ debug("%s cs %u\n", __func__, slave_plat->cs);
+ fsl->cs = slave_plat->cs;
+
+ return 0;
+}
+
+static int fsl_espi_probe(struct udevice *bus)
+{
+ struct fsl_espi_platdata *plat = dev_get_platdata(bus);
+ struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+ fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
+ fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
+ fsl->speed_hz = plat->speed_hz;
+
+ debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
+
+ return 0;
+}
+
+static const struct dm_spi_ops fsl_espi_ops = {
+ .claim_bus = fsl_espi_claim_bus,
+ .release_bus = fsl_espi_release_bus,
+ .xfer = fsl_espi_xfer,
+ .set_speed = fsl_espi_set_speed,
+ .set_mode = fsl_espi_set_mode,
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int fsl_espi_ofdata_to_platdata(struct udevice *bus)
+{
+ fdt_addr_t addr;
+ struct fsl_espi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+
+ addr = dev_read_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->regs_addr = lower_32_bits(addr);
+ plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+ FSL_ESPI_DEFAULT_SCK_FREQ);
+
+ debug("ESPI: regs=%p, max-frequency=%d\n",
+ &plat->regs_addr, plat->speed_hz);
+
+ return 0;
+}
+
+static const struct udevice_id fsl_espi_ids[] = {
+ { .compatible = "fsl,mpc8536-espi" },
+ { }
+};
+#endif
+
+U_BOOT_DRIVER(fsl_espi) = {
+ .name = "fsl_espi",
+ .id = UCLASS_SPI,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .of_match = fsl_espi_ids,
+ .ofdata_to_platdata = fsl_espi_ofdata_to_platdata,
+#endif
+ .ops = &fsl_espi_ops,
+ .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
+ .priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
+ .probe = fsl_espi_probe,
+ .child_pre_probe = fsl_espi_child_pre_probe,
+};
+#endif
return 0;
}
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
static struct kwspi_registers *spireg =
(struct kwspi_registers *)MVEBU_SPI_BASE;
static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
-#if defined(CONFIG_DM_SPI)
+#if CONFIG_IS_ENABLED(DM_SPI)
struct udevice *dev = mxcs->dev;
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
-#if defined(CONFIG_DM_SPI)
+#if CONFIG_IS_ENABLED(DM_SPI)
struct udevice *dev = mxcs->dev;
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
return 0;
}
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
};
struct omap3_spi_priv {
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
struct spi_slave slave;
#endif
struct mcspi *regs;
writel(conf, &priv->regs->modulctrl);
}
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
{
};
struct sh_qspi_slave {
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
struct spi_slave slave;
#endif
struct sh_qspi_regs *regs;
return ret;
}
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
{
return container_of(slave, struct sh_qspi_slave, slave);
SPICR_SPE)
#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
-#ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
-#endif
+#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) &&
i < priv->fifo_depth) {
- d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+ d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
debug("spi_xfer: tx:%x ", d);
/* write out and wait for processing (receive data) */
writel(d & SPIDTR_8BIT_MASK, ®s->spidtr);
#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_QSPI_FIFO_DEPTH 63
-#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
-#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
-#endif
+#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
/* zynq qspi register set */
struct zynq_qspi_regs {
do {
status = readl(®s->isr);
} while ((status == 0) &&
- (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
+ (get_timer(timeout) < ZYNQ_QSPI_WAIT));
if (status == 0) {
printf("zynq_qspi_irq_poll: Timeout!\n");
#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_SPI_FIFO_DEPTH 128
-#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
-#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
-#endif
+#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
/* zynq spi register set */
struct zynq_spi_regs {
ts = get_timer(0);
status = readl(®s->isr);
while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
- if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
+ if (get_timer(ts) > ZYNQ_SPI_WAIT) {
printf("spi_xfer: Timeout! TX FIFO not full\n");
return -1;
}
return usb_match_one_id_intf(desc, int_desc, id);
}
+static ofnode usb_get_ofnode(struct udevice *hub, int port)
+{
+ ofnode node;
+ u32 reg;
+
+ if (!dev_has_of_node(hub))
+ return ofnode_null();
+
+ /*
+ * The USB controller and its USB hub are two different udevices,
+ * but the device tree has only one node for both. Thus we are
+ * assigning this node to both udevices.
+ * If port is zero, the controller scans its root hub, thus we
+ * are using the same ofnode as the controller here.
+ */
+ if (!port)
+ return dev_ofnode(hub);
+
+ ofnode_for_each_subnode(node, dev_ofnode(hub)) {
+ if (ofnode_read_u32(node, "reg", ®))
+ continue;
+
+ if (reg == port)
+ return node;
+ }
+
+ return ofnode_null();
+}
+
/**
* usb_find_and_bind_driver() - Find and bind the right USB driver
*
static int usb_find_and_bind_driver(struct udevice *parent,
struct usb_device_descriptor *desc,
struct usb_interface_descriptor *iface,
- int bus_seq, int devnum,
+ int bus_seq, int devnum, int port,
struct udevice **devp)
{
struct usb_driver_entry *start, *entry;
int n_ents;
int ret;
char name[30], *str;
+ ofnode node = usb_get_ofnode(parent, port);
*devp = NULL;
debug("%s: Searching for driver\n", __func__);
* find another driver. For now this doesn't seem
* necesssary, so just bind the first match.
*/
- ret = device_bind(parent, drv, drv->name, NULL, -1,
- &dev);
+ ret = device_bind_ofnode(parent, drv, drv->name, NULL,
+ node, &dev);
if (ret)
goto error;
debug("%s: Match found: %s\n", __func__, drv->name);
if (ret) {
if (ret != -ENOENT)
return ret;
- ret = usb_find_and_bind_driver(parent, &udev->descriptor, iface,
+ ret = usb_find_and_bind_driver(parent, &udev->descriptor,
+ iface,
udev->controller_dev->seq,
- udev->devnum, &dev);
+ udev->devnum, port, &dev);
if (ret)
return ret;
created = true;
option compiles in the video uclass and routes all LCD/video access
through this.
+config BACKLIGHT
+ bool "Enable panel backlight uclass support"
+ depends on DM_VIDEO
+ default y
+ help
+ This provides backlight uclass driver that enables basic panel
+ backlight support.
+
config BACKLIGHT_PWM
bool "Generic PWM based Backlight Driver"
- depends on DM_VIDEO && DM_PWM
+ depends on BACKLIGHT && DM_PWM
default y
help
If you have a LCD backlight adjustable by PWM, say Y to enable
config BACKLIGHT_GPIO
bool "Generic GPIO based Backlight Driver"
- depends on DM_VIDEO
+ depends on BACKLIGHT
help
If you have a LCD backlight adjustable by GPIO, say Y to enable
this driver.
it understands the standard device tree
(leds/backlight/gpio-backlight.txt)
+config CMD_VIDCONSOLE
+ bool "Enable vidconsole commands lcdputs and setcurs"
+ depends on DM_VIDEO
+ default y
+ help
+ Enabling this will provide 'setcurs' and 'lcdputs' commands which
+ support cursor positioning and drawing strings on video framebuffer.
+
config VIDEO_BPP8
bool "Support 8-bit-per-pixel displays"
depends on DM_VIDEO
loads takes over the screen. This, for example, can be used to
keep splash image on screen until grub graphical boot menu starts.
+config PANEL
+ bool "Enable panel uclass support"
+ depends on DM_VIDEO
+ default y
+ help
+ This provides panel uclass driver that enables basic panel support.
+
+config SIMPLE_PANEL
+ bool "Enable simple panel support"
+ depends on PANEL
+ default y
+ help
+ This turns on a simple panel driver that enables a compatible
+ video panel.
+
source "drivers/video/fonts/Kconfig"
config VIDCONSOLE_AS_LCD
- bool "Use 'vidconsole' when 'lcd' is seen in stdout"
+ bool "Use 'vidconsole' when CONFIG_VIDCONSOLE_AS_NAME string is seen in stdout"
depends on DM_VIDEO
help
- This is a work-around for boards which have 'lcd' in their stdout
- environment variable, but have moved to use driver model for video.
- In this case the console will no-longer work. While it is possible
- to update the environment, the breakage may be confusing for users.
- This option will be removed around the end of 2016.
+ This is a work-around for boards which have 'lcd' or 'vga' in their
+ stdout environment variable, but have moved to use driver model for
+ video. In this case the console will no-longer work. While it is
+ possible to update the environment, the breakage may be confusing for
+ users. This option will be removed around the end of 2020.
+
+config VIDCONSOLE_AS_NAME
+ string "Use 'vidconsole' when string defined here is seen in stdout"
+ depends on VIDCONSOLE_AS_LCD
+ default "lcd" if LCD || TEGRA_COMMON
+ default "vga" if !LCD
+ help
+ This is a work-around for boards which have 'lcd' or 'vga' in their
+ stdout environment variable, but have moved to use driver model for
+ video. In this case the console will no-longer work. While it is
+ possible to update the environment, the breakage may be confusing for
+ users. This option will be removed around the end of 2020.
config VIDEO_COREBOOT
bool "Enable coreboot framebuffer driver support"
config ATMEL_HLCD
bool "Enable ATMEL video support using HLCDC"
- depends on DM_VIDEO
help
HLCDC supports video output to an attached LCD panel.
config AM335X_LCD
bool "Enable AM335x video support"
- depends on DM_VIDEO
help
Supports video output to an attached LCD panel.
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifdef CONFIG_DM
+obj-$(CONFIG_BACKLIGHT) += backlight-uclass.o
obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o
obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o
obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o
obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
obj-$(CONFIG_DISPLAY) += display-uclass.o
-obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
-obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
+obj-$(CONFIG_PANEL) += panel-uclass.o
+obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
endif
obj-${CONFIG_EXYNOS_FB} += exynos/
config VIDEO_IPUV3
bool "i.MX IPUv3 Core video support"
- depends on (VIDEO || DM_VIDEO) && (MX5 || MX6)
+ depends on DM_VIDEO && (MX5 || MX6)
help
This enables framebuffer driver for i.MX processors working
on the IPUv3(Image Processing Unit) internal graphic processor.
else
bg_chan = 0;
- if (!g_ipu_clk_enabled)
- clk_enable(g_ipu_clk);
-
if (bg_chan) {
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
- if (!g_ipu_clk_enabled)
- clk_disable(g_ipu_clk);
-
return 0;
}
(channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
return -EINVAL;
- if (!g_ipu_clk_enabled)
- clk_enable(g_ipu_clk);
-
color_key_4rgb = 1;
/* Transform color key from rgb to yuv if CSC is enabled */
if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
- if (!g_ipu_clk_enabled)
- clk_disable(g_ipu_clk);
-
return 0;
}
static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
-/* graphics setup */
-static GraphicDevice panel;
static struct fb_videomode const *gmode;
static uint8_t gdisp;
static uint32_t gpixfmt;
return pixfmt;
}
-/*
- * Set fixed framebuffer parameters based on variable settings.
- *
- * @param info framebuffer information pointer
- */
-static int mxcfb_set_fix(struct fb_info *info)
-{
- struct fb_fix_screeninfo *fix = &info->fix;
- struct fb_var_screeninfo *var = &info->var;
-
- fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
-
- fix->type = FB_TYPE_PACKED_PIXELS;
- fix->accel = FB_ACCEL_NONE;
- fix->visual = FB_VISUAL_TRUECOLOR;
- fix->xpanstep = 1;
- fix->ypanstep = 1;
-
- return 0;
-}
-
static int setup_disp_channel1(struct fb_info *fbi)
{
ipu_channel_params_t params;
ipu_disable_channel(mxc_fbi->ipu_ch);
ipu_uninit_channel(mxc_fbi->ipu_ch);
- mxcfb_set_fix(fbi);
mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
}
fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
-#if CONFIG_IS_ENABLED(DM_VIDEO)
fbi->screen_base = (char *)gd->video_bottom;
-#else
- fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
- fbi->fix.smem_len);
-#endif
fbi->fix.smem_start = (unsigned long)fbi->screen_base;
if (fbi->screen_base == 0) {
(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
fbi->screen_size = fbi->fix.smem_len;
-
-#if CONFIG_IS_ENABLED(VIDEO)
gd->fb_base = fbi->fix.smem_start;
-#endif
/* Clear the screen */
memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
return fbi;
}
+extern struct clk *g_ipu_clk;
+
/*
* Probe routine for the framebuffer driver. It is called during the
* driver binding process. The following functions are performed in
{
struct fb_info *fbi;
struct mxcfb_info *mxcfbi;
- int ret = 0;
/*
* Initialize FB structures
*/
fbi = mxcfb_init_fbinfo();
- if (!fbi) {
- ret = -ENOMEM;
- goto err0;
- }
+ if (!fbi)
+ return -ENOMEM;
+
mxcfbi = (struct mxcfb_info *)fbi->par;
if (!g_dp_in_use) {
mxcfbi->ipu_di = disp;
+ if (!ipu_clk_enabled())
+ clk_enable(g_ipu_clk);
+
ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);
- strcpy(fbi->fix.id, "DISP3 BG");
g_dp_in_use = 1;
mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
fb_videomode_to_var(&fbi->var, mode);
fbi->var.bits_per_pixel = 16;
- fbi->fix.line_length = fbi->var.xres * (fbi->var.bits_per_pixel / 8);
+ fbi->fix.line_length = fbi->var.xres_virtual *
+ (fbi->var.bits_per_pixel / 8);
fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length;
mxcfb_check_var(&fbi->var, fbi);
/* Default Y virtual size is 2x panel size */
fbi->var.yres_virtual = fbi->var.yres * 2;
- mxcfb_set_fix(fbi);
-
/* allocate fb first */
if (mxcfb_map_video_memory(fbi) < 0)
return -ENOMEM;
mxcfb_set_par(fbi);
- panel.winSizeX = mode->xres;
- panel.winSizeY = mode->yres;
- panel.plnSizeX = mode->xres;
- panel.plnSizeY = mode->yres;
-
- panel.frameAdrs = (u32)fbi->screen_base;
- panel.memSize = fbi->screen_size;
-
- panel.gdfBytesPP = 2;
- panel.gdfIndex = GDF_16BIT_565RGB;
-
+#ifdef DEBUG
ipu_dump_registers();
+#endif
return 0;
-
-err0:
- return ret;
}
void ipuv3_fb_shutdown(void)
}
}
-void *video_hw_init(void)
-{
- int ret;
-
- ret = ipu_probe();
- if (ret)
- puts("Error initializing IPU\n");
-
- ret = mxcfb_probe(gpixfmt, gdisp, gmode);
- debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs);
- gd->fb_base = panel.frameAdrs;
-
- return (void *)&panel;
-}
-
int ipuv3_fb_init(struct fb_videomode const *mode,
uint8_t disp,
uint32_t pixfmt)
return 0;
}
-#if CONFIG_IS_ENABLED(DM_VIDEO)
enum {
/* Maximum display size we support */
LCD_MAX_WIDTH = 1920,
#if defined(CONFIG_DISPLAY)
struct udevice *disp_dev;
#endif
- struct udevice *panel_dev;
u32 fb_start, fb_end;
int ret;
return ret;
}
#endif
- ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
- if (panel_dev)
- panel_enable_backlight(panel_dev);
+ if (CONFIG_IS_ENABLED(PANEL)) {
+ struct udevice *panel_dev;
+
+ ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
+ if (panel_dev)
+ panel_enable_backlight(panel_dev);
+ }
uc_priv->xsize = gmode->xres;
uc_priv->ysize = gmode->yres;
}
static const struct udevice_id ipuv3_video_ids[] = {
+#ifdef CONFIG_ARCH_MX6
{ .compatible = "fsl,imx6q-ipu" },
+#endif
+#ifdef CONFIG_ARCH_MX5
{ .compatible = "fsl,imx53-ipu" },
+#endif
{ }
};
.priv_auto_alloc_size = sizeof(struct ipuv3_video_priv),
.flags = DM_FLAG_PRE_RELOC,
};
-#endif /* CONFIG_DM_VIDEO */
.per_device_auto_alloc_size = sizeof(struct vidconsole_priv),
};
+#if CONFIG_IS_ENABLED(CMD_VIDCONSOLE)
void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned row)
{
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
"print string on video framebuffer",
" <string>"
);
+#endif /* CONFIG_IS_ENABLED(CMD_VIDCONSOLE) */
__func__, size, *addrp, dev->name);
}
gd->video_bottom = *addrp;
+ gd->fb_base = *addrp;
debug("Video frame buffers from %lx to %lx\n", gd->video_bottom,
gd->video_top);
static int setup_flash_device(void)
{
-#ifdef CONFIG_DM_SPI_FLASH
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
struct udevice *new;
int ret;
extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
extra-$(CONFIG_PPC) += sched
-ifndef CONFIG_DM_ETH
-extra-$(CONFIG_SMC911X) += smc911x_eeprom
-endif
-
#
# Some versions of make do not handle trailing white spaces properly;
# leading to build failures. The problem was found with GNU Make 3.80.
+++ /dev/null
-/*
- * smc911x_eeprom.c - EEPROM interface to SMC911x parts.
- * Only tested on SMSC9118 though ...
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Based on smc91111_eeprom.c which:
- * Heavily borrowed from the following peoples GPL'ed software:
- * - Wolfgang Denk, DENX Software Engineering, wd@denx.de
- * Das U-Boot
- * - Ladislav Michl ladis@linux-mips.org
- * A rejected patch on the U-Boot mailing list
- */
-
-#include <common.h>
-#include <console.h>
-#include <exports.h>
-#include <net.h>
-#include <linux/ctype.h>
-#include <linux/types.h>
-#include "../drivers/net/smc911x.h"
-
-#define DRIVERNAME "smc911x"
-
-#if defined (CONFIG_SMC911X_32_BIT) && \
- defined (CONFIG_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
- CONFIG_SMC911X_16_BIT shall be set"
-#endif
-
-struct chip_id {
- u16 id;
- char *name;
-};
-
-static const struct chip_id chip_ids[] = {
- { CHIP_89218, "LAN89218" },
- { CHIP_9115, "LAN9115" },
- { CHIP_9116, "LAN9116" },
- { CHIP_9117, "LAN9117" },
- { CHIP_9118, "LAN9118" },
- { CHIP_9211, "LAN9211" },
- { CHIP_9215, "LAN9215" },
- { CHIP_9216, "LAN9216" },
- { CHIP_9217, "LAN9217" },
- { CHIP_9218, "LAN9218" },
- { CHIP_9220, "LAN9220" },
- { CHIP_9221, "LAN9221" },
- { 0, NULL },
-};
-
-#if defined (CONFIG_SMC911X_32_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
- return *(volatile u32*)(dev->iobase + offset);
-}
-
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-{
- *(volatile u32*)(dev->iobase + offset) = val;
-}
-#elif defined (CONFIG_SMC911X_16_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
- return (*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16);
-}
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-{
- *(volatile u16 *)(dev->iobase + offset) = (u16)val;
- *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
-}
-#else
-#error "SMC911X: undefined bus width"
-#endif /* CONFIG_SMC911X_16_BIT */
-
-static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
-{
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
- smc911x_reg_write(dev, MAC_CSR_CMD,
- MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
-
- return smc911x_reg_read(dev, MAC_CSR_DATA);
-}
-
-static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
-{
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
- smc911x_reg_write(dev, MAC_CSR_DATA, data);
- smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
- while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
- ;
-}
-
-static int smc911x_detect_chip(struct eth_device *dev)
-{
- unsigned long val, i;
-
- val = smc911x_reg_read(dev, BYTE_TEST);
- if (val == 0xffffffff) {
- /* Special case -- no chip present */
- return -1;
- } else if (val != 0x87654321) {
- printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
- return -1;
- }
-
- val = smc911x_reg_read(dev, ID_REV) >> 16;
- for (i = 0; chip_ids[i].id != 0; i++) {
- if (chip_ids[i].id == val) break;
- }
- if (!chip_ids[i].id) {
- printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
- return -1;
- }
-
- dev->priv = (void *)&chip_ids[i];
-
- return 0;
-}
-
-static void smc911x_reset(struct eth_device *dev)
-{
- int timeout;
-
- /*
- * Take out of PM setting first
- * Device is already wake up if PMT_CTRL_READY bit is set
- */
- if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
- /* Write to the bytetest will take out of powerdown */
- smc911x_reg_write(dev, BYTE_TEST, 0x0);
-
- timeout = 10;
-
- while (timeout-- &&
- !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
- udelay(10);
- if (timeout < 0) {
- printf(DRIVERNAME
- ": timeout waiting for PM restore\n");
- return;
- }
- }
-
- /* Disable interrupts */
- smc911x_reg_write(dev, INT_EN, 0);
-
- smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
-
- timeout = 1000;
- while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
- udelay(10);
-
- if (timeout < 0) {
- printf(DRIVERNAME ": reset timeout\n");
- return;
- }
-
- /* Reset the FIFO level and flow control settings */
- smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
- smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
-
- /* Set to LED outputs */
- smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
-}
-
-/**
- * smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?)
- */
-static int smsc_ctrlc(void)
-{
- return (tstc() && getc() == 0x03);
-}
-
-/**
- * usage - dump usage information
- */
-static void usage(void)
-{
- puts(
- "MAC/EEPROM Commands:\n"
- " P : Print the MAC addresses\n"
- " D : Dump the EEPROM contents\n"
- " M : Dump the MAC contents\n"
- " C : Copy the MAC address from the EEPROM to the MAC\n"
- " W : Write a register in the EEPROM or in the MAC\n"
- " Q : Quit\n"
- "\n"
- "Some commands take arguments:\n"
- " W <E|M> <register> <value>\n"
- " E: EEPROM M: MAC\n"
- );
-}
-
-/**
- * dump_regs - dump the MAC registers
- *
- * Registers 0x00 - 0x50 are FIFOs. The 0x50+ are the control registers
- * and they're all 32bits long. 0xB8+ are reserved, so don't bother.
- */
-static void dump_regs(struct eth_device *dev)
-{
- u8 i, j = 0;
- for (i = 0x50; i < 0xB8; i += sizeof(u32))
- printf("%02x: 0x%08x %c", i,
- smc911x_reg_read(dev, i),
- (j++ % 2 ? '\n' : ' '));
-}
-
-/**
- * do_eeprom_cmd - handle eeprom communication
- */
-static int do_eeprom_cmd(struct eth_device *dev, int cmd, u8 reg)
-{
- if (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) {
- printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(dev, E2P_CMD));
- return -1;
- }
-
- smc911x_reg_write(dev, E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
-
- while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
- if (smsc_ctrlc()) {
- printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(dev, E2P_CMD));
- return -1;
- }
-
- return 0;
-}
-
-/**
- * read_eeprom_reg - read specified register in EEPROM
- */
-static u8 read_eeprom_reg(struct eth_device *dev, u8 reg)
-{
- int ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ, reg);
- return (ret ? : smc911x_reg_read(dev, E2P_DATA));
-}
-
-/**
- * write_eeprom_reg - write specified value into specified register in EEPROM
- */
-static int write_eeprom_reg(struct eth_device *dev, u8 value, u8 reg)
-{
- int ret;
-
- /* enable erasing/writing */
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN, reg);
- if (ret)
- goto done;
-
- /* erase the eeprom reg */
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE, reg);
- if (ret)
- goto done;
-
- /* write the eeprom reg */
- smc911x_reg_write(dev, E2P_DATA, value);
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE, reg);
- if (ret)
- goto done;
-
- /* disable erasing/writing */
- ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWDS, reg);
-
- done:
- return ret;
-}
-
-/**
- * skip_space - find first non-whitespace in given pointer
- */
-static char *skip_space(char *buf)
-{
- while (isblank(buf[0]))
- ++buf;
- return buf;
-}
-
-/**
- * write_stuff - handle writing of MAC registers / eeprom
- */
-static void write_stuff(struct eth_device *dev, char *line)
-{
- char dest;
- char *endp;
- u8 reg;
- u32 value;
-
- /* Skip over the "W " part of the command */
- line = skip_space(line + 1);
-
- /* Figure out destination */
- switch (line[0]) {
- case 'E':
- case 'M':
- dest = line[0];
- break;
- default:
- invalid_usage:
- printf("ERROR: Invalid write usage\n");
- usage();
- return;
- }
-
- /* Get the register to write */
- line = skip_space(line + 1);
- reg = simple_strtoul(line, &endp, 16);
- if (line == endp)
- goto invalid_usage;
-
- /* Get the value to write */
- line = skip_space(endp);
- value = simple_strtoul(line, &endp, 16);
- if (line == endp)
- goto invalid_usage;
-
- /* Check for trailing cruft */
- line = skip_space(endp);
- if (line[0])
- goto invalid_usage;
-
- /* Finally, execute the command */
- if (dest == 'E') {
- printf("Writing EEPROM register %02x with %02x\n", reg, value);
- write_eeprom_reg(dev, value, reg);
- } else {
- printf("Writing MAC register %02x with %08x\n", reg, value);
- smc911x_reg_write(dev, reg, value);
- }
-}
-
-/**
- * copy_from_eeprom - copy MAC address in eeprom to address registers
- */
-static void copy_from_eeprom(struct eth_device *dev)
-{
- ulong addrl =
- read_eeprom_reg(dev, 0x01) |
- read_eeprom_reg(dev, 0x02) << 8 |
- read_eeprom_reg(dev, 0x03) << 16 |
- read_eeprom_reg(dev, 0x04) << 24;
- ulong addrh =
- read_eeprom_reg(dev, 0x05) |
- read_eeprom_reg(dev, 0x06) << 8;
- smc911x_set_mac_csr(dev, ADDRL, addrl);
- smc911x_set_mac_csr(dev, ADDRH, addrh);
- puts("EEPROM contents copied to MAC\n");
-}
-
-/**
- * print_macaddr - print MAC address registers and MAC address in eeprom
- */
-static void print_macaddr(struct eth_device *dev)
-{
- puts("Current MAC Address in MAC: ");
- ulong addrl = smc911x_get_mac_csr(dev, ADDRL);
- ulong addrh = smc911x_get_mac_csr(dev, ADDRH);
- printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- (u8)(addrl), (u8)(addrl >> 8), (u8)(addrl >> 16),
- (u8)(addrl >> 24), (u8)(addrh), (u8)(addrh >> 8));
-
- puts("Current MAC Address in EEPROM: ");
- int i;
- for (i = 1; i < 6; ++i)
- printf("%02x:", read_eeprom_reg(dev, i));
- printf("%02x\n", read_eeprom_reg(dev, i));
-}
-
-/**
- * dump_eeprom - dump the whole content of the EEPROM
- */
-static void dump_eeprom(struct eth_device *dev)
-{
- int i;
- puts("EEPROM:\n");
- for (i = 0; i < 7; ++i)
- printf("%02x: 0x%02x\n", i, read_eeprom_reg(dev, i));
-}
-
-/**
- * smc911x_init - get the MAC/EEPROM up and ready for use
- */
-static int smc911x_init(struct eth_device *dev)
-{
- /* See if there is anything there */
- if (smc911x_detect_chip(dev))
- return 1;
-
- smc911x_reset(dev);
-
- /* Make sure we set EEDIO/EECLK to the EEPROM */
- if (smc911x_reg_read(dev, GPIO_CFG) & GPIO_CFG_EEPR_EN) {
- while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
- if (smsc_ctrlc()) {
- printf("init: timeout (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(dev, E2P_CMD));
- return 1;
- }
- smc911x_reg_write(dev, GPIO_CFG,
- smc911x_reg_read(dev, GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
- }
-
- return 0;
-}
-
-/**
- * getline - consume a line of input and handle some escape sequences
- */
-static char *getline(void)
-{
- static char buffer[100];
- char c;
- size_t i;
-
- i = 0;
- while (1) {
- buffer[i] = '\0';
- while (!tstc())
- continue;
-
- c = getc();
- /* Convert to uppercase */
- if (c >= 'a' && c <= 'z')
- c -= ('a' - 'A');
-
- switch (c) {
- case '\r': /* Enter/Return key */
- case '\n':
- puts("\n");
- return buffer;
-
- case 0x03: /* ^C - break */
- return NULL;
-
- case 0x5F:
- case 0x08: /* ^H - backspace */
- case 0x7F: /* DEL - backspace */
- if (i) {
- puts("\b \b");
- i--;
- }
- break;
-
- default:
- /* Ignore control characters */
- if (c < 0x20)
- break;
- /* Queue up all other characters */
- buffer[i++] = c;
- printf("%c", c);
- break;
- }
- }
-}
-
-/**
- * smc911x_eeprom - our application's main() function
- */
-int smc911x_eeprom(int argc, char *const argv[])
-{
- /* Avoid initializing on stack as gcc likes to call memset() */
- struct eth_device dev;
- dev.iobase = CONFIG_SMC911X_BASE;
-
- /* Print the ABI version */
- app_startup(argv);
- if (XF_VERSION != get_version()) {
- printf("Expects ABI version %d\n", XF_VERSION);
- printf("Actual U-Boot ABI version %lu\n", get_version());
- printf("Can't run\n\n");
- return 1;
- }
-
- /* Initialize the MAC/EEPROM somewhat */
- puts("\n");
- if (smc911x_init(&dev))
- return 1;
-
- /* Dump helpful usage information */
- puts("\n");
- usage();
- puts("\n");
-
- while (1) {
- char *line;
-
- /* Send the prompt and wait for a line */
- puts("eeprom> ");
- line = getline();
-
- /* Got a ctrl+c */
- if (!line)
- return 0;
-
- /* Eat leading space */
- line = skip_space(line);
-
- /* Empty line, try again */
- if (!line[0])
- continue;
-
- /* Only accept 1 letter commands */
- if (line[0] && line[1] && !isblank(line[1]))
- goto unknown_cmd;
-
- /* Now parse the command */
- switch (line[0]) {
- case 'W': write_stuff(&dev, line); break;
- case 'D': dump_eeprom(&dev); break;
- case 'M': dump_regs(&dev); break;
- case 'C': copy_from_eeprom(&dev); break;
- case 'P': print_macaddr(&dev); break;
- unknown_cmd:
- default: puts("ERROR: Unknown command!\n\n");
- case '?':
- case 'H': usage(); break;
- case 'Q': return 0;
- }
- }
-}
/* Volume label or VFAT entry, skip */
continue;
}
- } else if (!(dent->attr & ATTR_ARCH) &&
- !(dent->attr & ATTR_DIR))
- continue;
+ }
/* short file name */
break;
return ret;
}
-/*
- * Set short name in directory entry
+/**
+ * set_name() - set short name in directory entry
+ *
+ * @dirent: directory entry
+ * @filename: long file name
*/
static void set_name(dir_entry *dirent, const char *filename)
{
if (len == 0)
return;
- strcpy(s_name, filename);
+ strncpy(s_name, filename, VFAT_MAXLEN_BYTES - 1);
+ s_name[VFAT_MAXLEN_BYTES - 1] = '\0';
uppercase(s_name, len);
period = strchr(s_name, '.');
memcpy(dirent->name, s_name, period_location);
} else {
memcpy(dirent->name, s_name, 6);
+ /*
+ * TODO: Translating two long names with the same first six
+ * characters to the same short name is utterly wrong.
+ * Short names must be unique.
+ */
dirent->name[6] = '~';
dirent->name[7] = '1';
}
return 0;
}
+
+int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct fstype_info *drv = fstypes;
+ const int n_ents = ARRAY_SIZE(fstypes);
+ struct fstype_info *entry;
+ int i = 0;
+
+ puts("Supported filesystems");
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (entry->fstype != FS_TYPE_ANY) {
+ printf("%c %s", i ? ',' : ':', entry->name);
+ i++;
+ }
+ }
+ if (!i)
+ puts(": <none>");
+ puts("\n");
+ return CMD_RET_SUCCESS;
+}
unsigned long bi_vco; /* VCO Out from PLL, in MHz */
#endif
#if defined(CONFIG_M68K)
- unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
#if defined(CONFIG_EXTRA_CLOCK)
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
-
-#ifdef CONFIG_HAS_ETH1
- unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH2
- unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH3
- unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH4
- unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH5
- unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */
-#endif
-
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
#ifdef CONFIG_NR_DRAM_BANKS
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * B4860 QDS board configuration file
- */
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
-#ifndef CONFIG_MTD_RAW_NAND
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-#endif
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#ifndef CONFIG_ARCH_B4420
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#endif
-
-/* I2C bus multiplexer */
-#define I2C_MUX_PCA_ADDR 0x77
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define I2C_CH_DEFAULT 0x8
-#define I2C_CH_VSC3316 0xc
-#define I2C_CH_VSC3308 0xd
-
-#define VSC3316_TX_ADDRESS 0x70
-#define VSC3316_RX_ADDRESS 0x71
-#define VSC3308_TX_ADDRESS 0x02
-#define VSC3308_RX_ADDRESS 0x03
-
-/* IDT clock synthesizers */
-#define CONFIG_IDT8T49N222A
-#define I2C_CH_IDT 0x9
-
-#define IDT_SERDES1_ADDRESS 0x6E
-#define IDT_SERDES2_ADDRESS 0x6C
-
-/* Voltage monitor on channel 2*/
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-#define CONFIG_ZM7300
-#define I2C_MUX_CH_DPM 0xa
-#define I2C_DPM_ADDR 0x28
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#if 0
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#endif
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x53
-
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
- FTIM0_NOR_TEADC(0x04) | \
- FTIM0_NOR_TEAHC(0x20))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
- FTIM2_NOR_TCH(0x0E) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define CONFIG_FSL_QIXIS_V2
-#define QIXIS_BASE 0xffdf0000
-#ifdef CONFIG_PHYS_64BIT
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS QIXIS_BASE
-#endif
-#define QIXIS_LBMAP_SWITCH 0x01
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x02
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * RapidIO
- */
-#ifdef CONFIG_SYS_SRIO
-#ifdef CONFIG_SRIO1
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#endif
-
-#ifdef CONFIG_SRIO2
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-#endif
-#endif
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * MAPLE
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
-#else
-#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
-#endif
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 25
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 25
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-
-#define CONFIG_SYS_DPAA_RMAN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x10
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x11
-#endif
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
-#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
-
-/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
-#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
-
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#endif
-
-#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE ulpi
-
-#ifdef CONFIG_ARCH_B4860
-#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
- "bank_intlv=cs0_cs1;" \
- "en_cpc:cpc2;"
-#else
-#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- HWCONFIG \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=b4860qds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=b4860qds/b4860qds.dtb\0" \
- "bdev=sda3\0"
-
-/* For emulation this causes u-boot to jump to the start of the proof point
- app code automatically */
-#define CONFIG_PROOF_POINTS \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x29000000 - - -;" \
- "cpu 2 release 0x29000000 - - -;" \
- "cpu 3 release 0x29000000 - - -;" \
- "cpu 4 release 0x29000000 - - -;" \
- "cpu 5 release 0x29000000 - - -;" \
- "cpu 6 release 0x29000000 - - -;" \
- "cpu 7 release 0x29000000 - - -;" \
- "go 0x29000000"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x01e00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * BSC9131 RDB board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_NAND_FSL_IFC
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
-#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
-#if defined(CONFIG_SYS_CLK_100)
-#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
-#else
-#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
-#endif
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* enable branch predition */
-
-/* DDR Setup */
-#undef CONFIG_SYS_DDR_RAW_TIMING
-#undef CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_sdram_size(void);
-#endif
-#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-/* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
-
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
- /* CONFIG_SYS_IMMR */
-/* DSP CCSRBAR */
-#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
- * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
- * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
- * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
- * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
- * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
- * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
- * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
- * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
- * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
- *
- */
-
-/*
- * IFC Definitions
- */
-
-/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-/* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
- | FTIM0_NAND_TWP(0x05) \
- | FTIM0_NAND_TWCHT(0x02) \
- | FTIM0_NAND_TWH(0x04))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
- | FTIM1_NAND_TWBE(0x1E) \
- | FTIM1_NAND_TRR(0x07) \
- | FTIM1_NAND_TRP(0x05))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
- | FTIM2_NAND_TREH(0x04) \
- | FTIM2_NAND_TWHRE(0x11))
-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-/* Set up IFC registers for boot location NAND */
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-
-/* Serial Port */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-
-/* I2C EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/* eSPI - Enhanced SPI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 3
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#endif
-
-#define CONFIG_HOSTNAME "BSC9131rdb"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "loadaddr=1000000\0" \
- "bootfile=uImage\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=bsc9131rdb.dtb\0" \
- "bdev=sda1\0" \
- "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
- "bootm_size=0x37000000\0" \
- "othbootargs=ramdisk_size=600000 " \
- "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * BSC9132 QDS board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-#ifdef CONFIG_NAND_SECBOOT
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
-#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-/*
- * PCI Windows
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SYS_CLK_100_DDR_100)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-#elif defined(CONFIG_SYS_CLK_100_DDR_133)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133000000
-#endif
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* enable branch predition */
-
-/* DDR Setup */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
-#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_SDRAM_SIZE (1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* DDR3 Controller Settings */
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
-#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
-#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
-
-#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
-#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
-#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
-#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
-
-#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
-#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
-#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
-#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
-#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
-#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
-#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
-
-/*FIXME: the following params are constant w.r.t diff freq
-combinations. this should be removed later
-*/
-#if CONFIG_DDR_CLK_FREQ == 100000000
-#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
-#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
-#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
-#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
-#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
-#elif CONFIG_DDR_CLK_FREQ == 133000000
-#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
-#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
-#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
-#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
-#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
-#else
-#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
-#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
-#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
-#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
-#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
-#endif
-
-/* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
-
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
-
-/* DSP CCSRBAR */
-#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-
-/*
- * IFC Definitions
- */
-/* NOR Flash on IFC */
-
-#define CONFIG_SYS_FLASH_BASE 0x88000000
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_NOR_CSPR 0x88000101
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
-/* NOR Flash Timing Params */
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
- | FTIM0_NOR_TEADC(0x03) \
- | FTIM0_NOR_TAVDS(0x00) \
- | FTIM0_NOR_TEAHC(0x0f))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
- | FTIM1_NOR_TRAD_NOR(0x09) \
- | FTIM1_NOR_TSEQRAD_NOR(0x09))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
- | FTIM2_NOR_TCH(0x4) \
- | FTIM2_NOR_TWPH(0x7) \
- | FTIM2_NOR_TWP(0x1e))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/* CFI for NOR Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-/* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
- | FTIM0_NAND_TWP(0x05) \
- | FTIM0_NAND_TWCHT(0x02) \
- | FTIM0_NAND_TWH(0x04))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
- | FTIM1_NAND_TWBE(0x1e) \
- | FTIM1_NAND_TRR(0x07) \
- | FTIM1_NAND_TRP(0x05))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
- | FTIM2_NAND_TREH(0x04) \
- | FTIM2_NAND_TWHRE(0x11))
-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-/* NAND */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_FSL_QIXIS
-#endif
-#ifdef CONFIG_FSL_QIXIS
-#define CONFIG_SYS_FPGA_BASE 0xffb00000
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
-#define QIXIS_LBMAP_SWITCH 9
-#define QIXIS_LBMAP_MASK 0x07
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x83
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-
-#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
-
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-#endif
-
-/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-
-/* Serial Port */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/* I2C EEPROM */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/* I2C FPGA */
-#define CONFIG_I2C_FPGA
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-
-#define CONFIG_RTC_DS3231
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * SPI interface will not be available in case of NAND boot SPI CS0 will be
- * used for SLIC
- */
-/* eSPI - Enhanced SPI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-/* TBI PHY configuration for SGMII mode */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_ANEG_ENABLE \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
-#endif /* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * Environment
- */
-#if defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_HOSTNAME "BSC9132qds"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin"
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
-#else
-#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "loadaddr=1000000\0" \
- "bootfile=uImage\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=bsc9132qds.dtb\0" \
- "bdev=sda1\0" \
- CONFIG_DEF_HWCONFIG\
- "othbootargs=mem=880M ramdisk_size=600000 " \
- "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
- "isolcpus=0\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "debug_halt_off=mw ff7e0e30 0xf0000000;"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * C29XPCIE board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_NAND_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-/*
- * PCI Windows
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 1"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_DDR_CLK_FREQ 100000000
-#define CONFIG_SYS_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-
-/* DDR Setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x50
-#define CONFIG_SYS_DDR_RAW_TIMING
-
-/* DDR ECC Setup*/
-#define CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-
-#define CONFIG_SYS_SDRAM_SIZE 512
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* Platform SRAM setting */
-#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
-#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
- (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
-#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
-
-/*
- * IFC Definitions
- */
-/* NOR Flash on IFC */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
-
-/* 16Bit NOR Flash - S29GL512S10TFI01 */
-#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-/* CFI for NOR Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
-
-/* 8Bit NAND Flash - K9F1G08U0B */
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_NAND \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
- | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
- | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
- | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
- FTIM0_NAND_TWP(0x0c) | \
- FTIM0_NAND_TWCHT(0x08) | \
- FTIM0_NAND_TWH(0x06))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
- FTIM1_NAND_TWBE(0x1d) | \
- FTIM1_NAND_TRR(0x08) | \
- FTIM1_NAND_TRP(0x0c))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x18))
-#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-/* Set up IFC registers for boot location NOR/NAND */
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-/* CPLD on IFC, selected by CS2 */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
- | CONFIG_SYS_CPLD_BASE)
-
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif
-#endif
-#endif
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/* I2C EEPROM */
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/* eSPI - Enhanced SPI */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-/* Default mode is RGMII mode */
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SYS_RAMBOOT)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#else
-#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
-#endif
-#endif
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "loadaddr=1000000\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=name/of/device-tree.dtb\0" \
- "othbootargs=ramdisk_size=600000\0" \
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
-#define CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_83XX_PCI_STREAMING
-#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_83XX_PCI_STREAMING
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define CONFIG_83XX_PCI_STREAMING
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8536ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/*
- * Memory map -- xxx -this is wrong, needs updating
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
- CONFIG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_PWR 0x5 /* PIXIS Power status register */
-#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VSTAT 0x11 /* VELA Status Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
-#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
-#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
-#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
-#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
-#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
-#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
-#define PIXIS_VWATCH 0x24 /* Watchdog Register */
-#define PIXIS_LED 0x25 /* LED Register */
-
-#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
- CONFIG_SYS_NAND_BASE + 0x40000, \
- CONFIG_SYS_NAND_BASE + 0x80000, \
- CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
- (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR4_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 1"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 2"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_NAME "Slot 3"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_PCI)
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
-#endif
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1c
-
-#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
-#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#elif defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_MPH_USB
-#ifdef CONFIG_HAS_FSL_MPH_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR 192.168.1.254
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=8536ds/ramdisk.uboot\0" \
-"fdtaddr=1e00000\0" \
-"fdtfile=8536ds/mpc8536ds.dtb\0" \
-"bdev=sda3\0" \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#define CONFIG_MPC85XX_PCI2
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#error ("CONFIG_SPD_EEPROM is required")
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Memory map
*
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#ifndef CONFIG_PCI_PNP
#error ("CONFIG_SPD_EEPROM is required")
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
/*
* Physical Address Map
*
#endif
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_DM_PCI)
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#define CONFIG_MPC85XX_PCI2
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#error ("CONFIG_SPD_EEPROM is required")
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00010000
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#error ("CONFIG_SPD_EEPROM is required")
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Memory map
*
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#ifndef CONFIG_PCI_PNP
#define CONFIG_SYS_SDRAM_SIZE 256
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
#define CONFIG_SYS_INIT_RAM_LOCK 1
#ifndef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_SDRAM_SIZE 256
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
#define CONFIG_SYS_INIT_RAM_LOCK 1
#ifndef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
/************************************************************
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-#define CONFIG_SYS_NAND_MAX_OOBFREE 5
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_MAX_SIZE 4096
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#endif
-
-/* High Level Configuration Options */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
- SPL code*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_VERY_BIG_RAM
-
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 2048
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_TIMING_3 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0 0x40110104
-#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
-#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
-#define CONFIG_SYS_DDR_MODE_1 0x00441221
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
-#define CONFIG_SYS_DDR_CONTROL 0xc7000008
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
- * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#endif
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Nand Flash */
-#if defined(CONFIG_NAND_FSL_ELBC)
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
-#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#else
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-#endif /* CONFIG_NAND_FSL_ELBC */
-
-#define CONFIG_HWCONFIG
-
-#define CONFIG_FSL_NGPIXIS
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
-
-#define PIXIS_LBMAP_SWITCH 7
-#define PIXIS_LBMAP_MASK 0xF0
-#define PIXIS_LBMAP_ALTBANK 0x20
-#define PIXIS_SPD 0x07
-#define PIXIS_SPD_SYSCLK_MASK 0x07
-#define PIXIS_ELBC_SPI_MASK 0xc0
-#define PIXIS_SPI 0x80
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/*
- * Config the L2 Cache as L2 SRAM
-*/
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif
-#endif
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Video */
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-
-#ifdef CONFIG_ATI
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
-#endif
-#define CONFIG_SYS_I2C_FSL
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, Slot 1, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_TSECV2
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-#define TSEC1_PHY_ADDR 1
-#define TSEC2_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#endif
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#endif
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HOSTNAME "p1022ds"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=p1022ds.dtb\0" \
- "bdev=sda3\0" \
- "hwconfig=esdhc;audclk:12\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#endif
* for your console driver.
*/
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* for your console driver.
*/
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T1024/T1023 QDS board configuration file
- */
-
-#ifndef __T1024QDS_H
-#define __T1024QDS_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_DEEP_SLEEP
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
-#endif
-
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-/* PCIe Boot - Master */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-#else
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
-#endif
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#else
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
-#endif
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/* PCIe Boot - Slave */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-/* Set 1M boot space for PCIe boot */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (256 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#ifdef CONFIG_PHYS_64BIT
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS QIXIS_BASE
-#endif
-#define QIXIS_LBMAP_SWITCH 0x06
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_RST_FORCE_MEM 0x01
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* Video */
-#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
-#define CONFIG_FSL_DIU_FB
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_FSL_DIU_CH7301
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-
-#define I2C_MUX_PCA_ADDR 0x77
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
-#define I2C_RETIMER_ADDR 0x18
-
-/* I2C bus multiplexer */
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_DIU 0xC
-#define I2C_MUX_CH5 0xD
-#define I2C_MUX_CH7 0xF
-
-/* LDI/DVI Encoder for display */
-#define CONFIG_SYS_I2C_LDI_ADDR 0x38
-#define CONFIG_SYS_I2C_DVI_ADDR 0x75
-#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCIe
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/*
- *SATA
- */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_LBA48
-#endif
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
-/*
- * SDHC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-
-/* Default address of microcode for the Linux FMan driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define RGMII_PHY1_ADDR 0x1
-#define RGMII_PHY2_ADDR 0x2
-#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
-#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
-#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1@DTSEC4"
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
- "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
- "ramdiskfile=t1024qds/ramdisk.uboot\0" \
- "fdtfile=t1024qds/t1024qds.dtb\0" \
- "netdev=eth0\0" \
- "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "fdtaddr=d00000\0" \
- "bdev=sda3\0"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __T1024QDS_H */
+++ /dev/null
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * T1040 QDS board configuration file
- */
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-/* support deep sleep */
-#define CONFIG_DEEP_SLEEP
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
-
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-/*
- * TDM Definition
- */
-#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
-
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#define QIXIS_LBMAP_SWITCH 0x06
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_RST_FORCE_MEM 0x01
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* Video */
-#define CONFIG_FSL_DIU_FB
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_FSL_DIU_CH7301
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-
-/* I2C */
-
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SPEED 50000
-#define CONFIG_SYS_FSL_I2C3_SPEED 50000
-#define CONFIG_SYS_FSL_I2C4_SPEED 50000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#endif
-
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-
-#define I2C_MUX_PCA_ADDR 0x77
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
-
-/* I2C bus multiplexer */
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_DIU 0xC
-
-/* LDI/DVI Encoder for display */
-#define CONFIG_SYS_I2C_LDI_ADDR 0x38
-#define CONFIG_SYS_I2C_DVI_ADDR 0x75
-#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 4, Base address 203000 */
-#ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x10
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x11
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
-
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#endif
-
-/* Enable VSC9953 L2 Switch driver */
-#define CONFIG_VSC9953
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t1040qds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t1040qds/t1040qds.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * T4240 QDS board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE4
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
-#if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD)
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#endif
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_DDR_ECC
-
-#include "t4qds.h"
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS4 0x54
-#define SPD_EEPROM_ADDRESS5 0x55
-#define SPD_EEPROM_ADDRESS6 0x56
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_LBMAP_SWITCH 6
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x83
-#define QIXIS_RST_FORCE_MEM 0x1
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_BRDCFG5 0x55
-#define QIXIS_MUX_SDHC 2
-#define QIXIS_MUX_SDHC_WIDTH8 1
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#else
-#undef CONFIG_SYS_I2C
-#undef CONFIG_SYS_FSL_I2C2_OFFSET
-#undef CONFIG_SYS_FSL_I2C2_SLAVE
-#undef CONFIG_SYS_FSL_I2C2_SPEED
-#undef CONFIG_SYS_FSL_I2C_SLAVE
-#undef CONFIG_SYS_FSL_I2C_SPEED
-#undef CONFIG_SYS_FSL_I2C_OFFSET
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_MUX_CH_VSC3316_FS 0xc
-#define I2C_MUX_CH_VSC3316_BS 0xd
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define VSC3316_FSM_TX_ADDR 0x70
-#define VSC3316_FSM_RX_ADDR 0x71
-
-/*
- * RapidIO
- */
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-/*
- * eSPI - Enhanced SPI
- */
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define FM1_10GEC1_PHY_ADDR 0x0
-#define FM1_10GEC2_PHY_ADDR 0x1
-#define FM2_10GEC1_PHY_ADDR 0x2
-#define FM2_10GEC2_PHY_ADDR 0x3
-#endif
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_ESDHC_DETECT_QUIRK \
- (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
- IS_SVR_REV(get_svr(), 1, 0))
-#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
- (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
-#endif
-
-
-#define __USB_PHY_TYPE utmi
-
-/*
- * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
- * interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_ARCH_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t4240qds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-#undef CONFIG_EEPRO100
-#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define CONFIG_SYS_DDR_MODE_2 0x8000c000
#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Memory map
*
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */
-#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#endif
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#endif
#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/* Ethernet */
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#ifndef CONFIG_SPL_BUILD
/* CPSW Ethernet */
#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
#define CONFIG_HSMMC2_8BIT
/* CPSW Ethernet */
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
#define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */
-/* Serial */
-#define CONFIG_BAUDRATE 115200
-
/* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE SZ_2K
#include "tegra124-common.h"
-#define CONFIG_ARCH_MISC_INIT
-
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
#define CONFIG_HOSTNAME "apf27"
#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-/* general purpose I/O */
-#if !CONFIG_IS_ENABLED(DM_GPIO)
-#define CONFIG_AT91_GPIO
-#endif
-
/*
* BOOTP options
*/
* CONFIG_DBGU is DBGU unit on J10
* CONFIG_USART1 is USART1 on J14
*/
-#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0/* ignored in arm */
#define CONFIG_LCD_LOGO
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
-#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
/*
#define CONFIG_SYS_NS16550_COM2 0x66110000
#define CONFIG_SYS_NS16550_COM3 0x66120000
#define CONFIG_SYS_NS16550_COM4 0x66130000
-#define CONFIG_BAUDRATE 115200
/* console configuration */
#define CONFIG_SYS_CBSIZE SZ_1K
/*
* Serial console configuration.
*/
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
"saveenv; " \
"fi; "
-/* Autoboot options */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
- "Enter passphrase to stop autoboot, booting in %d seconds\n"
-#define CONFIG_AUTOBOOT_STOP_STR "123"
-
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include <configs/bur_am335x_common.h>
#include <linux/stringify.h>
/* ------------------------------------------------------------------------- */
-#define CONFIG_BOARD_TYPES
/* memory */
#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
/* SPI Flash */
/* Environment */
-
-#define CONFIG_CONS_INDEX 1
#endif /* __CONFIG_BRSMARC1_H__ */
#include <configs/bur_am335x_common.h>
#include <linux/stringify.h>
/* ------------------------------------------------------------------------- */
-#if !defined(CONFIG_AM335X_LCD)
-#define CONFIG_AM335X_LCD
-#endif
#define LCD_BPP LCD_COLOR32
/* memory */
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* Commands */
-
-#undef CONFIG_BOOTM_NETBSD
-
/* ENET Config */
#define CONFIG_FEC_XCV_TYPE RMII
#define FEC_QUIRK_ENET_MAC
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
-#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_BOOTCOUNT_ENV
-
/* Environment organisation */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1, eMMC */
/* NAND: SPL related configs */
/* USB configuration */
-#define CONFIG_ARCH_MISC_INIT
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
-/* Serial */
-#define CONFIG_BAUDRATE 115200
-
/* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-
#define CONFIG_HOSTNAME "ccdc"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "ccdc.img"
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_TCLK 166666667
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-#define CONFIG_BUILD_TARGET "u-boot.kwb"
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX 1 /* Console on UART0 */
/*
* Environment variables configurations
/* BOOTP/DHCP options */
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_TIMEOFFSET
#undef CONFIG_BOOTP_VENDOREX
/* UART */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_BAUDRATE 115200
/* USB Configs */
#ifdef CONFIG_CMD_USB
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND "if run check_em_pad; then " \
#include <configs/rk3368_common.h>
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#undef CONFIG_CONSOLE_SCROLL_LINES
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
#define SDRAM_BANK_SIZE (2UL << 30)
-#define CONFIG_CONSOLE_SCROLL_LINES 10
-
#endif
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#undef CONFIG_CONSOLE_SCROLL_LINES
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0xb0000c00
-#define CONFIG_CONS_INDEX 1
#endif
/* UART */
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
-#define CONFIG_BCH
-
#endif /* __GE_BX50V3_CONFIG_H */
#include <configs/rk3368_common.h>
-#define CONFIG_CONSOLE_SCROLL_LINES 10
-
#endif
/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
#define CONFIG_SYS_CLK_FREQ 66666666
-/* Serial Console */
-#define CONFIG_BAUDRATE 115200
-
/* Miscellaneous */
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_CMDLINE_TAG
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-/* Kernel Boot */
-#define CONFIG_BOOTARGS "ignore_loglevel"
-
/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CSF_SIZE SZ_8K
-#endif
-
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CSF_SIZE SZ_8K
-#endif
-
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CSF_SIZE SZ_8K
-#endif
-
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
-#endif
-
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
-#define CONFIG_BAUDRATE 115200
-
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
-/* Serial */
-#define CONFIG_BAUDRATE 115200
-
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
-#undef CONFIG_BOOTM_NETBSD
-
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */
#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
-/* Serial */
-#define CONFIG_BAUDRATE 115200
-
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
/* LPDDR4 board total DDR is 3GB */
#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
-/* Serial */
-#define CONFIG_BAUDRATE 115200
-
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
*/
#define CONFIG_TULIP
-#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
/*-----------------------------------------------------------------------
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CADENCE_QSPI
#define CONFIG_CQSPI_REF_CLK 384000000
#endif
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM3 0xb0000e00
-#define CONFIG_CONS_INDEX 3
#endif
#define CONFIG_SPI_FLASH_SPANSION
#endif
-/* DM SPI */
-#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_DM_SPI_FLASH
-#endif
-
/*
* eTSEC
*/
* MMC
*/
-/* DM SPI */
-#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_DM_SPI_FLASH
-#endif
-
/*
* Video
*/
#define CONFIG_SYS_FSL_PBL_RCW \
"board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
-#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif /* ifdef CONFIG_NXP_ESBC */
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#endif
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_BAUDRATE 115200
-
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
* MMC
*/
-/* DM SPI */
-#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_DM_SPI_FLASH
-#endif
-
/*
* Video
*/
#endif
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* Miscellaneous configurable options */
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
-#ifndef CONFIG_CMDLINE_EDITING
-#define CONFIG_CMDLINE_EDITING 1
-#endif
-
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/* DSPI */
#ifndef SPL_NO_DSPI
-#define CONFIG_FSL_DSPI
#ifdef CONFIG_FSL_DSPI
-#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
#define CONFIG_SPI_FLASH_SST /* cs1 */
#define CONFIG_SPI_FLASH_EON /* cs2 */
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F 1
/* DDR */
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
(void *)CONFIG_SYS_SERIAL1, \
(void *)CONFIG_SYS_SERIAL2, \
(void *)CONFIG_SYS_SERIAL3 }
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* MC firmware */
#define CONFIG_PCI_GT64120
#define CONFIG_PCI_MSC01
-#define CONFIG_PCNET
-#define PCNET_HAS_PROM
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0xb0000c00
-#define CONFIG_CONS_INDEX 1
#endif
/* Serial common */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
/* Command definition */
#define CONFIG_FSL_IIM
-#define CONFIG_BCH
-
/* Backlight Control */
#define CONFIG_IMX6_PWM_PER_CLK 66666000
#else
#error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx)
#endif
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16)
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* UART */
#define LPUART_BASE LPUART4_RBASE
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CACHELINE_SIZE 64
#ifdef CONFIG_DRIVER_TI_EMAC
#undef CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
/* SDRAM Definitions */
#define CONFIG_SYS_SDRAM_BASE 0x0
-#define CONFIG_SYS_SDRAM_SIZE 0x80000000
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY (24000000) /* 24MHz */
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00)
-/* UART Definitions */
-#define CONFIG_BAUDRATE 115200
-
/* Console configuration */
#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Memory map
*
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * QorIQ P1 Tower boards configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#if defined(CONFIG_TWR_P1025)
-#define CONFIG_BOARDNAME "TWR-P1025"
-#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
-#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
-
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* Default settings for DDR3 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00220004
-#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
-#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x80461320
-#define CONFIG_SYS_DDR_MODE_2 0x00008000
-#define CONFIG_SYS_DDR_INTERVAL 0x09480000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- *
- * Localbus
- * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
- * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
- *
- * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
- * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
- | BR_PS_16 | BR_V)
-
-#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
-
-#define CONFIG_SYS_SSD_BASE 0xe0000000
-#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
-#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
- BR_PS_16 | BR_V)
-#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
-/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-
-/* Serial Port
- * open - index 2
- * shorted - index 1
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
-
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#undef CONFIG_TSEC2
-#undef CONFIG_TSEC2_NAME
-#define CONFIG_TSEC3
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#undef CONFIG_HAS_ETH2
-#endif /* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_QE
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#endif /* CONFIG_QE */
-
-#ifdef CONFIG_TWR_P1025
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
-
-#undef CONFIG_UEC_ETH
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1 /* ETH1 */
-#define CONFIG_HAS_ETH0
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_UEC_ETH1 */
-
-#define CONFIG_UEC_ETH5 /* ETH5 */
-#define CONFIG_HAS_ETH1
-
-#ifdef CONFIG_UEC_ETH5
-#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
-#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
-#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
-#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
-#endif /* CONFIG_UEC_ETH5 */
-#endif /* CONFIG_TWR-P1025 */
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#ifdef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"loadaddr=1000000\0" \
-"bootfile=uImage\0" \
-"dtbfile=twr-p1025twr.dtb\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
-"kernelflash=tftpboot $loadaddr $bootfile; " \
- "protect off 0xefa80000 +$filesize; " \
- "erase 0xefa80000 +$filesize; " \
- "cp.b $loadaddr 0xefa80000 $filesize; " \
- "protect on 0xefa80000 +$filesize; " \
- "cmp.b $loadaddr 0xefa80000 $filesize\0" \
-"dtbflash=tftpboot $loadaddr $dtbfile; " \
- "protect off 0xefe80000 +$filesize; " \
- "erase 0xefe80000 +$filesize; " \
- "cp.b $loadaddr 0xefe80000 $filesize; " \
- "protect on 0xefe80000 +$filesize; " \
- "cmp.b $loadaddr 0xefe80000 $filesize\0" \
-"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
- "protect off 0xeeb80000 +$filesize; " \
- "erase 0xeeb80000 +$filesize; " \
- "cp.b $loadaddr 0xeeb80000 $filesize; " \
- "protect on 0xeeb80000 +$filesize; " \
- "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
-"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
- "protect off 0xefec0000 +$filesize; " \
- "erase 0xefec0000 +$filesize; " \
- "cp.b $loadaddr 0xefec0000 $filesize; " \
- "protect on 0xefec0000 +$filesize; " \
- "cmp.b $loadaddr 0xefec0000 $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"fdtaddr=1e00000\0" \
-"bdev=sda1\0" \
-"norbootaddr=ef080000\0" \
-"norfdtaddr=ef040000\0" \
-"ramdisk_size=120000\0" \
-"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
-"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
-
-#define CONFIG_NFSBOOTCOMMAND \
-"setenv bootargs root=/dev/nfs rw " \
-"nfsroot=$serverip:$rootpath " \
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile&&" \
-"tftp $fdtaddr $fdtfile&&" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT \
-"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"usb start;" \
-"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
-"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_USB_FAT_BOOT \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"usb start;" \
-"fatload usb 0:2 $loadaddr $bootfile;" \
-"fatload usb 0:2 $fdtaddr $fdtfile;" \
-"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_USB_EXT2_BOOT \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"usb start;" \
-"ext2load usb 0:4 $loadaddr $bootfile;" \
-"ext2load usb 0:4 $fdtaddr $fdtfile;" \
-"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_NORBOOT \
-"setenv bootargs root=/dev/mtdblock3 rw " \
-"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
-"bootm $norbootaddr - $norfdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND_TFTP \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"tftp $ramdiskaddr $ramdiskfile;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"bootm 0xefa80000 0xeeb80000 0xefe80000"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_COM4 UART3_BASE
#define CONFIG_SYS_NS16550_COM5 UART4_BASE
#define CONFIG_SYS_NS16550_COM6 UART5_BASE
-#define CONFIG_BAUDRATE 115200
#endif /* ! __CONFIG_PDU001_H */
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(PHYS_SDRAM_SIZE >> 1))
-#define CONFIG_BAUDRATE 115200
-
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */
-#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-/* MMC/SD IP block */
-//#define CONFIG_BOUNCE_BUFFER
-
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define SDRAM_BANK_SIZE (2UL << 30)
#endif
/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#endif
-
-/*
* OHCI USB
*/
#ifdef CONFIG_CMD_USB
#include "rockchip-common.h"
#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR)
#endif
-#if 0
-/* Configure PXE */
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
-#endif
-
/* Physical memory map */
/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
#define PHYS_SDRAM (DDR_BASE_ADDR)
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP 8
-#define CONFIG_PMECC_SECTOR_SIZE 512
-
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SD_BOOT
"bootz 0x22000000 - 0x21000000"
#endif
-#ifdef CONFIG_QSPI_BOOT
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
-#endif
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \
"fatload mmc 0:1 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
#endif
/* SPL */
#define CONFIG_KEEP_SERVERADDR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP
#endif
#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
- "eth1addr=00:00:11:22:33:45\0" \
- "eth3addr=00:00:11:22:33:46\0" \
- "eth5addr=00:00:11:22:33:47\0" \
+ "eth3addr=00:00:11:22:33:45\0" \
+ "eth5addr=00:00:11:22:33:46\0" \
+ "eth6addr=00:00:11:22:33:47\0" \
"ipaddr=1.2.3.4\0"
#define MEM_LAYOUT_ENV_SETTINGS \
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define CONFIG_SYS_DDR_CONTROL 0xc300c000
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* FLASH on the Local Bus
* Two banks, one 8MB the other 64MB, using the CFI driver.
#endif
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#undef CONFIG_CLOCKS_IN_MHZ
-
#define CONFIG_SYS_INIT_RAM_LOCK 1
#ifndef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define DTB_LOAD_ADDR 0x5600000
#define INITRD_LOAD_ADDR 0x5bf0000
-#define CONFIG_CONSOLE_SCROLL_LINES 10
-
#endif
*/
#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef CONFIGS_SIPEED_MAIX_H
+#define CONFIGS_SIPEED_MAIX_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+/* Start just below the second bank so we don't clobber it during reloc */
+#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
+#define CONFIG_SYS_MALLOC_LEN SZ_128K
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* Don't relocate into AI ram since it isn't set up yet */
+#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M)
+
+/* For early init */
+#define K210_SYSCTL_BASE 0x50440000
+
+#endif /* CONFIGS_SIPEED_MAIX_H */
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO /* enable the GPIO features */
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */
-#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/* GPIOs and IO expander */
#define CONFIG_ATMEL_LEGACY
-#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
/* UARTs/Serial console */
-#define CONFIG_ATMEL_USART
#ifndef CONFIG_DM_SERIAL
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/* GPIOs and IO expander */
#define CONFIG_ATMEL_LEGACY
-#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1
/* UARTs/Serial console */
-#define CONFIG_ATMEL_USART
/* Boot options */
#define CONFIG_SYS_LOAD_ADDR 0x23000000
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* Booting Linux */
-#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTFILE "zImage"
-#define CONFIG_BOOTARGS \
- "console=ttyS0," __stringify(CONFIG_BAUDRATE) \
- " ubi.fm_autoconvert=1" \
- " uio_pdrv_genirq.of_id=\"idq,regbank\""
#define CONFIG_BOOTCOMMAND \
"setenv bootcmd '" \
* CONFIG_BOOTARGS goes into the environment value "bootargs".
* Do note the value will override also the chosen node in FDT blob.
*/
-#define CONFIG_BOOTARGS "earlycon"
#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
"run mmcboot"
* for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), boot only on the same device
* for nand or spi-nand boot, boot with on ubifs partition on UBI partition
- * for nor boot, use the default order
+ * for nor boot, use SD card = mmc0
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
"if test ${boot_device} = nand ||" \
" test ${boot_device} = spi-nand ;" \
"then env set boot_targets ubifs0; fi;" \
+ "if test ${boot_device} = nor;" \
+ "then env set boot_targets mmc0; fi;" \
"run distro_bootcmd;" \
"fi;\0"
"splashimage=0xc4300000\0" \
"ramdisk_addr_r=0xc4400000\0" \
"altbootcmd=run bootcmd\0" \
- "env_default=1\0" \
- "env_check=if test $env_default -eq 1;"\
- " then env set env_default 0;env save;fi\0" \
+ "env_check=if env info -p -d; then env save; fi\0" \
STM32MP_BOOTCMD \
BOOTENV \
"boot_net_usb_start=true\0"
#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 root=/dev/ram0 rw " \
- "rootfstype=ramfs " \
- "rdinit=/bin/init " \
- "devtmpfs.mount=1"
-
#define CONFIG_BOOTCOMMAND \
"sf probe 0:1 50000000; " \
"sf read ${loadaddr} 0x100000 ${kern_size}; " \
*
*/
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
/* Framebuffer */
-#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#endif
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */
#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
"bootm 0x10800000 0x10d00000\0" \
"console=ttymxc0\0" \
"fan=gpio set 92\0" \
+ "fdt_addr=0x13000000\0" \
+ "fdt_addr_r=0x13000000\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "kernel_addr_r=0x10008000\0" \
+ "pxefile_addr_r=0x10008000\0" \
+ "ramdisk_addr_r=0x18000000\0" \
+ "scriptaddr=0x14000000\0" \
"set_con_serial=setenv stdout serial; " \
"setenv stderr serial\0" \
- "set_con_hdmi=setenv stdout serial,vga; " \
- "setenv stderr serial,vga\0" \
- "stderr=serial,vga\0" \
+ "set_con_hdmi=setenv stdout serial,vidconsole; " \
+ "setenv stderr serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0" \
"stdin=serial,usbkbd\0" \
- "stdout=serial,vga\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan; " \
- "if run bootcmd_up1; then " \
- "run bootcmd_up2; " \
- "else " \
- "run bootcmd_mmc; " \
- "fi"
+ "stdout=serial,vidconsole\0"
+
+/* Enable distro boot */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(SATA, sata, 0) \
+ func(USB, usb, 0)
+
+#include <config_distro_bootcmd.h>
#endif /* __TBS2910_CONFIG_H * */
#endif
/* Ethernet */
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_PHY_ET1011C_TX_CLK_FIX
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#ifndef CONFIG_SPL_BUILD
/* Network defines. */
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
/* Network Configuration */
#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 32
#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
-#define CONFIG_BOARD_TYPES
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
#error Unknown DDR size - please add!
#endif
-#define CONFIG_CONS_INDEX 1
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_BOARD_EARLY_INIT_R
#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
#define VCOREIII_DEFAULT_MTD_ENV \
"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CSF_SIZE SZ_8K
-#endif
-
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+#define COUNTER_FREQUENCY 24000000 /* 24MHz */
/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
-#define CONFIG_ARM_PL180_MMCI
#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
/* The value in the common file is too far away for the VInCo platform */
/* serial console */
-#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE 0xfc00c000
#define CONFIG_USART_ID 30
#if defined(CONFIG_PCI)
-#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM3 0xb0000e00
-#define CONFIG_CONS_INDEX 3
/* RAM */
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO
/* serial console */
-#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
#endif
-#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \
- "rw noinitrd mem=64M " \
- "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \
"autoload=no\0" \
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-/* general purpose I/O */
-#define CONFIG_AT91_GPIO
-
/* serial console */
-#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_DBGU
"nand read 0x22000000 0x000e0000 0x500000; " \
"bootm"
-#define CONFIG_BOOTARGS \
- "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
-
-#define CONFIG_BAUDRATE 115200
-
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
* for your console driver.
*/
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-
/* NAND */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Booting Linux */
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
#define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
"source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
- "xspi "
+ "xspi0 "
#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
#endif
-#define CONFIG_BOARD_EARLY_INIT_F
-
#endif /* __XILINX_ZYNQMP_H */
/* BOOTP options */
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_MAY_FAIL
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
#endif /* __CONFIG_ZYNQMP_MINI_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __fsl_espi_h
+#define __fsl_espi_h
+
+struct fsl_espi_platdata {
+ uint flags;
+ uint speed_hz;
+ uint num_chipselect;
+ fdt_addr_t regs_addr;
+};
+
+#endif /* __fsl_espi_h */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ */
+
+#ifndef __PXA_MMC_GEN_H
+#define __PXA_MMC_GEN_H
+
+#include <mmc.h>
+
+/*
+ * struct pxa_mmc_platdata - information about a PXA MMC controller
+ *
+ * @base: MMC controller base register address
+ */
+struct pxa_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ struct pxa_mmc_regs *base;
+};
+
+#endif /* __PXA_MMC_GEN_H */
#define FFUART_INDEX 1
#define STUART_INDEX 2
#elif CONFIG_CPU_PXA25X
-#define UART_CLK_BASE (1 << 4) /* HWUART */
+#define UART_CLK_BASE BIT(4) /* HWUART */
#define UART_CLK_REG CKEN
#define HWUART_INDEX 0
#define STUART_INDEX 1
/*
* struct pxa_serial_platdata - information about a PXA port
*
- * @base: Uart port base register address
- * @port: Uart port index, for cpu with pinmux for uart / gpio
- * baudrtatre: Uart port baudrate
+ * @base: Uart port base register address
+ * @port: Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre: Uart port baudrate
*/
struct pxa_serial_platdata {
struct pxa_uart_regs *base;
static inline void *dev_read_addr_ptr(const struct udevice *dev)
{
- return devfdt_get_addr_ptr(dev);
+ void *addr = devfdt_get_addr_ptr(dev);
+
+ return ((fdt_addr_t)(uintptr_t)addr == FDT_ADDR_T_NONE) ? NULL : addr;
}
static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev)
static inline int dev_read_alias_seq(const struct udevice *dev, int *devnump)
{
+#if CONFIG_IS_ENABLED(OF_CONTROL)
return fdtdec_get_alias_seq(gd->fdt_blob, dev->uclass->uc_drv->name,
dev_of_offset(dev), devnump);
+#else
+ return -ENOTSUPP;
+#endif
}
static inline int dev_read_u32_array(const struct udevice *dev,
static inline int dev_read_alias_highest_id(const char *stem)
{
+ if (!CONFIG_IS_ENABLED(OF_LIBFDT))
+ return -1;
return fdtdec_get_alias_highest_id(gd->fdt_blob, stem);
}
/* Dump out a list of drivers */
void dm_dump_drivers(void);
+/* Dump out a list with each driver's compatibility strings */
+void dm_dump_driver_compat(void);
+
+/* Dump out a list of drivers with static platform data */
+void dm_dump_static_driver_info(void);
+
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef CLOCK_K210_SYSCTL_H
+#define CLOCK_K210_SYSCTL_H
+
+/*
+ * Arbitrary identifiers for clocks.
+ */
+#define K210_CLK_NONE 0
+#define K210_CLK_IN0_H 1
+#define K210_CLK_PLL0_H 2
+#define K210_CLK_PLL0 3
+#define K210_CLK_PLL1 4
+#define K210_CLK_PLL2 5
+#define K210_CLK_PLL2_H 6
+#define K210_CLK_CPU 7
+#define K210_CLK_SRAM0 8
+#define K210_CLK_SRAM1 9
+#define K210_CLK_APB0 10
+#define K210_CLK_APB1 11
+#define K210_CLK_APB2 12
+#define K210_CLK_ROM 13
+#define K210_CLK_DMA 14
+#define K210_CLK_AI 15
+#define K210_CLK_DVP 16
+#define K210_CLK_FFT 17
+#define K210_CLK_GPIO 18
+#define K210_CLK_SPI0 19
+#define K210_CLK_SPI1 20
+#define K210_CLK_SPI2 21
+#define K210_CLK_SPI3 22
+#define K210_CLK_I2S0 23
+#define K210_CLK_I2S1 24
+#define K210_CLK_I2S2 25
+#define K210_CLK_I2S0_M 26
+#define K210_CLK_I2S1_M 27
+#define K210_CLK_I2S2_M 28
+#define K210_CLK_I2C0 29
+#define K210_CLK_I2C1 30
+#define K210_CLK_I2C2 31
+#define K210_CLK_UART1 32
+#define K210_CLK_UART2 33
+#define K210_CLK_UART3 34
+#define K210_CLK_AES 35
+#define K210_CLK_FPIOA 36
+#define K210_CLK_TIMER0 37
+#define K210_CLK_TIMER1 38
+#define K210_CLK_TIMER2 39
+#define K210_CLK_WDT0 40
+#define K210_CLK_WDT1 41
+#define K210_CLK_SHA 42
+#define K210_CLK_OTP 43
+#define K210_CLK_RTC 44
+#define K210_CLK_ACLK 45
+
+#endif /* CLOCK_K210_SYSCTL_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP4_H
+#define __DT_BINDINGS_CLK_OMAP4_H
+
+#define OMAP4_CLKCTRL_OFFSET 0x20
+#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
+
+/* mpuss clocks */
+#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* tesla clocks */
+#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
+
+/* l4_ao clocks */
+#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+
+/* l3_1 clocks */
+#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_2 clocks */
+#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+
+/* ducati clocks */
+#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_dma clocks */
+#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_emif clocks */
+#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+
+/* d2d clocks */
+#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l4_cfg clocks */
+#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+
+/* l3_instr clocks */
+#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+
+/* ivahd clocks */
+#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+
+/* iss clocks */
+#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+
+/* l3_dss clocks */
+#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_gfx clocks */
+#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_init clocks */
+#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0)
+#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
+
+/* l4_per clocks */
+#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0)
+#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8)
+#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0)
+#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8)
+#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0)
+#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0)
+#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8)
+#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100)
+#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108)
+#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120)
+#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128)
+#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138)
+#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140)
+#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
+#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150)
+#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
+#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
+
+/* l4_secure clocks */
+#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
+#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
+#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
+#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
+#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
+#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
+#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
+#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
+#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
+
+/* l4_wkup clocks */
+#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+
+/* emu_sys clocks */
+#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP5_H
+#define __DT_BINDINGS_CLK_OMAP5_H
+
+#define OMAP5_CLKCTRL_OFFSET 0x20
+#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dsp clocks */
+#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+
+/* l3main1 clocks */
+#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3main2 clocks */
+#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dma clocks */
+#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+
+/* l4cfg clocks */
+#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+
+/* l3instr clocks */
+#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+
+/* l4per clocks */
+#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
+#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
+#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
+#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
+#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
+#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
+#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
+#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
+#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
+#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
+#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
+#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
+#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
+#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
+#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
+#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
+#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
+#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
+#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
+#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
+#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
+
+/* l4_secure clocks */
+#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
+#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
+#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
+#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
+#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
+#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
+#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
+#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
+#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
+
+/* iva clocks */
+#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+
+/* dss clocks */
+#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* gpu clocks */
+#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3init clocks */
+#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
+#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
+#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
+#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+
+/* wkupaon clocks */
+#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef K210_SYSCTL_H
+#define K210_SYSCTL_H
+
+/* Taken from kendryte-standalone-sdk/lib/drivers/include/sysctl.h */
+#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */
+#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */
+#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */
+#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */
+#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
+#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */
+#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */
+#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */
+#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */
+#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */
+#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */
+#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */
+#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */
+#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */
+#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */
+#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */
+#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */
+#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */
+#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */
+#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */
+#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */
+#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */
+#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */
+#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */
+#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */
+#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */
+#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */
+
+#endif /* K210_SYSCTL_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef RESET_K210_SYSCTL_H
+#define RESET_K210_SYSCTL_H
+
+#define K210_RST_ROM 0
+#define K210_RST_DMA 1
+#define K210_RST_AI 2
+#define K210_RST_DVP 3
+#define K210_RST_FFT 4
+#define K210_RST_GPIO 5
+#define K210_RST_SPI0 6
+#define K210_RST_SPI1 7
+#define K210_RST_SPI2 8
+#define K210_RST_SPI3 9
+#define K210_RST_I2S0 10
+#define K210_RST_I2S1 11
+#define K210_RST_I2S2 12
+#define K210_RST_I2C0 13
+#define K210_RST_I2C1 14
+#define K210_RST_I2C2 15
+#define K210_RST_UART1 16
+#define K210_RST_UART2 17
+#define K210_RST_UART3 18
+#define K210_RST_AES 19
+#define K210_RST_FPIOA 20
+#define K210_RST_TIMER0 21
+#define K210_RST_TIMER1 22
+#define K210_RST_TIMER2 23
+#define K210_RST_WDT0 24
+#define K210_RST_WDT1 25
+#define K210_RST_SHA 26
+#define K210_RST_RTC 29
+
+#endif /* RESET_K210_SYSCTL_H */
/* Root node */
extern efi_handle_t efi_root;
+/* Set to EFI_SUCCESS when initialized */
+extern efi_status_t efi_obj_list_initialized;
+
/* EFI system partition */
extern struct efi_system_partition {
enum if_type if_type;
#ifdef CONFIG_LOADADDR
"loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=1\0"
-#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
#endif
*/
int do_fs_type(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+/**
+ * do_fs_types - List supported filesystems.
+ *
+ * @cmdtp: Command information for fstypes
+ * @flag: Command flags (CMD_FLAG_...)
+ * @argc: Number of arguments
+ * @argv: List of arguments
+ * @return result (see enum command_ret_t)
+ */
+int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+
#endif /* _FS_H */
* Maximum digest size for all algorithms we support. Having this value
* avoids a malloc() or C99 local declaration in common/cmd_hash.c.
*/
+#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#define HASH_MAX_DIGEST_SIZE 64
+#else
#define HASH_MAX_DIGEST_SIZE 32
+#endif
enum {
HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1
#define CONFIG_FIT_ENABLE_SHA256_SUPPORT
+#define CONFIG_FIT_ENABLE_SHA384_SUPPORT
+#define CONFIG_FIT_ENABLE_SHA512_SUPPORT
#define CONFIG_SHA1
#define CONFIG_SHA256
+#define CONFIG_SHA384
+#define CONFIG_SHA512
#define IMAGE_ENABLE_IGNORE 0
#define IMAGE_INDENT_STRING ""
#define IMAGE_ENABLE_SHA256 0
#endif
+#if defined(CONFIG_FIT_ENABLE_SHA384_SUPPORT) || \
+ defined(CONFIG_SPL_SHA384_SUPPORT)
+#define IMAGE_ENABLE_SHA384 1
+#else
+#define IMAGE_ENABLE_SHA384 0
+#endif
+
+#if defined(CONFIG_FIT_ENABLE_SHA512_SUPPORT) || \
+ defined(CONFIG_SPL_SHA512_SUPPORT)
+#define IMAGE_ENABLE_SHA512 1
+#else
+#define IMAGE_ENABLE_SHA512 0
+#endif
+
#endif /* IMAGE_ENABLE_FIT */
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
IH_COMP_LZMA, /* lzma Compression Used */
IH_COMP_LZO, /* lzo Compression Used */
IH_COMP_LZ4, /* lz4 Compression Used */
+ IH_COMP_ZSTD, /* zstd Compression Used */
IH_COMP_COUNT,
};
__attribute__ ((noreturn));
#endif
+/* Print a numeric value (for use in arch_print_bdinfo()) */
+void bdinfo_print_num(const char *name, ulong value);
+
+/* Print a clock speed in MHz */
+void bdinfo_print_mhz(const char *name, unsigned long hz);
+
+/* Show arch-specific information for the 'bd' command */
+void arch_print_bdinfo(void);
+
#endif /* __ASSEMBLY__ */
/* Put only stuff here that the assembler can digest */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+#ifndef K210_BYPASS_H
+#define K210_BYPASS_H
+
+#include <clk.h>
+
+struct k210_bypass {
+ struct clk clk;
+ struct clk **children; /* Clocks to reparent */
+ struct clk **saved_parents; /* Parents saved over en-/dis-able */
+ struct clk *bypassee; /* Clock to bypass */
+ const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */
+ struct clk *alt; /* Clock to set children to when bypassing */
+ size_t child_count;
+};
+
+#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk)
+
+int k210_bypass_set_children(struct clk *clk, struct clk **children,
+ size_t child_count);
+struct clk *k210_register_bypass_struct(const char *name,
+ const char *parent_name,
+ struct k210_bypass *bypass);
+struct clk *k210_register_bypass(const char *name, const char *parent_name,
+ struct clk *bypassee,
+ const struct clk_ops *bypassee_ops,
+ struct clk *alt);
+#endif /* K210_BYPASS_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef K210_CLK_H
+#define K210_CLK_H
+
+#define LOG_CATEGORY UCLASS_CLK
+#include <linux/types.h>
+#include <linux/clk-provider.h>
+
+static inline struct clk *k210_clk_gate(const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 bit_idx)
+{
+ return clk_register_gate(NULL, name, parent_name, 0, reg, bit_idx, 0,
+ NULL);
+}
+
+static inline struct clk *k210_clk_half(const char *name,
+ const char *parent_name)
+{
+ return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 2);
+}
+
+static inline struct clk *k210_clk_div(const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_register_divider(NULL, name, parent_name, 0, reg, shift,
+ width, 0);
+}
+
+#endif /* K210_CLK_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+#ifndef K210_PLL_H
+#define K210_PLL_H
+
+#include <clk.h>
+#include <test/export.h>
+
+#define K210_PLL_CLKR GENMASK(3, 0)
+#define K210_PLL_CLKF GENMASK(9, 4)
+#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
+#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
+#define K210_PLL_RESET BIT(20)
+#define K210_PLL_PWRD BIT(21) /* PoWeReD */
+#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
+#define K210_PLL_BYPASS BIT(23)
+#define K210_PLL_TEST BIT(24)
+#define K210_PLL_EN BIT(25)
+#define K210_PLL_TEST_EN BIT(26)
+
+#define K210_PLL_LOCK 0
+#define K210_PLL_CLEAR_SLIP 2
+#define K210_PLL_TEST_OUT 3
+
+struct k210_pll {
+ struct clk clk;
+ void __iomem *reg; /* Base PLL register */
+ void __iomem *lock; /* Common PLL lock register */
+ u8 shift; /* Offset of bits in lock register */
+ u8 width; /* Width of lock bits to test against */
+};
+
+#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk)
+
+struct k210_pll_config {
+ u8 r;
+ u8 f;
+ u8 od;
+};
+
+#ifdef CONFIG_UNIT_TEST
+TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
+ struct k210_pll_config *best);
+#define nop()
+#endif
+
+extern const struct clk_ops k210_pll_ops;
+
+struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
+ struct k210_pll *pll);
+struct clk *k210_register_pll(const char *name, const char *parent_name,
+ void __iomem *reg, void __iomem *lock, u8 shift,
+ u8 width);
+
+#endif /* K210_PLL_H */
-#ifndef __LINUX_COMPILER_H
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPILER_TYPES_H
#error "Please don't include <linux/compiler-clang.h> directly, include <linux/compiler.h> instead."
#endif
-/* Some compiler specific definitions are overwritten here
- * for Clang compiler
- */
+/* Compiler specific definitions for Clang compiler */
-#ifdef uninitialized_var
-#undef uninitialized_var
#define uninitialized_var(x) x = *(&(x))
+
+/* same as gcc, this was present in clang-2.6 so we can assume it works
+ * with any version that can compile the kernel
+ */
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+/* all clang versions usable with the kernel support KASAN ABI version 5 */
+#define KASAN_ABI_VERSION 5
+
+#if __has_feature(address_sanitizer) || __has_feature(hwaddress_sanitizer)
+/* emulate gcc's __SANITIZE_ADDRESS__ flag */
+#define __SANITIZE_ADDRESS__
+#define __no_sanitize_address \
+ __attribute__((no_sanitize("address", "hwaddress")))
+#else
+#define __no_sanitize_address
#endif
+
+/*
+ * Not all versions of clang implement the the type-generic versions
+ * of the builtin overflow checkers. Fortunately, clang implements
+ * __has_builtin allowing us to avoid awkward version
+ * checks. Unfortunately, we don't know which version of gcc clang
+ * pretends to be, so the macro may or may not be defined.
+ */
+#if __has_builtin(__builtin_mul_overflow) && \
+ __has_builtin(__builtin_add_overflow) && \
+ __has_builtin(__builtin_sub_overflow)
+#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
+#endif
+
+/* The following are for compatibility with GCC, from compiler-gcc.h,
+ * and may be redefined here because they should not be shared with other
+ * compilers, like ICC.
+ */
+#define barrier() __asm__ __volatile__("" : : : "memory")
-#ifndef __LINUX_COMPILER_H
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPILER_TYPES_H
#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
#endif
+ __GNUC_MINOR__ * 100 \
+ __GNUC_PATCHLEVEL__)
+#if GCC_VERSION < 40600
+# error Sorry, your compiler is too old - please upgrade it.
+#endif
+
/* Optimization barrier */
/* The "volatile" is due to gcc bugs */
-#define barrier() \
- __asm__ __volatile__("": : :"memory")
+#define barrier() __asm__ __volatile__("": : :"memory")
/*
* This version is i.e. to prevent dead stores elimination on @ptr
* where gcc and llvm may behave differently when otherwise using
* clobbered. The issue is as follows: while the inline asm might
* access any memory it wants, the compiler could have fit all of
* @ptr into memory registers instead, and since @ptr never escaped
- * from that, it proofed that the inline asm wasn't touching any of
+ * from that, it proved that the inline asm wasn't touching any of
* it. This version works well with both compilers, i.e. we're telling
* the compiler that the inline asm absolutely may see the contents
* of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
*/
-#define barrier_data(ptr) \
- __asm__ __volatile__("": :"r"(ptr) :"memory")
+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
/*
* This macro obfuscates arithmetic on a variable address so that gcc
(typeof(ptr)) (__ptr + (off)); \
})
-/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-#define OPTIMIZER_HIDE_VAR(var) \
- __asm__ ("" : "=r" (var) : "0" (var))
-
-#ifdef __CHECKER__
-#define __must_be_array(a) 0
-#else
-/* &a[0] degrades to a pointer: a different type from an array */
-#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-#endif
-
-/*
- * Force always-inline if the user requests it so via the .config,
- * or if gcc is too old:
- */
-#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
- !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-#define inline inline __attribute__((always_inline)) notrace
-#define __inline__ __inline__ __attribute__((always_inline)) notrace
-#define __inline __inline __attribute__((always_inline)) notrace
-#else
-/* A lot of inline functions can cause havoc with function tracing */
-#define inline inline notrace
-#define __inline__ __inline__ notrace
-#define __inline __inline notrace
-#endif
-
-#define __always_inline inline __attribute__((always_inline))
-#define noinline __attribute__((noinline))
-
-#define __deprecated __attribute__((deprecated))
-#define __packed __attribute__((packed))
-#define __weak __attribute__((weak))
-#define __alias(symbol) __attribute__((alias(#symbol)))
-
/*
- * it doesn't make sense on ARM (currently the only user of __naked)
- * to trace naked functions because then mcount is called without
- * stack and frame pointer being set up and there is no chance to
- * restore the lr register to the value before mcount was called.
- *
- * The asm() bodies of naked functions often depend on standard calling
- * conventions, therefore they must be noinline and noclone.
- *
- * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
- * See GCC PR44290.
- */
-#define __naked __attribute__((naked)) noinline __noclone notrace
-
-#define __noreturn __attribute__((noreturn))
-
-/*
- * From the GCC manual:
- *
- * Many functions have no effects except the return value and their
- * return value depends only on the parameters and/or global
- * variables. Such a function can be subject to common subexpression
- * elimination and loop optimization just as an arithmetic operator
- * would be.
- * [...]
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
*/
-#define __pure __attribute__((pure))
-#define __aligned(x) __attribute__((aligned(x)))
-#define __printf(a, b) __attribute__((format(printf, a, b)))
-#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-#define __attribute_const__ __attribute__((__const__))
-#define __maybe_unused __attribute__((unused))
-#define __always_unused __attribute__((unused))
-
-/* gcc version specific checks */
-
-#if GCC_VERSION < 30200
-# error Sorry, your compiler is too old - please upgrade it.
-#endif
-
-#if GCC_VERSION < 30300
-# define __used __attribute__((__unused__))
-#else
-# define __used __attribute__((__used__))
-#endif
-
-#ifdef CONFIG_GCOV_KERNEL
-# if GCC_VERSION < 30400
-# error "GCOV profiling support for gcc versions below 3.4 not included"
-# endif /* __GNUC_MINOR__ */
-#endif /* CONFIG_GCOV_KERNEL */
+#define uninitialized_var(x) x = x
-#if GCC_VERSION >= 30400
-#define __must_check __attribute__((warn_unused_result))
+#ifdef CONFIG_RETPOLINE
+#define __noretpoline __attribute__((__indirect_branch__("keep")))
#endif
-#if GCC_VERSION >= 40000
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-/* GCC 4.1.[01] miscompiles __weak */
-#ifdef __KERNEL__
-# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
-# error Your version of gcc miscompiles the __weak directive
-# endif
-#endif
+#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-#define __used __attribute__((__used__))
-#define __compiler_offsetof(a, b) \
- __builtin_offsetof(a, b)
+#define __compiletime_warning(message) __attribute__((__warning__(message)))
+#define __compiletime_error(message) __attribute__((__error__(message)))
-#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
+#if defined(LATENT_ENTROPY_PLUGIN) && !defined(__CHECKER__)
+#define __latent_entropy __attribute__((latent_entropy))
#endif
-#if GCC_VERSION >= 40300
-/* Mark functions as cold. gcc will assume any path leading to a call
- * to them will be unlikely. This means a lot of manual unlikely()s
- * are unnecessary now for any paths leading to the usual suspects
- * like BUG(), printk(), panic() etc. [but let's keep them for now for
- * older compilers]
- *
- * Early snapshots of gcc 4.3 don't support this and we can't detect this
- * in the preprocessor, but we can live with this because they're unreleased.
- * Maketime probing would be overkill here.
+/*
+ * calling noreturn functions, __builtin_unreachable() and __builtin_trap()
+ * confuse the stack allocation in gcc, leading to overly large stack
+ * frames, see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
*
- * gcc also has a __attribute__((__hot__)) to move hot functions into
- * a special section, but I don't see any sense in this right now in
- * the kernel context
+ * Adding an empty inline assembly before it works around the problem
*/
-#define __cold __attribute__((__cold__))
-
-#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+#define barrier_before_unreachable() asm volatile("")
-#ifndef __CHECKER__
-# define __compiletime_warning(message) __attribute__((warning(message)))
-# define __compiletime_error(message) __attribute__((error(message)))
-#endif /* __CHECKER__ */
-#endif /* GCC_VERSION >= 40300 */
-
-#if GCC_VERSION >= 40500
/*
* Mark a position in code as unreachable. This can be used to
* suppress control flow warnings after asm blocks that transfer
* control elsewhere.
- *
- * Early snapshots of gcc 4.5 don't support this and we can't detect
- * this in the preprocessor, but we can live with this because they're
- * unreleased. Really, we need to have autoconf for the kernel.
- */
-#define unreachable() __builtin_unreachable()
-
-/* Mark a function definition as prohibited from being cloned. */
-#define __noclone __attribute__((__noclone__))
-
-#endif /* GCC_VERSION >= 40500 */
-
-#if GCC_VERSION >= 40600
-/*
- * When used with Link Time Optimization, gcc can optimize away C functions or
- * variables which are referenced only from assembly code. __visible tells the
- * optimizer that something else uses this function or variable, thus preventing
- * this.
*/
-#define __visible __attribute__((externally_visible))
-#endif
-
+#define unreachable() \
+ do { \
+ annotate_unreachable(); \
+ barrier_before_unreachable(); \
+ __builtin_unreachable(); \
+ } while (0)
-#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-/*
- * __assume_aligned(n, k): Tell the optimizer that the returned
- * pointer can be assumed to be k modulo n. The second argument is
- * optional (default 0), so we use a variadic macro to make the
- * shorthand.
- *
- * Beware: Do not apply this to functions which may return
- * ERR_PTRs. Also, it is probably unwise to apply it to functions
- * returning extra information in the low bits (but in that case the
- * compiler should see some alignment anyway, when the return value is
- * massaged by 'flags = ptr & 3; ptr &= ~3;').
- */
-#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
+#if defined(RANDSTRUCT_PLUGIN) && !defined(__CHECKER__)
+#define __randomize_layout __attribute__((randomize_layout))
+#define __no_randomize_layout __attribute__((no_randomize_layout))
+/* This anon struct can add padding, so only enable it under randstruct. */
+#define randomized_struct_fields_start struct {
+#define randomized_struct_fields_end } __randomize_layout;
#endif
/*
*/
#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-#if GCC_VERSION >= 40400
+/*
+ * sparse (__CHECKER__) pretends to be gcc, but can't do constant
+ * folding in __builtin_bswap*() (yet), so don't set these for it.
+ */
+#if defined(CONFIG_ARCH_USE_BUILTIN_BSWAP) && !defined(__CHECKER__)
#define __HAVE_BUILTIN_BSWAP32__
#define __HAVE_BUILTIN_BSWAP64__
-#endif
-#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600)
+#if GCC_VERSION >= 40800
#define __HAVE_BUILTIN_BSWAP16__
#endif
-#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP && !__CHECKER__ */
-#if GCC_VERSION >= 50000
+#if GCC_VERSION >= 70000
+#define KASAN_ABI_VERSION 5
+#elif GCC_VERSION >= 50000
#define KASAN_ABI_VERSION 4
#elif GCC_VERSION >= 40902
#define KASAN_ABI_VERSION 3
#endif
-#if GCC_VERSION >= 40902
-/*
- * Tell the compiler that address safety instrumentation (KASAN)
- * should not be applied to that function.
- * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
- */
+#if __has_attribute(__no_sanitize_address__)
#define __no_sanitize_address __attribute__((no_sanitize_address))
+#else
+#define __no_sanitize_address
#endif
-#endif /* gcc version >= 40000 specific checks */
-
-#if !defined(__noclone)
-#define __noclone /* not needed */
-#endif
-
-#if !defined(__no_sanitize_address)
-#define __no_sanitize_address
+#if GCC_VERSION >= 50100
+#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
#endif
/*
- * A trick to suppress uninitialized variable warning without generating any
- * code
+ * Turn individual warnings and errors on and off locally, depending
+ * on version.
*/
-#define uninitialized_var(x) x = x
+#define __diag_GCC(version, severity, s) \
+ __diag_GCC_ ## version(__diag_GCC_ ## severity s)
+
+/* Severity used in pragma directives */
+#define __diag_GCC_ignore ignored
+#define __diag_GCC_warn warning
+#define __diag_GCC_error error
+
+#define __diag_str1(s) #s
+#define __diag_str(s) __diag_str1(s)
+#define __diag(s) _Pragma(__diag_str(GCC diagnostic s))
+
+#if GCC_VERSION >= 80000
+#define __diag_GCC_8(s) __diag(s)
+#else
+#define __diag_GCC_8(s)
+#endif
+
+#define __no_fgcse __attribute__((optimize("-fno-gcse")))
-#ifndef __LINUX_COMPILER_H
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPILER_TYPES_H
#error "Please don't include <linux/compiler-intel.h> directly, include <linux/compiler.h> instead."
#endif
#ifdef __ECC
-/* Some compiler specific definitions are overwritten here
- * for Intel ECC compiler
- */
+/* Compiler specific definitions for Intel ECC compiler */
#include <asm/intrinsics.h>
/* Intel ECC compiler doesn't support gcc specific asm stmts.
* It uses intrinsics to do the equivalent things.
*/
-#undef barrier
-#undef barrier_data
-#undef RELOC_HIDE
-#undef OPTIMIZER_HIDE_VAR
#define barrier() __memory_barrier()
#define barrier_data(ptr) barrier()
*/
#define OPTIMIZER_HIDE_VAR(var) barrier()
-/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */
-#define __must_be_array(a) 0
-
#endif
-#ifndef __HAVE_BUILTIN_BSWAP16__
/* icc has this, but it's called _bswap16 */
#define __HAVE_BUILTIN_BSWAP16__
#define __builtin_bswap16 _bswap16
-#endif
-
+/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_COMPILER_H
#define __LINUX_COMPILER_H
-#ifndef __ASSEMBLY__
+#include <linux/compiler_types.h>
-#ifdef __CHECKER__
-# define __user __attribute__((noderef, address_space(1)))
-# define __kernel __attribute__((address_space(0)))
-# define __safe __attribute__((safe))
-# define __force __attribute__((force))
-# define __nocast __attribute__((nocast))
-# define __iomem __attribute__((noderef, address_space(2)))
-# define __must_hold(x) __attribute__((context(x,1,1)))
-# define __acquires(x) __attribute__((context(x,0,1)))
-# define __releases(x) __attribute__((context(x,1,0)))
-# define __acquire(x) __context__(x,1)
-# define __release(x) __context__(x,-1)
-# define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0)
-# define __percpu __attribute__((noderef, address_space(3)))
-# define __pmem __attribute__((noderef, address_space(5)))
-#ifdef CONFIG_SPARSE_RCU_POINTER
-# define __rcu __attribute__((noderef, address_space(4)))
-#else
-# define __rcu
-#endif
-extern void __chk_user_ptr(const volatile void __user *);
-extern void __chk_io_ptr(const volatile void __iomem *);
-#else
-# define __user
-# define __kernel
-# define __safe
-# define __force
-# define __nocast
-# define __iomem
-# define __chk_user_ptr(x) (void)0
-# define __chk_io_ptr(x) (void)0
-# define __builtin_warning(x, y...) (1)
-# define __must_hold(x)
-# define __acquires(x)
-# define __releases(x)
-# define __acquire(x) (void)0
-# define __release(x) (void)0
-# define __cond_lock(x,c) (c)
-# define __percpu
-# define __rcu
-# define __pmem
-#endif
-
-/* Indirect macros required for expanded argument pasting, eg. __LINE__. */
-#define ___PASTE(a,b) a##b
-#define __PASTE(a,b) ___PASTE(a,b)
+#ifndef __ASSEMBLY__
#ifdef __KERNEL__
-#ifdef __GNUC__
-#include <linux/compiler-gcc.h>
-#endif
-
-#if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__)
-#define notrace __attribute__((hotpatch(0,0)))
-#else
-#define notrace __attribute__((no_instrument_function))
-#endif
-
-/* Intel compiler defines __GNUC__. So we will overwrite implementations
- * coming from above header files here
- */
-#ifdef __INTEL_COMPILER
-# include <linux/compiler-intel.h>
-#endif
-
-/* Clang compiler defines __GNUC__. So we will overwrite implementations
- * coming from above header files here
- */
-#ifdef __clang__
-#include <linux/compiler-clang.h>
-#endif
-
-/*
- * Generic compiler-dependent macros required for kernel
- * build go below this comment. Actual compiler/compiler version
- * specific implementations come from the above header files
- */
-
-struct ftrace_branch_data {
- const char *func;
- const char *file;
- unsigned line;
- union {
- struct {
- unsigned long correct;
- unsigned long incorrect;
- };
- struct {
- unsigned long miss;
- unsigned long hit;
- };
- unsigned long miss_hit[2];
- };
-};
-
/*
* Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code
* to disable branch tracing on a per file basis.
*/
#if defined(CONFIG_TRACE_BRANCH_PROFILING) \
&& !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__)
-void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+void ftrace_likely_update(struct ftrace_likely_data *f, int val,
+ int expect, int is_constant);
#define likely_notrace(x) __builtin_expect(!!(x), 1)
#define unlikely_notrace(x) __builtin_expect(!!(x), 0)
-#define __branch_check__(x, expect) ({ \
- int ______r; \
- static struct ftrace_branch_data \
- __attribute__((__aligned__(4))) \
- __attribute__((section("_ftrace_annotated_branch"))) \
+#define __branch_check__(x, expect, is_constant) ({ \
+ long ______r; \
+ static struct ftrace_likely_data \
+ __aligned(4) \
+ __section(_ftrace_annotated_branch) \
______f = { \
- .func = __func__, \
- .file = __FILE__, \
- .line = __LINE__, \
+ .data.func = __func__, \
+ .data.file = __FILE__, \
+ .data.line = __LINE__, \
}; \
- ______r = likely_notrace(x); \
- ftrace_likely_update(&______f, ______r, expect); \
+ ______r = __builtin_expect(!!(x), expect); \
+ ftrace_likely_update(&______f, ______r, \
+ expect, is_constant); \
______r; \
})
* written by Daniel Walker.
*/
# ifndef likely
-# define likely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1))
+# define likely(x) (__branch_check__(x, 1, __builtin_constant_p(x)))
# endif
# ifndef unlikely
-# define unlikely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0))
+# define unlikely(x) (__branch_check__(x, 0, __builtin_constant_p(x)))
# endif
#ifdef CONFIG_PROFILE_ALL_BRANCHES
* "Define 'is'", Bill Clinton
* "Define 'if'", Steven Rostedt
*/
-#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
-#define __trace_if(cond) \
- if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
- ({ \
- int ______r; \
- static struct ftrace_branch_data \
- __attribute__((__aligned__(4))) \
- __attribute__((section("_ftrace_branch"))) \
- ______f = { \
- .func = __func__, \
- .file = __FILE__, \
- .line = __LINE__, \
- }; \
- ______r = !!(cond); \
- ______f.miss_hit[______r]++; \
- ______r; \
- }))
+#define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
+
+#define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
+
+#define __trace_if_value(cond) ({ \
+ static struct ftrace_branch_data \
+ __aligned(4) \
+ __section(_ftrace_branch) \
+ __if_trace = { \
+ .func = __func__, \
+ .file = __FILE__, \
+ .line = __LINE__, \
+ }; \
+ (cond) ? \
+ (__if_trace.miss_hit[1]++,1) : \
+ (__if_trace.miss_hit[0]++,0); \
+})
+
#endif /* CONFIG_PROFILE_ALL_BRANCHES */
#else
# define barrier_data(ptr) barrier()
#endif
+/* workaround for GCC PR82365 if needed */
+#ifndef barrier_before_unreachable
+# define barrier_before_unreachable() do { } while (0)
+#endif
+
/* Unreachable code */
+#ifdef CONFIG_STACK_VALIDATION
+/*
+ * These macros help objtool understand GCC code flow for unreachable code.
+ * The __COUNTER__ based labels are a hack to make each instance of the macros
+ * unique, to convince GCC not to merge duplicate inline asm statements.
+ */
+#define annotate_reachable() ({ \
+ asm volatile("%c0:\n\t" \
+ ".pushsection .discard.reachable\n\t" \
+ ".long %c0b - .\n\t" \
+ ".popsection\n\t" : : "i" (__COUNTER__)); \
+})
+#define annotate_unreachable() ({ \
+ asm volatile("%c0:\n\t" \
+ ".pushsection .discard.unreachable\n\t" \
+ ".long %c0b - .\n\t" \
+ ".popsection\n\t" : : "i" (__COUNTER__)); \
+})
+#define ASM_UNREACHABLE \
+ "999:\n\t" \
+ ".pushsection .discard.unreachable\n\t" \
+ ".long 999b - .\n\t" \
+ ".popsection\n\t"
+
+/* Annotate a C jump table to allow objtool to follow the code flow */
+#define __annotate_jump_table __section(.rodata..c_jump_table)
+
+#else
+#define annotate_reachable()
+#define annotate_unreachable()
+#define __annotate_jump_table
+#endif
+
+#ifndef ASM_UNREACHABLE
+# define ASM_UNREACHABLE
+#endif
#ifndef unreachable
-# define unreachable() do { } while (1)
+# define unreachable() do { \
+ annotate_unreachable(); \
+ __builtin_unreachable(); \
+} while (0)
+#endif
+
+/*
+ * KENTRY - kernel entry point
+ * This can be used to annotate symbols (functions or data) that are used
+ * without their linker symbol being referenced explicitly. For example,
+ * interrupt vector handlers, or functions in the kernel image that are found
+ * programatically.
+ *
+ * Not required for symbols exported with EXPORT_SYMBOL, or initcalls. Those
+ * are handled in their own way (with KEEP() in linker scripts).
+ *
+ * KENTRY can be avoided if the symbols in question are marked as KEEP() in the
+ * linker script. For example an architecture could KEEP() its entire
+ * boot/exception vector code rather than annotate each function and data.
+ */
+#ifndef KENTRY
+# define KENTRY(sym) \
+ extern typeof(sym) sym; \
+ static const unsigned long __kentry_##sym \
+ __used \
+ __section("___kentry" "+" #sym ) \
+ = (unsigned long)&sym;
#endif
#ifndef RELOC_HIDE
#endif
#ifndef OPTIMIZER_HIDE_VAR
-#define OPTIMIZER_HIDE_VAR(var) barrier()
+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
+#define OPTIMIZER_HIDE_VAR(var) \
+ __asm__ ("" : "=r" (var) : "0" (var))
#endif
/* Not-quite-unique ID. */
#ifdef CONFIG_KASAN
/*
- * This function is not 'inline' because __no_sanitize_address confilcts
+ * We can't declare function 'inline' because __no_sanitize_address confilcts
* with inlining. Attempt to inline it may cause a build failure.
* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
* '__maybe_unused' allows us to avoid defined-but-not-used warnings.
*/
-static __no_sanitize_address __maybe_unused
-void __read_once_size_nocheck(const volatile void *p, void *res, int size)
-{
- __READ_ONCE_SIZE;
-}
+# define __no_kasan_or_inline __no_sanitize_address notrace __maybe_unused
#else
-static __always_inline
+# define __no_kasan_or_inline __always_inline
+#endif
+
+static __no_kasan_or_inline
void __read_once_size_nocheck(const volatile void *p, void *res, int size)
{
__READ_ONCE_SIZE;
}
-#endif
static __always_inline void __write_once_size(volatile void *p, void *res, int size)
{
/*
* Prevent the compiler from merging or refetching reads or writes. The
* compiler is also forbidden from reordering successive instances of
- * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the
- * compiler is aware of some particular ordering. One way to make the
- * compiler aware of ordering is to put the two invocations of READ_ONCE,
- * WRITE_ONCE or ACCESS_ONCE() in different C statements.
+ * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some
+ * particular ordering. One way to make the compiler aware of ordering is to
+ * put the two invocations of READ_ONCE or WRITE_ONCE in different C
+ * statements.
*
- * In contrast to ACCESS_ONCE these two macros will also work on aggregate
- * data types like structs or unions. If the size of the accessed data
- * type exceeds the word size of the machine (e.g., 32 bits or 64 bits)
- * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a
- * compile-time warning.
+ * These two macros will also work on aggregate data types like structs or
+ * unions. If the size of the accessed data type exceeds the word size of
+ * the machine (e.g., 32 bits or 64 bits) READ_ONCE() and WRITE_ONCE() will
+ * fall back to memcpy(). There's at least two memcpy()s: one for the
+ * __builtin_memcpy() and then one for the macro doing the copy of variable
+ * - '__u' allocated on the stack.
*
* Their two major use cases are: (1) Mediating communication between
* process-level code and irq/NMI handlers, all running on the same CPU,
- * and (2) Ensuring that the compiler does not fold, spindle, or otherwise
+ * and (2) Ensuring that the compiler does not fold, spindle, or otherwise
* mutilate accesses that either do not require ordering or that interact
* with an explicit memory barrier or atomic instruction that provides the
* required ordering.
*/
#define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0)
+static __no_kasan_or_inline
+unsigned long read_word_at_a_time(const void *addr)
+{
+ return *(unsigned long *)addr;
+}
+
#define WRITE_ONCE(x, val) \
({ \
union { typeof(x) __val; char __c[1]; } __u = \
__u.__val; \
})
-/**
- * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering
- * @cond: boolean expression to wait for
- *
- * Equivalent to using smp_load_acquire() on the condition variable but employs
- * the control dependency of the wait to reduce the barrier on many platforms.
- *
- * The control dependency provides a LOAD->STORE order, the additional RMB
- * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,
- * aka. ACQUIRE.
- */
-#define smp_cond_acquire(cond) do { \
- while (!(cond)) \
- cpu_relax(); \
- smp_rmb(); /* ctrl + rmb := acquire */ \
-} while (0)
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-/*
- * Allow us to mark functions as 'deprecated' and have gcc emit a nice
- * warning for each use, in hopes of speeding the functions removal.
- * Usage is:
- * int __deprecated foo(void)
- */
-#ifndef __deprecated
-# define __deprecated /* unimplemented */
-#endif
-
-#ifdef MODULE
-#define __deprecated_for_modules __deprecated
-#else
-#define __deprecated_for_modules
-#endif
-
-#ifndef __must_check
-#define __must_check
-#endif
-
-#ifndef CONFIG_ENABLE_MUST_CHECK
-#undef __must_check
-#define __must_check
-#endif
-#ifndef CONFIG_ENABLE_WARN_DEPRECATED
-#undef __deprecated
-#undef __deprecated_for_modules
-#define __deprecated
-#define __deprecated_for_modules
-#endif
-
-/*
- * Allow us to avoid 'defined but not used' warnings on functions and data,
- * as well as force them to be emitted to the assembly file.
- *
- * As of gcc 3.4, static functions that are not marked with attribute((used))
- * may be elided from the assembly file. As of gcc 3.4, static data not so
- * marked will not be elided, but this may change in a future gcc version.
- *
- * NOTE: Because distributions shipped with a backported unit-at-a-time
- * compiler in gcc 3.3, we must define __used to be __attribute__((used))
- * for gcc >=3.3 instead of 3.4.
- *
- * In prior versions of gcc, such functions and data would be emitted, but
- * would be warned about except with attribute((unused)).
- *
- * Mark functions that are referenced only in inline assembly as __used so
- * the code is emitted even though it appears to be unreferenced.
- */
-#ifndef __used
-# define __used /* unimplemented */
-#endif
-
-#ifndef __maybe_unused
-# define __maybe_unused /* unimplemented */
-#endif
-
-#ifndef __always_unused
-# define __always_unused /* unimplemented */
-#endif
-
-#ifndef noinline
-#define noinline
-#endif
-
-/*
- * Rather then using noinline to prevent stack consumption, use
- * noinline_for_stack instead. For documentation reasons.
- */
-#define noinline_for_stack noinline
-
-#ifndef __always_inline
-#define __always_inline inline
-#endif
-
#endif /* __KERNEL__ */
/*
- * From the GCC manual:
- *
- * Many functions do not examine any values except their arguments,
- * and have no effects except the return value. Basically this is
- * just slightly more strict class than the `pure' attribute above,
- * since function is not allowed to read global memory.
- *
- * Note that a function that has pointer arguments and examines the
- * data pointed to must _not_ be declared `const'. Likewise, a
- * function that calls a non-`const' function usually must not be
- * `const'. It does not make sense for a `const' function to return
- * `void'.
- */
-#ifndef __attribute_const__
-# define __attribute_const__ /* unimplemented */
-#endif
-
-/*
- * Tell gcc if a function is cold. The compiler will assume any path
- * directly leading to the call is unlikely.
+ * Force the compiler to emit 'sym' as a symbol, so that we can reference
+ * it from inline assembler. Necessary in case 'sym' could be inlined
+ * otherwise, or eliminated entirely due to lack of references that are
+ * visible to the compiler.
*/
+#define __ADDRESSABLE(sym) \
+ static void * __section(.discard.addressable) __used \
+ __PASTE(__addressable_##sym, __LINE__) = (void *)&sym;
-#ifndef __cold
-#define __cold
-#endif
-
-/* Simple shorthand for a section definition */
-#ifndef __section
-# define __section(S) __attribute__ ((__section__(#S)))
-#endif
-
-#ifndef __visible
-#define __visible
-#endif
-
-/*
- * Assume alignment of return value.
+/**
+ * offset_to_ptr - convert a relative memory offset to an absolute pointer
+ * @off: the address of the 32-bit offset value
*/
-#ifndef __assume_aligned
-#define __assume_aligned(a, ...)
-#endif
-
-
-/* Are two types/vars the same type (ignoring qualifiers)? */
-#ifndef __same_type
-# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
-#endif
+static inline void *offset_to_ptr(const int *off)
+{
+ return (void *)((unsigned long)off + *off);
+}
-/* Is this type a native word size -- useful for atomic operations */
-#ifndef __native_word
-# define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long))
-#endif
+#endif /* __ASSEMBLY__ */
/* Compile time object size, -1 for unknown */
#ifndef __compiletime_object_size
#endif
#ifndef __compiletime_error
# define __compiletime_error(message)
-/*
- * Sparse complains of variable sized arrays due to the temporary variable in
- * __compiletime_assert. Unfortunately we can't just expand it out to make
- * sparse see a constant array size without breaking compiletime_assert on old
- * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether.
- */
-# ifndef __CHECKER__
-# define __compiletime_error_fallback(condition) \
- do { ((void)sizeof(char[1 - 2 * condition])); } while (0)
-# endif
-#endif
-#ifndef __compiletime_error_fallback
-# define __compiletime_error_fallback(condition) do { } while (0)
#endif
#ifdef __OPTIMIZE__
# define __compiletime_assert(condition, msg, prefix, suffix) \
do { \
- bool __cond = !(condition); \
extern void prefix ## suffix(void) __compiletime_error(msg); \
- if (__cond) \
+ if (!(condition)) \
prefix ## suffix(); \
- __compiletime_error_fallback(__cond); \
} while (0)
#else
# define __compiletime_assert(condition, msg, prefix, suffix) do { } while (0)
* compiler has support to do so.
*/
#define compiletime_assert(condition, msg) \
- _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
+ _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
#define compiletime_assert_atomic_type(t) \
compiletime_assert(__native_word(t), \
"Need native word sized stores/loads for atomicity.")
-/*
- * Prevent the compiler from merging or refetching accesses. The compiler
- * is also forbidden from reordering successive instances of ACCESS_ONCE(),
- * but only when the compiler is aware of some particular ordering. One way
- * to make the compiler aware of ordering is to put the two invocations of
- * ACCESS_ONCE() in different C statements.
- *
- * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE
- * on a union member will work as long as the size of the member matches the
- * size of the union and the size is smaller than word size.
- *
- * The major use cases of ACCESS_ONCE used to be (1) Mediating communication
- * between process-level code and irq/NMI handlers, all running on the same CPU,
- * and (2) Ensuring that the compiler does not fold, spindle, or otherwise
- * mutilate accesses that either do not require ordering or that interact
- * with an explicit memory barrier or atomic instruction that provides the
- * required ordering.
- *
- * If possible use READ_ONCE()/WRITE_ONCE() instead.
- */
-#define __ACCESS_ONCE(x) ({ \
- __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \
- (volatile typeof(x) *)&(x); })
-#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x))
-
-/**
- * lockless_dereference() - safely load a pointer for later dereference
- * @p: The pointer to load
- *
- * Similar to rcu_dereference(), but for situations where the pointed-to
- * object's lifetime is managed by something other than RCU. That
- * "something other" might be reference counting or simple immortality.
- */
-#define lockless_dereference(p) \
-({ \
- typeof(p) _________p1 = READ_ONCE(p); \
- smp_read_barrier_depends(); /* Dependency order vs. p above. */ \
- (_________p1); \
-})
+/* &a[0] degrades to a pointer: a different type from an array */
+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */
-#ifdef CONFIG_KPROBES
-# define __kprobes __attribute__((__section__(".kprobes.text")))
-# define nokprobe_inline __always_inline
-#else
-# define __kprobes
-# define nokprobe_inline inline
-#endif
#endif /* __LINUX_COMPILER_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPILER_ATTRIBUTES_H
+#define __LINUX_COMPILER_ATTRIBUTES_H
+
+/*
+ * The attributes in this file are unconditionally defined and they directly
+ * map to compiler attribute(s), unless one of the compilers does not support
+ * the attribute. In that case, __has_attribute is used to check for support
+ * and the reason is stated in its comment ("Optional: ...").
+ *
+ * Any other "attributes" (i.e. those that depend on a configuration option,
+ * on a compiler, on an architecture, on plugins, on other attributes...)
+ * should be defined elsewhere (e.g. compiler_types.h or compiler-*.h).
+ * The intention is to keep this file as simple as possible, as well as
+ * compiler- and version-agnostic (e.g. avoiding GCC_VERSION checks).
+ *
+ * This file is meant to be sorted (by actual attribute name,
+ * not by #define identifier). Use the __attribute__((__name__)) syntax
+ * (i.e. with underscores) to avoid future collisions with other macros.
+ * Provide links to the documentation of each supported compiler, if it exists.
+ */
+
+/*
+ * __has_attribute is supported on gcc >= 5, clang >= 2.9 and icc >= 17.
+ * In the meantime, to support 4.6 <= gcc < 5, we implement __has_attribute
+ * by hand.
+ *
+ * sparse does not support __has_attribute (yet) and defines __GNUC_MINOR__
+ * depending on the compiler used to build it; however, these attributes have
+ * no semantic effects for sparse, so it does not matter. Also note that,
+ * in order to avoid sparse's warnings, even the unsupported ones must be
+ * defined to 0.
+ */
+#ifndef __has_attribute
+# define __has_attribute(x) __GCC4_has_attribute_##x
+# define __GCC4_has_attribute___assume_aligned__ (__GNUC_MINOR__ >= 9)
+# define __GCC4_has_attribute___copy__ 0
+# define __GCC4_has_attribute___designated_init__ 0
+# define __GCC4_has_attribute___externally_visible__ 1
+# define __GCC4_has_attribute___noclone__ 1
+# define __GCC4_has_attribute___nonstring__ 0
+# define __GCC4_has_attribute___no_sanitize_address__ (__GNUC_MINOR__ >= 8)
+# define __GCC4_has_attribute___fallthrough__ 0
+#endif
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-alias-function-attribute
+ */
+#define __alias(symbol) __attribute__((__alias__(#symbol)))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-aligned-function-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-aligned-type-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-aligned-variable-attribute
+ */
+#define __aligned(x) __attribute__((__aligned__(x)))
+#define __aligned_largest __attribute__((__aligned__))
+
+/*
+ * Note: users of __always_inline currently do not write "inline" themselves,
+ * which seems to be required by gcc to apply the attribute according
+ * to its docs (and also "warning: always_inline function might not be
+ * inlinable [-Wattributes]" is emitted).
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-always_005finline-function-attribute
+ * clang: mentioned
+ */
+#define __always_inline inline __attribute__((__always_inline__))
+
+/*
+ * The second argument is optional (default 0), so we use a variadic macro
+ * to make the shorthand.
+ *
+ * Beware: Do not apply this to functions which may return
+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
+ * returning extra information in the low bits (but in that case the
+ * compiler should see some alignment anyway, when the return value is
+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
+ *
+ * Optional: only supported since gcc >= 4.9
+ * Optional: not supported by icc
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-assume_005faligned-function-attribute
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#assume-aligned
+ */
+#if __has_attribute(__assume_aligned__)
+# define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
+#else
+# define __assume_aligned(a, ...)
+#endif
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-cold-function-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Label-Attributes.html#index-cold-label-attribute
+ */
+#define __cold __attribute__((__cold__))
+
+/*
+ * Note the long name.
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-const-function-attribute
+ */
+#define __attribute_const__ __attribute__((__const__))
+
+/*
+ * Optional: only supported since gcc >= 9
+ * Optional: not supported by clang
+ * Optional: not supported by icc
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-copy-function-attribute
+ */
+#if __has_attribute(__copy__)
+# define __copy(symbol) __attribute__((__copy__(symbol)))
+#else
+# define __copy(symbol)
+#endif
+
+/*
+ * Don't. Just don't. See commit 771c035372a0 ("deprecate the '__deprecated'
+ * attribute warnings entirely and for good") for more information.
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-deprecated-function-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-deprecated-type-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-deprecated-variable-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Enumerator-Attributes.html#index-deprecated-enumerator-attribute
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#deprecated
+ */
+#define __deprecated
+
+/*
+ * Optional: only supported since gcc >= 5.1
+ * Optional: not supported by clang
+ * Optional: not supported by icc
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-designated_005finit-type-attribute
+ */
+#if __has_attribute(__designated_init__)
+# define __designated_init __attribute__((__designated_init__))
+#else
+# define __designated_init
+#endif
+
+/*
+ * Optional: not supported by clang
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-externally_005fvisible-function-attribute
+ */
+#if __has_attribute(__externally_visible__)
+# define __visible __attribute__((__externally_visible__))
+#else
+# define __visible
+#endif
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-format-function-attribute
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#format
+ */
+#define __printf(a, b) __attribute__((__format__(printf, a, b)))
+#define __scanf(a, b) __attribute__((__format__(scanf, a, b)))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-gnu_005finline-function-attribute
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#gnu-inline
+ */
+#define __gnu_inline __attribute__((__gnu_inline__))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-malloc-function-attribute
+ */
+#define __malloc __attribute__((__malloc__))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-mode-type-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-mode-variable-attribute
+ */
+#define __mode(x) __attribute__((__mode__(x)))
+
+/*
+ * Optional: not supported by clang
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-noclone-function-attribute
+ */
+#if __has_attribute(__noclone__)
+# define __noclone __attribute__((__noclone__))
+#else
+# define __noclone
+#endif
+
+/*
+ * Add the pseudo keyword 'fallthrough' so case statement blocks
+ * must end with any of these keywords:
+ * break;
+ * fallthrough;
+ * goto <label>;
+ * return [expression];
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html#Statement-Attributes
+ */
+#if __has_attribute(__fallthrough__)
+# define fallthrough __attribute__((__fallthrough__))
+#else
+# define fallthrough do {} while (0) /* fallthrough */
+#endif
+
+/*
+ * Note the missing underscores.
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-noinline-function-attribute
+ * clang: mentioned
+ */
+#define noinline __attribute__((__noinline__))
+
+/*
+ * Optional: only supported since gcc >= 8
+ * Optional: not supported by clang
+ * Optional: not supported by icc
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-nonstring-variable-attribute
+ */
+#if __has_attribute(__nonstring__)
+# define __nonstring __attribute__((__nonstring__))
+#else
+# define __nonstring
+#endif
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-noreturn-function-attribute
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#noreturn
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#id1
+ */
+#define __noreturn __attribute__((__noreturn__))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-packed-type-attribute
+ * clang: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-packed-variable-attribute
+ */
+#define __packed __attribute__((__packed__))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-pure-function-attribute
+ */
+#define __pure __attribute__((__pure__))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-section-function-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-section-variable-attribute
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#section-declspec-allocate
+ */
+#define __section(S) __attribute__((__section__(#S)))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-unused-function-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-unused-type-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-unused-variable-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Label-Attributes.html#index-unused-label-attribute
+ * clang: https://clang.llvm.org/docs/AttributeReference.html#maybe-unused-unused
+ */
+#define __always_unused __attribute__((__unused__))
+#define __maybe_unused __attribute__((__unused__))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-used-function-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-used-variable-attribute
+ */
+#define __used __attribute__((__used__))
+
+/*
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-weak-function-attribute
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-weak-variable-attribute
+ */
+#define __weak __attribute__((__weak__))
+
+#endif /* __LINUX_COMPILER_ATTRIBUTES_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPILER_TYPES_H
+#define __LINUX_COMPILER_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef __CHECKER__
+# define __user __attribute__((noderef, address_space(1)))
+# define __kernel __attribute__((address_space(0)))
+# define __safe __attribute__((safe))
+# define __force __attribute__((force))
+# define __nocast __attribute__((nocast))
+# define __iomem __attribute__((noderef, address_space(2)))
+# define __must_hold(x) __attribute__((context(x,1,1)))
+# define __acquires(x) __attribute__((context(x,0,1)))
+# define __releases(x) __attribute__((context(x,1,0)))
+# define __acquire(x) __context__(x,1)
+# define __release(x) __context__(x,-1)
+# define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0)
+# define __percpu __attribute__((noderef, address_space(3)))
+# define __rcu __attribute__((noderef, address_space(4)))
+# define __private __attribute__((noderef))
+extern void __chk_user_ptr(const volatile void __user *);
+extern void __chk_io_ptr(const volatile void __iomem *);
+# define ACCESS_PRIVATE(p, member) (*((typeof((p)->member) __force *) &(p)->member))
+#else /* __CHECKER__ */
+# ifdef STRUCTLEAK_PLUGIN
+# define __user __attribute__((user))
+# else
+# define __user
+# endif
+# define __kernel
+# define __safe
+# define __force
+# define __nocast
+# define __iomem
+# define __chk_user_ptr(x) (void)0
+# define __chk_io_ptr(x) (void)0
+# define __builtin_warning(x, y...) (1)
+# define __must_hold(x)
+# define __acquires(x)
+# define __releases(x)
+# define __acquire(x) (void)0
+# define __release(x) (void)0
+# define __cond_lock(x,c) (c)
+# define __percpu
+# define __rcu
+# define __private
+# define ACCESS_PRIVATE(p, member) ((p)->member)
+#endif /* __CHECKER__ */
+
+/* Indirect macros required for expanded argument pasting, eg. __LINE__. */
+#define ___PASTE(a,b) a##b
+#define __PASTE(a,b) ___PASTE(a,b)
+
+#ifdef __KERNEL__
+
+/* Attributes */
+#include <linux/compiler_attributes.h>
+
+/* Compiler specific macros. */
+#ifdef __clang__
+#include <linux/compiler-clang.h>
+#elif defined(__INTEL_COMPILER)
+#include <linux/compiler-intel.h>
+#elif defined(__GNUC__)
+/* The above compilers also define __GNUC__, so order is important here. */
+#include <linux/compiler-gcc.h>
+#else
+#error "Unknown compiler"
+#endif
+
+/*
+ * Some architectures need to provide custom definitions of macros provided
+ * by linux/compiler-*.h, and can do so using asm/compiler.h. We include that
+ * conditionally rather than using an asm-generic wrapper in order to avoid
+ * build failures if any C compilation, which will include this file via an
+ * -include argument in c_flags, occurs prior to the asm-generic wrappers being
+ * generated.
+ */
+#ifdef CONFIG_HAVE_ARCH_COMPILER_H
+#include <asm/compiler.h>
+#endif
+
+struct ftrace_branch_data {
+ const char *func;
+ const char *file;
+ unsigned line;
+ union {
+ struct {
+ unsigned long correct;
+ unsigned long incorrect;
+ };
+ struct {
+ unsigned long miss;
+ unsigned long hit;
+ };
+ unsigned long miss_hit[2];
+ };
+};
+
+struct ftrace_likely_data {
+ struct ftrace_branch_data data;
+ unsigned long constant;
+};
+
+#ifdef CONFIG_ENABLE_MUST_CHECK
+#define __must_check __attribute__((__warn_unused_result__))
+#else
+#define __must_check
+#endif
+
+#if defined(CC_USING_HOTPATCH)
+#define notrace __attribute__((hotpatch(0, 0)))
+#elif defined(CC_USING_PATCHABLE_FUNCTION_ENTRY)
+#define notrace __attribute__((patchable_function_entry(0, 0)))
+#else
+#define notrace __attribute__((__no_instrument_function__))
+#endif
+
+/*
+ * it doesn't make sense on ARM (currently the only user of __naked)
+ * to trace naked functions because then mcount is called without
+ * stack and frame pointer being set up and there is no chance to
+ * restore the lr register to the value before mcount was called.
+ */
+#define __naked __attribute__((__naked__)) notrace
+
+#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
+
+/*
+ * Force always-inline if the user requests it so via the .config.
+ * Prefer gnu_inline, so that extern inline functions do not emit an
+ * externally visible function. This makes extern inline behave as per gnu89
+ * semantics rather than c99. This prevents multiple symbol definition errors
+ * of extern inline functions at link time.
+ * A lot of inline functions can cause havoc with function tracing.
+ * Do not use __always_inline here, since currently it expands to inline again
+ * (which would break users of __always_inline).
+ */
+#if !CONFIG_IS_ENABLED(OPTIMIZE_INLINING)
+#define inline inline __attribute__((__always_inline__)) __gnu_inline \
+ __inline_maybe_unused notrace
+#else
+#define inline inline __gnu_inline \
+ __inline_maybe_unused notrace
+#endif
+
+/*
+ * gcc provides both __inline__ and __inline as alternate spellings of
+ * the inline keyword, though the latter is undocumented. New kernel
+ * code should only use the inline spelling, but some existing code
+ * uses __inline__. Since we #define inline above, to ensure
+ * __inline__ has the same semantics, we need this #define.
+ *
+ * However, the spelling __inline is strictly reserved for referring
+ * to the bare keyword.
+ */
+#define __inline__ inline
+
+/*
+ * GCC does not warn about unused static inline functions for -Wunused-function.
+ * Suppress the warning in clang as well by using __maybe_unused, but enable it
+ * for W=1 build. This will allow clang to find unused functions. Remove the
+ * __inline_maybe_unused entirely after fixing most of -Wunused-function warnings.
+ */
+#ifdef KBUILD_EXTRA_WARN1
+#define __inline_maybe_unused
+#else
+#define __inline_maybe_unused __maybe_unused
+#endif
+
+/*
+ * Rather then using noinline to prevent stack consumption, use
+ * noinline_for_stack instead. For documentation reasons.
+ */
+#define noinline_for_stack noinline
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The below symbols may be defined for one or more, but not ALL, of the above
+ * compilers. We don't consider that to be an error, so set them to nothing.
+ * For example, some of them are for compiler specific plugins.
+ */
+#ifndef __latent_entropy
+# define __latent_entropy
+#endif
+
+#ifndef __randomize_layout
+# define __randomize_layout __designated_init
+#endif
+
+#ifndef __no_randomize_layout
+# define __no_randomize_layout
+#endif
+
+#ifndef randomized_struct_fields_start
+# define randomized_struct_fields_start
+# define randomized_struct_fields_end
+#endif
+
+#ifndef asm_volatile_goto
+#define asm_volatile_goto(x...) asm goto(x)
+#endif
+
+#ifdef CONFIG_CC_HAS_ASM_INLINE
+#define asm_inline asm __inline
+#else
+#define asm_inline asm
+#endif
+
+#ifndef __no_fgcse
+# define __no_fgcse
+#endif
+
+/* Are two types/vars the same type (ignoring qualifiers)? */
+#define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
+
+/* Is this type a native word size -- useful for atomic operations */
+#define __native_word(t) \
+ (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || \
+ sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long))
+
+/* Helpers for emitting diagnostics in pragmas. */
+#ifndef __diag
+#define __diag(string)
+#endif
+
+#ifndef __diag_GCC
+#define __diag_GCC(version, severity, string)
+#endif
+
+#define __diag_push() __diag(push)
+#define __diag_pop() __diag(pop)
+
+#define __diag_ignore(compiler, version, option, comment) \
+ __diag_ ## compiler(version, ignore, option)
+#define __diag_warn(compiler, version, option, comment) \
+ __diag_ ## compiler(version, warn, option)
+#define __diag_error(compiler, version, option, comment) \
+ __diag_ ## compiler(version, error, option)
+
+#endif /* __LINUX_COMPILER_TYPES_H */
*/
int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len);
-/* get a random source port */
-unsigned int random_port(void);
-
/**
* update_tftp - Update firmware over TFTP (via DFU)
*
int asym_pause;
};
+/**
+ * phy_read - Convenience function for reading a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to read
+ * @return: value for success or negative errno for failure
+ */
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
struct mii_dev *bus = phydev->bus;
return bus->read(bus, phydev->addr, devad, regnum);
}
+/**
+ * phy_write - Convenience function for writing a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @val: value to write to @regnum
+ * @return: 0 for success or negative errno for failure
+ */
static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
u16 val)
{
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+/**
+ * phy_mmd_start_indirect - Convenience function for writing MMD registers
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @return: None
+ */
static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
int regnum)
{
(devad | MII_MMD_CTRL_NOINCR));
}
+/**
+ * phy_read_mmd - Convenience function for reading a register
+ * from an MMD on a given PHY.
+ * @phydev: The phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: The register on the MMD to read
+ * @return: Value for success or negative errno for failure
+ */
static inline int phy_read_mmd(struct phy_device *phydev, int devad,
int regnum)
{
return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
}
+/**
+ * phy_write_mmd - Convenience function for writing a register
+ * on an MMD on a given PHY.
+ * @phydev: The phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: The register on the MMD to read
+ * @val: value to write to @regnum
+ * @return: 0 for success or negative errno for failure
+ */
static inline int phy_write_mmd(struct phy_device *phydev, int devad,
int regnum, u16 val)
{
return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
}
+/**
+ * phy_set_bits_mmd - Convenience function for setting bits in a register
+ * on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @val: bits to set
+ * @return: 0 for success or negative errno for failure
+ */
+static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
+ u32 regnum, u16 val)
+{
+ int value, ret;
+
+ value = phy_read_mmd(phydev, devad, regnum);
+ if (value < 0)
+ return value;
+
+ value |= val;
+
+ ret = phy_write_mmd(phydev, devad, regnum, value);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * phy_clear_bits_mmd - Convenience function for clearing bits in a register
+ * on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @val: bits to clear
+ * @return: 0 for success or negative errno for failure
+ */
+static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
+ u32 regnum, u16 val)
+{
+ int value, ret;
+
+ value = phy_read_mmd(phydev, devad, regnum);
+ if (value < 0)
+ return value;
+
+ value &= ~val;
+
+ ret = phy_write_mmd(phydev, devad, regnum, value);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
/**
* phy_init() - Initializes the PHY drivers
- *
* This function registers all available PHY drivers
*
- * @return 0 if OK, -ve on error
+ * @return: 0 if OK, -ve on error
*/
int phy_init(void);
/**
* phy_reset() - Resets the specified PHY
- *
* Issues a reset of the PHY and waits for it to complete
*
* @phydev: PHY to reset
- * @return 0 if OK, -ve on error
+ * @return: 0 if OK, -ve on error
*/
int phy_reset(struct phy_device *phydev);
/**
* phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
- *
* The function checks the PHY addresses flagged in phy_mask and returns a
* phy_device pointer if it detects a PHY.
* This function should only be called if just one PHY is expected to be present
* @bus: MII/MDIO bus to scan
* @phy_mask: bitmap of PYH addresses to scan
* @interface: type of MAC-PHY interface
- * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ * @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
phy_interface_t interface);
/**
* phy_connect() - Creates a PHY device for the Ethernet interface
- *
* Creates a PHY device for the PHY at the given address, if one doesn't exist
* already, and associates it with the Ethernet device.
* The function may be called with addr <= 0, in this case addr value is ignored
* @addr: PHY address on MDIO bus
* @dev: Ethernet device to associate to the PHY
* @interface: type of MAC-PHY interface
- * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ * @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
/**
* phy_connect() - Creates a PHY device for the Ethernet interface
- *
* Creates a PHY device for the PHY at the given address, if one doesn't exist
* already, and associates it with the Ethernet device.
* The function may be called with addr <= 0, in this case addr value is ignored
* @addr: PHY address on MDIO bus
* @dev: Ethernet device to associate to the PHY
* @interface: type of MAC-PHY interface
- * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ * @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
* phy_get_interface_by_name() - Look up a PHY interface name
*
* @str: PHY interface name, e.g. "mii"
- * @return PHY_INTERFACE_MODE_... value, or -1 if not found
+ * @return: PHY_INTERFACE_MODE_... value, or -1 if not found
*/
int phy_get_interface_by_name(const char *str);
* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
* is RGMII (all variants)
* @phydev: the phy_device struct
+ * @return: true if MII bus is RGMII or false if it is not
*/
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
* is SGMII (all variants)
* @phydev: the phy_device struct
+ * @return: true if MII bus is SGMII or false if it is not
*/
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
#define SPI_DEFAULT_WORDLEN 8
-#ifdef CONFIG_DM_SPI
+#if CONFIG_IS_ENABLED(DM_SPI)
/* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */
struct dm_spi_bus {
uint max_hz;
* @flags: Indication of SPI flags.
*/
struct spi_slave {
-#ifdef CONFIG_DM_SPI
+#if CONFIG_IS_ENABLED(DM_SPI)
struct udevice *dev; /* struct spi_slave is dev->parentdata */
uint max_hz;
uint speed;
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs);
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
/**
* Activate a SPI chipselect.
* This function is provided by the board code when using a driver
return ret < 0 ? ret : din[1];
}
-#ifdef CONFIG_DM_SPI
+#if CONFIG_IS_ENABLED(DM_SPI)
/**
* struct spi_cs_info - Information about a bus chip select
/* Access the serial operations for a device */
#define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
-#ifdef CONFIG_DM_SPI_FLASH
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
/**
* spi_flash_read_dm() - Read data from SPI flash
*
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef TEST_EXPORT_H
+#define TEST_EXPORT_H
+
+/* Declare something static, unless we are doing unit tests */
+#ifdef CONFIG_UNIT_TEST
+#define TEST_STATIC
+#else
+#define TEST_STATIC static
+#endif
+
+#endif /* TEST_EXPORT_H */
#include <image.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
/**
* hash_calculate() - Calculate hash over the data
--- /dev/null
+#ifndef _SHA512_H
+#define _SHA512_H
+
+#define SHA384_SUM_LEN 48
+#define SHA384_DER_LEN 19
+#define SHA512_SUM_LEN 64
+#define SHA512_DER_LEN 19
+#define SHA512_BLOCK_SIZE 128
+
+#define CHUNKSZ_SHA384 (16 * 1024)
+#define CHUNKSZ_SHA512 (16 * 1024)
+
+typedef struct {
+ uint64_t state[SHA512_SUM_LEN / 8];
+ uint64_t count[2];
+ uint8_t buf[SHA512_BLOCK_SIZE];
+} sha512_context;
+
+extern const uint8_t sha512_der_prefix[];
+
+void sha512_starts(sha512_context * ctx);
+void sha512_update(sha512_context *ctx, const uint8_t *input, uint32_t length);
+void sha512_finish(sha512_context * ctx, uint8_t digest[SHA512_SUM_LEN]);
+
+void sha512_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz);
+
+extern const uint8_t sha384_der_prefix[];
+
+void sha384_starts(sha512_context * ctx);
+void sha384_update(sha512_context *ctx, const uint8_t *input, uint32_t length);
+void sha384_finish(sha512_context * ctx, uint8_t digest[SHA384_SUM_LEN]);
+
+void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz);
+
+
+#endif /* _SHA512_H */
#include <xilinx.h>
#ifdef CONFIG_CMD_ZYNQ_AES
-int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen);
+int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
+ u8 bstype);
#endif
extern struct xilinx_fpga_op zynq_op;
The SHA256 algorithm produces a 256-bit (32-byte) hash value
(digest).
+config SHA512_ALGO
+ bool "Enable SHA512 algorithm"
+ help
+ This option enables support of internal SHA512 algorithm.
+
+config SHA512
+ bool "Enable SHA512 support"
+ depends on SHA512_ALGO
+ help
+ This option enables support of hashing using SHA512 algorithm.
+ The hash is calculated in software.
+ The SHA512 algorithm produces a 512-bit (64-byte) hash value
+ (digest).
+
+config SHA384
+ bool "Enable SHA384 support"
+ depends on SHA512_ALGO
+ help
+ This option enables support of hashing using SHA384 algorithm.
+ The hash is calculated in software.
+ The SHA384 algorithm produces a 384-bit (48-byte) hash value
+ (digest).
+
config SHA_HW_ACCEL
bool "Enable hashing using hardware"
help
obj-$(CONFIG_$(SPL_)RSA) += rsa/
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SHA256) += sha256.o
+obj-$(CONFIG_SHA512_ALGO) += sha512.o
obj-$(CONFIG_$(SPL_)ZLIB) += zlib/
obj-$(CONFIG_$(SPL_)ZSTD) += zstd/
select HAVE_BLOCK_DEVICE
select REGEX
imply CFB_CONSOLE_ANSI
+ imply FAT
+ imply FAT_WRITE
imply USB_KEYBOARD_FN_KEYS
imply VIDEO_ANSI
help
* Copyright (c) 2017 Rob Clark
*/
+#define LOG_CATEGORY LOGC_EFI
+
#include <common.h>
#include <charset.h>
#include <log.h>
if (lo.attributes & LOAD_OPTION_ACTIVE) {
u32 attributes;
- debug("%s: trying to load \"%ls\" from %pD\n",
- __func__, lo.label, lo.file_path);
+ log_debug("%s: trying to load \"%ls\" from %pD\n",
+ __func__, lo.label, lo.file_path);
ret = EFI_CALL(efi_load_image(true, efi_root, lo.file_path,
NULL, 0, handle));
if (ret != EFI_SUCCESS) {
- printf("Loading from Boot%04X '%ls' failed\n", n,
- lo.label);
+ log_warning("Loading %ls '%ls' failed\n",
+ varname, lo.label);
goto error;
}
if (ret != EFI_SUCCESS) {
if (EFI_CALL(efi_unload_image(*handle))
!= EFI_SUCCESS)
- printf("Unloading image failed\n");
+ log_err("Unloading image failed\n");
goto error;
}
- printf("Booting: %ls\n", lo.label);
+ log_info("Booting: %ls\n", lo.label);
} else {
ret = EFI_LOAD_ERROR;
}
if (ret == EFI_SUCCESS || ret == EFI_BUFFER_TOO_SMALL) {
/* BootNext does exist here */
if (ret == EFI_BUFFER_TOO_SMALL || size != sizeof(u16))
- printf("BootNext must be 16-bit integer\n");
+ log_err("BootNext must be 16-bit integer\n");
/* delete BootNext */
ret = EFI_CALL(efi_set_variable(
ret = try_load_entry(bootnext, handle);
if (ret == EFI_SUCCESS)
return ret;
- printf("Loading from BootNext failed, falling back to BootOrder\n");
+ log_warning(
+ "Loading from BootNext failed, falling back to BootOrder\n");
}
} else {
- printf("Deleting BootNext failed\n");
+ log_err("Deleting BootNext failed\n");
}
}
/* BootOrder */
bootorder = get_var(L"BootOrder", &efi_global_variable_guid, &size);
if (!bootorder) {
- printf("BootOrder not defined\n");
+ log_info("BootOrder not defined\n");
ret = EFI_NOT_FOUND;
goto error;
}
num = size / sizeof(uint16_t);
for (i = 0; i < num; i++) {
- debug("%s: trying to load Boot%04X\n", __func__, bootorder[i]);
+ log_debug("%s trying to load Boot%04X\n", __func__,
+ bootorder[i]);
ret = try_load_entry(bootorder[i], handle);
if (ret == EFI_SUCCESS)
break;
authoff = opt->DataDirectory[ctidx].VirtualAddress;
authsz = opt->DataDirectory[ctidx].Size;
} else {
- debug("%s: Invalid optional header magic %x\n", __func__,
- nt->OptionalHeader.Magic);
+ EFI_PRINT("%s: Invalid optional header magic %x\n", __func__,
+ nt->OptionalHeader.Magic);
goto err;
}
nt->FileHeader.SizeOfOptionalHeader);
sorted = calloc(sizeof(IMAGE_SECTION_HEADER *), num_sections);
if (!sorted) {
- debug("%s: Out of memory\n", __func__);
+ EFI_PRINT("%s: Out of memory\n", __func__);
goto err;
}
efi_image_region_add(regs, efi + sorted[i]->PointerToRawData,
efi + sorted[i]->PointerToRawData + size,
0);
- debug("section[%d](%s): raw: 0x%x-0x%x, virt: %x-%x\n",
- i, sorted[i]->Name,
- sorted[i]->PointerToRawData,
- sorted[i]->PointerToRawData + size,
- sorted[i]->VirtualAddress,
- sorted[i]->VirtualAddress
- + sorted[i]->Misc.VirtualSize);
+ EFI_PRINT("section[%d](%s): raw: 0x%x-0x%x, virt: %x-%x\n",
+ i, sorted[i]->Name,
+ sorted[i]->PointerToRawData,
+ sorted[i]->PointerToRawData + size,
+ sorted[i]->VirtualAddress,
+ sorted[i]->VirtualAddress
+ + sorted[i]->Misc.VirtualSize);
bytes_hashed += size;
}
/* 3. Extra data excluding Certificates Table */
if (bytes_hashed + authsz < len) {
- debug("extra data for hash: %zu\n",
- len - (bytes_hashed + authsz));
+ EFI_PRINT("extra data for hash: %lu\n",
+ len - (bytes_hashed + authsz));
efi_image_region_add(regs, efi + bytes_hashed,
efi + len - authsz, 0);
}
/* Return Certificates Table */
if (authsz) {
if (len < authoff + authsz) {
- debug("%s: Size for auth too large: %u >= %zu\n",
- __func__, authsz, len - authoff);
+ EFI_PRINT("%s: Size for auth too large: %u >= %zu\n",
+ __func__, authsz, len - authoff);
goto err;
}
if (authsz < sizeof(*auth)) {
- debug("%s: Size for auth too small: %u < %zu\n",
- __func__, authsz, sizeof(*auth));
+ EFI_PRINT("%s: Size for auth too small: %u < %zu\n",
+ __func__, authsz, sizeof(*auth));
goto err;
}
*auth = efi + authoff;
*auth_len = authsz;
- debug("WIN_CERTIFICATE: 0x%x, size: 0x%x\n", authoff, authsz);
+ EFI_PRINT("WIN_CERTIFICATE: 0x%x, size: 0x%x\n", authoff,
+ authsz);
} else {
*auth = NULL;
*auth_len = 0;
dbx = efi_sigstore_parse_sigdb(L"dbx");
if (!dbx) {
- debug("Getting signature database(dbx) failed\n");
+ EFI_PRINT("Getting signature database(dbx) failed\n");
goto out;
}
db = efi_sigstore_parse_sigdb(L"db");
if (!db) {
- debug("Getting signature database(db) failed\n");
+ EFI_PRINT("Getting signature database(db) failed\n");
goto out;
}
/* try black-list first */
if (efi_signature_verify_with_sigdb(regs, NULL, dbx, NULL)) {
- debug("Image is not signed and rejected by \"dbx\"\n");
+ EFI_PRINT("Image is not signed and rejected by \"dbx\"\n");
goto out;
}
if (efi_signature_verify_with_sigdb(regs, NULL, db, NULL))
ret = true;
else
- debug("Image is not signed and not found in \"db\" or \"dbx\"\n");
+ EFI_PRINT("Image is not signed and not found in \"db\" or \"dbx\"\n");
out:
efi_sigstore_free(db);
if (!efi_image_parse(efi, efi_size, ®s, &wincerts,
&wincerts_len)) {
- debug("Parsing PE executable image failed\n");
+ EFI_PRINT("Parsing PE executable image failed\n");
goto err;
}
*/
db = efi_sigstore_parse_sigdb(L"db");
if (!db) {
- debug("Getting signature database(db) failed\n");
+ EFI_PRINT("Getting signature database(db) failed\n");
goto err;
}
dbx = efi_sigstore_parse_sigdb(L"dbx");
if (!dbx) {
- debug("Getting signature database(dbx) failed\n");
+ EFI_PRINT("Getting signature database(dbx) failed\n");
goto err;
}
(void *)wincert < (void *)wincerts + wincerts_len;
wincert = (void *)wincert + ALIGN(wincert->dwLength, 8)) {
if (wincert->dwLength < sizeof(*wincert)) {
- debug("%s: dwLength too small: %u < %zu\n",
- __func__, wincert->dwLength, sizeof(*wincert));
+ EFI_PRINT("%s: dwLength too small: %u < %zu\n",
+ __func__, wincert->dwLength,
+ sizeof(*wincert));
goto err;
}
msg = pkcs7_parse_message((void *)wincert + sizeof(*wincert),
wincert->dwLength - sizeof(*wincert));
if (IS_ERR(msg)) {
- debug("Parsing image's signature failed\n");
+ EFI_PRINT("Parsing image's signature failed\n");
msg = NULL;
goto err;
}
/* try black-list first */
if (efi_signature_verify_with_sigdb(regs, msg, dbx, NULL)) {
- debug("Signature was rejected by \"dbx\"\n");
+ EFI_PRINT("Signature was rejected by \"dbx\"\n");
goto err;
}
if (!efi_signature_verify_signers(msg, dbx)) {
- debug("Signer was rejected by \"dbx\"\n");
+ EFI_PRINT("Signer was rejected by \"dbx\"\n");
goto err;
} else {
ret = true;
/* try white-list */
if (!efi_signature_verify_with_sigdb(regs, msg, db, &cert)) {
- debug("Verifying signature with \"db\" failed\n");
+ EFI_PRINT("Verifying signature with \"db\" failed\n");
goto err;
} else {
ret = true;
}
if (!efi_signature_verify_cert(cert, dbx)) {
- debug("Certificate was rejected by \"dbx\"\n");
+ EFI_PRINT("Certificate was rejected by \"dbx\"\n");
goto err;
} else {
ret = true;
#define OBJ_LIST_NOT_INITIALIZED 1
-static efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
+efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
/*
* Allow unaligned memory access.
if (ret != EFI_SUCCESS)
goto out;
+ ret = efi_console_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
+
#ifdef CONFIG_PARTITIONS
ret = efi_disk_register();
if (ret != EFI_SUCCESS)
if (ret != EFI_SUCCESS)
goto out;
- ret = efi_console_register();
- if (ret != EFI_SUCCESS)
- goto out;
#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
ret = efi_gop_register();
if (ret != EFI_SUCCESS)
*size = 0;
*hash = calloc(1, SHA256_SUM_LEN);
if (!*hash) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
return false;
}
*size = SHA256_SUM_LEN;
hash_calculate("sha256", regs->reg, regs->num, *hash);
#ifdef DEBUG
- debug("hash calculated:\n");
+ EFI_PRINT("hash calculated:\n");
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
*hash, SHA256_SUM_LEN, false);
#endif
*size = 0;
*hash = calloc(1, SHA256_SUM_LEN);
if (!*hash) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
free(msg);
return false;
}
hash_calculate("sha256", ®tmp, 1, *hash);
#ifdef DEBUG
- debug("hash calculated based on contentInfo:\n");
+ EFI_PRINT("hash calculated based on contentInfo:\n");
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
*hash, SHA256_SUM_LEN, false);
#endif
char c;
bool verified;
- debug("%s: Enter, %p, %p, %p(issuer: %s, subject: %s)\n", __func__,
- regs, ps_info, cert, cert->issuer, cert->subject);
+ EFI_PRINT("%s: Enter, %p, %p, %p(issuer: %s, subject: %s)\n", __func__,
+ regs, ps_info, cert, cert->issuer, cert->subject);
verified = false;
info.checksum = image_get_checksum_algo("sha256,rsa2048");
info.name = "sha256,rsa2048";
} else {
- debug("unknown msg digest algo: %s\n", ps_info->sig->hash_algo);
+ EFI_PRINT("unknown msg digest algo: %s\n",
+ ps_info->sig->hash_algo);
goto out;
}
info.crypto = image_get_crypto_algo(info.name);
info.keylen = cert->pub->keylen;
/* verify signature */
- debug("%s: crypto: %s, signature len:%x\n", __func__,
- info.name, ps_info->sig->s_size);
+ EFI_PRINT("%s: crypto: %s, signature len:%x\n", __func__,
+ info.name, ps_info->sig->s_size);
if (ps_info->aa_set & (1UL << sinfo_has_message_digest)) {
- debug("%s: RSA verify authentication attribute\n", __func__);
+ EFI_PRINT("%s: RSA verify authentication attribute\n",
+ __func__);
/*
* NOTE: This path will be executed only for
* PE image authentication
*/
/* check if hash matches digest first */
- debug("checking msg digest first, len:0x%x\n",
- ps_info->msgdigest_len);
+ EFI_PRINT("checking msg digest first, len:0x%x\n",
+ ps_info->msgdigest_len);
#ifdef DEBUG
- debug("hash in database:\n");
+ EFI_PRINT("hash in database:\n");
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
ps_info->msgdigest, ps_info->msgdigest_len,
false);
/* for authenticated variable */
if (ps_info->msgdigest_len != size ||
memcmp(hash, ps_info->msgdigest, size)) {
- debug("Digest doesn't match\n");
+ EFI_PRINT("Digest doesn't match\n");
free(hash);
goto out;
}
free(hash);
} else {
- debug("Digesting image failed\n");
+ EFI_PRINT("Digesting image failed\n");
goto out;
}
ps_info->sig->s, ps_info->sig->s_size))
verified = true;
} else {
- debug("%s: RSA verify content data\n", __func__);
+ EFI_PRINT("%s: RSA verify content data\n", __func__);
/* against all data */
if (!rsa_verify(&info, regs->reg, regs->num,
ps_info->sig->s, ps_info->sig->s_size))
}
out:
- debug("%s: Exit, verified: %d\n", __func__, verified);
+ EFI_PRINT("%s: Exit, verified: %d\n", __func__, verified);
return verified;
}
struct efi_sig_data *sig_data;
bool verified = false;
- debug("%s: Enter, %p, %p, %p, %p\n", __func__,
- regs, signed_info, siglist, valid_cert);
+ EFI_PRINT("%s: Enter, %p, %p, %p, %p\n", __func__,
+ regs, signed_info, siglist, valid_cert);
if (!signed_info) {
void *hash;
size_t size;
- debug("%s: unsigned image\n", __func__);
+ EFI_PRINT("%s: unsigned image\n", __func__);
/*
* verify based on calculated hash value
* TODO: support other hash algorithms
*/
if (guidcmp(&siglist->sig_type, &efi_guid_sha256)) {
- debug("Digest algorithm is not supported: %pUl\n",
- &siglist->sig_type);
+ EFI_PRINT("Digest algorithm is not supported: %pUl\n",
+ &siglist->sig_type);
goto out;
}
if (!efi_hash_regions(regs, &hash, &size)) {
- debug("Digesting unsigned image failed\n");
+ EFI_PRINT("Digesting unsigned image failed\n");
goto out;
}
for (sig_data = siglist->sig_data_list; sig_data;
sig_data = sig_data->next) {
#ifdef DEBUG
- debug("Msg digest in database:\n");
+ EFI_PRINT("Msg digest in database:\n");
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
sig_data->data, sig_data->size, false);
#endif
goto out;
}
- debug("%s: signed image\n", __func__);
+ EFI_PRINT("%s: signed image\n", __func__);
if (guidcmp(&siglist->sig_type, &efi_guid_cert_x509)) {
- debug("Signature type is not supported: %pUl\n",
- &siglist->sig_type);
+ EFI_PRINT("Signature type is not supported: %pUl\n",
+ &siglist->sig_type);
goto out;
}
cert = x509_cert_parse(sig_data->data, sig_data->size);
if (IS_ERR(cert)) {
- debug("Parsing x509 certificate failed\n");
+ EFI_PRINT("Parsing x509 certificate failed\n");
goto out;
}
}
out:
- debug("%s: Exit, verified: %d\n", __func__, verified);
+ EFI_PRINT("%s: Exit, verified: %d\n", __func__, verified);
return verified;
}
struct efi_signature_store *siglist;
bool verified = false;
- debug("%s: Enter, %p, %p, %p, %p\n", __func__, regs, msg, db, cert);
+ EFI_PRINT("%s: Enter, %p, %p, %p, %p\n", __func__, regs, msg, db, cert);
if (!db)
goto out;
/* for unsigned image */
if (!msg) {
- debug("%s: Verify unsigned image with db\n", __func__);
+ EFI_PRINT("%s: Verify unsigned image with db\n", __func__);
for (siglist = db; siglist; siglist = siglist->next)
if (efi_signature_verify_with_list(regs, NULL, NULL,
siglist, cert)) {
}
/* for signed image or variable */
- debug("%s: Verify signed image with db\n", __func__);
+ EFI_PRINT("%s: Verify signed image with db\n", __func__);
for (info = msg->signed_infos; info; info = info->next) {
- debug("Signed Info: digest algo: %s, pkey algo: %s\n",
- info->sig->hash_algo, info->sig->pkey_algo);
+ EFI_PRINT("Signed Info: digest algo: %s, pkey algo: %s\n",
+ info->sig->hash_algo, info->sig->pkey_algo);
for (siglist = db; siglist; siglist = siglist->next) {
if (efi_signature_verify_with_list(regs, msg, info,
}
out:
- debug("%s: Exit, verified: %d\n", __func__, verified);
+ EFI_PRINT("%s: Exit, verified: %d\n", __func__, verified);
return verified;
}
if (guidcmp(&siglist->sig_type, &efi_guid_cert_x509_sha256)) {
/* TODO: other hash algos */
- debug("Certificate's digest type is not supported: %pUl\n",
- &siglist->sig_type);
+ EFI_PRINT("Certificate's digest type is not supported: %pUl\n",
+ &siglist->sig_type);
goto out;
}
/* calculate hash of TBSCertificate */
msg = calloc(1, SHA256_SUM_LEN);
if (!msg) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
goto out;
}
hash = calloc(1, SHA256_SUM_LEN);
if (!hash) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
goto out;
}
time64_t revoc_time;
bool found = false;
- debug("%s: Enter, %p, %p\n", __func__, dbx, cert);
+ EFI_PRINT("%s: Enter, %p, %p\n", __func__, dbx, cert);
if (!cert)
return false;
}
}
- debug("%s: Exit, verified: %d\n", __func__, !found);
+ EFI_PRINT("%s: Exit, verified: %d\n", __func__, !found);
return !found;
}
struct pkcs7_signed_info *info;
bool found = false;
- debug("%s: Enter, %p, %p\n", __func__, msg, dbx);
+ EFI_PRINT("%s: Enter, %p, %p\n", __func__, msg, dbx);
if (!msg)
goto out;
}
}
out:
- debug("%s: Exit, verified: %d\n", __func__, !found);
+ EFI_PRINT("%s: Exit, verified: %d\n", __func__, !found);
return !found;
}
/**
- * efi_image_region_add - add an entry of region
+ * efi_image_region_add() - add an entry of region
* @regs: Pointer to array of regions
- * @start: Start address of region
- * @end: End address of region
+ * @start: Start address of region (included)
+ * @end: End address of region (excluded)
* @nocheck: flag against overlapped regions
*
- * Take one entry of region [@start, @end] and append it to the list
- * pointed to by @regs. If @nocheck is false, overlapping among entries
- * will be checked first.
+ * Take one entry of region [@start, @end[ and insert it into the list.
+ *
+ * * If @nocheck is false, the list will be sorted ascending by address.
+ * Overlapping entries will not be allowed.
+ *
+ * * If @nocheck is true, the list will be sorted ascending by sequence
+ * of adding the entries. Overlapping is allowed.
*
* Return: status code
*/
int i, j;
if (regs->num >= regs->max) {
- debug("%s: no more room for regions\n", __func__);
+ EFI_PRINT("%s: no more room for regions\n", __func__);
return EFI_OUT_OF_RESOURCES;
}
if (nocheck)
continue;
- if (start > reg->data + reg->size)
+ /* new data after registered region */
+ if (start >= reg->data + reg->size)
continue;
- if ((start >= reg->data && start < reg->data + reg->size) ||
- (end > reg->data && end < reg->data + reg->size)) {
- debug("%s: new region already part of another\n",
- __func__);
- return EFI_INVALID_PARAMETER;
- }
-
- if (start < reg->data && end < reg->data + reg->size) {
+ /* new data preceding registered region */
+ if (end <= reg->data) {
for (j = regs->num - 1; j >= i; j--)
- memcpy(®s->reg[j], ®s->reg[j + 1],
+ memcpy(®s->reg[j + 1], ®s->reg[j],
sizeof(*reg));
break;
}
+
+ /* new data overlapping registered region */
+ EFI_PRINT("%s: new region already part of another\n", __func__);
+ return EFI_INVALID_PARAMETER;
}
reg = ®s->reg[i];
if (esl->signature_list_size
<= (sizeof(*esl) + esl->signature_header_size)) {
- debug("Siglist in wrong format\n");
+ EFI_PRINT("Siglist in wrong format\n");
return NULL;
}
/* Create a head */
siglist = calloc(sizeof(*siglist), 1);
if (!siglist) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
goto err;
}
memcpy(&siglist->sig_type, &esl->signature_type, sizeof(efi_guid_t));
while (left > 0) {
/* Signature must exist if there is remaining data. */
if (left < esl->signature_size) {
- debug("Certificate is too small\n");
+ EFI_PRINT("Certificate is too small\n");
goto err;
}
sig_data = calloc(esl->signature_size
- sizeof(esd->signature_owner), 1);
if (!sig_data) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
goto err;
}
- sizeof(esd->signature_owner);
sig_data->data = malloc(sig_data->size);
if (!sig_data->data) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
goto err;
}
memcpy(sig_data->data, esd->signature_data, sig_data->size);
} else if (!u16_strcmp(name, L"db") || !u16_strcmp(name, L"dbx")) {
vendor = &efi_guid_image_security_database;
} else {
- debug("unknown signature database, %ls\n", name);
+ EFI_PRINT("unknown signature database, %ls\n", name);
return NULL;
}
db_size = 0;
ret = EFI_CALL(efi_get_variable(name, vendor, NULL, &db_size, NULL));
if (ret == EFI_NOT_FOUND) {
- debug("variable, %ls, not found\n", name);
+ EFI_PRINT("variable, %ls, not found\n", name);
sigstore = calloc(sizeof(*sigstore), 1);
return sigstore;
} else if (ret != EFI_BUFFER_TOO_SMALL) {
- debug("Getting variable, %ls, failed\n", name);
+ EFI_PRINT("Getting variable, %ls, failed\n", name);
return NULL;
}
db = malloc(db_size);
if (!db) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
return NULL;
}
ret = EFI_CALL(efi_get_variable(name, vendor, NULL, &db_size, db));
if (ret != EFI_SUCCESS) {
- debug("Getting variable, %ls, failed\n", name);
+ EFI_PRINT("Getting variable, %ls, failed\n", name);
goto err;
}
while (db_size > 0) {
/* List must exist if there is remaining data. */
if (db_size < sizeof(*esl)) {
- debug("variable, %ls, in wrong format\n", name);
+ EFI_PRINT("variable, %ls, in wrong format\n", name);
goto err;
}
if (db_size < esl->signature_list_size) {
- debug("variable, %ls, in wrong format\n", name);
+ EFI_PRINT("variable, %ls, in wrong format\n", name);
goto err;
}
/* Parse a single siglist. */
siglist = efi_sigstore_parse_siglist(esl);
if (!siglist) {
- debug("Parsing signature list of %ls failed\n", name);
+ EFI_PRINT("Parsing signature list of %ls failed\n",
+ name);
goto err;
}
static efi_status_t efi_get_variable_common(u16 *variable_name,
const efi_guid_t *vendor,
u32 *attributes,
- efi_uintn_t *data_size, void *data);
+ efi_uintn_t *data_size, void *data,
+ u64 *timep);
static efi_status_t efi_set_variable_common(u16 *variable_name,
const efi_guid_t *vendor,
{
efi_status_t ret;
- debug("Switching secure state from %d to %d\n", efi_secure_mode, mode);
+ EFI_PRINT("Switching secure state from %d to %d\n", efi_secure_mode,
+ mode);
if (mode == EFI_MODE_DEPLOYED) {
ret = efi_set_secure_state(1, 0, 0, 1);
size = 0;
ret = efi_get_variable_common(L"PK", &efi_global_variable_guid,
- NULL, &size, NULL);
+ NULL, &size, NULL, NULL);
if (ret == EFI_BUFFER_TOO_SMALL) {
if (IS_ENABLED(CONFIG_EFI_SECURE_BOOT))
mode = EFI_MODE_USER;
* TODO:
* The header should be composed in a more refined manner.
*/
- debug("Makeshift prefix added to authentication data\n");
+ EFI_PRINT("Makeshift prefix added to authentication data\n");
ebuflen = sizeof(pkcs7_hdr) + buflen;
if (ebuflen <= 0x7f) {
- debug("Data is too short\n");
+ EFI_PRINT("Data is too short\n");
return NULL;
}
ebuf = malloc(ebuflen);
if (!ebuf) {
- debug("Out of memory\n");
+ EFI_PRINT("Out of memory\n");
return NULL;
}
if (guidcmp(&auth->auth_info.cert_type, &efi_guid_cert_type_pkcs7))
goto err;
+ memcpy(×tamp, &auth->time_stamp, sizeof(timestamp));
+ if (timestamp.pad1 || timestamp.nanosecond || timestamp.timezone ||
+ timestamp.daylight || timestamp.pad2)
+ goto err;
+
*data += sizeof(auth->time_stamp) + auth->auth_info.hdr.dwLength;
*data_size -= (sizeof(auth->time_stamp)
+ auth->auth_info.hdr.dwLength);
- memcpy(×tamp, &auth->time_stamp, sizeof(timestamp));
memset(&tm, 0, sizeof(tm));
tm.tm_year = timestamp.year;
tm.tm_mon = timestamp.month;
auth->auth_info.hdr.dwLength
- sizeof(auth->auth_info));
if (!var_sig) {
- debug("Parsing variable's signature failed\n");
+ EFI_PRINT("Parsing variable's signature failed\n");
goto err;
}
/* verify signature */
if (efi_signature_verify_with_sigdb(regs, var_sig, truststore, NULL)) {
- debug("Verified\n");
+ EFI_PRINT("Verified\n");
} else {
if (truststore2 &&
efi_signature_verify_with_sigdb(regs, var_sig,
truststore2, NULL)) {
- debug("Verified\n");
+ EFI_PRINT("Verified\n");
} else {
- debug("Verifying variable's signature failed\n");
+ EFI_PRINT("Verifying variable's signature failed\n");
goto err;
}
}
/* finished checking */
- *time = rtc_mktime(&tm);
+ *time = new_time;
ret = EFI_SUCCESS;
err:
static efi_status_t efi_get_variable_common(u16 *variable_name,
const efi_guid_t *vendor,
u32 *attributes,
- efi_uintn_t *data_size, void *data)
+ efi_uintn_t *data_size, void *data,
+ u64 *timep)
{
char *native_name;
efi_status_t ret;
val = parse_attr(val, &attr, &time);
+ if (timep)
+ *timep = time;
+
in_size = *data_size;
if ((s = prefix(val, "(blob)"))) {
}
if (!data) {
- debug("Variable with no data shouldn't exist.\n");
+ EFI_PRINT("Variable with no data shouldn't exist.\n");
return EFI_INVALID_PARAMETER;
}
}
if (!data) {
- debug("Variable with no data shouldn't exist.\n");
+ EFI_PRINT("Variable with no data shouldn't exist.\n");
return EFI_INVALID_PARAMETER;
}
data_size, data);
ret = efi_get_variable_common(variable_name, vendor, attributes,
- data_size, data);
+ data_size, data, NULL);
return EFI_EXIT(ret);
}
old_size = 0;
attr = 0;
ret = efi_get_variable_common(variable_name, vendor, &attr,
- &old_size, NULL);
+ &old_size, NULL, &time);
append = !!(attributes & EFI_VARIABLE_APPEND_WRITE);
attributes &= ~(u32)EFI_VARIABLE_APPEND_WRITE;
delete = !append && (!data_size || !attributes);
/* authentication is mandatory */
if (!(attributes &
EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS)) {
- debug("%ls: AUTHENTICATED_WRITE_ACCESS required\n",
- variable_name);
+ EFI_PRINT("%ls: AUTHENTICATED_WRITE_ACCESS required\n",
+ variable_name);
ret = EFI_INVALID_PARAMETER;
goto err;
}
if (attributes &
(EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS |
EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS)) {
- debug("Secure boot is not configured\n");
+ EFI_PRINT("Secure boot is not configured\n");
ret = EFI_INVALID_PARAMETER;
goto err;
}
goto err;
}
ret = efi_get_variable_common(variable_name, vendor,
- &attr, &old_size, old_data);
+ &attr, &old_size, old_data, NULL);
if (ret != EFI_SUCCESS)
goto err;
} else {
/* find a matching node and return the phandle to that */
fdt_for_each_subnode(node, blob, parent) {
const char *name = fdt_get_name(blob, node, NULL);
- phys_addr_t addr, size;
+ fdt_addr_t addr;
+ fdt_size_t size;
- addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+ addr = fdtdec_get_addr_size_fixed(blob, node, "reg", 0, na, ns,
+ &size, false);
if (addr == FDT_ADDR_T_NONE) {
debug("failed to read address/size for %s\n", name);
continue;
}
/* There is still another table active. Return with error. */
- if (htab->table != NULL)
+ if (htab->table != NULL) {
+ __set_errno(EINVAL);
return 0;
+ }
/* Change nel to the first prime number not smaller as nel. */
nel |= 1; /* make odd */
/* allocate memory and zero out */
htab->table = (struct env_entry_node *)calloc(htab->size + 1,
sizeof(struct env_entry_node));
- if (htab->table == NULL)
+ if (htab->table == NULL) {
+ __set_errno(ENOMEM);
return 0;
+ }
/* everything went alright */
return 1;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * FIPS-180-2 compliant SHA-512 and SHA-384 implementation
+ *
+ * SHA-512 code by Jean-Luc Cooke <jlcooke@certainkey.com>
+ *
+ * Copyright (c) Jean-Luc Cooke <jlcooke@certainkey.com>
+ * Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
+ * Copyright (c) 2003 Kyle McMartin <kyle@debian.org>
+ * Copyright (c) 2020 Reuben Dowle <reuben.dowle@4rf.com>
+ */
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <linux/string.h>
+#else
+#include <string.h>
+#endif /* USE_HOSTCC */
+#include <watchdog.h>
+#include <u-boot/sha512.h>
+
+const uint8_t sha384_der_prefix[SHA384_DER_LEN] = {
+ 0x30, 0x41, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+ 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05,
+ 0x00, 0x04, 0x30
+};
+
+const uint8_t sha512_der_prefix[SHA512_DER_LEN] = {
+ 0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+ 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05,
+ 0x00, 0x04, 0x40
+};
+
+#define SHA384_H0 0xcbbb9d5dc1059ed8ULL
+#define SHA384_H1 0x629a292a367cd507ULL
+#define SHA384_H2 0x9159015a3070dd17ULL
+#define SHA384_H3 0x152fecd8f70e5939ULL
+#define SHA384_H4 0x67332667ffc00b31ULL
+#define SHA384_H5 0x8eb44a8768581511ULL
+#define SHA384_H6 0xdb0c2e0d64f98fa7ULL
+#define SHA384_H7 0x47b5481dbefa4fa4ULL
+
+#define SHA512_H0 0x6a09e667f3bcc908ULL
+#define SHA512_H1 0xbb67ae8584caa73bULL
+#define SHA512_H2 0x3c6ef372fe94f82bULL
+#define SHA512_H3 0xa54ff53a5f1d36f1ULL
+#define SHA512_H4 0x510e527fade682d1ULL
+#define SHA512_H5 0x9b05688c2b3e6c1fULL
+#define SHA512_H6 0x1f83d9abfb41bd6bULL
+#define SHA512_H7 0x5be0cd19137e2179ULL
+
+static inline uint64_t Ch(uint64_t x, uint64_t y, uint64_t z)
+{
+ return z ^ (x & (y ^ z));
+}
+
+static inline uint64_t Maj(uint64_t x, uint64_t y, uint64_t z)
+{
+ return (x & y) | (z & (x | y));
+}
+
+static const uint64_t sha512_K[80] = {
+ 0x428a2f98d728ae22ULL, 0x7137449123ef65cdULL, 0xb5c0fbcfec4d3b2fULL,
+ 0xe9b5dba58189dbbcULL, 0x3956c25bf348b538ULL, 0x59f111f1b605d019ULL,
+ 0x923f82a4af194f9bULL, 0xab1c5ed5da6d8118ULL, 0xd807aa98a3030242ULL,
+ 0x12835b0145706fbeULL, 0x243185be4ee4b28cULL, 0x550c7dc3d5ffb4e2ULL,
+ 0x72be5d74f27b896fULL, 0x80deb1fe3b1696b1ULL, 0x9bdc06a725c71235ULL,
+ 0xc19bf174cf692694ULL, 0xe49b69c19ef14ad2ULL, 0xefbe4786384f25e3ULL,
+ 0x0fc19dc68b8cd5b5ULL, 0x240ca1cc77ac9c65ULL, 0x2de92c6f592b0275ULL,
+ 0x4a7484aa6ea6e483ULL, 0x5cb0a9dcbd41fbd4ULL, 0x76f988da831153b5ULL,
+ 0x983e5152ee66dfabULL, 0xa831c66d2db43210ULL, 0xb00327c898fb213fULL,
+ 0xbf597fc7beef0ee4ULL, 0xc6e00bf33da88fc2ULL, 0xd5a79147930aa725ULL,
+ 0x06ca6351e003826fULL, 0x142929670a0e6e70ULL, 0x27b70a8546d22ffcULL,
+ 0x2e1b21385c26c926ULL, 0x4d2c6dfc5ac42aedULL, 0x53380d139d95b3dfULL,
+ 0x650a73548baf63deULL, 0x766a0abb3c77b2a8ULL, 0x81c2c92e47edaee6ULL,
+ 0x92722c851482353bULL, 0xa2bfe8a14cf10364ULL, 0xa81a664bbc423001ULL,
+ 0xc24b8b70d0f89791ULL, 0xc76c51a30654be30ULL, 0xd192e819d6ef5218ULL,
+ 0xd69906245565a910ULL, 0xf40e35855771202aULL, 0x106aa07032bbd1b8ULL,
+ 0x19a4c116b8d2d0c8ULL, 0x1e376c085141ab53ULL, 0x2748774cdf8eeb99ULL,
+ 0x34b0bcb5e19b48a8ULL, 0x391c0cb3c5c95a63ULL, 0x4ed8aa4ae3418acbULL,
+ 0x5b9cca4f7763e373ULL, 0x682e6ff3d6b2b8a3ULL, 0x748f82ee5defb2fcULL,
+ 0x78a5636f43172f60ULL, 0x84c87814a1f0ab72ULL, 0x8cc702081a6439ecULL,
+ 0x90befffa23631e28ULL, 0xa4506cebde82bde9ULL, 0xbef9a3f7b2c67915ULL,
+ 0xc67178f2e372532bULL, 0xca273eceea26619cULL, 0xd186b8c721c0c207ULL,
+ 0xeada7dd6cde0eb1eULL, 0xf57d4f7fee6ed178ULL, 0x06f067aa72176fbaULL,
+ 0x0a637dc5a2c898a6ULL, 0x113f9804bef90daeULL, 0x1b710b35131c471bULL,
+ 0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, 0x3c9ebe0a15c9bebcULL,
+ 0x431d67c49c100d4cULL, 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL,
+ 0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL,
+};
+
+static inline uint64_t ror64(uint64_t word, unsigned int shift)
+{
+ return (word >> (shift & 63)) | (word << ((-shift) & 63));
+}
+
+#define e0(x) (ror64(x,28) ^ ror64(x,34) ^ ror64(x,39))
+#define e1(x) (ror64(x,14) ^ ror64(x,18) ^ ror64(x,41))
+#define s0(x) (ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7))
+#define s1(x) (ror64(x,19) ^ ror64(x,61) ^ (x >> 6))
+
+/*
+ * 64-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_UINT64_BE
+#define GET_UINT64_BE(n,b,i) { \
+ (n) = ( (unsigned long long) (b)[(i) ] << 56 ) \
+ | ( (unsigned long long) (b)[(i) + 1] << 48 ) \
+ | ( (unsigned long long) (b)[(i) + 2] << 40 ) \
+ | ( (unsigned long long) (b)[(i) + 3] << 32 ) \
+ | ( (unsigned long long) (b)[(i) + 4] << 24 ) \
+ | ( (unsigned long long) (b)[(i) + 5] << 16 ) \
+ | ( (unsigned long long) (b)[(i) + 6] << 8 ) \
+ | ( (unsigned long long) (b)[(i) + 7] ); \
+}
+#endif
+#ifndef PUT_UINT64_BE
+#define PUT_UINT64_BE(n,b,i) { \
+ (b)[(i) ] = (unsigned char) ( (n) >> 56 ); \
+ (b)[(i) + 1] = (unsigned char) ( (n) >> 48 ); \
+ (b)[(i) + 2] = (unsigned char) ( (n) >> 40 ); \
+ (b)[(i) + 3] = (unsigned char) ( (n) >> 32 ); \
+ (b)[(i) + 4] = (unsigned char) ( (n) >> 24 ); \
+ (b)[(i) + 5] = (unsigned char) ( (n) >> 16 ); \
+ (b)[(i) + 6] = (unsigned char) ( (n) >> 8 ); \
+ (b)[(i) + 7] = (unsigned char) ( (n) ); \
+}
+#endif
+
+static inline void LOAD_OP(int I, uint64_t *W, const uint8_t *input)
+{
+ GET_UINT64_BE(W[I], input, I*8);
+}
+
+static inline void BLEND_OP(int I, uint64_t *W)
+{
+ W[I & 15] += s1(W[(I-2) & 15]) + W[(I-7) & 15] + s0(W[(I-15) & 15]);
+}
+
+static void
+sha512_transform(uint64_t *state, const uint8_t *input)
+{
+ uint64_t a, b, c, d, e, f, g, h, t1, t2;
+
+ int i;
+ uint64_t W[16];
+
+ /* load the state into our registers */
+ a=state[0]; b=state[1]; c=state[2]; d=state[3];
+ e=state[4]; f=state[5]; g=state[6]; h=state[7];
+
+ /* now iterate */
+ for (i=0; i<80; i+=8) {
+ if (!(i & 8)) {
+ int j;
+
+ if (i < 16) {
+ /* load the input */
+ for (j = 0; j < 16; j++)
+ LOAD_OP(i + j, W, input);
+ } else {
+ for (j = 0; j < 16; j++) {
+ BLEND_OP(i + j, W);
+ }
+ }
+ }
+
+ t1 = h + e1(e) + Ch(e,f,g) + sha512_K[i ] + W[(i & 15)];
+ t2 = e0(a) + Maj(a,b,c); d+=t1; h=t1+t2;
+ t1 = g + e1(d) + Ch(d,e,f) + sha512_K[i+1] + W[(i & 15) + 1];
+ t2 = e0(h) + Maj(h,a,b); c+=t1; g=t1+t2;
+ t1 = f + e1(c) + Ch(c,d,e) + sha512_K[i+2] + W[(i & 15) + 2];
+ t2 = e0(g) + Maj(g,h,a); b+=t1; f=t1+t2;
+ t1 = e + e1(b) + Ch(b,c,d) + sha512_K[i+3] + W[(i & 15) + 3];
+ t2 = e0(f) + Maj(f,g,h); a+=t1; e=t1+t2;
+ t1 = d + e1(a) + Ch(a,b,c) + sha512_K[i+4] + W[(i & 15) + 4];
+ t2 = e0(e) + Maj(e,f,g); h+=t1; d=t1+t2;
+ t1 = c + e1(h) + Ch(h,a,b) + sha512_K[i+5] + W[(i & 15) + 5];
+ t2 = e0(d) + Maj(d,e,f); g+=t1; c=t1+t2;
+ t1 = b + e1(g) + Ch(g,h,a) + sha512_K[i+6] + W[(i & 15) + 6];
+ t2 = e0(c) + Maj(c,d,e); f+=t1; b=t1+t2;
+ t1 = a + e1(f) + Ch(f,g,h) + sha512_K[i+7] + W[(i & 15) + 7];
+ t2 = e0(b) + Maj(b,c,d); e+=t1; a=t1+t2;
+ }
+
+ state[0] += a; state[1] += b; state[2] += c; state[3] += d;
+ state[4] += e; state[5] += f; state[6] += g; state[7] += h;
+
+ /* erase our data */
+ a = b = c = d = e = f = g = h = t1 = t2 = 0;
+}
+
+static void sha512_block_fn(sha512_context *sst, const uint8_t *src,
+ int blocks)
+{
+ while (blocks--) {
+ sha512_transform(sst->state, src);
+ src += SHA512_BLOCK_SIZE;
+ }
+}
+
+static void sha512_base_do_update(sha512_context *sctx,
+ const uint8_t *data,
+ unsigned int len)
+{
+ unsigned int partial = sctx->count[0] % SHA512_BLOCK_SIZE;
+
+ sctx->count[0] += len;
+ if (sctx->count[0] < len)
+ sctx->count[1]++;
+
+ if (unlikely((partial + len) >= SHA512_BLOCK_SIZE)) {
+ int blocks;
+
+ if (partial) {
+ int p = SHA512_BLOCK_SIZE - partial;
+
+ memcpy(sctx->buf + partial, data, p);
+ data += p;
+ len -= p;
+
+ sha512_block_fn(sctx, sctx->buf, 1);
+ }
+
+ blocks = len / SHA512_BLOCK_SIZE;
+ len %= SHA512_BLOCK_SIZE;
+
+ if (blocks) {
+ sha512_block_fn(sctx, data, blocks);
+ data += blocks * SHA512_BLOCK_SIZE;
+ }
+ partial = 0;
+ }
+ if (len)
+ memcpy(sctx->buf + partial, data, len);
+}
+
+static void sha512_base_do_finalize(sha512_context *sctx)
+{
+ const int bit_offset = SHA512_BLOCK_SIZE - sizeof(uint64_t[2]);
+ uint64_t *bits = (uint64_t *)(sctx->buf + bit_offset);
+ unsigned int partial = sctx->count[0] % SHA512_BLOCK_SIZE;
+
+ sctx->buf[partial++] = 0x80;
+ if (partial > bit_offset) {
+ memset(sctx->buf + partial, 0x0, SHA512_BLOCK_SIZE - partial);
+ partial = 0;
+
+ sha512_block_fn(sctx, sctx->buf, 1);
+ }
+
+ memset(sctx->buf + partial, 0x0, bit_offset - partial);
+ bits[0] = cpu_to_be64(sctx->count[1] << 3 | sctx->count[0] >> 61);
+ bits[1] = cpu_to_be64(sctx->count[0] << 3);
+ sha512_block_fn(sctx, sctx->buf, 1);
+}
+
+#if defined(CONFIG_SHA384)
+void sha384_starts(sha512_context * ctx)
+{
+ ctx->state[0] = SHA384_H0;
+ ctx->state[1] = SHA384_H1;
+ ctx->state[2] = SHA384_H2;
+ ctx->state[3] = SHA384_H3;
+ ctx->state[4] = SHA384_H4;
+ ctx->state[5] = SHA384_H5;
+ ctx->state[6] = SHA384_H6;
+ ctx->state[7] = SHA384_H7;
+ ctx->count[0] = ctx->count[1] = 0;
+}
+
+void sha384_update(sha512_context *ctx, const uint8_t *input, uint32_t length)
+{
+ sha512_base_do_update(ctx, input, length);
+}
+
+void sha384_finish(sha512_context * ctx, uint8_t digest[SHA384_SUM_LEN])
+{
+ int i;
+
+ sha512_base_do_finalize(ctx);
+ for(i=0; i<SHA384_SUM_LEN / sizeof(uint64_t); i++)
+ PUT_UINT64_BE(ctx->state[i], digest, i * 8);
+}
+
+/*
+ * Output = SHA-512( input buffer ). Trigger the watchdog every 'chunk_sz'
+ * bytes of input processed.
+ */
+void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz)
+{
+ sha512_context ctx;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ const unsigned char *end;
+ unsigned char *curr;
+ int chunk;
+#endif
+
+ sha384_starts(&ctx);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ curr = (unsigned char *)input;
+ end = input + ilen;
+ while (curr < end) {
+ chunk = end - curr;
+ if (chunk > chunk_sz)
+ chunk = chunk_sz;
+ sha384_update(&ctx, curr, chunk);
+ curr += chunk;
+ WATCHDOG_RESET();
+ }
+#else
+ sha384_update(&ctx, input, ilen);
+#endif
+
+ sha384_finish(&ctx, output);
+}
+
+#endif
+
+#if defined(CONFIG_SHA512)
+void sha512_starts(sha512_context * ctx)
+{
+ ctx->state[0] = SHA512_H0;
+ ctx->state[1] = SHA512_H1;
+ ctx->state[2] = SHA512_H2;
+ ctx->state[3] = SHA512_H3;
+ ctx->state[4] = SHA512_H4;
+ ctx->state[5] = SHA512_H5;
+ ctx->state[6] = SHA512_H6;
+ ctx->state[7] = SHA512_H7;
+ ctx->count[0] = ctx->count[1] = 0;
+}
+
+void sha512_update(sha512_context *ctx, const uint8_t *input, uint32_t length)
+{
+ sha512_base_do_update(ctx, input, length);
+}
+
+void sha512_finish(sha512_context * ctx, uint8_t digest[SHA512_SUM_LEN])
+{
+ int i;
+
+ sha512_base_do_finalize(ctx);
+ for(i=0; i<SHA512_SUM_LEN / sizeof(uint64_t); i++)
+ PUT_UINT64_BE(ctx->state[i], digest, i * 8);
+}
+
+/*
+ * Output = SHA-512( input buffer ). Trigger the watchdog every 'chunk_sz'
+ * bytes of input processed.
+ */
+void sha512_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz)
+{
+ sha512_context ctx;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ const unsigned char *end;
+ unsigned char *curr;
+ int chunk;
+#endif
+
+ sha512_starts(&ctx);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ curr = (unsigned char *)input;
+ end = input + ilen;
+ while (curr < end) {
+ chunk = end - curr;
+ if (chunk > chunk_sz)
+ chunk = chunk_sz;
+ sha512_update(&ctx, curr, chunk);
+ curr += chunk;
+ WATCHDOG_RESET();
+ }
+#else
+ sha512_update(&ctx, input, ilen);
+#endif
+
+ sha512_finish(&ctx, output);
+}
+#endif
return offset / FUNC_SITE_SIZE;
}
-#ifdef CONFIG_EFI_LOADER
+#if defined(CONFIG_EFI_LOADER) && defined(CONFIG_ARM)
/**
* trace_gd - the value of the gd register
*/
-static volatile void *trace_gd;
+static volatile gd_t *trace_gd;
/**
* trace_save_gd() - save the value of the gd register
*/
static void __attribute__((no_instrument_function)) trace_swap_gd(void)
{
- volatile void *temp_gd = trace_gd;
+ volatile gd_t *temp_gd = trace_gd;
trace_gd = gd;
- gd = temp_gd;
+ set_gd(temp_gd);
}
#else
#include <linux/types.h>
#include <linux/string.h>
-#define noinline __attribute__((noinline))
-
/* we use this so that we can do without the ctype library */
#define is_digit(c) ((c) >= '0' && (c) <= '9')
static int dns_our_port;
+/*
+ * make port a little random (1024-17407)
+ * This keeps the math somewhat trivial to compute, and seems to work with
+ * all supported protocols/clients/servers
+ */
+static unsigned int random_port(void)
+{
+ return 1024 + (get_timer(0) % 0x4000);
+}
+
static void dns_send(void)
{
struct header *header;
memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN);
} else if (is_valid_ethaddr(pdata->enetaddr)) {
eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr);
- printf("\nWarning: %s using MAC address from %s\n",
- dev->name, source);
} else if (is_zero_ethaddr(pdata->enetaddr) ||
!is_valid_ethaddr(pdata->enetaddr)) {
#ifdef CONFIG_NET_RANDOM_ETHADDR
net_dev_exists = 1;
net_boot_file_size = 0;
switch (protocol) {
+#ifdef CONFIG_CMD_TFTPBOOT
case TFTPGET:
#ifdef CONFIG_CMD_TFTPPUT
case TFTPPUT:
/* always use ARP to get server ethernet address */
tftp_start(protocol);
break;
+#endif
#ifdef CONFIG_CMD_TFTPSRV
case TFTPSRV:
tftp_start_server();
dhcp_request(); /* Basically same as BOOTP */
break;
#endif
-
+#if defined(CONFIG_CMD_BOOTP)
case BOOTP:
bootp_reset();
net_ip.s_addr = 0;
bootp_request();
break;
-
+#endif
#if defined(CONFIG_CMD_RARP)
case RARP:
rarp_try = 0;
return 1;
}
-#if defined(CONFIG_CMD_NFS) || \
- defined(CONFIG_CMD_SNTP) || \
- defined(CONFIG_CMD_DNS)
-/*
- * make port a little random (1024-17407)
- * This keeps the math somewhat trivial to compute, and seems to work with
- * all supported protocols/clients/servers
- */
-unsigned int random_port(void)
-{
- return 1024 + (get_timer(0) % 0x4000);
-}
-#endif
-
void ip_to_string(struct in_addr x, char *s)
{
x.s_addr = ntohl(x.s_addr);
TFTP_ERR_UNEXPECTED_OPCODE = 4,
TFTP_ERR_UNKNOWN_TRANSFER_ID = 5,
TFTP_ERR_FILE_ALREADY_EXISTS = 6,
+ TFTP_ERR_OPTION_NEGOTIATION = 8,
};
static struct in_addr tftp_remote_ip;
#define STATE_OACK 5
#define STATE_RECV_WRQ 6
#define STATE_SEND_WRQ 7
+#define STATE_INVALID_OPTION 8
/* default TFTP block size */
#define TFTP_BLOCK_SIZE 512
static void show_block_marker(void)
{
+ ulong pos;
+
#ifdef CONFIG_TFTP_TSIZE
if (tftp_tsize) {
- ulong pos = tftp_cur_block * tftp_block_size +
+ pos = tftp_cur_block * tftp_block_size +
tftp_block_wrap_offset;
if (pos > tftp_tsize)
pos = tftp_tsize;
} else
#endif
{
- if (((tftp_cur_block - 1) % 10) == 0)
+ pos = (tftp_cur_block - 1) +
+ (tftp_block_wrap * TFTP_SEQUENCE_SIZE);
+ if ((pos % 10) == 0)
putc('#');
- else if ((tftp_cur_block % (10 * HASHES_PER_LINE)) == 0)
+ else if (((pos + 1) % (10 * HASHES_PER_LINE)) == 0)
puts("\n\t ");
}
}
tftp_block_wrap++;
tftp_block_wrap_offset += tftp_block_size * TFTP_SEQUENCE_SIZE;
timeout_count = 0; /* we've done well, reset the timeout */
- } else {
- show_block_marker();
}
+ show_block_marker();
}
/* The TFTP get or put is complete */
uchar *xp;
int len = 0;
ushort *s;
+ bool err_pkt = false;
/*
* We will always be sending some sort of packet, so
strcpy((char *)pkt, "File too large");
pkt += 14 /*strlen("File too large")*/ + 1;
len = pkt - xp;
+ err_pkt = true;
break;
case STATE_BAD_MAGIC:
strcpy((char *)pkt, "File has bad magic");
pkt += 18 /*strlen("File has bad magic")*/ + 1;
len = pkt - xp;
+ err_pkt = true;
+ break;
+
+ case STATE_INVALID_OPTION:
+ xp = pkt;
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ERROR);
+ *s++ = htons(TFTP_ERR_OPTION_NEGOTIATION);
+ pkt = (uchar *)s;
+ strcpy((char *)pkt, "Option Negotiation Failed");
+ /* strlen("Option Negotiation Failed") + NULL*/
+ pkt += 25 + 1;
+ len = pkt - xp;
+ err_pkt = true;
break;
}
net_send_udp_packet(net_server_ethaddr, tftp_remote_ip,
tftp_remote_port, tftp_our_port, len);
+
+ if (err_pkt)
+ net_set_state(NETLOOP_FAIL);
}
#ifdef CONFIG_CMD_TFTPPUT
__be16 proto;
__be16 *s;
int i;
+ u16 timeout_val_rcvd;
if (dest != tftp_our_port) {
return;
#endif
case TFTP_OACK:
- debug("Got OACK: %s %s\n",
- pkt, pkt + strlen((char *)pkt) + 1);
+ debug("Got OACK: ");
+ for (i = 0; i < len; i++) {
+ if (pkt[i] == '\0')
+ debug(" ");
+ else
+ debug("%c", pkt[i]);
+ }
+ debug("\n");
tftp_state = STATE_OACK;
tftp_remote_port = src;
/*
* something like "len-8" may give a *huge* number
*/
for (i = 0; i+8 < len; i++) {
- if (strcmp((char *)pkt + i, "blksize") == 0) {
+ if (strcasecmp((char *)pkt + i, "blksize") == 0) {
tftp_block_size = (unsigned short)
simple_strtoul((char *)pkt + i + 8,
NULL, 10);
- debug("Blocksize ack: %s, %d\n",
+ debug("Blocksize oack: %s, %d\n",
(char *)pkt + i + 8, tftp_block_size);
+ if (tftp_block_size > tftp_block_size_option) {
+ printf("Invalid blk size(=%d)\n",
+ tftp_block_size);
+ tftp_state = STATE_INVALID_OPTION;
+ }
+ }
+ if (strcasecmp((char *)pkt + i, "timeout") == 0) {
+ timeout_val_rcvd = (unsigned short)
+ simple_strtoul((char *)pkt + i + 8,
+ NULL, 10);
+ debug("Timeout oack: %s, %d\n",
+ (char *)pkt + i + 8, timeout_val_rcvd);
+ if (timeout_val_rcvd != (timeout_ms / 1000)) {
+ printf("Invalid timeout val(=%d s)\n",
+ timeout_val_rcvd);
+ tftp_state = STATE_INVALID_OPTION;
+ }
}
#ifdef CONFIG_TFTP_TSIZE
- if (strcmp((char *)pkt+i, "tsize") == 0) {
+ if (strcasecmp((char *)pkt + i, "tsize") == 0) {
tftp_tsize = simple_strtoul((char *)pkt + i + 6,
NULL, 10);
debug("size = %s, %d\n",
#endif
}
#ifdef CONFIG_CMD_TFTPPUT
- if (tftp_put_active) {
+ if (tftp_put_active && tftp_state == STATE_OACK) {
/* Get ready to send the first block */
tftp_state = STATE_DATA;
tftp_cur_block++;
len -= 2;
tftp_cur_block = ntohs(*(__be16 *)pkt);
- update_block_number();
-
if (tftp_state == STATE_SEND_RRQ)
- debug("Server did not acknowledge timeout option!\n");
+ debug("Server did not acknowledge any options!\n");
if (tftp_state == STATE_SEND_RRQ || tftp_state == STATE_OACK ||
tftp_state == STATE_RECV_WRQ) {
break;
}
+ update_block_number();
tftp_prev_block = tftp_cur_block;
timeout_count_max = tftp_timeout_count_max;
net_set_timeout_handler(timeout_ms, tftp_timeout_handler);
--- /dev/null
+# Kconfig helper macros
+
+# Convenient variables
+comma := ,
+quote := "
+squote := '
+empty :=
+space := $(empty) $(empty)
+dollar := $
+right_paren := )
+left_paren := (
+
+# $(if-success,<command>,<then>,<else>)
+# Return <then> if <command> exits with 0, <else> otherwise.
+if-success = $(shell,{ $(1); } >/dev/null 2>&1 && echo "$(2)" || echo "$(3)")
+
+# $(success,<command>)
+# Return y if <command> exits with 0, n otherwise
+success = $(if-success,$(1),y,n)
+
+# $(cc-option,<flag>)
+# Return y if the compiler supports <flag>, n otherwise
+cc-option = $(success,$(CC) -Werror $(1) -E -x c /dev/null -o /dev/null)
+
+# $(ld-option,<flag>)
+# Return y if the linker supports <flag>, n otherwise
+ld-option = $(success,$(LD) -v $(1))
+
+# gcc version including patch level
+gcc-version := $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed 's/^0*//')
my $typedefsfile = "";
my $u_boot = 0;
my $color = "auto";
-my $allow_c99_comments = 1;
+my $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE
+# git output parsing needs US English output, so first set backtick child process LANGUAGE
+my $git_command ='export LANGUAGE=en_US.UTF-8; git';
+my $tabsize = 8;
sub help {
my ($exitcode) = @_;
if exceeded, warn on patches
requires --strict for use with --file
--min-conf-desc-length=n set the min description length, if shorter, warn
+ --tab-size=n set the number of spaces for tab (default $tabsize)
--root=PATH PATH to the kernel tree root
--no-summary suppress the per-file summary
--mailback only produce a report in case of warnings/errors
'list-types!' => \$list_types,
'max-line-length=i' => \$max_line_length,
'min-conf-desc-length=i' => \$min_conf_desc_length,
+ 'tab-size=i' => \$tabsize,
'root=s' => \$root,
'summary!' => \$summary,
'mailback!' => \$mailback,
die "Invalid color mode: $color\n";
}
+# skip TAB size 1 to avoid additional checks on $tabsize - 1
+die "Invalid TAB size: $tabsize\n" if ($tabsize < 2);
+
sub hash_save_array_words {
my ($hashRef, $arrayRef) = @_;
seq_vprintf|seq_printf|seq_puts
)};
+our $allocFunctions = qr{(?x:
+ (?:(?:devm_)?
+ (?:kv|k|v)[czm]alloc(?:_node|_array)? |
+ kstrdup(?:_const)? |
+ kmemdup(?:_nul)?) |
+ (?:\w+)?alloc_skb(?:_ip_align)? |
+ # dev_alloc_skb/netdev_alloc_skb, et al
+ dma_alloc_coherent
+)};
+
our $signature_tags = qr{(?xi:
Signed-off-by:|
+ Co-developed-by:|
Acked-by:|
Tested-by:|
Reviewed-by:|
}
$mode_perms_search = "(?:${mode_perms_search})";
+our %deprecated_apis = (
+ "synchronize_rcu_bh" => "synchronize_rcu",
+ "synchronize_rcu_bh_expedited" => "synchronize_rcu_expedited",
+ "call_rcu_bh" => "call_rcu",
+ "rcu_barrier_bh" => "rcu_barrier",
+ "synchronize_sched" => "synchronize_rcu",
+ "synchronize_sched_expedited" => "synchronize_rcu_expedited",
+ "call_rcu_sched" => "call_rcu",
+ "rcu_barrier_sched" => "rcu_barrier",
+ "get_state_synchronize_sched" => "get_state_synchronize_rcu",
+ "cond_synchronize_sched" => "cond_synchronize_rcu",
+);
+
+#Create a search pattern for all these strings to speed up a loop below
+our $deprecated_apis_search = "";
+foreach my $entry (keys %deprecated_apis) {
+ $deprecated_apis_search .= '|' if ($deprecated_apis_search ne "");
+ $deprecated_apis_search .= $entry;
+}
+$deprecated_apis_search = "(?:${deprecated_apis_search})";
+
our $mode_perms_world_writable = qr{
S_IWUGO |
S_IWOTH |
}x;
$Type = qr{
$NonptrType
- (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)?
+ (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+){0,4}
(?:\s+$Inline|\s+$Modifier)*
}x;
$TypeMisordered = qr{
$NonptrTypeMisordered
- (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)?
+ (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+){0,4}
(?:\s+$Inline|\s+$Modifier)*
}x;
$Declare = qr{(?:$Storage\s+(?:$Inline\s+)?)?$Type};
}
}
+our %maintained_status = ();
+
sub is_maintained_obsolete {
my ($filename) = @_;
return 0 if (!$tree || !(-e "$root/scripts/get_maintainer.pl"));
- my $status = `perl $root/scripts/get_maintainer.pl --status --nom --nol --nogit --nogit-fallback -f $filename 2>&1`;
+ if (!exists($maintained_status{$filename})) {
+ $maintained_status{$filename} = `perl $root/scripts/get_maintainer.pl --status --nom --nol --nogit --nogit-fallback -f $filename 2>&1`;
+ }
- return $status =~ /obsolete/i;
+ return $maintained_status{$filename} =~ /obsolete/i;
}
sub is_SPDX_License_valid {
$camelcase_seeded = 1;
if (-e ".git") {
- my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`;
+ my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`;
chomp $git_last_include_commit;
$camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit";
} else {
}
if (-e ".git") {
- $files = `git ls-files "include/*.h"`;
+ $files = `${git_command} ls-files "include/*.h"`;
@include_files = split('\n', $files);
}
return ($id, $desc) if ((which("git") eq "") || !(-e ".git"));
- my $output = `git log --no-color --format='%H %s' -1 $commit 2>&1`;
+ my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`;
$output =~ s/^\s*//gm;
my @lines = split("\n", $output);
return ($id, $desc) if ($#lines < 0);
- if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous\./) {
+ if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous/) {
# Maybe one day convert this block of bash into something that returns
# all matching commit ids, but it's very slow...
#
} else {
$git_range = "-1 $commit_expr";
}
- my $lines = `git log --no-color --no-merges --pretty=format:'%H %s' $git_range`;
+ my $lines = `${git_command} log --no-color --no-merges --pretty=format:'%H %s' $git_range`;
foreach my $line (split(/\n/, $lines)) {
$line =~ /^([0-9a-fA-F]{40,40}) (.*)$/;
next if (!defined($1) || !defined($2));
}
my $vname;
+$allow_c99_comments = !defined $ignore_type{"C99_COMMENT_TOLERANCE"};
for my $filename (@ARGV) {
my $FILE;
if ($git) {
my ($formatted_email) = @_;
my $name = "";
+ my $name_comment = "";
my $address = "";
my $comment = "";
$name = trim($name);
$name =~ s/^\"|\"$//g;
+ $name =~ s/(\s*\([^\)]+\))\s*//;
+ if (defined($1)) {
+ $name_comment = trim($1);
+ }
$address = trim($address);
$address =~ s/^\<|\>$//g;
$name = "\"$name\"";
}
- return ($name, $address, $comment);
+ return ($name, $name_comment, $address, $comment);
}
sub format_email {
return $formatted_email;
}
+sub reformat_email {
+ my ($email) = @_;
+
+ my ($email_name, $name_comment, $email_address, $comment) = parse_email($email);
+ return format_email($email_name, $email_address);
+}
+
+sub same_email_addresses {
+ my ($email1, $email2) = @_;
+
+ my ($email1_name, $name1_comment, $email1_address, $comment1) = parse_email($email1);
+ my ($email2_name, $name2_comment, $email2_address, $comment2) = parse_email($email2);
+
+ return $email1_name eq $email2_name &&
+ $email1_address eq $email2_address;
+}
+
sub which {
my ($bin) = @_;
if ($c eq "\t") {
$res .= ' ';
$n++;
- for (; ($n % 8) != 0; $n++) {
+ for (; ($n % $tabsize) != 0; $n++) {
$res .= ' ';
}
next;
sub tabify {
my ($leading) = @_;
- my $source_indent = 8;
+ my $source_indent = $tabsize;
my $max_spaces_before_tab = $source_indent - 1;
my $spaces_to_tab = " " x $source_indent;
return length(expand_tabs(substr($line, 0, $last_openparen))) + 1;
}
+sub get_raw_comment {
+ my ($line, $rawline) = @_;
+ my $comment = '';
+
+ for my $i (0 .. (length($line) - 1)) {
+ if (substr($line, $i, 1) eq "$;") {
+ $comment .= substr($rawline, $i, 1);
+ }
+ }
+
+ return $comment;
+}
+
# Checks specific to U-Boot
sub u_boot_line {
my ($realfile, $line, $herecurr) = @_;
my $is_binding_patch = -1;
my $in_header_lines = $file ? 0 : 1;
my $in_commit_log = 0; #Scanning lines before patch
+ my $has_patch_separator = 0; #Found a --- line
my $has_commit_log = 0; #Encountered lines before patch
my $commit_log_lines = 0; #Number of commit log lines
my $commit_log_possible_stack_dump = 0;
$sline =~ s/$;/ /g; #with comments as spaces
my $rawline = $rawlines[$linenr - 1];
+ my $raw_comment = get_raw_comment($line, $rawline);
# check if it's a mode change, rename or start of a patch
if (!$in_commit_log &&
$author = $1;
$author = encode("utf8", $author) if ($line =~ /=\?utf-8\?/i);
$author =~ s/"//g;
+ $author = reformat_email($author);
}
# Check the patch for a signoff:
- if ($line =~ /^\s*signed-off-by:/i) {
+ if ($line =~ /^\s*signed-off-by:\s*(.*)/i) {
$signoff++;
$in_commit_log = 0;
if ($author ne '') {
- my $l = $line;
- $l =~ s/"//g;
- if ($l =~ /^\s*signed-off-by:\s*\Q$author\E/i) {
- $authorsignoff = 1;
+ if (same_email_addresses($1, $author)) {
+ $authorsignoff = 1;
}
}
}
+# Check for patch separator
+ if ($line =~ /^---$/) {
+ $has_patch_separator = 1;
+ $in_commit_log = 0;
+ }
+
# Check if MAINTAINERS is being updated. If so, there's probably no need to
# emit the "does MAINTAINERS need updating?" message on file add/move/delete
if ($line =~ /^\s*MAINTAINERS\s*\|/) {
}
}
- my ($email_name, $email_address, $comment) = parse_email($email);
+ my ($email_name, $name_comment, $email_address, $comment) = parse_email($email);
my $suggested_email = format_email(($email_name, $email_address));
if ($suggested_email eq "") {
ERROR("BAD_SIGN_OFF",
$dequoted =~ s/" </ </;
# Don't force email to have quotes
# Allow just an angle bracketed address
- if ("$dequoted$comment" ne $email &&
- "<$email_address>$comment" ne $email &&
- "$suggested_email$comment" ne $email) {
+ if (!same_email_addresses($email, $suggested_email)) {
WARN("BAD_SIGN_OFF",
"email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
}
} else {
$signatures{$sig_nospace} = 1;
}
+
+# Check Co-developed-by: immediately followed by Signed-off-by: with same name and email
+ if ($sign_off =~ /^co-developed-by:$/i) {
+ if ($email eq $author) {
+ WARN("BAD_SIGN_OFF",
+ "Co-developed-by: should not be used to attribute nominal patch author '$author'\n" . "$here\n" . $rawline);
+ }
+ if (!defined $lines[$linenr]) {
+ WARN("BAD_SIGN_OFF",
+ "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline);
+ } elsif ($rawlines[$linenr] !~ /^\s*signed-off-by:\s*(.*)/i) {
+ WARN("BAD_SIGN_OFF",
+ "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]);
+ } elsif ($1 ne $email) {
+ WARN("BAD_SIGN_OFF",
+ "Co-developed-by and Signed-off-by: name/email do not match \n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]);
+ }
+ }
}
# Check email subject for common tools that don't need to be mentioned
"A patch subject line should describe the change not the tool that found it\n" . $herecurr);
}
-# Check for unwanted Gerrit info
- if ($in_commit_log && $line =~ /^\s*change-id:/i) {
+# Check for Gerrit Change-Ids not in any patch context
+ if ($realfile eq '' && !$has_patch_separator && $line =~ /^\s*change-id:/i) {
ERROR("GERRIT_CHANGE_ID",
- "Remove Gerrit Change-Id's before submitting upstream.\n" . $herecurr);
+ "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr);
}
# Check if the commit log is in a possible stack dump
($line =~ /^\s*(?:WARNING:|BUG:)/ ||
$line =~ /^\s*\[\s*\d+\.\d{6,6}\s*\]/ ||
# timestamp
- $line =~ /^\s*\[\<[0-9a-fA-F]{8,}\>\]/)) {
- # stack dump address
+ $line =~ /^\s*\[\<[0-9a-fA-F]{8,}\>\]/) ||
+ $line =~ /^(?:\s+\w+:\s+[0-9a-fA-F]+){3,3}/ ||
+ $line =~ /^\s*\#\d+\s*\[[0-9a-fA-F]+\]\s*\w+ at [0-9a-fA-F]+/) {
+ # stack dump address styles
$commit_log_possible_stack_dump = 1;
}
# Check for git id commit length and improperly formed commit descriptions
if ($in_commit_log && !$commit_log_possible_stack_dump &&
- $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink):/i &&
+ $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i &&
$line !~ /^This reverts commit [0-9a-f]{7,40}/ &&
($line =~ /\bcommit\s+[0-9a-f]{5,}\b/i ||
($line =~ /(?:\s|^)[0-9a-f]{12,40}(?:[\s"'\(\[]|$)/i &&
"added, moved or deleted file(s), does MAINTAINERS need updating?\n" . $herecurr);
}
+# Check for adding new DT bindings not in schema format
+ if (!$in_commit_log &&
+ ($line =~ /^new file mode\s*\d+\s*$/) &&
+ ($realfile =~ m@^Documentation/devicetree/bindings/.*\.txt$@)) {
+ WARN("DT_SCHEMA_BINDING_PATCH",
+ "DT bindings should be in DT schema format. See: Documentation/devicetree/writing-schema.rst\n");
+ }
+
# Check for wrappage within a valid hunk of the file
if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
ERROR("CORRUPTED_PATCH",
}
}
+# check for invalid commit id
+ if ($in_commit_log && $line =~ /(^fixes:|\bcommit)\s+([0-9a-f]{6,40})\b/i) {
+ my $id;
+ my $description;
+ ($id, $description) = git_commit_info($2, undef, undef);
+ if (!defined($id)) {
+ WARN("UNKNOWN_COMMIT_ID",
+ "Unknown commit id '$2', maybe rebased or not pulled?\n" . $herecurr);
+ }
+ }
+
# ignore non-hunk lines and lines being removed
next if (!$hunk_line || $line =~ /^-/);
my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g;
my $dt_path = $root . "/Documentation/devicetree/bindings/";
- my $vp_file = $dt_path . "vendor-prefixes.txt";
+ my $vp_file = $dt_path . "vendor-prefixes.yaml";
foreach my $compat (@compats) {
my $compat2 = $compat;
next if $compat !~ /^([a-zA-Z0-9\-]+)\,/;
my $vendor = $1;
- `grep -Eq "^$vendor\\b" $vp_file`;
+ `grep -Eq "\\"\\^\Q$vendor\E,\\.\\*\\":" $vp_file`;
if ( $? >> 8 ) {
WARN("UNDOCUMENTED_DT_STRING",
"DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr);
$comment = '/*';
} elsif ($realfile =~ /\.(c|dts|dtsi)$/) {
$comment = '//';
- } elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc)$/) {
+ } elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc|yaml)$/) {
$comment = '#';
} elsif ($realfile =~ /\.rst$/) {
$comment = '..';
}
+# check SPDX comment style for .[chsS] files
+ if ($realfile =~ /\.[chsS]$/ &&
+ $rawline =~ /SPDX-License-Identifier:/ &&
+ $rawline !~ m@^\+\s*\Q$comment\E\s*@) {
+ WARN("SPDX_LICENSE_TAG",
+ "Improper SPDX comment style for '$realfile', please use '$comment' instead\n" . $herecurr);
+ }
+
if ($comment !~ /^$/ &&
- $rawline !~ /^\+\Q$comment\E SPDX-License-Identifier: /) {
- WARN("SPDX_LICENSE_TAG",
- "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr);
+ $rawline !~ m@^\+\Q$comment\E SPDX-License-Identifier: @) {
+ WARN("SPDX_LICENSE_TAG",
+ "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr);
} elsif ($rawline =~ /(SPDX-License-Identifier: .*)/) {
- my $spdx_license = $1;
- if (!is_SPDX_License_valid($spdx_license)) {
- WARN("SPDX_LICENSE_TAG",
- "'$spdx_license' is not supported in LICENSES/...\n" . $herecurr);
- }
+ my $spdx_license = $1;
+ if (!is_SPDX_License_valid($spdx_license)) {
+ WARN("SPDX_LICENSE_TAG",
+ "'$spdx_license' is not supported in LICENSES/...\n" . $herecurr);
+ }
+ if ($realfile =~ m@^Documentation/devicetree/bindings/@ &&
+ not $spdx_license =~ /GPL-2\.0.*BSD-2-Clause/) {
+ my $msg_level = \&WARN;
+ $msg_level = \&CHK if ($file);
+ if (&{$msg_level}("SPDX_LICENSE_TAG",
+
+ "DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause)\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/SPDX-License-Identifier: .*/SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)/;
+ }
+ }
}
}
}
# check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/);
+# check for using SPDX-License-Identifier on the wrong line number
+ if ($realline != $checklicenseline &&
+ $rawline =~ /\bSPDX-License-Identifier:/ &&
+ substr($line, @-, @+ - @-) eq "$;" x (@+ - @-)) {
+ WARN("SPDX_LICENSE_TAG",
+ "Misplaced SPDX-License-Identifier tag - use line $checklicenseline instead\n" . $herecurr);
+ }
+
# line length limit (with some exclusions)
#
# There are a few types of lines that may extend beyond $max_line_length:
next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/);
# at the beginning of a line any tabs must come first and anything
-# more than 8 must use tabs.
+# more than $tabsize must use tabs.
if ($rawline =~ /^\+\s* \t\s*\S/ ||
$rawline =~ /^\+\s* \s*/) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
"please, no space before tabs\n" . $herevet) &&
$fix) {
while ($fixed[$fixlinenr] =~
- s/(^\+.*) {8,8}\t/$1\t\t/) {}
+ s/(^\+.*) {$tabsize,$tabsize}\t/$1\t\t/) {}
while ($fixed[$fixlinenr] =~
s/(^\+.*) +\t/$1\t/) {}
}
if ($perl_version_ok &&
$sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$)|$Declare\s*$Ident\s*[;=])/) {
my $indent = length($1);
- if ($indent % 8) {
+ if ($indent % $tabsize) {
if (WARN("TABSTOP",
"Statements should start on a tabstop\n" . $herecurr) &&
$fix) {
- $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/8)@e;
+ $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/$tabsize)@e;
}
}
}
my $newindent = $2;
my $goodtabindent = $oldindent .
- "\t" x ($pos / 8) .
- " " x ($pos % 8);
+ "\t" x ($pos / $tabsize) .
+ " " x ($pos % $tabsize);
my $goodspaceindent = $oldindent . " " x $pos;
if ($newindent ne $goodtabindent &&
#print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n";
if ($check && $s ne '' &&
- (($sindent % 8) != 0 ||
+ (($sindent % $tabsize) != 0 ||
($sindent < $indent) ||
($sindent == $indent &&
($s !~ /^\s*(?:\}|\{|else\b)/)) ||
- ($sindent > $indent + 8))) {
+ ($sindent > $indent + $tabsize))) {
WARN("SUSPECT_CODE_INDENT",
"suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n");
}
WARN("STATIC_CONST_CHAR_ARRAY",
"static const char * array should probably be static const char * const\n" .
$herecurr);
- }
+ }
+
+# check for initialized const char arrays that should be static const
+ if ($line =~ /^\+\s*const\s+(char|unsigned\s+char|_*u8|(?:[us]_)?int8_t)\s+\w+\s*\[\s*(?:\w+\s*)?\]\s*=\s*"/) {
+ if (WARN("STATIC_CONST_CHAR_ARRAY",
+ "const array should probably be static const\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/(^.\s*)const\b/${1}static const/;
+ }
+ }
# check for static char foo[] = "bar" declarations.
if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) {
WARN("STATIC_CONST_CHAR_ARRAY",
"static char array declaration should probably be static const char\n" .
$herecurr);
- }
+ }
# check for const <foo> const where <foo> is not a pointer or array type
if ($sline =~ /\bconst\s+($BasicType)\s+const\b/) {
}
# check for function declarations without arguments like "int foo()"
- if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) {
+ if ($line =~ /(\b$Type\s*$Ident)\s*\(\s*\)/) {
if (ERROR("FUNCTION_WITHOUT_ARGS",
"Bad function definition - $1() should probably be $1(void)\n" . $herecurr) &&
$fix) {
"Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr);
}
- if ($line =~ /\bpr_warning\s*\(/) {
- if (WARN("PREFER_PR_LEVEL",
- "Prefer pr_warn(... to pr_warning(...\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\bpr_warning\b/pr_warn/;
- }
- }
-
if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
my $orig = $1;
my $level = lc($orig);
($op eq '>' &&
$ca =~ /<\S+\@\S+$/))
{
- $ok = 1;
+ $ok = 1;
}
# for asm volatile statements
# closing brace should have a space following it when it has anything
# on the line
- if ($line =~ /}(?!(?:,|;|\)))\S/) {
+ if ($line =~ /}(?!(?:,|;|\)|\}))\S/) {
if (ERROR("SPACING",
"space required after that close brace '}'\n" . $herecurr) &&
$fix) {
# conditional.
substr($s, 0, length($c), '');
$s =~ s/\n.*//g;
- $s =~ s/$;//g; # Remove any comments
+ $s =~ s/$;//g; # Remove any comments
if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ &&
$c !~ /}\s*while\s*/)
{
# if and else should not have general statements after it
if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) {
my $s = $1;
- $s =~ s/$;//g; # Remove any comments
+ $s =~ s/$;//g; # Remove any comments
if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) {
ERROR("TRAILING_STATEMENTS",
"trailing statements should be on next line\n" . $herecurr);
while ($line =~ m{($Constant|$Lval)}g) {
my $var = $1;
-#gcc binary extension
- if ($var =~ /^$Binary$/) {
- if (WARN("GCC_BINARY_CONSTANT",
- "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) &&
- $fix) {
- my $hexval = sprintf("0x%x", oct($var));
- $fixed[$fixlinenr] =~
- s/\b$var\b/$hexval/;
- }
- }
-
#CamelCase
if ($var !~ /^$Constant$/ &&
$var =~ /[A-Z][a-z]|[a-z][A-Z]/ &&
#Ignore Page<foo> variants
$var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
-#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show)
- $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/ &&
+#Ignore SI style variants like nS, mV and dB
+#(ie: max_uV, regulator_min_uA_show, RANGE_mA_VALUE)
+ $var !~ /^(?:[a-z0-9_]*|[A-Z0-9_]*)?_?[a-z][A-Z](?:_[a-z0-9_]+|_[A-Z0-9_]+)?$/ &&
#Ignore some three character SI units explicitly, like MiB and KHz
$var !~ /^(?:[a-z_]*?)_?(?:[KMGT]iB|[KMGT]?Hz)(?:_[a-z_]+)?$/) {
while ($var =~ m{($Ident)}g) {
{
}
- # Flatten any obvious string concatentation.
+ # Flatten any obvious string concatenation.
while ($dstat =~ s/($String)\s*$Ident/$1/ ||
$dstat =~ s/$Ident\s*($String)/$1/)
{
next if ($arg =~ /\.\.\./);
next if ($arg =~ /^type$/i);
my $tmp_stmt = $define_stmt;
- $tmp_stmt =~ s/\b(typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
+ $tmp_stmt =~ s/\b(sizeof|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
$tmp_stmt =~ s/\#+\s*$arg\b//g;
$tmp_stmt =~ s/\b$arg\s*\#\#//g;
my $use_cnt = () = $tmp_stmt =~ /\b$arg\b/g;
my ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0);
# print("line: <$line>\nprevline: <$prevline>\ns: <$s>\nc: <$c>\n\n\n");
- if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*(?:devm_)?(?:[kv][czm]alloc(?:_node|_array)?\b|kstrdup|kmemdup|(?:dev_)?alloc_skb)/) {
+ if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*$allocFunctions\s*\(/ &&
+ $s !~ /\b__GFP_NOWARN\b/ ) {
WARN("OOM_MESSAGE",
"Possible unnecessary 'out of memory' message\n" . $hereprev);
}
# ignore udelay's < 10, however
if (! ($delay < 10) ) {
CHK("USLEEP_RANGE",
- "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $herecurr);
+ "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst\n" . $herecurr);
}
if ($delay > 2000) {
WARN("LONG_UDELAY",
if ($line =~ /\bmsleep\s*\((\d+)\);/) {
if ($1 < 20) {
WARN("MSLEEP",
- "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $herecurr);
+ "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst\n" . $herecurr);
}
}
"__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
}
+# Check for __attribute__ section, prefer __section
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $line =~ /\b__attribute__\s*\(\s*\(.*_*section_*\s*\(\s*("[^"]*")/) {
+ my $old = substr($rawline, $-[1], $+[1] - $-[1]);
+ my $new = substr($old, 1, -1);
+ if (WARN("PREFER_SECTION",
+ "__section($new) is preferred over __attribute__((section($old)))\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/;
+ }
+ }
+
# Check for __attribute__ format(printf, prefer __printf
if ($realfile !~ m@\binclude/uapi/@ &&
$line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
for (my $count = $linenr; $count <= $lc; $count++) {
my $specifier;
my $extension;
+ my $qualifier;
my $bad_specifier = "";
my $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0));
$fmt =~ s/%%//g;
- while ($fmt =~ /(\%[\*\d\.]*p(\w))/g) {
+ while ($fmt =~ /(\%[\*\d\.]*p(\w)(\w*))/g) {
$specifier = $1;
$extension = $2;
- if ($extension !~ /[SsBKRraEhMmIiUDdgVCbGNOx]/) {
+ $qualifier = $3;
+ if ($extension !~ /[SsBKRraEehMmIiUDdgVCbGNOxtf]/ ||
+ ($extension eq "f" &&
+ defined $qualifier && $qualifier !~ /^w/)) {
$bad_specifier = $specifier;
last;
}
my $ext_type = "Invalid";
my $use = "";
if ($bad_specifier =~ /p[Ff]/) {
- $ext_type = "Deprecated";
$use = " - use %pS instead";
$use =~ s/pS/ps/ if ($bad_specifier =~ /pf/);
}
my $max = $7;
if ($min eq $max) {
WARN("USLEEP_RANGE",
- "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+ "usleep_range should not use min == max args; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n");
} elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ &&
$min > $max) {
WARN("USLEEP_RANGE",
- "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+ "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n");
}
}
}
# check for function declarations that have arguments without identifier names
+# while avoiding uninitialized_var(x)
if (defined $stat &&
- $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s &&
- $1 ne "void") {
- my $args = trim($1);
+ $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:($Ident)|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s &&
+ (!defined($1) ||
+ (defined($1) && $1 ne "uninitialized_var")) &&
+ $2 ne "void") {
+ my $args = trim($2);
while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) {
my $arg = trim($1);
- if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) {
+ if ($arg =~ /^$Type$/ &&
+ $arg !~ /enum\s+$Ident$/) {
WARN("FUNCTION_ARGUMENTS",
"function definition argument '$arg' should also have an identifier name\n" . $herecurr);
}
}
}
-# check for pointless casting of kmalloc return
- if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) {
+# check for pointless casting of alloc functions
+ if ($line =~ /\*\s*\)\s*$allocFunctions\b/) {
WARN("UNNECESSARY_CASTS",
"unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
}
# alloc style
# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...)
if ($perl_version_ok &&
- $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) {
+ $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k|v)[mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) {
CHK("ALLOC_SIZEOF_STRUCT",
"Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr);
}
}
}
+# check for /* fallthrough */ like comment, prefer fallthrough;
+ my @fallthroughs = (
+ 'fallthrough',
+ '@fallthrough@',
+ 'lint -fallthrough[ \t]*',
+ 'intentional(?:ly)?[ \t]*fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)',
+ '(?:else,?\s*)?FALL(?:S | |-)?THR(?:OUGH|U|EW)[ \t.!]*(?:-[^\n\r]*)?',
+ 'Fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)[ \t.!]*(?:-[^\n\r]*)?',
+ 'fall(?:s | |-)?thr(?:ough|u|ew)[ \t.!]*(?:-[^\n\r]*)?',
+ );
+ if ($raw_comment ne '') {
+ foreach my $ft (@fallthroughs) {
+ if ($raw_comment =~ /$ft/) {
+ my $msg_level = \&WARN;
+ $msg_level = \&CHK if ($file);
+ &{$msg_level}("PREFER_FALLTHROUGH",
+ "Prefer 'fallthrough;' over fallthrough comment\n" . $herecurr);
+ last;
+ }
+ }
+ }
+
# check for switch/default statements without a break;
if ($perl_version_ok &&
defined $stat &&
}
}
-# check for bool bitfields
- if ($sline =~ /^.\s+bool\s*$Ident\s*:\s*\d+\s*;/) {
- WARN("BOOL_BITFIELD",
- "Avoid using bool as bitfield. Prefer bool bitfields as unsigned int or u<8|16|32>\n" . $herecurr);
- }
-
-# check for bool use in .h files
- if ($realfile =~ /\.h$/ &&
- $sline =~ /^.\s+bool\s*$Ident\s*(?::\s*d+\s*)?;/) {
- CHK("BOOL_MEMBER",
- "Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384\n" . $herecurr);
- }
-
# check for semaphores initialized locked
if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
WARN("CONSIDER_COMPLETION",
"please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\n" . $herecurr);
}
+# check for spin_is_locked(), suggest lockdep instead
+ if ($line =~ /\bspin_is_locked\(/) {
+ WARN("USE_LOCKDEP",
+ "Where possible, use lockdep_assert_held instead of assertions based on spin_is_locked\n" . $herecurr);
+ }
+
+# check for deprecated apis
+ if ($line =~ /\b($deprecated_apis_search)\b\s*\(/) {
+ my $deprecated_api = $1;
+ my $new_api = $deprecated_apis{$deprecated_api};
+ WARN("DEPRECATED_API",
+ "Deprecated use of '$deprecated_api', prefer '$new_api' instead\n" . $herecurr);
+ }
+
# check for various structs that are normally const (ops, kgdb, device_tree)
# and avoid what seem like struct definitions 'struct foo {'
if ($line !~ /\bconst\b/ &&
"Using $1 should generally have parentheses around the comparison\n" . $herecurr);
}
+# nested likely/unlikely calls
+ if ($line =~ /\b(?:(?:un)?likely)\s*\(\s*!?\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) {
+ WARN("LIKELY_MISUSE",
+ "nested (un)?likely() calls, $1 already uses unlikely() internally\n" . $herecurr);
+ }
+
# whine mightly about in_atomic
if ($line =~ /\bin_atomic\s*\(/) {
if ($realfile =~ m@^drivers/@) {
"unknown module license " . $extracted_string . "\n" . $herecurr);
}
}
+
+# check for sysctl duplicate constants
+ if ($line =~ /\.extra[12]\s*=\s*&(zero|one|int_max)\b/) {
+ WARN("DUPLICATED_SYSCTL_CONST",
+ "duplicated sysctl range checking value '$1', consider using the shared one in include/linux/sysctl.h\n" . $herecurr);
+ }
}
# If we have no input at all, then there is nothing to report on
CONFIG_EDB93XX_SDCS1
CONFIG_EDB93XX_SDCS2
CONFIG_EDB93XX_SDCS3
-CONFIG_EEPRO100
-CONFIG_EEPRO100_SROM_WRITE
CONFIG_EFLASH_PROTSECTORS
CONFIG_EHCI_DESC_BIG_ENDIAN
CONFIG_EHCI_HCD_INIT_AFTER_RESET
CONFIG_PSRAM_SCFG
CONFIG_PWM
CONFIG_PXA_LCD
-CONFIG_PXA_MMC_GENERIC
CONFIG_PXA_PWR_I2C
CONFIG_PXA_STD_I2C
CONFIG_PXA_VGA
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
CONFIG_SYS_XIMG_LEN
-CONFIG_SYS_ZYNQ_QSPI_WAIT
-CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_i2C_FSL
CONFIG_TAM3517_SETTINGS
CONFIG_TCA642X
CONFIG_X86_REFCODE_ADDR
CONFIG_X86_REFCODE_RUN_ADDR
CONFIG_XGI_XG22_BASE
-CONFIG_XILINX_SPI_IDLE_VAL
CONFIG_XSENGINE
CONFIG_XTFPGA
CONFIG_YAFFSFS_PROVIDE_VALUES
&& (memcmp(s, "/__overlay__", len - 1) == 0)) {
/* /<fragment-name>/__overlay__ */
rel_path = "";
- rel_path_len = 0;
+ rel_path_len = 1; /* Include NUL character */
} else {
/* Symbol refers to something that won't end
* up in the target tree */
}
ret = fdt_setprop_placeholder(fdt, root_sym, name,
- len + (len > 1) + rel_path_len + 1, &p);
+ len + (len > 1) + rel_path_len, &p);
if (ret < 0)
return ret;
buf[len] = '/';
memcpy(buf + len + 1, rel_path, rel_path_len);
- buf[len + 1 + rel_path_len] = '\0';
}
return 0;
obj-$(CONFIG_DM_MDIO) += mdio.o
obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
obj-$(CONFIG_DM_RNG) += rng.o
+obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
+obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
+obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
endif
ut_assertok(net_loop(PING));
ut_asserteq_str("eth@10002000", env_get("ethact"));
- env_set("ethact", "eth1");
+ env_set("ethact", "eth6");
ut_assertok(net_loop(PING));
ut_asserteq_str("eth@10004000", env_get("ethact"));
const char *ethname[DM_TEST_ETH_NUM] = {"eth@10002000", "eth@10003000",
"sbe5", "eth@10004000"};
const char *addrname[DM_TEST_ETH_NUM] = {"ethaddr", "eth5addr",
- "eth3addr", "eth1addr"};
+ "eth3addr", "eth6addr"};
char ethaddr[DM_TEST_ETH_NUM][18];
int i;
/* Invalidate eth1's MAC address */
memset(ethaddr, '\0', sizeof(ethaddr));
- strncpy(ethaddr, env_get("eth1addr"), 17);
- /* Must disable access protection for eth1addr before clearing */
- env_set(".flags", "eth1addr");
- env_set("eth1addr", NULL);
+ strncpy(ethaddr, env_get("eth6addr"), 17);
+ /* Must disable access protection for eth6addr before clearing */
+ env_set(".flags", "eth6addr");
+ env_set("eth6addr", NULL);
retval = _dm_test_eth_rotate1(uts);
/* Restore the env */
- env_set("eth1addr", ethaddr);
+ env_set("eth6addr", ethaddr);
env_set("ethrotate", NULL);
if (!retval) {
ut_assertok(dm_gpio_set_value(desc, 0));
ut_asserteq(0, dm_gpio_get_value(desc));
+ /* Check if lookup for labels work */
+ ut_assertok(gpio_lookup_name("hog_input_active_low", &dev, &offset,
+ &gpio));
+ ut_asserteq_str(dev->name, "base-gpios");
+ ut_asserteq(0, offset);
+ ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 0, gpio);
+ ut_assert(gpio_lookup_name("hog_not_exist", &dev, &offset,
+ &gpio));
+
return 0;
}
DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
+#include <div64.h>
+#include <dm/test.h>
+#include <kendryte/pll.h>
+#include <test/ut.h>
+
+static int dm_test_k210_pll_calc_config(u32 rate, u32 rate_in,
+ struct k210_pll_config *best)
+{
+ u64 f, r, od, max_r, inv_ratio;
+ s64 error, best_error;
+
+ best_error = S64_MAX;
+ error = best_error;
+ max_r = min(16ULL, DIV_ROUND_DOWN_ULL(rate_in, 13300000));
+ inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
+
+ /* Brute force it */
+ for (r = 1; r <= max_r; r++) {
+ for (f = 1; f <= 64; f++) {
+ for (od = 1; od <= 16; od++) {
+ u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
+
+ if (vco > 1750000000 || vco < 340000000)
+ continue;
+
+ error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio,
+ r * od);
+ /* The lower 16 bits are spurious */
+ error = abs((error - BIT(32))) >> 16;
+ if (error < best_error) {
+ best->r = r;
+ best->f = f;
+ best->od = od;
+ best_error = error;
+ }
+ }
+ }
+ }
+
+ if (best_error == S64_MAX)
+ return -EINVAL;
+ return 0;
+}
+
+static int dm_test_k210_pll_compare(struct k210_pll_config *ours,
+ struct k210_pll_config *theirs)
+{
+ return (u32)ours->f * theirs->r * theirs->od !=
+ (u32)theirs->f * ours->r * ours->od;
+}
+
+static int dm_test_k210_pll(struct unit_test_state *uts)
+{
+ struct k210_pll_config ours, theirs;
+
+ /* General range checks */
+ ut_asserteq(-EINVAL, k210_pll_calc_config(0, 26000000, &theirs));
+ ut_asserteq(-EINVAL, k210_pll_calc_config(390000000, 0, &theirs));
+ ut_asserteq(-EINVAL, k210_pll_calc_config(2000000000, 26000000,
+ &theirs));
+ ut_asserteq(-EINVAL, k210_pll_calc_config(390000000, 2000000000,
+ &theirs));
+ ut_asserteq(-EINVAL, k210_pll_calc_config(1500000000, 20000000,
+ &theirs));
+
+ /* Verify we get the same output with brute-force */
+ ut_assertok(dm_test_k210_pll_calc_config(390000000, 26000000, &ours));
+ ut_assertok(k210_pll_calc_config(390000000, 26000000, &theirs));
+ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+ ut_assertok(dm_test_k210_pll_calc_config(26000000, 390000000, &ours));
+ ut_assertok(k210_pll_calc_config(26000000, 390000000, &theirs));
+ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+ ut_assertok(dm_test_k210_pll_calc_config(400000000, 26000000, &ours));
+ ut_assertok(k210_pll_calc_config(400000000, 26000000, &theirs));
+ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+ ut_assertok(dm_test_k210_pll_calc_config(27000000, 26000000, &ours));
+ ut_assertok(k210_pll_calc_config(27000000, 26000000, &theirs));
+ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+ ut_assertok(dm_test_k210_pll_calc_config(26000000, 27000000, &ours));
+ ut_assertok(k210_pll_calc_config(26000000, 27000000, &theirs));
+ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+ return 0;
+}
+DM_TEST(dm_test_k210_pll, 0);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <dm/device-internal.h>
+#include <test/ut.h>
+#include <asm/clk.h>
+#include <asm/power-domain.h>
+
+/* These must match the ids in the device tree */
+#define TEST_CLOCK_ID 4
+#define TEST_POWER_ID 1
+
+static int dm_test_simple_pm_bus(struct unit_test_state *uts)
+{
+ struct udevice *power;
+ struct udevice *clock;
+ struct udevice *bus;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN,
+ "power-domain", &power));
+ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
+ &clock));
+ ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID));
+ ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, "pm-bus-test",
+ &bus));
+ ut_asserteq(1, sandbox_power_domain_query(power, TEST_POWER_ID));
+ ut_asserteq(1, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
+
+ ut_assertok(device_remove(bus, DM_REMOVE_NORMAL));
+ /* must re-probe since device_remove also removes the power domain */
+ ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN,
+ "power-domain", &power));
+ ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID));
+ ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
+
+ return 0;
+}
+DM_TEST(dm_test_simple_pm_bus, DM_TESTF_SCAN_FDT);
* Since we are about to destroy all devices, we must tell sandbox
* to forget the emulation device
*/
-#ifdef CONFIG_DM_SPI_FLASH
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
sandbox_sf_unbind_emul(state_get_current(), busnum, cs);
#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <test/ut.h>
+#include <asm/test.h>
+#include <linux/bitops.h>
+
+/* The following values must match the device tree */
+#define TEST_RESET_REG 1
+#define TEST_RESET_ASSERT_HIGH 0
+#define TEST_RESET_ASSERT (TEST_RESET_ASSERT_HIGH ? (u32)-1 : (u32)0)
+#define TEST_RESET_DEASSERT (~TEST_RESET_ASSERT)
+
+#define TEST_RESET_VALID 15
+#define TEST_RESET_NOMASK 30
+#define TEST_RESET_OUTOFRANGE 60
+
+static int dm_test_syscon_reset(struct unit_test_state *uts)
+{
+ struct regmap *map;
+ struct reset_ctl rst;
+ struct udevice *reset;
+ struct udevice *syscon;
+ struct udevice *syscon_reset;
+ uint reg;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "syscon-reset-test",
+ &reset));
+ ut_assertok(uclass_get_device_by_name(UCLASS_SYSCON, "syscon@0",
+ &syscon));
+ ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "syscon-reset",
+ &syscon_reset));
+ ut_assertok_ptr((map = syscon_get_regmap(syscon)));
+
+ ut_asserteq(-EINVAL, reset_get_by_name(reset, "no_mask", &rst));
+ ut_asserteq(-EINVAL, reset_get_by_name(reset, "out_of_range", &rst));
+ ut_assertok(reset_get_by_name(reset, "valid", &rst));
+
+ sandbox_set_enable_memio(true);
+ ut_assertok(regmap_write(map, TEST_RESET_REG, TEST_RESET_DEASSERT));
+ ut_assertok(reset_assert(&rst));
+ ut_assertok(regmap_read(map, TEST_RESET_REG, ®));
+ ut_asserteq(TEST_RESET_DEASSERT ^ BIT(TEST_RESET_VALID), reg);
+
+ ut_assertok(reset_deassert(&rst));
+ ut_assertok(regmap_read(map, TEST_RESET_REG, ®));
+ ut_asserteq(TEST_RESET_DEASSERT, reg);
+
+ return 0;
+}
+DM_TEST(dm_test_syscon_reset, DM_TESTF_SCAN_FDT);
ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 2, &dev));
ut_asserteq_str("d-test", dev->name);
- /* d-test actually gets 0 */
- ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 0, &dev));
+ /*
+ * d-test actually gets 9, because thats the next free one after the
+ * aliases.
+ */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 9, &dev));
ut_asserteq_str("d-test", dev->name);
- /* initially no one wants seq 1 */
- ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 1,
+ /* initially no one wants seq 10 */
+ ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 10,
&dev));
ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 4, &dev));
/* But now that it is probed, we can find it */
- ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 1, &dev));
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 10, &dev));
ut_asserteq_str("f-test", dev->name);
+ /*
+ * And we should still have holes in our sequence numbers, that is 2
+ * and 4 should not be used.
+ */
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 2,
+ true, &dev));
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 4,
+ true, &dev));
+
return 0;
}
DM_TEST(dm_test_fdt_uclass_seq, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
}
DM_TEST(dm_test_usb_multi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+/* test that we have an associated ofnode with the usb device */
+static int dm_test_usb_fdt_node(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ ofnode node;
+
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
+ node = ofnode_path("/usb@1/hub/usbstor@1");
+ ut_asserteq(1, ofnode_equal(node, dev_ofnode(dev)));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
+ ut_asserteq(1, ofnode_equal(ofnode_null(), dev_ofnode(dev)));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
+ node = ofnode_path("/usb@1/hub/usbstor@3");
+ ut_asserteq(1, ofnode_equal(node, dev_ofnode(dev)));
+ ut_assertok(usb_stop());
+
+ return 0;
+}
+DM_TEST(dm_test_usb_fdt_node, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
static int count_usb_devices(void)
{
struct udevice *hub;
# (C) Copyright 2018
# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
obj-y += cmd_ut_lib.o
+obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
obj-y += hexdump.o
obj-y += lmb.o
obj-y += string.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+#define UT_REG_CAPACITY 6
+
+static int lib_test_efi_image_region_add(struct unit_test_state *uts)
+{
+ struct efi_image_regions *regs;
+
+ regs = calloc(sizeof(*regs) +
+ sizeof(struct image_region) * UT_REG_CAPACITY, 1);
+ ut_assert(regs);
+
+ regs->max = UT_REG_CAPACITY;
+
+ ut_asserteq(0, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x4000,
+ (void *)0x3000, 1));
+ ut_asserteq(0, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x3100,
+ (void *)0x4000, 1));
+ ut_asserteq(1, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x2000,
+ (void *)0x3100, 1));
+ ut_asserteq(2, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x1000,
+ (void *)0x1f00, 1));
+ ut_asserteq(3, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x4000,
+ (void *)0x4e00, 1));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x1f00,
+ (void *)0x2001, 1));
+ ut_asserteq(5, regs->num);
+
+ ut_asserteq_ptr((void *)0x3100, regs->reg[0].data);
+ ut_asserteq(0x0f00, regs->reg[0].size);
+
+ ut_asserteq_ptr((void *)0x2000, regs->reg[1].data);
+ ut_asserteq(0x1100, regs->reg[1].size);
+
+ ut_asserteq_ptr((void *)0x1000, regs->reg[2].data);
+ ut_asserteq(0x0f00, regs->reg[2].size);
+
+ ut_asserteq_ptr((void *)0x4000, regs->reg[3].data);
+ ut_asserteq(0x0e00, regs->reg[3].size);
+
+ ut_asserteq_ptr((void *)0x1f00, regs->reg[4].data);
+ ut_asserteq(0x0101, regs->reg[4].size);
+
+ free(regs);
+
+ return 0;
+}
+
+LIB_TEST(lib_test_efi_image_region_add, 0);
+
+static int lib_test_efi_image_region_sort(struct unit_test_state *uts)
+{
+ struct efi_image_regions *regs;
+
+ regs = calloc(sizeof(*regs) +
+ sizeof(struct image_region) * UT_REG_CAPACITY, 1);
+ ut_assert(regs);
+
+ regs->max = UT_REG_CAPACITY;
+
+ ut_asserteq(0, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x4000,
+ (void *)0x3000, 0));
+ ut_asserteq(0, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x3100,
+ (void *)0x4000, 0));
+ ut_asserteq(1, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x2000,
+ (void *)0x3100, 0));
+ ut_asserteq(2, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x1000,
+ (void *)0x1f00, 0));
+ ut_asserteq(3, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x4000,
+ (void *)0x4e00, 0));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x1f00,
+ (void *)0x2001, 0));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x10ff,
+ (void *)0x11ff, 0));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x0000,
+ (void *)0x6000, 0));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x3100,
+ (void *)0x0e00, 0));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x3200,
+ (void *)0x0e00, 0));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_INVALID_PARAMETER,
+ efi_image_region_add(regs, (void *)0x3200,
+ (void *)0x0d00, 0));
+ ut_asserteq(4, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x1f00,
+ (void *)0x2000, 0));
+ ut_asserteq(5, regs->num);
+ ut_asserteq_64(EFI_SUCCESS,
+ efi_image_region_add(regs, (void *)0x4000,
+ (void *)0x4000, 0));
+ ut_asserteq(6, regs->num);
+ ut_asserteq_64(EFI_OUT_OF_RESOURCES,
+ efi_image_region_add(regs, (void *)0x6000,
+ (void *)0x0100, 0));
+ ut_asserteq(6, regs->num);
+
+ ut_asserteq_ptr((void *)0x1000, regs->reg[0].data);
+ ut_asserteq(0x0f00, regs->reg[0].size);
+
+ ut_asserteq_ptr((void *)0x1f00, regs->reg[1].data);
+ ut_asserteq(0x0100, regs->reg[1].size);
+
+ ut_asserteq_ptr((void *)0x2000, regs->reg[2].data);
+ ut_asserteq(0x1100, regs->reg[2].size);
+
+ ut_asserteq_ptr((void *)0x3100, regs->reg[3].data);
+ ut_asserteq(0x0f00, regs->reg[3].size);
+
+ ut_asserteq_ptr((void *)0x4000, regs->reg[4].data);
+ ut_asserteq(0x0000, regs->reg[4].size);
+
+ ut_asserteq_ptr((void *)0x4000, regs->reg[5].data);
+ ut_asserteq(0x0e00, regs->reg[5].size);
+
+ free(regs);
+
+ return 0;
+}
+
+LIB_TEST(lib_test_efi_image_region_sort, 0);
import pytest
@pytest.mark.buildconfigspec('cmd_dm')
-def test_dm_drivers(u_boot_console):
- """Test that each driver in `dm tree` is also listed in `dm drivers`."""
+def test_dm_compat(u_boot_console):
+ """Test that each driver in `dm tree` is also listed in `dm compat`."""
response = u_boot_console.run_command('dm tree')
driver_index = response.find('Driver')
assert driver_index != -1
drivers = (line[driver_index:].split()[0]
for line in response[:-1].split('\n')[2:])
+ response = u_boot_console.run_command('dm compat')
+ for driver in drivers:
+ assert driver in response
+
+@pytest.mark.buildconfigspec('cmd_dm')
+def test_dm_drivers(u_boot_console):
+ """Test that each driver in `dm compat` is also listed in `dm drivers`."""
+ response = u_boot_console.run_command('dm compat')
+ drivers = (line[:20].rstrip() for line in response[:-1].split('\n')[2:])
+ response = u_boot_console.run_command('dm drivers')
+ for driver in drivers:
+ assert driver in response
+
+@pytest.mark.buildconfigspec('cmd_dm')
+def test_dm_static(u_boot_console):
+ """Test that each driver in `dm static` is also listed in `dm drivers`."""
+ response = u_boot_console.run_command('dm static')
+ drivers = (line[:25].rstrip() for line in response[:-1].split('\n')[2:])
response = u_boot_console.run_command('dm drivers')
for driver in drivers:
assert driver in response
## PK
check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_PK/ -keyout PK.key -out PK.crt -nodes -days 365'
% mnt_point, shell=True)
- check_call('cd %s; %scert-to-efi-sig-list -g %s PK.crt PK.esl; %ssign-efi-sig-list -c PK.crt -k PK.key PK PK.esl PK.auth'
+ check_call('cd %s; %scert-to-efi-sig-list -g %s PK.crt PK.esl; %ssign-efi-sig-list -t "2020-04-01" -c PK.crt -k PK.key PK PK.esl PK.auth'
% (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
## PK_null for deletion
- check_call('cd %s; sleep 2; touch PK_null.esl; %ssign-efi-sig-list -c PK.crt -k PK.key PK PK_null.esl PK_null.auth'
+ check_call('cd %s; touch PK_null.esl; %ssign-efi-sig-list -t "2020-04-02" -c PK.crt -k PK.key PK PK_null.esl PK_null.auth'
% (mnt_point, EFITOOLS_PATH), shell=True)
## KEK
check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_KEK/ -keyout KEK.key -out KEK.crt -nodes -days 365'
% mnt_point, shell=True)
- check_call('cd %s; %scert-to-efi-sig-list -g %s KEK.crt KEK.esl; %ssign-efi-sig-list -c PK.crt -k PK.key KEK KEK.esl KEK.auth'
+ check_call('cd %s; %scert-to-efi-sig-list -g %s KEK.crt KEK.esl; %ssign-efi-sig-list -t "2020-04-03" -c PK.crt -k PK.key KEK KEK.esl KEK.auth'
% (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
## db
check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db/ -keyout db.key -out db.crt -nodes -days 365'
% mnt_point, shell=True)
- check_call('cd %s; %scert-to-efi-sig-list -g %s db.crt db.esl; %ssign-efi-sig-list -c KEK.crt -k KEK.key db db.esl db.auth'
+ check_call('cd %s; %scert-to-efi-sig-list -g %s db.crt db.esl; %ssign-efi-sig-list -t "2020-04-04" -c KEK.crt -k KEK.key db db.esl db.auth'
% (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
## db1
check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db1/ -keyout db1.key -out db1.crt -nodes -days 365'
% mnt_point, shell=True)
- check_call('cd %s; %scert-to-efi-sig-list -g %s db1.crt db1.esl; %ssign-efi-sig-list -c KEK.crt -k KEK.key db db1.esl db1.auth'
+ check_call('cd %s; %scert-to-efi-sig-list -g %s db1.crt db1.esl; %ssign-efi-sig-list -t "2020-04-05" -c KEK.crt -k KEK.key db db1.esl db1.auth'
% (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
## db1-update
- check_call('cd %s; %ssign-efi-sig-list -a -c KEK.crt -k KEK.key db db1.esl db1-update.auth'
+ check_call('cd %s; %ssign-efi-sig-list -t "2020-04-06" -a -c KEK.crt -k KEK.key db db1.esl db1-update.auth'
% (mnt_point, EFITOOLS_PATH), shell=True)
## dbx
check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_dbx/ -keyout dbx.key -out dbx.crt -nodes -days 365'
% mnt_point, shell=True)
- check_call('cd %s; %scert-to-efi-sig-list -g %s dbx.crt dbx.esl; %ssign-efi-sig-list -c KEK.crt -k KEK.key dbx dbx.esl dbx.auth'
+ check_call('cd %s; %scert-to-efi-sig-list -g %s dbx.crt dbx.esl; %ssign-efi-sig-list -t "2020-04-05" -c KEK.crt -k KEK.key dbx dbx.esl dbx.auth'
% (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
check_call('cd %s; sbsign --key db.key --cert db.crt helloworld.efi'
% mnt_point, shell=True)
## Digest image
- check_call('cd %s; %shash-to-efi-sig-list helloworld.efi db_hello.hash; %ssign-efi-sig-list -c KEK.crt -k KEK.key db db_hello.hash db_hello.auth'
+ check_call('cd %s; %shash-to-efi-sig-list helloworld.efi db_hello.hash; %ssign-efi-sig-list -t "2020-04-07" -c KEK.crt -k KEK.key db db_hello.hash db_hello.auth'
% (mnt_point, EFITOOLS_PATH, EFITOOLS_PATH),
shell=True)
"""
import pytest
-import re
from defs import *
@pytest.mark.boardspec('sandbox')
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -i 4000000,$filesize PK'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
with u_boot_console.log.section('Test Case 1c'):
# Test Case 1c, install PK
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK',
'printenv -e -n PK'])
- assert(re.search('PK:', ''.join(output)))
+ assert('PK:' in ''.join(output))
output = u_boot_console.run_command(
'printenv -e SecureBoot')
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
with u_boot_console.log.section('Test Case 1e'):
# Test Case 1e, install KEK
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -i 4000000,$filesize KEK'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'printenv -e -n KEK'])
- assert(re.search('KEK:', ''.join(output)))
+ assert('KEK:' in ''.join(output))
output = u_boot_console.run_command(
'printenv -e SecureBoot')
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -i 4000000,$filesize db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
output = u_boot_console.run_command(
'printenv -e SecureBoot')
with u_boot_console.log.section('Test Case 1g'):
# Test Case 1g, install dbx
output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 db.auth',
- 'setenv -e -nv -bs -rt -i 4000000,$filesize db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ 'fatload host 0:1 4000000 dbx.auth',
+ 'setenv -e -nv -bs -rt -i 4000000,$filesize dbx'])
+ assert('Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 db.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
- 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ 'fatload host 0:1 4000000 dbx.auth',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx',
+ 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f dbx'])
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('dbx:' in ''.join(output))
output = u_boot_console.run_command(
'printenv -e SecureBoot')
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK',
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db1.auth',
'setenv -e -nv -bs -rt -i 4000000,$filesize db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
with u_boot_console.log.section('Test Case 2b'):
# Test Case 2b, update without correct signature
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db.esl',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
with u_boot_console.log.section('Test Case 2c'):
# Test Case 2c, update with correct signature
'fatload host 0:1 4000000 db1.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
def test_efi_var_auth3(self, u_boot_console, efi_boot_env):
"""
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK',
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db1.auth',
'setenv -e -nv -bs -rt -a -i 4000000,$filesize db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
with u_boot_console.log.section('Test Case 3b'):
# Test Case 3b, update without correct signature
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db.esl',
'setenv -e -nv -bs -rt -at -a -i 4000000,$filesize db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
with u_boot_console.log.section('Test Case 3c'):
# Test Case 3c, update with correct signature
'fatload host 0:1 4000000 db1.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000,$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
def test_efi_var_auth4(self, u_boot_console, efi_boot_env):
"""
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK',
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
output = u_boot_console.run_command_list([
'setenv -e -nv -bs -rt db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
with u_boot_console.log.section('Test Case 4b'):
# Test Case 4b, update without correct signature/data
output = u_boot_console.run_command_list([
'setenv -e -nv -bs -rt -at db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('db:', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
+ assert('db:' in ''.join(output))
def test_efi_var_auth5(self, u_boot_console, efi_boot_env):
"""
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK',
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
'printenv -e -n PK'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('PK:', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('PK:' in ''.join(output))
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 PK_null.esl',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK',
'printenv -e -n PK'])
- assert(re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('PK:', ''.join(output)))
+ assert('Failed to set EFI variable' in ''.join(output))
+ assert('PK:' in ''.join(output))
with u_boot_console.log.section('Test Case 5b'):
# Test Case 5b, Uninstall PK with correct signature
'fatload host 0:1 4000000 PK_null.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK',
'printenv -e -n PK'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
- assert(re.search('\"PK\" not defined', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
+ assert('\"PK\" not defined' in ''.join(output))
output = u_boot_console.run_command(
'printenv -e SecureBoot')
"""
import pytest
-import re
from defs import *
@pytest.mark.boardspec('sandbox')
# Test Case 1a, run signed image if no db/dbx
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
- 'efidebug boot add 1 HELLO1 host 0:1 /helloworld.efi.signed ""; echo',
+ 'efidebug boot add 1 HELLO1 host 0:1 /helloworld.efi.signed ""',
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('Hello, world!', ''.join(output)))
+ assert('Hello, world!' in ''.join(output))
with u_boot_console.log.section('Test Case 1b'):
# Test Case 1b, run unsigned image if no db/dbx
'efidebug boot add 2 HELLO2 host 0:1 /helloworld.efi ""',
'efidebug boot next 2',
'bootefi bootmgr'])
- assert(re.search('Hello, world!', ''.join(output)))
+ assert('Hello, world!' in ''.join(output))
with u_boot_console.log.section('Test Case 1c'):
# Test Case 1c, not authenticated by db
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 2',
'bootefi bootmgr'])
- assert(re.search('\'HELLO2\' failed', ''.join(output)))
+ assert('\'HELLO2\' failed' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 2',
'efidebug test bootmgr'])
- assert(re.search('efi_start_image[(][)] returned: 26',
- ''.join(output)))
- assert(not re.search('Hello, world!', ''.join(output)))
+ assert('efi_start_image() returned: 26' in ''.join(output))
+ assert(not 'Hello, world!' in ''.join(output))
with u_boot_console.log.section('Test Case 1d'):
# Test Case 1d, authenticated by db
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('Hello, world!', ''.join(output)))
+ assert('Hello, world!' in ''.join(output))
def test_efi_signed_image_auth2(self, u_boot_console, efi_boot_env):
"""
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx',
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add 1 HELLO host 0:1 /helloworld.efi.signed ""',
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('\'HELLO\' failed', ''.join(output)))
+ assert('\'HELLO\' failed' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'efidebug test bootmgr'])
- assert(re.search('efi_start_image[(][)] returned: 26',
- ''.join(output)))
- assert(not re.search('Hello, world!', ''.join(output)))
+ assert('efi_start_image() returned: 26' in ''.join(output))
+ assert(not 'Hello, world!' in ''.join(output))
with u_boot_console.log.section('Test Case 2b'):
# Test Case 2b, rejected by dbx even if db allows
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('\'HELLO\' failed', ''.join(output)))
+ assert('\'HELLO\' failed' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'efidebug test bootmgr'])
- assert(re.search('efi_start_image[(][)] returned: 26',
- ''.join(output)))
- assert(not re.search('Hello, world!', ''.join(output)))
+ assert('efi_start_image() returned: 26' in ''.join(output))
+ assert(not 'Hello, world!' in ''.join(output))
"""
import pytest
-import re
from defs import *
@pytest.mark.boardspec('sandbox')
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 KEK.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add 1 HELLO host 0:1 /helloworld.efi ""',
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('\'HELLO\' failed', ''.join(output)))
+ assert('\'HELLO\' failed' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'efidebug test bootmgr'])
- assert(re.search('efi_start_image[(][)] returned: 26',
- ''.join(output)))
- assert(not re.search('Hello, world!', ''.join(output)))
+ assert('efi_start_image() returned: 26' in ''.join(output))
+ assert(not 'Hello, world!' in ''.join(output))
def test_efi_unsigned_image_auth2(self, u_boot_console, efi_boot_env):
"""
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db_hello.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize db; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize db',
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add 1 HELLO host 0:1 /helloworld.efi ""',
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('Hello, world!', ''.join(output)))
+ assert('Hello, world!' in ''.join(output))
def test_efi_unsigned_image_auth3(self, u_boot_console, efi_boot_env):
"""
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db_hello.auth',
- 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx; echo',
+ 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx',
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add 1 HELLO host 0:1 /helloworld.efi ""',
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('\'HELLO\' failed', ''.join(output)))
+ assert('\'HELLO\' failed' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'efidebug test bootmgr'])
- assert(re.search('efi_start_image[(][)] returned: 26',
- ''.join(output)))
- assert(not re.search('Hello, world!', ''.join(output)))
+ assert('efi_start_image() returned: 26' in ''.join(output))
+ assert(not 'Hello, world!' in ''.join(output))
with u_boot_console.log.section('Test Case 3b'):
# Test Case 3b, rejected by dbx even if db allows
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db_hello.auth',
'setenv -e -nv -bs -rt -at -i 4000000,$filesize db'])
- assert(not re.search('Failed to set EFI variable', ''.join(output)))
+ assert(not 'Failed to set EFI variable' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add 1 HELLO host 0:1 /helloworld.efi ""',
'efidebug boot next 1',
'bootefi bootmgr'])
- assert(re.search('\'HELLO\' failed', ''.join(output)))
+ assert('\'HELLO\' failed' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'efidebug test bootmgr'])
- assert(re.search('efi_start_image[(][)] returned: 26',
- ''.join(output)))
- assert(not re.search('Hello, world!', ''.join(output)))
+ assert('efi_start_image() returned: 26' in ''.join(output))
+ assert(not 'Hello, world!' in ''.join(output))
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2020
+# Niel Fourie, DENX Software Engineering, lusus@denx.de
+
+import pytest
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_fs_generic')
+def test_dm_compat(u_boot_console):
+ """Test that `fstypes` prints a result which includes `sandbox`."""
+ output = u_boot_console.run_command('fstypes')
+ assert "Supported filesystems:" in output
+ assert "sandbox" in output
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2020
+# Niel Fourie, DENX Software Engineering, lusus@denx.de
+
+import pytest
+
+@pytest.mark.buildconfigspec('blk')
+@pytest.mark.buildconfigspec('cmd_lsblk')
+def test_lsblk(u_boot_console):
+ """Test that `lsblk` prints a result which includes `host`."""
+ output = u_boot_console.run_command('lsblk')
+ assert "Block Driver" in output
+ assert "sandbox_host_blk" in output
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2020
+# Niel Fourie, DENX Software Engineering, lusus@denx.de
+
+import pytest
+
+@pytest.mark.buildconfigspec('cmd_part')
+@pytest.mark.buildconfigspec('partitions')
+@pytest.mark.buildconfigspec('efi_partition')
+def test_dm_compat(u_boot_console):
+ """Test that `part types` prints a result which includes `EFI`."""
+ output = u_boot_console.run_command('part types')
+ assert "Supported partition tables:" in output
+ assert "EFI" in output
# Setup env__sleep_accurate to False if time is not accurate on your platform
env__sleep_accurate = False
+# Setup env__sleep_time time in seconds board is set to sleep
+env__sleep_time = 3
+
+# Setup env__sleep_margin set a margin for any system overhead
+env__sleep_margin = 0.25
+
"""
def test_sleep(u_boot_console):
if u_boot_console.config.buildconfig.get('config_cmd_misc', 'n') != 'y':
pytest.skip('sleep command not supported')
+
# 3s isn't too long, but is enough to cross a few second boundaries.
- sleep_time = 3
+ sleep_time = u_boot_console.config.env.get('env__sleep_time', 3)
+ sleep_margin = u_boot_console.config.env.get('env__sleep_margin', 0.25)
tstart = time.time()
u_boot_console.run_command('sleep %d' % sleep_time)
tend = time.time()
elapsed = tend - tstart
assert elapsed >= (sleep_time - 0.01)
if not u_boot_console.config.gdbserver:
- # 0.25s margin is hopefully enough to account for any system overhead.
- assert elapsed < (sleep_time + 0.25)
+ # margin is hopefully enough to account for any system overhead.
+ assert elapsed < (sleep_time + sleep_margin)
lib/crc16.o \
lib/sha1.o \
lib/sha256.o \
+ lib/sha512.o \
common/hash.o \
ublimage.o \
zynqimage.o \
HOSTCFLAGS_md5.o := -pedantic
HOSTCFLAGS_sha1.o := -pedantic
HOSTCFLAGS_sha256.o := -pedantic
+HOSTCFLAGS_sha512.o := -pedantic -DCONFIG_SHA512 -DCONFIG_SHA384
quiet_cmd_wrap = WRAP $@
cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@
like this:
us-net/ base directory
- 01_of_02_g4ed4ebc_net--Add-tftp-speed-/
+ 01_g4ed4ebc_net--Add-tftp-speed-/
sandbox/
u-boot.bin
seaboard/
u-boot.bin
- 02_of_02_g4ed4ebc_net--Check-tftp-comp/
+ 02_g4ed4ebc_net--Check-tftp-comp/
sandbox/
u-boot.bin
seaboard/
commit = self.commits[commit_upto]
subject = commit.subject.translate(trans_valid_chars)
# See _GetOutputSpaceRemovals() which parses this name
- commit_dir = ('%02d_of_%02d_g%s_%s' % (commit_upto + 1,
- self.commit_count, commit.hash, subject[:20]))
+ commit_dir = ('%02d_g%s_%s' % (commit_upto + 1,
+ commit.hash, subject[:20]))
elif not self.no_subdirs:
commit_dir = 'current'
if not commit_dir:
for dirname in glob.glob(os.path.join(self.base_dir, '*')):
if dirname not in dir_list:
leaf = dirname[len(self.base_dir) + 1:]
- m = re.match('[0-9]+_of_[0-9]+_g[0-9a-f]+_.*', leaf)
+ m = re.match('[0-9]+_g[0-9a-f]+_.*', leaf)
if m:
to_remove.append(dirname)
return to_remove
from os.path import dirname, exists, expandvars, islink, join, realpath
-VERSION = (12, 14, 0)
+VERSION = (14, 1, 0)
# File layout:
See Kconfig.load_config() as well.
srctree:
- The value of the $srctree environment variable when the configuration was
- loaded, or the empty string if $srctree wasn't set. This gives nice
+ The value the $srctree environment variable had when the Kconfig instance
+ was created, or the empty string if $srctree wasn't set. This gives nice
behavior with os.path.join(), which treats "" as the current directory,
without adding "./".
if multiple configurations are loaded with different values for $srctree.
config_prefix:
- The value of the $CONFIG_ environment variable when the configuration was
- loaded. This is the prefix used (and expected) on symbol names in .config
- files and C headers. Defaults to "CONFIG_". Used in the same way in the C
- tools.
-
- Like for srctree, only the value of $CONFIG_ when the configuration is
- loaded matters.
+ The value the CONFIG_ environment variable had when the Kconfig instance
+ was created, or "CONFIG_" if CONFIG_ wasn't set. This is the prefix used
+ (and expected) on symbol names in .config files and C headers. Used in
+ the same way in the C tools.
+
+ config_header:
+ The value the KCONFIG_CONFIG_HEADER environment variable had when the
+ Kconfig instance was created, or the empty string if
+ KCONFIG_CONFIG_HEADER wasn't set. This string is inserted verbatim at the
+ beginning of configuration files. See write_config().
+
+ header_header:
+ The value the KCONFIG_AUTOHEADER_HEADER environment variable had when the
+ Kconfig instance was created, or the empty string if
+ KCONFIG_AUTOHEADER_HEADER wasn't set. This string is inserted verbatim at
+ the beginning of header files. See write_autoconf().
filename/linenr:
The current parsing location, for use in Python preprocessor functions.
"_warn_assign_no_prompt",
"choices",
"comments",
+ "config_header",
"config_prefix",
"const_syms",
"defconfig_list",
"defined_syms",
"env_vars",
+ "header_header",
"kconfig_filenames",
"m",
"menus",
#
def __init__(self, filename="Kconfig", warn=True, warn_to_stderr=True,
- encoding="utf-8"):
+ encoding="utf-8", suppress_traceback=False):
"""
Creates a new Kconfig object by parsing Kconfig files.
Note that Kconfig files are not the same as .config files (which store
anyway.
Related PEP: https://www.python.org/dev/peps/pep-0538/
+
+ suppress_traceback (default: False):
+ Helper for tools. When True, any EnvironmentError or KconfigError
+ generated during parsing is caught, the exception message is printed
+ to stderr together with the command name, and sys.exit(1) is called
+ (which generates SystemExit).
+
+ This hides the Python traceback for "expected" errors like syntax
+ errors in Kconfig files.
+
+ Other exceptions besides EnvironmentError and KconfigError are still
+ propagated when suppress_traceback is True.
"""
+ try:
+ self._init(filename, warn, warn_to_stderr, encoding)
+ except (EnvironmentError, KconfigError) as e:
+ if suppress_traceback:
+ cmd = sys.argv[0] # Empty string if missing
+ if cmd:
+ cmd += ": "
+ # Some long exception messages have extra newlines for better
+ # formatting when reported as an unhandled exception. Strip
+ # them here.
+ sys.exit(cmd + str(e).strip())
+ raise
+
+ def _init(self, filename, warn, warn_to_stderr, encoding):
+ # See __init__()
+
self._encoding = encoding
self.srctree = os.getenv("srctree", "")
self._unset_match = _re_match(r"# {}([^ ]+) is not set".format(
self.config_prefix))
+ self.config_header = os.getenv("KCONFIG_CONFIG_HEADER", "")
+ self.header_header = os.getenv("KCONFIG_AUTOHEADER_HEADER", "")
+
self.syms = {}
self.const_syms = {}
self.defined_syms = []
self._readline = self._open(join(self.srctree, filename), "r").readline
try:
- # Parse the Kconfig files
- self._parse_block(None, self.top_node, self.top_node)
+ # Parse the Kconfig files. Returns the last node, which we
+ # terminate with '.next = None'.
+ self._parse_block(None, self.top_node, self.top_node).next = None
self.top_node.list = self.top_node.next
self.top_node.next = None
except UnicodeDecodeError as e:
self._warn("'{}' is not a valid value for the {} "
"symbol {}. Assignment ignored."
.format(val, TYPE_TO_STR[sym.orig_type],
- _name_and_loc(sym)),
+ sym.name_and_loc),
filename, linenr)
continue
if not match:
self._warn("malformed string literal in "
"assignment to {}. Assignment ignored."
- .format(_name_and_loc(sym)),
+ .format(sym.name_and_loc),
filename, linenr)
continue
user_val = sym.user_value
msg = '{} set more than once. Old value "{}", new value "{}".'.format(
- _name_and_loc(sym), user_val, new_val)
+ sym.name_and_loc, user_val, new_val)
if user_val == new_val:
if self.warn_assign_redun:
elif self.warn_assign_override:
self._warn(msg, filename, linenr)
- def write_autoconf(self, filename,
- header="/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */\n"):
+ def load_allconfig(self, filename):
+ """
+ Helper for all*config. Loads (merges) the configuration file specified
+ by KCONFIG_ALLCONFIG, if any. See Documentation/kbuild/kconfig.txt in
+ the Linux kernel.
+
+ Disables warnings for duplicated assignments within configuration files
+ for the duration of the call
+ (kconf.warn_assign_override/warn_assign_redun = False), and restores
+ the previous warning settings at the end. The KCONFIG_ALLCONFIG
+ configuration file is expected to override symbols.
+
+ Exits with sys.exit() (which raises a SystemExit exception) and prints
+ an error to stderr if KCONFIG_ALLCONFIG is set but the configuration
+ file can't be opened.
+
+ filename:
+ Command-specific configuration filename - "allyes.config",
+ "allno.config", etc.
+ """
+ load_allconfig(self, filename)
+
+ def write_autoconf(self, filename=None, header=None):
r"""
Writes out symbol values as a C header file, matching the format used
by include/generated/autoconf.h in the kernel.
like the modification time and possibly triggering redundant work in
build tools.
- filename:
- Self-explanatory.
+ filename (default: None):
+ Path to write header to.
- header (default: "/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */\n"):
- Text that will be inserted verbatim at the beginning of the file. You
- would usually want it enclosed in '/* */' to make it a C comment,
- and include a final terminating newline.
+ If None (the default), the path in the environment variable
+ KCONFIG_AUTOHEADER is used if set, and "include/generated/autoconf.h"
+ otherwise. This is compatible with the C tools.
+
+ header (default: None):
+ Text inserted verbatim at the beginning of the file. You would
+ usually want it enclosed in '/* */' to make it a C comment, and
+ include a trailing newline.
+
+ If None (the default), the value of the environment variable
+ KCONFIG_AUTOHEADER_HEADER had when the Kconfig instance was created
+ will be used if it was set, and no header otherwise. See the
+ Kconfig.header_header attribute.
+
+ Returns a string with a message saying that the header got saved, or
+ that there were no changes to it. This is meant to reduce boilerplate
+ in tools, which can do e.g. print(kconf.write_autoconf()).
"""
- self._write_if_changed(filename, self._autoconf_contents(header))
+ if filename is None:
+ filename = os.getenv("KCONFIG_AUTOHEADER",
+ "include/generated/autoconf.h")
+
+ if self._write_if_changed(filename, self._autoconf_contents(header)):
+ return "Kconfig header saved to '{}'".format(filename)
+ return "No change to Kconfig header in '{}'".format(filename)
def _autoconf_contents(self, header):
# write_autoconf() helper. Returns the contents to write as a string,
- # with 'header' at the beginning.
+ # with 'header' or KCONFIG_AUTOHEADER_HEADER at the beginning.
- # "".join()ed later
- chunks = [header]
+ if header is None:
+ header = self.header_header
+
+ chunks = [header] # "".join()ed later
add = chunks.append
for sym in self.unique_defined_syms:
return "".join(chunks)
- def write_config(self, filename=None,
- header="# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)\n",
- save_old=True, verbose=None):
+ def write_config(self, filename=None, header=None, save_old=True,
+ verbose=None):
r"""
Writes out symbol values in the .config format. The format matches the
C implementation, including ordering.
(OSError/IOError). KconfigError is never raised here.
filename (default: None):
- Filename to save configuration to (a string).
+ Path to write configuration to (a string).
- If None (the default), the filename in the environment variable
+ If None (the default), the path in the environment variable
KCONFIG_CONFIG is used if set, and ".config" otherwise. See
standard_config_filename().
- header (default: "# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)\n"):
- Text that will be inserted verbatim at the beginning of the file. You
- would usually want each line to start with '#' to make it a comment,
- and include a final terminating newline.
+ header (default: None):
+ Text inserted verbatim at the beginning of the file. You would
+ usually want each line to start with '#' to make it a comment, and
+ include a trailing newline.
+
+ if None (the default), the value of the environment variable
+ KCONFIG_CONFIG_HEADER had when the Kconfig instance was created will
+ be used if it was set, and no header otherwise. See the
+ Kconfig.config_header attribute.
save_old (default: True):
If True and <filename> already exists, a copy of it will be saved to
contents = self._config_contents(header)
if self._contents_eq(filename, contents):
- return "No change to '{}'".format(filename)
+ return "No change to configuration in '{}'".format(filename)
if save_old:
_save_old(filename)
def _config_contents(self, header):
# write_config() helper. Returns the contents to write as a string,
- # with 'header' at the beginning.
+ # with 'header' or KCONFIG_CONFIG_HEADER at the beginning.
#
# More memory friendly would be to 'yield' the strings and
# "".join(_config_contents()), but it was a bit slower on my system.
for sym in self.unique_defined_syms:
sym._visited = False
- # Did we just print an '# end of ...' comment?
- after_end_comment = False
+ if header is None:
+ header = self.config_header
- # "".join()ed later
- chunks = [header]
+ chunks = [header] # "".join()ed later
add = chunks.append
+ # Did we just print an '# end of ...' comment?
+ after_end_comment = False
+
node = self.top_node
while 1:
# Jump to the next node with an iterative tree walk
add("\n#\n# {}\n#\n".format(node.prompt[0]))
after_end_comment = False
- def write_min_config(self, filename,
- header="# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)\n"):
+ def write_min_config(self, filename, header=None):
"""
Writes out a "minimal" configuration file, omitting symbols whose value
matches their default value. The format matches the one produced by
(OSError/IOError). KconfigError is never raised here.
filename:
- Self-explanatory.
+ Path to write minimal configuration to.
- header (default: "# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)\n"):
- Text that will be inserted verbatim at the beginning of the file. You
- would usually want each line to start with '#' to make it a comment,
- and include a final terminating newline.
+ header (default: None):
+ Text inserted verbatim at the beginning of the file. You would
+ usually want each line to start with '#' to make it a comment, and
+ include a final terminating newline.
- Returns a string with a message saying which file got saved. This is
- meant to reduce boilerplate in tools, which can do e.g.
+ if None (the default), the value of the environment variable
+ KCONFIG_CONFIG_HEADER had when the Kconfig instance was created will
+ be used if it was set, and no header otherwise. See the
+ Kconfig.config_header attribute.
+
+ Returns a string with a message saying the minimal configuration got
+ saved, or that there were no changes to it. This is meant to reduce
+ boilerplate in tools, which can do e.g.
print(kconf.write_min_config()).
"""
- contents = self._min_config_contents(header)
- if self._contents_eq(filename, contents):
- return "No change to '{}'".format(filename)
-
- with self._open(filename, "w") as f:
- f.write(contents)
-
- return "Minimal configuration saved to '{}'".format(filename)
+ if self._write_if_changed(filename, self._min_config_contents(header)):
+ return "Minimal configuration saved to '{}'".format(filename)
+ return "No change to minimal configuration in '{}'".format(filename)
def _min_config_contents(self, header):
# write_min_config() helper. Returns the contents to write as a string,
- # with 'header' at the beginning.
+ # with 'header' or KCONFIG_CONFIG_HEADER at the beginning.
- chunks = [header]
+ if header is None:
+ header = self.config_header
+
+ chunks = [header] # "".join()ed later
add = chunks.append
for sym in self.unique_defined_syms:
# it's part of a different construct
if self._reuse_tokens:
self._reuse_tokens = False
- # self._tokens_i is known to be 1 here, because _parse_properties()
- # leaves it like that when it can't recognize a line (or parses
- # a help text)
+ # self._tokens_i is known to be 1 here, because _parse_props()
+ # leaves it like that when it can't recognize a line (or parses a
+ # help text)
return True
# readline() returns '' over and over at EOF, which we rely on for help
self._tokens = self._tokenize(line)
# Initialize to 1 instead of 0 to factor out code from _parse_block()
- # and _parse_properties(). They immediately fetch self._tokens[0].
+ # and _parse_props(). They immediately fetch self._tokens[0].
self._tokens_i = 1
return True
# differs, but it breaks stuff like write_config("/dev/null"), which is
# used out there to force evaluation-related warnings to be generated.
# This simple version is pretty failsafe and portable.
+ #
+ # Returns True if the file has changed and is updated, and False
+ # otherwise.
- if not self._contents_eq(filename, contents):
- with self._open(filename, "w") as f:
- f.write(contents)
+ if self._contents_eq(filename, contents):
+ return False
+ with self._open(filename, "w") as f:
+ f.write(contents)
+ return True
def _contents_eq(self, filename, contents):
# Returns True if the contents of 'filename' is 'contents' (a string),
while 1:
match = _name_special_search(s, i)
- if match.group() == "$(":
- s, i = self._expand_macro(s, match.start(), ())
- else:
+ if match.group() != "$(":
return (s, match.start())
+ s, i = self._expand_macro(s, match.start(), ())
def _expand_str(self, s, i):
# Expands a quoted string starting at index 'i' in 's'. Handles both
# Returns the expanded 's' (including the part before the macro) and
# the index of the first character after the expanded macro in 's'.
- start = i
+ res = s[:i]
i += 2 # Skip over "$("
- # Start of current macro argument
- arg_start = i
-
- # Arguments of this macro call
- new_args = []
+ arg_start = i # Start of current macro argument
+ new_args = [] # Arguments of this macro call
+ nesting = 0 # Current parentheses nesting level
while 1:
match = _macro_special_search(s, i)
self._parse_error("missing end parenthesis in macro expansion")
- if match.group() == ")":
+ if match.group() == "(":
+ nesting += 1
+ i = match.end()
+
+ elif match.group() == ")":
+ if nesting:
+ nesting -= 1
+ i = match.end()
+ continue
+
# Found the end of the macro
new_args.append(s[arg_start:match.start()])
- prefix = s[:start]
-
# $(1) is replaced by the first argument to the function, etc.,
# provided at least that many arguments were passed
try:
# Does the macro look like an integer, with a corresponding
# argument? If so, expand it to the value of the argument.
- prefix += args[int(new_args[0])]
+ res += args[int(new_args[0])]
except (ValueError, IndexError):
# Regular variables are just functions without arguments,
# and also go through the function value path
- prefix += self._fn_val(new_args)
+ res += self._fn_val(new_args)
- return (prefix + s[match.end():],
- len(prefix))
+ return (res + s[match.end():], len(res))
elif match.group() == ",":
+ i = match.end()
+ if nesting:
+ continue
+
# Found the end of a macro argument
new_args.append(s[arg_start:match.start()])
- arg_start = i = match.end()
+ arg_start = i
else: # match.group() == "$("
# A nested macro call within the macro
#
# prev:
# The previous menu node. New nodes will be added after this one (by
- # modifying their 'next' pointer).
+ # modifying 'next' pointers).
#
# 'prev' is reused to parse a list of child menu nodes (for a menu or
# Choice): After parsing the children, the 'next' pointer is assigned
sym.nodes.append(node)
- self._parse_properties(node)
+ self._parse_props(node)
if node.is_menuconfig and not node.prompt:
self._warn("the menuconfig symbol {} has no prompt"
- .format(_name_and_loc(sym)))
+ .format(sym.name_and_loc))
# Equivalent to
#
self.menus.append(node)
- self._parse_properties(node)
+ self._parse_props(node)
self._parse_block(_T_ENDMENU, node, node)
node.list = node.next
self.comments.append(node)
- self._parse_properties(node)
+ self._parse_props(node)
prev.next = prev = node
choice.nodes.append(node)
- self._parse_properties(node)
+ self._parse_props(node)
self._parse_block(_T_ENDCHOICE, node, node)
node.list = node.next
"no corresponding 'menu'" if t0 is _T_ENDMENU else
"unrecognized construct")
- # End of file reached. Terminate the final node and return it.
+ # End of file reached. Return the last node.
if end_token:
raise KconfigError(
- "expected '{}' at end of '{}'"
+ "error: expected '{}' at end of '{}'"
.format("endchoice" if end_token is _T_ENDCHOICE else
"endif" if end_token is _T_ENDIF else
"endmenu",
self.filename))
- prev.next = None
return prev
def _parse_cond(self):
return expr
- def _parse_properties(self, node):
+ def _parse_props(self, node):
# Parses and adds properties to the MenuNode 'node' (type, 'prompt',
# 'default's, etc.) Properties are later copied up to symbols and
# choices in a separate pass after parsing, in e.g.
if t0 in _TYPE_TOKENS:
# Relies on '_T_BOOL is BOOL', etc., to save a conversion
- self._set_type(node, t0)
+ self._set_type(node.item, t0)
if self._tokens[1] is not None:
self._parse_prompt(node)
self._parse_cond()))
elif t0 in _DEF_TOKEN_TO_TYPE:
- self._set_type(node, _DEF_TOKEN_TO_TYPE[t0])
+ self._set_type(node.item, _DEF_TOKEN_TO_TYPE[t0])
node.defaults.append((self._parse_expr(False),
self._parse_cond()))
self._reuse_tokens = True
return
- def _set_type(self, node, new_type):
+ def _set_type(self, sc, new_type):
+ # Sets the type of 'sc' (symbol or choice) to 'new_type'
+
# UNKNOWN is falsy
- if node.item.orig_type and node.item.orig_type is not new_type:
+ if sc.orig_type and sc.orig_type is not new_type:
self._warn("{} defined with multiple types, {} will be used"
- .format(_name_and_loc(node.item),
- TYPE_TO_STR[new_type]))
+ .format(sc.name_and_loc, TYPE_TO_STR[new_type]))
- node.item.orig_type = new_type
+ sc.orig_type = new_type
def _parse_prompt(self, node):
# 'prompt' properties override each other within a single definition of
# multiple times
if node.prompt:
- self._warn(_name_and_loc(node.item) +
+ self._warn(node.item.name_and_loc +
" defined with multiple prompts in single location")
prompt = self._tokens[1]
self._parse_error("expected prompt string")
if prompt != prompt.strip():
- self._warn(_name_and_loc(node.item) +
+ self._warn(node.item.name_and_loc +
" has leading or trailing whitespace in its prompt")
# This avoid issues for e.g. reStructuredText documentation, where
def _parse_help(self, node):
if node.help is not None:
- self._warn(_name_and_loc(node.item) + " defined with more than "
+ self._warn(node.item.name_and_loc + " defined with more than "
"one help text -- only the last one will be used")
# Micro-optimization. This code is pretty hot.
self._line_after_help(line)
def _empty_help(self, node, line):
- self._warn(_name_and_loc(node.item) +
+ self._warn(node.item.name_and_loc +
" has 'help' but empty help text")
node.help = ""
if line:
# The calculated sets might be larger than necessary as we don't do any
# complex analysis of the expressions.
- make_depend_on = _make_depend_on # Micro-optimization
+ depend_on = _depend_on # Micro-optimization
# Only calculate _dependents for defined symbols. Constant and
# undefined symbols could theoretically be selected/implied, but it
# The prompt conditions
for node in sym.nodes:
if node.prompt:
- make_depend_on(sym, node.prompt[1])
+ depend_on(sym, node.prompt[1])
# The default values and their conditions
for value, cond in sym.defaults:
- make_depend_on(sym, value)
- make_depend_on(sym, cond)
+ depend_on(sym, value)
+ depend_on(sym, cond)
# The reverse and weak reverse dependencies
- make_depend_on(sym, sym.rev_dep)
- make_depend_on(sym, sym.weak_rev_dep)
+ depend_on(sym, sym.rev_dep)
+ depend_on(sym, sym.weak_rev_dep)
# The ranges along with their conditions
for low, high, cond in sym.ranges:
- make_depend_on(sym, low)
- make_depend_on(sym, high)
- make_depend_on(sym, cond)
+ depend_on(sym, low)
+ depend_on(sym, high)
+ depend_on(sym, cond)
# The direct dependencies. This is usually redundant, as the direct
# dependencies get propagated to properties, but it's needed to get
# invalidation solid for 'imply', which only checks the direct
# dependencies (even if there are no properties to propagate it
# to).
- make_depend_on(sym, sym.direct_dep)
+ depend_on(sym, sym.direct_dep)
# In addition to the above, choice symbols depend on the choice
# they're in, but that's handled automatically since the Choice is
# The prompt conditions
for node in choice.nodes:
if node.prompt:
- make_depend_on(choice, node.prompt[1])
+ depend_on(choice, node.prompt[1])
# The default symbol conditions
for _, cond in choice.defaults:
- make_depend_on(choice, cond)
+ depend_on(choice, cond)
def _add_choice_deps(self):
# Choices also depend on the choice symbols themselves, because the
if target_sym.orig_type not in _BOOL_TRISTATE_UNKNOWN:
self._warn("{} selects the {} symbol {}, which is not "
"bool or tristate"
- .format(_name_and_loc(sym),
+ .format(sym.name_and_loc,
TYPE_TO_STR[target_sym.orig_type],
- _name_and_loc(target_sym)))
+ target_sym.name_and_loc))
for target_sym, _ in sym.implies:
if target_sym.orig_type not in _BOOL_TRISTATE_UNKNOWN:
self._warn("{} implies the {} symbol {}, which is not "
"bool or tristate"
- .format(_name_and_loc(sym),
+ .format(sym.name_and_loc,
TYPE_TO_STR[target_sym.orig_type],
- _name_and_loc(target_sym)))
+ target_sym.name_and_loc))
elif sym.orig_type: # STRING/INT/HEX
for default, _ in sym.defaults:
if default.__class__ is not Symbol:
raise KconfigError(
- "the {} symbol {} has a malformed default {} -- expected "
- "a single symbol"
- .format(TYPE_TO_STR[sym.orig_type], _name_and_loc(sym),
- expr_str(default)))
+ "the {} symbol {} has a malformed default {} -- "
+ "expected a single symbol"
+ .format(TYPE_TO_STR[sym.orig_type],
+ sym.name_and_loc, expr_str(default)))
if sym.orig_type is STRING:
if not default.is_constant and not default.nodes and \
# (and no symbol named 'foo' exists).
self._warn("style: quotes recommended around "
"default value for string symbol "
- + _name_and_loc(sym))
+ + sym.name_and_loc)
elif not num_ok(default, sym.orig_type): # INT/HEX
self._warn("the {0} symbol {1} has a non-{0} default {2}"
.format(TYPE_TO_STR[sym.orig_type],
- _name_and_loc(sym),
- _name_and_loc(default)))
+ sym.name_and_loc,
+ default.name_and_loc))
if sym.selects or sym.implies:
self._warn("the {} symbol {} has selects or implies"
.format(TYPE_TO_STR[sym.orig_type],
- _name_and_loc(sym)))
+ sym.name_and_loc))
else: # UNKNOWN
self._warn("{} defined without a type"
- .format(_name_and_loc(sym)))
+ .format(sym.name_and_loc))
if sym.ranges:
self._warn(
"the {} symbol {} has ranges, but is not int or hex"
.format(TYPE_TO_STR[sym.orig_type],
- _name_and_loc(sym)))
+ sym.name_and_loc))
else:
for low, high, _ in sym.ranges:
if not num_ok(low, sym.orig_type) or \
self._warn("the {0} symbol {1} has a non-{0} "
"range [{2}, {3}]"
.format(TYPE_TO_STR[sym.orig_type],
- _name_and_loc(sym),
- _name_and_loc(low),
- _name_and_loc(high)))
+ sym.name_and_loc,
+ low.name_and_loc,
+ high.name_and_loc))
def _check_choice_sanity(self):
# Checks various choice properties that are handiest to check after
def warn_select_imply(sym, expr, expr_type):
msg = "the choice symbol {} is {} by the following symbols, but " \
"select/imply has no effect on choice symbols" \
- .format(_name_and_loc(sym), expr_type)
+ .format(sym.name_and_loc, expr_type)
# si = select/imply
for si in split_expr(expr, OR):
- msg += "\n - " + _name_and_loc(split_expr(si, AND)[0])
+ msg += "\n - " + split_expr(si, AND)[0].name_and_loc
self._warn(msg)
for choice in self.unique_choices:
if choice.orig_type not in _BOOL_TRISTATE:
self._warn("{} defined with type {}"
- .format(_name_and_loc(choice),
+ .format(choice.name_and_loc,
TYPE_TO_STR[choice.orig_type]))
for node in choice.nodes:
if node.prompt:
break
else:
- self._warn(_name_and_loc(choice) + " defined without a prompt")
+ self._warn(choice.name_and_loc + " defined without a prompt")
for default, _ in choice.defaults:
if default.__class__ is not Symbol:
raise KconfigError(
"{} has a malformed default {}"
- .format(_name_and_loc(choice), expr_str(default)))
+ .format(choice.name_and_loc, expr_str(default)))
if default.choice is not choice:
self._warn("the default selection {} of {} is not "
"contained in the choice"
- .format(_name_and_loc(default),
- _name_and_loc(choice)))
+ .format(default.name_and_loc,
+ choice.name_and_loc))
for sym in choice.syms:
if sym.defaults:
self._warn("default on the choice symbol {} will have "
"no effect, as defaults do not affect choice "
- "symbols".format(_name_and_loc(sym)))
+ "symbols".format(sym.name_and_loc))
if sym.rev_dep is not sym.kconfig.n:
warn_select_imply(sym, sym.rev_dep, "selected")
if node.parent.item is choice:
if not node.prompt:
self._warn("the choice symbol {} has no prompt"
- .format(_name_and_loc(sym)))
+ .format(sym.name_and_loc))
elif node.prompt:
self._warn("the choice symbol {} is defined with a "
"prompt outside the choice"
- .format(_name_and_loc(sym)))
+ .format(sym.name_and_loc))
def _parse_error(self, msg):
- raise KconfigError("{}couldn't parse '{}': {}".format(
+ raise KconfigError("{}error: couldn't parse '{}': {}".format(
"" if self.filename is None else
"{}:{}: ".format(self.filename, self.linenr),
self._line.strip(), msg))
The type as given in the Kconfig file, without any magic applied. Used
when printing the symbol.
+ tri_value:
+ The tristate value of the symbol as an integer. One of 0, 1, 2,
+ representing n, m, y. Always 0 (n) for non-bool/tristate symbols.
+
+ This is the symbol value that's used outside of relation expressions
+ (A, !A, A && B, A || B).
+
str_value:
The value of the symbol as a string. Gives the value for string/int/hex
symbols. For bool/tristate symbols, gives "n", "m", or "y".
This is the symbol value that's used in relational expressions
(A = B, A != B, etc.)
- Gotcha: For int/hex symbols, the exact format of the value must often be
- preserved (e.g., when writing a .config file), hence why you can't get it
+ Gotcha: For int/hex symbols, the exact format of the value is often
+ preserved (e.g. when writing a .config file), hence why you can't get it
directly as an int. Do int(int_sym.str_value) or
int(hex_sym.str_value, 16) to get the integer value.
- tri_value:
- The tristate value of the symbol as an integer. One of 0, 1, 2,
- representing n, m, y. Always 0 (n) for non-bool/tristate symbols.
+ user_value:
+ The user value of the symbol. None if no user value has been assigned
+ (via Kconfig.load_config() or Symbol.set_value()).
- This is the symbol value that's used outside of relation expressions
- (A, !A, A && B, A || B).
+ Holds 0, 1, or 2 for bool/tristate symbols, and a string for the other
+ symbol types.
+
+ WARNING: Do not assign directly to this. It will break things. Use
+ Symbol.set_value().
assignable:
A tuple containing the tristate user values that can currently be
The visibility of the symbol. One of 0, 1, 2, representing n, m, y. See
the module documentation for an overview of symbol values and visibility.
- user_value:
- The user value of the symbol. None if no user value has been assigned
- (via Kconfig.load_config() or Symbol.set_value()).
-
- Holds 0, 1, or 2 for bool/tristate symbols, and a string for the other
- symbol types.
-
- WARNING: Do not assign directly to this. It will break things. Use
- Symbol.set_value().
-
config_string:
The .config assignment string that would get written out for the symbol
by Kconfig.write_config(). Returns the empty string if no .config
though you might get some special symbols and possibly some "redundant"
n-valued symbol entries in there.
+ name_and_loc:
+ Holds a string like
+
+ "MY_SYMBOL (defined at foo/Kconfig:12, bar/Kconfig:14)"
+
+ , giving the name of the symbol and its definition location(s).
+
+ If the symbol is undefined, the location is given as "(undefined)".
+
nodes:
A list of MenuNodes for this symbol. Will contain a single MenuNode for
most symbols. Undefined and constant symbols have an empty nodes list.
"being outside the active range ([{}, {}]) -- falling "
"back on defaults"
.format(num2str(user_val), TYPE_TO_STR[self.orig_type],
- _name_and_loc(self),
+ self.name_and_loc,
num2str(low), num2str(high)))
else:
# If the user value is well-formed and satisfies range
self.kconfig._warn(
"default value {} on {} clamped to {} due to "
"being outside the active range ([{}, {}])"
- .format(val_num, _name_and_loc(self),
+ .format(val_num, self.name_and_loc,
num2str(clamp), num2str(low),
num2str(high)))
self.kconfig._warn(
"The {} symbol {} is being evaluated in a logical context "
"somewhere. It will always evaluate to n."
- .format(TYPE_TO_STR[self.orig_type], _name_and_loc(self)))
+ .format(TYPE_TO_STR[self.orig_type], self.name_and_loc))
self._cached_tri_val = 0
return 0
return '{}{}="{}"\n' \
.format(self.kconfig.config_prefix, self.name, escape(val))
+ @property
+ def name_and_loc(self):
+ """
+ See the class documentation.
+ """
+ return self.name + " " + _locs(self)
+
def set_value(self, value):
"""
Sets the user value of the symbol.
value:
The user value to give to the symbol. For bool and tristate symbols,
n/m/y can be specified either as 0/1/2 (the usual format for tristate
- values in Kconfiglib) or as one of the strings "n"/"m"/"y". For other
- symbol types, pass a string.
+ values in Kconfiglib) or as one of the strings "n", "m", or "y". For
+ other symbol types, pass a string.
Note that the value for an int/hex symbol is passed as a string, e.g.
"123" or "0x0123". The format of this string is preserved in the
"assignment ignored"
.format(TRI_TO_STR[value] if value in TRI_TO_STR else
"'{}'".format(value),
- _name_and_loc(self), TYPE_TO_STR[self.orig_type]))
+ self.name_and_loc, TYPE_TO_STR[self.orig_type]))
return False
return
if self.kconfig._warn_assign_no_prompt:
- self.kconfig._warn(_name_and_loc(self) + " has no prompt, meaning "
+ self.kconfig._warn(self.name_and_loc + " has no prompt, meaning "
"user values have no effect on it")
def _str_default(self):
msg = "{} has direct dependencies {} with value {}, but is " \
"currently being {}-selected by the following symbols:" \
- .format(_name_and_loc(self), expr_str(self.direct_dep),
+ .format(self.name_and_loc, expr_str(self.direct_dep),
TRI_TO_STR[expr_value(self.direct_dep)],
TRI_TO_STR[expr_value(self.rev_dep)])
msg += "\n - {}, with value {}, direct dependencies {} " \
"(value: {})" \
- .format(_name_and_loc(selecting_sym),
+ .format(selecting_sym.name_and_loc,
selecting_sym.str_value,
expr_str(selecting_sym.direct_dep),
TRI_TO_STR[expr_value(selecting_sym.direct_dep)])
Corresponding attributes have the same name in the Symbol and Choice
classes, for consistency and compatibility.
+ str_value:
+ Like choice.tri_value, but gives the value as one of the strings
+ "n", "m", or "y"
+
+ user_value:
+ The value (mode) selected by the user through Choice.set_value(). Either
+ 0, 1, or 2, or None if the user hasn't selected a mode. See
+ Symbol.user_value.
+
+ WARNING: Do not assign directly to this. It will break things. Use
+ Choice.set_value() instead.
+
assignable:
See the symbol class documentation. Gives the assignable values (modes).
- visibility:
- See the Symbol class documentation. Acts on the value (mode).
-
selection:
The Symbol instance of the currently selected symbol. None if the Choice
is not in y mode or has no selected symbol (due to unsatisfied
WARNING: Do not assign directly to this. It will break things. Call
sym.set_value(2) on the choice symbol you want to select instead.
- user_value:
- The value (mode) selected by the user through Choice.set_value(). Either
- 0, 1, or 2, or None if the user hasn't selected a mode. See
- Symbol.user_value.
-
- WARNING: Do not assign directly to this. It will break things. Use
- Choice.set_value() instead.
-
user_selection:
The symbol selected by the user (by setting it to y). Ignored if the
choice is not in y mode, but still remembered so that the choice "snaps
WARNING: Do not assign directly to this. It will break things. Call
sym.set_value(2) on the choice symbol to be selected instead.
+ visibility:
+ See the Symbol class documentation. Acts on the value (mode).
+
+ name_and_loc:
+ Holds a string like
+
+ "<choice MY_CHOICE> (defined at foo/Kconfig:12)"
+
+ , giving the name of the choice and its definition location(s). If the
+ choice has no name (isn't defined with 'choice MY_CHOICE'), then it will
+ be shown as "<choice>" before the list of locations (always a single one
+ in that case).
+
syms:
List of symbols contained in the choice.
return self._cached_vis
@property
+ def name_and_loc(self):
+ """
+ See the class documentation.
+ """
+ # Reuse the expression format, which is '<choice (name, if any)>'.
+ return standard_sc_expr_str(self) + " " + _locs(self)
+
+ @property
def selection(self):
"""
See the class documentation.
"assignment ignored"
.format(TRI_TO_STR[value] if value in TRI_TO_STR else
"'{}'".format(value),
- _name_and_loc(self), TYPE_TO_STR[self.orig_type]))
+ self.name_and_loc, TYPE_TO_STR[self.orig_type]))
return False
self._cached_selection = _NO_CACHED_SELECTION
- # is_constant is checked by _make_depend_on(). Just set it to avoid
- # having to special-case choices.
+ # is_constant is checked by _depend_on(). Just set it to avoid having
+ # to special-case choices.
self.is_constant = self.is_optional = False
# See Kconfig._build_dep()
_unescape_sub = re.compile(r"\\(.)").sub
-def standard_kconfig():
+def standard_kconfig(description=None):
"""
- Helper for tools. Loads the top-level Kconfig specified as the first
- command-line argument, or "Kconfig" if there are no command-line arguments.
- Returns the Kconfig instance.
+ Argument parsing helper for tools that take a single optional Kconfig file
+ argument (default: Kconfig). Returns the Kconfig instance for the parsed
+ configuration. Uses argparse internally.
+
+ Exits with sys.exit() (which raises SystemExit) on errors.
- Exits with sys.exit() (which raises a SystemExit exception) and prints a
- usage note to stderr if more than one command-line argument is passed.
+ description (default: None):
+ The 'description' passed to argparse.ArgumentParser().
+ argparse.RawDescriptionHelpFormatter is used, so formatting is preserved.
"""
- if len(sys.argv) > 2:
- sys.exit("usage: {} [Kconfig]".format(sys.argv[0]))
+ import argparse
- # Only show backtraces for unexpected exceptions
- try:
- return Kconfig("Kconfig" if len(sys.argv) < 2 else sys.argv[1])
- except (EnvironmentError, KconfigError) as e:
- # Some long exception messages have extra newlines for better
- # formatting when reported as an unhandled exception. Strip them here.
- sys.exit(str(e).strip())
+ parser = argparse.ArgumentParser(
+ formatter_class=argparse.RawDescriptionHelpFormatter,
+ description=description)
+
+ parser.add_argument(
+ "kconfig",
+ metavar="KCONFIG",
+ default="Kconfig",
+ nargs="?",
+ help="Top-level Kconfig file (default: Kconfig)")
+
+ return Kconfig(parser.parse_args().kconfig, suppress_traceback=True)
def standard_config_filename():
def load_allconfig(kconf, filename):
"""
- Helper for all*config. Loads (merges) the configuration file specified by
- KCONFIG_ALLCONFIG, if any. See Documentation/kbuild/kconfig.txt in the
- Linux kernel.
-
- Disables warnings for duplicated assignments within configuration files for
- the duration of the call (kconf.warn_assign_override/warn_assign_redun = False),
- and restores the previous warning settings at the end. The
- KCONFIG_ALLCONFIG configuration file is expected to override symbols.
-
- Exits with sys.exit() (which raises a SystemExit exception) and prints an
- error to stderr if KCONFIG_ALLCONFIG is set but the configuration file
- can't be opened.
-
- kconf:
- Kconfig instance to load the configuration in.
-
- filename:
- Command-specific configuration filename - "allyes.config",
- "allno.config", etc.
+ Use Kconfig.load_allconfig() instead, which was added in Kconfiglib 13.4.0.
+ Supported for backwards compatibility. Might be removed at some point after
+ a long period of deprecation warnings.
"""
allconfig = os.getenv("KCONFIG_ALLCONFIG")
if allconfig is None:
return vis
-def _make_depend_on(sc, expr):
+def _depend_on(sc, expr):
# Adds 'sc' (symbol or choice) as a "dependee" to all symbols in 'expr'.
# Constant symbols in 'expr' are skipped as they can never change value
# anyway.
if expr.__class__ is tuple:
# AND, OR, NOT, or relation
- _make_depend_on(sc, expr[1])
+ _depend_on(sc, expr[1])
# NOTs only have a single operand
if expr[0] is not NOT:
- _make_depend_on(sc, expr[2])
+ _depend_on(sc, expr[2])
elif not expr.is_constant:
# Non-constant symbol, or choice
pass
-def _name_and_loc(sc):
- # Helper for giving the symbol/choice name and location(s) in e.g. warnings
+def _locs(sc):
+ # Symbol/Choice.name_and_loc helper. Returns the "(defined at ...)" part of
+ # the string. 'sc' is a Symbol or Choice.
- # Reuse the expression format. That way choices show up as
- # '<choice (name, if any)>'
- name = standard_sc_expr_str(sc)
+ if sc.nodes:
+ return "(defined at {})".format(
+ ", ".join("{0.filename}:{0.linenr}".format(node)
+ for node in sc.nodes))
- if not sc.nodes:
- return name + " (undefined)"
-
- return "{} (defined at {})".format(
- name,
- ", ".join("{}:{}".format(node.filename, node.linenr)
- for node in sc.nodes))
+ return "(undefined)"
# Menu manipulation
msg += "the choice symbol "
msg += "{}, with definition...\n\n{}\n\n" \
- .format(_name_and_loc(item), item)
+ .format(item.name_and_loc, item)
# Small wart: Since we reuse the already calculated
# Symbol/Choice._dependents sets for recursive dependency detection, we
msg += "(imply-related dependencies: {})\n\n" \
.format(expr_str(item.rev_dep))
- msg += "...depends again on {}".format(_name_and_loc(loop[0]))
+ msg += "...depends again on " + loop[0].name_and_loc
raise KconfigError(msg)
def _shell_fn(kconf, _, command):
- # Only import as needed, to save some startup time
- import subprocess
+ import subprocess # Only import as needed, to save some startup time
stdout, stderr = subprocess.Popen(
command, shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE
# variable assignment
_assignment_rhs_match = _re_match(r"\s*(=|:=|\+=)\s*(.*)")
-# Special characters/strings while expanding a macro (')', ',', and '$(')
-_macro_special_search = _re_search(r"\)|,|\$\(")
+# Special characters/strings while expanding a macro ('(', ')', ',', and '$(')
+_macro_special_search = _re_search(r"\(|\)|,|\$\(")
# Special characters/strings while expanding a string (quotes, '\', and '$(')
_string_special_search = _re_search(r'"|\'|\\|\$\(')
build.commits = self.commits
build.commit_count = len(self.commits)
subject = self.commits[1].subject.translate(builder.trans_valid_chars)
- dirname ='/%02d_of_%02d_g%s_%s' % (2, build.commit_count, commits[1][0],
+ dirname ='/%02d_g%s_%s' % (2, build.commit_count, commits[1][0],
subject[:20])
self.CheckDirs(build, dirname)
base_dir = tempfile.mkdtemp()
# Add various files that we want removed and left alone
- to_remove = ['01_of_22_g0982734987_title', '102_of_222_g92bf_title',
- '01_of_22_g2938abd8_title']
- to_leave = ['something_else', '01-something.patch', '01_of_22_another']
+ to_remove = ['01_g0982734987_title', '102_g92bf_title',
+ '01_g2938abd8_title']
+ to_leave = ['something_else', '01-something.patch', '01_another']
for name in to_remove + to_leave:
_Touch(name)
--- /dev/null
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+
+"""
+Simple tool to swap the byte endianness of a binary file.
+"""
+
+import argparse
+import io
+
+def parse_args():
+ """Parse command line arguments."""
+ description = "Swap endianness of given input binary and write to output binary."
+
+ parser = argparse.ArgumentParser(description=description)
+ parser.add_argument("input_bin", type=str, help="input binary")
+ parser.add_argument("output_bin", type=str, help="output binary")
+ parser.add_argument("-c", action="store", dest="chunk_size", type=int,
+ default=io.DEFAULT_BUFFER_SIZE, help="chunk size for reading")
+
+ return parser.parse_args()
+
+def swap_chunk(chunk_orig):
+ """Swap byte endianness of the given chunk.
+
+ Returns:
+ swapped chunk
+ """
+ chunk = bytearray(chunk_orig)
+
+ # align to 4 bytes and pad with 0x0
+ chunk_len = len(chunk)
+ pad_len = chunk_len % 4
+ if pad_len > 0:
+ chunk += b'\x00' * (4 - pad_len)
+
+ chunk[0::4], chunk[1::4], chunk[2::4], chunk[3::4] =\
+ chunk[3::4], chunk[2::4], chunk[1::4], chunk[0::4]
+
+ return chunk
+
+def main():
+ args = parse_args()
+
+ with open(args.input_bin, "rb") as input_bin:
+ with open(args.output_bin, "wb") as output_bin:
+ while True:
+ chunk = bytearray(input_bin.read(args.chunk_size))
+ if not chunk:
+ break
+
+ output_bin.write(swap_chunk(chunk))
+
+if __name__ == '__main__':
+ main()
LOADADDR=0x41c00000
BOOTCORE_OPTS=0
BOOTCORE=16
+DEBUG_TYPE=0
gen_degen_template() {
cat << 'EOF' > degen-template.txt
[ debug ]
debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000
- debugType = INTEGER:4
+ debugType = INTEGER:TEST_DEBUG_TYPE
coreDbgEn = INTEGER:0
coreDbgSecEn = INTEGER:0
EOF
options_help[o]="output_file:Name of the final output file. default to $OUTPUT"
options_help[c]="core_id:target core id on which the image would be running. Default to $BOOTCORE"
options_help[l]="loadaddr: Target load address of the binary in hex. Default to $LOADADDR"
+options_help[d]="debug_type: Debug type, set to 4 to enable early JTAG. Default to $DEBUG_TYPE"
-while getopts "b:k:o:c:l:h" opt
+while getopts "b:k:o:c:l:d:h" opt
do
case $opt in
b)
c)
BOOTCORE=$OPTARG
;;
+ d)
+ DEBUG_TYPE=$OPTARG
+ ;;
h)
usage
exit 0
#echo " LOADADDR = 0x$ADDR"
#echo " IMAGE_SIZE = $BIN_SIZE"
#echo " CERT_TYPE = $CERTTYPE"
+ #echo " DEBUG_TYPE = $DEBUG_TYPE"
sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/" \
-e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \
-e "s/TEST_CERT_TYPE/$CERTTYPE/" \
-e "s/TEST_BOOT_CORE_OPTS/$BOOTCORE_OPTS/" \
-e "s/TEST_BOOT_CORE/$BOOTCORE/" \
- -e "s/TEST_BOOT_ADDR/$ADDR/" x509-template.txt > $TEMP_X509
+ -e "s/TEST_BOOT_ADDR/$ADDR/" \
+ -e "s/TEST_DEBUG_TYPE/$DEBUG_TYPE/" \
+ x509-template.txt > $TEMP_X509
openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config $TEMP_X509 -sha512
}
'stdout']
result = collections.namedtuple('CheckPatchResult', fields)
result.ok = False
- result.errors, result.warning, result.checks = 0, 0, 0
+ result.errors, result.warnings, result.checks = 0, 0, 0
result.lines = 0
result.problems = []
chk = FindCheckPatch()
# total: 0 errors, 0 warnings, 159 lines checked
# or:
# total: 0 errors, 2 warnings, 7 checks, 473 lines checked
- re_stats = re.compile('total: (\\d+) errors, (\d+) warnings, (\d+)')
- re_stats_full = re.compile('total: (\\d+) errors, (\d+) warnings, (\d+)'
+ emacs_prefix = '(?:[0-9]{4}.*\.patch:[0-9]+: )?'
+ emacs_stats = '(?:[0-9]{4}.*\.patch )?'
+ re_stats = re.compile(emacs_stats +
+ 'total: (\\d+) errors, (\d+) warnings, (\d+)')
+ re_stats_full = re.compile(emacs_stats +
+ 'total: (\\d+) errors, (\d+) warnings, (\d+)'
' checks, (\d+)')
re_ok = re.compile('.*has no obvious style problems')
re_bad = re.compile('.*has style problems, please review')
re_error = re.compile('ERROR: (.*)')
- re_warning = re.compile('WARNING: (.*)')
+ re_warning = re.compile(emacs_prefix + 'WARNING:(?:[A-Z_]+:)? (.*)')
re_check = re.compile('CHECK: (.*)')
re_file = re.compile('#\d+: FILE: ([^:]*):(\d+):')
-
+ re_note = re.compile('NOTE: (.*)')
+ indent = ' ' * 6
for line in result.stdout.splitlines():
if verbose:
print(line)
# A blank line indicates the end of a message
- if not line and item:
- result.problems.append(item)
- item = {}
+ if not line:
+ if item:
+ result.problems.append(item)
+ item = {}
+ continue
+ if re_note.match(line):
+ continue
+ # Skip lines which quote code
+ if line.startswith(indent):
+ continue
+ # Skip code quotes and #<n>
+ if line.startswith('+') or line.startswith('#'):
+ continue
match = re_stats_full.match(line)
if not match:
match = re_stats.match(line)
result.lines = int(match.group(4))
else:
result.lines = int(match.group(3))
+ continue
elif re_ok.match(line):
result.ok = True
+ continue
elif re_bad.match(line):
result.ok = False
+ continue
err_match = re_error.match(line)
warn_match = re_warning.match(line)
file_match = re_file.match(line)
check_match = re_check.match(line)
+ subject_match = line.startswith('Subject:')
if err_match:
item['msg'] = err_match.group(1)
item['type'] = 'error'
elif file_match:
item['file'] = file_match.group(1)
item['line'] = int(file_match.group(2))
+ elif subject_match:
+ item['file'] = '<patch subject>'
+ item['line'] = None
+ else:
+ print('bad line "%s", %d' % (line, len(line)))
return result
msg_type = col.Color(col.RED, msg_type)
elif msg_type == 'check':
msg_type = col.Color(col.MAGENTA, msg_type)
- return '%s:%d: %s: %s\n' % (fname, line, msg_type, msg)
+ line_str = '' if line is None else '%d' % line
+ return '%s:%s: %s: %s\n' % (fname, line_str, msg_type, msg)
def CheckPatches(verbose, args):
'''Run the checkpatch.pl script on each patch'''
projects / platform / kernel / u-boot.git / commitdiff