Merge branch 'master' of git://git.denx.de/u-boot-coldfire
authorTom Rini <trini@konsulko.com>
Sun, 16 Sep 2018 14:32:33 +0000 (10:32 -0400)
committerTom Rini <trini@konsulko.com>
Sun, 16 Sep 2018 14:32:33 +0000 (10:32 -0400)
44 files changed:
Makefile
arch/arm/mach-socfpga/include/mach/sdram_s10.h
arch/sh/include/asm/config.h
arch/sh/include/asm/cpu_sh7724.h
arch/sh/lib/time.c
board/renesas/ap325rxa/cpld-ap325rxa.c
configs/socfpga_stratix10_defconfig
drivers/ddr/altera/sdram_s10.c
drivers/gpio/dwapb_gpio.c
drivers/usb/host/ehci-generic.c
include/configs/MigoR.h
include/configs/alt.h
include/configs/ap325rxa.h
include/configs/ap_sh4a_4a.h
include/configs/armadillo-800eva.h
include/configs/blanche.h
include/configs/ecovec.h
include/configs/espt.h
include/configs/gose.h
include/configs/koelsch.h
include/configs/lager.h
include/configs/mpr2.h
include/configs/ms7720se.h
include/configs/ms7722se.h
include/configs/ms7750se.h
include/configs/porter.h
include/configs/r0p7734.h
include/configs/r2dplus.h
include/configs/r7780mp.h
include/configs/rcar-gen2-common.h
include/configs/rsk7203.h
include/configs/rsk7264.h
include/configs/rsk7269.h
include/configs/sh7752evb.h
include/configs/sh7753evb.h
include/configs/sh7757lcr.h
include/configs/sh7763rdp.h
include/configs/sh7785lcr.h
include/configs/shmin.h
include/configs/silk.h
include/configs/socfpga_stratix10_socdk.h
include/configs/stout.h
include/sh_tmu.h [deleted file]
scripts/config_whitelist.txt

index 1891c3a..e38966e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -985,6 +985,11 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
                $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
 
+OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
+
+spl/u-boot-spl.hex: spl/u-boot-spl FORCE
+       $(call if_changed,objcopy)
+
 binary_size_check: u-boot-nodtb.bin FORCE
        @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
        map_size=$(shell cat u-boot.map | \
index 91bfc0e..ca68594 100644 (file)
@@ -7,7 +7,7 @@
 #ifndef        _SDRAM_S10_H_
 #define        _SDRAM_S10_H_
 
-unsigned long sdram_calculate_size(void);
+phys_size_t sdram_calculate_size(void);
 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
 int sdram_calibration_full(void);
 
index bad0026..d2862df 100644 (file)
@@ -6,4 +6,13 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#if !defined(CONFIG_CPU_SH2)
+#include <asm/processor.h>
+
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER       (TMU_BASE + 0x8)        /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE          (CONFIG_SYS_CLK_FREQ / 4)
+#endif
+
 #endif
index 7a81e16..7b21795 100644 (file)
 #define PYDR        0xA405016A
 #define PZDR        0xA405016C
 
-/* Ether */
-#define EDMR           0xA4600000
-
 /* UBC */
 /* H-UDI */
 
index eb64296..fb317f9 100644 (file)
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <sh_tmu.h>
 
-#define TCR_TPSC 0x07
+#if defined(CONFIG_CPU_SH3)
+#define TSTR   0x2
+#define TCR0   0xc
+#endif /* CONFIG_CPU_SH3 */
 
-static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
+#define TSTR   0x4
+#define TCR0   0x10
+#endif /* CONFIG_CPU_SH4 */
 
-unsigned long get_tbclk(void)
-{
-       u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
-       return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
-}
-
-unsigned long timer_read_counter(void)
-{
-       return ~readl(&tmu->tcnt0);
-}
-
-static void tmu_timer_start(unsigned int timer)
-{
-       if (timer > 2)
-               return;
-       writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
-}
-
-static void tmu_timer_stop(unsigned int timer)
-{
-       if (timer > 2)
-               return;
-       writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
-}
+#define TCR_TPSC       0x07
+#define TSTR_STR0      BIT(0)
 
 int timer_init(void)
 {
-       u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
-       writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
-
-       tmu_timer_stop(0);
-       tmu_timer_start(0);
+       writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0);
+       writeb(readb(TMU_BASE + TSTR) & ~TSTR_STR0, TMU_BASE + TSTR);
+       writeb(readb(TMU_BASE + TSTR) | TSTR_STR0, TMU_BASE + TSTR);
 
        return 0;
 }
index 16fadcb..5d9dc93 100644 (file)
@@ -61,8 +61,6 @@
 #define CPLD_DONE_ADR  ((vu_char *)0xA4050132)
 #define CPLD_DONE_DAT  0x20
 
-#define        HIZCRB                  ((vu_short *)0xA405015A)
-
 /* data */
 #define CPLD_NOMAL_START       0xA0A80000
 #define CPLD_SAFE_START                0xA0AC0000
@@ -191,7 +189,7 @@ void init_cpld(void)
        if (*CPLD_DONE_ADR & CPLD_DONE_DAT)     /* Already DONE */
                return;
 
-       *HIZCRB = 0x0000;
+       *((vu_short *)HIZCRB) = 0x0000;
        *CPLD_PFC_ADR = 0x7c00;                 /* FPGA PROG = OUTPUT */
 
        /* write CPLD data from NOR flash to device */
index c27985a..5f3d733 100644 (file)
@@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
index 48f4f47..a48567c 100644 (file)
@@ -371,11 +371,11 @@ int sdram_mmr_init_full(unsigned int unused)
  * Calculate SDRAM device size based on SDRAM controller parameters.
  * Size is specified in bytes.
  */
-unsigned long sdram_calculate_size(void)
+phys_size_t sdram_calculate_size(void)
 {
        u32 dramaddrw = hmc_readl(DRAMADDRW);
 
-       u32 size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+       phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
                         DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
                         DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
                         DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
index a118f58..0f6574d 100644 (file)
@@ -15,6 +15,7 @@
 #include <dm/lists.h>
 #include <dm/root.h>
 #include <errno.h>
+#include <reset.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,6 +30,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_PORTA_EOI         0x4c
 #define GPIO_EXT_PORT(p)       (0x50 + (p) * 4)
 
+struct gpio_dwapb_priv {
+       struct reset_ctl_bulk   resets;
+};
+
 struct gpio_dwapb_platdata {
        const char      *name;
        int             bank;
@@ -78,20 +83,63 @@ static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
        return 0;
 }
 
+static int dwapb_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+       struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+       u32 gpio;
+
+       gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank));
+
+       if (gpio & BIT(offset))
+               return GPIOF_OUTPUT;
+       else
+               return GPIOF_INPUT;
+}
+
 static const struct dm_gpio_ops gpio_dwapb_ops = {
        .direction_input        = dwapb_gpio_direction_input,
        .direction_output       = dwapb_gpio_direction_output,
        .get_value              = dwapb_gpio_get_value,
        .set_value              = dwapb_gpio_set_value,
+       .get_function           = dwapb_gpio_get_function,
 };
 
+static int gpio_dwapb_reset(struct udevice *dev)
+{
+       int ret;
+       struct gpio_dwapb_priv *priv = dev_get_priv(dev);
+
+       ret = reset_get_bulk(dev, &priv->resets);
+       if (ret) {
+               /* Return 0 if error due to !CONFIG_DM_RESET and reset
+                * DT property is not present.
+                */
+               if (ret == -ENOENT || ret == -ENOTSUPP)
+                       return 0;
+
+               dev_warn(dev, "Can't get reset: %d\n", ret);
+               return ret;
+       }
+
+       ret = reset_deassert_bulk(&priv->resets);
+       if (ret) {
+               reset_release_bulk(&priv->resets);
+               dev_err(dev, "Failed to reset: %d\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+
 static int gpio_dwapb_probe(struct udevice *dev)
 {
        struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
        struct gpio_dwapb_platdata *plat = dev->platdata;
 
-       if (!plat)
-               return 0;
+       if (!plat) {
+               /* Reset on parent device only */
+               return gpio_dwapb_reset(dev);
+       }
 
        priv->gpio_count = plat->pins;
        priv->bank_name = plat->name;
@@ -111,7 +159,7 @@ static int gpio_dwapb_bind(struct udevice *dev)
        if (plat)
                return 0;
 
-       base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+       base = dev_read_addr(dev);
        if (base == FDT_ADDR_T_NONE) {
                debug("Can't get the GPIO register base address\n");
                return -ENXIO;
@@ -152,6 +200,17 @@ err:
        return ret;
 }
 
+static int gpio_dwapb_remove(struct udevice *dev)
+{
+       struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+       struct gpio_dwapb_priv *priv = dev_get_priv(dev);
+
+       if (!plat && priv)
+               return reset_release_bulk(&priv->resets);
+
+       return 0;
+}
+
 static const struct udevice_id gpio_dwapb_ids[] = {
        { .compatible = "snps,dw-apb-gpio" },
        { }
@@ -164,4 +223,6 @@ U_BOOT_DRIVER(gpio_dwapb) = {
        .ops            = &gpio_dwapb_ops,
        .bind           = gpio_dwapb_bind,
        .probe          = gpio_dwapb_probe,
+       .remove         = gpio_dwapb_remove,
+       .priv_auto_alloc_size   = sizeof(struct gpio_dwapb_priv),
 };
index cc2f338..0270f3b 100644 (file)
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <dm.h>
 #include "ehci.h"
+#include <power/regulator.h>
 
 /*
  * Even though here we don't explicitly use "struct ehci_ctrl"
@@ -22,10 +23,56 @@ struct generic_ehci {
        struct clk *clocks;
        struct reset_ctl *resets;
        struct phy phy;
+#ifdef CONFIG_DM_REGULATOR
+       struct udevice *vbus_supply;
+#endif
        int clock_count;
        int reset_count;
 };
 
+#ifdef CONFIG_DM_REGULATOR
+static int ehci_enable_vbus_supply(struct udevice *dev)
+{
+       struct generic_ehci *priv = dev_get_priv(dev);
+       int ret;
+
+       ret = device_get_supply_regulator(dev, "vbus-supply",
+                                         &priv->vbus_supply);
+       if (ret && ret != -ENOENT)
+               return ret;
+
+       if (priv->vbus_supply) {
+               ret = regulator_set_enable(priv->vbus_supply, true);
+               if (ret) {
+                       dev_err(dev, "Error enabling VBUS supply\n");
+                       return ret;
+               }
+       } else {
+               dev_dbg(dev, "No vbus supply\n");
+       }
+
+       return 0;
+}
+
+static int ehci_disable_vbus_supply(struct generic_ehci *priv)
+{
+       if (priv->vbus_supply)
+               return regulator_set_enable(priv->vbus_supply, false);
+       else
+               return 0;
+}
+#else
+static int ehci_enable_vbus_supply(struct udevice *dev)
+{
+       return 0;
+}
+
+static int ehci_disable_vbus_supply(struct generic_ehci *priv)
+{
+       return 0;
+}
+#endif
+
 static int ehci_usb_probe(struct udevice *dev)
 {
        struct generic_ehci *priv = dev_get_priv(dev);
@@ -95,10 +142,14 @@ static int ehci_usb_probe(struct udevice *dev)
                }
        }
 
-       err = ehci_setup_phy(dev, &priv->phy, 0);
+       err = ehci_enable_vbus_supply(dev);
        if (err)
                goto reset_err;
 
+       err = ehci_setup_phy(dev, &priv->phy, 0);
+       if (err)
+               goto regulator_err;
+
        hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
        hcor = (struct ehci_hcor *)((uintptr_t)hccr +
                                    HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
@@ -114,6 +165,11 @@ phy_err:
        if (ret)
                dev_err(dev, "failed to shutdown usb phy\n");
 
+regulator_err:
+       ret = ehci_disable_vbus_supply(priv);
+       if (ret)
+               dev_err(dev, "failed to disable VBUS supply\n");
+
 reset_err:
        ret = reset_release_all(priv->resets, priv->reset_count);
        if (ret)
@@ -139,6 +195,10 @@ static int ehci_usb_remove(struct udevice *dev)
        if (ret)
                return ret;
 
+       ret = ehci_disable_vbus_supply(priv);
+       if (ret)
+               return ret;
+
        ret =  reset_release_all(priv->resets, priv->reset_count);
        if (ret)
                return ret;
index 5cb2348..1ff04c3 100644 (file)
@@ -91,8 +91,6 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 
 #endif /* __MIGO_R_H */
index d44a0b3..cc6a7bf 100644 (file)
@@ -37,9 +37,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "fdt_high=0xffffffff\0"         \
index 8680eb6..40a843a 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 
 #endif /* __AP325RXA_H */
index a4bdd44..b9ff965 100644 (file)
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV      4
 
 #endif /* __AP_SH4A_4A_H */
index c0e1740..3c6b2c3 100644 (file)
@@ -18,6 +18,9 @@
 
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER       (TMU_BASE + 0xc)        /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE          (CONFIG_SYS_CLK_FREQ / 4)
 #define CONFIG_SYS_DCACHE_OFF
 
 /* STACK */
@@ -91,8 +94,6 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    50000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #endif /* __ARMADILLO_800EVA_H */
index 6df0e9b..e0acde3 100644 (file)
@@ -52,8 +52,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 /* ENV setting */
 #if !defined(CONFIG_MTD_NOR_FLASH)
index e99564d..1e358ec 100644 (file)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ 41666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV      4
 
 #endif /* __ECOVEC_H */
index 978a9e0..6bb23c6 100644 (file)
@@ -69,9 +69,7 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ    66666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV      4
 
 /* Ether */
 #define CONFIG_SH_ETHER_USE_PORT (1)
index 00523d2..36ac88a 100644 (file)
@@ -33,9 +33,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "fdt_high=0xffffffff\0"         \
index e5e667c..ef26a14 100644 (file)
@@ -33,9 +33,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "fdt_high=0xffffffff\0"         \
index ebcd179..08498c6 100644 (file)
@@ -34,9 +34,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "fdt_high=0xffffffff\0"         \
index c6023a1..901a302 100644 (file)
@@ -49,9 +49,7 @@
 
 /* Clocks */
 #define CONFIG_SYS_CLK_FREQ    24000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         4       /* 4 (default), 16, 64, 256 or 1024 */
 
 /* UART */
 #define CONFIG_CONS_SCIF0      1
index e717970..b159c10 100644 (file)
@@ -60,9 +60,7 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         4       /* 4 (default), 16, 64, 256 or 1024 */
 
 /* PCMCIA */
 #define CONFIG_IDE_PCMCIA      1
index 1232764..230b86b 100644 (file)
@@ -82,8 +82,6 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 
 #endif /* __MS7722SE_H */
index b2cb6ba..3584906 100644 (file)
@@ -62,8 +62,6 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         4
 
 #endif /* __MS7750SE_H */
index 42b9073..e56dc3f 100644 (file)
@@ -38,9 +38,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "fdt_high=0xffffffff\0"         \
index 523764d..8847685 100644 (file)
@@ -98,8 +98,6 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV      4
 
 #endif /* __R0P7734_H */
index 129dcf3..b39b13b 100644 (file)
@@ -46,9 +46,7 @@
  * SuperH Clock setting
  */
 #define CONFIG_SYS_CLK_FREQ    60000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         4
 #define        CONFIG_SYS_PLL_SETTLING_TIME    100/* in us */
 
 /*
index 8068ca7..a819e1b 100644 (file)
@@ -71,9 +71,7 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         4
 
 /* PCI Controller */
 #if defined(CONFIG_CMD_PCI)
index 2a5cd6b..01583f8 100644 (file)
@@ -22,7 +22,6 @@
 
 #define CONFIG_ARCH_CPU_INIT
 
-#define CONFIG_TMU_TIMER
 #ifndef CONFIG_PINCTRL_PFC
 #define CONFIG_SH_GPIO_PFC
 #endif
 #undef CONFIG_SPI_FLASH_MTD
 #endif
 
+/* Timer */
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER       (TMU_BASE + 0xc)        /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE          (32500000 / 4)          /* CP/4 */
+
 #endif /* __RCAR_GEN2_COMMON_H */
index a40b7ba..ef2b79e 100644 (file)
@@ -58,7 +58,6 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER        32      /* 8 (default), 32, 128 or 512 */
 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
index b936b13..54ca879 100644 (file)
@@ -47,7 +47,6 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    36000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER                32      /* 8 (default), 32, 128 or 512 */
 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
index 0c0b773..f8e66e6 100644 (file)
@@ -46,7 +46,6 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    66125000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER                32      /* 8 (default), 32, 128 or 512 */
 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
index 9b40e0f..1f29e3d 100644 (file)
@@ -75,7 +75,5 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
 #endif /* __SH7752EVB_H */
index 080b405..0693fb5 100644 (file)
@@ -75,7 +75,5 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
 #endif /* __SH7753EVB_H */
index 95d70bc..05b2f01 100644 (file)
@@ -87,7 +87,5 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ    48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
 #endif /* __SH7757LCR_H */
index 4015fb2..2aefc69 100644 (file)
@@ -69,9 +69,7 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ    66666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         (4)     /* 4 (default), 16, 64, 256 or 1024 */
 
 /* Ether */
 #define CONFIG_SH_ETHER_USE_PORT (1)
index 38ae66b..6cb0ef3 100644 (file)
 /* Board Clock */
 /* The SCIF used external clock. system clock only used timer. */
 #define CONFIG_SYS_CLK_FREQ    50000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV         4
 
 #endif /* __SH7785LCR_H */
index aada22d..5eabdf5 100644 (file)
@@ -78,9 +78,7 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 33333333
 #endif /* CONFIG_T_SH7706LSR */
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 /* Network device */
 #define CONFIG_DRIVER_NE2000
index 549aa79..a94928b 100644 (file)
@@ -38,9 +38,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "fdt_high=0xffffffff\0"         \
index b58f478..e190b3d 100644 (file)
@@ -202,6 +202,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
  *
  */
+#define CONFIG_SPL_TARGET              "spl/u-boot-spl.hex"
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE            CONFIG_SYS_INIT_RAM_SIZE
 #define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
@@ -215,6 +216,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 
 /* SPL SDMMC boot support */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot.img"
 
 #endif /* __CONFIG_H */
index eab0ef2..b72b565 100644 (file)
@@ -42,9 +42,6 @@
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "fdt_high=0xffffffff\0"         \
diff --git a/include/sh_tmu.h b/include/sh_tmu.h
deleted file mode 100644 (file)
index aa60c98..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2012  Renesas Solutions Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SH_TMU_H
-#define __SH_TMU_H
-
-#include <asm/types.h>
-
-#if defined(CONFIG_CPU_SH3)
-struct tmu_regs {
-       u8      tocr;
-       u8      reserved0;
-       u8      tstr;
-       u8      reserved1;
-       u32     tcor0;
-       u32     tcnt0;
-       u16     tcr0;
-       u16     reserved2;
-       u32     tcor1;
-       u32     tcnt1;
-       u16     tcr1;
-       u16     reserved3;
-       u32     tcor2;
-       u32     tcnt2;
-       u16     tcr2;
-       u16     reserved4;
-       u32     tcpr2;
-};
-#endif /* CONFIG_CPU_SH3 */
-
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
-struct tmu_regs {
-       u32 reserved;
-       u8  tstr;
-       u8  reserved2[3];
-       u32 tcor0;
-       u32 tcnt0;
-       u16 tcr0;
-       u16 reserved3;
-       u32 tcor1;
-       u32 tcnt1;
-       u16 tcr1;
-       u16 reserved4;
-       u32 tcor2;
-       u32 tcnt2;
-       u16 tcr2;
-       u16 reserved5;
-};
-#endif /* CONFIG_CPU_SH4 */
-
-static inline unsigned long get_tmu0_clk_rate(void)
-{
-       return CONFIG_SH_TMU_CLK_FREQ;
-}
-
-#endif /* __SH_TMU_H */
index 30c79a6..94953d8 100644 (file)
@@ -4277,7 +4277,6 @@ CONFIG_SYS_TMRINTR_PEND
 CONFIG_SYS_TMRINTR_PRI
 CONFIG_SYS_TMRPND_REG
 CONFIG_SYS_TMR_BASE
-CONFIG_SYS_TMU_CLK_DIV
 CONFIG_SYS_TSEC1
 CONFIG_SYS_TSEC1_OFFSET
 CONFIG_SYS_TSEC2