M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
+F: arch/arm/dts/rk3*
+F: arch/arm/dts/rockchip*
+F: arch/arm/dts/rv1108*
F: arch/arm/include/asm/arch-rockchip/
F: arch/arm/mach-rockchip/
F: board/rockchip/
F: tools/rkimage.c
F: tools/rksd.c
F: tools/rkspi.c
+N: rockchip
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
-RISC-V KENDRYTE
+RISC-V CANAAN KENDRYTE K210
M: Sean Anderson <seanga2@gmail.com>
S: Maintained
-F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
-F: doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
-F: drivers/clk/clk_kendryte.c
-F: drivers/pinctrl/pinctrl-kendryte.c
-F: include/kendryte/
+F: doc/device-tree-bindings/mfd/canaan,k210-sysctl.txt
+F: doc/device-tree-bindings/pinctrl/canaan,k210-fpioa.txt
+F: drivers/clk/clk_k210.c
+F: drivers/pinctrl/pinctrl-k210.c
+F: include/k210/
RNG
M: Sughosh Ganu <sughosh.ganu@linaro.org>
VERSION = 2022
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*
echo >&2 "for $(2)). Please update the board to use"; \
echo >&2 "$(firstword $(1)) before the $(3) release. Failure to"; \
echo >&2 "update by the deadline may result in board removal."; \
- echo >&2 "See doc/driver-model/migration.rst for more info."; \
+ echo >&2 "See doc/develop/driver-model/migration.rst for more info."; \
echo >&2 "===================================================="; \
fi; fi
@echo >&2 "This board does not use CONFIG_DM. CONFIG_DM will be"
@echo >&2 "compulsory starting with the v2020.01 release."
@echo >&2 "Failure to update may result in board removal."
- @echo >&2 "See doc/driver-model/migration.rst for more info."
+ @echo >&2 "See doc/develop/driver-model/migration.rst for more info."
@echo >&2 "===================================================="
endif
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(foreach d, spl tpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
-CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
+ drivers/video/u_boot_logo.S tools/version.h \
u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-gru-kevin.dtb \
rk3399-khadas-edge.dtb \
rk3399-khadas-edge-captain.dtb \
rk3399-khadas-edge-v.dtb \
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
&spi0 {
- spi-flash@0 {
+ flash@0 {
+ /*
+ * For some unknown reason U-Boot SPI driver cannot access
+ * SPI-NOR with higher frequency. Linux kernel SPI driver
+ * does not have this problem.
+ */
+ spi-max-frequency = <50000000>;
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
label = "u-boot-env";
};
};
+#endif
};
};
-#endif
/*
* U-Boot requires to have this eMMC node by default in "okay" status. U-Boot
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * 2022 by Marek Behún <kabel@kernel.org>
+ */
+
+/ {
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ old_binding_phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
+
+ð0 {
+ pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+ /delete-property/ phy-handle;
+ phy = <&old_binding_phy1>;
+};
+
+/delete-node/ &mdio;
+
+&usb3 {
+ vbus-supply = <&exp_usb3_vbus>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-gru-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
+
+&ppvar_centerlogic_pwm {
+ regulator-init-microvolt = <925000>;
+};
#include "rk3399-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = &spi_flash;
+ };
+
+ config {
+ u-boot,spl-payload-offset = <0x40000>;
+ };
+};
+
+&binman {
+ rom {
+ size = <0x800000>;
+ };
+};
+
+&cros_ec {
+ ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
+};
+
+&edp {
+ rockchip,panel = <&edp_panel>;
+};
+
+&pp1800_audio {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+};
+
+&ppvar_bigcpu_pwm {
+ regulator-init-microvolt = <900000>;
+};
+
+&ppvar_centerlogic_pwm {
+ regulator-init-microvolt = <900000>;
+};
+
+&ppvar_gpu_pwm {
+ regulator-init-microvolt = <900000>;
+};
+
+&ppvar_litcpu_pwm {
+ regulator-init-microvolt = <900000>;
+};
+
+&ppvar_sd_card_io {
+ enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+};
+
+&spi5 {
+ spi-activate-delay = <100>;
+ spi-max-frequency = <3000000>;
+ spi-deactivate-delay = <200>;
+};
+
&spi_flash {
u-boot,dm-pre-reloc;
};
stusb1600_pins_a: stusb1600-0 {
pins {
- pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
+ pinmux = <STM32_PINMUX('I', 11, GPIO)>;
bias-pull-up;
};
};
};
uart4_idle_pins_a: uart4-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
};
uart4_sleep_pins_a: uart4-sleep-0 {
- pins {
+ pins {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
- };
+ };
};
uart4_pins_b: uart4-1 {
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
- bias-disable;
+ bias-pull-up;
};
};
};
pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
+ bias-pull-up;
};
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
+ bias-pull-up;
};
};
};
pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
+ bias-pull-up;
};
};
&usbphyc {
status = "okay";
};
+
+&usbphyc_port0 {
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+};
+
+&usbphyc_port1 {
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+};
&i2c4 {
u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
eeprom0: eeprom@50 {
};
&pmic {
u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+
+ regulators {
+ u-boot,dm-spl;
+ };
};
&flash0 {
bias-pull-up;
};
};
+
+®11 {
+ u-boot,dm-spl;
+};
+
+®18 {
+ u-boot,dm-spl;
+};
+
+&usb33 {
+ u-boot,dm-spl;
+};
+
+&usbotg_hs_pins_a {
+ u-boot,dm-spl;
+};
+
+&usbotg_hs {
+ u-boot,dm-spl;
+};
+
+&usbphyc {
+ u-boot,dm-spl;
+};
+
+&usbphyc_port0 {
+ u-boot,dm-spl;
+};
+
+&usbphyc_port1 {
+ u-boot,dm-spl;
+};
+
+&vdd_usb {
+ u-boot,dm-spl;
+};
u-boot,force-b-session-valid;
hnp-srp-disable;
};
+
+&vdd_io {
+ u-boot,dm-spl;
+};
u-boot,dm-spl;
};
+&usb33 {
+ u-boot,dm-spl;
+};
+
+&usbotg_hs_pins_a {
+ u-boot,dm-spl;
+};
+
&usbotg_hs {
u-boot,dm-spl;
};
u-boot,dm-spl;
};
-&vdd_io {
- u-boot,dm-spl;
-};
-
&vdd_usb {
u-boot,dm-spl;
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
};
&vrefbuf {
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <®_dc1sw>;
status = "okay";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_hummingbird>;
phy = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_gmac_3v3>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_gmac_3v3>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_gmac_3v3>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@1 {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@1 {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@1 {
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_sw>;
phy-handle = <&rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
allwinner,rx-delay-ps = <700>;
allwinner,tx-delay-ps = <700>;
status = "okay";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_dldo4>;
phy-handle = <&rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
#include <common.h>
#include <dm.h>
#include <efi_loader.h>
+#include <lmb.h>
#include <asm/armv8/mmu.h>
#include <asm/global_data.h>
return SZ_256K;
}
+#define KERNEL_COMP_SIZE SZ_128M
+
int board_late_init(void)
{
- unsigned long base;
- unsigned long top;
+ struct lmb lmb;
u32 status = 0;
- /* Reserve 4M each for scriptaddr and pxefile_addr_r at the top of RAM
- * at least 1M below the stack.
- */
- top = gd->start_addr_sp - CONFIG_STACK_SIZE - SZ_8M - SZ_1M;
- top = ALIGN_DOWN(top, SZ_8M);
-
- status |= env_set_hex("scriptaddr", top + SZ_4M);
- status |= env_set_hex("pxefile_addr_r", top);
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
/* somewhat based on the Linux Kernel boot requirements:
* align by 2M and maximal FDT size 2M
*/
- base = ALIGN(gd->ram_base, SZ_2M);
-
- status |= env_set_hex("fdt_addr_r", base);
- status |= env_set_hex("kernel_addr_r", base + SZ_2M);
- status |= env_set_hex("ramdisk_addr_r", base + SZ_128M);
- status |= env_set_hex("loadaddr", base + SZ_2G);
- status |= env_set_hex("kernel_comp_addr_r", base + SZ_2G - SZ_128M);
- status |= env_set_hex("kernel_comp_size", SZ_128M);
+ status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M));
+ status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M));
+ status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M));
+ status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M));
+ status |= env_set_hex("kernel_comp_addr_r",
+ lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M));
+ status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
+ status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M));
+ status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M));
if (status)
log_warning("late_init: Failed to set run time variables\n");
pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP;
while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) {
- ret = mbox_recv(chan, &msg, 100000);
+ ret = mbox_recv(chan, &msg, 1000000);
if (ret < 0)
return ret;
containing U-Boot. The image is built by binman. U-Boot sits near
the start of the image.
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default SYS_TEXT_BASE
+
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"
display. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
+config TARGET_CHROMEBOOK_KEVIN
+ bool "Samsung Chromebook Plus (RK3399)"
+ select HAS_ROM
+ select ROCKCHIP_SPI_IMAGE
+ help
+ Kevin is a RK3399-based convertible chromebook. It has two USB 3.0
+ Type-C ports, 4GB of SDRAM, WiFi and a 12.3" 2400x1600 display. It
+ uses its USB ports for both power and external display. It includes
+ a Chromium OS EC (Cortex-M3) to provide access to the keyboard and
+ battery functions.
+
config TARGET_EVB_RK3399
bool "RK3399 evaluation board"
help
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
- IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB)) {
+ (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
+ IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
rk_setreg(&grf->io_vsel, 1 << 0);
/*
defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \
- defined(CONFIG_TARGET_CHROMEBOOK_BOB)
+ defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \
+ defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
return BOOT_DEVICE_SPI;
#endif
if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
#include <linux/iopoll.h>
#define BSEC_OTP_MAX_VALUE 95
+#define BSEC_OTP_UPPER_START 32
#define BSEC_TIMEOUT_US 10000
/* BSEC REGISTER OFFSET (base relative) */
/* BSEC_CONTROL Register */
#define BSEC_READ 0x000
#define BSEC_WRITE 0x100
+#define BSEC_LOCK 0x200
/* LOCK Register */
#define OTP_LOCK_MASK 0x1F
*/
#define BSEC_LOCK_PROGRAM 0x04
+/*
+ * OTP status: bit 0 permanent lock
+ */
+#define BSEC_LOCK_PERM BIT(0)
+
/**
* bsec_lock() - manage lock for each type SR/SP/SW
* @address: address of bsec IP register
/**
* bsec_shadow_register() - copy safmen otp to bsec data
+ * @dev: bsec IP device
* @base: base address of bsec IP
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
/**
* bsec_read_shadow() - read an otp data value from shadow
+ * @dev: bsec IP device
* @base: base address of bsec IP
* @val: read value
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
/**
* bsec_write_shadow() - write value in BSEC data register in shadow
+ * @dev: bsec IP device
* @base: base address of bsec IP
* @val: value to write
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
/**
* bsec_program_otp() - program a bit in SAFMEM
+ * @dev: bsec IP device
* @base: base address of bsec IP
* @val: value to program
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
return ret;
}
+/**
+ * bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM
+ * @dev: bsec IP device
+ * @base: base address of bsec IP
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: 0 if no error
+ */
+static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
+{
+ int ret;
+ bool power_up = false;
+ u32 val, addr;
+
+ /* check if safemem is power up */
+ if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
+ ret = bsec_power_safmem(base, true);
+ if (ret)
+ return ret;
+
+ power_up = true;
+ }
+
+ /*
+ * low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP
+ * and only 16 bits used in WRDATA
+ */
+ if (otp < BSEC_OTP_UPPER_START) {
+ addr = otp / 8;
+ val = 0x03 << ((otp * 2) & 0xF);
+ } else {
+ addr = BSEC_OTP_UPPER_START / 8 +
+ ((otp - BSEC_OTP_UPPER_START) / 16);
+ val = 0x01 << (otp & 0xF);
+ }
+
+ /* set value in write register*/
+ writel(val, base + BSEC_OTP_WRDATA_OFF);
+
+ /* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/
+ writel(addr | BSEC_WRITE | BSEC_LOCK, base + BSEC_OTP_CTRL_OFF);
+
+ /* check otp status*/
+ ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
+ val, (val & BSEC_MODE_BUSY_MASK) == 0,
+ BSEC_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ if (val & BSEC_MODE_PROGFAIL_MASK)
+ ret = -EACCES;
+ else
+ ret = bsec_check_error(base, otp);
+
+ if (power_up)
+ bsec_power_safmem(base, false);
+
+ return ret;
+}
+
/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_plat {
u32 base;
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
{
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
+ u32 wrlock;
/* return OTP permanent write lock status */
- *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
+ wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
+
+ *val = 0;
+ if (wrlock)
+ *val = BSEC_LOCK_PERM;
return 0;
}
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
{
- if (!IS_ENABLED(CONFIG_ARM_SMCCC) || IS_ENABLED(CONFIG_SPL_BUILD))
- return -ENOTSUPP;
+ struct stm32mp_bsec_plat *plat;
+
+ /* only permanent write lock is supported in U-Boot */
+ if (!(val & BSEC_LOCK_PERM)) {
+ dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val);
+ return 0; /* nothing to do */
+ }
- if (val == 1)
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRLOCK_OTP,
otp, 0);
- if (val == 0)
- return 0; /* nothing to do */
+
+ plat = dev_get_plat(dev);
+
+ return bsec_permanent_lock_otp(dev, plat->base, otp);
return -EINVAL;
}
*/
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
+#define STM32_SYSCFG_BASE 0x50020000
#define STM32_DBGMCU_BASE 0x50081000
#define STM32_FMC2_BASE 0x58002000
+#define STM32_DDRCTRL_BASE 0x5A003000
+#define STM32_DDRPHYC_BASE 0x5A004000
#define STM32_TZC_BASE 0x5C006000
#define STM32_ETZPC_BASE 0x5C007000
#define STM32_STGEN_BASE 0x5C008000
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
+#include <hang.h>
#include <linux/bitops.h>
-#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0
-#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1
-
-#define MPIDR_AFF0 GENMASK(7, 0)
-
-#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
-#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
-#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
-#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
-
-#define STM32MP1_PSCI_NR_CPUS 2
+/* PWR */
+#define PWR_CR3 0x0c
+#define PWR_MPUCR 0x10
+
+#define PWR_CR3_DDRSREN BIT(10)
+#define PWR_CR3_DDRRETEN BIT(12)
+
+#define PWR_MPUCR_PDDS BIT(0)
+#define PWR_MPUCR_CSTDBYDIS BIT(3)
+#define PWR_MPUCR_CSSF BIT(9)
+
+/* RCC */
+#define RCC_DDRITFCR 0xd8
+
+#define RCC_DDRITFCR_DDRC1EN BIT(0)
+#define RCC_DDRITFCR_DDRC1LPEN BIT(1)
+#define RCC_DDRITFCR_DDRC2EN BIT(2)
+#define RCC_DDRITFCR_DDRC2LPEN BIT(3)
+#define RCC_DDRITFCR_DDRPHYCEN BIT(4)
+#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5)
+#define RCC_DDRITFCR_DDRCAPBEN BIT(6)
+#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7)
+#define RCC_DDRITFCR_AXIDCGEN BIT(8)
+#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9)
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10)
+#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
+#define RCC_DDRITFCR_GSKPCTRL BIT(24)
+
+#define RCC_MP_SREQSETR 0x104
+#define RCC_MP_SREQCLRR 0x108
+
+#define RCC_MP_CIER 0x414
+#define RCC_MP_CIFR 0x418
+#define RCC_MP_CIFR_WKUPF BIT(20)
+
+/* SYSCFG */
+#define SYSCFG_CMPCR 0x20
+#define SYSCFG_CMPCR_SW_CTRL BIT(2)
+#define SYSCFG_CMPENSETR 0x24
+#define SYSCFG_CMPENCLRR 0x28
+#define SYSCFG_CMPENR_MPUEN BIT(0)
+
+/* DDR Controller registers offsets */
+#define DDRCTRL_STAT 0x004
+#define DDRCTRL_PWRCTL 0x030
+#define DDRCTRL_PWRTMG 0x034
+#define DDRCTRL_HWLPCTL 0x038
+#define DDRCTRL_DFIMISC 0x1b0
+#define DDRCTRL_SWCTL 0x320
+#define DDRCTRL_SWSTAT 0x324
+#define DDRCTRL_PSTAT 0x3fc
+#define DDRCTRL_PCTRL_0 0x490
+#define DDRCTRL_PCTRL_1 0x540
+
+/* DDR Controller Register fields */
+#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
+#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 0x1
+#define DDRCTRL_STAT_OPERATING_MODE_SR 0x3
+#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_ASR (0x3 << 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_SR (0x2 << 4)
+
+#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
+#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
+
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
+
+#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
+
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
+
+#define DDRCTRL_SWCTL_SW_DONE BIT(0)
+
+#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
+
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 BIT(0)
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 BIT(1)
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 BIT(16)
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 BIT(17)
+
+#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
+
+/* DDR PHY registers offsets */
+#define DDRPHYC_PIR 0x004
+#define DDRPHYC_PGSR 0x00c
+#define DDRPHYC_ACDLLCR 0x014
+#define DDRPHYC_ACIOCR 0x024
+#define DDRPHYC_DXCCR 0x028
+#define DDRPHYC_DSGCR 0x02c
+#define DDRPHYC_ZQ0CR0 0x180
+#define DDRPHYC_DX0DLLCR 0x1cc
+#define DDRPHYC_DX1DLLCR 0x20c
+#define DDRPHYC_DX2DLLCR 0x24c
+#define DDRPHYC_DX3DLLCR 0x28c
+
+/* DDR PHY Register fields */
+#define DDRPHYC_PIR_INIT BIT(0)
+#define DDRPHYC_PIR_DLLSRST BIT(1)
+#define DDRPHYC_PIR_DLLLOCK BIT(2)
+#define DDRPHYC_PIR_ITMSRST BIT(4)
+
+#define DDRPHYC_PGSR_IDONE BIT(0)
+
+#define DDRPHYC_ACDLLCR_DLLSRST BIT(30)
+#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
+
+#define DDRPHYC_ACIOCR_ACOE BIT(1)
+#define DDRPHYC_ACIOCR_ACPDD BIT(3)
+#define DDRPHYC_ACIOCR_ACPDR BIT(4)
+#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
+#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8)
+#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
+#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11)
+#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(20, 18)
+#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18)
+
+#define DDRPHYC_DXCCR_DXPDD BIT(2)
+#define DDRPHYC_DXCCR_DXPDR BIT(3)
+
+#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
+#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16)
+#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
+#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20)
+#define DDRPHYC_DSGCR_NL2PD BIT(24)
+#define DDRPHYC_DSGCR_CKOE BIT(28)
+
+#define DDRPHYC_ZQ0CRN_ZQPD BIT(31)
+
+#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
+
+#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xca7face0
+#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xca7face1
+
+#define MPIDR_AFF0 GENMASK(7, 0)
+
+#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
+#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
+#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
+#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
+
+#define STM32MP1_PSCI_NR_CPUS 2
#if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
#endif
case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
case ARM_PSCI_0_2_FN_SYSTEM_OFF:
case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+ case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
return 0x0;
}
return ARM_PSCI_RET_NI;
while (1)
wfi();
}
+
+static void __secure secure_udelay(unsigned int delay)
+{
+ u32 freq = cp15_read_cntfrq() / 1000000;
+ u64 start, end;
+
+ delay *= freq;
+
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
+ for (;;) {
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
+ if ((end - start) > delay)
+ break;
+ }
+}
+
+static int __secure secure_waitbits(u32 reg, u32 mask, u32 val)
+{
+ u32 freq = cp15_read_cntfrq() / 1000000;
+ u32 delay = 500 * freq; /* 500 us */
+ u64 start, end;
+ u32 tmp;
+
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
+ for (;;) {
+ tmp = readl(reg);
+ tmp &= mask;
+ if ((tmp & val) == val)
+ return 0;
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
+ if ((end - start) > delay)
+ return -ETIMEDOUT;
+ }
+}
+
+static void __secure ddr_sr_mode_ssr(u32 *saved_pwrctl)
+{
+ setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
+ RCC_DDRITFCR_DDRC1LPEN | RCC_DDRITFCR_DDRC1EN |
+ RCC_DDRITFCR_DDRC2LPEN | RCC_DDRITFCR_DDRC2EN |
+ RCC_DDRITFCR_DDRCAPBLPEN | RCC_DDRITFCR_DDRPHYCAPBLPEN |
+ RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN |
+ RCC_DDRITFCR_DDRPHYCEN);
+
+ clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
+ RCC_DDRITFCR_AXIDCGEN | RCC_DDRITFCR_DDRCKMOD_MASK);
+
+ /* Disable HW LP interface of uMCTL2 */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_HWLPCTL,
+ DDRCTRL_HWLPCTL_HW_LP_EN);
+
+ /* Configure Automatic LP modes of uMCTL2 */
+ clrsetbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRTMG,
+ DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK,
+ DDRCTRL_PWRTMG_SELFREF_TO_X32_0);
+
+ /* Save PWRCTL register to restart ASR after suspend (if applicable) */
+ *saved_pwrctl = readl(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL);
+
+ /*
+ * Disable Clock disable with LP modes
+ * (used in RUN mode for LPDDR2 with specific timing).
+ */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
+ DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
+
+ /* Disable automatic Self-Refresh mode */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
+ DDRCTRL_PWRCTL_SELFREF_EN);
+}
+
+static void __secure ddr_sr_mode_restore(u32 saved_pwrctl)
+{
+ saved_pwrctl &= DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
+ DDRCTRL_PWRCTL_SELFREF_EN;
+
+ /* Restore ASR mode in case it was enabled before suspend. */
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, saved_pwrctl);
+}
+
+static int __secure ddr_sw_self_refresh_in(void)
+{
+ int ret;
+
+ clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
+
+ /* Blocks AXI ports from taking anymore transactions */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0,
+ DDRCTRL_PCTRL_N_PORT_EN);
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1,
+ DDRCTRL_PCTRL_N_PORT_EN);
+
+ /*
+ * Waits unit all AXI ports are idle
+ * Poll PSTAT.rd_port_busy_n = 0
+ * Poll PSTAT.wr_port_busy_n = 0
+ */
+ ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_PSTAT,
+ DDRCTRL_PSTAT_RD_PORT_BUSY_0 |
+ DDRCTRL_PSTAT_RD_PORT_BUSY_1 |
+ DDRCTRL_PSTAT_WR_PORT_BUSY_0 |
+ DDRCTRL_PSTAT_WR_PORT_BUSY_1, 0);
+ if (ret)
+ goto pstat_failed;
+
+ /* SW Self-Refresh entry */
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
+
+ /*
+ * Wait operating mode change in self-refresh mode
+ * with STAT.operating_mode[1:0]==11.
+ * Ensure transition to self-refresh was due to software
+ * by checking also that STAT.selfref_type[1:0]=2.
+ */
+ ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT,
+ DDRCTRL_STAT_OPERATING_MODE_MASK |
+ DDRCTRL_STAT_SELFREF_TYPE_MASK,
+ DDRCTRL_STAT_OPERATING_MODE_SR |
+ DDRCTRL_STAT_SELFREF_TYPE_SR);
+ if (ret)
+ goto selfref_sw_failed;
+
+ /* IOs powering down (PUBL registers) */
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD);
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR);
+
+ clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
+ DDRPHYC_ACIOCR_CKPDD_MASK,
+ DDRPHYC_ACIOCR_CKPDD_0);
+
+ clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
+ DDRPHYC_ACIOCR_CKPDR_MASK,
+ DDRPHYC_ACIOCR_CKPDR_0);
+
+ clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
+ DDRPHYC_ACIOCR_CSPDD_MASK,
+ DDRPHYC_ACIOCR_CSPDD_0);
+
+ /* Disable command/address output driver */
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR);
+
+ clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR,
+ DDRPHYC_DSGCR_ODTPDD_MASK,
+ DDRPHYC_DSGCR_ODTPDD_0);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD);
+
+ clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR,
+ DDRPHYC_DSGCR_CKEPDD_MASK,
+ DDRPHYC_DSGCR_CKEPDD_0);
+
+ /* Disable PZQ cell (PUBL register) */
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD);
+
+ /* Set latch */
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE);
+
+ /* Additional delay to avoid early latch */
+ secure_udelay(10);
+
+ /* Activate sw retention in PWRCTRL */
+ setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN);
+
+ /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
+ setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
+
+ /* Disable all DLLs: GLITCH window */
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLDIS);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ /* Switch controller clocks (uMCTL2/PUBL) to DLL output clock */
+ clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
+
+ /* Deactivate all DDR clocks */
+ clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
+ RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN |
+ RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN);
+
+ return 0;
+
+selfref_sw_failed:
+ /* This bit should be cleared to restore DDR in its previous state */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
+ DDRCTRL_PWRCTL_SELFREF_SW);
+
+pstat_failed:
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0,
+ DDRCTRL_PCTRL_N_PORT_EN);
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1,
+ DDRCTRL_PCTRL_N_PORT_EN);
+
+ return -EINVAL;
+};
+
+static void __secure ddr_sw_self_refresh_exit(void)
+{
+ int ret;
+
+ /* Enable all clocks */
+ setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
+ RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN |
+ RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCAPBEN |
+ RCC_DDRITFCR_DDRCAPBEN);
+
+ /* Handshake */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
+
+ /* Mask dfi_init_complete_en */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC,
+ DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+
+ /* Ack */
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
+ ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT,
+ DDRCTRL_SWSTAT_SW_DONE_ACK,
+ DDRCTRL_SWSTAT_SW_DONE_ACK);
+ if (ret)
+ hang();
+
+ /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
+ setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
+
+ /* Enable all DLLs: GLITCH window */
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR,
+ DDRPHYC_ACDLLCR_DLLDIS);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
+
+ /* Additional delay to avoid early DLL clock switch */
+ secure_udelay(50);
+
+ /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
+ clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST);
+
+ secure_udelay(10);
+
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST);
+
+ /* PHY partial init: (DLL lock and ITM reset) */
+ writel(DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK |
+ DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_INIT,
+ STM32_DDRPHYC_BASE + DDRPHYC_PIR);
+
+ /* Need to wait at least 10 clock cycles before accessing PGSR */
+ secure_udelay(1);
+
+ /* Pool end of init */
+ ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR,
+ DDRPHYC_PGSR_IDONE, DDRPHYC_PGSR_IDONE);
+ if (ret)
+ hang();
+
+ /* Handshake */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
+
+ /* Unmask dfi_init_complete_en to uMCTL2 */
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+
+ /* Ack */
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
+ ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT,
+ DDRCTRL_SWSTAT_SW_DONE_ACK,
+ DDRCTRL_SWSTAT_SW_DONE_ACK);
+ if (ret)
+ hang();
+
+ /* Deactivate sw retention in PWR */
+ clrbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN);
+
+ /* Enable PZQ cell (PUBL register) */
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD);
+
+ /* Enable pad drivers */
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD);
+
+ /* Enable command/address output driver */
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CKPDD_MASK);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CSPDD_MASK);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR);
+
+ /* Release latch */
+ setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_ODTPDD_MASK);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD);
+
+ clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKEPDD_MASK);
+
+ /* Remove selfrefresh */
+ clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
+
+ /* Wait operating_mode == normal */
+ ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT,
+ DDRCTRL_STAT_OPERATING_MODE_MASK,
+ DDRCTRL_STAT_OPERATING_MODE_NORMAL);
+ if (ret)
+ hang();
+
+ /* AXI ports are no longer blocked from taking transactions */
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, DDRCTRL_PCTRL_N_PORT_EN);
+ setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, DDRCTRL_PCTRL_N_PORT_EN);
+
+ setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
+}
+
+void __secure psci_system_suspend(u32 __always_unused function_id,
+ u32 ep, u32 context_id)
+{
+ u32 saved_pwrctl, reg;
+
+ /* Disable IO compensation */
+
+ /* Place current APSRC/ANSRC into RAPSRC/RANSRC */
+ reg = readl(STM32_SYSCFG_BASE + SYSCFG_CMPCR);
+ reg >>= 8;
+ reg &= 0xff << 16;
+ reg |= SYSCFG_CMPCR_SW_CTRL;
+ writel(reg, STM32_SYSCFG_BASE + SYSCFG_CMPCR);
+ writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENCLRR);
+
+ writel(RCC_MP_CIFR_WKUPF, STM32_RCC_BASE + RCC_MP_CIFR);
+ setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
+
+ setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
+ PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
+
+ psci_v7_flush_dcache_all();
+ ddr_sr_mode_ssr(&saved_pwrctl);
+ ddr_sw_self_refresh_in();
+ setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN);
+ writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR);
+
+ /* Zzz, enter stop mode */
+ asm volatile(
+ "isb\n"
+ "dsb\n"
+ "wfi\n");
+
+ writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR);
+ ddr_sw_self_refresh_exit();
+ ddr_sr_mode_restore(saved_pwrctl);
+
+ writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
+ clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+}
clock_init();
timer_init();
gpio_init();
- eth_init_board();
spl_init();
preloader_console_init();
/ {
model = "Sipeed Maix Bit 2.0";
- compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210";
+ compatible = "sipeed,maix-bitm", "sipeed,maix-bit",
+ "canaan,kendryte-k210";
chosen {
stdout-path = "serial0:115200";
*/
#address-cells = <1>;
#size-cells = <1>;
- compatible = "kendryte,k210";
+ compatible = "canaan,kendryte-k210";
aliases {
cpu0 = &cpu0;
timebase-frequency = <7800000>;
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+ compatible = "canaan,k210", "sifive,rocket0", "riscv";
reg = <0>;
riscv,isa = "rv64imafdgc";
mmu-type = "sv39";
};
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+ compatible = "canaan,k210", "sifive,rocket0", "riscv";
reg = <1>;
riscv,isa = "rv64imafdgc";
mmu-type = "sv39";
sram: memory@80000000 {
device_type = "memory";
- compatible = "kendryte,k210-sram";
+ compatible = "canaan,k210-sram";
reg = <0x80000000 0x400000>,
<0x80400000 0x200000>,
<0x80600000 0x200000>;
soc {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "kendryte,k210-soc", "simple-bus";
+ compatible = "canaan,k210-soc", "simple-bus";
ranges;
interrupt-parent = <&plic0>;
debug0: debug@0 {
- compatible = "kendryte,k210-debug", "riscv,debug";
+ compatible = "canaan,k210-debug", "riscv,debug";
reg = <0x0 0x1000>;
};
clint0: clint@2000000 {
#interrupt-cells = <1>;
- compatible = "kendryte,k210-clint", "riscv,clint0";
+ compatible = "canaan,k210-clint", "sifive,clint0", "riscv,clint0";
reg = <0x2000000 0xC000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>;
plic0: interrupt-controller@C000000 {
#interrupt-cells = <1>;
- compatible = "kendryte,k210-plic", "riscv,plic0";
+ compatible = "canaan,k210-plic", "sifive,plic-1.0.0", "riscv,plic0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
- <&cpu1_intc 9>, <&cpu1_intc 11>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
riscv,ndev = <65>;
riscv,max-priority = <7>;
};
uarths0: serial@38000000 {
- compatible = "kendryte,k210-uarths", "sifive,uart0";
+ compatible = "canaan,k210-uarths", "sifive,uart0";
reg = <0x38000000 0x1000>;
interrupts = <33>;
clocks = <&sysclk K210_CLK_CPU>;
gpio0: gpio-controller@38001000 {
#interrupt-cells = <2>;
#gpio-cells = <2>;
- compatible = "kendryte,k210-gpiohs", "sifive,gpio0";
+ compatible = "canaan,k210-gpiohs", "sifive,gpio0";
reg = <0x38001000 0x1000>;
interrupt-controller;
interrupts = <34 35 36 37 38 39 40 41
};
kpu0: kpu@40800000 {
- compatible = "kendryte,k210-kpu";
+ compatible = "canaan,k210-kpu";
reg = <0x40800000 0xc00000>;
interrupts = <25>;
clocks = <&sysclk K210_CLK_AI>;
};
fft0: fft@42000000 {
- compatible = "kendryte,k210-fft";
+ compatible = "canaan,k210-fft";
reg = <0x42000000 0x400000>;
interrupts = <26>;
clocks = <&sysclk K210_CLK_FFT>;
};
dmac0: dma-controller@50000000 {
- compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a";
+ compatible = "canaan,k210-dmac", "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
interrupts = <27 28 29 30 31 32>;
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
apb0: bus@50200000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "kendryte,k210-apb", "simple-pm-bus";
+ compatible = "canaan,k210-apb", "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB0>;
gpio1: gpio-controller@50200000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "kendryte,k210-gpio",
+ compatible = "canaan,k210-gpio",
"snps,dw-apb-gpio";
reg = <0x50200000 0x80>;
- clocks = <&sysclk K210_CLK_GPIO>;
+ clocks = <&sysclk K210_CLK_APB0>,
+ <&sysclk K210_CLK_GPIO>;
+ clock-names = "bus", "db";
resets = <&sysrst K210_RST_GPIO>;
status = "disabled";
};
uart1: serial@50210000 {
- compatible = "kendryte,k210-uart",
+ compatible = "canaan,k210-uart",
"snps,dw-apb-uart";
reg = <0x50210000 0x100>;
interrupts = <11>;
- clocks = <&sysclk K210_CLK_UART1>;
+ clocks = <&sysclk K210_CLK_UART1>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "baudclk", "apb_pclk";
resets = <&sysrst K210_RST_UART1>;
reg-io-width = <4>;
reg-shift = <2>;
};
uart2: serial@50220000 {
- compatible = "kendryte,k210-uart",
+ compatible = "canaan,k210-uart",
"snps,dw-apb-uart";
reg = <0x50220000 0x100>;
interrupts = <12>;
- clocks = <&sysclk K210_CLK_UART2>;
+ clocks = <&sysclk K210_CLK_UART2>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "baudclk", "apb_pclk";
resets = <&sysrst K210_RST_UART2>;
reg-io-width = <4>;
reg-shift = <2>;
};
uart3: serial@50230000 {
- compatible = "kendryte,k210-uart",
+ compatible = "canaan,k210-uart",
"snps,dw-apb-uart";
reg = <0x50230000 0x100>;
interrupts = <13>;
- clocks = <&sysclk K210_CLK_UART3>;
+ clocks = <&sysclk K210_CLK_UART3>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "baudclk", "apb_pclk";
resets = <&sysrst K210_RST_UART3>;
reg-io-width = <4>;
reg-shift = <2>;
};
spi2: spi@50240000 {
- compatible = "canaan,kendryte-k210-spi",
+ compatible = "canaan,k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
spi-slave;
reg = <0x50240000 0x100>;
interrupts = <2>;
- clocks = <&sysclk K210_CLK_SPI2>;
+ clocks = <&sysclk K210_CLK_SPI2>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI2>;
spi-max-frequency = <25000000>;
status = "disabled";
};
i2s0: i2s@50250000 {
- compatible = "kendryte,k210-i2s",
+ compatible = "canaan,k210-i2s",
"snps,designware-i2s";
reg = <0x50250000 0x200>;
interrupts = <5>;
};
apu0: sound@520250200 {
- compatible = "kendryte,k210-apu";
+ compatible = "canaan,k210-apu";
reg = <0x50250200 0x200>;
status = "disabled";
};
i2s1: i2s@50260000 {
- compatible = "kendryte,k210-i2s",
+ compatible = "canaan,k210-i2s",
"snps,designware-i2s";
reg = <0x50260000 0x200>;
interrupts = <6>;
};
i2s2: i2s@50270000 {
- compatible = "kendryte,k210-i2s",
+ compatible = "canaan,k210-i2s",
"snps,designware-i2s";
reg = <0x50270000 0x200>;
interrupts = <7>;
};
i2c0: i2c@50280000 {
- compatible = "kendryte,k210-i2c",
+ compatible = "canaan,k210-i2c",
"snps,designware-i2c";
reg = <0x50280000 0x100>;
interrupts = <8>;
- clocks = <&sysclk K210_CLK_I2C0>;
+ clocks = <&sysclk K210_CLK_I2C0>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_I2C0>;
status = "disabled";
};
i2c1: i2c@50290000 {
- compatible = "kendryte,k210-i2c",
+ compatible = "canaan,k210-i2c",
"snps,designware-i2c";
reg = <0x50290000 0x100>;
interrupts = <9>;
- clocks = <&sysclk K210_CLK_I2C1>;
+ clocks = <&sysclk K210_CLK_I2C1>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_I2C1>;
status = "disabled";
};
i2c2: i2c@502A0000 {
- compatible = "kendryte,k210-i2c",
+ compatible = "canaan,k210-i2c",
"snps,designware-i2c";
reg = <0x502A0000 0x100>;
interrupts = <10>;
- clocks = <&sysclk K210_CLK_I2C2>;
+ clocks = <&sysclk K210_CLK_I2C2>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_I2C2>;
status = "disabled";
};
fpioa: pinmux@502B0000 {
- compatible = "kendryte,k210-fpioa";
+ compatible = "canaan,k210-fpioa";
reg = <0x502B0000 0x100>;
- clocks = <&sysclk K210_CLK_FPIOA>;
+ clocks = <&sysclk K210_CLK_FPIOA>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_FPIOA>;
- kendryte,sysctl = <&sysctl>;
- kendryte,power-offset = <K210_SYSCTL_POWER_SEL>;
+ canaan,k210-sysctl-power = <&sysctl K210_SYSCTL_POWER_SEL>;
pinctrl-0 = <&fpioa_jtag>;
pinctrl-names = "default";
status = "disabled";
};
sha256: sha256@502C0000 {
- compatible = "kendryte,k210-sha256";
+ compatible = "canaan,k210-sha256";
reg = <0x502C0000 0x100>;
clocks = <&sysclk K210_CLK_SHA>;
resets = <&sysrst K210_RST_SHA>;
};
timer0: timer@502D0000 {
- compatible = "kendryte,k210-timer",
+ compatible = "canaan,k210-timer",
"snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
interrupts = <14 15>;
- clocks = <&sysclk K210_CLK_TIMER0>;
- clock-names = "timer";
+ clocks = <&sysclk K210_CLK_TIMER0>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "timer", "pclk";
resets = <&sysrst K210_RST_TIMER0>;
status = "disabled";
};
timer1: timer@502E0000 {
- compatible = "kendryte,k210-timer",
+ compatible = "canaan,k210-timer",
"snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
interrupts = <16 17>;
- clocks = <&sysclk K210_CLK_TIMER1>;
- clock-names = "timer";
+ clocks = <&sysclk K210_CLK_TIMER1>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "timer", "pclk";
resets = <&sysrst K210_RST_TIMER1>;
status = "disabled";
};
timer2: timer@502F0000 {
- compatible = "kendryte,k210-timer",
+ compatible = "canaan,k210-timer",
"snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
interrupts = <18 19>;
- clocks = <&sysclk K210_CLK_TIMER2>;
- clock-names = "timer";
+ clocks = <&sysclk K210_CLK_TIMER2>,
+ <&sysclk K210_CLK_APB0>;
+ clock-names = "timer", "pclk";
resets = <&sysrst K210_RST_TIMER2>;
status = "disabled";
};
apb1: bus@50400000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "kendryte,k210-apb", "simple-pm-bus";
+ compatible = "canaan,k210-apb", "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB1>;
wdt0: watchdog@50400000 {
- compatible = "kendryte,k210-wdt", "snps,dw-wdt";
+ compatible = "canaan,k210-wdt", "snps,dw-wdt";
reg = <0x50400000 0x100>;
interrupts = <21>;
- clocks = <&sysclk K210_CLK_WDT0>;
+ clocks = <&sysclk K210_CLK_WDT0>,
+ <&sysclk K210_CLK_APB1>;
+ clock-names = "tclk", "pclk";
resets = <&sysrst K210_RST_WDT0>;
};
wdt1: watchdog@50410000 {
- compatible = "kendryte,k210-wdt", "snps,dw-wdt";
+ compatible = "canaan,k210-wdt", "snps,dw-wdt";
reg = <0x50410000 0x100>;
interrupts = <22>;
- clocks = <&sysclk K210_CLK_WDT1>;
+ clocks = <&sysclk K210_CLK_WDT1>,
+ <&sysclk K210_CLK_APB1>;
+ clock-names = "tclk", "pclk";
resets = <&sysrst K210_RST_WDT1>;
status = "disabled";
};
otp0: nvmem@50420000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "kendryte,k210-otp";
+ compatible = "canaan,k210-otp";
reg = <0x50420000 0x100>,
<0x88000000 0x20000>;
reg-names = "reg", "mem";
};
dvp0: camera@50430000 {
- compatible = "kendryte,k210-dvp";
+ compatible = "canaan,k210-dvp";
reg = <0x50430000 0x100>;
interrupts = <24>;
clocks = <&sysclk K210_CLK_DVP>;
resets = <&sysrst K210_RST_DVP>;
- kendryte,sysctl = <&sysctl>;
- kendryte,misc-offset = <K210_SYSCTL_MISC>;
+ canaan,k210-sysctl = <&sysctl>;
+ canaan,k210-misc-offset = <K210_SYSCTL_MISC>;
status = "disabled";
};
sysctl: syscon@50440000 {
- compatible = "kendryte,k210-sysctl",
+ compatible = "canaan,k210-sysctl",
"syscon", "simple-mfd";
reg = <0x50440000 0x100>;
+ clocks = <&sysclk K210_CLK_APB1>;
+ clock-names = "pclk";
reg-io-width = <4>;
u-boot,dm-pre-reloc;
sysclk: clock-controller {
#clock-cells = <1>;
- compatible = "kendryte,k210-clk";
+ compatible = "canaan,k210-clk";
clocks = <&in0>;
assigned-clocks = <&sysclk K210_CLK_PLL1>;
assigned-clock-rates = <390000000>;
};
sysrst: reset-controller {
- compatible = "kendryte,k210-rst",
+ compatible = "canaan,k210-rst",
"syscon-reset";
#reset-cells = <1>;
regmap = <&sysctl>;
};
aes0: aes@50450000 {
- compatible = "kendryte,k210-aes";
+ compatible = "canaan,k210-aes";
reg = <0x50450000 0x100>;
clocks = <&sysclk K210_CLK_AES>;
resets = <&sysrst K210_RST_AES>;
};
rtc: rtc@50460000 {
- compatible = "kendryte,k210-rtc";
+ compatible = "canaan,k210-rtc";
reg = <0x50460000 0x100>;
clocks = <&in0>;
resets = <&sysrst K210_RST_RTC>;
apb2: bus@52000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "kendryte,k210-apb", "simple-pm-bus";
+ compatible = "canaan,k210-apb", "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB2>;
spi0: spi@52000000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "canaan,kendryte-k210-spi",
+ compatible = "canaan,k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x52000000 0x100>;
interrupts = <1>;
- clocks = <&sysclk K210_CLK_SPI0>;
- clock-names = "ssi_clk";
+ clocks = <&sysclk K210_CLK_SPI0>,
+ <&sysclk K210_CLK_APB2>;
+ clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI0>;
spi-max-frequency = <25000000>;
num-cs = <4>;
spi1: spi@53000000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "canaan,kendryte-k210-spi",
+ compatible = "canaan,k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x53000000 0x100>;
interrupts = <2>;
- clocks = <&sysclk K210_CLK_SPI1>;
- clock-names = "ssi_clk";
+ clocks = <&sysclk K210_CLK_SPI1>,
+ <&sysclk K210_CLK_APB2>;
+ clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI1>;
spi-max-frequency = <25000000>;
num-cs = <4>;
spi3: spi@54000000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "canaan,kendryte-k210-ssi",
+ compatible = "canaan,k210-ssi",
"snps,dwc-ssi-1.01a";
reg = <0x54000000 0x200>;
interrupts = <4>;
- clocks = <&sysclk K210_CLK_SPI3>;
- clock-names = "ssi_clk";
+ clocks = <&sysclk K210_CLK_SPI3>,
+ <&sysclk K210_CLK_APB2>;
+ clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI3>;
/* Could possibly go up to 200 MHz */
spi-max-frequency = <100000000>;
def_bool y
endif
+
+if TARGET_CHROMEBOOK_KEVIN
+
+config SYS_BOARD
+ default "gru"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_CONFIG_NAME
+ default "gru"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
F: board/google/gru/
F: include/configs/gru.h
F: configs/chromebook_bob_defconfig
+
+CHROMEBOOK KEVIN BOARD
+M: Simon Glass <sjg@chromium.org>
+M: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+S: Maintained
+F: board/google/gru/
+F: include/configs/gru.h
+F: configs/chromebook_kevin_defconfig
#include <common.h>
#include <dm.h>
#include <init.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+
+#define GRF_IO_VSEL_BT656_SHIFT 0
+#define GRF_IO_VSEL_AUDIO_SHIFT 1
+#define PMUGRF_CON0_VSEL_SHIFT 8
+#define PMUGRF_CON0_VOL_SHIFT 9
#ifdef CONFIG_SPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
int board_early_init_f(void)
{
-# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
int sum, i;
/*
return 0;
}
#endif
+
+static void setup_iodomain(void)
+{
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ struct rk3399_pmugrf_regs *pmugrf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+ /* BT656 and audio is in 1.8v domain */
+ rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
+ 1 << GRF_IO_VSEL_AUDIO_SHIFT));
+
+ /*
+ * Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
+ * and explicitly configure that PMU1830_VOL to be 1.8V
+ */
+ rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
+ 1 << PMUGRF_CON0_VOL_SHIFT));
+}
+
+int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ setup_iodomain();
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ ret = rockchip_setup_macaddr();
+
+ return ret;
+}
#include <malloc.h>
#include <twl4030.h>
#include <i2c.h>
-#include <video_fb.h>
+#include <video.h>
#include <keyboard.h>
#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-GraphicDevice gdev;
-
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"Nokia RX-51",
*in_params = params;
}
-/*
- * Routine: video_hw_init
- * Description: Set up the GraphicDevice depending on sys_boot.
- */
-void *video_hw_init(void)
+static int rx51_video_probe(struct udevice *dev)
{
- /* fill in Graphic Device */
- gdev.frameAdrs = 0x8f9c0000;
- gdev.winSizeX = 800;
- gdev.winSizeY = 480;
- gdev.gdfBytesPP = 2;
- gdev.gdfIndex = GDF_16BIT_565RGB;
- memset((void *)gdev.frameAdrs, 0, 0xbb800);
- return (void *) &gdev;
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_plat->base = 0x8f9c0000;
+ uc_plat->size = 800 * 480 * sizeof(u16);
+ uc_priv->xsize = 800;
+ uc_priv->ysize = 480;
+ uc_priv->bpix = VIDEO_BPP16;
+
+ video_set_flush_dcache(dev, true);
+
+ return 0;
}
+U_BOOT_DRIVER(rx51_video) = {
+ .name = "rx51_video",
+ .id = UCLASS_VIDEO,
+ .probe = rx51_video_probe,
+};
+
/*
* Routine: twl4030_regulator_set_mode
* Description: Set twl4030 regulator mode over i2c powerbus.
{ "rx51_watchdog" },
};
+U_BOOT_DRVINFOS(rx51_video) = {
+ { "rx51_video" },
+};
+
U_BOOT_DRVINFOS(rx51_kp) = {
{ "rx51_kp" },
};
struct clk clk;
/* Enable RAM clocks */
- memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram");
+ memory = ofnode_by_compatible(ofnode_null(), "canaan,k210-sram");
if (ofnode_equal(memory, ofnode_null()))
return -ENOENT;
ret = misc_read(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
&otp, sizeof(otp));
- if (ret < 0) {
+ if (ret != sizeof(otp)) {
puts("OTP read error");
return CMD_RET_FAILURE;
}
ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD),
&lock, sizeof(lock));
- if (ret < 0) {
+ if (ret != sizeof(lock)) {
puts("LOCK read error");
return CMD_RET_FAILURE;
}
ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
&otp, sizeof(otp));
- if (ret < 0) {
+ if (ret != sizeof(otp)) {
puts("BOARD programming error\n");
return CMD_RET_FAILURE;
}
otp = 1;
ret = misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD),
&otp, sizeof(otp));
- if (ret < 0) {
+ if (ret != sizeof(otp)) {
puts("BOARD lock error\n");
return CMD_RET_FAILURE;
}
#include <asm/arch/prcm.h>
#include <asm/arch/pmic_bus.h>
#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <u-boot/crc.h>
#endif
#endif /* CONFIG_DM_MMC */
+ eth_init_board();
+
return 0;
}
struct abuf in, out;
abuf_init_set(&in, image_buf, image_len);
- abuf_init_set(&in, load_buf, unc_len);
+ abuf_init_set(&out, load_buf, unc_len);
ret = zstd_decompress(&in, &out);
if (ret >= 0) {
image_len = ret;
*/
#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
if (fdt) {
- log_err("ERROR: can't have ACPI table and device tree.\n");
- return EFI_LOAD_ERROR;
+ log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
+ return EFI_SUCCESS;
}
#else
bootm_headers_t img = { 0 };
int rcode = 0;
uchar addr[3];
-#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+#if !CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS)
eeprom_init(CONFIG_SYS_I2C_EEPROM_BUS);
#endif
}
/**
- * create_initrd_dp() - Create a special device for our Boot### option
- *
- * @dev: Device
- * @part: Disk partition
- * @file: Filename
- * Return: Pointer to the device path or ERR_PTR
+ * create_initrd_dp() - create a special device for our Boot### option
*
+ * @dev: device
+ * @part: disk partition
+ * @file: filename
+ * @shortform: create short form device path
+ * Return: pointer to the device path or ERR_PTR
*/
static
struct efi_device_path *create_initrd_dp(const char *dev, const char *part,
- const char *file)
+ const char *file, int shortform)
{
- struct efi_device_path *tmp_dp = NULL, *tmp_fp = NULL;
+ struct efi_device_path *tmp_dp = NULL, *tmp_fp = NULL, *short_fp = NULL;
struct efi_device_path *initrd_dp = NULL;
efi_status_t ret;
const struct efi_initrd_dp id_dp = {
printf("Cannot create device path for \"%s %s\"\n", part, file);
goto out;
}
+ if (shortform)
+ short_fp = efi_dp_shorten(tmp_fp);
+ if (!short_fp)
+ short_fp = tmp_fp;
initrd_dp = efi_dp_append((const struct efi_device_path *)&id_dp,
- tmp_fp);
+ short_fp);
out:
efi_free_pool(tmp_dp);
efi_guid_t guid;
size_t label_len, label_len16;
u16 *label;
- struct efi_device_path *device_path = NULL, *file_path = NULL;
+ struct efi_device_path *file_path = NULL;
+ struct efi_device_path *fp_free = NULL;
struct efi_device_path *final_fp = NULL;
struct efi_device_path *initrd_dp = NULL;
struct efi_load_option lo;
argc--;
argv++; /* 'add' */
for (; argc > 0; argc--, argv++) {
- if (!strcmp(argv[0], "-b")) {
+ int shortform;
+
+ if (*argv[0] != '-' || strlen(argv[0]) != 2) {
+ r = CMD_RET_USAGE;
+ goto out;
+ }
+ shortform = 0;
+ switch (argv[0][1]) {
+ case 'b':
+ shortform = 1;
+ /* fallthrough */
+ case 'B':
if (argc < 5 || lo.label) {
r = CMD_RET_USAGE;
goto out;
/* file path */
ret = efi_dp_from_name(argv[3], argv[4], argv[5],
- &device_path, &file_path);
+ NULL, &fp_free);
if (ret != EFI_SUCCESS) {
printf("Cannot create device path for \"%s %s\"\n",
argv[3], argv[4]);
r = CMD_RET_FAILURE;
goto out;
}
+ if (shortform)
+ file_path = efi_dp_shorten(fp_free);
+ if (!file_path)
+ file_path = fp_free;
fp_size += efi_dp_size(file_path) +
sizeof(struct efi_device_path);
argc -= 5;
argv += 5;
- } else if (!strcmp(argv[0], "-i")) {
+ break;
+ case 'i':
+ shortform = 1;
+ /* fallthrough */
+ case 'I':
if (argc < 3 || initrd_dp) {
r = CMD_RET_USAGE;
goto out;
}
- initrd_dp = create_initrd_dp(argv[1], argv[2], argv[3]);
+ initrd_dp = create_initrd_dp(argv[1], argv[2], argv[3],
+ shortform);
if (!initrd_dp) {
printf("Cannot add an initrd\n");
r = CMD_RET_FAILURE;
argv += 3;
fp_size += efi_dp_size(initrd_dp) +
sizeof(struct efi_device_path);
- } else if (!strcmp(argv[0], "-s")) {
+ break;
+ case 's':
if (argc < 1 || lo.optional_data) {
r = CMD_RET_USAGE;
goto out;
lo.optional_data = (const u8 *)argv[1];
argc -= 1;
argv += 1;
- } else {
+ break;
+ default:
r = CMD_RET_USAGE;
goto out;
}
free(data);
efi_free_pool(final_fp);
efi_free_pool(initrd_dp);
- efi_free_pool(device_path);
- efi_free_pool(file_path);
+ efi_free_pool(fp_free);
free(lo.label);
return r;
static char efidebug_help_text[] =
" - UEFI Shell-like interface to configure UEFI environment\n"
"\n"
- "efidebug boot add "
- "-b <bootid> <label> <interface> <devnum>[:<part>] <file path> "
- "-i <interface> <devnum>[:<part>] <initrd file path> "
- "-s '<optional data>'\n"
- " - set UEFI BootXXXX variable\n"
- " <load options> will be passed to UEFI application\n"
+ "efidebug boot add - set UEFI BootXXXX variable\n"
+ " -b|-B <bootid> <label> <interface> <devnum>[:<part>] <file path>\n"
+ " -i|-I <interface> <devnum>[:<part>] <initrd file path>\n"
+ " (-b, -i for short form device path)\n"
+ " -s '<optional data>'\n"
"efidebug boot rm <bootid#1> [<bootid#2> [<bootid#3> [...]]]\n"
" - delete UEFI BootXXXX variables\n"
"efidebug boot dump\n"
printf("Device: %s\n", mmc->cfg->name);
printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24);
- printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff);
- printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff,
- (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
- (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
+ if (IS_SD(mmc)) {
+ printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff);
+ printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff,
+ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
+ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
+ } else {
+ printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xff);
+ printf("Name: %c%c%c%c%c%c \n", mmc->cid[0] & 0xff,
+ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
+ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
+ (mmc->cid[2] >> 24));
+ }
printf("Bus Speed: %d\n", mmc->clock);
#if CONFIG_IS_ENABLED(MMC_VERBOSE)
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_MISC_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
-CONFIG_DM_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_CROS_EC=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1280
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=800
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
+CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_BOOT_MODE_REG=0
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+# CONFIG_SPL_MMC is not set
+CONFIG_TARGET_CHROMEBOOK_KEVIN=y
+CONFIG_DEBUG_UART_BASE=0xff1a0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_MISC_INIT_R=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_ADDR=0x100000
+CONFIG_BLOBLIST_SIZE=0x1000
+CONFIG_HANDOFF=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_LOG=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_MMC_PWRSEQ=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_CROS_EC=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_XRES=2400
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1600
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
CONFIG_BOOTCOMMAND="run sdboot;run emmcboot;run attachboot;echo"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run preboot"
-CONFIG_CONSOLE_MUX=y
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "
CONFIG_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
-CONFIG_CFB_CONSOLE=y
-CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=31000
CONFIG_WDT=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_SYS_I2C_RCAR_I2C=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_SYS_I2C_RCAR_I2C=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_CLK_RENESAS=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=1
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=1536
CONFIG_DFU_MMC=y
CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
-CONFIG_DFU_VIRT=y
-CONFIG_SET_DFU_ALT_INFO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_DWC_ETH_QOS=y
CONFIG_KS8851_MLL=y
CONFIG_PHY=y
+CONFIG_SPL_PHY=y
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_PINCONF=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_PINCTRL_STMFX=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_STPMIC1=y
CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_SPL_DM_REGULATOR_STPMIC1=y
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SYSRESET_SYSCON=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC2=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
Boot Count Limit
================
+This is enabled by CONFIG_BOOTCOUNT_LIMIT.
+
This allows to detect multiple failed attempts to boot Linux.
-After a power-on reset, "bootcount" variable will be initialized with 1, and
+After a power-on reset, the "bootcount" variable will be initialized to 1, and
each reboot will increment the value by 1.
If, after a reboot, the new value of "bootcount" exceeds the value of
"bootlimit", then instead of the standard boot action (executing the contents of
-"bootcmd") an alternate boot action will be performed, and the contents of
+"bootcmd"), an alternate boot action will be performed, and the contents of
"altbootcmd" will be executed.
If the variable "bootlimit" is not defined in the environment, the Boot Count
then U-Boot will drop into interactive mode and remain there.
It is the responsibility of some application code (typically a Linux
-application) to reset the variable "bootcount", thus allowing for more boot
-cycles.
+application) to reset the variable "bootcount" to 0 when the system booted
+successfully, thus allowing for more boot cycles.
-BOOTCOUNT_EXT
--------------
+CONFIG_BOOTCOUNT_EXT
+--------------------
This adds support for maintaining boot count in a file on an EXT filesystem.
-The file to use is define by:
+The file to use is defined by:
-SYS_BOOTCOUNT_EXT_INTERFACE
-SYS_BOOTCOUNT_EXT_DEVPART
-SYS_BOOTCOUNT_EXT_NAME
+CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE
+CONFIG_SYS_BOOTCOUNT_EXT_DEVPART
+CONFIG_SYS_BOOTCOUNT_EXT_NAME
The format of the file is:
u8 upgrade_available
==== =================
-To prevent unattended usage of "altbootcmd" the "upgrade_available" variable is
+To prevent unattended usage of "altbootcmd", the "upgrade_available" variable is
used.
-If "upgrade_available" is 0, "bootcount" is not saved, if "upgrade_available" is
-1 "bootcount" is save.
-So the Userspace Application must set the "upgrade_available" and "bootcount"
-variables to 0, if a boot was successfully.
-This also prevents writes on all reboots.
+If "upgrade_available" is 0, "bootcount" is not saved.
+If "upgrade_available" is 1, "bootcount" is saved.
+So a userspace application should take care of setting the "upgrade_available"
+and "bootcount" variables to 0, if the system boots successfully.
+This also avoids writing the "bootcount" information on all reboots.
========================
you can browse it online at:
-http://git.freescale.com/git/cgit.cgi/ppc/sdk/boot-format.git/
+https://source.codeaurora.org/external/qoriq/qoriq-yocto-sdk/boot-format
Building
========
NB: Beelink use a common board config for GT-King, GT-King Pro and the
GS-King-X model, hence the "beelink-s922x" name.
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+
.. code-block:: bash
$ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
NB: Beelink use a common board config for GT-King, GT-King Pro and the
GS-King-X model, hence the "beelink-s922x" name.
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+
.. code-block:: bash
$ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+Boot Documentation
+------------------
+
+.. toctree::
+ :maxdepth: 1
+
+ pre-generated-fip
+
Board Documentation
-------------------
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j100`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain binaries
from the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j80`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain binaries
from the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim2`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3l`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lafrite`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
for convenience at <https://github.com/BayLibre/u-boot/releases/>. These
apply to both v1 and v2.
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lepotato`
+
Download and extract the libretech-cc release from there, and set FIPDIR to
point to the `fip` subdirectory.
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `nanopi-k2`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c2`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c4` or `odroid-hc4`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2` or `odroid-n2-plus`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p200`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
$ mkdir fip
- $ cp $FIPDIR/gxl/bl2.bin fip/
- $ cp $FIPDIR/gxl/acs.bin fip/
- $ cp $FIPDIR/gxl/bl21.bin fip/
- $ cp $FIPDIR/gxl/bl30.bin fip/
- $ cp $FIPDIR/gxl/bl301.bin fip/
- $ cp $FIPDIR/gxl/bl31.img fip/
+ $ cp $FIPDIR/gxb/bl2.bin fip/
+ $ cp $FIPDIR/gxb/acs.bin fip/
+ $ cp $FIPDIR/gxb/bl21.bin fip/
+ $ cp $FIPDIR/gxb/bl30.bin fip/
+ $ cp $FIPDIR/gxb/bl301.bin fip/
+ $ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
- $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+ $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
-
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+
+ $ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
+
+ $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
and then write the image to SD with:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p201`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
$ mkdir fip
- $ cp $FIPDIR/gxl/bl2.bin fip/
- $ cp $FIPDIR/gxl/acs.bin fip/
- $ cp $FIPDIR/gxl/bl21.bin fip/
- $ cp $FIPDIR/gxl/bl30.bin fip/
- $ cp $FIPDIR/gxl/bl301.bin fip/
- $ cp $FIPDIR/gxl/bl31.img fip/
+ $ cp $FIPDIR/gxb/bl2.bin fip/
+ $ cp $FIPDIR/gxb/acs.bin fip/
+ $ cp $FIPDIR/gxb/bl21.bin fip/
+ $ cp $FIPDIR/gxb/bl30.bin fip/
+ $ cp $FIPDIR/gxb/bl301.bin fip/
+ $ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
- $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+ $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
-
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+
+ $ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
+
+ $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
and then write the image to SD with:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p212`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Pre-Generated FIP file set
+==========================
+
+The Amlogic ARMv8 based SoCs uses a vendor variant of the Trusted Firmware-A
+boot architecture.
+
+You can find documentation on the Trusted Firmware-A architecture on: https://www.trustedfirmware.org/projects/tf-a/
+
+The Trusted Firmware-A uses the following boot elements (simplified):
+
+- BL1: First boot step, implemented in ROM on Amlogic SoCs
+- BL2: Second boot step, used to initialize the SoC main clocks & DDR interface. The BL21 and ACS board-specific binaries are "inserted" in the BL32 binary before signing/packaging in order to be flashed on the platform.
+- BL30: Amlogic Secure Co-Processor (SCP) firmware used to handle all the system management operations (DVFS, suspend/resume, ...)
+- BL301: Amlogic Secure Co-Processor (SCP) board-specific firmware "plug-in" to handle custom DVFS & suspend-resume parameters
+- BL31: Initializes the interrupt controller and the system management interface (PSCI)
+- BL32 (Optional): Is the Trusted Environment Execution (TEE) Operating System to run secure Trusted Apps, e.g. OP-TEE
+- BL33: Is the last non-secure step, usually U-Boot which loads Linux
+
+Amlogic provides in binary form:
+
+- bl2.bin
+- bl30.bin
+- bl30.bin
+- bl31.img
+- bl32.bin
+
+And for lastest SoCs, Amlogic also provides the DDR drivers used by the BL2 binary.
+
+The licence of these files wasn't clear until recently, the currently Amlogic distribution licence
+is the following:
+
+.. code-block:: C
+
+ // Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ //
+ // All information contained herein is Amlogic confidential.
+ //
+ // This software is provided to you pursuant to Software License
+ // Agreement (SLA) with Amlogic Inc ("Amlogic"). This software may be
+ // used only in accordance with the terms of this agreement.
+ //
+ // Redistribution and use in source and binary forms, with or without
+ // modification is strictly prohibited without prior written permission
+ // from Amlogic.
+ //
+ // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+The following files are generated from the Amlogic U-Boot fork:
+
+- acs.bin: contains the PLL & DDR parameters for the board
+- bl301.bin: contains the DVFS & suspend-resume handling code for the board
+- bl33.bin: U-boot binary image
+
+The acs.bin & bl301.bin uses the U-Boot GPL-2.0+ headers & build systems, thus those
+are considered issued from GPL-2.0+ source code.
+
+The tools used to sign & package those binary files are delivered in binary format
+for Intel x86-64 and Python 2.x only.
+
+A collection of pre-built with the corresponding Amlogic binaries for the common
+commercially available boards were collected in the https://github.com/LibreELEC/amlogic-boot-fip
+repository.
+
+Using this collection for a commercially available board is very easy.
+
+Here considering the Libre Computer AML-S905X-CC, which codename is `lepotato`:
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `radxa-zero`
+
Amlogic does not provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
git trees published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `s400`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei510`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei610`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `u200`
+
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
Image creation
--------------
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `wetek-core2`
+
Amlogic does not provide sources for the firmware or the tools needed
to create the bootloader image, and WeTek has not publicly shared the
precompiled FIP binaries. However the public Khadas VIM2 sources also
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2022 Matthias Brugger <mbrugger@suse.com>
+
+Broadcom
+========
+
+.. toctree::
+ :maxdepth: 2
+
+ raspberrypi
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2022 Matthias Brugger <mbrugger@suse.com>
+
+Raspberry Pi
+============
+
+About this
+----------
+
+This document describes the information about Raspberry Pi boards
+and it's usage steps.
+
+Raspberry Pi boards
+-------------------
+
+List of the supported Rasbperry Pi boards and the corresponding defconfig files:
+
+32 bit
+^^^^^^
+
+* rpi_defconfig
+ - Raspberry Pi
+* rpi_0_w_defconfig
+ - Raspberry Pi 1
+ - Raspberry Pi zero
+* rpi_2_defconfig
+ - Raspberry Pi 2
+* rpi_3_32b_defconfig
+ - Raspberry Pi 3b
+* rpi_4_32b_defconfig
+ - Raspberry Pi 4b
+
+64 bit
+^^^^^^
+
+* rpi_3_defconfig
+ - Raspberry Pi 3b
+* rpi_3_b_plus_defconfig
+ - Raspberry Pi 3b+
+* rpi_4_defconfig
+ - Raspberry Pi 4b
+* rpi_arm64_defconfig
+ - Raspberry Pi 3b
+ - Raspberry Pi 3b+
+ - Raspberry Pi 4b
+ - Raspberry Pi 400
+ - Raspberry Pi CM 3
+ - Raspberry Pi CM 3+
+ - Raspberry Pi CM 4
+ - Raspberry Pi zero 2 w
+
+rpi_arm64_defconfig uses the device-tree provided by the firmware instead of
+the embedded one. It allows to use the same U-Boot binary to boot different
+boards.
apple/index
armltd/index
atmel/index
+ broadcom/index
congatec/index
coreboot/index
emulation/index
CONFIG_CMD_UBIFS=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+
+Run in QEMU
+-----------
+
+Download and compile Linaro version of qemu which contains ``n900`` qemu
+machine. Source code is available in qemu-linaro git repository and the
+last working version is at commit 8f8d8e0796efe1a6f34cdd83fb798f3c41217ec1.
+
+Use following commands to compile ``qemu-system-arm`` binary with ``n900``
+qemu machine support:
+
+.. code-block:: bash
+
+ git clone https://git.linaro.org/qemu/qemu-linaro.git
+ cd qemu-linaro
+ git checkout 8f8d8e0796efe1a6f34cdd83fb798f3c41217ec1
+ ./configure --enable-system --target-list=arm-softmmu --disable-werror
+ make -j4
+ cd ..
+ ln -s qemu-linaro/arm-softmmu/qemu-system-arm .
+
+Using ``n900`` qemu machine requires proprietary Nokia qemu ``qflasher`` tool
+(in reality it is just generator of qemu MTD images) with first stage images
+(``xloader-qemu.bin`` and ``secondary-qemu.bin``), similar what is required
+on the real HW. License of flasher and images allows non-commercial
+redistribution and it is available at maemo.org website:
+
+.. code-block:: bash
+
+ wget -c http://repository.maemo.org/qemu-n900/qemu-n900.tar.gz
+ tar -xf qemu-n900.tar.gz
+
+To generate qemu bootable MTD image ``mtd.img`` from U-Boot binary
+``u-boot.bin`` and unpacked first stage images, run following command:
+
+.. code-block:: bash
+
+ ./qflasher -v -x xloader-qemu.bin -s secondary-qemu.bin -k u-boot.bin -m rx51 -o mtd.img
+
+Instead of ``u-boot.bin`` binary it is possible to also used combined
+U-Boot + kernel binary ``combined.bin``.
+
+Finally, to boot ``mtd.img`` with graphics display and keyboard with optional
+serial console on current terminal, run:
+
+.. code-block:: bash
+
+ ./qemu-system-arm -M n900 -mtdblock mtd.img -serial /dev/tty
+
+Additionally it is possible to emulate also eMMC and uSD card by appending
+qemu ``-sd`` arguments:
+
+.. code-block:: bash
+
+ ./qemu-system-arm -M n900 -mtdblock mtd.img -sd emmc.img -sd sd.img -serial /dev/tty
+
+For more examples, look into the ``test/nokia_rx51_test.sh`` CI testing script.
- FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
- FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
- Google Bob (chromebook_bob)
+ - Google Kevin (chromebook_kevin)
- Khadas Edge (khadas-edge-rk3399)
- Khadas Edge-Captain (khadas-edge-captain-rk3399)
- Khadas Edge-V (hadas-edge-v-rk3399)
MAIX
====
-Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
-a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
-neural network processing and other "ai" tasks. This includes a "KPU" neural
-network processor, an audio processor supporting beamforming reception, and a
-digital video port supporting capture and output at VGA resolution. Other
-peripherals include 8M of SRAM (accessible with and without caching); remappable
-pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
-and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash;
-on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
-ESP32 chips.
+Several of the Sipeed Maix series of boards contain the Kendryte K210 processor,
+a 64-bit RISC-V CPU produced by Canaan Inc. This processor contains several
+peripherals to accelerate neural network processing and other "ai" tasks. This
+includes a "KPU" neural network processor, an audio processor supporting
+beamforming reception, and a digital video port supporting capture and output at
+VGA resolution. Other peripherals include 8M of SRAM (accessible with and
+without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
+accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
+peripherals vary, but include spi flash; on-board usb-serial bridges; ports for
+cameras, displays, and sd cards; and ESP32 chips.
Currently, only the Sipeed MAIX BiT V2.0 (bitm) and Sipeed MAIXDUINO are
supported, but the boards are fairly similar.
by verifying a signature (or message digest) of image with certificates.
This feature on U-Boot is enabled with::
- CONFIG_UEFI_SECURE_BOOT=y
+ CONFIG_EFI_SECURE_BOOT=y
To make the boot sequence safe, you need to establish a chain of trust;
In UEFI secure boot the chain trust is defined by the following UEFI variables
Required properties:
- compatible: should be
- "kendryte,k210-sysctl", "syscon", "simple-mfd"
+ "canaan,k210-sysctl", "syscon", "simple-mfd"
- reg: address and length of the sysctl registers
- reg-io-width: must be <4>
This node is a binding for the clock tree driver
Required properties:
-- compatible: should be "kendryte,k210-clk"
+- compatible: should be "canaan,k210-clk"
- clocks: phandle to the "in0" external oscillator
- #clock-cells: must be <1>
Example:
sysctl: syscon@50440000 {
- compatible = "kendryte,k210-sysctl", "syscon", "simple-mfd";
+ compatible = "canaan,k210-sysctl", "syscon", "simple-mfd";
reg = <0x50440000 0x100>;
reg-io-width = <4>;
sysclk: clock-controller {
- compatible = "kendryte,k210-clk";
+ compatible = "canaan,k210-clk";
clocks = <&in0>;
#clock-cells = <1>;
};
pins.
Required properties:
-- compatible: should be "kendryte,k210-fpioa"
+- compatible: should be "canaan,k210-fpioa"
- reg: address and length of the FPIOA registers
-- kendryte,sysctl: phandle to the "sysctl" register map node
-- kendryte,power-offset: offset in the register map of the power bank control
+- canaan,sysctl: phandle to the "sysctl" register map node
+- canaan,k210-power-offset: offset in the register map of the power bank control
register (in bytes)
Configuration nodes
Example:
fpioa: pinmux@502B0000 {
- compatible = "kendryte,k210-fpioa";
+ compatible = "canaan,k210-fpioa";
reg = <0x502B0000 0x100>;
- kendryte,sysctl = <&sysctl>;
- kendryte,power-offset = <K210_SYSCTL_POWER_SEL>;
+ canaan,k210-sysctl = <&sysctl>;
+ canaan,k210-power-offset = <K210_SYSCTL_POWER_SEL>;
/* JTAG running at 3.3V and driven at 11 mA */
fpioa_jtag: jtag {
- compatible : One of
"altr,socfpga-spi",
"altr,socfpga-arria10-spi",
- "canaan,kendryte-k210-spi",
- "canaan,kendryte-k210-ssi",
+ "canaan,k210-spi",
+ "canaan,k210-ssi",
"intel,stratix10-spi",
"intel,agilex-spi",
"mscc,ocelot-spi",
+alabaster==0.7.12
+Babel==2.9.1
+certifi==2021.10.8
+charset-normalizer==2.0.12
docutils==0.16
-sphinx==3.4.3
-sphinx_rtd_theme==1.0.0
+idna==3.3
+imagesize==1.3.0
+Jinja2==3.0.3
+MarkupSafe==2.1.1
+packaging==21.3
+Pygments==2.11.2
+pyparsing==3.0.7
+pytz==2022.1
+requests==2.27.1
six==1.16.0
+snowballstemmer==2.2.0
+Sphinx==3.4.3
+sphinx-rtd-theme==1.0.0
+sphinxcontrib-applehelp==1.0.2
+sphinxcontrib-devhelp==1.0.2
+sphinxcontrib-htmlhelp==2.0.0
+sphinxcontrib-jsmath==1.0.1
+sphinxcontrib-qthelp==1.0.3
+sphinxcontrib-serializinghtml==1.1.5
+urllib3==1.26.9
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+:
+
+wdt command
+============
+
+Synopsis
+--------
+
+::
+
+ wdt list
+ wdt dev [<name>]
+ wdt start <timeout_ms> [flags]
+ wdt stop
+ wdt reset
+ wdt expirer [flags]
+
+Description
+-----------
+
+The wdt command is used to control watchdog timers.
+
+The 'wdt list' command shows a list of all watchdog devices.
+
+The 'wdt dev' command called without argument shows the current watchdog device.
+The current device is set when passing the name of the device as argument.
+
+The 'wdt start' command starts the current watchdog timer.
+
+The 'wdt stop' command stops the current watchdog timer.
+
+The 'wdt reset' command resets the current watchdog timer without stopping it.
+
+The 'wdt expire' command let's the current watchdog timer expire immediately.
+This will lead to a reset.
+
+name
+ name of the watchdog device
+
+timeout_ms
+ timeout interval in milliseconds
+
+flags
+ unsigned long value passed to the driver. The usage is driver specific.
+ The value is ignored by most drivers.
+
+Example
+-------
+
+::
+
+ => wdt dev
+ No watchdog timer device set!
+ => wdt list
+ watchdog@1c20ca0 (sunxi_wdt)
+ => wdt dev watchdog@1c20ca0
+ => wdt dev
+ dev: watchdog@1c20ca0
+ => wdt start 3000
+ => wdt reset
+ => wdt stop
+ => wdt expire
+
+ U-Boot SPL 2022.04-rc3 (Mar 25 2022 - 13:48:33 +0000)
+
+ In the example above '(sunxi_wdt)' refers to the driver for the watchdog
+ device.
+
+Configuration
+-------------
+
+The command is only available if CONFIG_CMD_WDT=y.
+
+Return value
+------------
+
+The return value $? is 0 if the command succeeds, 1 upon failure.
}
priv->data = data;
- uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;;
+ uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;
uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
"bootcount" is stored in the environment. To prevent a
saveenv on all reboots, the environment variable
"upgrade_available" is used. If "upgrade_available" is
- 0, "bootcount" is always 0, if "upgrade_available" is
- 1 "bootcount" is incremented in the environment.
+ 0, "bootcount" is always 0. If "upgrade_available" is 1,
+ "bootcount" is incremented in the environment.
So the Userspace Application must set the "upgrade_available"
- and "bootcount" variable to 0, if a boot was successfully.
+ and "bootcount" variables to 0, if the system booted successfully.
config BOOTCOUNT_RAM
bool "Boot counter in RAM"
help
- Store the bootcount in DRAM protected against against bit errors
+ Store the bootcount in DRAM protected against bit errors
due to short power loss or holding a system in RESET.
config BOOTCOUNT_I2C
help
Set the Maximum number of reboot cycles allowed without the boot
counter being cleared.
- If set to 0 do not set a boot limit in the environment.
+ If set to 0, do not set a boot limit in the environment.
config BOOTCOUNT_ALEN
int "I2C address length"
obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
-obj-$(CONFIG_CLK_K210) += clk_kendryte.o
+obj-$(CONFIG_CLK_K210) += clk_k210.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_MVEBU) += mvebu/
#include <serial.h>
#include <dt-bindings/clock/k210-sysctl.h>
#include <dt-bindings/mfd/k210-sysctl.h>
-#include <kendryte/pll.h>
+#include <k210/pll.h>
#include <linux/bitfield.h>
DECLARE_GLOBAL_DATA_PTR;
}
static const struct udevice_id k210_clk_ids[] = {
- { .compatible = "kendryte,k210-clk" },
+ { .compatible = "canaan,k210-clk" },
{ },
};
if (ops->probe_chip) {
ret = ops->probe_chip(bus, chip_addr, chip_flags);
- if (!ret || ret != -ENOSYS)
+ if (ret != -ENOSYS)
return ret;
}
}
debug("success\n");
- break;
+ return 0;
}
- return 0;
+ return -ETIMEDOUT;
}
int atsha204a_idle(struct udevice *dev)
}
do {
+ udelay(ATSHA204A_EXECTIME);
res = atsha204a_recv_resp(dev, resp);
if (!res || res == -EMSGSIZE || res == -EBADMSG)
break;
debug("ATSHA204A transaction polling for response "
"(timeout = %d)\n", timeout);
- udelay(ATSHA204A_EXECTIME);
timeout -= ATSHA204A_EXECTIME;
} while (timeout > 0);
fdt_addr_t *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE) {
debug("Can't get ATSHA204A I2C base address\n");
return -ENXIO;
* Based on Dirk Behme's
* https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
* which is based on Freescale's
- * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
+ * https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/misc/imx_otp.c?id=9aa74e6,
* which is:
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*/
struct mmc *mmc = &plat->mmc;
u32 irqstaten = esdhc_read32(®s->irqstaten);
u32 irqsigen = esdhc_read32(®s->irqsigen);
- int i, ret = -ETIMEDOUT;
- u32 val, mixctrl;
+ int i, err, ret = -ETIMEDOUT;
+ u32 val, mixctrl, tmp;
/* clock tuning is not needed for upto 52MHz */
if (mmc->clock <= 52000000)
return 0;
+ /* make sure the card clock keep on */
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
val = esdhc_read32(®s->autoc12err);
esdhc_stop_tuning(mmc);
+ /* change to default setting, let host control the card clock */
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
+ if (err)
+ dev_warn(dev, "card clock not gate off as expect.\n");
+
return ret;
}
#endif
static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
int timeout_us)
{
- int ret;
+ int ret, err;
u32 tmp;
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
+ /* make sure the card clock keep on */
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp,
!!(tmp & PRSSTAT_DAT0) == !!state,
timeout_us);
+
+ /* change to default setting, let host control the card clock */
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
+ if (err)
+ dev_warn(dev, "card clock not gate off as expect.\n");
+
return ret;
}
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
+/* DWCMSHC specific Mode Select value */
+#define DWCMSHC_CTRL_HS400 0x7
/* 400KHz is max freq for card ID etc. Use that as min */
#define EMMC_MIN_FREQ 400000
#define KHz (1000)
((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
PHYCTRL_DLLRDY_DONE)
+#define ARASAN_VENDOR_REGISTER 0x78
+#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
+
+/* DWC IP vendor area 1 pointer */
+#define DWCMSHC_P_VENDOR_AREA1 0xe8
+#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
+/* Offset inside the vendor area 1 */
+#define DWCMSHC_EMMC_CONTROL 0x2c
+#define DWCMSHC_CARD_IS_EMMC BIT(0)
+#define DWCMSHC_ENHANCED_STROBE BIT(8)
+
/* Rockchip specific Registers */
#define DWCMSHC_EMMC_DLL_CTRL 0x800
#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
#define DWCMSHC_EMMC_DLL_INC_VALUE 2
#define DWCMSHC_EMMC_DLL_INC 8
#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
-#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
-#define DLL_STRBIN_TAPNUM_DEFAULT 0x3
+#define DLL_TXCLK_TAPNUM_DEFAULT 0xA
+
+#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
+#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
+#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
+#define DLL_STRBIN_DELAY_NUM_OFFSET 16
+#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
+
#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
* Return: 0 if successful, -ve on error
*/
int (*set_ios_post)(struct sdhci_host *host);
+
+ /**
+ * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
+ *
+ * This is the set_enhanced_strobe() SDHCI operation that should
+ * be used for the hardware this driver data is associated with.
+ * Normally, this is used to set any host-specific configuration
+ * necessary for HS400 ES.
+ *
+ * @host: SDHCI host structure
+ * Return: 0 if successful, -ve on error
+ */
+ int (*set_enhanced_strobe)(struct sdhci_host *host);
};
static int rk3399_emmc_phy_init(struct udevice *dev)
return 0;
}
+static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+ u32 vendor;
+
+ vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
+ if (mmc->selected_mode == MMC_HS_400_ES)
+ vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
+ else
+ vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
+ sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
+
+ return 0;
+}
+
static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
{
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
rk3399_emmc_phy_power_off(priv->phy);
sdhci_set_control_reg(host);
+
+ /*
+ * Reinitializing the device tries to set it to lower-speed modes
+ * first, which fails if the Enhanced Strobe bit is set, making
+ * the device impossible to use. Set the correct value here to
+ * let reinitialization attempts succeed.
+ */
+ if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
+ rk3399_sdhci_set_enhanced_strobe(host);
};
static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_STRBIN_TAPNUM_DEFAULT;
+ DLL_STRBIN_TAPNUM_DEFAULT |
+ DLL_STRBIN_TAPNUM_FROM_SW;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
} else {
/* reset the clock phase when the frequency is lower than 100MHz */
extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
+ /*
+ * Before switching to hs400es mode, the driver will enable
+ * enhanced strobe first. PHY needs to configure the parameters
+ * of enhanced strobe first.
+ */
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_STRBIN_DELAY_NUM_SEL |
+ DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
}
return 0;
return 0;
}
+static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+ u32 vendor;
+ int reg;
+
+ reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
+ + DWCMSHC_EMMC_CONTROL;
+
+ vendor = sdhci_readl(host, reg);
+ if (mmc->selected_mode == MMC_HS_400_ES)
+ vendor |= DWCMSHC_ENHANCED_STROBE;
+ else
+ vendor &= ~DWCMSHC_ENHANCED_STROBE;
+ sdhci_writel(host, vendor, reg);
+
+ return 0;
+}
+
static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
uint clock = mmc->tran_speed;
- u32 reg;
+ u32 reg, vendor_reg;
if (!clock)
clock = mmc->clock;
if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg &= ~SDHCI_CTRL_UHS_MASK;
- reg |= SDHCI_CTRL_HS400;
+ reg |= DWCMSHC_CTRL_HS400;
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+
+ vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
+ + DWCMSHC_EMMC_CONTROL;
+ /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
+ reg = sdhci_readw(host, vendor_reg);
+ reg |= DWCMSHC_CARD_IS_EMMC;
+ sdhci_writew(host, reg, vendor_reg);
} else {
sdhci_set_uhs_timing(host);
}
return ret;
}
+static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+
+ if (data->set_enhanced_strobe)
+ return data->set_enhanced_strobe(host);
+
+ return -ENOTSUPP;
+}
+
static struct sdhci_ops rockchip_sdhci_ops = {
.set_ios_post = rockchip_sdhci_set_ios_post,
.platform_execute_tuning = &rockchip_sdhci_execute_tuning,
.set_control_reg = rockchip_sdhci_set_control_reg,
+ .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
};
static int rockchip_sdhci_probe(struct udevice *dev)
.emmc_phy_init = rk3399_emmc_phy_init,
.set_control_reg = rk3399_sdhci_set_control_reg,
.set_ios_post = rk3399_sdhci_set_ios_post,
+ .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
};
static const struct sdhci_data rk3568_data = {
.get_phy = rk3568_emmc_get_phy,
.emmc_phy_init = rk3568_emmc_phy_init,
.set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
};
static const struct udevice_id sdhci_ids[] = {
reg |= SDHCI_CTRL_UHS_SDR104;
break;
case MMC_HS_400:
+ case MMC_HS_400_ES:
reg |= SDHCI_CTRL_HS400;
break;
default:
mmc->selected_mode == MMC_DDR_52 ||
mmc->selected_mode == MMC_HS_200 ||
mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == MMC_HS_400_ES ||
mmc->selected_mode == UHS_SDR25 ||
mmc->selected_mode == UHS_SDR50 ||
mmc->selected_mode == UHS_SDR104 ||
return -ETIMEDOUT;
}
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+static int sdhci_set_enhanced_strobe(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct sdhci_host *host = mmc->priv;
+
+ if (host->ops && host->ops->set_enhanced_strobe)
+ return host->ops->set_enhanced_strobe(host);
+
+ return -ENOTSUPP;
+}
+#endif
+
const struct dm_mmc_ops sdhci_ops = {
.send_cmd = sdhci_send_command,
.set_ios = sdhci_set_ios,
.execute_tuning = sdhci_execute_tuning,
#endif
.wait_dat0 = sdhci_wait_dat0,
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ .set_enhanced_strobe = sdhci_set_enhanced_strobe,
+#endif
};
#else
static const struct mmc_ops sdhci_ops = {
.set_ios_post = xenon_sdhci_set_ios_post
};
+static struct dm_mmc_ops xenon_mmc_ops;
+
static int xenon_sdhci_probe(struct udevice *dev)
{
struct xenon_sdhci_plat *plat = dev_get_plat(dev);
host->mmc->dev = dev;
upriv->mmc = host->mmc;
+ xenon_mmc_ops = sdhci_ops;
+ xenon_mmc_ops.wait_dat0 = NULL;
+
/* Set quirks */
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
.id = UCLASS_MMC,
.of_match = xenon_sdhci_ids,
.of_to_plat = xenon_sdhci_of_to_plat,
- .ops = &sdhci_ops,
+ .ops = &xenon_mmc_ops,
.bind = xenon_sdhci_bind,
.probe = xenon_sdhci_probe,
.remove = xenon_sdhci_remove,
struct nand_chip *chip = mtd_to_nand(mtd);
struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
unsigned int block_mark_bit_offset;
+ int corr, ds_corr;
/* The default for the length of Galois Field. */
geo->gf_len = 13;
geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
nand_info->max_ecc_strength_supported);
+ /* check ecc strength, same as nand_ecc_is_strong_enough() did*/
+ if (chip->ecc_step_ds) {
+ corr = mtd->writesize * geo->ecc_strength /
+ geo->ecc_chunkn_size;
+ ds_corr = mtd->writesize * chip->ecc_strength_ds /
+ chip->ecc_step_ds;
+ if (corr < ds_corr ||
+ geo->ecc_strength < chip->ecc_strength_ds)
+ return -EINVAL;
+ }
+
block_mark_bit_offset = mtd->writesize * 8 -
(geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
+ MXS_NAND_METADATA_SIZE * 8);
struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_chip *nand = mtd_to_nand(mtd);
struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
+ int err;
if (chip->ecc_strength_ds > nand_info->max_ecc_strength_supported) {
printf("unsupported NAND chip, minimum ecc required %d\n"
return -EINVAL;
}
- if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) &&
- mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) {
- dev_warn(mtd->dev, "use legacy bch geometry\n");
- return mxs_nand_legacy_calc_ecc_layout(geo, mtd);
+ /* use the legacy bch setting by default */
+ if ((!nand_info->use_minimum_ecc && mtd->oobsize < 1024) ||
+ !(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) {
+ dev_dbg(mtd->dev, "use legacy bch geometry\n");
+ err = mxs_nand_legacy_calc_ecc_layout(geo, mtd);
+ if (!err)
+ return 0;
}
- if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize)
- return mxs_nand_calc_ecc_for_large_oob(geo, mtd);
+ /* for large oob nand */
+ if (mtd->oobsize > 1024) {
+ dev_dbg(mtd->dev, "use large oob bch geometry\n");
+ err = mxs_nand_calc_ecc_for_large_oob(geo, mtd);
+ if (!err)
+ return 0;
+ }
- return mxs_nand_calc_ecc_layout_by_info(geo, mtd,
- chip->ecc_strength_ds, chip->ecc_step_ds);
+ /* otherwise use the minimum ecc nand chips required */
+ dev_dbg(mtd->dev, "use minimum ecc bch geometry\n");
+ err = mxs_nand_calc_ecc_layout_by_info(geo, mtd, chip->ecc_strength_ds,
+ chip->ecc_step_ds);
- return 0;
+ if (err)
+ dev_err(mtd->dev, "none of the bch geometry setting works\n");
+
+ return err;
+}
+
+void mxs_nand_dump_geo(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
+ struct bch_geometry *geo = &nand_info->bch_geometry;
+
+ dev_dbg(mtd->dev, "BCH Geometry :\n"
+ "GF Length\t\t: %u\n"
+ "ECC Strength\t\t: %u\n"
+ "ECC for Meta\t\t: %u\n"
+ "ECC Chunk0 Size\t\t: %u\n"
+ "ECC Chunkn Size\t\t: %u\n"
+ "ECC Chunk Count\t\t: %u\n"
+ "Block Mark Byte Offset\t: %u\n"
+ "Block Mark Bit Offset\t: %u\n",
+ geo->gf_len,
+ geo->ecc_strength,
+ geo->ecc_for_meta,
+ geo->ecc_chunk0_size,
+ geo->ecc_chunkn_size,
+ geo->ecc_chunk_count,
+ geo->block_mark_byte_offset,
+ geo->block_mark_bit_offset);
}
/*
if (ret)
return ret;
+ mxs_nand_dump_geo(mtd);
+
/* Configure BCH and set NFC geometry */
mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
- info->legacy_bch_geometry = dev_read_bool(dev, "fsl,legacy-bch-geometry");
-
if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) {
/* Assigned clock already set clock */
struct clk gpmi_clk;
#include <log.h>
#include <nand.h>
#include <reset.h>
+#include <asm/gpio.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
struct stm32_fmc2_nand {
struct nand_chip chip;
struct stm32_fmc2_timings timings;
+ struct gpio_desc wp_gpio;
int ncs;
int cs_used[FMC2_MAX_CE];
};
nand->cs_used[i] = cs[i];
}
+ gpio_request_by_name_nodev(node, "wp-gpios", 0, &nand->wp_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
nand->chip.flash_node = node;
return 0;
chip->ecc.size = FMC2_ECC_STEP_SIZE;
chip->ecc.strength = FMC2_ECC_BCH8;
+ /* Disable Write Protect */
+ if (dm_gpio_is_valid(&nand->wp_gpio))
+ dm_gpio_set_value(&nand->wp_gpio, 0);
+
ret = nand_scan_ident(mtd, nand->ncs, NULL);
if (ret)
return ret;
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
-obj-$(CONFIG_PINCTRL_K210) += pinctrl-kendryte.o
+obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-$(CONFIG_PINCTRL_MTK) += mediatek/
obj-$(CONFIG_PINCTRL_MSCC) += mscc/
{
int i;
- for (i = K210_PC_DRIVE_MAX; i; i--)
+ for (i = K210_PC_DRIVE_MAX; i >= 0; i--)
if (k210_pc_drive_strength[i] < max_strength_ua)
return i;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (argument)
- val |= K210_PC_PD;
+ val |= K210_PC_PU;
else
return -EINVAL;
break;
{
int ret, i, j;
struct k210_pc_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
priv->fpioa = dev_read_addr_ptr(dev);
if (!priv->fpioa)
if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
goto err;
- priv->sysctl = syscon_regmap_lookup_by_phandle(dev, "kendryte,sysctl");
+ ret = dev_read_phandle_with_args(dev, "canaan,k210-sysctl-power",
+ NULL, 1, 0, &args);
+ if (ret)
+ goto err;
+
+ if (args.args_count != 1) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ priv->sysctl = syscon_node_to_regmap(args.node);
if (IS_ERR(priv->sysctl)) {
- ret = -ENODEV;
+ ret = PTR_ERR(priv->sysctl);
goto err;
}
- ret = dev_read_u32(dev, "kendryte,power-offset", &priv->power_offset);
- if (ret)
- goto err;
+ priv->power_offset = args.args[0];
debug("%s: fpioa = %p sysctl = %p power offset = %x\n", __func__,
priv->fpioa, (void *)priv->sysctl->ranges[0].start,
}
static const struct udevice_id k210_pc_ids[] = {
- { .compatible = "kendryte,k210-fpioa" },
+ { .compatible = "canaan,k210-fpioa" },
{ }
};
* CS1, n=2
* CS0 & CS1, n = 3
*/
- sdram_params->ch[channel].rank = 2,
+ sdram_params->ch[channel].rank = 2;
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);
* CS1, n=2
* CS0 & CS1, n = 3
*/
- sdram_params->ch[channel].rank = 2,
+ sdram_params->ch[channel].rank = 2;
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);
#define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
#define RCC_DDRITFCR_DPHYRST (BIT(18))
#define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
+#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
+#define RCC_DDRITFCR_DDRCKMOD_ASR BIT(20)
struct reg_desc {
const char *name;
wait_sw_done_ack(ctl);
}
+static void stm32mp1_asr_enable(struct ddr_info *priv)
+{
+ struct stm32mp1_ddrctl *ctl = priv->ctl;
+
+ clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK,
+ RCC_DDRITFCR_DDRCKMOD_ASR);
+
+ start_sw_done(ctl);
+
+ setbits_le32(&ctl->hwlpctl, DDRCTRL_HWLPCTL_HW_LP_EN);
+ writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) |
+ DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01),
+ &ctl->pwrtmg);
+ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
+ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
+
+ setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ wait_sw_done_ack(ctl);
+}
+
/* board-specific DDR power initializations. */
__weak int board_ddr_power_init(enum ddr_type ddr_type)
{
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
config->c_reg.pwrctl);
+/* Enable auto-self-refresh, which saves a bit of power at runtime. */
+ stm32mp1_asr_enable(priv);
+
/* enable uMCTL2 AXI port 0 and 1 */
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32(n) (((n) & 0xff) << 16)
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32(n) ((n) & 0x1f)
+
+#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
+
#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
return 0;
}
+static int dw_spi_apb_k210_init(struct udevice *bus, struct dw_spi_priv *priv)
+{
+ /*
+ * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
+ * documented to have a 32 word deep TX and RX FIFO, which
+ * spi_hw_init() detects. However, when the RX FIFO is filled up to
+ * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid
+ * this problem by force setting fifo_len to 31.
+ */
+ priv->fifo_len = 31;
+
+ return dw_spi_apb_init(bus, priv);
+}
+
static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv)
{
priv->max_xfer = 32;
static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
{
dw_write(priv, DW_SPI_SSIENR, 0);
- dw_write(priv, DW_SPI_IMR, 0xff);
+ dw_write(priv, DW_SPI_IMR, 0);
dw_write(priv, DW_SPI_SSIENR, 1);
/*
*/
{ .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init },
- { .compatible = "canaan,kendryte-k210-spi", .data = (ulong)dw_spi_apb_init },
- { .compatible = "canaan,kendryte-k210-ssi", .data = (ulong)dw_spi_dwc_init },
+ { .compatible = "canaan,k210-spi", .data = (ulong)dw_spi_apb_k210_init},
+ { .compatible = "canaan,k210-ssi", .data = (ulong)dw_spi_dwc_init },
{ .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "mscc,ocelot-spi", .data = (ulong)dw_spi_apb_init },
plat->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
plat->np_tx_fifo_sz = dev_read_u32_default(dev, "g-np-tx-fifo-size", 0);
- plat->tx_fifo_sz_nb =
- dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32);
+ ret = dev_read_size(dev, "g-tx-fifo-size");
+ if (ret > 0)
+ plat->tx_fifo_sz_nb = ret / sizeof(u32);
if (plat->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS)
plat->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS;
if (plat->tx_fifo_sz_nb) {
struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
+ ulong rate;
int ret;
priv->regs = (void *)dev_read_addr(dev);
}
}
- ret = clk_set_rate(&pclk, timings.pixelclock.typ);
- if (ret)
- dev_warn(dev, "fail to set pixel clock %d hz\n",
- timings.pixelclock.typ);
+ rate = clk_set_rate(&pclk, timings.pixelclock.typ);
+ if (IS_ERR_VALUE(rate))
+ dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
+ timings.pixelclock.typ, rate);
dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
- timings.pixelclock.typ, clk_get_rate(&pclk));
+ timings.pixelclock.typ, rate);
ret = reset_get_by_index(dev, 0, &rst);
if (ret) {
* information represents the requires size and alignment of the frame buffer
* for the device. The values can be an over-estimate but cannot be too
* small. The actual values will be suppled (in the same manner) by the bind()
- * method after relocation.
+ * method after relocation. Additionally driver can allocate frame buffer
+ * itself by setting plat->base.
*
* This information is then picked up by video_reserve() which works out how
* much memory is needed for all devices. This is allocated between
if (!plat->size)
return 0;
+ /* Allow drivers to allocate the frame buffer themselves */
+ if (plat->base)
+ return 0;
+
align = plat->align ? plat->align : 1 << 20;
base = *addrp - plat->size;
base &= ~(align - 1);
}
/**
+ * get_bmp_col_x2r10g10b10() - Convert a colour-table entry into a x2r10g10b10 pixel value
+ *
+ * Return: value to write to the x2r10g10b10 frame buffer for this palette entry
+ */
+static u32 get_bmp_col_x2r10g10b10(struct bmp_color_table_entry *cte)
+{
+ return ((cte->red << 22U) |
+ (cte->green << 12U) |
+ (cte->blue << 2U));
+}
+
+/**
* write_pix8() - Write a pixel from a BMP image into the framebuffer
*
* This handles frame buffers with 8, 16, 24 or 32 bits per pixel
* which is either written directly (bpix == 8) or used to look up the
* palette to get a colour to write
*/
-static void write_pix8(u8 *fb, uint bpix, struct bmp_color_table_entry *palette,
- u8 *bmap)
+static void write_pix8(u8 *fb, uint bpix, enum video_format eformat,
+ struct bmp_color_table_entry *palette, u8 *bmap)
{
if (bpix == 8) {
*fb++ = *bmap;
*fb++ = cte->red;
*fb++ = cte->green;
*fb++ = cte->blue;
+ } else if (eformat == VIDEO_X2R10G10B10) {
+ *(u32 *)fb = get_bmp_col_x2r10g10b10(cte);
} else {
*fb++ = cte->blue;
*fb++ = cte->green;
}
}
-static void draw_unencoded_bitmap(u8 **fbp, uint bpix, uchar *bmap,
+static void draw_unencoded_bitmap(u8 **fbp, uint bpix,
+ enum video_format eformat, uchar *bmap,
struct bmp_color_table_entry *palette,
int cnt)
{
u8 *fb = *fbp;
while (cnt > 0) {
- write_pix8(fb, bpix, palette, bmap++);
+ write_pix8(fb, bpix, eformat, palette, bmap++);
fb += bpix / 8;
cnt--;
}
*fbp = fb;
}
-static void draw_encoded_bitmap(u8 **fbp, uint bpix,
+static void draw_encoded_bitmap(u8 **fbp, uint bpix, enum video_format eformat,
struct bmp_color_table_entry *palette, u8 *bmap,
int cnt)
{
u8 *fb = *fbp;
while (cnt > 0) {
- write_pix8(fb, bpix, palette, bmap);
+ write_pix8(fb, bpix, eformat, palette, bmap);
fb += bpix / 8;
cnt--;
}
int x, y;
int decode = 1;
uint bytes_per_pixel = bpix / 8;
+ enum video_format eformat = priv->format;
debug("%s\n", __func__);
bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
else
cnt = runlen;
draw_unencoded_bitmap(
- &fb, bpix,
+ &fb, bpix, eformat,
bmap, palette, cnt);
}
x += runlen;
cnt = width - x;
else
cnt = runlen;
- draw_encoded_bitmap(&fb, bpix, palette,
- &bmap[1], cnt);
+ draw_encoded_bitmap(&fb, bpix, eformat,
+ palette, &bmap[1],
+ cnt);
}
x += runlen;
}
unsigned long width, height, byte_width;
unsigned long pwidth = priv->xsize;
unsigned colours, bpix, bmp_bpix;
+ enum video_format eformat;
struct bmp_color_table_entry *palette;
int hdr_size;
int ret;
colours = 1 << bmp_bpix;
bpix = VNBITS(priv->bpix);
+ eformat = priv->format;
if (bpix != 1 && bpix != 8 && bpix != 16 && bpix != 32) {
printf("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
for (j = 0; j < width; j++) {
- write_pix8(fb, bpix, palette, bmap);
+ write_pix8(fb, bpix, eformat, palette, bmap);
bmap++;
fb += bpix / 8;
}
(bmap[0] >> 3);
bmap += 3;
fb += 2;
+ } else if (eformat == VIDEO_X2R10G10B10) {
+ u32 pix;
+
+ pix = *bmap++ << 2U;
+ pix |= *bmap++ << 12U;
+ pix |= *bmap++ << 22U;
+ *fb++ = pix & 0xff;
+ *fb++ = (pix >> 8) & 0xff;
+ *fb++ = (pix >> 16) & 0xff;
+ *fb++ = pix >> 24;
} else {
*fb++ = *bmap++;
*fb++ = *bmap++;
if (IS_ENABLED(CONFIG_BMP_32BPP)) {
for (i = 0; i < height; ++i) {
for (j = 0; j < width; j++) {
- *fb++ = *bmap++;
- *fb++ = *bmap++;
- *fb++ = *bmap++;
- *fb++ = *bmap++;
+ if (eformat == VIDEO_X2R10G10B10) {
+ u32 pix;
+
+ pix = *bmap++ << 2U;
+ pix |= *bmap++ << 12U;
+ pix |= *bmap++ << 22U;
+ pix |= (*bmap++ >> 6) << 30U;
+ *fb++ = pix & 0xff;
+ *fb++ = (pix >> 8) & 0xff;
+ *fb++ = (pix >> 16) & 0xff;
+ *fb++ = pix >> 24;
+ } else {
+ *fb++ = *bmap++;
+ *fb++ = *bmap++;
+ *fb++ = *bmap++;
+ *fb++ = *bmap++;
+ }
}
fb -= priv->line_length + width * (bpix / 8);
}
#include <configs/rk3399_common.h>
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+
#endif
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-/*
- * Framebuffer
- */
-/* Video console */
-#define VIDEO_FB_16BPP_PIXEL_SWAP
-#define VIDEO_FB_16BPP_WORD_SWAP
-
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
"stdin=usbtty,serial,keyboard\0" \
- "stdout=usbtty,serial,vga\0" \
- "stderr=usbtty,serial,vga\0" \
+ "stdout=usbtty,serial,vidconsole\0" \
+ "stderr=usbtty,serial,vidconsole\0" \
"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
"switchmmc=mmc dev ${mmcnum}\0" \
"kernaddr=0x82008000\0" \
"fdt_addr_r=0x80400000\0" \
"scriptaddr=0x80020000\0" \
"kernel_addr_r=0x80060000\0" \
- "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "fdtfile=k210/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"k210_bootcmd=load mmc 0:1 $loadaddr /uImage && " \
"load mmc 0:1 $fdt_addr_r /k210.dtb && " \
"bootm $loadaddr - $fdt_addr_r\0"
#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
#define SW_LINEIN_INSERT 0x0d /* set = inserted */
#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
-#define SW_MAX 0x0f
+#define SW_PEN_INSERTED 0x0f /* set = pen inserted */
+#define SW_MAX 0x10
#define SW_CNT (SW_MAX+1)
/*
extern const efi_guid_t efi_global_variable_guid;
extern const efi_guid_t efi_guid_console_control;
extern const efi_guid_t efi_guid_device_path;
+/* GUID of the EFI system partition */
+extern const efi_guid_t efi_system_partition_guid;
/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
extern const efi_guid_t efi_guid_driver_binding_protocol;
/* event group ExitBootServices() invoked */
int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
const char *if_typename, int diskid,
const char *pdevname);
-/* Check if it is EFI system partition */
-bool efi_disk_is_system_part(efi_handle_t handle);
/* Called by bootefi to make GOP (graphical) interface available */
efi_status_t efi_gop_register(void);
/* Called by bootefi to make the network interface available */
#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024)
#endif
-
+/* shorten device path */
+struct efi_device_path *efi_dp_shorten(struct efi_device_path *dp);
struct efi_device_path *efi_dp_next(const struct efi_device_path *dp);
int efi_dp_match(const struct efi_device_path *a,
const struct efi_device_path *b);
-struct efi_object *efi_dp_find_obj(struct efi_device_path *dp,
- struct efi_device_path **rem);
+efi_handle_t efi_dp_find_obj(struct efi_device_path *dp,
+ const efi_guid_t *guid,
+ struct efi_device_path **rem);
/* get size of the first device path instance excluding end node */
efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp);
/* size of multi-instance device path excluding end node */
#define VENDORSPEC_HCKEN 0x00001000
#define VENDORSPEC_IPGEN 0x00000800
#define VENDORSPEC_INIT 0x20007809
+#define VENDORSPEC_FRC_SDCLK_ON 0x00000100
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define PRSSTAT_CINS (0x00010000)
#define PRSSTAT_BREN (0x00000800)
#define PRSSTAT_BWEN (0x00000400)
+#define PRSSTAT_SDOFF (0x00000080)
#define PRSSTAT_SDSTB (0X00000008)
#define PRSSTAT_DLA (0x00000004)
#define PRSSTAT_CICHB (0x00000002)
struct udevice *dev;
unsigned int max_ecc_strength_supported;
bool use_minimum_ecc;
- /* legacy bch geometry flag */
- bool legacy_bch_geometry;
int cur_chip;
uint32_t cmd_queue_len;
int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
int (*set_delay)(struct sdhci_host *host);
int (*deferred_probe)(struct sdhci_host *host);
+
+ /**
+ * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
+ *
+ * This is called after setting the card speed and mode to
+ * HS400 ES, and should set any host-specific configuration
+ * necessary for it.
+ *
+ * @host: SDHCI host structure
+ * Return: 0 if successful, -ve on error
+ */
+ int (*set_enhanced_strobe)(struct sdhci_host *host);
};
#define ADMA_MAX_LEN 65532
-DFW_PATCHLEVEL="0x$(PATCHLEVEL)"
CFLAGS_helloworld.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI)
+CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI)
+CFLAGS_initrddump_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI)
ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
always += helloworld.efi
targets += helloworld.o
endif
+ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
+always += dtbdump.efi
+endif
+
+ifdef CONFIG_EFI_LOAD_FILE2_INITRD
+always += initrddump.efi
+endif
+
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += efi_bootmgr.o
obj-y += efi_boottime.o
info->system_table = &systab;
if (device_path) {
- info->device_handle = efi_dp_find_obj(device_path, NULL);
+ info->device_handle = efi_dp_find_obj(device_path, NULL, NULL);
dp = efi_dp_append(device_path, file_path);
if (!dp) {
{
efi_handle_t device;
efi_status_t ret;
- struct efi_device_path *dp;
+ struct efi_device_path *dp, *rem;
struct efi_load_file_protocol *load_file_protocol = NULL;
efi_uintn_t buffer_size;
uint64_t addr, pages;
*size = 0;
dp = file_path;
- ret = EFI_CALL(efi_locate_device_path(
- &efi_simple_file_system_protocol_guid, &dp, &device));
+ device = efi_dp_find_obj(dp, NULL, &rem);
+ ret = efi_search_protocol(device, &efi_simple_file_system_protocol_guid,
+ NULL);
if (ret == EFI_SUCCESS)
return efi_load_image_from_file(file_path, buffer, size);
- ret = EFI_CALL(efi_locate_device_path(
- &efi_guid_load_file_protocol, &dp, &device));
+ ret = efi_search_protocol(device, &efi_guid_load_file_protocol, NULL);
if (ret == EFI_SUCCESS) {
guid = &efi_guid_load_file_protocol;
} else if (!boot_policy) {
guid = &efi_guid_load_file2_protocol;
- ret = EFI_CALL(efi_locate_device_path(guid, &dp, &device));
+ ret = efi_search_protocol(device, guid, NULL);
}
if (ret != EFI_SUCCESS)
return EFI_NOT_FOUND;
if (ret != EFI_SUCCESS)
return EFI_NOT_FOUND;
buffer_size = 0;
- ret = load_file_protocol->load_file(load_file_protocol, dp,
- boot_policy, &buffer_size,
- NULL);
+ ret = EFI_CALL(load_file_protocol->load_file(
+ load_file_protocol, rem, boot_policy,
+ &buffer_size, NULL));
if (ret != EFI_BUFFER_TOO_SMALL)
goto out;
pages = efi_size_in_pages(buffer_size);
goto out;
}
ret = EFI_CALL(load_file_protocol->load_file(
- load_file_protocol, dp, boot_policy,
+ load_file_protocol, rem, boot_policy,
&buffer_size, (void *)(uintptr_t)addr));
if (ret != EFI_SUCCESS)
efi_free_pages(addr, pages);
/**
* device_is_present_and_system_part - check if a device exists
- * @dp Device path
*
* Check if a device pointed to by the device path, @dp, exists and is
* located in UEFI system partition.
*
+ * @dp device path
* Return: true - yes, false - no
*/
static bool device_is_present_and_system_part(struct efi_device_path *dp)
{
efi_handle_t handle;
+ struct efi_device_path *rem;
- handle = efi_dp_find_obj(dp, NULL);
+ /* Check device exists */
+ handle = efi_dp_find_obj(dp, NULL, NULL);
if (!handle)
return false;
- return efi_disk_is_system_part(handle);
+ /* Check device is on system partition */
+ handle = efi_dp_find_obj(dp, &efi_system_partition_guid, &rem);
+ if (!handle)
+ return false;
+
+ return true;
}
/**
}
}
-/*
+/**
+ * efi_dp_shorten() - shorten device-path
+ *
* We can have device paths that start with a USB WWID or a USB Class node,
* and a few other cases which don't encode the full device path with bus
* hierarchy:
*
- * - MESSAGING:USB_WWID
- * - MESSAGING:USB_CLASS
- * - MEDIA:FILE_PATH
- * - MEDIA:HARD_DRIVE
- * - MESSAGING:URI
+ * * MESSAGING:USB_WWID
+ * * MESSAGING:USB_CLASS
+ * * MEDIA:FILE_PATH
+ * * MEDIA:HARD_DRIVE
+ * * MESSAGING:URI
*
* See UEFI spec (section 3.1.2, about short-form device-paths)
+ *
+ * @dp: original device-path
+ * @Return: shortened device-path or NULL
*/
-static struct efi_device_path *shorten_path(struct efi_device_path *dp)
+struct efi_device_path *efi_dp_shorten(struct efi_device_path *dp)
{
while (dp) {
/*
return dp;
}
-static struct efi_object *find_obj(struct efi_device_path *dp, bool short_path,
- struct efi_device_path **rem)
+/**
+ * find_handle() - find handle by device path and installed protocol
+ *
+ * If @rem is provided, the handle with the longest partial match is returned.
+ *
+ * @dp: device path to search
+ * @guid: GUID of protocol that must be installed on path or NULL
+ * @short_path: use short form device path for matching
+ * @rem: pointer to receive remaining device path
+ * Return: matching handle
+ */
+static efi_handle_t find_handle(struct efi_device_path *dp,
+ const efi_guid_t *guid, bool short_path,
+ struct efi_device_path **rem)
{
- struct efi_object *efiobj;
- efi_uintn_t dp_size = efi_dp_instance_size(dp);
+ efi_handle_t handle, best_handle = NULL;
+ efi_uintn_t len, best_len = 0;
+
+ len = efi_dp_instance_size(dp);
- list_for_each_entry(efiobj, &efi_obj_list, link) {
+ list_for_each_entry(handle, &efi_obj_list, link) {
struct efi_handler *handler;
- struct efi_device_path *obj_dp;
+ struct efi_device_path *dp_current;
+ efi_uintn_t len_current;
efi_status_t ret;
- ret = efi_search_protocol(efiobj,
- &efi_guid_device_path, &handler);
+ if (guid) {
+ ret = efi_search_protocol(handle, guid, &handler);
+ if (ret != EFI_SUCCESS)
+ continue;
+ }
+ ret = efi_search_protocol(handle, &efi_guid_device_path,
+ &handler);
if (ret != EFI_SUCCESS)
continue;
- obj_dp = handler->protocol_interface;
-
- do {
- if (efi_dp_match(dp, obj_dp) == 0) {
- if (rem) {
- /*
- * Allow partial matches, but inform
- * the caller.
- */
- *rem = ((void *)dp) +
- efi_dp_instance_size(obj_dp);
- return efiobj;
- } else {
- /* Only return on exact matches */
- if (efi_dp_instance_size(obj_dp) ==
- dp_size)
- return efiobj;
- }
- }
-
- obj_dp = shorten_path(efi_dp_next(obj_dp));
- } while (short_path && obj_dp);
+ dp_current = handler->protocol_interface;
+ if (short_path) {
+ dp_current = efi_dp_shorten(dp_current);
+ if (!dp_current)
+ continue;
+ }
+ len_current = efi_dp_instance_size(dp_current);
+ if (rem) {
+ if (len_current > len)
+ continue;
+ } else {
+ if (len_current != len)
+ continue;
+ }
+ if (memcmp(dp_current, dp, len_current))
+ continue;
+ if (!rem)
+ return handle;
+ if (len_current > best_len) {
+ best_len = len_current;
+ best_handle = handle;
+ *rem = (void*)((u8 *)dp + len_current);
+ }
}
-
- return NULL;
+ return best_handle;
}
-/*
- * Find an efiobj from device-path, if 'rem' is not NULL, returns the
- * remaining part of the device path after the matched object.
+/**
+ * efi_dp_find_obj() - find handle by device path
+ *
+ * If @rem is provided, the handle with the longest partial match is returned.
+ *
+ * @dp: device path to search
+ * @guid: GUID of protocol that must be installed on path or NULL
+ * @rem: pointer to receive remaining device path
+ * Return: matching handle
*/
-struct efi_object *efi_dp_find_obj(struct efi_device_path *dp,
- struct efi_device_path **rem)
+efi_handle_t efi_dp_find_obj(struct efi_device_path *dp,
+ const efi_guid_t *guid,
+ struct efi_device_path **rem)
{
- struct efi_object *efiobj;
-
- /* Search for an exact match first */
- efiobj = find_obj(dp, false, NULL);
-
- /* Then for a fuzzy match */
- if (!efiobj)
- efiobj = find_obj(dp, false, rem);
+ efi_handle_t handle;
- /* And now for a fuzzy short match */
- if (!efiobj)
- efiobj = find_obj(dp, true, rem);
+ handle = find_handle(dp, guid, false, rem);
+ if (!handle)
+ /* Match short form device path */
+ handle = find_handle(dp, guid, true, rem);
- return efiobj;
+ return handle;
}
/*
efi_free_pool(file_path);
/* Get the EFI object for the partition */
- efiobj = efi_dp_find_obj(device_path, NULL);
+ efiobj = efi_dp_find_obj(device_path, NULL, NULL);
efi_free_pool(device_path);
if (!efiobj)
return NULL;
return EFI_SUCCESS;
}
-
-/**
- * efi_disk_is_system_part() - check if handle refers to an EFI system partition
- *
- * @handle: handle of partition
- *
- * Return: true if handle refers to an EFI system partition
- */
-bool efi_disk_is_system_part(efi_handle_t handle)
-{
- struct efi_handler *handler;
- struct efi_disk_obj *diskobj;
- struct disk_partition info;
- efi_status_t ret;
- int r;
-
- /* check if this is a block device */
- ret = efi_search_protocol(handle, &efi_block_io_guid, &handler);
- if (ret != EFI_SUCCESS)
- return false;
-
- diskobj = container_of(handle, struct efi_disk_obj, header);
-
- r = part_get_info(diskobj->desc, diskobj->part, &info);
- if (r)
- return false;
-
- return !!(info.bootable & PART_EFI_SYSTEM_PARTITION);
-}
efi_uintn_t name_size;
efi_uintn_t tmp_dsize;
u8 *comm_buf = NULL;
- efi_status_t ret;
+ efi_status_t ret, tmp;
if (!variable_name || !vendor || !data_size) {
ret = EFI_INVALID_PARAMETER;
/* Communicate */
ret = mm_communicate(comm_buf, payload_size);
- if (ret == EFI_SUCCESS || ret == EFI_BUFFER_TOO_SMALL) {
- /* Update with reported data size for trimmed case */
- *data_size = var_acc->data_size;
- }
- if (ret != EFI_SUCCESS)
- goto out;
-
- ret = get_property_int(variable_name, name_size, vendor, &var_property);
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS && ret != EFI_BUFFER_TOO_SMALL)
goto out;
+ /* Update with reported data size for trimmed case */
+ *data_size = var_acc->data_size;
+ /*
+ * UEFI > 2.7 needs the attributes set even if the buffer is
+ * smaller
+ */
if (attributes) {
+ tmp = get_property_int(variable_name, name_size, vendor,
+ &var_property);
+ if (tmp != EFI_SUCCESS) {
+ ret = tmp;
+ goto out;
+ }
*attributes = var_acc->attr;
- if (var_property.property & VAR_CHECK_VARIABLE_PROPERTY_READ_ONLY)
+ if (var_property.property &
+ VAR_CHECK_VARIABLE_PROPERTY_READ_ONLY)
*attributes |= EFI_VARIABLE_READ_ONLY;
}
+ /* return if ret is EFI_BUFFER_TOO_SMALL */
+ if (ret != EFI_SUCCESS)
+ goto out;
+
if (data)
memcpy(data, (u8 *)var_acc->name + var_acc->name_size,
var_acc->data_size);
*
* initrddump.efi saves the initial RAM disk provided via the
* EFI_LOAD_FILE2_PROTOCOL.
+ *
+ * Specifying 'nocolor' as load option data suppresses colored output and
+ * clearing of the screen.
*/
#include <common.h>
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
static const efi_guid_t load_file2_guid = EFI_LOAD_FILE2_PROTOCOL_GUID;
static efi_handle_t handle;
+static bool nocolor;
/*
* Device path defined by Linux to identify the handle providing the
};
/**
+ * color() - set foreground color
+ *
+ * @color: foreground color
+ */
+static void color(u8 color)
+{
+ if (!nocolor)
+ cout->set_attribute(cout, color | EFI_BACKGROUND_BLACK);
+}
+
+/**
* print() - print string
*
* @string: text
}
/**
+ * cls() - clear screen
+ */
+static void cls(void)
+{
+ if (nocolor)
+ print(u"\r\n");
+ else
+ cout->clear_screen(cout);
+}
+
+/**
* error() - print error string
*
* @string: error text
*/
static void error(u16 *string)
{
- cout->set_attribute(cout, EFI_LIGHTRED | EFI_BACKGROUND_BLACK);
+ color(EFI_LIGHTRED);
print(string);
- cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
+ color(EFI_LIGHTBLUE);
}
/*
}
/**
+ * efi_drain_input() - drain console input
+ */
+static void efi_drain_input(void)
+{
+ cin->reset(cin, true);
+}
+
+/**
* efi_input_yn() - get answer to yes/no question
*
* Return:
efi_uintn_t index;
efi_status_t ret;
- /* Drain the console input */
- ret = cin->reset(cin, true);
for (;;) {
ret = bs->wait_for_event(1, &cin->wait_for_key, &index);
if (ret != EFI_SUCCESS)
u16 outbuf[2] = u" ";
efi_status_t ret;
- /* Drain the console input */
- ret = cin->reset(cin, true);
*buffer = 0;
for (;;) {
ret = bs->wait_for_event(1, &cin->wait_for_key, &index);
*
* @string: string to search for keyword
* @keyword: keyword to be searched
- * Return: true fi @string starts with the keyword
+ * Return: true if @string starts with the keyword
*/
static bool starts_with(u16 *string, u16 *keyword)
{
+ if (!string || !keyword)
+ return false;
+
for (; *keyword; ++string, ++keyword) {
if (*string != *keyword)
return false;
ret = root->open(root, &file, filename, EFI_FILE_MODE_READ, 0);
if (ret == EFI_SUCCESS) {
file->close(file);
+ efi_drain_input();
print(u"Overwrite existing file (y/n)? ");
ret = efi_input_yn();
print(u"\r\n");
}
/**
+ * get_load_options() - get load options
+ *
+ * Return: load options or NULL
+ */
+u16 *get_load_options(void)
+{
+ efi_status_t ret;
+ struct efi_loaded_image *loaded_image;
+
+ ret = bs->open_protocol(handle, &loaded_image_guid,
+ (void **)&loaded_image, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ error(u"Loaded image protocol not found\r\n");
+ return NULL;
+ }
+
+ if (!loaded_image->load_options_size || !loaded_image->load_options)
+ return NULL;
+
+ return loaded_image->load_options;
+}
+
+/**
* efi_main() - entry point of the EFI application.
*
* @handle: handle of the loaded image
efi_status_t EFIAPI efi_main(efi_handle_t image_handle,
struct efi_system_table *systab)
{
+ u16 *load_options;
+
handle = image_handle;
systable = systab;
cerr = systable->std_err;
cout = systable->con_out;
cin = systable->con_in;
bs = systable->boottime;
+ load_options = get_load_options();
- cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
- cout->clear_screen(cout);
- cout->set_attribute(cout, EFI_WHITE | EFI_BACKGROUND_BLACK);
- print(u"INITRD Dump\r\n========\r\n\r\n");
- cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
+ if (starts_with(load_options, u"nocolor"))
+ nocolor = true;
+
+ color(EFI_WHITE);
+ cls();
+ print(u"INITRD Dump\r\n===========\r\n\r\n");
+ color(EFI_LIGHTBLUE);
for (;;) {
u16 command[BUFFER_SIZE];
u16 *pos;
efi_uintn_t ret;
+ efi_drain_input();
print(u"=> ");
ret = efi_input(command, sizeof(command));
if (ret == EFI_ABORTED)
do_help();
}
- cout->set_attribute(cout, EFI_LIGHTGRAY | EFI_BACKGROUND_BLACK);
- cout->clear_screen(cout);
+ color(EFI_LIGHTGRAY);
+ cls();
+
return EFI_SUCCESS;
}
asflags-y += -DHOST_ARCH="$(HOST_ARCH)"
ccflags-y += -DHOST_ARCH="$(HOST_ARCH)"
-CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding
-CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI)
CFLAGS_efi_selftest_miniapp_exception.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_efi_selftest_miniapp_exception.o := $(CFLAGS_NON_EFI)
CFLAGS_efi_selftest_miniapp_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI)
CFLAGS_efi_selftest_miniapp_return.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_efi_selftest_miniapp_return.o := $(CFLAGS_NON_EFI)
-CFLAGS_initrddump_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
-CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI)
obj-y += \
efi_selftest.o \
efi_selftest_miniapp_exit.efi \
efi_selftest_miniapp_return.efi
-ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
-always += dtbdump.efi
-endif
-
-ifdef CONFIG_EFI_LOAD_FILE2_INITRD
-always += initrddump.efi
-endif
-
$(obj)/efi_miniapp_file_image_exception.h: $(obj)/efi_selftest_miniapp_exception.efi
$(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exception.efi > \
$(obj)/efi_miniapp_file_image_exception.h
/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
#include <div64.h>
#include <dm/test.h>
-#include <kendryte/pll.h>
+#include <k210/pll.h>
#include <test/ut.h>
static int dm_test_k210_pll_calc_config(u32 rate, u32 rate_in,
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+"""Fixture for UEFI bootmanager test
+"""
+
+import os
+import pytest
+import shutil
+from subprocess import call, check_call
+
+@pytest.fixture(scope='session')
+def efi_bootmgr_data(u_boot_config):
+ """Set up a file system to be used in UEFI bootmanager
+ tests
+
+ Args:
+ u_boot_config: U-boot configuration.
+
+ Return:
+ A path to disk image to be used for testing
+ """
+ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_bootmgr'
+ image_path = u_boot_config.persistent_data_dir + '/efi_bootmgr.img'
+
+ shutil.rmtree(mnt_point, ignore_errors=True)
+ os.mkdir(mnt_point, mode = 0o755)
+
+ with open(mnt_point + '/initrd-1.img', 'w', encoding = 'ascii') as file:
+ file.write("initrd 1")
+
+ with open(mnt_point + '/initrd-2.img', 'w', encoding = 'ascii') as file:
+ file.write("initrd 2")
+
+ shutil.copyfile(u_boot_config.build_dir + '/lib/efi_loader/initrddump.efi',
+ mnt_point + '/initrddump.efi')
+
+ check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat {} {}'
+ .format(mnt_point, image_path), shell=True)
+
+ print(image_path)
+
+ yield image_path
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+import pytest
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_efidebug')
+@pytest.mark.buildconfigspec('cmd_bootefi_bootmgr')
+def test_efi_bootmgr(u_boot_console, efi_bootmgr_data):
+ u_boot_console.run_command(cmd = 'host bind 0 {}'.format(efi_bootmgr_data))
+
+ u_boot_console.run_command(cmd = 'efidebug boot add ' \
+ '-b 0001 label-1 host 0:1 initrddump.efi ' \
+ '-i host 0:1 initrd-1.img -s nocolor')
+ u_boot_console.run_command(cmd = 'efidebug boot dump')
+ u_boot_console.run_command(cmd = 'efidebug boot order 0001')
+ u_boot_console.run_command(cmd = 'bootefi bootmgr')
+ response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ assert 'crc32: 0x181464af' in response
+ u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+
+ u_boot_console.run_command(cmd = 'efidebug boot add ' \
+ '-B 0002 label-2 host 0:1 initrddump.efi ' \
+ '-I host 0:1 initrd-2.img -s nocolor')
+ u_boot_console.run_command(cmd = 'efidebug boot dump')
+ u_boot_console.run_command(cmd = 'efidebug boot order 0002')
+ u_boot_console.run_command(cmd = 'bootefi bootmgr')
+ response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ assert 'crc32: 0x811d3515' in response
+ u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+
+ u_boot_console.run_command(cmd = 'efidebug boot rm 0001')
+ u_boot_console.run_command(cmd = 'efidebug boot rm 0002')
This board does not use CONFIG_DM. CONFIG_DM will be
compulsory starting with the v2020.01 release.
Failure to update may result in board removal.
-See doc/driver-model/migration.rst for more info.
+See doc/develop/driver-model/migration.rst for more info.
====================================================
'''
projects / platform / kernel / u-boot.git / commitdiff