#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16
#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
-/* Peripherals registers */
-#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2))
-
-#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50)
-#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51)
-
-#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
-#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
-#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
-#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
-#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
-#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
-#define AXG_ETH_REG_0_CLK_EN BIT(12)
-
-/* HIU registers */
-#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2))
-
-#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
-
#endif /* __AXG_H__ */
#ifndef __MESON_ETH_H__
#define __MESON_ETH_H__
-#include <phy.h>
-
-enum {
- /* Use Internal RMII PHY */
- MESON_USE_INTERNAL_RMII_PHY = 1,
-};
-
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags);
-
/* Generate an unique MAC address based on the HW serial */
int meson_generate_serial_ethaddr(void);
#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
-/* Peripherals registers */
-#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
-
-#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
-#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
-
-#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
-#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
-#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
-#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
-#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
-#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
-#define G12A_ETH_REG_0_CLK_EN BIT(12)
-
-#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
-#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
-#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
-#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
-#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
-#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
-#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
-#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
-#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
-#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
-#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
-#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
-
-/* HIU registers */
-#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
-
-#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
-
#endif /* __G12A_H__ */
#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
-#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50)
-#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51)
-#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56)
-#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57)
-
-#define GX_ETH_REG_0_PHY_INTF BIT(0)
-#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
-#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
-#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
-#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
-#define GX_ETH_REG_0_CLK_EN BIT(12)
-
-/* HIU registers */
-#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2))
-
-#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
-
#endif /* __GX_H__ */
struct mm_region *mem_map = axg_mem_map;
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags)
-{
- switch (mode) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- /* Set RGMII mode */
- setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
- AXG_ETH_REG_0_TX_PHASE(1) |
- AXG_ETH_REG_0_TX_RATIO(4) |
- AXG_ETH_REG_0_PHY_CLK_EN |
- AXG_ETH_REG_0_CLK_EN);
- break;
-
- case PHY_INTERFACE_MODE_RMII:
- /* Set RMII mode */
- out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
- AXG_ETH_REG_0_INVERT_RMII_CLK |
- AXG_ETH_REG_0_CLK_EN);
- break;
-
- default:
- printf("Invalid Ethernet interface mode\n");
- return;
- }
-
- /* Enable power gate */
- clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
-}
-
#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
static struct dwc2_plat_otg_data meson_gx_dwc2_data;
struct mm_region *mem_map = g12a_mem_map;
-static void g12a_enable_external_mdio(void)
-{
- writel(0x0, ETH_PHY_CNTL2);
-}
-
-static void g12a_enable_internal_mdio(void)
-{
- /* Fire up the PHY PLL */
- writel(0x29c0040a, ETH_PLL_CNTL0);
- writel(0x927e0000, ETH_PLL_CNTL1);
- writel(0xac5f49e5, ETH_PLL_CNTL2);
- writel(0x00000000, ETH_PLL_CNTL3);
- writel(0x00000000, ETH_PLL_CNTL4);
- writel(0x20200000, ETH_PLL_CNTL5);
- writel(0x0000c002, ETH_PLL_CNTL6);
- writel(0x00000023, ETH_PLL_CNTL7);
- writel(0x39c0040a, ETH_PLL_CNTL0);
- writel(0x19c0040a, ETH_PLL_CNTL0);
-
- /* Select the internal MDIO */
- writel(0x33000180, ETH_PHY_CNTL0);
- writel(0x00074043, ETH_PHY_CNTL1);
- writel(0x00000260, ETH_PHY_CNTL2);
-}
-
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags)
-{
- switch (mode) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- /* Set RGMII mode */
- setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
- G12A_ETH_REG_0_TX_PHASE(1) |
- G12A_ETH_REG_0_TX_RATIO(4) |
- G12A_ETH_REG_0_PHY_CLK_EN |
- G12A_ETH_REG_0_CLK_EN);
- g12a_enable_external_mdio();
- break;
-
- case PHY_INTERFACE_MODE_RMII:
- /* Set RMII mode */
- out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
- G12A_ETH_REG_0_INVERT_RMII_CLK |
- G12A_ETH_REG_0_CLK_EN);
-
- /* Use G12A RMII Internal PHY */
- if (flags & MESON_USE_INTERNAL_RMII_PHY)
- g12a_enable_internal_mdio();
- else
- g12a_enable_external_mdio();
-
- break;
-
- default:
- printf("Invalid Ethernet interface mode\n");
- return;
- }
-
- /* Enable power gate */
- clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
-}
-
#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
struct mm_region *mem_map = gx_mem_map;
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags)
-{
- switch (mode) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- /* Set RGMII mode */
- setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
- GX_ETH_REG_0_TX_PHASE(1) |
- GX_ETH_REG_0_TX_RATIO(4) |
- GX_ETH_REG_0_PHY_CLK_EN |
- GX_ETH_REG_0_CLK_EN);
-
- /* Reset to external PHY */
- if(!IS_ENABLED(CONFIG_MESON_GXBB))
- writel(0x2009087f, GX_ETH_REG_3);
-
- break;
-
- case PHY_INTERFACE_MODE_RMII:
- /* Set RMII mode */
- out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
- GX_ETH_REG_0_CLK_EN);
-
- /* Use GXL RMII Internal PHY (also on GXM) */
- if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
- if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
- writel(0x10110181, GX_ETH_REG_2);
- writel(0xe40908ff, GX_ETH_REG_3);
- } else
- writel(0x2009087f, GX_ETH_REG_3);
- }
-
- break;
-
- default:
- printf("Invalid Ethernet interface mode\n");
- return;
- }
-
- /* Enable power gate */
- clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
-}
-
#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
static struct dwc2_plat_otg_data meson_gx_dwc2_data;
meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
env_set("soc_rev", tmp);
- meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
efuse_mac_addr, EFUSE_MAC_SIZE);
meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
env_set("soc_rev", tmp);
- meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
efuse_mac_addr, EFUSE_MAC_SIZE);
char serial[EFUSE_SN_SIZE];
ssize_t len;
- meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
char serial[EFUSE_SN_SIZE];
ssize_t len;
- meson_eth_init(PHY_INTERFACE_MODE_RMII, 0);
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
char serial[EFUSE_SN_SIZE];
ssize_t len;
- meson_eth_init(PHY_INTERFACE_MODE_RMII,
- MESON_USE_INTERNAL_RMII_PHY);
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
char serial[EFUSE_SN_SIZE];
ssize_t len;
- meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
int misc_init_r(void)
{
- meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
meson_generate_serial_ethaddr();
return 0;
int misc_init_r(void)
{
- meson_eth_init(PHY_INTERFACE_MODE_RMII,
- MESON_USE_INTERNAL_RMII_PHY);
-
meson_generate_serial_ethaddr();
env_set("serial#", "AMLG12ASEI510");
int misc_init_r(void)
{
- meson_eth_init(PHY_INTERFACE_MODE_RMII,
- MESON_USE_INTERNAL_RMII_PHY);
-
meson_generate_serial_ethaddr();
env_set("serial#", "AMLG12ASEI610");
int misc_init_r(void)
{
- meson_eth_init(PHY_INTERFACE_MODE_RMII,
- MESON_USE_INTERNAL_RMII_PHY);
+ meson_generate_serial_ethaddr();
return 0;
}
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
- meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
efuse_mac_addr, EFUSE_MAC_SIZE);
int misc_init_r(void)
{
- meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+ meson_generate_serial_ethaddr();
return 0;
}
U-Boot calls last_stage_init() before the command-line interpreter is
started.
+config MISC_INIT_F
+ bool "Execute pre-relocation misc init"
+ help
+ Enabling this option calls the 'misc_init_f' function in the init
+ sequence just before DRAM is inited.
+
config MISC_INIT_R
bool "Execute Misc Init"
default y if ARCH_KEYSTONE || ARCH_SUNXI || MPC85xx
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
+CONFIG_MISC_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
+CONFIG_MISC_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
+CONFIG_MISC_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
+CONFIG_MISC_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_PHY=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_WDT=y
+CONFIG_WDT_ARMADA_37XX=y
CONFIG_SHA1=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_PHY=y
CONFIG_MESON_GXBB_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_LOG_SYSLOG=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_F=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_LOG_SYSLOG=y
CONFIG_LOG_ERROR_RETURN=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_F=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
-CONFIG_LOG_SYSLOG=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_F=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_TARGET_SANDBOX_SPL=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_F=y
CONFIG_HANDOFF=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
# CONFIG_INPUT is not set
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
# CONFIG_INPUT is not set
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_MISC_INIT_F=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=8
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
The dm_remove_devices_flags() function can be used to remove devices based on
their driver flags.
+
+Error codes
+-----------
+
+Driver model tries to use errors codes in a consistent way, as follows:
+
+\-EAGAIN
+ Try later, e.g. dependencies not ready
+
+\-EINVAL
+ Invalid argument, such as `dev_read_...()` failed or any other
+ devicetree-related access. Also used when a driver method is passed an
+ argument it considers invalid or does not support.
+
+\-EIO
+ Failed to perform an I/O operation. This is used when a local device
+ (i.e. part of the SOC) does not work as expected. Use -EREMOTEIO for
+ failures to talk to a separate device, e.g. over an I2C or SPI
+ channel.
+
+\-ENODEV
+ Do not bind the device. This should not be used to indicate an
+ error probing the device or for any other purpose, lest driver model get
+ confused. Using `-ENODEV` inside a driver method makes no sense, since
+ clearly there is a device.
+
+\-ENOENT
+ Entry or object not found. This is used when a device, file or directory
+ cannot be found (e.g. when looked up by name), It can also indicate a
+ missing devicetree subnode.
+
+\-ENOMEM
+ Out of memory
+
+\-ENOSPC
+ Ran out of space (e.g. in a buffer or limited-size array)
+
+\-ENOSYS
+ Function not implemented. This is returned by uclasses where the driver does
+ not implement a particular method. It can also be returned by drivers when
+ a particular sub-method is not implemented. This is widely checked in the
+ wider code base, where a feature may or may not be compiled into U-Boot. It
+ indicates that the feature is not available, but this is often just normal
+ operation. Please do not use -ENOSUPP. If an incorrect or unknown argument
+ is provided to a method (e.g. an unknown clock ID), return -EINVAL.
+
+\-ENXIO
+ Couldn't find device/address. This is used when a device or address
+ could not be obtained or is not valid. It is often used to indicate a
+ different type of problem, if -ENOENT is already used for something else in
+ the driver.
+
+\-EPERM
+ This is -1 so some older code may use it as a generic error. This indicates
+ that an operation is not permitted, e.g. a security violation or policy
+ constraint. It is returned internally when binding devices before relocation,
+ if the device is not marked for pre-relocation use.
+
+\-EPFNOSUPPORT
+ Missing uclass. This is deliberately an uncommon error code so that it can
+ easily be distinguished. If you see this very early in U-Boot, it means that
+ a device exists with a particular uclass but the uclass does not (mostly
+ likely because it is not compiled in). Enable DEBUG in uclass.c or lists.c
+ to see which uclass ID or driver is causing the problem.
+
+\-EREMOTEIO
+ This indicates an error in talking to a peripheral over a comms link, such
+ as I2C or SPI. It might indicate that the device is not present or is not
+ responding as expected.
+
+\-ETIMEDOUT
+ Hardware access or some other operation has timed out. This is used where
+ there is an expected time of response and that was exceeded by enough of
+ a margin that there is probably something wrong.
+
+
+Less common ones:
+
+\-ECOMM
+ Not widely used, but similar to -EREMOTEIO. Can be useful as a secondary
+ error to distinguish the problem from -EREMOTEIO.
+
+\-EKEYREJECTED
+ Attempt to remove a device which does not match the removal flags. See
+ device_remove().
+
+\-EILSEQ
+ Devicetree read failure, specifically trying to read a string index which
+ does not exist, in a string-listg property
+
+\-ENOEXEC
+ Attempt to use a uclass method on a device not in that uclass. This is
+ seldom checked at present, since it is generally a programming error and a
+ waste of code space. A DEBUG-only check would be useful here.
+
+\-ENODATA
+ Devicetree read error, where a property exists but has no data associated
+ with it
+
+\-EOVERFLOW
+ Devicetree read error, where the property is longer than expected
+
+\-EPROBE_DEFER
+ Attempt to remove a non-vital device when the removal flags indicate that
+ only vital devices should be removed
+
+\-ERANGE
+ Returned by regmap functions when arguments are out of range. This can be
+ useful for disinguishing regmap errors from other errors obtained while
+ probing devices.
+
+Drivers should use the same conventions so that things function as expected.
+In particular, if a driver fails to probe, or a uclass operation fails, the
+error code is the primary way to indicate what actually happened.
+
+Printing error messages in drivers is discouraged due to code size bloat and
+since it can result in messages appearing in normal operation. For example, if
+a command tries two different devices and uses whichever one probes correctly,
+we don't want an error message displayed, even if the command itself might show
+a warning or informational message. Ideally, messages in drivers should only be
+displayed when debugging, e.g. by using log_debug() although in extreme cases
+log_warning() or log_error() may be used.
+
+Error messages can be logged using `log_msg_ret()`, so that enabling
+`CONFIG_LOG` and `CONFIG_LOG_ERROR_RETURN` shows a trace of error codes returned
+through the call stack. That can be a handy way of quickly figuring out where
+an error occurred. Get into the habit of return errors with
+`return log_msg_ret("here", ret)` instead of just `return ret`. The string
+just needs to be long enough to find in a single function, since a log record
+stores (and can print with `CONFIG_LOGF_FUNC`) the function where it was
+generated.
+
+
Data Structures
---------------
clk_free(&clk);
- if (ret == -ENOTSUPP) {
+ if (ret == -EINVAL) {
printf("clk ID %lu not supported yet\n",
aspeed_clk_names[i].id);
continue;
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk *mux = composite->mux;
- if (mux && mux_ops)
- return mux_ops->set_parent(mux, parent);
- else
- return -ENOTSUPP;
+ if (!mux || !mux_ops)
+ return -ENOSYS;
+
+ return mux_ops->set_parent(mux, parent);
}
static unsigned long clk_composite_recalc_rate(struct clk *clk)
if (clk->map[sclk->id].set_rate)
return clk->map[sclk->id].set_rate(sclk, rate);
- return -ENOTSUPP;
+ return -EINVAL;
}
static int hsdk_cgu_disable(struct clk *sclk)
if (clk->map[sclk->id].disable)
return clk->map[sclk->id].disable(sclk);
- return -ENOTSUPP;
+ return -EINVAL;
}
static const struct clk_ops hsdk_cgu_ops = {
__weak int __imx8_clk_enable(struct clk *clk, bool enable)
{
- return -ENOTSUPP;
+ return -EINVAL;
}
static int imx8_clk_disable(struct clk *clk)
clk_free(&clk);
- if (ret == -ENOTSUPP) {
+ if (ret == -EINVAL) {
printf("clk ID %lu not supported yet\n",
imx8_clk_names[i].id);
continue;
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
}
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
}
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
break;
default:
kfree(pll);
- return ERR_PTR(-ENOTSUPP);
+ return ERR_PTR(-EINVAL);
}
pll->base = base;
if (ops->set_parent)
return ops->set_parent(bypass->bypassee, parent);
else
- return -ENOTSUPP;
+ return -EINVAL;
}
/*
* could fix this, but it's Probably Not Worth It (TM).
*/
if (probed)
- return -ENOTSUPP;
+ return -EINVAL;
base = dev_read_addr_ptr(dev_get_parent(dev));
if (!base)
return -EINVAL;
if (!periph_clk->can_gate)
- return -ENOTSUPP;
+ return -EINVAL;
if (enable)
clrbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit);
return old_rate;
if (!periph_clk->can_gate || !periph_clk->dividers)
- return -ENOTSUPP;
+ return -EINVAL;
parent_rate = get_parent_rate(priv, clk->id);
if (parent_rate == -EINVAL)
return -EINVAL;
if (!periph_clk->can_mux || !periph_clk->can_gate)
- return -ENOTSUPP;
+ return -EINVAL;
ret = clk_get_by_index(clk->dev, 0, &check_parent);
if (ret < 0)
path = dev_read_string(dev, "acpi,path");
if (path) {
if (strlen(path) >= maxlen)
- return -E2BIG;
+ return -ENOSPC;
strcpy(out_path, path);
return 0;
}
return ret;
ret = clk_enable_bulk(bulk);
- if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ if (ret && ret != -ENOSYS) {
clk_release_bulk(bulk);
return ret;
}
struct clk_bulk *bulk = dev_get_priv(dev);
ret = clk_release_bulk(bulk);
- if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+ if (ret && ret != -ENOSYS)
return ret;
else
return 0;
{
unsigned int byte_offset = offset * info->portwidth;
- return (void *)(info->start[sect] + byte_offset);
+ return (void *)(info->start[sect] + (byte_offset << info->chip_lsb));
}
static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
sizeof(struct cfi_qry));
info->interface = le16_to_cpu(qry->interface_desc);
+ /* Some flash chips can support multiple bus widths.
+ * In this case, override the interface width and
+ * limit it to the port width.
+ */
+ if ((info->interface == FLASH_CFI_X8X16) &&
+ (info->portwidth == FLASH_CFI_8BIT)) {
+ debug("Overriding 16-bit interface width to"
+ " 8-bit port width\n");
+ info->interface = FLASH_CFI_X8;
+ } else if ((info->interface == FLASH_CFI_X16X32) &&
+ (info->portwidth == FLASH_CFI_16BIT)) {
+ debug("Overriding 16-bit interface width to"
+ " 16-bit port width\n");
+ info->interface = FLASH_CFI_X16;
+ }
info->cfi_offset = flash_offset_cfi[cfi_offset];
debug("device interface is %d\n",
info->interface);
- debug("found port %d chip %d ",
- info->portwidth, info->chipwidth);
+ debug("found port %d chip %d chip_lsb %d ",
+ info->portwidth, info->chipwidth, info->chip_lsb);
debug("port %d bits chip %d bits\n",
info->portwidth << CFI_FLASH_SHIFT_WIDTH,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
for (info->chipwidth = FLASH_CFI_BY8;
info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1)
+ info->chipwidth <<= 1) {
+ /*
+ * First, try detection without shifting the addresses
+ * for 8bit devices (16bit wide connection)
+ */
+ info->chip_lsb = 0;
+ if (__flash_detect_cfi(info, qry))
+ return 1;
+
+ /*
+ * Not detected, so let's try with shifting
+ * for 8bit devices
+ */
+ info->chip_lsb = 1;
if (__flash_detect_cfi(info, qry))
return 1;
+ }
}
debug("not found\n");
return 0;
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
provide the PHY (physical media interface).
+config ETH_DESIGNWARE_MESON8B
+ bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC"
+ depends on DM_ETH
+ select ETH_DESIGNWARE
+ help
+ This provides glue layer to use Synopsys Designware Ethernet MAC
+ present on the Amlogic Meson8b, GX, AXG & G12A SoCs.
+
config ETH_DESIGNWARE_SOCFPGA
select REGMAP
select SYSCON
This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and
on the mEMAC (which supports both Clauses 22 and 45).
+config MDIO_MUX_MMIOREG
+ bool "MDIO MUX accessed as a MMIO register access"
+ depends on DM_MDIO_MUX
+ help
+ This driver is used for MDIO muxes driven by writing to a register in
+ the MMIO physical memory.
+
+config MDIO_MUX_MESON_G12A
+ bool "MDIO MUX for Amlogic Meson G12A SoCs"
+ depends on DM_MDIO_MUX
+ help
+ This driver is used for the MDIO mux found on the Amlogic G12A & compatible
+ SoCs.
+
endif # NETDEVICES
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
+obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
+obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o
+obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o
#include <reset.h>
#include <asm/cache.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
#include <dm/devres.h>
+#include <dm/lists.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/err.h>
}
#endif
+#if IS_ENABLED(CONFIG_DM_MDIO)
+int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+
+ return dw_mdio_read(pdata->mii_bus, addr, devad, reg);
+}
+
+int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+
+ return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
+}
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+int designware_eth_mdio_reset(struct udevice *mdio_dev)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+
+ return dw_mdio_reset(pdata->mii_bus);
+}
+#endif
+
+static const struct mdio_ops designware_eth_mdio_ops = {
+ .read = designware_eth_mdio_read,
+ .write = designware_eth_mdio_write,
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ .reset = designware_eth_mdio_reset,
+#endif
+};
+
+static int designware_eth_mdio_probe(struct udevice *dev)
+{
+ /* Use the priv data of parent */
+ dev_set_priv(dev, dev_get_priv(dev->parent));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(designware_eth_mdio) = {
+ .name = "eth_designware_mdio",
+ .id = UCLASS_MDIO,
+ .probe = designware_eth_mdio_probe,
+ .ops = &designware_eth_mdio_ops,
+ .plat_auto = sizeof(struct mdio_perdev_priv),
+};
+#endif
+
static int dw_mdio_init(const char *name, void *priv)
{
struct mii_dev *bus = mdio_alloc();
return mdio_register(bus);
}
+#if IS_ENABLED(CONFIG_DM_MDIO)
+static int dw_dm_mdio_init(const char *name, void *priv)
+{
+ struct udevice *dev = priv;
+ ofnode node;
+ int ret;
+
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ const char *subnode_name = ofnode_get_name(node);
+ struct udevice *mdiodev;
+
+ if (strcmp(subnode_name, "mdio"))
+ continue;
+
+ ret = device_bind_driver_to_node(dev, "eth_designware_mdio",
+ subnode_name, node, &mdiodev);
+ if (ret)
+ debug("%s: not able to bind mdio device node\n", __func__);
+
+ return 0;
+ }
+
+ printf("%s: mdio node is missing, registering legacy mdio bus", __func__);
+
+ return dw_mdio_init(name, priv);
+}
+#endif
+
static void tx_descs_init(struct dw_eth_dev *priv)
{
struct eth_dma_regs *dma_p = priv->dma_regs_p;
static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
- int phy_addr = -1, ret;
+ int ret;
+
+#if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH)
+ phydev = dm_eth_phy_connect(dev);
+ if (!phydev)
+ return -ENODEV;
+#else
+ int phy_addr = -1;
#ifdef CONFIG_PHY_ADDR
phy_addr = CONFIG_PHY_ADDR;
phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
+#endif
phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
priv->interface = pdata->phy_interface;
priv->max_speed = pdata->max_speed;
+#if IS_ENABLED(CONFIG_DM_MDIO)
+ ret = dw_dm_mdio_init(dev->name, dev);
+#else
ret = dw_mdio_init(dev->name, dev);
+#endif
if (ret) {
err = ret;
goto mdio_err;
static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "allwinner,sun7i-a20-gmac" },
{ .compatible = "amlogic,meson6-dwmac" },
- { .compatible = "amlogic,meson-gx-dwmac" },
- { .compatible = "amlogic,meson-gxbb-dwmac" },
- { .compatible = "amlogic,meson-axg-dwmac" },
{ .compatible = "st,stm32-dwmac" },
{ .compatible = "snps,arc-dwmac-3.70a" },
{ }
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 BayLibre, SAS
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <phy.h>
+#include "designware.h"
+#include <dm/device_compat.h>
+#include <linux/err.h>
+
+#define ETH_REG_0 0x0
+#define ETH_REG_1 0x4
+#define ETH_REG_2 0x18
+#define ETH_REG_3 0x1c
+
+#define GX_ETH_REG_0_PHY_INTF BIT(0)
+#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
+#define GX_ETH_REG_0_CLK_EN BIT(12)
+
+#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
+#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
+#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
+#define AXG_ETH_REG_0_CLK_EN BIT(12)
+
+struct dwmac_meson8b_plat {
+ struct dw_eth_pdata dw_eth_pdata;
+ int (*dwmac_setup)(struct udevice *dev, struct eth_pdata *edata);
+ void *regs;
+};
+
+static int dwmac_meson8b_of_to_plat(struct udevice *dev)
+{
+ struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
+
+ pdata->regs = (void *)dev_read_addr_index(dev, 1);
+ if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ pdata->dwmac_setup = (void *)dev_get_driver_data(dev);
+ if (!pdata->dwmac_setup)
+ return -EINVAL;
+
+ return designware_eth_of_to_plat(dev);
+}
+
+static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata)
+{
+ struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
+
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set RGMII mode */
+ setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
+ AXG_ETH_REG_0_TX_PHASE(1) |
+ AXG_ETH_REG_0_TX_RATIO(4) |
+ AXG_ETH_REG_0_PHY_CLK_EN |
+ AXG_ETH_REG_0_CLK_EN);
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ /* Set RMII mode */
+ out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
+ AXG_ETH_REG_0_INVERT_RMII_CLK |
+ AXG_ETH_REG_0_CLK_EN);
+ break;
+ default:
+ dev_err(dev, "Unsupported PHY mode\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata)
+{
+ struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
+
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set RGMII mode */
+ setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
+ GX_ETH_REG_0_TX_PHASE(1) |
+ GX_ETH_REG_0_TX_RATIO(4) |
+ GX_ETH_REG_0_PHY_CLK_EN |
+ GX_ETH_REG_0_CLK_EN);
+
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ /* Set RMII mode */
+ out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
+ GX_ETH_REG_0_CLK_EN);
+
+ if (!IS_ENABLED(CONFIG_MESON_GXBB))
+ writel(0x10110181, plat->regs + ETH_REG_2);
+
+ break;
+ default:
+ dev_err(dev, "Unsupported PHY mode\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int dwmac_meson8b_probe(struct udevice *dev)
+{
+ struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
+ struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
+ int ret;
+
+ ret = pdata->dwmac_setup(dev, edata);
+ if (ret)
+ return ret;
+
+ return designware_eth_probe(dev);
+}
+
+static const struct udevice_id dwmac_meson8b_ids[] = {
+ { .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx },
+ { .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg },
+ { }
+};
+
+U_BOOT_DRIVER(dwmac_meson8b) = {
+ .name = "dwmac_meson8b",
+ .id = UCLASS_ETH,
+ .of_match = dwmac_meson8b_ids,
+ .of_to_plat = dwmac_meson8b_of_to_plat,
+ .probe = dwmac_meson8b_probe,
+ .ops = &designware_eth_ops,
+ .priv_auto = sizeof(struct dw_eth_dev),
+ .plat_auto = sizeof(struct dwmac_meson8b_plat),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+
+#define ETH_PLL_STS 0x40
+#define ETH_PLL_CTL0 0x44
+#define PLL_CTL0_LOCK_DIG BIT(30)
+#define PLL_CTL0_RST BIT(29)
+#define PLL_CTL0_EN BIT(28)
+#define PLL_CTL0_SEL BIT(23)
+#define PLL_CTL0_N GENMASK(14, 10)
+#define PLL_CTL0_M GENMASK(8, 0)
+#define PLL_LOCK_TIMEOUT 1000000
+#define PLL_MUX_NUM_PARENT 2
+#define ETH_PLL_CTL1 0x48
+#define ETH_PLL_CTL2 0x4c
+#define ETH_PLL_CTL3 0x50
+#define ETH_PLL_CTL4 0x54
+#define ETH_PLL_CTL5 0x58
+#define ETH_PLL_CTL6 0x5c
+#define ETH_PLL_CTL7 0x60
+
+#define ETH_PHY_CNTL0 0x80
+#define EPHY_G12A_ID 0x33010180
+#define ETH_PHY_CNTL1 0x84
+#define PHY_CNTL1_ST_MODE GENMASK(2, 0)
+#define PHY_CNTL1_ST_PHYADD GENMASK(7, 3)
+#define EPHY_DFLT_ADD 8
+#define PHY_CNTL1_MII_MODE GENMASK(15, 14)
+#define EPHY_MODE_RMII 0x1
+#define PHY_CNTL1_CLK_EN BIT(16)
+#define PHY_CNTL1_CLKFREQ BIT(17)
+#define PHY_CNTL1_PHY_ENB BIT(18)
+#define ETH_PHY_CNTL2 0x88
+#define PHY_CNTL2_USE_INTERNAL BIT(5)
+#define PHY_CNTL2_SMI_SRC_MAC BIT(6)
+#define PHY_CNTL2_RX_CLK_EPHY BIT(9)
+
+#define MESON_G12A_MDIO_EXTERNAL_ID 0
+#define MESON_G12A_MDIO_INTERNAL_ID 1
+
+struct mdio_mux_meson_g12a_priv {
+ struct udevice *chip;
+ phys_addr_t phys;
+};
+
+static int meson_g12a_ephy_pll_init(struct mdio_mux_meson_g12a_priv *priv)
+{
+ /* Fire up the PHY PLL */
+ writel(0x29c0040a, priv->phys + ETH_PLL_CTL0);
+ writel(0x927e0000, priv->phys + ETH_PLL_CTL1);
+ writel(0xac5f49e5, priv->phys + ETH_PLL_CTL2);
+ writel(0x00000000, priv->phys + ETH_PLL_CTL3);
+ writel(0x00000000, priv->phys + ETH_PLL_CTL4);
+ writel(0x20200000, priv->phys + ETH_PLL_CTL5);
+ writel(0x0000c002, priv->phys + ETH_PLL_CTL6);
+ writel(0x00000023, priv->phys + ETH_PLL_CTL7);
+ writel(0x39c0040a, priv->phys + ETH_PLL_CTL0);
+ writel(0x19c0040a, priv->phys + ETH_PLL_CTL0);
+
+ return 0;
+}
+
+static int meson_g12a_enable_internal_mdio(struct mdio_mux_meson_g12a_priv *priv)
+{
+ /* Initialize ephy control */
+ writel(EPHY_G12A_ID, priv->phys + ETH_PHY_CNTL0);
+ writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
+ FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
+ FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
+ PHY_CNTL1_CLK_EN |
+ PHY_CNTL1_CLKFREQ |
+ PHY_CNTL1_PHY_ENB,
+ priv->phys + ETH_PHY_CNTL1);
+ writel(PHY_CNTL2_USE_INTERNAL |
+ PHY_CNTL2_SMI_SRC_MAC |
+ PHY_CNTL2_RX_CLK_EPHY,
+ priv->phys + ETH_PHY_CNTL2);
+
+ return 0;
+}
+
+static int meson_g12a_enable_external_mdio(struct mdio_mux_meson_g12a_priv *priv)
+{
+ /* Reset the mdio bus mux */
+ writel(0x0, priv->phys + ETH_PHY_CNTL2);
+
+ return 0;
+}
+
+static int mdio_mux_meson_g12a_select(struct udevice *mux, int cur, int sel)
+{
+ struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(mux);
+
+ debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
+
+ /* if last selection didn't change we're good to go */
+ if (cur == sel)
+ return 0;
+
+ switch (sel) {
+ case MESON_G12A_MDIO_EXTERNAL_ID:
+ return meson_g12a_enable_external_mdio(priv);
+ case MESON_G12A_MDIO_INTERNAL_ID:
+ return meson_g12a_enable_internal_mdio(priv);
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_meson_g12a_ops = {
+ .select = mdio_mux_meson_g12a_select,
+};
+
+static int mdio_mux_meson_g12a_probe(struct udevice *dev)
+{
+ struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(dev);
+
+ priv->phys = dev_read_addr(dev);
+
+ meson_g12a_ephy_pll_init(priv);
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_meson_g12a_ids[] = {
+ { .compatible = "amlogic,g12a-mdio-mux" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_meson_g12a) = {
+ .name = "mdio_mux_meson_g12a",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_meson_g12a_ids,
+ .probe = mdio_mux_meson_g12a_probe,
+ .ops = &mdio_mux_meson_g12a_ops,
+ .priv_auto = sizeof(struct mdio_mux_meson_g12a_priv),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Based on linux/drivers/net/phy/mdio-mux-mmioreg.c :
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <miiphy.h>
+#include <linux/io.h>
+
+struct mdio_mux_mmioreg_priv {
+ struct udevice *chip;
+ phys_addr_t phys;
+ unsigned int iosize;
+ unsigned int mask;
+};
+
+static int mdio_mux_mmioreg_select(struct udevice *mux, int cur, int sel)
+{
+ struct mdio_mux_mmioreg_priv *priv = dev_get_priv(mux);
+
+ debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
+
+ /* if last selection didn't change we're good to go */
+ if (cur == sel)
+ return 0;
+
+ switch (priv->iosize) {
+ case sizeof(u8): {
+ u8 x, y;
+
+ x = ioread8((void *)priv->phys);
+ y = (x & ~priv->mask) | (u32)sel;
+ if (x != y) {
+ iowrite8((x & ~priv->mask) | sel, (void *)priv->phys);
+ debug("%s: %02x -> %02x\n", __func__, x, y);
+ }
+
+ break;
+ }
+ case sizeof(u16): {
+ u16 x, y;
+
+ x = ioread16((void *)priv->phys);
+ y = (x & ~priv->mask) | (u32)sel;
+ if (x != y) {
+ iowrite16((x & ~priv->mask) | sel, (void *)priv->phys);
+ debug("%s: %04x -> %04x\n", __func__, x, y);
+ }
+
+ break;
+ }
+ case sizeof(u32): {
+ u32 x, y;
+
+ x = ioread32((void *)priv->phys);
+ y = (x & ~priv->mask) | (u32)sel;
+ if (x != y) {
+ iowrite32((x & ~priv->mask) | sel, (void *)priv->phys);
+ debug("%s: %08x -> %08x\n", __func__, x, y);
+ }
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_mmioreg_ops = {
+ .select = mdio_mux_mmioreg_select,
+};
+
+static int mdio_mux_mmioreg_probe(struct udevice *dev)
+{
+ struct mdio_mux_mmioreg_priv *priv = dev_get_priv(dev);
+ phys_addr_t reg_base, reg_size;
+ u32 reg_mask;
+ int err;
+
+ reg_base = ofnode_get_addr_size_index(dev_ofnode(dev), 0, ®_size);
+ if (reg_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ if (reg_size != sizeof(u8) &&
+ reg_size != sizeof(u16) &&
+ reg_size != sizeof(u32)) {
+ printf("%s: only 8/16/32-bit registers are supported\n", __func__);
+ return -EINVAL;
+ }
+
+ err = dev_read_u32(dev, "mux-mask", ®_mask);
+ if (err) {
+ debug("%s: error reading mux-mask property\n", __func__);
+ return err;
+ }
+
+ if (reg_mask >= BIT(reg_size * 8)) {
+ printf("%s: mask doesn't fix in register width\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->phys = reg_base;
+ priv->iosize = reg_size;
+ priv->mask = reg_mask;
+
+ debug("%s: %llx@%lld / %x\n", __func__, reg_base, reg_size, reg_mask);
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_mmioreg_ids[] = {
+ { .compatible = "mdio-mux-mmioreg" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_mmioreg) = {
+ .name = "mdio_mux_mmioreg",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_mmioreg_ids,
+ .probe = mdio_mux_mmioreg_probe,
+ .ops = &mdio_mux_mmioreg_ops,
+ .priv_auto = sizeof(struct mdio_mux_mmioreg_priv),
+};
return ret;
ops = pinctrl_get_ops(pctldev);
- if (!ops || !ops->gpio_request_enable)
- return -ENOTSUPP;
+ assert(ops);
+ if (!ops->gpio_request_enable)
+ return -ENOSYS;
return ops->gpio_request_enable(pctldev, pin_selector);
}
return ret;
ops = pinctrl_get_ops(pctldev);
- if (!ops || !ops->gpio_disable_free)
- return -ENOTSUPP;
+ assert(ops);
+ if (!ops->gpio_disable_free)
+ return -ENOSYS;
return ops->gpio_disable_free(pctldev, pin_selector);
}
dev_array[index] = NULL;
return ret;
#else
- return -ENOTSUPP;
+ return -ENOSYS;
#endif
}
this option if you want to service enabled watchdog by U-Boot. Disable
this option if you want U-Boot to start watchdog but never service it.
+config WATCHDOG_AUTOSTART
+ bool "Automatically start watchdog timer"
+ depends on WDT
+ default y
+ help
+ Automatically start watchdog timer and start servicing it during
+ init phase. Enabled by default. Disable this option if you want
+ to compile U-Boot with CONFIG_WDT support but do not want to
+ activate watchdog, like when CONFIG_WDT option is disabled. You
+ would be able to start watchdog manually by 'wdt' command. Useful
+ when you want to have support for 'wdt' command but do not want
+ to have watchdog enabled by default.
+
config WATCHDOG_TIMEOUT_MSECS
int "Watchdog timeout in msec"
default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6
int initr_watchdog(void)
{
u32 timeout = WATCHDOG_TIMEOUT_SECS;
+ int ret;
/*
* Init watchdog: This will call the probe function of the
4 * reset_period) / 4;
}
- wdt_start(gd->watchdog_dev, timeout * 1000, 0);
- gd->flags |= GD_FLG_WDT_READY;
+ if (!CONFIG_IS_ENABLED(WATCHDOG_AUTOSTART)) {
+ printf("WDT: Not starting\n");
+ return 0;
+ }
+
+ ret = wdt_start(gd->watchdog_dev, timeout * 1000, 0);
+ if (ret != 0) {
+ printf("WDT: Failed to start\n");
+ return 0;
+ }
+
printf("WDT: Started with%s servicing (%ds timeout)\n",
IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout);
int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
const struct wdt_ops *ops = device_get_ops(dev);
+ int ret;
if (!ops->start)
return -ENOSYS;
- return ops->start(dev, timeout_ms, flags);
+ ret = ops->start(dev, timeout_ms, flags);
+ if (ret == 0)
+ gd->flags |= GD_FLG_WDT_READY;
+
+ return ret;
}
int wdt_stop(struct udevice *dev)
{
const struct wdt_ops *ops = device_get_ops(dev);
+ int ret;
if (!ops->stop)
return -ENOSYS;
- return ops->stop(dev);
+ ret = ops->stop(dev);
+ if (ret == 0)
+ gd->flags &= ~GD_FLG_WDT_READY;
+
+ return ret;
}
int wdt_reset(struct udevice *dev)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MISC_INIT_F
-
/*
* On-board devices
*/
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
-#define CONFIG_MISC_INIT_F
-
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_MISC_INIT_F
-
#endif
#ifdef CONFIG_SYS_FLASH_CFI
uchar portwidth; /* the width of the port */
uchar chipwidth; /* the width of the chip */
+ uchar chip_lsb; /* extra Least Significant Bit in the */
+ /* address of chip */
ushort buffer_size; /* # of bytes in write buffer */
ulong erase_blk_tout; /* maximum block erase timeout */
ulong write_tout; /* maximum write timeout */
#define _SPL_BUILD 0
#endif
-#if !_DEBUG && CONFIG_IS_ENABLED(LOG)
+#if CONFIG_IS_ENABLED(LOG)
-#define debug_cond(cond, fmt, args...) \
-({ \
- log(LOG_CATEGORY, LOGL_DEBUG, fmt, ##args); \
+#define debug_cond(cond, fmt, args...) \
+({ \
+ if (cond) \
+ log(LOG_CATEGORY, \
+ (enum log_level_t)(LOGL_FORCE_DEBUG | _LOG_DEBUG), \
+ fmt, ##args); \
})
#else /* _DEBUG */
* This follows the semantics of realloc(), so can perform an os_malloc() or
* os_free() depending on @ptr and @length.
*
- * Return: Pointer to reallocated memory or NULL if @length is 0
+ * @ptr: pointer to previously allocated memory of NULL
+ * @length: number of bytes to allocate
+ * Return: pointer to reallocated memory or NULL if @length is 0
*/
void *os_realloc(void *ptr, size_t length);
const struct spi_mem_op *op,
struct sg_table *sg)
{
- return -ENOTSUPP;
+ return -ENOSYS;
}
static inline void
*/
struct udevice *testbus_get_clear_removed(void);
+static inline void arch_reset_for_test(void)
+{
+#ifdef CONFIG_SANDBOX
+#include <asm/state.h>
+
+ state_reset_for_test(state_get_current());
+#endif
+}
+
#endif /* __TEST_TEST_H */
static inline int read_tlv_eeprom(void *eeprom, int offset, int len, int dev)
{
- return -ENOTSUPP;
+ return -ENOSYS;
}
static inline int write_tlv_eeprom(void *eeprom, int len)
{
- return -ENOTSUPP;
+ return -ENOSYS;
}
static inline int
read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
struct tlvinfo_tlv **first_entry, int dev)
{
- return -ENOTSUPP;
+ return -ENOSYS;
}
#endif /* CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
CONFIG_MIPS_MT_FPAFF
CONFIG_MIRQ_EN
CONFIG_MISC_COMMON
-CONFIG_MISC_INIT_F
CONFIG_MIU_1BIT_INTERLEAVED
CONFIG_MIU_2BIT_21_7_INTERLEAVED
CONFIG_MIU_2BIT_INTERLEAVED
fi
$(obj)/_libfdt.so $(obj)/libfdt.py &: rebuild
+ @:
always += _libfdt.so libfdt.py
#include <common.h>
#include <console.h>
#include <dm.h>
-#include <asm/state.h>
#include <dm/root.h>
#include <dm/test.h>
#include <dm/uclass-internal.h>
uts->force_fail_alloc = false;
uts->skip_post_probe = false;
gd->dm_root = NULL;
- if (!CONFIG_IS_ENABLED(OF_PLATDATA))
+ if (IS_ENABLED(CONFIG_UT_DM) && !CONFIG_IS_ENABLED(OF_PLATDATA))
memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count));
- state_reset_for_test(state_get_current());
+ arch_reset_for_test();
/* Determine whether to make the live tree available */
gd_set_of_root(of_live ? uts->of_root : NULL);
# Write out the image and function size information and an objdump
env = result.toolchain.MakeEnvironment(self.builder.full_path)
- with open(os.path.join(build_dir, 'out-env'), 'w') as fd:
+ with open(os.path.join(build_dir, 'out-env'), 'w',
+ encoding='utf-8') as fd:
for var in sorted(env.keys()):
print('%s="%s"' % (var, env[var]), file=fd)
lines = []
Number of size cells for this node
"""
parent = node.parent
+ if parent and not parent.props:
+ raise ValueError("Parent node '%s' has no properties - do you need u-boot,dm-spl or similar?" %
+ parent.path)
num_addr, num_size = 2, 2
if parent:
addr_prop = parent.props.get('#address-cells')
if reg.type != fdt.Type.INT:
raise ValueError("Node '%s' reg property is not an int" %
node.name)
+ if not isinstance(reg.value, list):
+ reg.value = [reg.value]
if len(reg.value) % total:
raise ValueError(
- "Node '%s' reg property has %d cells "
+ "Node '%s' (parent '%s') reg property has %d cells "
'which is not a multiple of na + ns = %d + %d)' %
- (node.name, len(reg.value), num_addr, num_size))
+ (node.name, node.parent.name, len(reg.value), num_addr,
+ num_size))
reg.num_addr = num_addr
reg.num_size = num_size
- if num_addr != 1 or num_size != 1:
+ if num_addr > 1 or num_size > 1:
reg.type = fdt.Type.INT64
i = 0
new_value = []
val = reg.value
- if not isinstance(val, list):
- val = [val]
while i < len(val):
addr = fdt_util.fdt_cells_to_cpu(val[i:], reg.num_addr)
i += num_addr
raise ValueError('Must specify either output or output_dirs, not both')
if not scan:
- scan = src_scan.Scanner(basedir, warning_disabled, drivers_additional,
- phase)
+ scan = src_scan.Scanner(basedir, drivers_additional, phase)
scan.scan_drivers()
do_process = True
else:
plat.out_header(outfile)
outfile.method(plat)
plat.finish_output()
+
+ if not warning_disabled:
+ scan.show_warnings()
return plat
key: Driver alias declared with
DM_DRIVER_ALIAS(driver_alias, driver_name)
value: Driver name declared with U_BOOT_DRIVER(driver_name)
- _warning_disabled: true to disable warnings about driver names not found
_drivers_additional (list or str): List of additional drivers to use
during scanning
_of_match: Dict holding information about compatible strings
_phase: The phase of U-Boot that we are generating data for, e.g. 'spl'
or 'tpl'. None if not known
"""
- def __init__(self, basedir, warning_disabled, drivers_additional, phase=''):
+ def __init__(self, basedir, drivers_additional, phase=''):
"""Set up a new Scanner
"""
if not basedir:
self._drivers = {}
self._driver_aliases = {}
self._drivers_additional = drivers_additional or []
- self._warning_disabled = warning_disabled
+ self._missing_drivers = set()
self._of_match = {}
self._compat_to_driver = {}
self._uclass = {}
aliases_c.remove(compat_c)
return compat_c, aliases_c
- if not self._warning_disabled:
- print('WARNING: the driver %s was not found in the driver list'
- % (compat_list_c[0]))
+ self._missing_drivers.add(compat_list_c[0])
return compat_list_c[0], compat_list_c[1:]
self._drivers[driver.name] = driver
self._of_match.update(of_match)
+ def show_warnings(self):
+ """Show any warnings that have been collected"""
+ for name in sorted(list(self._missing_drivers)):
+ print('WARNING: the driver %s was not found in the driver list'
+ % name)
+
def scan_driver(self, fname):
"""Scan a driver file to build a list of driver names and aliases
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ i2c@0 {
+ pmic@9 {
+ compatible = "sandbox,pmic";
+ u-boot,dm-pre-reloc;
+ reg = <9>;
+ low-power;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2c@0 {
+ compatible = "sandbox,i2c";
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@9 {
+ compatible = "sandbox,pmic";
+ u-boot,dm-pre-reloc;
+ reg = <9>;
+ low-power;
+
+ gpio {
+ compatible = "sandbox,gpio";
+ };
+ };
+ };
+};
# Disable warnings so that calls to get_normalized_compat_name() will not
# output things.
- saved_scan = src_scan.Scanner(None, True, False)
+ saved_scan = src_scan.Scanner(None, False)
saved_scan.scan_drivers()
def copy_scan():
};
struct dtd_sandbox_pmic {
\tbool\t\tlow_power;
-\tfdt64_t\t\treg[2];
+\tfdt32_t\t\treg[1];
};
struct dtd_sandbox_spl_test {
\tconst char * acpi_name;
*/
static struct dtd_sandbox_pmic dtv_pmic_at_9 = {
\t.low_power\t\t= true,
-\t.reg\t\t\t= {0x9, 0x0},
+\t.reg\t\t\t= {0x9},
};
U_BOOT_DRVINFO(pmic_at_9) = {
\t.name\t\t= "sandbox_pmic",
\t.dtplat = {
\t\t.ping_add\t\t= 0x5,
\t\t.ping_expect\t\t= 0x5,
-\t\t.reg\t\t\t= {0x5, 0x0},
+\t\t.reg\t\t\t= {0x5},
\t},
};
#include <dm/test.h>
with self.assertRaises(ValueError) as exc:
self.run_test(['struct'], dtb_file, output)
self.assertIn(
- "Node 'spl-test' reg property has 3 cells which is not a multiple of na + ns = 1 + 1)",
+ "Node 'spl-test' (parent '/') reg property has 3 cells which is not a multiple of na + ns = 1 + 1)",
str(exc.exception))
def test_add_prop(self):
self.assertEqual(
'Warning: Cannot find header file for struct dm_test_uc_priv',
stdout.getvalue().strip())
+
+ def test_missing_props(self):
+ """Test detection of a parent node with no properties"""
+ dtb_file = get_dtb_file('dtoc_test_noprops.dts', capture_stderr=True)
+ output = tools.GetOutputFilename('output')
+ with self.assertRaises(ValueError) as exc:
+ self.run_test(['struct'], dtb_file, output)
+ self.assertIn("Parent node '/i2c@0' has no properties - do you need",
+ str(exc.exception))
+
+ def test_single_reg(self):
+ """Test detection of a parent node with no properties"""
+ dtb_file = get_dtb_file('dtoc_test_single_reg.dts')
+ output = tools.GetOutputFilename('output')
+ self.run_test(['struct'], dtb_file, output)
def test_simple(self):
"""Simple test of scanning drivers"""
- scan = src_scan.Scanner(None, True, None)
+ scan = src_scan.Scanner(None, None)
scan.scan_drivers()
self.assertIn('sandbox_gpio', scan._drivers)
self.assertIn('sandbox_gpio_alias', scan._driver_aliases)
def test_additional(self):
"""Test with additional drivers to scan"""
scan = src_scan.Scanner(
- None, True,
- [None, '', 'tools/dtoc/test/dtoc_test_scan_drivers.cxx'])
+ None, [None, '', 'tools/dtoc/test/dtoc_test_scan_drivers.cxx'])
scan.scan_drivers()
self.assertIn('sandbox_gpio_alias2', scan._driver_aliases)
self.assertEqual('sandbox_gpio',
with open(driver_fn, 'wb+') as fout:
fout.write(b'\x81')
- scan = src_scan.Scanner(None, True, [driver_fn])
+ scan = src_scan.Scanner(None, [driver_fn])
with test_util.capture_sys_output() as (stdout, _):
scan.scan_drivers()
self.assertRegex(stdout.getvalue(),
# Mock out scan_driver and check that it is called with the
# expected files
with mock.patch.object(src_scan.Scanner, "scan_driver") as mocked:
- scan = src_scan.Scanner(indir, True, None)
+ scan = src_scan.Scanner(indir, None)
scan.scan_drivers()
self.assertEqual(2, len(mocked.mock_calls))
self.assertEqual(mock.call(fname_list[0]),
"""Test scanning of a driver"""
fname = os.path.join(OUR_PATH, '..', '..', 'drivers/i2c/tegra_i2c.c')
buff = tools.ReadFile(fname, False)
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
scan._parse_driver(fname, buff)
self.assertIn('i2c_tegra', scan._drivers)
drv = scan._drivers['i2c_tegra']
# get_normalized_compat_name() uses this to check for root node
node.parent = FakeNode()
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
with test_util.capture_sys_output() as (stdout, _):
name, aliases = scan.get_normalized_compat_name(node)
self.assertEqual('rockchip_rk3288_grf', name)
self.assertEqual([], aliases)
- self.assertEqual(
- 'WARNING: the driver rockchip_rk3288_grf was not found in the driver list',
- stdout.getvalue().strip())
+ self.assertEqual(1, len(scan._missing_drivers))
+ self.assertEqual({'rockchip_rk3288_grf'}, scan._missing_drivers)
+ #'WARNING: the driver rockchip_rk3288_grf was not found in the driver list',
+ #stdout.getvalue().strip())
i2c = 'I2C_UCLASS'
compat = {'rockchip,rk3288-grf': 'ROCKCHIP_SYSCON_GRF',
.of_match = tegra_i2c_ids,
};
'''
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
with self.assertRaises(ValueError) as exc:
scan._parse_driver('file.c', buff)
self.assertIn(
.of_match = of_match_ptr(tegra_i2c_ids),
};
'''
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
scan._parse_driver('file.c', buff)
self.assertIn('i2c_tegra', scan._drivers)
drv = scan._drivers['i2c_tegra']
DM_HEADER(<asm/clk.h>)
};
'''
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
scan._parse_driver('file.c', buff)
self.assertIn('testing', scan._drivers)
drv = scan._drivers['testing']
};
'''
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
scan._parse_uclass_driver('file.c', buff)
self.assertIn('UCLASS_I2C', scan._uclass)
drv = scan._uclass['UCLASS_I2C']
};
'''
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
with self.assertRaises(ValueError) as exc:
scan._parse_uclass_driver('file.c', buff)
self.assertIn("file.c: Cannot parse uclass ID in driver 'i2c'",
uint nmsgs;
};
'''
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
scan._basedir = os.path.join(OUR_PATH, '..', '..')
scan._parse_structs('arch/arm/include/asm/file.h', buff)
self.assertIn('some_struct1', scan._structs)
output = tools.GetOutputFilename('output.h')
tools.WriteFile(output, b'struct this is a test \x81 of bad unicode')
- scan = src_scan.Scanner(None, False, None)
+ scan = src_scan.Scanner(None, None)
with test_util.capture_sys_output() as (stdout, _):
scan.scan_header(output)
self.assertIn('due to unicode error', stdout.getvalue())
.of_match = test_ids,
};
''' % name
- scan = src_scan.Scanner(None, False, None, phase)
+ scan = src_scan.Scanner(None, None, phase)
scan._parse_driver('file1.c', driver1)
self.assertIn(name, scan._drivers)
drv1 = scan._drivers[name]
def test_sequence(self):
"""Test assignment of sequence numnbers"""
- scan = src_scan.Scanner(None, False, None, '')
+ scan = src_scan.Scanner(None, None, '')
node = FakeNode()
uc = src_scan.UclassDriver('UCLASS_I2C')
node.uclass = uc
This tool intends to help this tremendous work.
+Installing
+----------
+
+You may need to install 'python3-asteval' for the 'asteval' module.
Usage
-----
"""
pattern = re.compile(r'^\s*#\s*if.*$\n^\s*#\s*endif.*$\n*', flags=re.M)
with open(header_path) as f:
- data = f.read()
+ try:
+ data = f.read()
+ except UnicodeDecodeError as e:
+ print("Failed on file %s': %s" % (header_path, e))
+ return
new_data = pattern.sub('\n', data)
options: option flags.
"""
with open(header_path) as f:
- lines = f.readlines()
+ try:
+ lines = f.readlines()
+ except UnicodeDecodeError as e:
+ print("Failed on file %s': %s" % (header_path, e))
+ return
matched = []
for i, line in enumerate(lines):
ValueError: Warning is generated with no commit associated
"""
if not self.commit:
- raise ValueError('Warning outside commit: %s' % warn)
- if warn not in self.commit.warn:
+ print('Warning outside commit: %s' % warn)
+ elif warn not in self.commit.warn:
self.commit.warn.append(warn)
def _add_to_series(self, line, name, value):
projects / platform / kernel / u-boot.git / commitdiff