Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u...
authorTom Rini <trini@konsulko.com>
Wed, 16 Mar 2022 16:52:02 +0000 (12:52 -0400)
committerTom Rini <trini@konsulko.com>
Wed, 16 Mar 2022 16:52:02 +0000 (12:52 -0400)
Xilinx changes for v2022.07-rc1

microblaze:
- Add support for reserved memory

xilinx:
- Update FRU code with MAC reading

zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0

zynq:
- Update nand binding

nand:
- Aligned zynq_nand to upstream DT binding

net:
- Add support for ethernet-phy-id

mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs

gpio:
- Add driver for slg7xl45106

firmware:
- Add support for dynamic SD config

power-domain:
- Update zynqmp driver with the latest firmware

video:
- Add skeleton driver for DP and DPDMA

i2c:
- Fix i2c to work with QEMU

pinctrl:
- Add driver for zynqmp pinctrl driver

761 files changed:
.azure-pipelines.yml
.gitlab-ci.yml
.mailmap
MAINTAINERS
Makefile
README
arch/Kconfig
arch/arm/Kconfig
arch/arm/cpu/armv7/ls102xa/Kconfig
arch/arm/cpu/armv7/ls102xa/soc.c
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
arch/arm/cpu/armv8/start.S
arch/arm/dts/Makefile
arch/arm/dts/am33xx.dtsi
arch/arm/dts/am3517-evm-u-boot.dtsi
arch/arm/dts/am3517-evm-ui.dtsi
arch/arm/dts/am3517-evm.dts
arch/arm/dts/am3517-som.dtsi
arch/arm/dts/armada-3720-turris-mox.dts
arch/arm/dts/armada-37xx.dtsi
arch/arm/dts/ast2500.dtsi
arch/arm/dts/bcm6753.dtsi [new file with mode: 0644]
arch/arm/dts/bcm96753ref.dts [new file with mode: 0644]
arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
arch/arm/dts/logicpd-som-lv-baseboard.dtsi
arch/arm/dts/logicpd-som-lv.dtsi
arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
arch/arm/dts/logicpd-torpedo-baseboard.dtsi
arch/arm/dts/logicpd-torpedo-som.dtsi
arch/arm/dts/phytium-pomelo.dts [new file with mode: 0644]
arch/arm/include/asm/io.h
arch/arm/include/asm/macro.h
arch/arm/include/asm/system.h
arch/arm/mach-exynos/Kconfig
arch/arm/mach-exynos/spl_boot.c
arch/arm/mach-imx/imx8/cpu.c
arch/arm/mach-imx/imx8m/soc.c
arch/arm/mach-imx/imx8ulp/soc.c
arch/arm/mach-mvebu/Kconfig
arch/arm/mach-omap2/am33xx/board.c
arch/arm/mach-omap2/hwinit-common.c
arch/arm/mach-omap2/omap3/clock.c
arch/arm/mach-rmobile/lowlevel_init_gen3.S
arch/arm/mach-socfpga/lowlevel_init_soc64.S
arch/arm/mach-sunxi/Kconfig
arch/mips/Kconfig
arch/mips/mach-pic32/cpu.c
arch/nios2/cpu/cpu.c
arch/powerpc/cpu/mpc85xx/Kconfig
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/commproc.c [deleted file]
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/serial_scc.c [deleted file]
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/include/asm/cpm_85xx.h [deleted file]
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/lib/bdinfo.c
arch/powerpc/lib/bootm.c
arch/riscv/cpu/cpu.c
arch/riscv/include/asm/system.h
arch/riscv/lib/spl.c
arch/sandbox/cpu/start.c
arch/sandbox/dts/test.dts
arch/sandbox/include/asm/scmi_test.h
arch/x86/cpu/baytrail/cpu.c
arch/x86/cpu/broadwell/cpu.c
arch/x86/cpu/ivybridge/cpu.c
arch/x86/cpu/quark/quark.c
arch/x86/include/asm/fsp2/fsp_api.h
arch/x86/include/asm/intel_gnvs.h
arch/x86/lib/fsp2/fsp_init.c
arch/x86/lib/spl.c
arch/x86/lib/tpl.c
arch/xtensa/Kconfig
board/advantech/som-db5800-som-6867/.gitignore
board/broadcom/bcm96753ref/Kconfig [new file with mode: 0644]
board/broadcom/bcm96753ref/MAINTAINERS [new file with mode: 0644]
board/broadcom/bcm96753ref/Makefile [new file with mode: 0644]
board/broadcom/bcm96753ref/bcm96753ref.c [new file with mode: 0644]
board/congatec/conga-qeval20-qa3-e3845/.gitignore
board/coreboot/coreboot/MAINTAINERS
board/cortina/presidio-asic/lowlevel_init.S
board/google/Kconfig
board/google/chromebook_coral/coral.c
board/intel/bayleybay/.gitignore
board/intel/edison/.gitignore
board/intel/galileo/.gitignore
board/intel/minnowmax/.gitignore
board/keymile/kmcent2/kmcent2.c
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
board/logicpd/am3517evm/am3517evm.c
board/logicpd/am3517evm/am3517evm.h
board/logicpd/omap3som/omap3logic.h
board/phytium/pomelo/Kconfig [new file with mode: 0644]
board/phytium/pomelo/MAINTAINERS [new file with mode: 0644]
board/phytium/pomelo/Makefile [new file with mode: 0644]
board/phytium/pomelo/cpu.h [new file with mode: 0644]
board/phytium/pomelo/ddr.c [new file with mode: 0644]
board/phytium/pomelo/pcie.c [new file with mode: 0644]
board/phytium/pomelo/pll.c [new file with mode: 0644]
board/phytium/pomelo/pomelo.c [new file with mode: 0644]
board/phytium/pomelo/sec.c [new file with mode: 0644]
board/sunxi/board.c
board/ti/beagle/beagle.c
board/ti/j721e/evm.c
cmd/Kconfig
cmd/Makefile
cmd/arm/exception64.c
cmd/cls.c
cmd/erofs.c [new file with mode: 0644]
cmd/event.c [new file with mode: 0644]
common/Kconfig
common/Makefile
common/board_f.c
common/board_r.c
common/event.c [new file with mode: 0644]
common/log.c
configs/10m50_defconfig
configs/3c120_defconfig
configs/M5235EVB_Flash32_defconfig
configs/M5235EVB_defconfig
configs/M5272C3_defconfig
configs/M5275EVB_defconfig
configs/M5282EVB_defconfig
configs/MPC837XERDB_defconfig
configs/MPC8548CDS_36BIT_defconfig
configs/MPC8548CDS_defconfig
configs/MPC8548CDS_legacy_defconfig
configs/P1010RDB-PA_36BIT_NAND_defconfig
configs/P1010RDB-PA_36BIT_NOR_defconfig
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PA_NAND_defconfig
configs/P1010RDB-PA_NOR_defconfig
configs/P1010RDB-PA_SDCARD_defconfig
configs/P1010RDB-PA_SPIFLASH_defconfig
configs/P1010RDB-PB_36BIT_NAND_defconfig
configs/P1010RDB-PB_36BIT_NOR_defconfig
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PB_NAND_defconfig
configs/P1010RDB-PB_NOR_defconfig
configs/P1010RDB-PB_SDCARD_defconfig
configs/P1010RDB-PB_SPIFLASH_defconfig
configs/P1020RDB-PC_36BIT_NAND_defconfig
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P1020RDB-PC_36BIT_defconfig
configs/P1020RDB-PC_NAND_defconfig
configs/P1020RDB-PC_SDCARD_defconfig
configs/P1020RDB-PC_SPIFLASH_defconfig
configs/P1020RDB-PC_defconfig
configs/P1020RDB-PD_NAND_defconfig
configs/P1020RDB-PD_SDCARD_defconfig
configs/P1020RDB-PD_SPIFLASH_defconfig
configs/P1020RDB-PD_defconfig
configs/P2020RDB-PC_36BIT_NAND_defconfig
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P2020RDB-PC_36BIT_defconfig
configs/P2020RDB-PC_NAND_defconfig
configs/P2020RDB-PC_SDCARD_defconfig
configs/P2020RDB-PC_SPIFLASH_defconfig
configs/P2020RDB-PC_defconfig
configs/P2041RDB_NAND_defconfig
configs/P2041RDB_SDCARD_defconfig
configs/P2041RDB_SPIFLASH_defconfig
configs/P2041RDB_defconfig
configs/P3041DS_NAND_defconfig
configs/P3041DS_SDCARD_defconfig
configs/P3041DS_SPIFLASH_defconfig
configs/P3041DS_defconfig
configs/P4080DS_SDCARD_defconfig
configs/P4080DS_SPIFLASH_defconfig
configs/P4080DS_defconfig
configs/P5040DS_NAND_defconfig
configs/P5040DS_SDCARD_defconfig
configs/P5040DS_SPIFLASH_defconfig
configs/P5040DS_defconfig
configs/T1024RDB_NAND_defconfig
configs/T1024RDB_SDCARD_defconfig
configs/T1024RDB_SPIFLASH_defconfig
configs/T1024RDB_defconfig
configs/T1042D4RDB_NAND_defconfig
configs/T1042D4RDB_SDCARD_defconfig
configs/T1042D4RDB_SPIFLASH_defconfig
configs/T1042D4RDB_defconfig
configs/T2080QDS_NAND_defconfig
configs/T2080QDS_SDCARD_defconfig
configs/T2080QDS_SECURE_BOOT_defconfig
configs/T2080QDS_SPIFLASH_defconfig
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
configs/T2080QDS_defconfig
configs/T2080RDB_NAND_defconfig
configs/T2080RDB_SDCARD_defconfig
configs/T2080RDB_SPIFLASH_defconfig
configs/T2080RDB_defconfig
configs/T2080RDB_revD_NAND_defconfig
configs/T2080RDB_revD_SDCARD_defconfig
configs/T2080RDB_revD_SPIFLASH_defconfig
configs/T2080RDB_revD_defconfig
configs/T4240RDB_SDCARD_defconfig
configs/T4240RDB_defconfig
configs/am3517_evm_defconfig
configs/at91sam9260ek_dataflash_cs0_defconfig
configs/at91sam9260ek_dataflash_cs1_defconfig
configs/at91sam9260ek_nandflash_defconfig
configs/at91sam9261ek_dataflash_cs0_defconfig
configs/at91sam9261ek_dataflash_cs3_defconfig
configs/at91sam9261ek_nandflash_defconfig
configs/at91sam9263ek_dataflash_cs0_defconfig
configs/at91sam9263ek_dataflash_defconfig
configs/at91sam9263ek_nandflash_defconfig
configs/at91sam9263ek_norflash_boot_defconfig
configs/at91sam9263ek_norflash_defconfig
configs/at91sam9g10ek_dataflash_cs0_defconfig
configs/at91sam9g10ek_dataflash_cs3_defconfig
configs/at91sam9g10ek_nandflash_defconfig
configs/at91sam9g20ek_2mmc_defconfig
configs/at91sam9g20ek_2mmc_nandflash_defconfig
configs/at91sam9g20ek_dataflash_cs0_defconfig
configs/at91sam9g20ek_dataflash_cs1_defconfig
configs/at91sam9g20ek_nandflash_defconfig
configs/at91sam9m10g45ek_mmc_defconfig
configs/at91sam9m10g45ek_nandflash_defconfig
configs/at91sam9n12ek_mmc_defconfig
configs/at91sam9n12ek_nandflash_defconfig
configs/at91sam9n12ek_spiflash_defconfig
configs/at91sam9x5ek_dataflash_defconfig
configs/at91sam9x5ek_mmc_defconfig
configs/at91sam9x5ek_nandflash_defconfig
configs/at91sam9x5ek_spiflash_defconfig
configs/at91sam9xeek_dataflash_cs0_defconfig
configs/at91sam9xeek_dataflash_cs1_defconfig
configs/at91sam9xeek_nandflash_defconfig
configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
configs/axs101_defconfig
configs/axs103_defconfig
configs/bayleybay_defconfig
configs/bcm96753ref_ram_defconfig [new file with mode: 0644]
configs/bitmain_antminer_s9_defconfig
configs/blanche_defconfig
configs/brppt1_mmc_defconfig
configs/brppt1_nand_defconfig
configs/brppt1_spi_defconfig
configs/brppt2_defconfig
configs/brsmarc1_defconfig
configs/brxre1_defconfig
configs/cherryhill_defconfig
configs/chromebook_coral_defconfig
configs/chromebook_link64_defconfig
configs/chromebook_link_defconfig
configs/chromebook_samus_defconfig
configs/chromebook_samus_tpl_defconfig
configs/chromebox_panther_defconfig
configs/cobra5272_defconfig
configs/colibri_pxa270_defconfig
configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
configs/conga-qeval20-qa3-e3845_defconfig
configs/controlcenterdc_defconfig
configs/coreboot64_defconfig
configs/coreboot_defconfig
configs/cortina_presidio-asic-emmc_defconfig
configs/corvus_defconfig
configs/cougarcanyon2_defconfig
configs/crownbay_defconfig
configs/da850evm_defconfig
configs/da850evm_direct_nor_defconfig
configs/da850evm_nand_defconfig
configs/devkit3250_defconfig
configs/devkit8000_defconfig
configs/dfi-bt700-q7x-151_defconfig
configs/dragonboard410c_defconfig
configs/dragonboard820c_defconfig
configs/eb_cpu5282_defconfig
configs/eb_cpu5282_internal_defconfig
configs/efi-x86_app32_defconfig
configs/efi-x86_app64_defconfig
configs/efi-x86_payload32_defconfig
configs/efi-x86_payload64_defconfig
configs/emsdp_defconfig
configs/ethernut5_defconfig
configs/evb-ast2500_defconfig
configs/evb-ast2600_defconfig
configs/galileo_defconfig
configs/gazerbeam_defconfig
configs/gurnard_defconfig
configs/hikey_defconfig
configs/hsdk_4xd_defconfig
configs/hsdk_defconfig
configs/ids8313_defconfig
configs/imx28_xea_defconfig
configs/imx28_xea_sb_defconfig
configs/integratorap_cm720t_defconfig
configs/integratorap_cm920t_defconfig
configs/integratorap_cm926ejs_defconfig
configs/integratorap_cm946es_defconfig
configs/integratorcp_cm1136_defconfig
configs/integratorcp_cm920t_defconfig
configs/integratorcp_cm926ejs_defconfig
configs/integratorcp_cm946es_defconfig
configs/iot_devkit_defconfig
configs/j721e_evm_a72_defconfig
configs/j721e_hs_evm_a72_defconfig
configs/km_kirkwood_128m16_defconfig
configs/km_kirkwood_defconfig
configs/km_kirkwood_pci_defconfig
configs/kmcent2_defconfig
configs/kmcoge5ne_defconfig
configs/kmcoge5un_defconfig
configs/kmeter1_defconfig
configs/kmnusa_defconfig
configs/kmopti2_defconfig
configs/kmsupx5_defconfig
configs/kmsuse2_defconfig
configs/kmtegr1_defconfig
configs/kmtepr2_defconfig
configs/legoev3_defconfig
configs/libretech_all_h3_it_h5_defconfig
configs/libretech_all_h5_cc_h5_defconfig
configs/ls1021aqds_ddr4_nor_defconfig
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
configs/ls1021aqds_nand_defconfig
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
configs/ls1021aqds_nor_defconfig
configs/ls1021aqds_nor_lpuart_defconfig
configs/ls1021aqds_sdcard_ifc_defconfig
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
configs/ls1021atwr_nor_defconfig
configs/ls1021atwr_nor_lpuart_defconfig
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
configs/ls1021atwr_sdcard_ifc_defconfig
configs/ls1043aqds_defconfig
configs/ls1043aqds_lpuart_defconfig
configs/ls1043aqds_nand_defconfig
configs/ls1043aqds_nor_ddr3_defconfig
configs/ls1043aqds_sdcard_ifc_defconfig
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
configs/ls1043aqds_tfa_defconfig
configs/ls1043ardb_SECURE_BOOT_defconfig
configs/ls1043ardb_defconfig
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
configs/ls1043ardb_nand_defconfig
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
configs/ls1043ardb_sdcard_defconfig
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
configs/ls1043ardb_tfa_defconfig
configs/ls1046aqds_SECURE_BOOT_defconfig
configs/ls1046aqds_defconfig
configs/ls1046aqds_lpuart_defconfig
configs/ls1046aqds_nand_defconfig
configs/ls1046aqds_sdcard_ifc_defconfig
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
configs/ls1046aqds_tfa_defconfig
configs/m53menlo_defconfig
configs/meesc_dataflash_defconfig
configs/meesc_defconfig
configs/microblaze-generic_defconfig
configs/minnowmax_defconfig
configs/mx23_olinuxino_defconfig
configs/mx23evk_defconfig
configs/mx28evk_auart_console_defconfig
configs/mx28evk_defconfig
configs/mx28evk_nand_defconfig
configs/mx28evk_spi_defconfig
configs/novena_defconfig
configs/nsim_700_defconfig
configs/nsim_700be_defconfig
configs/nsim_hs38_defconfig
configs/nsim_hs38be_defconfig
configs/oceanic_5205_5inmfd_defconfig
configs/octeontx2_95xx_defconfig
configs/octeontx2_96xx_defconfig
configs/octeontx_81xx_defconfig
configs/octeontx_83xx_defconfig
configs/omap3_beagle_defconfig
configs/omapl138_lcdk_defconfig
configs/orangepi_pc2_defconfig
configs/orangepi_r1_defconfig
configs/orangepi_win_defconfig
configs/orangepi_zero2_defconfig
configs/orangepi_zero_defconfig
configs/pg_wcom_expu1_defconfig
configs/pg_wcom_expu1_update_defconfig
configs/pg_wcom_seli8_defconfig
configs/pg_wcom_seli8_update_defconfig
configs/pic32mzdask_defconfig
configs/pine64-lts_defconfig
configs/pine_h64_defconfig
configs/pinecube_defconfig
configs/pm9263_defconfig
configs/pm9g45_defconfig
configs/pomelo_defconfig [new file with mode: 0644]
configs/qemu-ppce500_defconfig
configs/qemu-x86_64_defconfig
configs/qemu-x86_defconfig
configs/qemu_arm64_defconfig
configs/qemu_arm_defconfig
configs/r8a77990_ebisu_defconfig
configs/r8a77995_draak_defconfig
configs/rcar3_salvator-x_defconfig
configs/rcar3_ulcb_defconfig
configs/sam9x60ek_mmc_defconfig
configs/sam9x60ek_nandflash_defconfig
configs/sam9x60ek_qspiflash_defconfig
configs/sama5d27_som1_ek_mmc1_defconfig
configs/sama5d27_som1_ek_mmc_defconfig
configs/sama5d27_som1_ek_qspiflash_defconfig
configs/sama5d27_wlsom1_ek_mmc_defconfig
configs/sama5d27_wlsom1_ek_qspiflash_defconfig
configs/sama5d2_icp_mmc_defconfig
configs/sama5d2_icp_qspiflash_defconfig
configs/sama5d2_ptc_ek_mmc_defconfig
configs/sama5d2_ptc_ek_nandflash_defconfig
configs/sama5d2_xplained_emmc_defconfig
configs/sama5d2_xplained_mmc_defconfig
configs/sama5d2_xplained_qspiflash_defconfig
configs/sama5d2_xplained_spiflash_defconfig
configs/sama5d36ek_cmp_mmc_defconfig
configs/sama5d36ek_cmp_nandflash_defconfig
configs/sama5d36ek_cmp_spiflash_defconfig
configs/sama5d3_xplained_mmc_defconfig
configs/sama5d3_xplained_nandflash_defconfig
configs/sama5d3xek_mmc_defconfig
configs/sama5d3xek_nandflash_defconfig
configs/sama5d3xek_spiflash_defconfig
configs/sama5d4_xplained_mmc_defconfig
configs/sama5d4_xplained_nandflash_defconfig
configs/sama5d4_xplained_spiflash_defconfig
configs/sama5d4ek_mmc_defconfig
configs/sama5d4ek_nandflash_defconfig
configs/sama5d4ek_spiflash_defconfig
configs/sandbox64_defconfig
configs/sandbox_defconfig
configs/sandbox_flattree_defconfig
configs/sandbox_spl_defconfig
configs/slimbootloader_defconfig
configs/smartweb_defconfig
configs/snapper9260_defconfig
configs/snapper9g20_defconfig
configs/socfpga_agilex_atf_defconfig
configs/socfpga_agilex_defconfig
configs/socfpga_agilex_vab_defconfig
configs/socfpga_dbm_soc1_defconfig
configs/socfpga_is1_defconfig
configs/socfpga_mcvevk_defconfig
configs/socfpga_n5x_atf_defconfig
configs/socfpga_n5x_defconfig
configs/socfpga_n5x_vab_defconfig
configs/socfpga_secu1_defconfig
configs/socfpga_stratix10_atf_defconfig
configs/socfpga_stratix10_defconfig
configs/socfpga_vining_fpga_defconfig
configs/socrates_defconfig
configs/som-db5800-som-6867_defconfig
configs/sopine_baseboard_defconfig
configs/stih410-b2260_defconfig
configs/syzygy_hub_defconfig
configs/tb100_defconfig
configs/tbs2910_defconfig
configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
configs/theadorable-x86-conga-qa3-e3845_defconfig
configs/theadorable-x86-dfi-bt700_defconfig
configs/tools-only_defconfig
configs/tuge1_defconfig
configs/tuxx1_defconfig
configs/uniphier_ld4_sld8_defconfig
configs/uniphier_v7_defconfig
configs/uniphier_v8_defconfig
configs/usb_a9263_dataflash_defconfig
configs/vexpress_aemv8a_juno_defconfig
configs/vexpress_aemv8a_semi_defconfig
configs/vexpress_ca9x4_defconfig
configs/vinco_defconfig
configs/work_92105_defconfig
configs/xilinx_versal_virt_defconfig
configs/xilinx_zynq_virt_defconfig
configs/xilinx_zynqmp_virt_defconfig
configs/xtfpga_defconfig
doc/board/sifive/unmatched.rst
doc/build/gcc.rst
doc/develop/event.rst [new file with mode: 0644]
doc/develop/index.rst
doc/develop/python_cq.rst
doc/device-tree-bindings/arm/arm,scmi.txt
doc/usage/event.rst [new file with mode: 0644]
doc/usage/index.rst
drivers/clk/clk_scmi.c
drivers/core/Kconfig
drivers/core/device-remove.c
drivers/core/device.c
drivers/core/root.c
drivers/ddr/fsl/Kconfig
drivers/firmware/scmi/sandbox-scmi_agent.c
drivers/firmware/scmi/sandbox-scmi_devices.c
drivers/firmware/scmi/scmi_agent-uclass.c
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/gpio-aspeed.c [new file with mode: 0644]
drivers/led/Kconfig
drivers/led/Makefile
drivers/led/led_bcm6753.c [new file with mode: 0644]
drivers/mmc/omap_hsmmc.c
drivers/mmc/rockchip_sdhci.c
drivers/mtd/Kconfig
drivers/mtd/nand/raw/Kconfig
drivers/mtd/nand/raw/brcmnand/Makefile
drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c [new file with mode: 0644]
drivers/mtd/spi/spi-nor-ids.c
drivers/pci/pci_mpc85xx.c
drivers/phy/cadence/phy-cadence-sierra.c
drivers/power/regulator/scmi_regulator.c
drivers/ram/aspeed/Kconfig
drivers/reset/reset-scmi.c
drivers/serial/serial-uclass.c
drivers/spi/Kconfig
drivers/spi/Makefile
drivers/spi/cadence_qspi.c
drivers/spi/cadence_qspi.h
drivers/spi/designware_spi.c
drivers/spi/iproc_qspi.c [new file with mode: 0644]
drivers/watchdog/Kconfig
drivers/watchdog/armada-37xx-wdt.c
drivers/watchdog/rti_wdt.c
drivers/watchdog/wdt-uclass.c
env/Kconfig
fs/Kconfig
fs/Makefile
fs/erofs/Kconfig [new file with mode: 0644]
fs/erofs/Makefile [new file with mode: 0644]
fs/erofs/data.c [new file with mode: 0644]
fs/erofs/decompress.c [new file with mode: 0644]
fs/erofs/decompress.h [new file with mode: 0644]
fs/erofs/erofs_fs.h [new file with mode: 0644]
fs/erofs/fs.c [new file with mode: 0644]
fs/erofs/internal.h [new file with mode: 0644]
fs/erofs/namei.c [new file with mode: 0644]
fs/erofs/super.c [new file with mode: 0644]
fs/erofs/zmap.c [new file with mode: 0644]
fs/fs.c
include/asm-generic/global_data.h
include/asm-generic/u-boot.h
include/configs/10m50_devboard.h
include/configs/3c120_devboard.h
include/configs/M5235EVB.h
include/configs/M5249EVB.h
include/configs/M5272C3.h
include/configs/M5275EVB.h
include/configs/M5282EVB.h
include/configs/MPC837XERDB.h
include/configs/MPC8540ADS.h [deleted file]
include/configs/MPC8548CDS.h
include/configs/MPC8560ADS.h [deleted file]
include/configs/P1010RDB.h
include/configs/P2041RDB.h
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/am3517_evm.h
include/configs/aspeed-common.h
include/configs/at91-sama5_common.h
include/configs/at91sam9260ek.h
include/configs/at91sam9261ek.h
include/configs/at91sam9263ek.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9n12ek.h
include/configs/at91sam9x5ek.h
include/configs/axs10x.h
include/configs/blanche.h
include/configs/broadcom_bcm96753ref.h [new file with mode: 0644]
include/configs/brppt2.h
include/configs/bur_cfg_common.h
include/configs/chromebook_samus.h
include/configs/cobra5272.h
include/configs/colibri_pxa270.h
include/configs/controlcenterdc.h
include/configs/corenet_ds.h
include/configs/corvus.h
include/configs/da850evm.h
include/configs/db-mv784mp-gp.h
include/configs/devkit3250.h
include/configs/devkit8000.h
include/configs/draak.h
include/configs/dragonboard410c.h
include/configs/dragonboard820c.h
include/configs/eb_cpu5282.h
include/configs/ebisu.h
include/configs/emsdp.h
include/configs/espresso7420.h
include/configs/ethernut5.h
include/configs/exynos4-common.h
include/configs/exynos5-common.h
include/configs/exynos5-dt-common.h
include/configs/exynos78x0-common.h
include/configs/gazerbeam.h
include/configs/hikey.h
include/configs/hsdk-4xd.h
include/configs/hsdk.h
include/configs/ids8313.h
include/configs/integratorap.h
include/configs/integratorcp.h
include/configs/iot_devkit.h
include/configs/j721e_evm.h
include/configs/km/keymile-common.h
include/configs/km/pg-wcom-ls102xa.h
include/configs/kmcent2.h
include/configs/kontron_sl28.h
include/configs/legoev3.h
include/configs/ls1012a2g5rdb.h
include/configs/ls1012afrdm.h
include/configs/ls1012afrwy.h
include/configs/ls1012aqds.h
include/configs/ls1012ardb.h
include/configs/ls1021aiot.h
include/configs/ls1021aqds.h
include/configs/ls1021atsn.h
include/configs/ls1021atwr.h
include/configs/ls1028a_common.h
include/configs/ls1043aqds.h
include/configs/ls1043ardb.h
include/configs/ls1046afrwy.h
include/configs/ls1046aqds.h
include/configs/ls1046ardb.h
include/configs/ls1088a_common.h
include/configs/ls2080a_common.h
include/configs/ls2080aqds.h
include/configs/ls2080ardb.h
include/configs/lx2160a_common.h
include/configs/m53menlo.h
include/configs/maxbcm.h
include/configs/meesc.h
include/configs/microblaze-generic.h
include/configs/mx23_olinuxino.h
include/configs/mx23evk.h
include/configs/mx28evk.h
include/configs/mx6_common.h
include/configs/mx7ulp_com.h
include/configs/mx7ulp_evk.h
include/configs/novena.h
include/configs/nsim.h
include/configs/octeontx2_common.h
include/configs/octeontx_common.h
include/configs/odroid_xu3.h
include/configs/omapl138_lcdk.h
include/configs/origen.h
include/configs/p1_p2_rdb_pc.h
include/configs/pic32mzdask.h
include/configs/pm9261.h
include/configs/pm9263.h
include/configs/pm9g45.h
include/configs/pomelo.h [new file with mode: 0644]
include/configs/presidio_asic.h
include/configs/qemu-arm.h
include/configs/qemu-ppce500.h
include/configs/salvator-x.h
include/configs/sam9x60ek.h
include/configs/smartweb.h
include/configs/smdk5250.h
include/configs/smdk5420.h
include/configs/smdkv310.h
include/configs/snapper9260.h
include/configs/snapper9g45.h
include/configs/snow.h
include/configs/socfpga_arria5_secu1.h
include/configs/socfpga_dbm_soc1.h
include/configs/socfpga_is1.h
include/configs/socfpga_mcvevk.h
include/configs/socfpga_soc64_common.h
include/configs/socfpga_vining_fpga.h
include/configs/socrates.h
include/configs/spring.h
include/configs/stih410-b2260.h
include/configs/tb100.h
include/configs/thunderx_88xx.h
include/configs/ulcb.h
include/configs/uniphier.h
include/configs/usb_a9263.h
include/configs/vexpress_aemv8.h
include/configs/vexpress_common.h
include/configs/work_92105.h
include/configs/x86-chromebook.h
include/configs/x86-common.h
include/configs/xea.h
include/configs/xilinx_versal.h
include/configs/xilinx_versal_mini.h
include/configs/xilinx_zynqmp.h
include/configs/xilinx_zynqmp_mini.h
include/configs/xtfpga.h
include/configs/zynq-common.h
include/dm/device-internal.h
include/efi_loader.h
include/env_default.h
include/erofs.h [new file with mode: 0644]
include/event.h [new file with mode: 0644]
include/event_internal.h [new file with mode: 0644]
include/fs.h
include/init.h
include/log.h
include/scmi_agent.h
include/scmi_protocols.h
include/u-boot/lz4.h
lib/efi_loader/efi_boottime.c
lib/efi_loader/efi_image_loader.c
lib/lz4.c
lib/lz4_wrapper.c
net/bootp.c
scripts/config_whitelist.txt
scripts/event_dump.py [new file with mode: 0755]
test/common/Makefile
test/common/event.c [new file with mode: 0644]
test/dm/scmi.c
test/py/tests/test_android/test_avb.py
test/py/tests/test_bind.py
test/py/tests/test_event_dump.py [new file with mode: 0644]
test/py/tests/test_fs/test_erofs.py [new file with mode: 0644]
test/py/tests/vboot_evil.py
test/py/u_boot_console_base.py
test/test-main.c
tools/binman/cmdline.py
tools/binman/control.py
tools/binman/elf.py
tools/binman/elf_test.py
tools/binman/entry.py
tools/binman/entry_test.py
tools/binman/etype/blob_dtb.py
tools/binman/etype/blob_phase.py
tools/binman/etype/cbfs.py
tools/binman/etype/fdtmap.py
tools/binman/etype/files.py
tools/binman/etype/section.py
tools/binman/etype/u_boot_dtb_with_ucode.py
tools/binman/ftest.py
tools/buildman/bsettings.py
tools/buildman/builder.py
tools/buildman/cfgutil.py
tools/buildman/func_test.py
tools/buildman/kconfiglib.py
tools/buildman/main.py
tools/concurrencytest/__init__.py [new file with mode: 0644]
tools/docker/Dockerfile
tools/dtoc/test_dtoc.py
tools/dtoc/test_fdt.py
tools/kwboot.c
tools/moveconfig.py
tools/patman/checkpatch.py
tools/patman/command.py
tools/patman/commit.py
tools/patman/cros_subprocess.py
tools/patman/func_test.py
tools/patman/patchstream.py
tools/patman/series.py
tools/patman/settings.py
tools/patman/tools.py

index db45291..cf49161 100644 (file)
@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2019
   ubuntu_vm: ubuntu-18.04
   macos_vm: macOS-10.15
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -202,6 +202,28 @@ stages:
           export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
           test/nokia_rx51_test.sh
 
+  - job: pylint
+    displayName: Check for any pylint regressions
+    pool:
+      vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
+    steps:
+      - script: |
+          cd ${WORK_DIR}
+          export USER=azure
+          pip install -r test/py/requirements.txt
+          pip install asteval pylint pyopenssl
+          export PATH=${PATH}:~/.local/bin
+          echo "[MASTER]" >> .pylintrc
+          echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
+          export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
+          pylint --version
+          export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
+          make pylint_err
+
 - stage: test_py
   jobs:
   - job: test_py
index 85b5296..31f5096 100644 (file)
@@ -2,7 +2,7 @@
 
 # Grab our configured image.  The source for this is found at:
 # https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
+image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -215,6 +215,22 @@ Run tests for Nokia RX-51 (aka N900):
     - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
       test/nokia_rx51_test.sh
 
+# Check for any pylint regressions
+Run pylint:
+  stage: testsuites
+  script:
+    - pip install -r test/py/requirements.txt
+    - pip install asteval pylint pyopenssl
+    - export PATH=${PATH}:~/.local/bin
+    - echo "[MASTER]" >> .pylintrc
+    - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
+    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+    - ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
+        --board sandbox_spl
+    - pylint --version
+    - export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
+    - make pylint_err
+
 # Test sandbox with test.py
 sandbox test.py:
   variables:
index 36fc116..1f88ea9 100644 (file)
--- a/.mailmap
+++ b/.mailmap
@@ -28,6 +28,7 @@ Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
 Dirk Behme <dirk.behme@googlemail.com>
 Fabio Estevam <fabio.estevam@nxp.com>
 Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
+Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
 Jagan Teki <402jagan@gmail.com>
 Jagan Teki <jaganna@gmail.com>
 Jagan Teki <jaganna@xilinx.com>
index 915316a..126bb43 100644 (file)
@@ -811,6 +811,25 @@ S: Maintained
 F:     doc/usage/environment.rst
 F:     scripts/env2string.awk
 
+EROFS
+M:     Huang Jianan <jnhuang95@gmail.com>
+L:     linux-erofs@lists.ozlabs.org
+S:     Maintained
+F:     cmd/erofs.c
+F:     fs/erofs/
+F:     include/erofs.h
+F:     test/py/tests/test_fs/test_erofs.py
+
+EVENTS
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+F:     cmd/event.c
+F:     common/event.c
+F:     include/event.h
+F:     scripts/event_dump.py
+F:     test/common/event.c
+F:     test/py/tests/test_event_dump.py
+
 FASTBOOT
 S:     Orphaned
 F:     cmd/fastboot.c
@@ -1328,6 +1347,14 @@ F:       include/virtio*.h
 F:     test/dm/virtio.c
 F:     doc/develop/driver-model/virtio.rst
 
+WATCHDOG
+M:     Stefan Roese <sr@denx.de>
+S:     Maintained
+T:     git https://source.denx.de/u-boot/custodians/u-boot-watchdog.git
+F:     cmd/wdt.c
+F:     drivers/watchdog/
+F:     include/watchdog*.h
+
 X86
 M:     Simon Glass <sjg@chromium.org>
 M:     Bin Meng <bmeng.cn@gmail.com>
index f8f3f24..06572ac 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
 VERSION = 2022
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =
 
 # *DOCUMENTATION*
@@ -521,7 +521,8 @@ env_h := include/generated/environment.h
 
 no-dot-config-targets := clean clobber mrproper distclean \
                         help %docs check% coccicheck \
-                        ubootversion backup tests check qcheck tcheck pylint
+                        ubootversion backup tests check qcheck tcheck pylint \
+                        pylint_err
 
 config-targets := 0
 mixed-targets  := 0
@@ -2261,7 +2262,7 @@ distclean: mrproper
        @rm -f boards.cfg CHANGELOG
 
 # See doc/develop/python_cq.rst
-PHONY += pylint
+PHONY += pylint pylint_err
 PYLINT_BASE := scripts/pylint.base
 PYLINT_CUR := pylint.cur
 PYLINT_DIFF := pylint.diff
@@ -2303,6 +2304,11 @@ pylint:
                        echo "No pylint regressions"; \
                fi
 
+# Check for errors only
+pylint_err:
+       $(Q)pylint -E  -j 0 --ignore-imports=yes \
+               $(shell find tools test -name "*.py")
+
 backup:
        F=`basename $(srctree)` ; cd .. ; \
        gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
diff --git a/README b/README
index f51f392..6bb8d6e 100644 (file)
--- a/README
+++ b/README
@@ -1172,35 +1172,6 @@ The following options need to be configured:
                from a BOOTP client in networks with unusually high latency.
 
 - DHCP Advanced Options:
-               You can fine tune the DHCP functionality by defining
-               CONFIG_BOOTP_* symbols:
-
-               CONFIG_BOOTP_NISDOMAIN
-               CONFIG_BOOTP_BOOTFILESIZE
-               CONFIG_BOOTP_NTPSERVER
-               CONFIG_BOOTP_TIMEOFFSET
-               CONFIG_BOOTP_VENDOREX
-               CONFIG_BOOTP_MAY_FAIL
-
-               CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
-               after the configured retry count, the call will fail
-               instead of starting over.  This can be used to fail over
-               to Link-local IP address configuration if the DHCP server
-               is not available.
-
-               CONFIG_BOOTP_DHCP_REQUEST_DELAY
-
-               A 32bit value in microseconds for a delay between
-               receiving a "DHCP Offer" and sending the "DHCP Request".
-               This fixes a problem with certain DHCP servers that don't
-               respond 100% of the time to a "DHCP request". E.g. On an
-               AT91RM9200 processor running at 180MHz, this delay needed
-               to be *at least* 15,000 usec before a Windows Server 2003
-               DHCP server would reply 100% of the time. I recommend at
-               least 50,000 usec to be safe. The alternative is to hope
-               that one of the retries will be successful but note that
-               the DHCP timeout and retry process takes a longer than
-               this delay.
 
  - Link-local IP address negotiation:
                Negotiate with other link-local clients on the local network
@@ -1972,7 +1943,6 @@ typically in board_init_f() and board_init_r().
 - CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f()
 - CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
 - CONFIG_BOARD_LATE_INIT: Call board_late_init()
-- CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init()
 
 Configuration Settings:
 -----------------------
index e619144..1b35fda 100644 (file)
@@ -94,6 +94,7 @@ config NIOS2
        bool "Nios II architecture"
        select CPU
        select DM
+       imply DM_EVENT
        select OF_CONTROL
        select SUPPORT_OF_CONTROL
        imply CMD_DM
@@ -113,6 +114,7 @@ config RISCV
        select DM
        imply DM_SERIAL
        imply DM_ETH
+       imply DM_EVENT
        imply DM_MMC
        imply DM_SPI
        imply DM_SPI_FLASH
@@ -238,6 +240,7 @@ config X86
        imply CMD_SF_TEST
        imply CMD_ZBOOT
        imply DM_ETH
+       imply DM_EVENT
        imply DM_GPIO
        imply DM_KEYBOARD
        imply DM_MMC
index 391a77c..474ce4a 100644 (file)
@@ -617,6 +617,13 @@ config ARCH_BCM63158
        select OF_CONTROL
        imply CMD_DM
 
+config ARCH_BCM6753
+       bool "Broadcom BCM6753 family"
+       select CPU_V7A
+       select DM
+       select OF_CONTROL
+       imply CMD_DM
+
 config ARCH_BCM68360
        bool "Broadcom BCM68360 family"
        select DM
@@ -767,6 +774,7 @@ config ARCH_OMAP2PLUS
        select SUPPORT_SPL
        imply TI_SYSC if DM && OF_CONTROL
        imply FIT
+       imply DM_EVENT
 
 config ARCH_MESON
        bool "Amlogic Meson"
@@ -811,6 +819,7 @@ config ARCH_IMX8
        select MACH_IMX
        select OF_CONTROL
        select ENABLE_ARM_SOC_BOOT0_HOOK
+       imply DM_EVENT
 
 config ARCH_IMX8M
        bool "NXP i.MX8M platform"
@@ -824,6 +833,7 @@ config ARCH_IMX8M
        select DM
        select SUPPORT_SPL
        imply CMD_DM
+       imply DM_EVENT
 
 config ARCH_IMX8ULP
        bool "NXP i.MX8ULP platform"
@@ -834,6 +844,7 @@ config ARCH_IMX8ULP
        select SUPPORT_SPL
        select GPIO_EXTRA_HEADER
        imply CMD_DM
+       imply DM_EVENT
 
 config ARCH_IMXRT
        bool "NXP i.MXRT platform"
@@ -869,6 +880,7 @@ config ARCH_MX31
 
 config ARCH_MX7ULP
        bool "NXP MX7ULP"
+       select BOARD_POSTCLK_INIT
        select CPU_V7A
        select GPIO_EXTRA_HEADER
        select MACH_IMX
@@ -894,6 +906,7 @@ config ARCH_MX7
 
 config ARCH_MX6
        bool "Freescale MX6"
+       select BOARD_POSTCLK_INIT
        select CPU_V7A
        select GPIO_EXTRA_HEADER
        select MACH_IMX
@@ -1062,6 +1075,8 @@ config ARCH_SUNXI
        select DM_ETH
        select DM_GPIO
        select DM_I2C if I2C
+       select DM_SPI if SPI
+       select DM_SPI_FLASH if SPI
        select DM_KEYBOARD
        select DM_MMC if MMC
        select DM_SCSI if SCSI
@@ -1973,6 +1988,25 @@ config TARGET_DURIAN
          Support for durian platform.
          It has 2GB Sdram, uart and pcie.
 
+config TARGET_POMELO
+       bool "Support Phytium Pomelo Platform"
+       select ARM64
+       select DM
+       select AHCI
+       select SCSI_AHCI
+       select AHCI_PCI
+       select BLK
+       select PCI
+       select DM_PCI
+       select SCSI
+       select DM_SCSI
+       select DM_SERIAL
+       select DM_ETH if NET
+       imply CMD_PCI
+       help
+          Support for pomelo platform.
+          It has 8GB Sdram, uart and pcie.
+
 config TARGET_PRESIDIO_ASIC
        bool "Support Cortina Presidio ASIC Platform"
        select ARM64
@@ -2204,6 +2238,7 @@ source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/cortina/presidio-asic/Kconfig"
 source "board/broadcom/bcm963158/Kconfig"
+source "board/broadcom/bcm96753ref/Kconfig"
 source "board/broadcom/bcm968360bg/Kconfig"
 source "board/broadcom/bcm968580xref/Kconfig"
 source "board/broadcom/bcmns3/Kconfig"
@@ -2243,6 +2278,7 @@ source "board/traverse/ten64/Kconfig"
 source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/phytium/durian/Kconfig"
+source "board/phytium/pomelo/Kconfig"
 source "board/xen/xenguest_arm64/Kconfig"
 source "board/keymile/Kconfig"
 
index 6a948d7..ef1f456 100644 (file)
@@ -5,7 +5,7 @@ config ARCH_LS1021A
        select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A008407
-       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
        select SYS_FSL_ERRATUM_A008997 if USB
        select SYS_FSL_ERRATUM_A009007 if USB
        select SYS_FSL_ERRATUM_A009008 if USB
index 8a95ee8..c131d92 100644 (file)
@@ -12,7 +12,9 @@
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_stream_id.h>
 #include <fsl_csu.h>
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 #include <fsl_ddr_sdram.h>
+#endif
 
 struct liodn_id_table sec_liodn_tbl[] = {
        SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
index 2ded3e4..177f568 100644 (file)
@@ -8,7 +8,6 @@
 #include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
-#include <fsl_ddr_sdram.h>
 #include <init.h>
 #include <hang.h>
 #include <log.h>
@@ -36,6 +35,7 @@
 #endif
 #include <asm/armv8/sec_firmware.h>
 #ifdef CONFIG_SYS_FSL_DDR
+#include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
 #endif
 #include <asm/arch/clock.h>
@@ -1632,12 +1632,14 @@ void update_early_mmu_table(void)
 
 __weak int dram_init(void)
 {
+#ifdef CONFIG_SYS_FSL_DDR
        fsl_initdram();
 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
        defined(CONFIG_SPL_BUILD)
        /* This will break-before-make MMU for DDR */
        update_early_mmu_table();
 #endif
+#endif
 
        return 0;
 }
index 3aa1a9c..2fb4e40 100644 (file)
@@ -74,15 +74,6 @@ ENDPROC(smp_kick_all_cpus)
 ENTRY(lowlevel_init)
        mov     x29, lr                 /* Save LR */
 
-       /* unmask SError and abort */
-       msr daifclr, #4
-
-       /* Set HCR_EL2[AMO] so SError @EL2 is taken */
-       mrs     x0, hcr_el2
-       orr     x0, x0, #0x20                   /* AMO */
-       msr     hcr_el2, x0
-       isb
-
        switch_el x1, 1f, 100f, 100f    /* skip if not in EL3 */
 1:
 
@@ -209,7 +200,7 @@ ENTRY(lowlevel_init)
 #endif
 
 100:
-       branch_if_master x0, x1, 2f
+       branch_if_master x0, 2f
 
 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
        /*
index 91b00a4..6a6a4f8 100644 (file)
@@ -126,6 +126,8 @@ pie_fixup_done:
        b       0f
 2:     mrs     x1, hcr_el2
        tbnz    x1, #34, 1f                     /* HCR_EL2.E2H */
+       orr     x1, x1, #HCR_EL2_AMO_EL2        /* Route SErrors to EL2 */
+       msr     hcr_el2, x1
        set_vbar vbar_el2, x0
        mov     x0, #0x33ff
        msr     cptr_el2, x0                    /* Enable FP/SIMD */
@@ -134,6 +136,7 @@ pie_fixup_done:
        mov     x0, #3 << 20
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
+       msr     daifclr, #0x4                   /* Unmask SError interrupts */
 
 #ifdef COUNTER_FREQUENCY
        branch_if_not_highest_el x0, 4f
@@ -172,11 +175,11 @@ pie_fixup_done:
        bl      lowlevel_init
 
 #if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
-       branch_if_master x0, x1, master_cpu
+       branch_if_master x0, master_cpu
        b       spin_table_secondary_jump
        /* never return */
 #elif defined(CONFIG_ARMV8_MULTIENTRY)
-       branch_if_master x0, x1, master_cpu
+       branch_if_master x0, master_cpu
 
        /*
         * Slave CPUs
@@ -189,6 +192,7 @@ slave_cpu:
        br      x0                      /* branch to the given address */
 #endif /* CONFIG_ARMV8_MULTIENTRY */
 master_cpu:
+       msr     SPSel, #1               /* make sure we use SP_ELx */
        bl      _main
 
 /*-----------------------------------------------------------------------*/
@@ -301,7 +305,7 @@ WEAK(lowlevel_init)
 #endif
 
 #ifdef CONFIG_ARMV8_MULTIENTRY
-       branch_if_master x0, x1, 2f
+       branch_if_master x0, 2f
 
        /*
         * Slave should wait for master clearing spin table.
index 2edcb26..770a519 100644 (file)
@@ -1105,6 +1105,9 @@ dtb-$(CONFIG_ARCH_BCM63158) += \
 dtb-$(CONFIG_ARCH_BCM68360) += \
        bcm968360bg.dtb
 
+dtb-$(CONFIG_ARCH_BCM6753) += \
+       bcm96753ref.dtb
+
 dtb-$(CONFIG_ARCH_BCM6858) += \
        bcm968580xref.dtb
 
@@ -1186,6 +1189,7 @@ dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb
 dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
 
 dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
 
 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
 
index b509302..5871344 100644 (file)
@@ -40,6 +40,9 @@
                ethernet1 = &cpsw_emac1;
                spi0 = &spi0;
                spi1 = &spi1;
+               mmc0 = &mmc1;
+               mmc1 = &mmc2;
+               mmc2 = &mmc3;
        };
 
        cpus {
                        };
                };
 
+               target-module@47810000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       reg = <0x478102fc 0x4>,
+                             <0x47810110 0x4>,
+                             <0x47810114 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_ENAWAKEUP |
+                                        SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,syss-mask = <1>;
+                       clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x47810000 0x1000>;
+
+                       mmc3: mmc@0 {
+                             compatible = "ti,am335-sdhci";
+                             ti,needs-special-reset;
+                             interrupts = <29>;
+                             reg = <0x0 0x1000>;
+                             status = "disabled";
+                       };
+               };
+
                i2c0: i2c@44e0b000 {
                        compatible = "ti,omap4-i2c";
                        #address-cells = <1>;
                        status = "disabled";
                };
 
-               mmc3: mmc@47810000 {
-                       compatible = "ti,omap4-hsmmc";
-                       ti,hwmods = "mmc3";
-                       ti,needs-special-reset;
-                       interrupts = <29>;
-                       reg = <0x47810000 0x1000>;
-                       status = "disabled";
-               };
-
                wdt2: wdt@44e35000 {
                        compatible = "ti,omap3-wdt";
                        ti,hwmods = "wd_timer2";
index d5a4ce9..1a70630 100644 (file)
        /delete-property/ u-boot,dm-spl;
 };
 
-/delete-node/ &uart1;
-/delete-node/ &uart2;
-/delete-node/ &mmc2;
-/delete-node/ &mmc3;
+&mmc2 {
+       /delete-property/ u-boot,dm-spl;
+};
+
+&mmc3 {
+       /delete-property/ u-boot,dm-spl;
+};
+
+&uart1 {
+       /delete-property/ u-boot,dm-spl;
+};
+
+&uart2 {
+       /delete-property/ u-boot,dm-spl;
+};
index 54aa252..7d8f32b 100644 (file)
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/
  */
 
 #include <dt-bindings/input/input.h>
index 935c471..a01f9cf 100644 (file)
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
        };
 
        lcd0: display@0 {
-               compatible = "panel-dpi";
+               /* This isn't the exact LCD, but the timings meet spec */
+               /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
+               compatible = "newhaven,nhd-4.3-480272ef-atxl";
                label = "15";
-               status = "okay";
-               pinctrl-names = "default";
+               backlight = <&bl>;
                enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;    /* gpio176, lcd INI */
                vcc-supply = <&vdd_io_reg>;
 
                                remote-endpoint = <&dpi_out>;
                        };
                };
-
-               panel-timing {
-                       clock-frequency = <9000000>;
-                       hactive = <480>;
-                       vactive = <272>;
-                       hfront-porch = <3>;
-                       hback-porch = <2>;
-                       hsync-len = <42>;
-                       vback-porch = <3>;
-                       vfront-porch = <4>;
-                       vsync-len = <11>;
-                       hsync-active = <0>;
-                       vsync-active = <0>;
-                       de-active = <1>;
-                       pixelclk-active = <1>;
-               };
        };
 
        bl: backlight {
                pinctrl-0 = <&pwm_pins>;
                ti,timers = <&timer11>;
                #pwm-cells = <3>;
+               ti,clock-source = <0x01>;
        };
 
        /* HS USB Host PHY on PORT 1 */
        hsusb1_phy: hsusb1_phy {
+               pinctrl-names = "default";
+               pinctrl-0 = <&hsusb1_rst_pins>;
                compatible = "usb-nop-xceiv";
                reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
                #phy-cells = <0>;
 };
 
 &davinci_emac {
-            status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&ethernet_pins>;
+       status = "okay";
 };
 
 &davinci_mdio {
 };
 
 &usbhshost {
+       pinctrl-names = "default";
+       pinctrl-0 = <&hsusb1_pins>;
        port1-mode = "ehci-phy";
 };
 
 };
 
 &omap3_pmx_core {
-       pinctrl-names = "default";
-       pinctrl-0 = <&hsusb1_rst_pins>;
+
+       ethernet_pins: pinmux_ethernet_pins {
+               pinctrl-single,pins = <
+                       OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */
+                       OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */
+                       OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */
+                       OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */
+                       OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */
+                       OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */
+                       OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */
+                       OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */
+                       OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */
+                       OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */
+               >;
+       };
 
        leds_pins: pinmux_leds_pins {
                pinctrl-single,pins = <
 };
 
 &omap3_pmx_core2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&hsusb1_pins>;
 
        hsusb1_pins: pinmux_hsusb1_pins {
                pinctrl-single,pins = <
index b1c988e..8b669e2 100644 (file)
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2016 Derald D. Woods <woods.technical@gmail.com>
  *
  * Based on am3517-evm.dts
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 / {
index 1fc4a30..595b4b5 100644 (file)
        /*
         * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
         * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
-        * 2 size cells and also expects that the second range starts at 16 MB offset. If these
+        * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
+        * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
+        * no remapping) and that this address is the lowest from all specified ranges. If these
         * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
         * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
         * for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping.
         * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
         * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
         * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
+        * Bug related to requirement of same child and parent addresses for first range is fixed
+        * in U-Boot version 2022.04 by following commit:
+        * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
         */
        #address-cells = <3>;
        #size-cells = <2>;
index 9fa6457..0bb4f60 100644 (file)
                         * (totaling 127 MiB) for MEM.
                         */
                        ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
-                                 0x81000000 0 0xeff00000   0 0xeff00000   0 0x00100000>; /* Port 0 IO*/
+                                 0x81000000 0 0x00000000   0 0xeff00000   0 0x00100000>; /* Port 0 IO */
                        interrupt-map-mask = <0 0 0 7>;
                        interrupt-map = <0 0 0 1 &pcie_intc 0>,
                                        <0 0 0 2 &pcie_intc 1>,
index 98359bf..ee66ef6 100644 (file)
                                reg = <0x1e780000 0x1000>;
                                interrupts = <20>;
                                gpio-ranges = <&pinctrl 0 0 220>;
+                               ngpios = <228>;
                                interrupt-controller;
                        };
 
diff --git a/arch/arm/dts/bcm6753.dtsi b/arch/arm/dts/bcm6753.dtsi
new file mode 100644 (file)
index 0000000..e88ab09
--- /dev/null
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "brcm,bcm6753";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               u-boot,dm-pre-reloc;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       next-level-cache = <&l2>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0x1>;
+                       next-level-cache = <&l2>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               cpu2: cpu@2 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0x2>;
+                       next-level-cache = <&l2>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               l2: l2-cache0 {
+                       compatible = "cache";
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               u-boot,dm-pre-reloc;
+
+               periph_osc: periph-osc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clocks = <&periph_osc>;
+                       clock-mult = <2>;
+                       clock-div = <1>;
+               };
+
+               refclk50mhz: refclk50mhz {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <50000000>;
+               };
+       };
+
+       ubus {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               uart0: serial@ff812000 {
+                       compatible = "arm,pl011", "arm,primecell";
+                       reg = <0xff812000 0x1000>;
+                       clock = <50000000>;
+
+                       status = "disabled";
+               };
+
+               wdt1: watchdog@ff800480 {
+                       compatible = "brcm,bcm6345-wdt";
+                       reg = <0xff800480 0x14>;
+                       clocks = <&refclk50mhz>;
+               };
+
+               wdt2: watchdog@ff8004c0 {
+                       compatible = "brcm,bcm6345-wdt";
+                       reg = <0xff8004c0 0x14>;
+                       clocks = <&refclk50mhz>;
+               };
+
+               wdt-reboot {
+                       compatible = "wdt-reboot";
+                       wdt = <&wdt1>;
+               };
+
+               gpio0: gpio-controller@0xff800500 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff800500 0x4>,
+                             <0xff800520 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio1: gpio-controller@0xff800504 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff800504 0x4>,
+                             <0xff800524 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio2: gpio-controller@0xff800508 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff800508 0x4>,
+                             <0xff800528 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio3: gpio-controller@0xff80050c {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff80050c 0x4>,
+                             <0xff80052c 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio4: gpio-controller@0xff800510 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff800510 0x4>,
+                             <0xff800530 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio5: gpio-controller@0xff800514 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff800514 0x4>,
+                             <0xff800534 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio6: gpio-controller@0xff800518 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff800518 0x4>,
+                             <0xff800538 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio7: gpio-controller@0xff80051c {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0xff80051c 0x4>,
+                             <0xff80053c 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               nand: nand-controller@ff801800 {
+                       compatible = "brcm,nand-bcm6753",
+                                    "brcm,brcmnand-v5.0",
+                                    "brcm,brcmnand";
+                       reg-names = "nand", "nand-int-base", "nand-cache";
+                       reg = <0xff801800 0x180>,
+                             <0xff802000 0x10>,
+                             <0xff801c00 0x200>;
+                       parameter-page-big-endian = <0>;
+
+                       status = "disabled";
+               };
+
+               leds: led-controller@ff803000 {
+                       compatible = "brcm,bcm6753-leds";
+                       reg = <0xff803000 0x3480>;
+
+                       status = "disabled";
+               };
+       };
+};
diff --git a/arch/arm/dts/bcm96753ref.dts b/arch/arm/dts/bcm96753ref.dts
new file mode 100644 (file)
index 0000000..ca15ca5
--- /dev/null
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+/dts-v1/;
+
+#include "bcm6753.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "Broadcom bcm6753ref";
+       compatible = "broadcom,bcm6753ref", "brcm,bcm6753";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x40000000>;
+       };
+};
+
+&uart0 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio2 {
+       status = "okay";
+};
+
+&gpio3 {
+       status = "okay";
+};
+
+&gpio4 {
+       status = "okay";
+};
+
+&gpio5 {
+       status = "okay";
+};
+
+&gpio6 {
+       status = "okay";
+};
+
+&gpio7 {
+       status = "okay";
+};
+
+&nand {
+       status = "okay";
+       write-protect = <0>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       nandcs@0 {
+               compatible = "brcm,nandcs";
+               reg = <0>;
+               nand-ecc-strength = <4>;
+               nand-ecc-step-size = <512>;
+               brcm,nand-oob-sector-size = <16>;
+       };
+};
+
+&leds {
+       status = "okay";
+       #address-cells = <1>;
+       #size-cells = <0>;
+       brcm,serial-led-en-pol;
+       brcm,serial-led-data-ppol;
+
+       led@0 {
+               reg = <0>;
+               label = "led_red";
+       };
+
+       led@1 {
+               reg = <1>;
+               label = "led_green";
+       };
+};
index f7a841a..f690bc8 100644 (file)
@@ -9,5 +9,19 @@
 
 / {
        model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
-       compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3";
+       compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+
+       hsusb2_2_pins: pinmux_hsusb2_2_pins {
+               pinctrl-single,pins = <
+                       OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                       OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                       OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                       OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                       OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                       OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+               >;
+       };
 };
index a604d92..e28e962 100644 (file)
        model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
        compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
 };
+
+&omap3_pmx_core2 {
+
+       hsusb2_2_pins: pinmux_hsusb2_2_pins {
+               pinctrl-single,pins = <
+                       OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                       OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                       OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                       OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                       OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                       OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+               >;
+       };
+};
index 100396f..7d0468a 100644 (file)
@@ -51,6 +51,8 @@
 
 &mcbsp2 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcbsp2_pins>;
 };
 
 &charger {
@@ -77,7 +79,7 @@
 };
 
 &dss {
-       status = "ok";
+       status = "okay";
        vdds_dsi-supply = <&vpll2>;
        vdda_video-supply = <&video_reg>;
        pinctrl-names = "default";
                regulator-max-microvolt = <3300000>;
        };
 
-       lcd0: display@0 {
-               compatible = "panel-dpi";
-               label = "28";
-               status = "okay";
-               /* default-on; */
+       lcd0: display {
+               /* This isn't the exact LCD, but the timings meet spec */
+               compatible = "logicpd,type28";
                pinctrl-names = "default";
                pinctrl-0 = <&lcd_enable_pin>;
-               enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;    /* gpio155, lcd INI */
+               backlight = <&bl>;
+               enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
                port {
                        lcd_in: endpoint {
                                remote-endpoint = <&dpi_out>;
                        };
                };
-
-               panel-timing {
-                       clock-frequency = <9000000>;
-                       hactive = <480>;
-                       vactive = <272>;
-                       hfront-porch = <3>;
-                       hback-porch = <2>;
-                       hsync-len = <42>;
-                       vback-porch = <3>;
-                       vfront-porch = <2>;
-                       vsync-len = <11>;
-                       hsync-active = <1>;
-                       vsync-active = <1>;
-                       de-active = <1>;
-                       pixelclk-active = <0>;
-               };
        };
 
        bl: backlight {
index b56524c..385bc8d 100644 (file)
@@ -27,6 +27,8 @@
 
        /* HS USB Host PHY on PORT 1 */
        hsusb2_phy: hsusb2_phy {
+               pinctrl-names = "default";
+               pinctrl-0 = <&hsusb2_reset_pin>;
                compatible = "usb-nop-xceiv";
                reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
                #phy-cells = <0>;
 };
 
 &usbhshost {
+       pinctrl-names = "default";
+       pinctrl-0 = <&hsusb2_pins>, <&hsusb2_2_pins>;
        port2-mode = "ehci-phy";
 };
 
 
 
 &omap3_pmx_core {
-       pinctrl-names = "default";
-       pinctrl-0 = <&hsusb2_pins>;
 
        mmc3_pins: pinmux_mm3_pins {
                pinctrl-single,pins = <
                        OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
                >;
        };
+
        mcbsp2_pins: pinmux_mcbsp2_pins {
                pinctrl-single,pins = <
                        OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
                        OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)       /* GPIO_162,BT_EN */
                >;
        };
+
        mcspi1_pins: pinmux_mcspi1_pins {
                pinctrl-single,pins = <
                        OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
 };
 
 &omap3_pmx_wkup {
-       pinctrl-names = "default";
-       pinctrl-0 = <&hsusb2_reset_pin>;
+
        hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
                pinctrl-single,pins = <
                        OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)        /* sys_boot2.gpio_4 */
                >;
        };
+
        wl127x_gpio: pinmux_wl127x_gpio_pin {
                pinctrl-single,pins = <
                        OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4)         /* sys_boot0.gpio_2 */
        };
 };
 
-&omap3_pmx_core2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&hsusb2_2_pins>;
-       hsusb2_2_pins: pinmux_hsusb2_2_pins {
-               pinctrl-single,pins = <
-                       OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
-                       OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
-                       OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
-                       OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
-                       OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
-                       OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
-               >;
-       };
-};
-
 &uart2 {
        interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
        pinctrl-names = "default";
index 7675bc3..cb08aa6 100644 (file)
@@ -9,5 +9,13 @@
 
 / {
        model = "LogicPD Zoom OMAP35xx Torpedo Development Kit";
-       compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3";
+       compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3";
+};
+
+&omap3_pmx_core {
+       isp1763_pins: pinmux_isp1763_pins {
+               pinctrl-single,pins = <
+                       OMAP3_CORE1_IOPAD(0x2154,  PIN_INPUT_PULLUP | MUX_MODE4)        /* sdmmc1_dat6.gpio_128 */
+               >;
+       };
 };
index 18c27e8..07ea822 100644 (file)
        };
 };
 
+&uart2 {
+       /delete-property/dma-names;
+       bluetooth {
+               compatible = "ti,wl1283-st";
+               enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */
+               max-speed = <3000000>;
+       };
+};
+
+/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */
+&mt9p031_out {
+       pixel-clock-frequency = <90000000>;
+};
+
 &omap3_pmx_core {
        mmc3_pins: pinmux_mm3_pins {
                pinctrl-single,pins = <
                >;
        };
 };
+
+/* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */
+&omap3_pmx_wkup {
+       isp1763_pins: pinmux_isp1763_pins {
+               pinctrl-single,pins = <
+                       OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4)  /* reserved.gpio_128 */
+               >;
+       };
+};
index 642e809..b4664ab 100644 (file)
@@ -65,6 +65,7 @@
                pinctrl-0 = <&pwm_pins>;
                ti,timers = <&timer10>;
                #pwm-cells = <3>;
+               ti,clock-source = <0x01>;
        };
 
 };
@@ -80,6 +81,8 @@
 };
 
 &mcbsp2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcbsp2_pins>;
        status = "okay";
 };
 
@@ -90,7 +93,8 @@
 
 &gpmc {
        ranges = <0 0 0x30000000 0x1000000      /* CS0: 16MB for NAND */
-                 1 0 0x2c000000 0x1000000>;    /* CS1: 16MB for LAN9221 */
+                 1 0 0x2c000000 0x1000000      /* CS1: 16MB for LAN9221 */
+                 6 0 0x28000000 0x1000000>;    /* CS6: 16MB for ISP1763 */
 
        ethernet@gpmc {
                pinctrl-names = "default";
                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;            /* gpio129 */
                reg = <1 0 0xff>;
        };
+
+       usb@6,0 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&isp1763_pins>;
+               compatible = "nxp,usb-isp1763";
+               reg = <0x6 0x0 0xff>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "host";
+               bus-width = <16>;
+               dr_mode = "host";
+               gpmc,mux-add-data = <0>;
+               gpmc,device-width = <2>;
+               gpmc,wait-pin = <0>;
+               gpmc,burst-length = <4>;
+               gpmc,cycle2cycle-samecsen = <1>;
+               gpmc,cycle2cycle-diffcsen = <1>;
+               gpmc,cs-on-ns = <0>;
+               gpmc,cs-rd-off-ns = <45>;
+               gpmc,cs-wr-off-ns = <45>;
+               gpmc,adv-on-ns = <0>;
+               gpmc,adv-rd-off-ns = <0>;
+               gpmc,adv-wr-off-ns = <0>;
+               gpmc,oe-on-ns = <0>;
+               gpmc,oe-off-ns = <45>;
+               gpmc,we-on-ns = <0>;
+               gpmc,we-off-ns = <25>;
+               gpmc,rd-cycle-ns = <60>;
+               gpmc,wr-cycle-ns = <45>;
+               gpmc,access-ns = <35>;
+               gpmc,page-burst-access-ns = <0>;
+               gpmc,bus-turnaround-ns = <0>;
+               gpmc,cycle2cycle-delay-ns = <60>;
+               gpmc,wait-monitoring-ns = <0>;
+               gpmc,clk-activation-ns = <0>;
+               gpmc,wr-data-mux-bus-ns = <5>;
+               gpmc,wr-access-ns = <20>;
+       };
 };
 
+&hdqw1w {
+       pinctrl-names = "default";
+       pinctrl-0 = <&hdq_pins>;
+};
+
+
 &vpll2 {
        regulator-always-on;
 };
 
 &dss {
-       status = "ok";
+       status = "okay";
        vdds_dsi-supply = <&vpll2>;
-       vdda_video-supply = <&video_reg>;
+       vdda_video-supply = <&vpll2>;
        pinctrl-names = "default";
        pinctrl-0 = <&dss_dpi_pins1>;
        port {
                display0 = &lcd0;
        };
 
-       video_reg: video_reg {
-               pinctrl-names = "default";
-               pinctrl-0 = <&panel_pwr_pins>;
-               compatible = "regulator-fixed";
-               regulator-name = "fixed-supply";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-               gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>;    /* gpio155, lcd INI */
-       };
-
        lcd0: display {
-               compatible = "panel-dpi";
+               /* This isn't the exact LCD, but the timings meet spec */
+               compatible = "newhaven,nhd-4.3-480272ef-atxl";
                label = "15";
-               status = "okay";
-               /* default-on; */
                pinctrl-names = "default";
-
+               pinctrl-0 = <&panel_pwr_pins>;
+               backlight = <&bl>;
+               enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
                port {
                        lcd_in: endpoint {
                                remote-endpoint = <&dpi_out>;
                        };
                };
-
-               panel-timing {
-                       clock-frequency = <9000000>;
-                       hactive = <480>;
-                       vactive = <272>;
-                       hfront-porch = <3>;
-                       hback-porch = <2>;
-                       hsync-len = <42>;
-                       vback-porch = <3>;
-                       vfront-porch = <4>;
-                       vsync-len = <11>;
-                       hsync-active = <0>;
-                       vsync-active = <0>;
-                       de-active = <1>;
-                       pixelclk-active = <1>;
-               };
        };
 
        bl: backlight {
                >;
        };
 
+       hdq_pins: hdq_pins {
+               pinctrl-single,pins = <
+                       OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */
+               >;
+       };
+
        pwm_pins: pinmux_pwm_pins {
                pinctrl-single,pins = <
                        OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3)       /* gpmc_ncs5.gpt_10_pwm_evt */
index 3fdd0a7..3a52285 100644 (file)
        };
 };
 
+/* The Torpedo doesn't route the USB host pins */
+&usbhshost {
+       status = "disabled";
+};
+
 &gpmc {
        ranges = <0 0 0x30000000 0x1000000>;    /* CS0: 16MB for NAND */
 
 &twl_gpio {
        ti,use-leds;
 };
+
+&twl_keypad {
+       status = "disabled";
+};
diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts
new file mode 100644 (file)
index 0000000..3f809c0
--- /dev/null
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Phytium Pomelo board
+ * Copyright (C) 2021, Phytium Ltd.
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+/dts-v1/;
+
+/ {
+       model = "Phytium Pomelo Board";
+       compatible = "phytium,d2000-pomelo", "phytium,d2000";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       sysclk_48mhz: clk48mhz {
+               compatible = "fixed-clock";
+               #clock-cells = <0x0>;
+               clock-frequency = <48000000>;
+               clock-output-names = "sysclk_48mhz";
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               uart0: serial@28001000 {
+                       compatible = "arm,pl011", "arm,primecell";
+                       reg = <0x0 0x28001000 0x0 0x1000>;
+                       clocks = <&sysclk_48mhz>;
+               };
+
+               pcie@40000000 {
+                       compatible = "pci-host-ecam-generic";
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       reg = <0x0 0x40000000 0x0 0x10000000>;
+                       ranges = <0x01000000 0x00 0x00000000 0x0  0x50000000 0x0  0x00F00000>,
+                        <0x02000000 0x00 0x58000000 0x0  0x58000000 0x0  0x28000000>,
+                        <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10  0x00000000>;
+               };
+       };
+};
index 36b8403..89b1015 100644 (file)
@@ -1,45 +1,26 @@
 /*
- *  linux/include/asm-arm/io.h
+ * I/O device access primitives. Based on early versions from the Linux kernel.
  *
  *  Copyright (C) 1996-2000 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * Modifications:
- *  16-Sep-1996        RMK     Inlined the inx/outx functions & optimised for both
- *                     constant addresses and variable addresses.
- *  04-Dec-1997        RMK     Moved a lot of this stuff to the new architecture
- *                     specific IO header files.
- *  27-Mar-1999        PJB     Second parameter of memcpy_toio is const..
- *  04-Apr-1999        PJB     Added check_signature.
- *  12-Dec-1999        RMK     More cleanups
- *  18-Jun-2000 RMK    Removed virt_to_* and friends definitions
  */
 #ifndef __ASM_ARM_IO_H
 #define __ASM_ARM_IO_H
 
-#ifdef __KERNEL__
-
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
 #include <asm/barriers.h>
-#if 0  /* XXX###XXX */
-#include <asm/arch/hardware.h>
-#endif /* XXX###XXX */
 
 static inline void sync(void)
 {
 }
 
-/*
- * Generic virtual read/write.  Note that we don't support half-word
- * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
- * to the architecture specific code.
- */
+/* Generic virtual read/write. */
 #define __arch_getb(a)                 (*(volatile unsigned char *)(a))
 #define __arch_getw(a)                 (*(volatile unsigned short *)(a))
 #define __arch_getl(a)                 (*(volatile unsigned int *)(a))
@@ -248,13 +229,6 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 #define clrsetbits_64(addr, clear, set) clrsetbits(64, addr, clear, set)
 
 /*
- * Now, pick up the machine-defined IO definitions
- */
-#if 0  /* XXX###XXX */
-#include <asm/arch/io.h>
-#endif /* XXX###XXX */
-
-/*
  *  IO port access primitives
  *  -------------------------
  *
@@ -318,24 +292,12 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 #define readsb(a, d, s)                __raw_readsb((unsigned long)a, d, s)
 
 /*
- * DMA-consistent mapping functions.  These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices.  This is the "generic" version.  The PCI specific version
- * is in pci.h
- */
-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
-extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
-extern void consistent_sync(void *vaddr, size_t size, int rw);
-
-/*
  * String version of IO memory access ops:
  */
 extern void _memcpy_fromio(void *, unsigned long, size_t);
 extern void _memcpy_toio(unsigned long, const void *, size_t);
 extern void _memset_io(unsigned long, int, size_t);
 
-extern void __readwrite_bug(const char *fn);
-
 /* Optimized copy functions to read from/write to IO sapce */
 #ifdef CONFIG_ARM64
 #include <cpu_func.h>
@@ -441,62 +403,6 @@ void __memset_io(volatile void __iomem *dst, int c, size_t count)
 #define memcpy_toio(a, b, c)           memcpy((void *)(a), (b), (c))
 #endif
 
-/*
- * If this architecture has ISA IO, then define the isa_read/isa_write
- * macros.
- */
-#ifdef __mem_isa
-
-#define isa_readb(addr)                        __raw_readb(__mem_isa(addr))
-#define isa_readw(addr)                        __raw_readw(__mem_isa(addr))
-#define isa_readl(addr)                        __raw_readl(__mem_isa(addr))
-#define isa_writeb(val,addr)           __raw_writeb(val,__mem_isa(addr))
-#define isa_writew(val,addr)           __raw_writew(val,__mem_isa(addr))
-#define isa_writel(val,addr)           __raw_writel(val,__mem_isa(addr))
-#define isa_memset_io(a,b,c)           _memset_io(__mem_isa(a),(b),(c))
-#define isa_memcpy_fromio(a,b,c)       _memcpy_fromio((a),__mem_isa(b),(c))
-#define isa_memcpy_toio(a,b,c)         _memcpy_toio(__mem_isa((a)),(b),(c))
-
-#define isa_eth_io_copy_and_sum(a,b,c,d) \
-                               eth_copy_and_sum((a),__mem_isa(b),(c),(d))
-
-static inline int
-isa_check_signature(unsigned long io_addr, const unsigned char *signature,
-                   int length)
-{
-       int retval = 0;
-       do {
-               if (isa_readb(io_addr) != *signature)
-                       goto out;
-               io_addr++;
-               signature++;
-               length--;
-       } while (length);
-       retval = 1;
-out:
-       return retval;
-}
-
-#else  /* __mem_isa */
-
-#define isa_readb(addr)                        (__readwrite_bug("isa_readb"),0)
-#define isa_readw(addr)                        (__readwrite_bug("isa_readw"),0)
-#define isa_readl(addr)                        (__readwrite_bug("isa_readl"),0)
-#define isa_writeb(val,addr)           __readwrite_bug("isa_writeb")
-#define isa_writew(val,addr)           __readwrite_bug("isa_writew")
-#define isa_writel(val,addr)           __readwrite_bug("isa_writel")
-#define isa_memset_io(a,b,c)           __readwrite_bug("isa_memset_io")
-#define isa_memcpy_fromio(a,b,c)       __readwrite_bug("isa_memcpy_fromio")
-#define isa_memcpy_toio(a,b,c)         __readwrite_bug("isa_memcpy_toio")
-
-#define isa_eth_io_copy_and_sum(a,b,c,d) \
-                               __readwrite_bug("isa_eth_io_copy_and_sum")
-
-#define isa_check_signature(io,sig,len)        (0)
-
-#endif /* __mem_isa */
-#endif /* __KERNEL__ */
-
 #include <asm-generic/io.h>
 #include <iotrace.h>
 
index ec0171e..1a1edc9 100644 (file)
@@ -69,12 +69,10 @@ lr  .req    x30
  */
 .macro switch_el, xreg, el3_label, el2_label, el1_label
        mrs     \xreg, CurrentEL
-       cmp     \xreg, 0xc
-       b.eq    \el3_label
-       cmp     \xreg, 0x8
+       cmp     \xreg, #0x8
+       b.gt    \el3_label
        b.eq    \el2_label
-       cmp     \xreg, 0x4
-       b.eq    \el1_label
+       b.lt    \el1_label
 .endm
 
 /*
@@ -123,19 +121,10 @@ lr        .req    x30
  */
 .macro branch_if_slave, xreg, slave_label
 #ifdef CONFIG_ARMV8_MULTIENTRY
-       /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
        mrs     \xreg, mpidr_el1
-       tst     \xreg, #0xff            /* Test Affinity 0 */
-       b.ne    \slave_label
-       lsr     \xreg, \xreg, #8
-       tst     \xreg, #0xff            /* Test Affinity 1 */
-       b.ne    \slave_label
-       lsr     \xreg, \xreg, #8
-       tst     \xreg, #0xff            /* Test Affinity 2 */
-       b.ne    \slave_label
-       lsr     \xreg, \xreg, #16
-       tst     \xreg, #0xff            /* Test Affinity 3 */
-       b.ne    \slave_label
+       and     \xreg, \xreg,  0xffffffffff     /* clear bits [63:40] */
+       and     \xreg, \xreg, ~0x00ff000000     /* also clear bits [31:24] */
+       cbnz    \xreg, \slave_label
 #endif
 .endm
 
@@ -143,16 +132,12 @@ lr        .req    x30
  * Branch if current processor is a master,
  * choose processor with all zero affinity value as the master.
  */
-.macro branch_if_master, xreg1, xreg2, master_label
+.macro branch_if_master, xreg, master_label
 #ifdef CONFIG_ARMV8_MULTIENTRY
-       /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
-       mrs     \xreg1, mpidr_el1
-       lsr     \xreg2, \xreg1, #32
-       lsl     \xreg2, \xreg2, #32
-       lsl     \xreg1, \xreg1, #40
-       lsr     \xreg1, \xreg1, #40
-       orr     \xreg1, \xreg1, \xreg2
-       cbz     \xreg1, \master_label
+       mrs     \xreg, mpidr_el1
+       and     \xreg, \xreg,  0xffffffffff     /* clear bits [63:40] */
+       and     \xreg, \xreg, ~0x00ff000000     /* also clear bits [31:24] */
+       cbz     \xreg, \master_label
 #else
        b       \master_label
 #endif
index f75eea1..87d1c77 100644 (file)
@@ -82,6 +82,7 @@
 #define HCR_EL2_RW_AARCH64     (1 << 31) /* EL1 is AArch64                   */
 #define HCR_EL2_RW_AARCH32     (0 << 31) /* Lower levels are AArch32         */
 #define HCR_EL2_HCD_DIS                (1 << 29) /* Hypervisor Call disabled         */
+#define HCR_EL2_AMO_EL2                (1 <<  5) /* Route SErrors to EL2             */
 
 /*
  * ID_AA64ISAR1_EL1 bits definitions
index 6087d93..f73dbbb 100644 (file)
@@ -1,5 +1,9 @@
 if ARCH_EXYNOS
 
+config BOARD_COMMON
+       def_bool y
+       depends on !TARGET_SMDKV310 && !TARGET_ARNDALE
+
 choice
        prompt "EXYNOS architecture type select"
        optional
index 7224498..93fea9c 100644 (file)
 #include "common_setup.h"
 #include "clock_init.h"
 
+#ifdef CONFIG_ARCH_EXYNOS5
+#define SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef SECURE_BL1_ONLY
+#define SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define RES_BLOCK_SIZE (512)
+#define BL1_SIZE       (16 << 10) /*16 K reserved for BL1*/
+#define BL2_SIZE       (512UL << 10UL) /* 512 KB */
+
+#define BL1_OFFSET     (RES_BLOCK_SIZE + SEC_FW_SIZE)
+#define BL2_OFFSET     (BL1_OFFSET + BL1_SIZE)
+
+/* U-Boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET       (BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT    (BL2_SIZE/512)
+
+#define EXYNOS_COPY_SPI_FNPTR_ADDR     0x02020058
+#define SPI_FLASH_UBOOT_POS    (SEC_FW_SIZE + BL1_SIZE)
+#elif defined(CONFIG_ARCH_EXYNOS4)
+#define COPY_BL2_SIZE          0x80000
+#define BL2_START_OFFSET       ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define BL2_SIZE_BLOC_COUNT    (COPY_BL2_SIZE/512)
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Index into irom ptr table */
index ee5cc47..359f8c7 100644 (file)
@@ -8,6 +8,7 @@
 #include <cpu.h>
 #include <cpu_func.h>
 #include <dm.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <asm/cache.h>
@@ -66,7 +67,7 @@ int arch_cpu_init(void)
        return 0;
 }
 
-int arch_cpu_init_dm(void)
+static int imx8_init_mu(void *ctx, struct event *event)
 {
        struct udevice *devp;
        int node, ret;
@@ -88,6 +89,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
 
 int print_bootinfo(void)
 {
index 1a5a391..838f0a3 100644 (file)
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <cpu_func.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <asm/arch/imx-regs.h>
@@ -494,7 +495,7 @@ static void imx_set_wdog_powerdown(bool enable)
        writew(enable, &wdog3->wmcr);
 }
 
-int arch_cpu_init_dm(void)
+static int imx8m_check_clock(void *ctx, struct event *event)
 {
        struct udevice *dev;
        int ret;
@@ -511,6 +512,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
 
 int arch_cpu_init(void)
 {
index 934b0ef..e6d417e 100644 (file)
@@ -11,6 +11,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/global_data.h>
 #include <efi_loader.h>
+#include <event.h>
 #include <spl.h>
 #include <asm/arch/rdc.h>
 #include <asm/arch/s400_api.h>
@@ -569,7 +570,7 @@ int arch_cpu_init(void)
        return 0;
 }
 
-int arch_cpu_init_dm(void)
+static int imx8ulp_check_mu(void *ctx, struct event *event)
 {
        struct udevice *devp;
        int node, ret;
@@ -584,6 +585,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu);
 
 #if defined(CONFIG_SPL_BUILD)
 __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
index 7d487f2..e17a55a 100644 (file)
@@ -152,6 +152,7 @@ config TARGET_OCTEONTX2_CN913x
 
 config TARGET_DB_MV784MP_GP
        bool "Support db-mv784mp-gp"
+       select BOARD_ECC_SUPPORT
        select MV78460
 
 config TARGET_DS414
@@ -160,6 +161,7 @@ config TARGET_DS414
 
 config TARGET_MAXBCM
        bool "Support maxbcm"
+       select BOARD_ECC_SUPPORT
        select MV78460
 
 config TARGET_THEADORABLE
@@ -226,6 +228,9 @@ config DDR_RESET_ON_TRAINING_FAILURE
          device will still hang - it doesn't make sense to reset the board
          in such a case.
 
+config BOARD_ECC_SUPPORT
+       bool
+
 config SYS_BOARD
        default "clearfog" if TARGET_CLEARFOG
        default "helios4" if TARGET_HELIOS4
index c446676..bcc907c 100644 (file)
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <debug_uart.h>
 #include <errno.h>
+#include <event.h>
 #include <init.h>
 #include <net.h>
 #include <ns16550.h>
@@ -596,7 +597,7 @@ void board_init_f(ulong dummy)
 
 #endif
 
-int arch_cpu_init_dm(void)
+static int am33xx_dm_post_init(void *ctx, struct event *event)
 {
        hw_data_init();
 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
@@ -604,3 +605,4 @@ int arch_cpu_init_dm(void)
 #endif
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init);
index 3da50f9..c4a8eab 100644 (file)
@@ -12,6 +12,7 @@
  */
 #include <common.h>
 #include <debug_uart.h>
+#include <event.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <spl.h>
@@ -239,11 +240,13 @@ void board_init_f(ulong dummy)
 }
 #endif
 
-int arch_cpu_init_dm(void)
+static int omap2_system_init(void *ctx, struct event *event)
 {
        early_system_init();
+
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, omap2_system_init);
 
 /*
  * Routine: wait_for_command_complete
index 71f7349..13685e0 100644 (file)
@@ -23,7 +23,7 @@
  * get_sys_clk_speed() - determine reference oscillator speed
  *                       based on known 32kHz clock and gptimer.
  *****************************************************************************/
-u32 get_osc_clk_speed(void)
+static u32 get_osc_clk_speed(void)
 {
        u32 start, cstart, cend, cdiff, cdiv, val;
        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -90,7 +90,7 @@ u32 get_osc_clk_speed(void)
  * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
  *                       input oscillator clock frequency.
  *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+static void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
 {
        switch(osc_clk) {
        case S38_4M:
index 1df2c40..0d77800 100644 (file)
@@ -64,7 +64,7 @@ ENTRY(lowlevel_init)
 #endif
 #endif
 
-       branch_if_master x0, x1, 2f
+       branch_if_master x0, 2f
 
        /*
         * Slave should wait for master clearing spin table.
index 612ea8a..875927c 100644 (file)
@@ -38,7 +38,7 @@ slave_wait_atf:
 #endif
 
 #ifdef CONFIG_ARMV8_MULTIENTRY
-       branch_if_master x0, x1, 2f
+       branch_if_master x0, 2f
 
        /*
         * Slave should wait for master clearing spin table.
index d1c60d2..73da6b8 100644 (file)
@@ -332,9 +332,6 @@ config MACH_SUN9I
 config MACH_SUN50I
        bool "sun50i (Allwinner A64)"
        select ARM64
-       select SPI
-       select DM_SPI if SPI
-       select DM_SPI_FLASH
        select PHY_SUN4I_USB
        select SUN6I_PRCM
        select SUNXI_DE2
index 28234aa..06cae68 100644 (file)
@@ -130,6 +130,7 @@ config MACH_PIC32
 config TARGET_BOSTON
        bool "Support Boston"
        select DM
+       imply DM_EVENT
        select DM_SERIAL
        select MIPS_CM
        select SYS_CACHE_SHIFT_6
index eac2fe5..de449e3 100644 (file)
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
+#include <event.h>
 #include <init.h>
 #include <malloc.h>
 #include <asm/global_data.h>
@@ -95,12 +96,13 @@ static void prefetch_init(void)
 }
 
 /* arch specific CPU init after DM */
-int arch_cpu_init_dm(void)
+static int pic32_flash_prefetch(void *ctx, struct event *event)
 {
        /* flash prefetch */
        prefetch_init();
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, pic32_flash_prefetch);
 
 /* Un-gate DDR2 modules (gated by default) */
 static void ddr2_pmd_ungate(void)
index b55c8fb..4dd9c10 100644 (file)
@@ -10,6 +10,7 @@
 #include <cpu_func.h>
 #include <dm.h>
 #include <errno.h>
+#include <event.h>
 #include <init.h>
 #include <irq_func.h>
 #include <asm/cache.h>
@@ -63,7 +64,7 @@ static void copy_exception_trampoline(void)
 }
 #endif
 
-int arch_cpu_init_dm(void)
+static int nios_cpu_setup(void *ctx, struct event *event)
 {
        struct udevice *dev;
        int ret;
@@ -79,6 +80,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup);
 
 static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
                                 int size)
index c308447..a978eea 100644 (file)
@@ -317,6 +317,7 @@ config ARCH_MPC8540
 
 config ARCH_MPC8544
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_FSL_ERRATUM_A005125
@@ -330,6 +331,7 @@ config ARCH_MPC8544
 
 config ARCH_MPC8548
        bool
+       select BTB
        select FSL_LAW
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_NMG_DDR120
@@ -352,6 +354,7 @@ config ARCH_MPC8560
 
 config ARCH_P1010
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_HAS_SERDES
@@ -400,6 +403,7 @@ config ARCH_P1011
 
 config ARCH_P1020
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_FSL_ERRATUM_A004508
@@ -496,6 +500,7 @@ config ARCH_P1025
 
 config ARCH_P2020
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_FSL_ERRATUM_A004477
@@ -772,6 +777,9 @@ config MPC85XX_HAVE_RESET_VECTOR
        bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
        depends on MPC85xx
 
+config BTB
+       bool "toggle branch predition"
+
 config BOOKE
        bool
        default y
@@ -784,12 +792,14 @@ config E500
 
 config E500MC
        bool
+       select BTB
        imply CMD_PCI
        help
                Enble PowerPC E500MC core
 
 config E6500
        bool
+       select BTB
        help
                Enable PowerPC E6500 core
 
index 6f4ad1f..c32cde0 100644 (file)
@@ -27,7 +27,6 @@ obj-$(CONFIG_MP)      += release.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
 endif
-obj-$(CONFIG_CPM2)     += commproc.o
 
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_FSL_CORENET) += liodn.o
@@ -49,7 +48,6 @@ obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
 
 
 obj-$(CONFIG_QE)       += qe_io.o
-obj-$(CONFIG_CPM2)     += serial_scc.o
 obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c
deleted file mode 100644 (file)
index 8e8427a..0000000
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Adapted for Motorola MPC8560 chips
- * Xianghua Xiao <x.xiao@motorola.com>
- *
- * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
- * copyright notice:
- *
- * General Purpose functions for the global management of the
- * 8220 Communication Processor Module.
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
- *     2.3.99 Updates
- * Copyright (c) 2003 Motorola,Inc.
- *
- * In addition to the individual control of the communication
- * channels, there are a few functions that globally affect the
- * communication processor.
- *
- * Buffer descriptors must be allocated from the dual ported memory
- * space.  The allocator for that is here.  When the communication
- * process is reset, we reclaim the memory available.  There is
- * currently no deallocator for this memory.
- */
-#include <common.h>
-#include <asm-offsets.h>
-#include <asm/cpm_85xx.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * because we have stack and init data in dual port ram
- * we must reduce the size
- */
-#undef CPM_DATAONLY_SIZE
-#define CPM_DATAONLY_SIZE      ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-
-void
-m8560_cpm_reset(void)
-{
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       volatile ulong count;
-
-       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-       /* Reclaim the DP memory for our use.
-       */
-       gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
-       gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
-
-       /*
-        * Reset CPM
-        */
-       cpm->im_cpm_cp.cpcr = CPM_CR_RST;
-       count = 0;
-       do {                    /* Spin until command processed         */
-               __asm__ __volatile__ ("eieio");
-       } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
-}
-
-/* Allocate some memory from the dual ported ram.
- * To help protocols with object alignment restrictions, we do that
- * if they ask.
- */
-uint
-m8560_cpm_dpalloc(uint size, uint align)
-{
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       uint    retloc;
-       uint    align_mask, off;
-       uint    savebase;
-
-       align_mask = align - 1;
-       savebase = gd->arch.dp_alloc_base;
-
-       off = gd->arch.dp_alloc_base & align_mask;
-       if (off != 0)
-               gd->arch.dp_alloc_base += (align - off);
-
-       if ((off = size & align_mask) != 0)
-               size += align - off;
-
-       if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
-               gd->arch.dp_alloc_base = savebase;
-               panic("m8560_cpm_dpalloc: ran out of dual port ram!");
-       }
-
-       retloc = gd->arch.dp_alloc_base;
-       gd->arch.dp_alloc_base += size;
-
-       memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
-
-       return(retloc);
-}
-
-/* We also own one page of host buffer space for the allocation of
- * UART "fifos" and the like.
- */
-uint
-m8560_cpm_hostalloc(uint size, uint align)
-{
-       /* the host might not even have RAM yet - just use dual port RAM */
-       return (m8560_cpm_dpalloc(size, align));
-}
-
-/* Set a baud rate generator.  This needs lots of work.  There are
- * eight BRGs, which can be connected to the CPM channels or output
- * as clocks.  The BRGs are in two different block of internal
- * memory mapped space.
- * The baud rate clock is the system clock divided by something.
- * It was set up long ago during the initial boot phase and is
- * is given to us.
- * Baud rate clocks are zero-based in the driver code (as that maps
- * to port numbers).  Documentation uses 1-based numbering.
- */
-#define BRG_INT_CLK    gd->arch.brg_clk
-#define BRG_UART_CLK   ((BRG_INT_CLK + 15) / 16)
-
-/* This function is used by UARTS, or anything else that uses a 16x
- * oversampled clock.
- */
-void
-m8560_cpm_setbrg(uint brg, uint rate)
-{
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       volatile uint   *bp;
-
-       /* This is good enough to get SMCs running.....
-       */
-       if (brg < 4) {
-               bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
-       }
-       else {
-               bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
-               brg -= 4;
-       }
-       bp += brg;
-       *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
-}
-
-/* This function is used to set high speed synchronous baud rate
- * clocks.
- */
-void
-m8560_cpm_fastbrg(uint brg, uint rate, int div16)
-{
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       volatile uint   *bp;
-
-       /* This is good enough to get SMCs running.....
-       */
-       if (brg < 4) {
-               bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
-       }
-       else {
-               bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
-               brg -= 4;
-       }
-       bp += brg;
-       *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
-       if (div16)
-               *bp |= CPM_BRG_DIV16;
-}
-
-/* This function is used to set baud rate generators using an external
- * clock source and 16x oversampling.
- */
-
-void
-m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
-{
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       volatile uint   *bp;
-
-       if (brg < 4) {
-               bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
-       }
-       else {
-               bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
-               brg -= 4;
-       }
-       bp += brg;
-       *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
-       if (pinsel == 0)
-               *bp |= CPM_BRG_EXTC_CLK3_9;
-       else
-               *bp |= CPM_BRG_EXTC_CLK5_15;
-}
index cd32290..cc1d02d 100644 (file)
@@ -241,10 +241,6 @@ int checkcpu (void)
        printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
 #endif
 
-#ifdef CONFIG_CPM2
-       printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
-#endif
-
 #ifdef CONFIG_QE
        printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
 #endif
index e920e01..e9e133b 100644 (file)
@@ -152,70 +152,6 @@ static void config_qe_ioports(void)
 }
 #endif
 
-#ifdef CONFIG_CPM2
-void config_8560_ioports (volatile ccsr_cpm_t * cpm)
-{
-       int portnum;
-
-       for (portnum = 0; portnum < 4; portnum++) {
-               uint pmsk = 0,
-                    ppar = 0,
-                    psor = 0,
-                    pdir = 0,
-                    podr = 0,
-                    pdat = 0;
-               iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
-               iop_conf_t *eiopc = iopc + 32;
-               uint msk = 1;
-
-               /*
-                * NOTE:
-                * index 0 refers to pin 31,
-                * index 31 refers to pin 0
-                */
-               while (iopc < eiopc) {
-                       if (iopc->conf) {
-                               pmsk |= msk;
-                               if (iopc->ppar)
-                                       ppar |= msk;
-                               if (iopc->psor)
-                                       psor |= msk;
-                               if (iopc->pdir)
-                                       pdir |= msk;
-                               if (iopc->podr)
-                                       podr |= msk;
-                               if (iopc->pdat)
-                                       pdat |= msk;
-                       }
-
-                       msk <<= 1;
-                       iopc++;
-               }
-
-               if (pmsk != 0) {
-                       volatile ioport_t *iop = ioport_addr (cpm, portnum);
-                       uint tpmsk = ~pmsk;
-
-                       /*
-                        * the (somewhat confused) paragraph at the
-                        * bottom of page 35-5 warns that there might
-                        * be "unknown behaviour" when programming
-                        * PSORx and PDIRx, if PPARx = 1, so I
-                        * decided this meant I had to disable the
-                        * dedicated function first, and enable it
-                        * last.
-                        */
-                       iop->ppar &= tpmsk;
-                       iop->psor = (iop->psor & tpmsk) | psor;
-                       iop->podr = (iop->podr & tpmsk) | podr;
-                       iop->pdat = (iop->pdat & tpmsk) | pdat;
-                       iop->pdir = (iop->pdir & tpmsk) | pdir;
-                       iop->ppar |= ppar;
-               }
-       }
-}
-#endif
-
 #ifdef CONFIG_SYS_FSL_CPC
 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
 void disable_cpc_sram(void)
@@ -474,16 +410,8 @@ ulong cpu_init_f(void)
 #endif
 #endif
 
-#ifdef CONFIG_CPM2
-       config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
-#endif
-
        init_early_memctl_regs();
 
-#if defined(CONFIG_CPM2)
-       m8560_cpm_reset();
-#endif
-
 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
        /* Config QE ioports */
        config_qe_ioports();
index d4b828e..c8ad6a1 100644 (file)
@@ -652,14 +652,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
                "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
-#ifdef CONFIG_CPM2
-       do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
-               "current-speed", gd->baudrate, 1);
-
-       do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
-               "clock-frequency", bd->bi_brgfreq, 1);
-#endif
-
 #ifdef CONFIG_FSL_CORENET
        do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
                "clock-frequency", get_board_sys_clk(), 1);
diff --git a/arch/powerpc/cpu/mpc85xx/serial_scc.c b/arch/powerpc/cpu/mpc85xx/serial_scc.c
deleted file mode 100644 (file)
index a2505d1..0000000
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao (X.Xiao@motorola.com)
- * Modified based on 8260 for 8560.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
- */
-
-/*
- * Minimal serial functions needed to use one of the SCC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <asm/cpm_85xx.h>
-#include <serial.h>
-#include <asm/global_data.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONS_ON_SCC)
-
-#if CONFIG_CONS_INDEX == 1     /* Console on SCC1 */
-
-#define SCC_INDEX              0
-#define PROFF_SCC              PROFF_SCC1
-#define CMXSCR_MASK            (CMXSCR_GR1|CMXSCR_SC1|\
-                                       CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
-#define CMXSCR_VALUE           (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
-#define CPM_CR_SCC_PAGE                CPM_CR_SCC1_PAGE
-#define CPM_CR_SCC_SBLOCK      CPM_CR_SCC1_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 2   /* Console on SCC2 */
-
-#define SCC_INDEX              1
-#define PROFF_SCC              PROFF_SCC2
-#define CMXSCR_MASK            (CMXSCR_GR2|CMXSCR_SC2|\
-                                       CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
-#define CMXSCR_VALUE           (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
-#define CPM_CR_SCC_PAGE                CPM_CR_SCC2_PAGE
-#define CPM_CR_SCC_SBLOCK      CPM_CR_SCC2_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 3   /* Console on SCC3 */
-
-#define SCC_INDEX              2
-#define PROFF_SCC              PROFF_SCC3
-#define CMXSCR_MASK            (CMXSCR_GR3|CMXSCR_SC3|\
-                                       CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
-#define CMXSCR_VALUE           (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
-#define CPM_CR_SCC_PAGE                CPM_CR_SCC3_PAGE
-#define CPM_CR_SCC_SBLOCK      CPM_CR_SCC3_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 4   /* Console on SCC4 */
-
-#define SCC_INDEX              3
-#define PROFF_SCC              PROFF_SCC4
-#define CMXSCR_MASK            (CMXSCR_GR4|CMXSCR_SC4|\
-                                       CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
-#define CMXSCR_VALUE           (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
-#define CPM_CR_SCC_PAGE                CPM_CR_SCC4_PAGE
-#define CPM_CR_SCC_SBLOCK      CPM_CR_SCC4_SBLOCK
-
-#else
-
-#error "console not correctly defined"
-
-#endif
-
-static int mpc85xx_serial_init(void)
-{
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       volatile ccsr_cpm_scc_t *sp;
-       volatile scc_uart_t *up;
-       volatile cbd_t *tbdf, *rbdf;
-       volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
-       uint    dpaddr;
-
-       /* initialize pointers to SCC */
-
-       sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
-       up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-
-       /* Disable transmitter/receiver.
-       */
-       sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-       /* put the SCC channel into NMSI (non multiplexd serial interface)
-        * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
-        */
-       cpm->im_cpm_mux.cmxscr = \
-               (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
-
-       /* Set up the baud rate generator.
-       */
-       serial_setbrg ();
-
-       /* Allocate space for two buffer descriptors in the DP ram.
-        * damm: allocating space after the two buffers for rx/tx data
-        */
-
-       dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
-
-       /* Set the physical address of the host memory buffers in
-        * the buffer descriptors.
-        */
-       rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
-       rbdf->cbd_bufaddr = (uint) (rbdf+2);
-       rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
-       tbdf = rbdf + 1;
-       tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-       tbdf->cbd_sc = BD_SC_WRAP;
-
-       /* Set up the uart parameters in the parameter ram.
-       */
-       up->scc_genscc.scc_rbase = dpaddr;
-       up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
-       up->scc_genscc.scc_rfcr = CPMFCR_EB;
-       up->scc_genscc.scc_tfcr = CPMFCR_EB;
-       up->scc_genscc.scc_mrblr = 1;
-       up->scc_maxidl = 0;
-       up->scc_brkcr = 1;
-       up->scc_parec = 0;
-       up->scc_frmec = 0;
-       up->scc_nosec = 0;
-       up->scc_brkec = 0;
-       up->scc_uaddr1 = 0;
-       up->scc_uaddr2 = 0;
-       up->scc_toseq = 0;
-       up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
-       up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
-       up->scc_rccm = 0xc0ff;
-
-       /* Mask all interrupts and remove anything pending.
-       */
-       sp->sccm = 0;
-       sp->scce = 0xffff;
-
-       /* Set 8 bit FIFO, 16 bit oversampling and UART mode.
-       */
-       sp->gsmrh = SCC_GSMRH_RFW;      /* 8 bit FIFO */
-       sp->gsmrl = \
-               SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
-
-       /* Set CTS no flow control, 1 stop bit, 8 bit character length,
-        * normal async UART mode, no parity
-        */
-       sp->psmr = SCU_PSMR_CL;
-
-       /* execute the "Init Rx and Tx params" CP command.
-       */
-
-       while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-         ;
-
-       cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
-                                       0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-       while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-         ;
-
-       /* Enable transmitter/receiver.
-       */
-       sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
-
-       return (0);
-}
-
-static void mpc85xx_serial_setbrg(void)
-{
-#if defined(CONFIG_CONS_USE_EXTC)
-       m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
-               CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
-#else
-       m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
-#endif
-}
-
-static void mpc85xx_serial_putc(const char c)
-{
-       volatile scc_uart_t     *up;
-       volatile cbd_t          *tbdf;
-       volatile ccsr_cpm_t     *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-
-       if (c == '\n')
-               serial_putc ('\r');
-
-       up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-       tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
-
-       /* Wait for last character to go.
-        */
-       while (tbdf->cbd_sc & BD_SC_READY)
-               ;
-
-       /* Load the character into the transmit buffer.
-        */
-       *(volatile char *)tbdf->cbd_bufaddr = c;
-       tbdf->cbd_datlen = 1;
-       tbdf->cbd_sc |= BD_SC_READY;
-}
-
-static int mpc85xx_serial_getc(void)
-{
-       volatile cbd_t          *rbdf;
-       volatile scc_uart_t     *up;
-       volatile ccsr_cpm_t     *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       unsigned char           c;
-
-       up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-       rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
-
-       /* Wait for character to show up.
-        */
-       while (rbdf->cbd_sc & BD_SC_EMPTY)
-               ;
-
-       /* Grab the char and clear the buffer again.
-        */
-       c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
-       rbdf->cbd_sc |= BD_SC_EMPTY;
-
-       return (c);
-}
-
-static int mpc85xx_serial_tstc(void)
-{
-       volatile cbd_t          *rbdf;
-       volatile scc_uart_t     *up;
-       volatile ccsr_cpm_t     *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-
-       up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-       rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
-
-       return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
-}
-
-static struct serial_device mpc85xx_serial_drv = {
-       .name   = "mpc85xx_serial",
-       .start  = mpc85xx_serial_init,
-       .stop   = NULL,
-       .setbrg = mpc85xx_serial_setbrg,
-       .putc   = mpc85xx_serial_putc,
-       .puts   = default_serial_puts,
-       .getc   = mpc85xx_serial_getc,
-       .tstc   = mpc85xx_serial_tstc,
-};
-
-void mpc85xx_serial_initialize(void)
-{
-       serial_register(&mpc85xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-       return &mpc85xx_serial_drv;
-}
-#endif /* CONFIG_CONS_ON_SCC */
index 5a9cd28..4b6f3d2 100644 (file)
@@ -581,15 +581,6 @@ int get_clocks(void)
 #ifdef CONFIG_ARCH_MPC8544
        volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 #endif
-#if defined(CONFIG_CPM2)
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       uint sccr, dfbrg;
-
-       /* set VCO = 4 * BRG */
-       cpm->im_cpm_intctl.sccr &= 0xfffffffc;
-       sccr = cpm->im_cpm_intctl.sccr;
-       dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
-#endif
        get_sys_info (&sys_info);
        gd->cpu_clk = sys_info.freq_processor[0];
        gd->bus_clk = sys_info.freq_systembus;
@@ -635,13 +626,6 @@ int get_clocks(void)
 #endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
-#if defined(CONFIG_CPM2)
-       gd->arch.vco_out = 2*sys_info.freq_systembus;
-       gd->arch.cpm_clk = gd->arch.vco_out / 2;
-       gd->arch.scc_clk = gd->arch.vco_out / 4;
-       gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
-#endif
-
        if(gd->cpu_clk != 0) return (0);
        else return (1);
 }
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
deleted file mode 100644 (file)
index d42469c..0000000
+++ /dev/null
@@ -1,824 +0,0 @@
-/*
- * MPC85xx Communication Processor Module
- * Copyright (c) 2003,Motorola Inc.
- * Xianghua Xiao (X.Xiao@motorola.com)
- *
- * MPC8260 Communication Processor Module.
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * This file contains structures and information for the communication
- * processor channels found in the dual port RAM or parameter RAM.
- * All CPM control and status is available through the MPC8260 internal
- * memory map.  See immap.h for details.
- */
-#ifndef __CPM_85XX__
-#define __CPM_85XX__
-
-#include <asm/immap_85xx.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST     ((uint)0x80000000)
-#define CPM_CR_PAGE    ((uint)0x7c000000)
-#define CPM_CR_SBLOCK  ((uint)0x03e00000)
-#define CPM_CR_FLG     ((uint)0x00010000)
-#define CPM_CR_MCN     ((uint)0x00003fc0)
-#define CPM_CR_OPCODE  ((uint)0x0000000f)
-
-/* Device sub-block and page codes.
-*/
-#define CPM_CR_SCC1_SBLOCK     (0x04)
-#define CPM_CR_SCC2_SBLOCK     (0x05)
-#define CPM_CR_SCC3_SBLOCK     (0x06)
-#define CPM_CR_SCC4_SBLOCK     (0x07)
-#define CPM_CR_SMC1_SBLOCK     (0x08)
-#define CPM_CR_SMC2_SBLOCK     (0x09)
-#define CPM_CR_SPI_SBLOCK      (0x0a)
-#define CPM_CR_I2C_SBLOCK      (0x0b)
-#define CPM_CR_TIMER_SBLOCK    (0x0f)
-#define CPM_CR_RAND_SBLOCK     (0x0e)
-#define CPM_CR_FCC1_SBLOCK     (0x10)
-#define CPM_CR_FCC2_SBLOCK     (0x11)
-#define CPM_CR_FCC3_SBLOCK     (0x12)
-#define CPM_CR_MCC1_SBLOCK     (0x1c)
-
-#define CPM_CR_SCC1_PAGE       (0x00)
-#define CPM_CR_SCC2_PAGE       (0x01)
-#define CPM_CR_SCC3_PAGE       (0x02)
-#define CPM_CR_SCC4_PAGE       (0x03)
-#define CPM_CR_SPI_PAGE                (0x09)
-#define CPM_CR_I2C_PAGE                (0x0a)
-#define CPM_CR_TIMER_PAGE      (0x0a)
-#define CPM_CR_RAND_PAGE       (0x0a)
-#define CPM_CR_FCC1_PAGE       (0x04)
-#define CPM_CR_FCC2_PAGE       (0x05)
-#define CPM_CR_FCC3_PAGE       (0x06)
-#define CPM_CR_MCC1_PAGE       (0x07)
-#define CPM_CR_MCC2_PAGE       (0x08)
-
-/* Some opcodes (there are more...later)
-*/
-#define CPM_CR_INIT_TRX                ((ushort)0x0000)
-#define CPM_CR_INIT_RX         ((ushort)0x0001)
-#define CPM_CR_INIT_TX         ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE       ((ushort)0x0003)
-#define CPM_CR_STOP_TX         ((ushort)0x0004)
-#define CPM_CR_RESTART_TX      ((ushort)0x0006)
-#define CPM_CR_SET_GADDR       ((ushort)0x0008)
-
-#define mk_cr_cmd(PG, SBC, MCN, OP) \
-       ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
-
-/* Dual Port RAM addresses.  The first 16K is available for almost
- * any CPM use, so we put the BDs there.  The first 128 bytes are
- * used for SMC1 and SMC2 parameter RAM, so we start allocating
- * BDs above that.  All of this must change when we start
- * downloading RAM microcode.
- */
-#define CPM_DATAONLY_BASE      ((uint)128)
-#define CPM_DP_NOSPACE         ((uint)0x7FFFFFFF)
-#define CPM_FCC_SPECIAL_BASE   ((uint)0x0000B000)
-#define CPM_DATAONLY_SIZE      ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-
-/* The number of pages of host memory we allocate for CPM.  This is
- * done early in kernel initialization to get physically contiguous
- * pages.
- */
-#define NUM_CPM_HOST_PAGES     2
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-/*extern       cpm8560_t       *cpmp;   Pointer to comm processor */
-uint           m8560_cpm_dpalloc(uint size, uint align);
-uint           m8560_cpm_hostalloc(uint size, uint align);
-void           m8560_cpm_setbrg(uint brg, uint rate);
-void           m8560_cpm_fastbrg(uint brg, uint rate, int div16);
-void           m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-       ushort  cbd_sc;         /* Status and Control */
-       ushort  cbd_datlen;     /* Data length in buffer */
-       uint    cbd_bufaddr;    /* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY    ((ushort)0x8000)        /* Receive is empty */
-#define BD_SC_READY    ((ushort)0x8000)        /* Transmit is ready */
-#define BD_SC_WRAP     ((ushort)0x2000)        /* Last buffer descriptor */
-#define BD_SC_INTRPT   ((ushort)0x1000)        /* Interrupt on change */
-#define BD_SC_LAST     ((ushort)0x0800)        /* Last buffer in frame */
-#define BD_SC_CM       ((ushort)0x0200)        /* Continous mode */
-#define BD_SC_ID       ((ushort)0x0100)        /* Rec'd too many idles */
-#define BD_SC_P                ((ushort)0x0100)        /* xmt preamble */
-#define BD_SC_BR       ((ushort)0x0020)        /* Break received */
-#define BD_SC_FR       ((ushort)0x0010)        /* Framing error */
-#define BD_SC_PR       ((ushort)0x0008)        /* Parity error */
-#define BD_SC_OV       ((ushort)0x0002)        /* Overrun */
-#define BD_SC_CD       ((ushort)0x0001)        /* ?? */
-
-/* Function code bits, usually generic to devices.
-*/
-#define CPMFCR_GBL     ((u_char)0x20)  /* Set memory snooping */
-#define CPMFCR_EB      ((u_char)0x10)  /* Set big endian byte order */
-#define CPMFCR_TC2     ((u_char)0x04)  /* Transfer code 2 value */
-#define CPMFCR_DTB     ((u_char)0x02)  /* Use local bus for data when set */
-#define CPMFCR_BDB     ((u_char)0x01)  /* Use local bus for BD when set */
-
-/* Parameter RAM offsets from the base.
-*/
-#define CPM_POST_WORD_ADDR      0x80FC /* steal a long at the end of SCC1 */
-#define PROFF_SCC1             ((uint)0x8000)
-#define PROFF_SCC2             ((uint)0x8100)
-#define PROFF_SCC3             ((uint)0x8200)
-#define PROFF_SCC4             ((uint)0x8300)
-#define PROFF_FCC1             ((uint)0x8400)
-#define PROFF_FCC2             ((uint)0x8500)
-#define PROFF_FCC3             ((uint)0x8600)
-#define PROFF_MCC1             ((uint)0x8700)
-#define PROFF_MCC2             ((uint)0x8800)
-#define PROFF_SPI_BASE         ((uint)0x89fc)
-#define PROFF_TIMERS           ((uint)0x8ae0)
-#define PROFF_REVNUM           ((uint)0x8af0)
-#define PROFF_RAND             ((uint)0x8af8)
-#define PROFF_I2C_BASE         ((uint)0x8afc)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST            ((uint)0x00020000)
-#define CPM_BRG_EN             ((uint)0x00010000)
-#define CPM_BRG_EXTC_INT       ((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK3_9    ((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK5_15   ((uint)0x00008000)
-#define CPM_BRG_ATB            ((uint)0x00002000)
-#define CPM_BRG_CD_MASK                ((uint)0x00001ffe)
-#define CPM_BRG_DIV16          ((uint)0x00000001)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP          ((uint)0x00040000)
-#define SCC_GSMRH_GDE          ((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT   ((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC  ((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC    ((uint)0x00000000)
-#define SCC_GSMRH_REVD         ((uint)0x00002000)
-#define SCC_GSMRH_TRX          ((uint)0x00001000)
-#define SCC_GSMRH_TTX          ((uint)0x00000800)
-#define SCC_GSMRH_CDP          ((uint)0x00000400)
-#define SCC_GSMRH_CTSP         ((uint)0x00000200)
-#define SCC_GSMRH_CDS          ((uint)0x00000100)
-#define SCC_GSMRH_CTSS         ((uint)0x00000080)
-#define SCC_GSMRH_TFL          ((uint)0x00000040)
-#define SCC_GSMRH_RFW          ((uint)0x00000020)
-#define SCC_GSMRH_TXSY         ((uint)0x00000010)
-#define SCC_GSMRH_SYNL16       ((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8                ((uint)0x00000008)
-#define SCC_GSMRH_SYNL4                ((uint)0x00000004)
-#define SCC_GSMRH_RTSM         ((uint)0x00000002)
-#define SCC_GSMRH_RSYN         ((uint)0x00000001)
-
-#define SCC_GSMRL_SIR          ((uint)0x80000000)      /* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE    ((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG     ((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS     ((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH    ((uint)0x00000000)
-#define SCC_GSMRL_TCI          ((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3       ((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4       ((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14      ((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF     ((uint)0x00000000)
-#define SCC_GSMRL_RINV         ((uint)0x02000000)
-#define SCC_GSMRL_TINV         ((uint)0x01000000)
-#define SCC_GSMRL_TPL_128      ((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64       ((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48       ((uint)0x00800000)
-#define SCC_GSMRL_TPL_32       ((uint)0x00600000)
-#define SCC_GSMRL_TPL_16       ((uint)0x00400000)
-#define SCC_GSMRL_TPL_8                ((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE     ((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1     ((uint)0x00180000)
-#define SCC_GSMRL_TPP_01       ((uint)0x00100000)
-#define SCC_GSMRL_TPP_10       ((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS    ((uint)0x00000000)
-#define SCC_GSMRL_TEND         ((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32      ((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16      ((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8       ((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1       ((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32      ((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16      ((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8       ((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1       ((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN   ((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH   ((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0     ((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI    ((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ     ((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN   ((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH   ((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0     ((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI    ((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ     ((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE      ((uint)0x000000c0)      /* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO    ((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP    ((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM    ((uint)0x00000000)
-#define SCC_GSMRL_ENR          ((uint)0x00000020)
-#define SCC_GSMRL_ENT          ((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET    ((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP   ((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC  ((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14     ((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC   ((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS        ((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART    ((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7     ((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK   ((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC    ((uint)0x00000000)
-
-#define SCC_TODR_TOD           ((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define        SCCM_TXE        ((unsigned char)0x10)
-#define        SCCM_BSY        ((unsigned char)0x04)
-#define        SCCM_TX         ((unsigned char)0x02)
-#define        SCCM_RX         ((unsigned char)0x01)
-
-typedef struct scc_param {
-       ushort  scc_rbase;      /* Rx Buffer descriptor base address */
-       ushort  scc_tbase;      /* Tx Buffer descriptor base address */
-       u_char  scc_rfcr;       /* Rx function code */
-       u_char  scc_tfcr;       /* Tx function code */
-       ushort  scc_mrblr;      /* Max receive buffer length */
-       uint    scc_rstate;     /* Internal */
-       uint    scc_idp;        /* Internal */
-       ushort  scc_rbptr;      /* Internal */
-       ushort  scc_ibc;        /* Internal */
-       uint    scc_rxtmp;      /* Internal */
-       uint    scc_tstate;     /* Internal */
-       uint    scc_tdp;        /* Internal */
-       ushort  scc_tbptr;      /* Internal */
-       ushort  scc_tbc;        /* Internal */
-       uint    scc_txtmp;      /* Internal */
-       uint    scc_rcrc;       /* Internal */
-       uint    scc_tcrc;       /* Internal */
-} sccp_t;
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-       sccp_t  sen_genscc;
-       uint    sen_cpres;      /* Preset CRC */
-       uint    sen_cmask;      /* Constant mask for CRC */
-       uint    sen_crcec;      /* CRC Error counter */
-       uint    sen_alec;       /* alignment error counter */
-       uint    sen_disfc;      /* discard frame counter */
-       ushort  sen_pads;       /* Tx short frame pad character */
-       ushort  sen_retlim;     /* Retry limit threshold */
-       ushort  sen_retcnt;     /* Retry limit counter */
-       ushort  sen_maxflr;     /* maximum frame length register */
-       ushort  sen_minflr;     /* minimum frame length register */
-       ushort  sen_maxd1;      /* maximum DMA1 length */
-       ushort  sen_maxd2;      /* maximum DMA2 length */
-       ushort  sen_maxd;       /* Rx max DMA */
-       ushort  sen_dmacnt;     /* Rx DMA counter */
-       ushort  sen_maxb;       /* Max BD byte count */
-       ushort  sen_gaddr1;     /* Group address filter */
-       ushort  sen_gaddr2;
-       ushort  sen_gaddr3;
-       ushort  sen_gaddr4;
-       uint    sen_tbuf0data0; /* Save area 0 - current frame */
-       uint    sen_tbuf0data1; /* Save area 1 - current frame */
-       uint    sen_tbuf0rba;   /* Internal */
-       uint    sen_tbuf0crc;   /* Internal */
-       ushort  sen_tbuf0bcnt;  /* Internal */
-       ushort  sen_paddrh;     /* physical address (MSB) */
-       ushort  sen_paddrm;
-       ushort  sen_paddrl;     /* physical address (LSB) */
-       ushort  sen_pper;       /* persistence */
-       ushort  sen_rfbdptr;    /* Rx first BD pointer */
-       ushort  sen_tfbdptr;    /* Tx first BD pointer */
-       ushort  sen_tlbdptr;    /* Tx last BD pointer */
-       uint    sen_tbuf1data0; /* Save area 0 - current frame */
-       uint    sen_tbuf1data1; /* Save area 1 - current frame */
-       uint    sen_tbuf1rba;   /* Internal */
-       uint    sen_tbuf1crc;   /* Internal */
-       ushort  sen_tbuf1bcnt;  /* Internal */
-       ushort  sen_txlen;      /* Tx Frame length counter */
-       ushort  sen_iaddr1;     /* Individual address filter */
-       ushort  sen_iaddr2;
-       ushort  sen_iaddr3;
-       ushort  sen_iaddr4;
-       ushort  sen_boffcnt;    /* Backoff counter */
-
-       /* NOTE: Some versions of the manual have the following items
-        * incorrectly documented.  Below is the proper order.
-        */
-       ushort  sen_taddrh;     /* temp address (MSB) */
-       ushort  sen_taddrm;
-       ushort  sen_taddrl;     /* temp address (LSB) */
-} scc_enet_t;
-
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA  ((ushort)0x0080)        /* Graceful stop complete */
-#define SCCE_ENET_TXE  ((ushort)0x0010)        /* Transmit Error */
-#define SCCE_ENET_RXF  ((ushort)0x0008)        /* Full frame received */
-#define SCCE_ENET_BSY  ((ushort)0x0004)        /* All incoming buffers full */
-#define SCCE_ENET_TXB  ((ushort)0x0002)        /* A buffer was transmitted */
-#define SCCE_ENET_RXB  ((ushort)0x0001)        /* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC   ((ushort)0x8000)        /* Enable heartbeat */
-#define SCC_PSMR_FC    ((ushort)0x4000)        /* Force collision */
-#define SCC_PSMR_RSH   ((ushort)0x2000)        /* Receive short frames */
-#define SCC_PSMR_IAM   ((ushort)0x1000)        /* Check individual hash */
-#define SCC_PSMR_ENCRC ((ushort)0x0800)        /* Ethernet CRC mode */
-#define SCC_PSMR_PRO   ((ushort)0x0200)        /* Promiscuous mode */
-#define SCC_PSMR_BRO   ((ushort)0x0100)        /* Catch broadcast pkts */
-#define SCC_PSMR_SBT   ((ushort)0x0080)        /* Special backoff timer */
-#define SCC_PSMR_LPB   ((ushort)0x0040)        /* Set Loopback mode */
-#define SCC_PSMR_SIP   ((ushort)0x0020)        /* Sample Input Pins */
-#define SCC_PSMR_LCW   ((ushort)0x0010)        /* Late collision window */
-#define SCC_PSMR_NIB22 ((ushort)0x000a)        /* Start frame search */
-#define SCC_PSMR_FDE   ((ushort)0x0001)        /* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY       ((ushort)0x8000)
-#define BD_ENET_RX_WRAP                ((ushort)0x2000)
-#define BD_ENET_RX_INTR                ((ushort)0x1000)
-#define BD_ENET_RX_LAST                ((ushort)0x0800)
-#define BD_ENET_RX_FIRST       ((ushort)0x0400)
-#define BD_ENET_RX_MISS                ((ushort)0x0100)
-#define BD_ENET_RX_BC          ((ushort)0x0080)        /* FCC Only */
-#define BD_ENET_RX_MC          ((ushort)0x0040)        /* FCC Only */
-#define BD_ENET_RX_LG          ((ushort)0x0020)
-#define BD_ENET_RX_NO          ((ushort)0x0010)
-#define BD_ENET_RX_SH          ((ushort)0x0008)
-#define BD_ENET_RX_CR          ((ushort)0x0004)
-#define BD_ENET_RX_OV          ((ushort)0x0002)
-#define BD_ENET_RX_CL          ((ushort)0x0001)
-#define BD_ENET_RX_STATS       ((ushort)0x01ff)        /* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY       ((ushort)0x8000)
-#define BD_ENET_TX_PAD         ((ushort)0x4000)
-#define BD_ENET_TX_WRAP                ((ushort)0x2000)
-#define BD_ENET_TX_INTR                ((ushort)0x1000)
-#define BD_ENET_TX_LAST                ((ushort)0x0800)
-#define BD_ENET_TX_TC          ((ushort)0x0400)
-#define BD_ENET_TX_DEF         ((ushort)0x0200)
-#define BD_ENET_TX_HB          ((ushort)0x0100)
-#define BD_ENET_TX_LC          ((ushort)0x0080)
-#define BD_ENET_TX_RL          ((ushort)0x0040)
-#define BD_ENET_TX_RCMASK      ((ushort)0x003c)
-#define BD_ENET_TX_UN          ((ushort)0x0002)
-#define BD_ENET_TX_CSL         ((ushort)0x0001)
-#define BD_ENET_TX_STATS       ((ushort)0x03ff)        /* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-       sccp_t  scc_genscc;
-       uint    scc_res1;       /* Reserved */
-       uint    scc_res2;       /* Reserved */
-       ushort  scc_maxidl;     /* Maximum idle chars */
-       ushort  scc_idlc;       /* temp idle counter */
-       ushort  scc_brkcr;      /* Break count register */
-       ushort  scc_parec;      /* receive parity error counter */
-       ushort  scc_frmec;      /* receive framing error counter */
-       ushort  scc_nosec;      /* receive noise counter */
-       ushort  scc_brkec;      /* receive break condition counter */
-       ushort  scc_brkln;      /* last received break length */
-       ushort  scc_uaddr1;     /* UART address character 1 */
-       ushort  scc_uaddr2;     /* UART address character 2 */
-       ushort  scc_rtemp;      /* Temp storage */
-       ushort  scc_toseq;      /* Transmit out of sequence char */
-       ushort  scc_char1;      /* control character 1 */
-       ushort  scc_char2;      /* control character 2 */
-       ushort  scc_char3;      /* control character 3 */
-       ushort  scc_char4;      /* control character 4 */
-       ushort  scc_char5;      /* control character 5 */
-       ushort  scc_char6;      /* control character 6 */
-       ushort  scc_char7;      /* control character 7 */
-       ushort  scc_char8;      /* control character 8 */
-       ushort  scc_rccm;       /* receive control character mask */
-       ushort  scc_rccr;       /* receive control character register */
-       ushort  scc_rlbc;       /* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR          ((ushort)0x1000)
-#define UART_SCCM_GLT          ((ushort)0x0800)
-#define UART_SCCM_AB           ((ushort)0x0200)
-#define UART_SCCM_IDL          ((ushort)0x0100)
-#define UART_SCCM_GRA          ((ushort)0x0080)
-#define UART_SCCM_BRKE         ((ushort)0x0040)
-#define UART_SCCM_BRKS         ((ushort)0x0020)
-#define UART_SCCM_CCR          ((ushort)0x0008)
-#define UART_SCCM_BSY          ((ushort)0x0004)
-#define UART_SCCM_TX           ((ushort)0x0002)
-#define UART_SCCM_RX           ((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC           ((ushort)0x8000)
-#define SCU_PSMR_SL            ((ushort)0x4000)
-#define SCU_PSMR_CL            ((ushort)0x3000)
-#define SCU_PSMR_UM            ((ushort)0x0c00)
-#define SCU_PSMR_FRZ           ((ushort)0x0200)
-#define SCU_PSMR_RZS           ((ushort)0x0100)
-#define SCU_PSMR_SYN           ((ushort)0x0080)
-#define SCU_PSMR_DRT           ((ushort)0x0040)
-#define SCU_PSMR_PEN           ((ushort)0x0010)
-#define SCU_PSMR_RPM           ((ushort)0x000c)
-#define SCU_PSMR_REVP          ((ushort)0x0008)
-#define SCU_PSMR_TPM           ((ushort)0x0003)
-#define SCU_PSMR_TEVP          ((ushort)0x0003)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-       sccp_t  st_genscc;
-       uint    st_cpres;       /* Preset CRC */
-       uint    st_cmask;       /* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST         ((ushort)0x0800)
-
-/* How about some FCCs.....
-*/
-#define FCC_GFMR_DIAG_NORM     ((uint)0x00000000)
-#define FCC_GFMR_DIAG_LE       ((uint)0x40000000)
-#define FCC_GFMR_DIAG_AE       ((uint)0x80000000)
-#define FCC_GFMR_DIAG_ALE      ((uint)0xc0000000)
-#define FCC_GFMR_TCI           ((uint)0x20000000)
-#define FCC_GFMR_TRX           ((uint)0x10000000)
-#define FCC_GFMR_TTX           ((uint)0x08000000)
-#define FCC_GFMR_TTX           ((uint)0x08000000)
-#define FCC_GFMR_CDP           ((uint)0x04000000)
-#define FCC_GFMR_CTSP          ((uint)0x02000000)
-#define FCC_GFMR_CDS           ((uint)0x01000000)
-#define FCC_GFMR_CTSS          ((uint)0x00800000)
-#define FCC_GFMR_SYNL_NONE     ((uint)0x00000000)
-#define FCC_GFMR_SYNL_AUTO     ((uint)0x00004000)
-#define FCC_GFMR_SYNL_8                ((uint)0x00008000)
-#define FCC_GFMR_SYNL_16       ((uint)0x0000c000)
-#define FCC_GFMR_RTSM          ((uint)0x00002000)
-#define FCC_GFMR_RENC_NRZ      ((uint)0x00000000)
-#define FCC_GFMR_RENC_NRZI     ((uint)0x00000800)
-#define FCC_GFMR_REVD          ((uint)0x00000400)
-#define FCC_GFMR_TENC_NRZ      ((uint)0x00000000)
-#define FCC_GFMR_TENC_NRZI     ((uint)0x00000100)
-#define FCC_GFMR_TCRC_16       ((uint)0x00000000)
-#define FCC_GFMR_TCRC_32       ((uint)0x00000080)
-#define FCC_GFMR_ENR           ((uint)0x00000020)
-#define FCC_GFMR_ENT           ((uint)0x00000010)
-#define FCC_GFMR_MODE_ENET     ((uint)0x0000000c)
-#define FCC_GFMR_MODE_ATM      ((uint)0x0000000a)
-#define FCC_GFMR_MODE_HDLC     ((uint)0x00000000)
-
-/* Generic FCC parameter ram.
-*/
-typedef struct fcc_param {
-       ushort  fcc_riptr;      /* Rx Internal temp pointer */
-       ushort  fcc_tiptr;      /* Tx Internal temp pointer */
-       ushort  fcc_res1;
-       ushort  fcc_mrblr;      /* Max receive buffer length, mod 32 bytes */
-       uint    fcc_rstate;     /* Upper byte is Func code, must be set */
-       uint    fcc_rbase;      /* Receive BD base */
-       ushort  fcc_rbdstat;    /* RxBD status */
-       ushort  fcc_rbdlen;     /* RxBD down counter */
-       uint    fcc_rdptr;      /* RxBD internal data pointer */
-       uint    fcc_tstate;     /* Upper byte is Func code, must be set */
-       uint    fcc_tbase;      /* Transmit BD base */
-       ushort  fcc_tbdstat;    /* TxBD status */
-       ushort  fcc_tbdlen;     /* TxBD down counter */
-       uint    fcc_tdptr;      /* TxBD internal data pointer */
-       uint    fcc_rbptr;      /* Rx BD Internal buf pointer */
-       uint    fcc_tbptr;      /* Tx BD Internal buf pointer */
-       uint    fcc_rcrc;       /* Rx temp CRC */
-       uint    fcc_res2;
-       uint    fcc_tcrc;       /* Tx temp CRC */
-} fccp_t;
-
-
-/* Ethernet controller through FCC.
-*/
-typedef struct fcc_enet {
-       fccp_t  fen_genfcc;
-       uint    fen_statbuf;    /* Internal status buffer */
-       uint    fen_camptr;     /* CAM address */
-       uint    fen_cmask;      /* Constant mask for CRC */
-       uint    fen_cpres;      /* Preset CRC */
-       uint    fen_crcec;      /* CRC Error counter */
-       uint    fen_alec;       /* alignment error counter */
-       uint    fen_disfc;      /* discard frame counter */
-       ushort  fen_retlim;     /* Retry limit */
-       ushort  fen_retcnt;     /* Retry counter */
-       ushort  fen_pper;       /* Persistence */
-       ushort  fen_boffcnt;    /* backoff counter */
-       uint    fen_gaddrh;     /* Group address filter, high 32-bits */
-       uint    fen_gaddrl;     /* Group address filter, low 32-bits */
-       ushort  fen_tfcstat;    /* out of sequence TxBD */
-       ushort  fen_tfclen;
-       uint    fen_tfcptr;
-       ushort  fen_mflr;       /* Maximum frame length (1518) */
-       ushort  fen_paddrh;     /* MAC address */
-       ushort  fen_paddrm;
-       ushort  fen_paddrl;
-       ushort  fen_ibdcount;   /* Internal BD counter */
-       ushort  fen_ibdstart;   /* Internal BD start pointer */
-       ushort  fen_ibdend;     /* Internal BD end pointer */
-       ushort  fen_txlen;      /* Internal Tx frame length counter */
-       uint    fen_ibdbase[8]; /* Internal use */
-       uint    fen_iaddrh;     /* Individual address filter */
-       uint    fen_iaddrl;
-       ushort  fen_minflr;     /* Minimum frame length (64) */
-       ushort  fen_taddrh;     /* Filter transfer MAC address */
-       ushort  fen_taddrm;
-       ushort  fen_taddrl;
-       ushort  fen_padptr;     /* Pointer to pad byte buffer */
-       ushort  fen_cftype;     /* control frame type */
-       ushort  fen_cfrange;    /* control frame range */
-       ushort  fen_maxb;       /* maximum BD count */
-       ushort  fen_maxd1;      /* Max DMA1 length (1520) */
-       ushort  fen_maxd2;      /* Max DMA2 length (1520) */
-       ushort  fen_maxd;       /* internal max DMA count */
-       ushort  fen_dmacnt;     /* internal DMA counter */
-       uint    fen_octc;       /* Total octect counter */
-       uint    fen_colc;       /* Total collision counter */
-       uint    fen_broc;       /* Total broadcast packet counter */
-       uint    fen_mulc;       /* Total multicast packet count */
-       uint    fen_uspc;       /* Total packets < 64 bytes */
-       uint    fen_frgc;       /* Total packets < 64 bytes with errors */
-       uint    fen_ospc;       /* Total packets > 1518 */
-       uint    fen_jbrc;       /* Total packets > 1518 with errors */
-       uint    fen_p64c;       /* Total packets == 64 bytes */
-       uint    fen_p65c;       /* Total packets 64 < bytes <= 127 */
-       uint    fen_p128c;      /* Total packets 127 < bytes <= 255 */
-       uint    fen_p256c;      /* Total packets 256 < bytes <= 511 */
-       uint    fen_p512c;      /* Total packets 512 < bytes <= 1023 */
-       uint    fen_p1024c;     /* Total packets 1024 < bytes <= 1518 */
-       uint    fen_cambuf;     /* Internal CAM buffer poiner */
-       ushort  fen_rfthr;      /* Received frames threshold */
-       ushort  fen_rfcnt;      /* Received frames count */
-} fcc_enet_t;
-
-/* FCC Event/Mask register as used by Ethernet.
-*/
-#define FCC_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
-#define FCC_ENET_RXC   ((ushort)0x0040)        /* Control Frame Received */
-#define FCC_ENET_TXC   ((ushort)0x0020)        /* Out of seq. Tx sent */
-#define FCC_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
-#define FCC_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
-#define FCC_ENET_BSY   ((ushort)0x0004)        /* Busy.  Rx Frame dropped */
-#define FCC_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
-#define FCC_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
-
-/* FCC Mode Register (FPSMR) as used by Ethernet.
-*/
-#define FCC_PSMR_HBC   ((uint)0x80000000)      /* Enable heartbeat */
-#define FCC_PSMR_FC    ((uint)0x40000000)      /* Force Collision */
-#define FCC_PSMR_SBT   ((uint)0x20000000)      /* Stop backoff timer */
-#define FCC_PSMR_LPB   ((uint)0x10000000)      /* Local protect. 1 = FDX */
-#define FCC_PSMR_LCW   ((uint)0x08000000)      /* Late collision select */
-#define FCC_PSMR_FDE   ((uint)0x04000000)      /* Full Duplex Enable */
-#define FCC_PSMR_MON   ((uint)0x02000000)      /* RMON Enable */
-#define FCC_PSMR_PRO   ((uint)0x00400000)      /* Promiscuous Enable */
-#define FCC_PSMR_FCE   ((uint)0x00200000)      /* Flow Control Enable */
-#define FCC_PSMR_RSH   ((uint)0x00100000)      /* Receive Short Frames */
-#define FCC_PSMR_CAM   ((uint)0x00000400)      /* CAM enable */
-#define FCC_PSMR_BRO   ((uint)0x00000200)      /* Broadcast pkt discard */
-#define FCC_PSMR_ENCRC ((uint)0x00000080)      /* Use 32-bit CRC */
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-       ushort  iic_rbase;      /* Rx Buffer descriptor base address */
-       ushort  iic_tbase;      /* Tx Buffer descriptor base address */
-       u_char  iic_rfcr;       /* Rx function code */
-       u_char  iic_tfcr;       /* Tx function code */
-       ushort  iic_mrblr;      /* Max receive buffer length */
-       uint    iic_rstate;     /* Internal */
-       uint    iic_rdp;        /* Internal */
-       ushort  iic_rbptr;      /* Internal */
-       ushort  iic_rbc;        /* Internal */
-       uint    iic_rxtmp;      /* Internal */
-       uint    iic_tstate;     /* Internal */
-       uint    iic_tdp;        /* Internal */
-       ushort  iic_tbptr;      /* Internal */
-       ushort  iic_tbc;        /* Internal */
-       uint    iic_txtmp;      /* Internal */
-} iic_t;
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-       ushort  spi_rbase;      /* Rx Buffer descriptor base address */
-       ushort  spi_tbase;      /* Tx Buffer descriptor base address */
-       u_char  spi_rfcr;       /* Rx function code */
-       u_char  spi_tfcr;       /* Tx function code */
-       ushort  spi_mrblr;      /* Max receive buffer length */
-       uint    spi_rstate;     /* Internal */
-       uint    spi_rdp;        /* Internal */
-       ushort  spi_rbptr;      /* Internal */
-       ushort  spi_rbc;        /* Internal */
-       uint    spi_rxtmp;      /* Internal */
-       uint    spi_tstate;     /* Internal */
-       uint    spi_tdp;        /* Internal */
-       ushort  spi_tbptr;      /* Internal */
-       ushort  spi_tbc;        /* Internal */
-       uint    spi_txtmp;      /* Internal */
-       uint    spi_res;        /* Tx temp. */
-       uint    spi_res1[4];    /* SDMA temp. */
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP    ((ushort)0x4000)        /* Loopback */
-#define SPMODE_CI      ((ushort)0x2000)        /* Clock Invert */
-#define SPMODE_CP      ((ushort)0x1000)        /* Clock Phase */
-#define SPMODE_DIV16   ((ushort)0x0800)        /* BRG/16 mode */
-#define SPMODE_REV     ((ushort)0x0400)        /* Reversed Data */
-#define SPMODE_MSTR    ((ushort)0x0200)        /* SPI Master */
-#define SPMODE_EN      ((ushort)0x0100)        /* Enable */
-#define SPMODE_LENMSK  ((ushort)0x00f0)        /* character length */
-#define SPMODE_PMMSK   ((ushort)0x000f)        /* prescale modulus */
-
-#define SPMODE_LEN(x)  ((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)   ((x) &0xF)
-
-#define SPI_EB         ((u_char)0x10)          /* big endian byte order */
-
-#define BD_IIC_START   ((ushort)0x0400)
-
-/*-----------------------------------------------------------------------
- * CMXFCR - CMX FCC Clock Route Register                                15-12
- */
-#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
-#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
-#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
-#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
-#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
-#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
-#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
-#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
-#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
-
-#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
-#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
-#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
-#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
-#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
-#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
-#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
-#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
-#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
-#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
-#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
-#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
-#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
-#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
-#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
-#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
-#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
-#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
-#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
-#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
-#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
-#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
-#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
-#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
-#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
-#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
-#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
-#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
-#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
-#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
-#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
-#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
-#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
-#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
-#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
-#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
-
-#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
-#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
-#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
-#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
-#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
-#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
-#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
-#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
-
-/*-----------------------------------------------------------------------
- * CMXSCR - CMX SCC Clock Route Register                                15-14
- */
-#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
-#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
-#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
-#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
-#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
-#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
-#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
-#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
-#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
-#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
-#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
-#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
-#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
-#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
-#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
-#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
-
-#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
-#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
-#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
-#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
-#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
-#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
-#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
-#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
-#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
-#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
-#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
-#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
-#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
-#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
-#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
-#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
-#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
-#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
-#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
-#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
-#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
-#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
-#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
-#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
-#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
-#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
-#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
-#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
-#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
-#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
-#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
-#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
-#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
-#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
-#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
-#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
-#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
-#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
-#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
-#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
-#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
-#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
-#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
-
-#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
-#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
-#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
-#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
-#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
-#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
-#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
-#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
-#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
-#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
-#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
-#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
-#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
-#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
-#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
-
-#endif /* __CPM_85XX__ */
index 2975255..770adcd 100644 (file)
@@ -20,13 +20,6 @@ struct arch_global_data {
 #if defined(CONFIG_MPC8xx)
        unsigned long brg_clk;
 #endif
-#if defined(CONFIG_CPM2)
-       /* There are many clocks on the MPC8260 - see page 9-5 */
-       unsigned long vco_out;
-       unsigned long cpm_clk;
-       unsigned long scc_clk;
-       unsigned long brg_clk;
-#endif
        /* TODO: sjg@chromium.org: Should these be unslgned long? */
 #if defined(CONFIG_MPC83xx)
 #ifdef CONFIG_CLK_MPC83XX
@@ -88,10 +81,6 @@ struct arch_global_data {
        unsigned long arbiter_event_attributes;
        unsigned long arbiter_event_address;
 #endif
-#if defined(CONFIG_CPM2)
-       unsigned int dp_alloc_base;
-       unsigned int dp_alloc_top;
-#endif
 #ifdef CONFIG_SYS_FPGA_COUNT
        unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
 #endif
index 770705a..b8bc584 100644 (file)
@@ -921,330 +921,6 @@ typedef struct ccsr_pic {
        u8      res150[130892];
 } ccsr_pic_t;
 
-/* CPM Block */
-#ifndef CONFIG_CPM2
-typedef struct ccsr_cpm {
-       u8 res[262144];
-} ccsr_cpm_t;
-#else
-/*
- * DPARM
- * General SIU
- */
-typedef struct ccsr_cpm_siu {
-       u8      res1[80];
-       u32     smaer;
-       u32     smser;
-       u32     smevr;
-       u8      res2[4];
-       u32     lmaer;
-       u32     lmser;
-       u32     lmevr;
-       u8      res3[2964];
-} ccsr_cpm_siu_t;
-
-/* IRQ Controller */
-typedef struct ccsr_cpm_intctl {
-       u16     sicr;
-       u8      res1[2];
-       u32     sivec;
-       u32     sipnrh;
-       u32     sipnrl;
-       u32     siprr;
-       u32     scprrh;
-       u32     scprrl;
-       u32     simrh;
-       u32     simrl;
-       u32     siexr;
-       u8      res2[88];
-       u32     sccr;
-       u8      res3[124];
-} ccsr_cpm_intctl_t;
-
-/* input/output port */
-typedef struct ccsr_cpm_iop {
-       u32     pdira;
-       u32     ppara;
-       u32     psora;
-       u32     podra;
-       u32     pdata;
-       u8      res1[12];
-       u32     pdirb;
-       u32     pparb;
-       u32     psorb;
-       u32     podrb;
-       u32     pdatb;
-       u8      res2[12];
-       u32     pdirc;
-       u32     pparc;
-       u32     psorc;
-       u32     podrc;
-       u32     pdatc;
-       u8      res3[12];
-       u32     pdird;
-       u32     ppard;
-       u32     psord;
-       u32     podrd;
-       u32     pdatd;
-       u8      res4[12];
-} ccsr_cpm_iop_t;
-
-/* CPM timers */
-typedef struct ccsr_cpm_timer {
-       u8      tgcr1;
-       u8      res1[3];
-       u8      tgcr2;
-       u8      res2[11];
-       u16     tmr1;
-       u16     tmr2;
-       u16     trr1;
-       u16     trr2;
-       u16     tcr1;
-       u16     tcr2;
-       u16     tcn1;
-       u16     tcn2;
-       u16     tmr3;
-       u16     tmr4;
-       u16     trr3;
-       u16     trr4;
-       u16     tcr3;
-       u16     tcr4;
-       u16     tcn3;
-       u16     tcn4;
-       u16     ter1;
-       u16     ter2;
-       u16     ter3;
-       u16     ter4;
-       u8      res3[608];
-} ccsr_cpm_timer_t;
-
-/* SDMA */
-typedef struct ccsr_cpm_sdma {
-       u8      sdsr;
-       u8      res1[3];
-       u8      sdmr;
-       u8      res2[739];
-} ccsr_cpm_sdma_t;
-
-/* FCC1 */
-typedef struct ccsr_cpm_fcc1 {
-       u32     gfmr;
-       u32     fpsmr;
-       u16     ftodr;
-       u8      res1[2];
-       u16     fdsr;
-       u8      res2[2];
-       u16     fcce;
-       u8      res3[2];
-       u16     fccm;
-       u8      res4[2];
-       u8      fccs;
-       u8      res5[3];
-       u8      ftirr_phy[4];
-} ccsr_cpm_fcc1_t;
-
-/* FCC2 */
-typedef struct ccsr_cpm_fcc2 {
-       u32     gfmr;
-       u32     fpsmr;
-       u16     ftodr;
-       u8      res1[2];
-       u16     fdsr;
-       u8      res2[2];
-       u16     fcce;
-       u8      res3[2];
-       u16     fccm;
-       u8      res4[2];
-       u8      fccs;
-       u8      res5[3];
-       u8      ftirr_phy[4];
-} ccsr_cpm_fcc2_t;
-
-/* FCC3 */
-typedef struct ccsr_cpm_fcc3 {
-       u32     gfmr;
-       u32     fpsmr;
-       u16     ftodr;
-       u8      res1[2];
-       u16     fdsr;
-       u8      res2[2];
-       u16     fcce;
-       u8      res3[2];
-       u16     fccm;
-       u8      res4[2];
-       u8      fccs;
-       u8      res5[3];
-       u8      res[36];
-} ccsr_cpm_fcc3_t;
-
-/* FCC1 extended */
-typedef struct ccsr_cpm_fcc1_ext {
-       u32     firper;
-       u32     firer;
-       u32     firsr_h;
-       u32     firsr_l;
-       u8      gfemr;
-       u8      res[15];
-
-} ccsr_cpm_fcc1_ext_t;
-
-/* FCC2 extended */
-typedef struct ccsr_cpm_fcc2_ext {
-       u32     firper;
-       u32     firer;
-       u32     firsr_h;
-       u32     firsr_l;
-       u8      gfemr;
-       u8      res[31];
-} ccsr_cpm_fcc2_ext_t;
-
-/* FCC3 extended */
-typedef struct ccsr_cpm_fcc3_ext {
-       u8      gfemr;
-       u8      res[47];
-} ccsr_cpm_fcc3_ext_t;
-
-/* TC layers */
-typedef struct ccsr_cpm_tmp1 {
-       u8      res[496];
-} ccsr_cpm_tmp1_t;
-
-/* BRGs:5,6,7,8 */
-typedef struct ccsr_cpm_brg2 {
-       u32     brgc5;
-       u32     brgc6;
-       u32     brgc7;
-       u32     brgc8;
-       u8      res[608];
-} ccsr_cpm_brg2_t;
-
-/* I2C */
-typedef struct ccsr_cpm_i2c {
-       u8      i2mod;
-       u8      res1[3];
-       u8      i2add;
-       u8      res2[3];
-       u8      i2brg;
-       u8      res3[3];
-       u8      i2com;
-       u8      res4[3];
-       u8      i2cer;
-       u8      res5[3];
-       u8      i2cmr;
-       u8      res6[331];
-} ccsr_cpm_i2c_t;
-
-/* CPM core */
-typedef struct ccsr_cpm_cp {
-       u32     cpcr;
-       u32     rccr;
-       u8      res1[14];
-       u16     rter;
-       u8      res2[2];
-       u16     rtmr;
-       u16     rtscr;
-       u8      res3[2];
-       u32     rtsr;
-       u8      res4[12];
-} ccsr_cpm_cp_t;
-
-/* BRGs:1,2,3,4 */
-typedef struct ccsr_cpm_brg1 {
-       u32     brgc1;
-       u32     brgc2;
-       u32     brgc3;
-       u32     brgc4;
-} ccsr_cpm_brg1_t;
-
-/* SCC1-SCC4 */
-typedef struct ccsr_cpm_scc {
-       u32     gsmrl;
-       u32     gsmrh;
-       u16     psmr;
-       u8      res1[2];
-       u16     todr;
-       u16     dsr;
-       u16     scce;
-       u8      res2[2];
-       u16     sccm;
-       u8      res3;
-       u8      sccs;
-       u8      res4[8];
-} ccsr_cpm_scc_t;
-
-typedef struct ccsr_cpm_tmp2 {
-       u8      res[32];
-} ccsr_cpm_tmp2_t;
-
-/* SPI */
-typedef struct ccsr_cpm_spi {
-       u16     spmode;
-       u8      res1[4];
-       u8      spie;
-       u8      res2[3];
-       u8      spim;
-       u8      res3[2];
-       u8      spcom;
-       u8      res4[82];
-} ccsr_cpm_spi_t;
-
-/* CPM MUX */
-typedef struct ccsr_cpm_mux {
-       u8      cmxsi1cr;
-       u8      res1;
-       u8      cmxsi2cr;
-       u8      res2;
-       u32     cmxfcr;
-       u32     cmxscr;
-       u8      res3[2];
-       u16     cmxuar;
-       u8      res4[16];
-} ccsr_cpm_mux_t;
-
-/* SI,MCC,etc */
-typedef struct ccsr_cpm_tmp3 {
-       u8 res[58592];
-} ccsr_cpm_tmp3_t;
-
-typedef struct ccsr_cpm_iram {
-       u32     iram[8192];
-       u8      res[98304];
-} ccsr_cpm_iram_t;
-
-typedef struct ccsr_cpm {
-       /* Some references are into the unique & known dpram spaces,
-        * others are from the generic base.
-        */
-#define im_dprambase           im_dpram1
-       u8                      im_dpram1[16*1024];
-       u8                      res1[16*1024];
-       u8                      im_dpram2[16*1024];
-       u8                      res2[16*1024];
-       ccsr_cpm_siu_t          im_cpm_siu; /* SIU Configuration */
-       ccsr_cpm_intctl_t       im_cpm_intctl; /* IRQ Controller */
-       ccsr_cpm_iop_t          im_cpm_iop; /* IO Port control/status */
-       ccsr_cpm_timer_t        im_cpm_timer; /* CPM timers */
-       ccsr_cpm_sdma_t         im_cpm_sdma; /* SDMA control/status */
-       ccsr_cpm_fcc1_t         im_cpm_fcc1;
-       ccsr_cpm_fcc2_t         im_cpm_fcc2;
-       ccsr_cpm_fcc3_t         im_cpm_fcc3;
-       ccsr_cpm_fcc1_ext_t     im_cpm_fcc1_ext;
-       ccsr_cpm_fcc2_ext_t     im_cpm_fcc2_ext;
-       ccsr_cpm_fcc3_ext_t     im_cpm_fcc3_ext;
-       ccsr_cpm_tmp1_t         im_cpm_tmp1;
-       ccsr_cpm_brg2_t         im_cpm_brg2;
-       ccsr_cpm_i2c_t          im_cpm_i2c;
-       ccsr_cpm_cp_t           im_cpm_cp;
-       ccsr_cpm_brg1_t         im_cpm_brg1;
-       ccsr_cpm_scc_t          im_cpm_scc[4];
-       ccsr_cpm_tmp2_t         im_cpm_tmp2;
-       ccsr_cpm_spi_t          im_cpm_spi;
-       ccsr_cpm_mux_t          im_cpm_mux;
-       ccsr_cpm_tmp3_t         im_cpm_tmp3;
-       ccsr_cpm_iram_t         im_cpm_iram;
-} ccsr_cpm_t;
-#endif
-
 #ifdef CONFIG_SYS_SRIO
 /* Architectural regsiters */
 struct rio_arch {
@@ -2888,7 +2564,6 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
 #define CONFIG_SYS_SEC_MON_OFFSET              0xE6000
 #define CONFIG_SYS_SFP_OFFSET                  0xE7000
-#define CONFIG_SYS_MPC85xx_CPM_OFFSET          0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
 #define CONFIG_SYS_FSL_BMAN_OFFSET             0x8a000
 #define CONFIG_SYS_FSL_FM1_OFFSET              0x100000
@@ -2965,8 +2640,6 @@ struct ccsr_pman {
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_CPM_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
index d2e5e60..55dcad5 100644 (file)
@@ -27,13 +27,6 @@ int arch_setup_bdinfo(void)
        bd->bi_intfreq = gd->cpu_clk;   /* Internal Freq, in Hz */
        bd->bi_busfreq = gd->bus_clk;   /* Bus Freq,      in Hz */
 
-#if defined(CONFIG_CPM2)
-       bd->bi_cpmfreq = gd->arch.cpm_clk;
-       bd->bi_brgfreq = gd->arch.brg_clk;
-       bd->bi_sccfreq = gd->arch.scc_clk;
-       bd->bi_vco = gd->arch.vco_out;
-#endif /* CONFIG_CPM2 */
-
        return 0;
 }
 
@@ -59,10 +52,4 @@ void arch_print_bdinfo(void)
                puts("addressing  = 32-bit\n");
 #endif
        board_detail();
-#if defined(CONFIG_CPM2)
-       bdinfo_print_mhz("cpmfreq", bd->bi_cpmfreq);
-       bdinfo_print_mhz("vco", bd->bi_vco);
-       bdinfo_print_mhz("sccfreq", bd->bi_sccfreq);
-       bdinfo_print_mhz("brgfreq", bd->bi_brgfreq);
-#endif
 }
index 8d65047..3b43066 100644 (file)
@@ -266,12 +266,6 @@ static void set_clocks_in_mhz (struct bd_info *kbd)
                /* convert all clock information to MHz */
                kbd->bi_intfreq /= 1000000L;
                kbd->bi_busfreq /= 1000000L;
-#if defined(CONFIG_CPM2)
-               kbd->bi_cpmfreq /= 1000000L;
-               kbd->bi_brgfreq /= 1000000L;
-               kbd->bi_sccfreq /= 1000000L;
-               kbd->bi_vco     /= 1000000L;
-#endif
        }
 }
 
index 8d90c5e..3ffcbbd 100644 (file)
@@ -7,9 +7,11 @@
 #include <cpu.h>
 #include <dm.h>
 #include <dm/lists.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <asm/encoding.h>
+#include <asm/system.h>
 #include <dm/uclass-internal.h>
 #include <linux/bitops.h>
 
@@ -81,7 +83,7 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
 }
 #endif
 
-int arch_cpu_init_dm(void)
+int riscv_cpu_setup(void *ctx, struct event *event)
 {
        int ret;
 
@@ -133,6 +135,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, riscv_cpu_setup);
 
 int arch_early_init_r(void)
 {
index a340475..9d8e43e 100644 (file)
@@ -7,6 +7,8 @@
 #ifndef __ASM_RISCV_SYSTEM_H
 #define __ASM_RISCV_SYSTEM_H
 
+struct event;
+
 /*
  * Interrupt configuring macros.
  *
@@ -14,4 +16,7 @@
  *
  */
 
+/* Hook to set up the CPU (called from SPL too) */
+int riscv_cpu_setup(void *ctx, struct event *event);
+
 #endif /* __ASM_RISCV_SYSTEM_H */
index 8baee07..f4d3b67 100644 (file)
@@ -11,6 +11,7 @@
 #include <spl.h>
 #include <asm/global_data.h>
 #include <asm/smp.h>
+#include <asm/system.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,7 +28,7 @@ __weak void board_init_f(ulong dummy)
        if (ret)
                panic("spl_early_init() failed: %d\n", ret);
 
-       arch_cpu_init_dm();
+       riscv_cpu_setup(NULL, NULL);
 
        preloader_console_init();
 
index 13b0731..0f5a873 100644 (file)
@@ -4,14 +4,14 @@
  */
 
 #include <common.h>
+#include <cli.h>
 #include <command.h>
-#include <dm/root.h>
 #include <efi_loader.h>
 #include <errno.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <os.h>
-#include <cli.h>
 #include <sort.h>
 #include <asm/getopt.h>
 #include <asm/global_data.h>
@@ -19,6 +19,7 @@
 #include <asm/malloc.h>
 #include <asm/sections.h>
 #include <asm/state.h>
+#include <dm/root.h>
 #include <linux/ctype.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -119,10 +120,11 @@ int sandbox_early_getopt_check(void)
        os_exit(0);
 }
 
-int misc_init_f(void)
+static int sandbox_misc_init_f(void *ctx, struct event *event)
 {
        return sandbox_early_getopt_check();
 }
+EVENT_SPY(EVT_MISC_INIT_F, sandbox_misc_init_f);
 
 static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg)
 {
index 48ca3e1..3d206fd 100644 (file)
                        compatible = "sandbox,firmware";
                };
 
-               sandbox-scmi-agent@0 {
+               scmi {
                        compatible = "sandbox,scmi-agent";
                        #address-cells = <1>;
                        #size-cells = <0>;
 
-                       clk_scmi0: protocol@14 {
+                       protocol@10 {
+                               reg = <0x10>;
+                       };
+
+                       clk_scmi: protocol@14 {
                                reg = <0x14>;
                                #clock-cells = <1>;
                        };
 
-                       reset_scmi0: protocol@16 {
+                       reset_scmi: protocol@16 {
                                reg = <0x16>;
                                #reset-cells = <1>;
                        };
                                        #address-cells = <1>;
                                        #size-cells = <0>;
 
-                                       regul0_scmi0: reg@0 {
+                                       regul0_scmi: reg@0 {
                                                reg = <0>;
                                                regulator-name = "sandbox-voltd0";
                                                regulator-min-microvolt = <1100000>;
                                                regulator-max-microvolt = <3300000>;
                                        };
-                                       regul1_scmi0: reg@1 {
+                                       regul1_scmi: reg@1 {
                                                reg = <0x1>;
                                                regulator-name = "sandbox-voltd1";
                                                regulator-min-microvolt = <1800000>;
                                };
                        };
                };
-
-               sandbox-scmi-agent@1 {
-                       compatible = "sandbox,scmi-agent";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       clk_scmi1: protocol@14 {
-                               reg = <0x14>;
-                               #clock-cells = <1>;
-                       };
-
-                       protocol@10 {
-                               reg = <0x10>;
-                       };
-               };
        };
 
        pinctrl-gpio {
 
        sandbox_scmi {
                compatible = "sandbox,scmi-devices";
-               clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
-               resets = <&reset_scmi0 3>;
-               regul0-supply = <&regul0_scmi0>;
-               regul1-supply = <&regul1_scmi0>;
+               clocks = <&clk_scmi 2>, <&clk_scmi 0>;
+               resets = <&reset_scmi 3>;
+               regul0-supply = <&regul0_scmi>;
+               regul1-supply = <&regul1_scmi>;
        };
 
        pinctrl {
index 2930e68..c72ec1e 100644 (file)
@@ -17,7 +17,6 @@ struct sandbox_scmi_service;
  * @rate:      Clock rate in Hertz
  */
 struct sandbox_scmi_clk {
-       uint id;
        bool enabled;
        ulong rate;
 };
@@ -46,7 +45,6 @@ struct sandbox_scmi_voltd {
 
 /**
  * struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent
- * @idx:       Identifier for the SCMI agent, its index
  * @clk:       Simulated clocks
  * @clk_count: Simulated clocks array size
  * @reset:     Simulated reset domains
@@ -55,7 +53,6 @@ struct sandbox_scmi_voltd {
  * @voltd_count: Simulated voltage domains array size
  */
 struct sandbox_scmi_agent {
-       uint idx;
        struct sandbox_scmi_clk *clk;
        size_t clk_count;
        struct sandbox_scmi_reset *reset;
@@ -66,12 +63,10 @@ struct sandbox_scmi_agent {
 
 /**
  * struct sandbox_scmi_service - Reference to simutaed SCMI agents/services
- * @agent:             Pointer to SCMI sandbox agent pointers array
- * @agent_count:       Number of emulated agents exposed in array @agent.
+ * @agent:             Pointer to SCMI sandbox agent or NULL if not probed
  */
 struct sandbox_scmi_service {
-       struct sandbox_scmi_agent **agent;
-       size_t agent_count;
+       struct sandbox_scmi_agent *agent;
 };
 
 /**
@@ -94,13 +89,13 @@ struct sandbox_scmi_devices {
 
 #ifdef CONFIG_SCMI_FIRMWARE
 /**
- * sandbox_scmi_service_context - Get the simulated SCMI services context
+ * sandbox_scmi_service_ctx - Get the simulated SCMI services context
  * @return:    Reference to backend simulated resources state
  */
 struct sandbox_scmi_service *sandbox_scmi_service_ctx(void);
 
 /**
- * sandbox_scmi_devices_get_ref - Get references to devices accessed through SCMI
+ * sandbox_scmi_devices_ctx - Get references to devices accessed through SCMI
  * @dev:       Reference to the test device used get test resources
  * @return:    Reference to the devices probed by the SCMI test
  */
index 309a50a..68bf40b 100644 (file)
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <cpu.h>
 #include <dm.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <pci.h>
@@ -44,7 +45,7 @@ static void hsuart_clock_set(void *base)
  * Configure the internal clock of both SIO HS-UARTs, if they are enabled
  * via FSP
  */
-int arch_cpu_init_dm(void)
+static int baytrail_uart_init(void *ctx, struct event *event)
 {
        struct udevice *dev;
        void *base;
@@ -63,6 +64,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, baytrail_uart_init);
 
 static void set_max_freq(void)
 {
index 3832a97..2adcf4b 100644 (file)
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <cpu.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <asm/cpu.h>
@@ -24,7 +25,7 @@
 #include <asm/arch/pch.h>
 #include <asm/arch/rcb.h>
 
-int arch_cpu_init_dm(void)
+static int broadwell_init_cpu(void *ctx, struct event *event)
 {
        struct udevice *dev;
        int ret;
@@ -41,6 +42,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu);
 
 void set_max_freq(void)
 {
index a02f4f9..cffc5d5 100644 (file)
@@ -14,6 +14,7 @@
 #include <cpu_func.h>
 #include <dm.h>
 #include <errno.h>
+#include <event.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <log.h>
@@ -53,7 +54,7 @@ int arch_cpu_init(void)
        return x86_cpu_init_f();
 }
 
-int arch_cpu_init_dm(void)
+static int ivybridge_cpu_init(void *ctx, struct event *ev)
 {
        struct pci_controller *hose;
        struct udevice *bus, *dev;
@@ -85,6 +86,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, ivybridge_cpu_init);
 
 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
index 30b4711..e016fae 100644 (file)
@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <cpu_func.h>
+#include <event.h>
 #include <init.h>
 #include <mmc.h>
 #include <asm/cache.h>
@@ -247,7 +248,7 @@ int arch_cpu_init(void)
        return 0;
 }
 
-int arch_cpu_init_dm(void)
+static int quark_init_pcie(void *ctx, struct event *event)
 {
        /*
         * Initialize PCIe controller
@@ -262,6 +263,7 @@ int arch_cpu_init_dm(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT, quark_init_pcie);
 
 int checkcpu(void)
 {
index dccbfa4..ca3f684 100644 (file)
@@ -60,4 +60,12 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash);
 
 typedef asmlinkage int (*fsp_silicon_init_func)(struct fsps_upd *params);
 
+/**
+ *  fsp_setup_pinctrl() - Set up the pinctrl for FSP
+ *
+ * @ctx: Event context (not used)
+ * @event: Event information (not used)
+ */
+int fsp_setup_pinctrl(void *ctx, struct event *event);
+
 #endif
index fc743dc..0b69530 100644 (file)
@@ -47,7 +47,13 @@ enum {
        BINF_RW_B = 2
 };
 
-enum {
+/**
+ * enum cros_fw_type_t - Used to indicate Chromium OS firmware type
+ *
+ * Chromium OS uses a region of the GNVS starting at offset 0x100 to store
+ * various bits of information, including the type of firmware being booted
+ */
+enum cros_fw_type_t {
        FIRMWARE_TYPE_AUTO_DETECT = -1,
        FIRMWARE_TYPE_RECOVERY = 0,
        FIRMWARE_TYPE_NORMAL = 1,
index 5afdce1..b15926e 100644 (file)
@@ -9,6 +9,7 @@
 #include <bootstage.h>
 #include <cbfs.h>
 #include <dm.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <spi.h>
@@ -18,7 +19,7 @@
 #include <dm/uclass-internal.h>
 #include <asm/fsp2/fsp_internal.h>
 
-int arch_cpu_init_dm(void)
+int fsp_setup_pinctrl(void *ctx, struct event *event)
 {
        struct udevice *dev;
        ofnode node;
@@ -41,6 +42,7 @@ int arch_cpu_init_dm(void)
 
        return ret;
 }
+EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl);
 
 #if !defined(CONFIG_TPL_BUILD)
 binman_sym_declare(ulong, intel_fsp_m, image_pos);
index b18c1cd..2d50c62 100644 (file)
@@ -17,6 +17,7 @@
 #include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/cpu_common.h>
+#include <asm/fsp2/fsp_api.h>
 #include <asm/global_data.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
@@ -27,7 +28,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-__weak int arch_cpu_init_dm(void)
+__weak int fsp_setup_pinctrl(void *ctx, struct event *event)
 {
        return 0;
 }
@@ -89,7 +90,7 @@ static int x86_spl_init(void)
                return ret;
        }
 #ifndef CONFIG_TPL
-       ret = arch_cpu_init_dm();
+       ret = fsp_setup_pinctrl(NULL, NULL);
        if (ret) {
                debug("%s: arch_cpu_init_dm() failed\n", __func__);
                return ret;
index 5b57e53..18b05b2 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-__weak int arch_cpu_init_dm(void)
-{
-       return 0;
-}
-
 static int x86_tpl_init(void)
 {
        int ret;
@@ -44,11 +39,6 @@ static int x86_tpl_init(void)
                debug("%s: arch_cpu_init() failed\n", __func__);
                return ret;
        }
-       ret = arch_cpu_init_dm();
-       if (ret) {
-               debug("%s: arch_cpu_init_dm() failed\n", __func__);
-               return ret;
-       }
        preloader_console_init();
 
        return 0;
index 35e5b89..8f668cc 100644 (file)
@@ -13,6 +13,7 @@ choice
 
 config TARGET_XTFPGA
        bool "Support XTFPGA"
+       select BOARD_POSTCLK_INIT
 
 endchoice
 
index 6eb8a54..39e46ba 100644 (file)
@@ -1,3 +1,3 @@
-dsdt.aml
-dsdt.asl.tmp
-dsdt.c
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
diff --git a/board/broadcom/bcm96753ref/Kconfig b/board/broadcom/bcm96753ref/Kconfig
new file mode 100644 (file)
index 0000000..479e790
--- /dev/null
@@ -0,0 +1,16 @@
+if TARGET_BCM96753REF
+
+config SYS_VENDOR
+       default "broadcom"
+
+config SYS_BOARD
+       default "bcm96753ref"
+
+config SYS_CONFIG_NAME
+       default "broadcom_bcm96753ref"
+
+endif
+
+config TARGET_BCM96753REF
+       bool "Support Broadcom bcm96753ref"
+       depends on ARCH_BCM6753
diff --git a/board/broadcom/bcm96753ref/MAINTAINERS b/board/broadcom/bcm96753ref/MAINTAINERS
new file mode 100644 (file)
index 0000000..be060f5
--- /dev/null
@@ -0,0 +1,6 @@
+BROADCOM BCM96753REF
+M:     Philippe Reynes <philippe.reynes@softathome.com>
+S:     Maintained
+F:     board/broadcom/bcm96753ref
+F:     include/configs/broadcom_bcm96753ref.h
+F:     configs/bcm96753ref_ram_defconfig
diff --git a/board/broadcom/bcm96753ref/Makefile b/board/broadcom/bcm96753ref/Makefile
new file mode 100644 (file)
index 0000000..a1fa2bf
--- /dev/null
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y  += bcm96753ref.o
diff --git a/board/broadcom/bcm96753ref/bcm96753ref.c b/board/broadcom/bcm96753ref/bcm96753ref.c
new file mode 100644 (file)
index 0000000..bf78d84
--- /dev/null
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <cpu_func.h>
+
+int board_init(void)
+{
+       return 0;
+}
+
+int dram_init(void)
+{
+       if (fdtdec_setup_mem_size_base() != 0)
+               printf("fdtdec_setup_mem_size_base() has failed\n");
+
+       return 0;
+}
+
+int dram_init_banksize(void)
+{
+       fdtdec_setup_memory_banksize();
+
+       return 0;
+}
+
+int print_cpuinfo(void)
+{
+       return 0;
+}
+
+void enable_caches(void)
+{
+       icache_enable();
+       dcache_enable();
+}
index 6eb8a54..39e46ba 100644 (file)
@@ -1,3 +1,3 @@
-dsdt.aml
-dsdt.asl.tmp
-dsdt.c
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
index a05673b..ee12d32 100644 (file)
@@ -2,12 +2,12 @@ COREBOOT BOARD
 M:     Simon Glass <sjg@chromium.org>
 S:     Maintained
 F:     board/coreboot/coreboot/
-F:     include/configs/chromebook_link.h
+F:     include/configs/coreboot.h
 F:     configs/coreboot_defconfig
 
 COREBOOT64 BOARD
 M:     Simon Glass <sjg@chromium.org>
 S:     Maintained
 F:     board/coreboot/coreboot/
-F:     include/configs/chromebook_link.h
+F:     include/configs/coreboot.h
 F:     configs/coreboot64_defconfig
index 4450a5d..cbf8134 100644 (file)
@@ -50,7 +50,7 @@ skip_smp_setup:
 #endif
 
 #ifdef CONFIG_ARMV8_MULTIENTRY
-       branch_if_master x0, x1, 2f
+       branch_if_master x0, 2f
 
        /*
         * Slave should wait for master clearing spin table.
index 22c4be3..c57e518 100644 (file)
@@ -4,12 +4,16 @@
 
 if VENDOR_GOOGLE
 
+config BIOSEMU
+       bool
+
 choice
        prompt "Mainboard model"
        optional
 
 config TARGET_CHROMEBOOK_CORAL
        bool "Chromebook coral"
+       select BIOSEMU
        help
          This is a range of Intel-based laptops released in 2018. They use an
          Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of
@@ -24,6 +28,7 @@ config TARGET_CHROMEBOOK_CORAL
 
 config TARGET_CHROMEBOOK_LINK
        bool "Chromebook link"
+       select BIOSEMU
        help
          This is the Chromebook Pixel released in 2013. It uses an Intel
          i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
@@ -36,6 +41,7 @@ config TARGET_CHROMEBOOK_LINK
 
 config TARGET_CHROMEBOOK_LINK64
        bool "Chromebook link 64-bit"
+       select BIOSEMU
        help
          This is the Chromebook Pixel released in 2013. With this config
          U-Boot is built as a 64-bit binary. This allows testing while this
@@ -43,6 +49,7 @@ config TARGET_CHROMEBOOK_LINK64
 
 config TARGET_CHROMEBOX_PANTHER
        bool "Chromebox panther (not available)"
+       select BIOSEMU
        help
          Note: At present this must be used with coreboot. See README.x86
          for instructions.
index 182cf75..9e23f5c 100644 (file)
@@ -10,6 +10,7 @@
 #include <command.h>
 #include <cros_ec.h>
 #include <dm.h>
+#include <event.h>
 #include <init.h>
 #include <log.h>
 #include <sysinfo.h>
@@ -32,11 +33,12 @@ struct cros_gpio_info {
        int flags;
 };
 
-int misc_init_f(void)
+static int coral_check_ll_boot(void *ctx, struct event *event)
 {
        if (!ll_boot_init()) {
                printf("Running as secondary loader");
-               if (gd->arch.coreboot_table) {
+               if (CONFIG_IS_ENABLED(COREBOOT_SYSINFO) &&
+                   gd->arch.coreboot_table) {
                        int ret;
 
                        printf(" (found coreboot table at %lx)",
@@ -55,6 +57,7 @@ int misc_init_f(void)
 
        return 0;
 }
+EVENT_SPY(EVT_MISC_INIT_F, coral_check_ll_boot);
 
 int arch_misc_init(void)
 {
index 6eb8a54..39e46ba 100644 (file)
@@ -1,3 +1,3 @@
-dsdt.aml
-dsdt.asl.tmp
-dsdt.c
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
index 6eb8a54..39e46ba 100644 (file)
@@ -1,3 +1,3 @@
-dsdt.aml
-dsdt.asl.tmp
-dsdt.c
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
index 6eb8a54..39e46ba 100644 (file)
@@ -1,3 +1,3 @@
-dsdt.aml
-dsdt.asl.tmp
-dsdt.c
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
index 6eb8a54..39e46ba 100644 (file)
@@ -1,3 +1,3 @@
-dsdt.aml
-dsdt.asl.tmp
-dsdt.c
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
index ca24b96..4486538 100644 (file)
@@ -6,6 +6,7 @@
  * Copyright 2013 Freescale Semiconductor, Inc.
  */
 
+#include <event.h>
 #include <asm/cache.h>
 #include <asm/fsl_fdt.h>
 #include <asm/fsl_law.h>
@@ -181,7 +182,7 @@ unsigned long get_serial_clock(unsigned long dummy)
        return (gd->bus_clk / 2);
 }
 
-int misc_init_f(void)
+static int kmcent2_misc_init_f(void *ctx, struct event *event)
 {
        /* configure QRIO pis for i2c deblocking */
        i2c_deblock_gpio_cfg();
@@ -209,6 +210,7 @@ int misc_init_f(void)
 
        return 0;
 }
+EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
 
 #define USED_SRDS_BANK 0
 #define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
index 467f110..ed8142d 100644 (file)
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <event.h>
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
@@ -109,12 +110,14 @@ int board_early_init_f(void)
        return 0;
 }
 
-int misc_init_f(void)
+static int pg_wcom_misc_init_f(void *ctx, struct event *event)
 {
        if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED))
                check_for_uboot_update();
+
        return 0;
 }
+EVENT_SPY(EVT_MISC_INIT_F, pg_wcom_misc_init_f);
 
 int board_init(void)
 {
index f014165..e787441 100644 (file)
@@ -117,17 +117,10 @@ static void am3517_evm_musb_init(void)
  */
 int misc_init_r(void)
 {
-       u32 reset;
-
        omap_die_id_display();
 
        am3517_evm_musb_init();
 
-       /* ensure that the Ethernet module is out of reset */
-       reset = readl(AM3517_IP_SW_RESET);
-       reset &= (~CPGMACSS_SW_RST);
-       writel(reset, AM3517_IP_SW_RESET);
-
        return 0;
 }
 
@@ -142,7 +135,6 @@ void set_muxconf_regs(void)
        MUX_AM3517EVM();
 }
 
-
 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
 int board_eth_init(struct bd_info *bis)
 {
index db2134b..aec2b41 100644 (file)
@@ -122,64 +122,7 @@ const omap3_sysinfo sysinfo = {
        MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)) \
        MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)) \
        MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M4)) /*GPIO_64*/\
-                                                        /* - ETH_nRESET*/\
        MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | EN  | M0)) \
-       /* DSS */\
-       MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) \
-       /* CAMERA */\
-       MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(CAM_XCLKA),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_PCLK),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-                                                        /* - CAM_RESET*/\
-       MUX_VAL(CP(CAM_D0),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D1),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D2),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D3),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D4),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D5),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D6),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D7),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D8),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D9),             (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D10),            (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_D11),            (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-       MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(CSI2_DX0),           (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CSI2_DY0),           (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CSI2_DY1),           (IEN  | PTD | DIS | M0)) \
        /* MMC */\
        MUX_VAL(CP(MMC1_CLK),           (IEN  | PTU | EN  | M0)) \
        MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | DIS | M0)) \
@@ -187,144 +130,15 @@ const omap3_sysinfo sysinfo = {
        MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | DIS | M0)) \
        MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | DIS | M0)) \
        MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | DIS | M0)) \
-       /* WriteProtect */\
-       MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M4)) \
-       MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M4)) /*CardDetect*/\
-       MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M4)) \
-       MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M4)) \
-       \
-       MUX_VAL(CP(MMC2_CLK),           (IEN  | PTD | EN  | M0)) \
-       MUX_VAL(CP(MMC2_CMD),           (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTD | DIS | M0)) \
-       /* McBSP */\
-       MUX_VAL(CP(MCBSP_CLKS),         (IEN  | PTU | DIS | M0)) \
-       MUX_VAL(CP(MCBSP1_CLKR),        (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | EN  | M0)) \
-       MUX_VAL(CP(MCBSP1_DX),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP1_DR),          (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP1_FSX),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP1_CLKX),        (IEN  | PTD | DIS | M0)) \
-       \
-       MUX_VAL(CP(MCBSP2_FSX),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP2_CLKX),        (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP2_DR),          (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP2_DX),          (IDIS | PTD | DIS | M0)) \
-       \
-       MUX_VAL(CP(MCBSP3_DX),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP3_DR),          (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP3_CLKX),        (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCBSP3_FSX),         (IEN  | PTD | DIS | M0)) \
-       \
-       MUX_VAL(CP(MCBSP4_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
-                                                        /* - LCD_INI*/\
-       MUX_VAL(CP(MCBSP4_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
-                                                        /* - LCD_ENVDD */\
-       MUX_VAL(CP(MCBSP4_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
-                                                        /* - LCD_QVGA/nVGA */\
-       MUX_VAL(CP(MCBSP4_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
-                                                        /* - LCD_RESB */\
        /* UART */\
-       MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(UART1_CTS),          (IEN  | PTU | DIS | M0)) \
-       \
-       MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(UART2_CTS),          (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M0)) \
-       MUX_VAL(CP(UART2_RX),           (IEN  | PTD | DIS | M0)) \
-       \
        MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTU | DIS | M0)) \
        MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTD | DIS | M0)) \
        MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)) \
        MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)) \
-       /* I2C */\
-       MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(I2C4_SCL),           (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(I2C4_SDA),           (IEN  | PTU | EN  | M0)) \
-       /* McSPI */\
-       MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | EN  | M0)) \
-       MUX_VAL(CP(MCSPI1_CS1),         (IEN  | PTD | EN  | M4)) /*GPIO_175*/\
-       MUX_VAL(CP(MCSPI1_CS2),         (IEN  | PTU | DIS | M4)) /*GPIO_176*/\
-                                                        /* - LAN_INTR*/\
-       MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M0)) \
-       \
-       MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M4)) \
-       MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M4)) \
-       /* CCDC */\
-       MUX_VAL(CP(CCDC_PCLK),          (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(CCDC_FIELD),         (IEN  | PTD | DIS | M1)) \
-       MUX_VAL(CP(CCDC_HD),            (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(CCDC_VD),            (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(CCDC_WEN),           (IEN  | PTD | DIS | M1)) \
-       MUX_VAL(CP(CCDC_DATA0),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CCDC_DATA1),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CCDC_DATA2),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CCDC_DATA3),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CCDC_DATA4),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CCDC_DATA5),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CCDC_DATA6),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(CCDC_DATA7),         (IEN  | PTD | DIS | M0)) \
-       /* RMII */\
-       MUX_VAL(CP(RMII_MDIO_DATA),     (IEN  |  M0)) \
-       MUX_VAL(CP(RMII_MDIO_CLK),      (M0)) \
-       MUX_VAL(CP(RMII_RXD0)   ,       (IEN  | PTD | M0)) \
-       MUX_VAL(CP(RMII_RXD1),          (IEN  | PTD | M0)) \
-       MUX_VAL(CP(RMII_CRS_DV),        (IEN  | PTD | M0)) \
-       MUX_VAL(CP(RMII_RXER),          (PTD | M0)) \
-       MUX_VAL(CP(RMII_TXD0),          (PTD | M0)) \
-       MUX_VAL(CP(RMII_TXD1),          (PTD | M0)) \
-       MUX_VAL(CP(RMII_TXEN),          (PTD | M0)) \
-       MUX_VAL(CP(RMII_50MHZ_CLK),     (IEN  | PTD | EN  | M0)) \
-       /* HECC */\
-       MUX_VAL(CP(HECC1_TXD),          (IEN  | PTU | EN  | M0)) \
-       MUX_VAL(CP(HECC1_RXD),          (IEN  | PTU | EN  | M0)) \
-       /* HSUSB */\
-       MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)) \
-       MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)) \
-       MUX_VAL(CP(USB0_DRVBUS),        (IEN  | PTD | EN  | M0)) \
-       /* HDQ */\
-       MUX_VAL(CP(HDQ_SIO),            (IEN  | PTU | EN  | M0)) \
        /* Control and debug */\
        MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)) \
        MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)) \
        MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)) \
-       /*SYS_nRESWARM */\
-       MUX_VAL(CP(SYS_NRESWARM),       (IDIS | PTU | EN | M4)) \
-                                                       /* - GPIO30 */\
-       MUX_VAL(CP(SYS_BOOT0),          (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-                                                        /* - PEN_IRQ */\
-       MUX_VAL(CP(SYS_BOOT1),          (IEN  | PTD | DIS | M4)) /*GPIO_3 */\
-       MUX_VAL(CP(SYS_BOOT2),          (IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-       MUX_VAL(CP(SYS_BOOT3),          (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-       MUX_VAL(CP(SYS_BOOT4),          (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-       MUX_VAL(CP(SYS_BOOT5),          (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-       MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
-                                                        /* - VIO_1V8*/\
        MUX_VAL(CP(SYS_BOOT7),          (IEN  | PTD | EN  | M0)) \
        MUX_VAL(CP(SYS_BOOT8),          (IEN  | PTD | EN  | M0)) \
        \
@@ -339,18 +153,6 @@ const omap3_sysinfo sysinfo = {
        MUX_VAL(CP(JTAG_EMU0),          (IEN  | PTD | DIS | M0)) \
        MUX_VAL(CP(JTAG_EMU1),          (IEN  | PTD | DIS | M0)) \
        /* ETK (ES2 onwards) */\
-       MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
-       MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
-       MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
-       MUX_VAL(CP(ETK_D1_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
-       MUX_VAL(CP(ETK_D2_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
-       MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
-       MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
-       MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
-       MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
-       MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
-       MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
-       MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
        MUX_VAL(CP(ETK_D10_ES2),        (IEN  | PTD | DIS | M0)) \
        MUX_VAL(CP(ETK_D11_ES2),        (IEN  | PTD | DIS | M0)) \
        MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTD | DIS | M0)) \
index 3a6f6c1..ba63aa0 100644 (file)
@@ -233,23 +233,6 @@ void set_muxconf_regs(void)
        MUX_VAL(CP(D2D_SREAD), (IEN  | PTD | DIS | M0)) /*d2d_sread*/
        MUX_VAL(CP(D2D_MBUSFLAG), (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/
        MUX_VAL(CP(D2D_SBUSFLAG), (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/
-
-#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
-       MUX_VAL(CP(ETK_D14_ES2), (IEN  | PTD | DIS | M3)) /*HSUSB2_DATA0*/
-       MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTD | DIS | M3)) /*HSUSB2_DATA1*/
-       MUX_VAL(CP(MCSPI1_CS3), (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/
-       MUX_VAL(CP(MCSPI2_CS1), (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/
-       MUX_VAL(CP(MCSPI2_SIMO), (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/
-       MUX_VAL(CP(MCSPI2_SOMI), (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/
-       MUX_VAL(CP(MCSPI2_CS0), (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/
-       MUX_VAL(CP(MCSPI2_CLK), (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/
-       MUX_VAL(CP(SYS_BOOT2),  (IEN  | PTD | DIS | M4)) /* GPIO_4 */
-       MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/
-       MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/
-       MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/
-       MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTD | DIS | M3)) /*HSUSB2_NXT*/
-#endif
-
 }
 
 #endif
diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig
new file mode 100644 (file)
index 0000000..281aa8f
--- /dev/null
@@ -0,0 +1,12 @@
+if TARGET_POMELO
+
+config SYS_BOARD
+       default "pomelo"
+
+config SYS_VENDOR
+       default "phytium"
+
+config SYS_CONFIG_NAME
+       default "pomelo"
+
+endif
diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS
new file mode 100644 (file)
index 0000000..d76a4a0
--- /dev/null
@@ -0,0 +1,8 @@
+POMELO BOARD
+M:     lixinde <lixinde@phytium.com.cn>
+M:     weichangzheng <weichangzheng@phytium.com.cn>
+S:     Maintained
+F:     board/phytium/pomelo/*
+F:     include/configs/pomelo.h
+F:     configs/pomelo_defconfig
+F:     arch/arm/dts/phytium-pomelo.dts
diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile
new file mode 100644 (file)
index 0000000..b9cb360
--- /dev/null
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021
+# lixinde         <lixinde@phytium.com.cn>
+# weichangzheng   <weichangzheng@phytium.com.cn>
+#
+
+obj-y += pomelo.o
+obj-y += pll.o
+obj-y += pcie.o
+obj-y += ddr.o
+obj-y += sec.o
+
+
diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h
new file mode 100644 (file)
index 0000000..005ea59
--- /dev/null
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021
+ * Phytium Technology Ltd <www.phytium.com>
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+
+#ifndef _FT_POMELO_H
+#define _FT_POMELO_H
+
+/* SMCCC ID */
+#define CPU_SVC_VERSION                        0xC2000F00
+#define CPU_GET_RST_SOURCE             0xC2000F01
+#define CPU_INIT_PLL                   0xC2000F02
+#define CPU_INIT_PCIE                  0xC2000F03
+#define CPU_INIT_MEM                   0xC2000F04
+#define CPU_INIT_SEC_SVC               0xC2000F05
+
+/*CPU RESET*/
+#define CPU_RESET_POWER_ON             0x1
+#define CPU_RESET_PLL                  0x4
+#define CPU_RESET_WATCH_DOG            0x8
+
+/* PLL */
+#define PARAMETER_PLL_MAGIC            0x54460010
+
+/* PCIE */
+#define PARAMETER_PCIE_MAGIC           0x54460011
+#define CFG_INDEPENDENT_TREE           0x0
+#define PCI_PEU0                       0x1
+#define PCI_PEU1                       0x1
+#define PEU1_OFFSET                    16
+#define PEU_C_OFFSET_MODE              16
+#define PEU_C_OFFSET_SPEED             0
+#define RC_MODE                                0x1
+#define X8X8                           0x1
+#define GEN3                           3
+
+/* DDR */
+#define PARAMETER_MCU_MAGIC            0x54460014
+#define PARAM_MCU_VERSION              0x1
+#define PARAM_MCU_SIZE                 0x100
+#define PARAM_CH_ENABLE                        0x3
+#define PARAM_ECC_ENABLE               0x3
+#define PARAM_FORCE_SPD_DISABLE                0x0
+#define PARAM_MCU_MISC_ENABLE          0x0
+
+#define UDIMM_TYPE                     0x2
+#define DIMM_X8                                0x1
+#define NO_MIRROR                      0x0
+#define NO_ECC_TYPE                    0
+#define DDR4_TYPE                      0xC
+
+/* SEC */
+#define PARAMETER_COMMON_MAGIC         0x54460013
+
+/* FLUSH L3 CASHE */
+#define HNF_COUNT                      0x8
+#define HNF_PSTATE_REQ                 (HNF_BASE + 0x10)
+#define HNF_PSTATE_STAT                        (HNF_BASE + 0x18)
+#define HNF_PSTATE_OFF                 0x0
+#define HNF_PSTATE_SFONLY              0x1
+#define HNF_PSTATE_HALF                        0x2
+#define HNF_PSTATE_FULL                        0x3
+#define HNF_STRIDE                     0x10000
+#define HNF_BASE                       (unsigned long)(0x3A200000)
+void ddr_init(void);
+void sec_init(void);
+void check_reset(void);
+void pcie_init(void);
+
+#endif /* _FT_POMELO_H */
diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c
new file mode 100644 (file)
index 0000000..c6dbed9
--- /dev/null
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct ddr_spd {
+       /******************* read from spd *****************/
+       u8  dimm_type;  /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */
+       u8  data_width; /* 0: x4; 1: x8; 2: x16 */
+       u8  mirror_type;/* 0: stardard; 1: mirror */
+       u8  ecc_type;   /* 0: no-ecc; 1:ecc */
+       u8  dram_type;  /* 0xB: DDR3; 0xC: DDR4 */
+       u8  rank_num;
+       u8  row_num;
+       u8  col_num;
+
+       u8  bg_num;     /*only DDR4*/
+       u8  bank_num;
+       u16 module_manufacturer_id;
+       u16 taamin;
+       u16 trcdmin;
+
+       u16 trpmin;
+       u16 trasmin;
+       u16 trcmin;
+       u16 tfawmin;
+
+       u16 trrd_smin;  /*only DDR4*/
+       u16 trrd_lmin;  /*only DDR4*/
+       u16 tccd_lmin;  /*only DDR4*/
+       u16 twrmin;
+
+       u16 twtr_smin;  /*only DDR4*/
+       u16 twtr_lmin;  /*only DDR4*/
+       u16 twtrmin;    /*only DDR3*/
+       u16 trrdmin;    /*only DDR3*/
+
+       /******************* RCD control words *****************/
+       u8  f0rc03; /*bit[3:2]:CS               bit[1:0]:CA  */
+       u8  f0rc04; /*bit[3:2]:ODT              bit[1:0]:CKE */
+       u8  f0rc05; /*bit[3:2]:CLK-A side       bit[1:0]:CLK-B side */
+       u8  bc00;
+       u8  bc01;
+       u8  bc02;
+       u8  bc03;
+       u8  bc04;
+
+       u8  bc05;
+       u8  f5bc5x;
+       u8  f5bc6x;
+       /******************* LRDIMM special *****************/
+       u8  vrefdq_pr0;
+       u8  vrefdq_mdram;
+       u8  rtt_mdram_1866;
+       u8  rtt_mdram_2400;
+       u8  rtt_mdram_3200;
+
+       u8  drive_dram;
+       u8  odt_dram_1866;
+       u8  odt_dram_2400;
+       u8  odt_dram_3200;
+       u8  park_dram_1866;
+       u8  park_dram_2400;
+       u8  park_dram_3200;
+       u8  rcd_num;
+} __attribute((aligned(4)));
+
+struct mcu_config {
+       u32 magic;
+       u32 version;
+       u32 size;
+       u8 rev1[4];
+
+       u8 ch_enable;
+       u8 misc1_enable;
+       u8 misc2_enable;
+       u8 force_spd_enable;
+       u8 misc3_enable;
+       u8 train_debug;
+       u8 train_recover;
+       u8 rev2[9];
+
+       struct ddr_spd ddr_spd_info[2];
+} __attribute((aligned(4)));
+
+static void get_mcu_up_info_default(struct mcu_config *pm)
+{
+       pm->magic               = PARAMETER_MCU_MAGIC;
+       pm->version             = PARAM_MCU_VERSION;
+       pm->size                = PARAM_MCU_SIZE;
+       pm->ch_enable           = PARAM_CH_ENABLE;
+       pm->misc1_enable        = PARAM_ECC_ENABLE;
+       pm->force_spd_enable    = PARAM_FORCE_SPD_DISABLE;
+       pm->misc3_enable        = PARAM_MCU_MISC_ENABLE;
+       pm->train_recover       = 0x0;
+}
+
+static u8 init_dimm_param(u8 ch, struct mcu_config *pm)
+{
+       debug("manual config dimm info...\n");
+       pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE;
+       pm->ddr_spd_info[ch].data_width = DIMM_X8;
+       pm->ddr_spd_info[ch].mirror_type = NO_MIRROR;
+       pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE;
+       pm->ddr_spd_info[ch].dram_type = DDR4_TYPE;
+       pm->ddr_spd_info[ch].rank_num = 1;
+       pm->ddr_spd_info[ch].row_num  = 16;
+       pm->ddr_spd_info[ch].col_num = 10;
+       pm->ddr_spd_info[ch].bg_num = 4;
+       pm->ddr_spd_info[ch].bank_num = 4;
+       pm->ddr_spd_info[ch].taamin = 13750;
+       pm->ddr_spd_info[ch].trcdmin = 13750;
+
+       pm->ddr_spd_info[ch].trpmin = 13750;
+       pm->ddr_spd_info[ch].trasmin = 32000;
+       pm->ddr_spd_info[ch].trcmin =  45750;
+       pm->ddr_spd_info[ch].tfawmin = 21000;
+
+       pm->ddr_spd_info[ch].trrd_smin = 3000;
+       pm->ddr_spd_info[ch].trrd_lmin = 4900;
+       pm->ddr_spd_info[ch].tccd_lmin = 5000;
+       pm->ddr_spd_info[ch].twrmin = 15000;
+
+       pm->ddr_spd_info[ch].twtr_smin = 2500;
+       pm->ddr_spd_info[ch].twtr_lmin = 7500;
+
+       return 0;
+}
+
+void get_default_mcu_info(u8 *data)
+{
+       get_mcu_up_info_default((struct mcu_config *)data);
+}
+
+void fix_mcu_info(u8 *data)
+{
+       struct mcu_config *mcu_info = (struct mcu_config *)data;
+
+       for (int ch = 0; ch < 2; ch++)
+               init_dimm_param(ch, mcu_info);
+}
+
+void ddr_init(void)
+{
+       u8 buffer[0x100];
+       struct arm_smccc_res res;
+
+       get_default_mcu_info(buffer);
+       fix_mcu_info(buffer);
+
+       arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+       if (res.a0 != 0)
+               panic("DRAM init failed :0x%lx\n", res.a0);
+}
diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c
new file mode 100644 (file)
index 0000000..698d82f
--- /dev/null
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct pcu_ctr {
+       u32 base_config[3];
+       u32 equalization[3];
+       u8 rev[80];
+} __attribute((aligned(4)));
+
+struct pcu_config {
+       u32 magic;
+       u32 version;
+       u32 size;
+       u8 rev1[4];
+       u32 independent_tree;
+       u32 base_cfg;
+       u8 rev2[16];
+       struct pcu_ctr ctr_cfg[2];
+} __attribute((aligned(4)));
+
+struct pcu_config const peu_base_info = {
+       .magic = PARAMETER_PCIE_MAGIC,
+       .version = 0x2,
+       .size = 0x100,
+       .independent_tree = CFG_INDEPENDENT_TREE,
+       .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))),
+       .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+       .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+       .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+       .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+       .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+       .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+       .ctr_cfg[0].equalization[0] = 0x7,
+       .ctr_cfg[0].equalization[1] = 0x7,
+       .ctr_cfg[0].equalization[2] = 0x7,
+       .ctr_cfg[1].equalization[0] = 0x7,
+       .ctr_cfg[1].equalization[1] = 0x7,
+       .ctr_cfg[1].equalization[2] = 0x7,
+};
+
+void pcie_init(void)
+{
+       u8 buffer[0x100];
+       struct arm_smccc_res res;
+
+       memcpy(buffer, &peu_base_info, sizeof(peu_base_info));
+       arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+       if (res.a0 != 0)
+               panic("PCIE init failed :0x%lx\n", res.a0);
+}
diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c
new file mode 100644 (file)
index 0000000..a66ffdd
--- /dev/null
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct pll_config {
+       u32 magic;
+       u32 version;
+       u32 size;
+       u8 rev1[4];
+       u32 core_pll;
+       u32 res1;
+       u32 lmu_pll;
+       u32 res2;
+       u32 res3;
+       u32 res4;
+       u32 res5;
+} __attribute((aligned(4)));
+
+struct pll_config const pll_base_info = {
+       .magic = PARAMETER_PLL_MAGIC,
+       .version = 0x1,
+       .size = 0x30,
+       .core_pll = 2300,       /*MHz*/
+       .lmu_pll = 667,         /*MHz*/
+};
+
+u32 get_reset_source(void)
+{
+       struct arm_smccc_res res;
+
+       arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res);
+       return res.a0;
+}
+
+void pll_init(void)
+{
+       u8 buffer[0x100];
+       struct arm_smccc_res res;
+
+       memcpy(buffer, &pll_base_info, sizeof(pll_base_info));
+       arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+       if (res.a0 != 0)
+               panic("PLL init failed :0x%lx\n", res.a0);
+}
+
+void check_reset(void)
+{
+       u32 rst;
+
+       rst = get_reset_source();
+
+       switch (rst) {
+       case CPU_RESET_POWER_ON:
+               pll_init();
+               break;
+       case CPU_RESET_PLL:
+               break;
+       case CPU_RESET_WATCH_DOG:
+               break;
+       default:
+               panic("other reset source\n");
+       }
+}
diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c
new file mode 100644 (file)
index 0000000..4fbe1e5
--- /dev/null
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <command.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <scsi.h>
+#include <init.h>
+#include <asm/u-boot.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       debug("Phytium ddr init\n");
+       ddr_init();
+
+       gd->mem_clk = 0;
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000);
+
+       sec_init();
+       debug("PBF relocate done\n");
+
+       return 0;
+}
+
+int board_init(void)
+{
+       return 0;
+}
+
+void reset_cpu(void)
+{
+       struct arm_smccc_res res;
+
+       debug("run in reset cpu\n");
+       arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
+       if (res.a0 != 0)
+               panic("reset cpu error, %lx\n", res.a0);
+}
+
+int mach_cpu_init(void)
+{
+       check_reset();
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       pcie_init();
+       return 0;
+}
+
+static struct mm_region pomelo_mem_map[] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                                PTE_BLOCK_NON_SHARE |
+                                PTE_BLOCK_PXN |
+                                PTE_BLOCK_UXN
+       },
+       {
+               .virt = 0x80000000UL,
+               .phys = 0x80000000UL,
+               .size = 0x7b000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                                PTE_BLOCK_NS |
+                                PTE_BLOCK_INNER_SHARE
+       },
+       {
+               0,
+       }
+};
+
+struct mm_region *mem_map = pomelo_mem_map;
+
+int __asm_flush_l3_dcache(void)
+{
+       int i, pstate;
+
+       for (i = 0; i < HNF_COUNT; i++)
+               writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
+       for (i = 0; i < HNF_COUNT; i++) {
+               do {
+                       pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
+               } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
+       }
+
+       for (i = 0; i < HNF_COUNT; i++)
+               writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
+
+       return 0;
+}
+
+int last_stage_init(void)
+{
+       int ret;
+
+       /* pci e */
+       pci_init();
+       /* scsi scan */
+       ret = scsi_scan(true);
+       if (ret) {
+               printf("scsi scan failed\n");
+               return CMD_RET_FAILURE;
+       }
+       return ret;
+}
diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c
new file mode 100644 (file)
index 0000000..aeb3983
--- /dev/null
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct common_config {
+       u32 magic;
+       u32 version;
+       u32 size;
+       u8 rev1[4];
+       u64  core_bit_map;
+} __attribute((aligned(4)));
+
+struct common_config const common_base_info = {
+       .magic = PARAMETER_COMMON_MAGIC,
+       .version = 0x1,
+       .core_bit_map = 0x3333,
+};
+
+void sec_init(void)
+{
+       u8 buffer[0x100];
+       struct arm_smccc_res res;
+
+       memcpy(buffer, &common_base_info, sizeof(common_base_info));
+       arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+       if (res.a0 != 0)
+               panic("SEC init failed :0x%lx\n", res.a0);
+}
index 82c52b2..a096159 100644 (file)
@@ -171,21 +171,56 @@ void i2c_init_board(void)
 #endif
 }
 
-#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
+/*
+ * Try to use the environment from the boot source first.
+ * For MMC, this means a FAT partition on the boot device (SD or eMMC).
+ * If the raw MMC environment is also enabled, this is tried next.
+ * SPI flash falls back to FAT (on SD card).
+ */
 enum env_location env_get_location(enum env_operation op, int prio)
 {
-       switch (prio) {
-       case 0:
-               return ENVL_FAT;
+       enum env_location boot_loc = ENVL_FAT;
 
-       case 1:
-               return ENVL_MMC;
+       gd->env_load_prio = prio;
 
+       switch (sunxi_get_boot_device()) {
+       case BOOT_DEVICE_MMC1:
+       case BOOT_DEVICE_MMC2:
+               boot_loc = ENVL_FAT;
+               break;
+       case BOOT_DEVICE_NAND:
+               if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+                       boot_loc = ENVL_NAND;
+               break;
+       case BOOT_DEVICE_SPI:
+               if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+                       boot_loc = ENVL_SPI_FLASH;
+               break;
+       case BOOT_DEVICE_BOARD:
+               break;
        default:
-               return ENVL_UNKNOWN;
+               break;
+       }
+
+       /* Always try to access the environment on the boot device first. */
+       if (prio == 0)
+               return boot_loc;
+
+       if (prio == 1) {
+               switch (boot_loc) {
+               case ENVL_SPI_FLASH:
+                       return ENVL_FAT;
+               case ENVL_FAT:
+                       if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+                               return ENVL_MMC;
+                       break;
+               default:
+                       break;
+               }
        }
+
+       return ENVL_UNKNOWN;
 }
-#endif
 
 #ifdef CONFIG_DM_MMC
 static void mmc_pinmux_setup(int sdc);
index 888a958..847d596 100644 (file)
@@ -447,6 +447,8 @@ int misc_init_r(void)
                env_set(expansion_config.env_var, expansion_config.env_setting);
 
        twl4030_power_init();
+       twl4030_power_mmc_init(0);
+
        switch (get_board_revision()) {
        case REVISION_XM_AB:
                twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
@@ -499,17 +501,3 @@ void set_muxconf_regs(void)
 {
        MUX_BEAGLE();
 }
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(struct bd_info *bis)
-{
-       return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
-       twl4030_power_mmc_init(0);
-}
-#endif
index f479197..e6ff54c 100644 (file)
@@ -397,36 +397,34 @@ void configure_serdes_torrent(void)
 
 void configure_serdes_sierra(void)
 {
-       struct udevice *dev, *lnk_dev;
-       struct phy serdes;
+       struct udevice *dev, *link_dev;
+       struct phy link;
        int ret, count, i;
+       int link_count = 0;
 
        if (!IS_ENABLED(CONFIG_PHY_CADENCE_SIERRA))
                return;
 
-       ret = uclass_get_device_by_driver(UCLASS_PHY,
+       ret = uclass_get_device_by_driver(UCLASS_MISC,
                                          DM_DRIVER_GET(sierra_phy_provider),
                                          &dev);
        if (ret)
                printf("Sierra init failed:%d\n", ret);
 
-       serdes.dev = dev;
-       serdes.id = 0;
-
        count = device_get_child_count(dev);
        for (i = 0; i < count; i++) {
-               ret = device_get_child(dev, i, &lnk_dev);
+               ret = device_get_child(dev, i, &link_dev);
                if (ret)
                        printf("probe of sierra child node %d failed\n", i);
-       }
+               if (link_dev->driver->id == UCLASS_PHY) {
+                       link.dev = link_dev;
+                       link.id = link_count++;
 
-       ret = generic_phy_init(&serdes);
-       if (ret)
-               printf("phy_init failed!!\n");
-
-       ret = generic_phy_power_on(&serdes);
-       if (ret)
-               printf("phy_power_on failed !!\n");
+                       ret = generic_phy_power_on(&link);
+                       if (ret)
+                               printf("phy_power_on failed !!\n");
+               }
+       }
 }
 
 #ifdef CONFIG_BOARD_LATE_INIT
index 5e25e45..9d0e803 100644 (file)
@@ -1485,6 +1485,15 @@ config CMD_DHCP
        help
          Boot image via network using DHCP/TFTP protocol
 
+config BOOTP_MAY_FAIL
+       bool "Allow for the BOOTP/DHCP server to not be found"
+       depends on CMD_BOOTP
+       help
+         If the DHCP server is not found after the configured retry count, the
+         call will fail instead of starting over.  This can be used to fail
+         over to Link-local IP address configuration if the DHCP server is not
+         available.
+
 config BOOTP_BOOTPATH
        bool "Request & store 'rootpath' from BOOTP/DHCP server"
        default y
@@ -1493,6 +1502,14 @@ config BOOTP_BOOTPATH
          Even though the config is called BOOTP_BOOTPATH, it stores the
          path in the variable 'rootpath'.
 
+config BOOTP_VENDOREX
+       bool "Support vendor extensions from BOOTP/DHCP server"
+       depends on CMD_BOOTP
+
+config BOOTP_BOOTFILESIZE
+       bool "Request & store 'bootfilesize' from BOOTP/DHCP server"
+       depends on CMD_BOOTP
+
 config BOOTP_DNS
        bool "Request & store 'dnsip' from BOOTP/DHCP server"
        default y
@@ -1540,10 +1557,18 @@ config BOOTP_SUBNETMASK
        default y
        depends on CMD_BOOTP
 
+config BOOTP_NISDOMAIN
+       bool "Request & store 'nisdomain' from BOOTP/DHCP server"
+       depends on CMD_BOOTP
+
 config BOOTP_NTPSERVER
        bool "Request & store 'ntpserverip' from BOOTP/DHCP server"
        depends on CMD_BOOTP
 
+config BOOTP_TIMEOFFSET
+       bool "Request & store 'timeoffset' from BOOTP/DHCP server"
+       depends on CMD_BOOTP && CMD_SNTP
+
 config CMD_PCAP
        bool "pcap capture"
        help
@@ -2176,6 +2201,12 @@ config CMD_CRAMFS
             cramfsls   - lists files in a cramfs image
             cramfsload - loads a file from a cramfs image
 
+config CMD_EROFS
+       bool "EROFS command support"
+       select FS_EROFS
+       help
+         Support for the EROFS fs
+
 config CMD_EXT2
        bool "ext2 command support"
        select FS_EXT4
@@ -2342,6 +2373,14 @@ config CMD_DIAG
          available tests and running either all the tests, or specific tests
          identified by name.
 
+config CMD_EVENT
+       bool "event - Show information about events"
+       default y if EVENT_DEBUG
+       help
+         This enables the 'event' command which provides information about
+         events and event-handler routines. This can help to device event
+         hadling.
+
 config CMD_IRQ
        bool "irq - Show information about interrupts"
        depends on !ARM && !MIPS && !RISCV && !SH
index 166c652..ede634d 100644 (file)
@@ -53,6 +53,7 @@ obj-$(CONFIG_CMD_DIAG) += diag.o
 endif
 obj-$(CONFIG_CMD_ADTIMG) += adtimg.o
 obj-$(CONFIG_CMD_ABOOTIMG) += abootimg.o
+obj-$(CONFIG_CMD_EVENT) += event.o
 obj-$(CONFIG_CMD_EXTENSION) += extension_board.o
 obj-$(CONFIG_CMD_ECHO) += echo.o
 obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
@@ -60,6 +61,7 @@ obj-$(CONFIG_CMD_EEPROM) += eeprom.o
 obj-$(CONFIG_EFI) += efi.o
 obj-$(CONFIG_CMD_EFIDEBUG) += efidebug.o
 obj-$(CONFIG_CMD_ELF) += elf.o
+obj-$(CONFIG_CMD_EROFS) += erofs.o
 obj-$(CONFIG_HUSH_PARSER) += exit.o
 obj-$(CONFIG_CMD_EXT4) += ext4.o
 obj-$(CONFIG_CMD_EXT2) += ext2.o
index d5de50a..589a231 100644 (file)
@@ -7,19 +7,73 @@
 
 #include <common.h>
 #include <command.h>
+#include <linux/bitops.h>
 
 static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
                        char *const argv[])
 {
        /*
-        * 0xe7f...f.   is undefined in ARM mode
-        * 0xde..       is undefined in Thumb mode
+        * Instructions starting with the upper 16 bits all 0 are permanently
+        * undefined. The lower 16 bits can be used for some kind of immediate.
+        * --- ARMv8 ARM (ARM DDI 0487G.a C6.2.339: "UDF")
         */
-       asm volatile (".word 0xe7f7defb\n");
+       asm volatile (".word 0x00001234\n");
+
+       return CMD_RET_FAILURE;
+}
+
+/*
+ * The ID_AA64MMFR2_EL1 register name is only know to binutils for ARMv8.2
+ * and later architecture revisions. However the register is valid regardless
+ * of binutils architecture support or the core the code is running on, so
+ * just use the generic encoding.
+ */
+#define ID_AA64MMFR2_EL1 "S3_0_C0_C7_2"
+
+static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
+                       char *const argv[])
+{
+       uint64_t reg;
+
+       /*
+        * The unaligned LDAR access below is only guaranteed to generate an
+        * alignment fault on cores not implementing FEAT_LSE2. To avoid false
+        * negatives, check this condition before we exectute LDAR.
+        */
+       asm ("mrs %0, "ID_AA64MMFR2_EL1"\n" : "=r" (reg));
+       if (reg & GENMASK(35, 32)) {
+               printf("unaligned access check only supported on pre-v8.4 cores\n");
+               return CMD_RET_FAILURE;
+       }
+
+       /*
+        * The load acquire instruction requires the data source to be
+        * naturally aligned, and will fault even if strict alignment fault
+        * checking is disabled (but only without FEAT_LSE2).
+        * --- ARMv8 ARM (ARM DDI 0487G.a B2.5.2: "Alignment of data accesses")
+        */
+       asm volatile (
+               "mov    x1, sp\n\t"
+               "orr    x1, x1, #3\n\t"
+               "ldar   x0, [x1]\n"
+               ::: "x0", "x1" );
+
+       return CMD_RET_FAILURE;
+}
+
+static int do_breakpoint(struct cmd_tbl *cmdtp, int flag, int argc,
+                        char *const argv[])
+{
+       asm volatile ("brk      #123\n");
+
        return CMD_RET_FAILURE;
 }
 
 static struct cmd_tbl cmd_sub[] = {
+       U_BOOT_CMD_MKENT(breakpoint, CONFIG_SYS_MAXARGS, 1, do_breakpoint,
+                        "", ""),
+       U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
+                        "", ""),
        U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
                         "", ""),
 };
@@ -27,7 +81,9 @@ static struct cmd_tbl cmd_sub[] = {
 static char exception_help_text[] =
        "<ex>\n"
        "  The following exceptions are available:\n"
-       "  undefined  - undefined instruction\n"
+       "  breakpoint - breakpoint instruction exception\n"
+       "  unaligned  - unaligned LDAR data abort\n"
+       "  undefined  - undefined instruction exception\n"
        ;
 
 #include <exception.h>
index eab4e69..bdeb497 100644 (file)
--- a/cmd/cls.c
+++ b/cmd/cls.c
 #include <lcd.h>
 #include <video.h>
 
+#define CSI "\x1b["
+
 static int do_video_clear(struct cmd_tbl *cmdtp, int flag, int argc,
                          char *const argv[])
 {
-#if defined(CONFIG_DM_VIDEO)
-       struct udevice *dev;
+       __maybe_unused struct udevice *dev;
 
+       /*  Send clear screen and home */
+       printf(CSI "2J" CSI "1;1H");
+#if defined(CONFIG_DM_VIDEO)
+#if !defined(CONFIG_VIDEO_ANSI)
        if (uclass_first_device_err(UCLASS_VIDEO, &dev))
                return CMD_RET_FAILURE;
 
        if (video_clear(dev))
                return CMD_RET_FAILURE;
+#endif
 #elif defined(CONFIG_CFB_CONSOLE)
        video_clear();
 #elif defined(CONFIG_LCD)
diff --git a/cmd/erofs.c b/cmd/erofs.c
new file mode 100644 (file)
index 0000000..add80b8
--- /dev/null
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Huang Jianan <jnhuang95@gmail.com>
+ *
+ * Author: Huang Jianan <jnhuang95@gmail.com>
+ *
+ * erofs.c:    implements EROFS related commands
+ */
+
+#include <command.h>
+#include <fs.h>
+#include <erofs.h>
+
+static int do_erofs_ls(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+       return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EROFS);
+}
+
+U_BOOT_CMD(erofsls, 4, 1, do_erofs_ls,
+          "List files in directory. Default: root (/).",
+          "<interface> [<dev[:part]>] [directory]\n"
+          "    - list files from 'dev' on 'interface' in 'directory'\n"
+);
+
+static int do_erofs_load(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+       return do_load(cmdtp, flag, argc, argv, FS_TYPE_EROFS);
+}
+
+U_BOOT_CMD(erofsload, 7, 0, do_erofs_load,
+          "load binary file from a EROFS filesystem",
+          "<interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]]\n"
+          "    - Load binary file 'filename' from 'dev' on 'interface'\n"
+          "      to address 'addr' from EROFS filesystem.\n"
+          "      'pos' gives the file position to start loading from.\n"
+          "      If 'pos' is omitted, 0 is used. 'pos' requires 'bytes'.\n"
+          "      'bytes' gives the size to load. If 'bytes' is 0 or omitted,\n"
+          "      the load stops on end of file.\n"
+          "      If either 'pos' or 'bytes' are not aligned to\n"
+          "      ARCH_DMA_MINALIGN then a misaligned buffer warning will\n"
+          "      be printed and performance will suffer for the load."
+);
diff --git a/cmd/event.c b/cmd/event.c
new file mode 100644 (file)
index 0000000..9cac202
--- /dev/null
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Command-line access to events
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <event.h>
+
+static int do_event_list(struct cmd_tbl *cmdtp, int flag, int argc,
+                        char *const argv[])
+{
+       event_show_spy_list();
+
+       return 0;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char event_help_text[] =
+       "event list   - list event spies";
+#endif
+
+U_BOOT_CMD_WITH_SUBCMDS(event, "Events", event_help_text,
+       U_BOOT_SUBCMD_MKENT(list, 1, 1, do_event_list));
index 82cd864..24c83f0 100644 (file)
@@ -492,6 +492,37 @@ config DISPLAY_BOARDINFO_LATE
 
 menu "Start-up hooks"
 
+config EVENT
+       bool "General-purpose event-handling mechanism"
+       default y if SANDBOX
+       help
+         This enables sending and processing of events, to allow interested
+         parties to be alerted when something happens. This is an attempt to
+         step the flow of weak functions, hooks, functions in board_f.c
+         and board_r.c and the Kconfig options below.
+
+         See doc/develop/event.rst for more information.
+
+if EVENT
+
+config EVENT_DYNAMIC
+       bool "Support event registration at runtime"
+       default y if SANDBOX
+       help
+         Enable this to support adding an event spy at runtime, without adding
+         it to the EVENT_SPy() linker list. This increases code size slightly
+         but provides more flexibility for boards and subsystems that need it.
+
+config EVENT_DEBUG
+       bool "Enable event debugging assistance"
+       default y if SANDBOX
+       help
+         Enable this get usefui features for seeing what is happening with
+         events, such as event-type names. This adds to the code size of
+         U-Boot so can be turned off for production builds.
+
+endif # EVENT
+
 config ARCH_EARLY_INIT_R
        bool "Call arch-specific init soon after relocation"
        help
@@ -524,6 +555,12 @@ config BOARD_EARLY_INIT_R
          relocation. With this option, U-Boot calls board_early_init_r()
          in the post-relocation init sequence.
 
+config BOARD_POSTCLK_INIT
+       bool "Call board_postclk_init"
+       help
+         Some boards need this to initialize select items, after clocks /
+         timebase and before env / serial.
+
 config BOARD_LATE_INIT
        bool "Execute Board late init"
        help
@@ -552,12 +589,6 @@ config LAST_STAGE_INIT
          U-Boot calls last_stage_init() before the command-line interpreter is
          started.
 
-config MISC_INIT_F
-       bool "Execute pre-relocation misc init"
-       help
-         Enabling this option calls the 'misc_init_f' function in the init
-         sequence just before DRAM is inited.
-
 config MISC_INIT_R
        bool "Execute Misc Init"
        default y if ARCH_KEYSTONE || ARCH_SUNXI || MPC85xx
index 3eff719..cc2ba30 100644 (file)
@@ -89,6 +89,8 @@ obj-y += malloc_simple.o
 endif
 endif
 
+obj-$(CONFIG_$(SPL_TPL_)EVENT) += event.o
+
 obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o
 obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
index a687600..5b655ad 100644 (file)
@@ -19,6 +19,7 @@
 #include <dm.h>
 #include <env.h>
 #include <env_internal.h>
+#include <event.h>
 #include <fdtdec.h>
 #include <fs.h>
 #include <hang.h>
@@ -802,19 +803,19 @@ __weak int reserve_arch(void)
        return 0;
 }
 
-__weak int arch_cpu_init_dm(void)
+__weak int checkcpu(void)
 {
        return 0;
 }
 
-__weak int checkcpu(void)
+__weak int clear_bss(void)
 {
        return 0;
 }
 
-__weak int clear_bss(void)
+static int misc_init_f(void)
 {
-       return 0;
+       return event_notify_null(EVT_MISC_INIT_F);
 }
 
 static const init_fnc_t init_sequence_f[] = {
@@ -828,6 +829,7 @@ static const init_fnc_t init_sequence_f[] = {
        initf_malloc,
        log_init,
        initf_bootstage,        /* uses its own timer, so does not need DM */
+       event_init,
 #ifdef CONFIG_BLOBLIST
        bloblist_init,
 #endif
@@ -841,7 +843,6 @@ static const init_fnc_t init_sequence_f[] = {
        arch_cpu_init,          /* basic arch cpu dependent setup */
        mach_cpu_init,          /* SoC/machine dependent CPU setup */
        initf_dm,
-       arch_cpu_init_dm,
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
        board_early_init_f,
 #endif
@@ -875,9 +876,7 @@ static const init_fnc_t init_sequence_f[] = {
        show_board_info,
 #endif
        INIT_FUNC_WATCHDOG_INIT
-#if defined(CONFIG_MISC_INIT_F)
        misc_init_f,
-#endif
        INIT_FUNC_WATCHDOG_RESET
 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
        init_func_i2c,
index c24d9b4..b92c1bb 100644 (file)
@@ -594,6 +594,7 @@ static int run_main_loop(void)
 static init_fnc_t init_sequence_r[] = {
        initr_trace,
        initr_reloc,
+       event_init,
        /* TODO: could x86/PPC have this also perhaps? */
 #if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
        initr_caches,
diff --git a/common/event.c b/common/event.c
new file mode 100644 (file)
index 0000000..9d67a06
--- /dev/null
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Events provide a general-purpose way to react to / subscribe to changes
+ * within U-Boot
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY   LOGC_EVENT
+
+#include <common.h>
+#include <event.h>
+#include <event_internal.h>
+#include <log.h>
+#include <linker_lists.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <linux/list.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(EVENT_DEBUG)
+const char *const type_name[] = {
+       "none",
+       "test",
+
+       /* Events related to driver model */
+       "dm_post_init",
+       "dm_pre_probe",
+       "dm_post_probe",
+       "dm_pre_remove",
+       "dm_post_remove",
+
+       /* init hooks */
+       "misc_init_f",
+};
+
+_Static_assert(ARRAY_SIZE(type_name) == EVT_COUNT, "event type_name size");
+#endif
+
+static const char *event_type_name(enum event_t type)
+{
+#if CONFIG_IS_ENABLED(EVENT_DEBUG)
+       return type_name[type];
+#else
+       return "(unknown)";
+#endif
+}
+
+static int notify_static(struct event *ev)
+{
+       struct evspy_info *start =
+               ll_entry_start(struct evspy_info, evspy_info);
+       const int n_ents = ll_entry_count(struct evspy_info, evspy_info);
+       struct evspy_info *spy;
+
+       for (spy = start; spy != start + n_ents; spy++) {
+               if (spy->type == ev->type) {
+                       int ret;
+
+                       log_debug("Sending event %x/%s to spy '%s'\n", ev->type,
+                                 event_type_name(ev->type), event_spy_id(spy));
+                       ret = spy->func(NULL, ev);
+
+                       /*
+                        * TODO: Handle various return codes to
+                        *
+                        * - claim an event (no others will see it)
+                        * - return an error from the event
+                        */
+                       if (ret)
+                               return log_msg_ret("spy", ret);
+               }
+       }
+
+       return 0;
+}
+
+static int notify_dynamic(struct event *ev)
+{
+       struct event_state *state = gd_event_state();
+       struct event_spy *spy, *next;
+
+       list_for_each_entry_safe(spy, next, &state->spy_head, sibling_node) {
+               if (spy->type == ev->type) {
+                       int ret;
+
+                       log_debug("Sending event %x/%s to spy '%s'\n", ev->type,
+                                 event_type_name(ev->type), spy->id);
+                       ret = spy->func(spy->ctx, ev);
+
+                       /*
+                        * TODO: Handle various return codes to
+                        *
+                        * - claim an event (no others will see it)
+                        * - return an error from the event
+                        */
+                       if (ret)
+                               return log_msg_ret("spy", ret);
+               }
+       }
+
+       return 0;
+}
+
+int event_notify(enum event_t type, void *data, int size)
+{
+       struct event event;
+       int ret;
+
+       event.type = type;
+       if (size > sizeof(event.data))
+               return log_msg_ret("size", -E2BIG);
+       memcpy(&event.data, data, size);
+
+       ret = notify_static(&event);
+       if (ret)
+               return log_msg_ret("dyn", ret);
+
+       if (CONFIG_IS_ENABLED(EVENT_DYNAMIC)) {
+               ret = notify_dynamic(&event);
+               if (ret)
+                       return log_msg_ret("dyn", ret);
+       }
+
+       return 0;
+}
+
+int event_notify_null(enum event_t type)
+{
+       return event_notify(type, NULL, 0);
+}
+
+void event_show_spy_list(void)
+{
+       struct evspy_info *start =
+               ll_entry_start(struct evspy_info, evspy_info);
+       const int n_ents = ll_entry_count(struct evspy_info, evspy_info);
+       struct evspy_info *spy;
+       const int size = sizeof(ulong) * 2;
+
+       printf("Seq  %-24s  %*s  %s\n", "Type", size, "Function", "ID");
+       for (spy = start; spy != start + n_ents; spy++) {
+               printf("%3x  %-3x %-20s  %*p  %s\n", (uint)(spy - start),
+                      spy->type, event_type_name(spy->type), size, spy->func,
+                      event_spy_id(spy));
+       }
+}
+
+#if CONFIG_IS_ENABLED(EVENT_DYNAMIC)
+static void spy_free(struct event_spy *spy)
+{
+       list_del(&spy->sibling_node);
+}
+
+int event_register(const char *id, enum event_t type, event_handler_t func, void *ctx)
+{
+       struct event_state *state = gd_event_state();
+       struct event_spy *spy;
+
+       if (!CONFIG_IS_ENABLED(EVENT_DYNAMIC))
+               return -ENOSYS;
+       spy = malloc(sizeof(*spy));
+       if (!spy)
+               return log_msg_ret("alloc", -ENOMEM);
+
+       spy->id = id;
+       spy->type = type;
+       spy->func = func;
+       spy->ctx = ctx;
+       list_add_tail(&spy->sibling_node, &state->spy_head);
+
+       return 0;
+}
+
+int event_uninit(void)
+{
+       struct event_state *state = gd_event_state();
+       struct event_spy *spy, *next;
+
+       list_for_each_entry_safe(spy, next, &state->spy_head, sibling_node)
+               spy_free(spy);
+
+       return 0;
+}
+
+int event_init(void)
+{
+       struct event_state *state = gd_event_state();
+
+       INIT_LIST_HEAD(&state->spy_head);
+
+       return 0;
+}
+#endif /* EVENT_DYNAMIC */
index f7e0c0f..7254aa7 100644 (file)
@@ -28,6 +28,7 @@ static const char *const log_cat_name[] = {
        "devres",
        "acpi",
        "boot",
+       "event",
 };
 
 _Static_assert(ARRAY_SIZE(log_cat_name) == LOGC_COUNT - LOGC_NONE,
index 7f5ca9a..e98b81e 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CPU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index e7911f0..ba2dce8 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CPU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index abac898..424e816 100644 (file)
@@ -18,12 +18,15 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="u-boot.bin"
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_FSL=y
 CONFIG_SYS_FSL_I2C_OFFSET=0x300
index 8a12e4b..9a8656a 100644 (file)
@@ -18,12 +18,15 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="u-boot.bin"
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_FSL=y
 CONFIG_SYS_FSL_I2C_OFFSET=0x300
index e46b097..90f98ee 100644 (file)
@@ -15,6 +15,7 @@ CONFIG_CMD_IMLS=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
index 3cb77b7..073bc96 100644 (file)
@@ -19,6 +19,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
index 0d17cf5..3e8e8b5 100644 (file)
@@ -15,6 +15,7 @@ CONFIG_CMD_IMLS=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
index eac5b74..c21caee 100644 (file)
@@ -160,6 +160,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
@@ -168,6 +169,8 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_ADDR=0xFE080000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_SATA=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
index d6351d5..76d2b55 100644 (file)
@@ -23,13 +23,17 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_ADDR=0xFFF60000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="8548cds/uImage.uboot"
 CONFIG_DM=y
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
index da0b80b..6a55087 100644 (file)
@@ -22,13 +22,17 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_ADDR=0xFFF60000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="8548cds/uImage.uboot"
 CONFIG_DM=y
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
index 87d1fd7..ae262bf 100644 (file)
@@ -22,13 +22,17 @@ CONFIG_CMD_IMLS=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_ADDR=0xFFF60000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="8548cds/uImage.uboot"
 CONFIG_DM=y
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
index 61fd2a7..0782dce 100644 (file)
@@ -53,10 +53,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 0e537eb..9c0df84 100644 (file)
@@ -35,10 +35,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index dc113be..5804ba7 100644 (file)
@@ -47,10 +47,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index cd5c80c..bcf82eb 100644 (file)
@@ -49,10 +49,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index f80a0d9..a1cd44b 100644 (file)
@@ -52,10 +52,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 035aac2..3ce8e3f 100644 (file)
@@ -34,10 +34,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index cd031d2..7a6b19c 100644 (file)
@@ -46,10 +46,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index f339502..22798d8 100644 (file)
@@ -48,10 +48,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index ba64f88..f861734 100644 (file)
@@ -54,10 +54,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index a8e9556..80a8f4e 100644 (file)
@@ -36,10 +36,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 8719967..4082cef 100644 (file)
@@ -48,10 +48,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 2d646f9..4b58168 100644 (file)
@@ -50,10 +50,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index f8437ff..d8e5882 100644 (file)
@@ -53,10 +53,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index b99531c..bec233f 100644 (file)
@@ -35,10 +35,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index ebe2af6..f8a795d 100644 (file)
@@ -47,10 +47,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 7893782..510ff5e 100644 (file)
@@ -49,10 +49,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 30b841d..b499ec3 100644 (file)
@@ -53,8 +53,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
index 79edbf3..530693b 100644 (file)
@@ -48,8 +48,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index c5a64de..75e5851 100644 (file)
@@ -50,8 +50,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 9671a6d..79afdab 100644 (file)
@@ -37,8 +37,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 0201c51..44a4ec9 100644 (file)
@@ -52,8 +52,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
index 371a8b5..7e06a9a 100644 (file)
@@ -47,8 +47,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 7c8b3c8..da35cdd 100644 (file)
@@ -49,8 +49,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 01b4fd3..c8919b7 100644 (file)
@@ -36,8 +36,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index e70c1a7..cfc73c4 100644 (file)
@@ -55,8 +55,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8796
index 2596b52..2d35773 100644 (file)
@@ -50,8 +50,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index f6f8888..bce232e 100644 (file)
@@ -52,8 +52,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index e1a4965..5b10317 100644 (file)
@@ -39,8 +39,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 2c302b6..1731d4f 100644 (file)
@@ -57,8 +57,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
index 2d08071..6662fe9 100644 (file)
@@ -52,8 +52,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 7b53b02..d9d1f8b 100644 (file)
@@ -54,8 +54,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 5e8a474..6111d3b 100644 (file)
@@ -41,8 +41,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 74165dc..9e0de44 100644 (file)
@@ -56,8 +56,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
index 0505f40..cbe30d3 100644 (file)
@@ -51,8 +51,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index f1085fd..7f73500 100644 (file)
@@ -53,8 +53,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index f933ed4..728336e 100644 (file)
@@ -40,8 +40,11 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=1
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
index 01d6192..4103ac8 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index dc56c79..b28903e 100644 (file)
@@ -40,6 +40,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 78a2450..d0959f8 100644 (file)
@@ -41,6 +41,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index f6bf4da..54f649f 100644 (file)
@@ -36,6 +36,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index ec58500..3b6585a 100644 (file)
@@ -37,6 +37,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 58a3eae..c92b6f7 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index c48976b..98fe2d5 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index fcc7361..fbcc1e4 100644 (file)
@@ -34,6 +34,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 25f7861..b9dbb7b 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_ECC=y
index c32c394..66d95e6 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_ECC=y
index e3c41c3..1d0c710 100644 (file)
@@ -34,6 +34,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_ECC=y
index 279976c..7cd2ae6 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 34ebc51..fdde26e 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index ea8b673..3e4ef80 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index e9bf7ff..94afb8b 100644 (file)
@@ -34,6 +34,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 20ded48..d4dc7bf 100644 (file)
@@ -61,6 +61,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
index 8a82082..ea1ff59 100644 (file)
@@ -60,6 +60,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
index 87d4083..4077ed9 100644 (file)
@@ -62,6 +62,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
index de34ba7..5bc0735 100644 (file)
@@ -45,6 +45,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
index a755d9c..76747d4 100644 (file)
@@ -52,9 +52,12 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_DM_I2C=y
index efb46b3..a8d1fbe 100644 (file)
@@ -51,9 +51,12 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_DM_I2C=y
index 1568c79..9734511 100644 (file)
@@ -53,9 +53,12 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_DM_I2C=y
index 3abd079..a73bbb0 100644 (file)
@@ -36,9 +36,12 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_DM_I2C=y
index 1b6ef8a..56ab58a 100644 (file)
@@ -55,6 +55,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 8ab1c5d..f87c52c 100644 (file)
@@ -54,6 +54,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index a84b7ad..ddf43f6 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
index 8fd0248..78d859a 100644 (file)
@@ -56,6 +56,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index f9dbc84..65aa560 100644 (file)
@@ -36,6 +36,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_REMOTE=y
 CONFIG_ENV_ADDR=0xFFE20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 424b3f2..e65b8d1 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 1c55d30..73bd84e 100644 (file)
@@ -59,6 +59,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index ea9c479..72d8417 100644 (file)
@@ -58,6 +58,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 5e08b82..ec0fd47 100644 (file)
@@ -60,6 +60,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 1c1fea6..344d8c3 100644 (file)
@@ -43,6 +43,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index ae924b1..cbab106 100644 (file)
@@ -60,6 +60,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index fef0893..68e7987 100644 (file)
@@ -59,6 +59,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index 0b7e715..a0a331b 100644 (file)
@@ -61,6 +61,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index c78b21d..9001131 100644 (file)
@@ -44,6 +44,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index ea6a528..ae8a57b 100644 (file)
@@ -50,6 +50,8 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index e17e8b1..57d4ea6 100644 (file)
@@ -35,6 +35,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
index e287e8e..e18bdea 100644 (file)
@@ -52,6 +52,8 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 # CONFIG_ENV_IS_IN_FAT is not set
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_SPL_DM=y
index ebcf14d..0a6295e 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 7b9e0a4..1ddee34 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 6e7da85..0e92e3a 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 5ec1e61..28e48b2 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 94c2834..7110e92 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index ed2b04b..22fd19e 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 29b3923..5508855 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 29b3923..5508855 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 4551cfd..4df2bfe 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index ae69c54..4eb24a8 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 21ed22a..99c4d67 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index f4d5dba..0eead52 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 72228b5..fd28775 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 293683c..60c8016 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 97057b5..cbfaef4 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index cb381e2..77d9ab6 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index cff3b1a..2e09c7d 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 350faaf..5ad7c4c 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index ef37695..763a5f4 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 21ad962..ea7b07d 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 695b4c5..c242c5c 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 998bacf..b84f924 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index 90a832a..b5964de 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index e704ee0..852d635 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index f00f3c8..923ed9a 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index 1b89828..b23c4b6 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index 124c58d..edb16c9 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index 4eecdf3..781a854 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index 28479b9..8b4a146 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 5072a9b..57484df 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index fa7f052..6c25da9 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 083f50e..1220a94 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADP=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4_WRITE=y
index 5dd323d..ff2e5e4 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_HSDK_CREG_GPIO=y
 CONFIG_MMC=y
index 698dbda..82bac62 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_HSDK_CREG_GPIO=y
 CONFIG_MMC=y
index 1f72c53..667240b 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -48,6 +49,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/bcm96753ref_ram_defconfig b/configs/bcm96753ref_ram_defconfig
new file mode 100644 (file)
index 0000000..2c44083
--- /dev/null
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_ARCH_BCM6753=y
+CONFIG_SYS_TEXT_BASE=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96753ref"
+CONFIG_ARMV7_LPAE=y
+CONFIG_TARGET_BCM96753REF=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_CIPHER=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
+# CONFIG_NET is not set
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
+CONFIG_BCM6345_GPIO=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_BCM6753=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_6753=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_REGEX=y
index 7b42b7a..f3d5e5d 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_CMD_NAND_LOCK_UNLOCK=y
 CONFIG_CMD_PART=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_MAY_FAIL=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index 1e117c9..82d54de 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_RENESAS_SDHI=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
index 6e96ed5..be3959a 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_MAY_FAIL=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index 551eda8..0561e62 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_MAY_FAIL=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index ad6cc44..10749f0 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_MAY_FAIL=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index ddcf8ee..cd53e21 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_MAY_FAIL=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_CACHE=y
index 343d75a..5d1a8af 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_MAY_FAIL=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index a30c1b8..ca29f9b 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_MAY_FAIL=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
index 7bfbcf6..38302dd 100644 (file)
@@ -25,6 +25,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -37,6 +38,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 0cd8f39..29bf9b9 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="tpm init; tpm startup TPM2_SU_CLEAR; read mmc 0:2 100000 0 80; setexpr loader *001004f0; setexpr size *00100518; setexpr blocks $size / 200; read mmc 0:2 100000 80 $blocks; setexpr setup $loader - 1000; setexpr cmdline_ptr $loader - 2000; setexpr.s cmdline *$cmdline_ptr; setexpr cmdline gsub %U \\\\${uuid}; if part uuid mmc 0:2 uuid; then zboot start 100000 0 0 0 $setup cmdline; zboot load; zboot setup; zboot dump; zboot go;fi"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_EVENT=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_BLOBLIST=y
 # CONFIG_TPL_BLOBLIST is not set
@@ -59,6 +60,7 @@ CONFIG_CMD_READ=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_BOOTSTAGE=y
@@ -77,6 +79,8 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent interrupts linux-name acpi,name acpi,path u-boot,acpi-dsdt-order u-boot,acpi-ssdt-order"
 CONFIG_ENV_OVERWRITE=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index a575437..b29c5cc 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -61,6 +62,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 4bb52b6..9186621 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -52,6 +53,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index fc1292b..93f1d40 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -54,6 +55,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 6839d8c..ef1d770 100644 (file)
@@ -71,6 +71,8 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 # CONFIG_NET is not set
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 748a0e7..363b5f3 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -46,6 +47,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 4fc3b0a..ce1c4e0 100644 (file)
@@ -15,6 +15,7 @@ CONFIG_CMD_IMLS=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
index 0116cfa..a955ba5 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_CMD_DM=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
index c1cf8cc..1c5efec 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -55,6 +56,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 5cad4d7..5aba0e2 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -51,6 +52,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index fa41c5e..657af57 100644 (file)
@@ -57,6 +57,8 @@ CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_SPI_MAX_HZ=50000000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="ccdc.img"
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SCSI_AHCI=y
 CONFIG_DM_PCA953X=y
index 933bea6..79b42a8 100644 (file)
@@ -26,6 +26,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -43,6 +44,8 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index dcf8ab3..5a0bf1f 100644 (file)
@@ -24,6 +24,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -38,6 +39,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index cbabdab..00ea238 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_WDT=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_SMC=y
index d448113..4688e0a 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_DOS_PARTITION=y
index 073807b..9226c78 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -41,6 +42,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index f7dc932..590fee9 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -45,6 +46,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 0c27677..bbd1401 100644 (file)
@@ -61,6 +61,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_DM=y
index 694e17c..d40f875 100644 (file)
@@ -47,6 +47,8 @@ CONFIG_CMD_DIAG=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x60100000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_DM=y
index aeb9c35..5d417a8 100644 (file)
@@ -58,6 +58,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_DM=y
index af17900..2210fab 100644 (file)
@@ -41,6 +41,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_JFFS2=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DMA_LPC32XX=y
 CONFIG_LPC32XX_GPIO=y
index 6f03714..a0e423d 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_LOCK_UNLOCK=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_BOOTP_NISDOMAIN=y
 CONFIG_BOOTP_NTPSERVER=y
 CONFIG_CMD_JFFS2=y
 CONFIG_JFFS2_DEV="nand0"
index 60077ed..0dfb7bb 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -49,6 +50,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index a6a0c66..ce90b7f 100644 (file)
@@ -25,6 +25,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 CONFIG_ENV_IS_IN_MMC=y
index 7a9771e..b780a32 100644 (file)
@@ -21,6 +21,7 @@ CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_PMIC=y
index f695429..d93104e 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_DATE=y
 CONFIG_ENV_ADDR=0xFF040000
index 0c00ead..f9a00b8 100644 (file)
@@ -17,6 +17,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_DATE=y
 CONFIG_ENV_ADDR=0xFF040000
index bb4c405..228643a 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_EFI_PARTITION=y
 CONFIG_OF_EMBED=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 # CONFIG_REGEX is not set
index 3a2e789..1ed2f13 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_EFI_PARTITION=y
 CONFIG_OF_EMBED=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 # CONFIG_REGEX is not set
index 04573fc..ceadd82 100644 (file)
@@ -23,6 +23,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -36,6 +37,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index df904c8..b5d1cf1 100644 (file)
@@ -23,6 +23,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -36,6 +37,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 75a3d93..28fce77 100644 (file)
@@ -22,6 +22,8 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="app.bin"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_NET is not set
 CONFIG_MMC=y
index 658fbfe..1bb0aa7 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_SAVES=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_RARP=y
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
index ea00185..53fe777 100644 (file)
@@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_EVB_AST2500=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
 CONFIG_PRE_CON_BUF_ADDR=0x1e720000
 CONFIG_SYS_LOAD_ADDR=0x83000000
@@ -18,9 +19,11 @@ CONFIG_PRE_CONSOLE_BUFFER=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_AUTO_COMPLETE is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_OVERWRITE=y
@@ -28,6 +31,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_CLK=y
+CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_ASPEED=y
 CONFIG_MMC_SDHCI=y
index 172b08e..f541c69 100644 (file)
@@ -11,6 +11,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x83000000
@@ -39,9 +40,11 @@ CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPL_OF_CONTROL=y
@@ -57,6 +60,7 @@ CONFIG_SPL_CLK=y
 CONFIG_DM_HASH=y
 CONFIG_HASH_ASPEED=y
 CONFIG_ASPEED_ACRY=y
+CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
 CONFIG_SPL_MISC=y
index 0a4c207..58c8bb9 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -40,6 +41,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
index 199afb4..03cad40 100644 (file)
@@ -152,6 +152,8 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xFE080000
 CONFIG_ENV_ADDR_REDUND=0xFE090000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_DM=y
 CONFIG_REGMAP=y
 CONFIG_AXI=y
index 05e9d18..26b97b2 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
 CONFIG_CMD_PING=y
index 9f1ce4e..3bf235d 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CACHE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
index 792cc1a..d78261f 100644 (file)
@@ -36,6 +36,8 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK_HSDK=y
 CONFIG_HSDK_CREG_GPIO=y
index c72ad9f..cd9f697 100644 (file)
@@ -35,6 +35,8 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK_HSDK=y
 CONFIG_HSDK_CREG_GPIO=y
index 246cc3d..64e2a4c 100644 (file)
@@ -142,6 +142,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
@@ -154,6 +155,8 @@ CONFIG_CMD_UBI=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xFFFC0000
 CONFIG_ENV_ADDR_REDUND=0xFFFE0000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="ids8313/uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_I2C=y
index 4273b4b..418bd06 100644 (file)
@@ -74,6 +74,8 @@ CONFIG_SPL_OF_PLATDATA=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
index 332ff3f..7c777a5 100644 (file)
@@ -60,6 +60,8 @@ CONFIG_SPL_OF_PLATDATA=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
index 420aae6..7b970b9 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="Integrator-AP # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
index 3ff47e1..05aa6dc 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="Integrator-AP # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
index 2160887..52973da 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="Integrator-AP # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
index b384dc6..336f1d3 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="Integrator-AP # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
index ba6450b..4cfe0bd 100644 (file)
@@ -23,6 +23,8 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_ENV_ADDR=0x24F00000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
index 06bfdff..ddff8ac 100644 (file)
@@ -23,6 +23,8 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_ENV_ADDR=0x24F00000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
index 3d15887..87e2a97 100644 (file)
@@ -23,6 +23,8 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_ENV_ADDR=0x24F00000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
index 8d49ef4..c1868fb 100644 (file)
@@ -23,6 +23,8 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_ENV_ADDR=0x24F00000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
index 431491e..14a30e3 100644 (file)
@@ -27,6 +27,8 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="app.bin"
 # CONFIG_NET is not set
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
index 60c96f8..d518195 100644 (file)
@@ -29,7 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
index 6479f9b..6850b99 100644 (file)
@@ -30,7 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
index f4b1abf..75f8a0b 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
index eba4f09..44a87ca 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
index 5d19c51..e4bd6df 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
index cf0748c..982cef6 100644 (file)
@@ -16,10 +16,10 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_EVENT=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_LAST_STAGE_INIT=y
-CONFIG_MISC_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
@@ -27,6 +27,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_SPI=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_ETHSW=y
 CONFIG_CMD_CRAMFS=y
@@ -47,6 +48,7 @@ CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
index 53f7abc..b4e2938 100644 (file)
@@ -178,6 +178,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index 9124504..61a6502 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
index 228bbe6..510ff45 100644 (file)
@@ -147,6 +147,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index d81c787..b8433b7 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
index d230638..9bdd7ae 100644 (file)
@@ -159,6 +159,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index b0b5926..0fd6ec7 100644 (file)
@@ -138,6 +138,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index d274c95..43db187 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
index 53aaf6c..42990da 100644 (file)
@@ -139,6 +139,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index b333769..fff5b1d 100644 (file)
@@ -158,6 +158,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index 87890cd..d616610 100644 (file)
@@ -36,6 +36,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_DIAG=y
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_NET is not set
 CONFIG_DM=y
index 7f0e0be..cb7ffb4 100644 (file)
@@ -7,9 +7,7 @@ CONFIG_DRAM_CLK=672
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_XMC=y
 CONFIG_SPI=y
-CONFIG_DM_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index 25bfe52..c3aa4b1 100644 (file)
@@ -7,10 +7,8 @@ CONFIG_DRAM_CLK=672
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_XMC=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SPI=y
-CONFIG_DM_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index 925d68d..1bc73db 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index c71c864..2a3348f 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index 58629be..c31047f 100644 (file)
@@ -87,6 +87,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index d252ed4..7ad5c16 100644 (file)
@@ -64,6 +64,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index fb9f457..3e8b34b 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index 1d6d88f..fdfcf9d 100644 (file)
@@ -67,6 +67,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index 38b1704..29045bf 100644 (file)
@@ -84,6 +84,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index 2f66d83..834a2d3 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
index c1adc6e..a31560a 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
index 150179d..427fa1b 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
index a8288e9..0139f03 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
index 695505a..aec9e5c 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
index ef1a591..ad59689 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index 8dd6ce4..d583573 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index 3e54803..8027b01 100644 (file)
@@ -85,6 +85,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_NAND_FSL_IFC=y
index 97fe2ce..5be7e4c 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index be40f49..dd36d81 100644 (file)
@@ -84,6 +84,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index e196c44..7fadadb 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index 6a89794..5510d50 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index e7c277d..c0ffae9 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index 94daa1f..173109e 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index a86138f..37687fc 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_NAND_FSL_IFC=y
index 19a54d1..a8dc348 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_NAND_FSL_IFC=y
index 61e3482..bd1c455 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index ef82842..0976b96 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index 6ff5614..4b0ef66 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index 551807e..ea5d004 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
index c15302c..bbeea5a 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index bc32611..f1f82d7 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index 52855d1..282cb43 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index ab780c1..9f158aa 100644 (file)
@@ -84,6 +84,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index b5b501c..f906202 100644 (file)
@@ -85,6 +85,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index 740838b..5d71bbe 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index 11de0d4..b817907 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS=2
index c713a44..5d8dd4b 100644 (file)
@@ -67,6 +67,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="boot/fitImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
index 5d9f783..0d09d91 100644 (file)
@@ -25,6 +25,7 @@ CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
index cc7697b..e9f7288 100644 (file)
@@ -24,6 +24,7 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
index 5409ca7..b59445e 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_SAVES=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_JFFS2=y
index c4d37db..c051e00 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -54,6 +55,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index fc1606a..062d922 100644 (file)
@@ -35,6 +35,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DM=y
 CONFIG_MXS_GPIO=y
index f51398c..d48ac4c 100644 (file)
@@ -36,6 +36,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_NET is not set
 CONFIG_DM=y
index 22310f5..0b0459e 100644 (file)
@@ -43,6 +43,8 @@ CONFIG_CMD_UBI=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_MXS_GPIO=y
 CONFIG_MMC_MXS=y
index b7502aa..4bd9982 100644 (file)
@@ -44,6 +44,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_NET is not set
 CONFIG_DM=y
index 090e5fa..7ffdb81 100644 (file)
@@ -44,6 +44,8 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_MXS_GPIO=y
 CONFIG_MMC_MXS=y
index 6cb21b9..1bac585 100644 (file)
@@ -40,6 +40,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),5
 CONFIG_CMD_UBI=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_MXS_GPIO=y
 CONFIG_MMC_MXS=y
index 664a9b2..db33d11 100644 (file)
@@ -52,6 +52,8 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="fitImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
index 3607583..71d6fe5 100644 (file)
@@ -17,6 +17,8 @@ CONFIG_SYS_PROMPT="nsim# "
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 # CONFIG_NET is not set
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_SHIFT=2
index 2d8a3e4..954ea42 100644 (file)
@@ -18,6 +18,8 @@ CONFIG_SYS_PROMPT="nsim# "
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 # CONFIG_NET is not set
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_SHIFT=2
index 51ce560..60b7a01 100644 (file)
@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_BLK=y
 CONFIG_HAVE_BLOCK_DEVICE=y
 CONFIG_DM_ETH=y
index 60e6094..bd1cdf3 100644 (file)
@@ -19,6 +19,8 @@ CONFIG_SYS_PROMPT="nsim# "
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 # CONFIG_NET is not set
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_SHIFT=2
index 9ba115c..7ce63ba 100644 (file)
@@ -11,5 +11,6 @@ CONFIG_MMC0_CD_PIN=""
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index d29c850..823e3e4 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
index 1ce892d..28c093e 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
index ddb9007..5eab817 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
index b8ebc28..6ad0359 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
index 206118e..c7111f4 100644 (file)
@@ -83,6 +83,13 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
 CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y
index ca1a581..cdba090 100644 (file)
@@ -54,6 +54,8 @@ CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="zImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
index 2eaddcf..777af8c 100644 (file)
@@ -11,9 +11,11 @@ CONFIG_SPL_SPI_SUNXI=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_SY8106A_VOUT1_VOLT=1100
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
index 745451c..4496aa4 100644 (file)
@@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=624
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index 8c2179b..3b78ad7 100644 (file)
@@ -7,7 +7,9 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_MACPWR="PD14"
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_REALTEK=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index 22563c8..54faf6a 100644 (file)
@@ -15,5 +15,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHY_REALTEK=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
index 332cd47..2dc69d2 100644 (file)
@@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=624
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index f92532f..648cb2c 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
 CONFIG_SILENT_CONSOLE=y
+CONFIG_EVENT=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
@@ -45,6 +46,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CRAMFS=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
@@ -66,6 +68,7 @@ CONFIG_SYS_I2C_LEGACY=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
index 1020b68..f489555 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
 CONFIG_SILENT_CONSOLE=y
+CONFIG_EVENT=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
@@ -43,6 +44,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CRAMFS=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
@@ -64,6 +66,7 @@ CONFIG_SYS_I2C_LEGACY=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
index 1a2ba8c..bca0163 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
 CONFIG_SILENT_CONSOLE=y
+CONFIG_EVENT=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
@@ -45,6 +46,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CRAMFS=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
@@ -66,6 +68,7 @@ CONFIG_SYS_I2C_LEGACY=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
index 3a51d4e..af1812b 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
 CONFIG_SILENT_CONSOLE=y
+CONFIG_EVENT=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
@@ -43,6 +44,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_CRAMFS=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
@@ -64,6 +66,7 @@ CONFIG_SYS_I2C_LEGACY=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
index 9d5aa3a..4efddc0 100644 (file)
@@ -24,6 +24,7 @@ CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_RARP=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
index 6209e68..45a9e77 100644 (file)
@@ -10,6 +10,8 @@ CONFIG_MMC0_CD_PIN=""
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index 1928509..1e730dd 100644 (file)
@@ -11,8 +11,10 @@ CONFIG_USB3_VBUS_PIN="PL5"
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_PSCI_RESET is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_PHY_SUN50I_USB3=y
+CONFIG_SPI=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
index 0c71d59..e779663 100644 (file)
@@ -12,8 +12,10 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_NETDEVICES is not set
 CONFIG_AXP209_POWER=y
 CONFIG_AXP_DCDC2_VOLT=1250
 CONFIG_AXP_DCDC3_VOLT=3300
 CONFIG_CONS_INDEX=3
+CONFIG_SPI=y
index e8a5b4d..f0767a4 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_SYS_PROMPT="u-boot-pm9263> "
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_JFFS2=y
index 7fbbbab..96bd30c 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig
new file mode 100644 (file)
index 0000000..e10eced
--- /dev/null
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_POMELO=y
+CONFIG_SYS_TEXT_BASE=0x180000
+CONFIG_SYS_MALLOC_LEN=0x101000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo"
+CONFIG_SYS_PCI_64BIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x90000000
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_SYS_PROMPT="pomelo#"
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCI_PHYTIUM=y
+CONFIG_PL01X_SERIAL=y
index d1f928d..3b3632f 100644 (file)
@@ -30,11 +30,14 @@ CONFIG_DOS_PARTITION=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SIMPLE_BUS_CORRECT_RANGE=y
 CONFIG_BLK=y
 CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CHIP_SELECTS_PER_CTRL=0
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
index 591b311..36214fc 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_QFW=y
@@ -51,6 +52,8 @@ CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 928fa68..6010b61 100644 (file)
@@ -26,6 +26,7 @@ CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_QFW=y
@@ -34,6 +35,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 606a7fd..62aa341 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
index febf8f2..791a26c 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
index 9470bee..0d8c9d5 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
index ea94d5c..de9cfd9 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_RENESAS_RPC_HF=y
index d4dc8ec..5fb27d2 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
index 3a5e433..ade9286 100644 (file)
@@ -70,6 +70,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
index 59fc4a9..25181d7 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
index 48b6a6a..a786f5a 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
index 4e46e46..bc30c4c 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
index afcd41a..c958f2a 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 149e480..279a5f3 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 3fb79be..8753790 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index d1dee02..ac2e916 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
index 700aef7..a44ba50 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
index 7761a57..49fe180 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 88bbbb4..78b65a9 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CMD_SDRAM=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_GETTIME=y
 CONFIG_CMD_TIMER=y
index 9f458e1..46f9bd3 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 6460ff3..cbef580 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 844a9cd..47672b5 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 0de0636..4f22d6b 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index a6e002e..e21b6a8 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 676385f..e4a2e45 100644 (file)
@@ -49,6 +49,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 1967352..3732b68 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
index a7cf6b2..2a26140 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
index 33ce03c..df62e0e 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
index 7660dbe..d89b6f3 100644 (file)
@@ -42,6 +42,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
index 97361a0..a06f524 100644 (file)
@@ -42,6 +42,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
index 7828bfd..8bb3706 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT4=y
index 5e2b79e..b4568cd 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
index bffcc49..03c2b20 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
index c664274..878f3a3 100644 (file)
@@ -42,6 +42,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index c6cb19e..1061762 100644 (file)
@@ -42,6 +42,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index 3a7da73..21e9fc3 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
index b0689fb..01b2a58 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index a853026..25e2b98 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index b36f4b5..484df6a 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
index 7c157a2..40d1422 100644 (file)
@@ -23,7 +23,6 @@ CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_F=y
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 CONFIG_CMD_BOOTZ=y
index 7ebeb89..41f73f8 100644 (file)
@@ -32,7 +32,6 @@ CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_F=y
 CONFIG_STACKPROTECTOR=y
 CONFIG_ANDROID_AB=y
 CONFIG_CMD_CPU=y
@@ -105,6 +104,7 @@ CONFIG_CMD_TPM_TEST=y
 CONFIG_CMD_BTRFS=y
 CONFIG_CMD_CBFS=y
 CONFIG_CMD_CRAMFS=y
+CONFIG_CMD_EROFS=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_MTDPARTS=y
index 217b064..7ccee70 100644 (file)
@@ -20,7 +20,6 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_F=y
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 CONFIG_CMD_BOOTZ=y
index 1687ccf..31f5aa8 100644 (file)
@@ -30,7 +30,6 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_F=y
 CONFIG_HANDOFF=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_ENV_SUPPORT=y
index 1597616..5988777 100644 (file)
@@ -15,11 +15,14 @@ CONFIG_LAST_STAGE_INIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 0e99c36..36593ec 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
index 4b3267e..bd8c17f 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
 CONFIG_CMD_PING=y
index 3674c8f..eb62cfd 100644 (file)
@@ -26,6 +26,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
 CONFIG_CMD_PING=y
index f85953f..6b15bc3 100644 (file)
@@ -47,6 +47,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_ALTERA_SDRAM=y
index 2e116fb..342a702 100644 (file)
@@ -41,6 +41,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="Image"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_ALTERA_SDRAM=y
index b62f509..486c88f 100644 (file)
@@ -48,6 +48,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_ALTERA_SDRAM=y
index 15652a1..24687f1 100644 (file)
@@ -46,6 +46,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="fitImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DFU_MMC=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
index 2124a08..01b7086 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_CMD_UBI=y
 # CONFIG_EFI_PARTITION is not set
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="zImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BOOTCOUNT_LIMIT=y
index d31c3f5..a6e3a77 100644 (file)
@@ -37,6 +37,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="fitImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DFU_MMC=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
index 31346fc..d458818 100644 (file)
@@ -47,6 +47,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
index 7e7d1cc..57ccf70 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="Image"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
index cf7bf23..91b05ca 100644 (file)
@@ -48,6 +48,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
index f7bdb90..e71b1e1 100644 (file)
@@ -54,6 +54,8 @@ CONFIG_CMD_UBI=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="zImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_SPL_BLK is not set
index 60e7750..386a773 100644 (file)
@@ -48,6 +48,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_ALTERA_SDRAM=y
index 8249a12..038e0b6 100644 (file)
@@ -45,6 +45,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="Image"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_ALTERA_SDRAM=y
index 4e2c0c1..15848af 100644 (file)
@@ -50,6 +50,8 @@ CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="fitImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
index bad08e7..e24be7a 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_SDRAM=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -45,6 +46,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xFFF40000
 CONFIG_ENV_ADDR_REDUND=0xFFF20000
 CONFIG_DM=y
+CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFE001001
 CONFIG_SYS_OR0_PRELIM=0xFE000030
index 9781b10..fb630bd 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -49,6 +50,8 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 0093076..982f7b0 100644 (file)
@@ -13,5 +13,6 @@ CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
index 90a4ec4..e99bb1e 100644 (file)
@@ -25,6 +25,8 @@ CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
index 6dbf8c2..cbc6208 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
index 94ed3fb..0adf050 100644 (file)
@@ -16,6 +16,8 @@ CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_SERIAL=y
index e1278f2..8a33160 100644 (file)
@@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910"
 CONFIG_PRE_CON_BUF_ADDR=0x7c000000
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_AHCI=y
+CONFIG_LTO=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
index 4a9bbef..25758b4 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
@@ -51,6 +52,8 @@ CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 66aab79..73241ae 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
@@ -50,6 +51,8 @@ CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 2f87c08..9dd2d4f 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
@@ -48,6 +49,8 @@ CONFIG_EFI_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
 CONFIG_TFTP_TSIZE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
index 64eb766..211acc7 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TIMESTAMP=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run distro_bootcmd"
-CONFIG_MISC_INIT_F=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_ELF is not set
index 6078b46..4ba18e9 100644 (file)
@@ -138,6 +138,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index cc9bbab..7dbc3cc 100644 (file)
@@ -160,6 +160,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_JFFS2=y
index 304d6a8..3c9fee3 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_CMD_UBI=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="zImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
index 87eb939..0bedfe1 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_CMD_UBI=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="zImage"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
index b9e2d9b..8269aab 100644 (file)
@@ -34,6 +34,8 @@ CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)"
 CONFIG_CMD_UBI=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="Image"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
index 5792d78..2dccfb1 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_PING=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"
 CONFIG_OF_CONTROL=y
index e02124c..aac4c4c 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 # CONFIG_CMD_SLEEP is not set
index 82a5b52..50715e2 100644 (file)
@@ -17,7 +17,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_BOOTDELAY=1
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9"
-CONFIG_BOOTCOMMAND="if smhload ${boot_name} ${boot_addr_r}; then   set bootargs;   abootimg addr ${boot_addr_r};   abootimg get dtb --index=0 fdt_addr_r;   bootm ${boot_addr_r} ${boot_addr_r}   ${fdt_addr_r}; else;   set fdt_high 0xffffffffffffffff;   set initrd_high 0xffffffffffffffff;   smhload ${kernel_name} ${kernel_addr};   smhload ${fdtfile} ${fdt_addr_r};   smhload ${ramdisk_name} ${ramdisk_addr_r}   ramdisk_end;   fdt addr ${fdt_addr_r}; fdt resize;   fdt chosen ${ramdisk_addr_r} ${ramdisk_end};   booti $kernel_addr - $fdt_addr_r; fi"
+CONFIG_BOOTCOMMAND="if smhload ${boot_name} ${boot_addr_r}; then   setenv bootargs;   abootimg addr ${boot_addr_r};   abootimg get dtb --index=0 fdt_addr_r;   bootm ${boot_addr_r} ${boot_addr_r}   ${fdt_addr_r}; else;   setenv fdt_high 0xffffffffffffffff;   setenv initrd_high 0xffffffffffffffff;   smhload ${kernel_name} ${kernel_addr_r};   smhload ${fdtfile} ${fdt_addr_r};   smhload ${ramdisk_name} ${ramdisk_addr_r}   ramdisk_end;   fdt addr ${fdt_addr_r}; fdt resize;   fdt chosen ${ramdisk_addr_r} ${ramdisk_end};   booti $kernel_addr_r - $fdt_addr_r; fi"
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_PROMPT="VExpress64# "
@@ -30,6 +30,7 @@ CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 # CONFIG_CMD_SLEEP is not set
index dfcaafb..10e93cf 100644 (file)
@@ -22,6 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_SLEEP is not set
 CONFIG_CMD_UBI=y
index 52d5506..9df9da4 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
index 8b21dc2..c702491 100644 (file)
@@ -45,6 +45,8 @@ CONFIG_CMD_DATE=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_LPC32XX_GPIO=y
 CONFIG_SYS_I2C_LEGACY=y
index adc30a7..6e7d0ac 100644 (file)
@@ -35,6 +35,8 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EFIDEBUG=y
index 9122b24..5e035d1 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_CMD_NAND_LOCK_UNLOCK=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EFIDEBUG=y
index 0fa03e7..2777332 100644 (file)
@@ -64,6 +64,8 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_WDT=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
index 1c8d57b..0e1a193 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_DIAG=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xF7FE0000
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DM=y
 # CONFIG_DM_WARN is not set
index 24a8899..a994422 100644 (file)
@@ -560,7 +560,7 @@ Write U-boot SPL and U-boot to their partitions.
 
 .. code-block:: none
 
-       dd if=u-boot-spl.bin of=/dev/mtdblock0 bs=4096 seek=5 conv=sync
+       dd if=spl/u-boot-spl.bin of=/dev/mtdblock0 bs=4096 seek=5 conv=sync
        dd if=u-boot.itb  of=/dev/mtdblock0 bs=4096 seek=261 conv=sync
 
 Power off the board.
index b883cf7..470a7aa 100644 (file)
@@ -25,11 +25,12 @@ Depending on the build targets further packages maybe needed
 
     sudo apt-get install bc bison build-essential coccinelle \
       device-tree-compiler dfu-util efitools flex gdisk graphviz imagemagick \
-      liblz4-tool libguestfs-tools libncurses-dev libpython3-dev libsdl2-dev \
-      libssl-dev lz4 lzma lzma-alone openssl pkg-config python3 \
-      python3-coverage python3-pkg-resources python3-pycryptodome \
-      python3-pyelftools python3-pytest python3-sphinxcontrib.apidoc \
-      python3-sphinx-rtd-theme python3-virtualenv swig
+      liblz4-tool libgnutls28-dev libguestfs-tools libncurses-dev \
+      libpython3-dev libsdl2-dev libssl-dev lz4 lzma lzma-alone openssl \
+      pkg-config python3 python3-coverage python3-pkg-resources \
+      python3-pycryptodome python3-pyelftools python3-pytest \
+      python3-sphinxcontrib.apidoc python3-sphinx-rtd-theme python3-virtualenv \
+      swig
 
 SUSE based
 ~~~~~~~~~~
diff --git a/doc/develop/event.rst b/doc/develop/event.rst
new file mode 100644 (file)
index 0000000..6e144cf
--- /dev/null
@@ -0,0 +1,66 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Events
+======
+
+U-Boot supports a way for various events to be handled by interested
+subsystems. This provide a generic way to handle 'hooks' like setting up the
+CPUs after driver model is active, or reading a partition table after a new
+block device is probed.
+
+Rather than using weak functions and direct calls across subsystemss, it is
+often easier to use an event.
+
+An event consists of a type (e.g. EVT_DM_POST_INIT) and some optional data,
+in `union event_data`. An event spy can be creasted to watch for events of a
+particular type. When the event is created, it is sent to each spy in turn.
+
+
+Declaring a spy
+---------------
+
+To declare a spy, use something like this::
+
+    static int snow_setup_cpus(void *ctx, struct event *event)
+    {
+        /* do something */
+        return 0;
+    }
+    EVENT_SPY(EVT_DM_POST_INIT, snow_setup_cpus);
+
+Your function is called when EVT_DM_POST_INIT is emitted, i.e. after driver
+model is inited (in SPL, or in U-Boot proper before and after relocation).
+
+
+Debugging
+---------
+
+To assist with debugging events, enable `CONFIG_EVENT_DEBUG` and
+`CONFIG_CMD_EVENT`. The :doc:`../usage/event` command can then be used to
+provide a spy list.
+
+It is also possible to list spy information from the U-Boot executable,, using
+the `event_dump.py` script::
+
+    $ scripts/event_dump.py /tmp/b/sandbox/u-boot
+    Event type            Id                              Source location
+    --------------------  ------------------------------  ------------------------------
+    EVT_MISC_INIT_F       f:sandbox_misc_init_f           arch/sandbox/cpu/start.c:125
+
+This shows each event spy in U-Boot, along with the event type, function name
+(or ID) and source location.
+
+Note that if `CONFIG_EVENT_DEBUG` is not enabled, the event ID is missing, so
+the function is shown instead (with an `f:` prefix as above). Since the ID is
+generally the same as the function name, this does not matter much.
+
+The event type is decoded by the symbol used by U-Boot for the event linker
+list. Symbols have the form::
+
+    _u_boot_list_2_evspy_info_2_EVT_MISC_INIT_F
+
+so the event type can be read from the end. To manually list spy information
+in an image, use $(CROSS_COMPILE)nm::
+
+    nm u-boot |grep evspy |grep list
+    00000000002d6300 D _u_boot_list_2_evspy_info_2_EVT_MISC_INIT_F
index 93ebfa4..2e6d6c3 100644 (file)
@@ -17,6 +17,7 @@ Implementation
    distro
    driver-model/index
    environment
+   event
    global_data
    logging
    makefiles
index 3f99f1d..1e209ff 100644 (file)
@@ -77,4 +77,15 @@ If the pylint version is updated in CI, this may result in needing to regenerate
 `scripts/pylint.base`.
 
 
+Checking for errors
+-------------------
+
+If you only want to check for pylint errors, use::
+
+   PYTHONPATH=/path/to/scripts/dtc/pylibfdt/ make pylint_err
+
+This will show only pylint errors. Note that you must set PYTHONPATH to point
+to the pylibfdt directory build by U-Boot (typically the sandbox_spl board). If
+you have used `make qcheck` then it sill be in `board-sandbox_spl`.
+
 .. _`PEP 8`: https://www.python.org/dev/peps/pep-0008/
index 92572ea..0a7886d 100644 (file)
@@ -1,234 +1,2 @@
-System Control and Management Interface (SCMI) Message Protocol
-----------------------------------------------------------
-
-The SCMI is intended to allow agents such as OSPM to manage various functions
-that are provided by the hardware platform it is running on, including power
-and performance functions.
-
-This binding is intended to define the interface the firmware implementing
-the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
-and Management Interface Platform Design Document")[0] provide for OSPM in
-the device tree.
-
-Required properties:
-
-The scmi node with the following properties shall be under the /firmware/ node.
-
-- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports,
-         or "linaro,scmi-optee" for OP-TEE transport.
-- mboxes: List of phandle and mailbox channel specifiers. It should contain
-         exactly one or two mailboxes, one for transmitting messages("tx")
-         and another optional for receiving the notifications("rx") if
-         supported.
-- shmem : List of phandle pointing to the shared memory(SHM) area as per
-         generic mailbox client binding.
-- #address-cells : should be '1' if the device has sub-nodes, maps to
-         protocol identifier for a given sub-node.
-- #size-cells : should be '0' as 'reg' property doesn't have any size
-         associated with it.
-- arm,smc-id : SMC id required when using smc or hvc transports
-- linaro,optee-channel-id : Channel specifier required when using OP-TEE
-         transport.
-
-Optional properties:
-
-- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
-
-See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
-about the generic mailbox controller and client driver bindings.
-Mailbox doorbell is used as a mechanism to alert the presence of a
-messages and/or notification.
-
-Each protocol supported shall have a sub-node with corresponding compatible
-as described in the following sections. If the platform supports dedicated
-communication channel for a particular protocol, properties shall be present
-in the sub-node corresponding to that protocol. These properties are:
-- mboxes, mbox-names and shmem for mailbox transport
-- arm,smc-id and shmem for smc/hvc transport
-- linaro,optee-channel-id and possibly shmem for OP-TEE transport
-
-Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding uses the common clock binding[1].
-
-Required properties:
-- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
-
-Power domain bindings for the power domains based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding for the SCMI power domain providers uses the generic power
-domain binding[2].
-
-Required properties:
- - #power-domain-cells : Should be 1. Contains the device or the power
-                        domain ID value used by SCMI commands.
-
-Regulator bindings for the SCMI Regulator based on SCMI Message Protocol
-------------------------------------------------------------
-An SCMI Regulator is permanently bound to a well defined SCMI Voltage Domain,
-and should be always positioned as a root regulator.
-It does not support any current operation.
-
-SCMI Regulators are grouped under a 'regulators' node which in turn is a child
-of the SCMI Voltage protocol node inside the desired SCMI instance node.
-
-This binding uses the common regulator binding[6].
-
-Required properties:
- - reg : shall identify an existent SCMI Voltage Domain.
-
-Sensor bindings for the sensors based on SCMI Message Protocol
---------------------------------------------------------------
-SCMI provides an API to access the various sensors on the SoC.
-
-Required properties:
-- #thermal-sensor-cells: should be set to 1. This property follows the
-                        thermal device tree bindings[3].
-
-                        Valid cell values are raw identifiers (Sensor ID)
-                        as used by the firmware. Refer to  platform details
-                        for your implementation for the IDs to use.
-
-Reset signal bindings for the reset domains based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding for the SCMI reset domain providers uses the generic reset
-signal binding[5].
-
-Required properties:
- - #reset-cells : Should be 1. Contains the reset domain ID value used
-                 by SCMI commands.
-
-SRAM and Shared Memory for SCMI
--------------------------------
-
-A small area of SRAM is reserved for SCMI communication between application
-processors and SCP.
-
-The properties should follow the generic mmio-sram description found in [4]
-
-Each sub-node represents the reserved area for SCMI.
-
-Required sub-node properties:
-- reg : The base offset and size of the reserved area with the SRAM
-- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
-              shared memory
-
-[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/power/power-domain.yaml
-[3] Documentation/devicetree/bindings/thermal/thermal.txt
-[4] Documentation/devicetree/bindings/sram/sram.yaml
-[5] Documentation/devicetree/bindings/reset/reset.txt
-[6] Documentation/devicetree/bindings/regulator/regulator.yaml
-
-Example:
-
-sram@50000000 {
-       compatible = "mmio-sram";
-       reg = <0x0 0x50000000 0x0 0x10000>;
-
-       #address-cells = <1>;
-       #size-cells = <1>;
-       ranges = <0 0x0 0x50000000 0x10000>;
-
-       cpu_scp_lpri: scp-shmem@0 {
-               compatible = "arm,scmi-shmem";
-               reg = <0x0 0x200>;
-       };
-
-       cpu_scp_hpri: scp-shmem@200 {
-               compatible = "arm,scmi-shmem";
-               reg = <0x200 0x200>;
-       };
-};
-
-mailbox@40000000 {
-       ....
-       #mbox-cells = <1>;
-       reg = <0x0 0x40000000 0x0 0x10000>;
-};
-
-firmware {
-
-       ...
-
-       scmi {
-               compatible = "arm,scmi";
-               mboxes = <&mailbox 0 &mailbox 1>;
-               mbox-names = "tx", "rx";
-               shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               scmi_devpd: protocol@11 {
-                       reg = <0x11>;
-                       #power-domain-cells = <1>;
-               };
-
-               scmi_dvfs: protocol@13 {
-                       reg = <0x13>;
-                       #clock-cells = <1>;
-               };
-
-               scmi_clk: protocol@14 {
-                       reg = <0x14>;
-                       #clock-cells = <1>;
-               };
-
-               scmi_sensors0: protocol@15 {
-                       reg = <0x15>;
-                       #thermal-sensor-cells = <1>;
-               };
-
-               scmi_reset: protocol@16 {
-                       reg = <0x16>;
-                       #reset-cells = <1>;
-               };
-
-               scmi_voltage: protocol@17 {
-                       reg = <0x17>;
-
-                       regulators {
-                               regulator_devX: regulator@0 {
-                                       reg = <0x0>;
-                                       regulator-max-microvolt = <3300000>;
-                               };
-
-                               regulator_devY: regulator@9 {
-                                       reg = <0x9>;
-                                       regulator-min-microvolt = <500000>;
-                                       regulator-max-microvolt = <4200000>;
-                               };
-
-                               ...
-                       };
-               };
-       };
-};
-
-cpu@0 {
-       ...
-       reg = <0 0>;
-       clocks = <&scmi_dvfs 0>;
-};
-
-hdlcd@7ff60000 {
-       ...
-       reg = <0 0x7ff60000 0 0x1000>;
-       clocks = <&scmi_clk 4>;
-       power-domains = <&scmi_devpd 1>;
-       resets = <&scmi_reset 10>;
-};
-
-thermal-zones {
-       soc_thermal {
-               polling-delay-passive = <100>;
-               polling-delay = <1000>;
-                                       /* sensor ID */
-               thermal-sensors = <&scmi_sensors0 3>;
-               ...
-       };
-};
+See Binding in Linux documentation:
+Documentation/devicetree/bindings/firmware/arm,scmi.yaml
diff --git a/doc/usage/event.rst b/doc/usage/event.rst
new file mode 100644 (file)
index 0000000..c0f8acd
--- /dev/null
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+event command
+=============
+
+Synopsis
+--------
+
+::
+
+    event list
+
+Description
+-----------
+
+The event command provides spy list.
+
+This shows the following information:
+
+Seq
+    Sequence number of the spy, numbered from 0
+
+Type
+    Type of the spy, both as a number and a label. If `CONFIG_EVENT_DEBUG` is
+    not enabled, the label just shows `(unknown)`.
+
+Function
+    Address of the function to call
+
+ID
+    ID string for this event, if `CONFIG_EVENT_DEBUG` is enabled. Otherwise this
+    just shows `?`.
+
+
+See :doc:`../develop/event` for more information on events.
+
+Example
+-------
+
+::
+
+    => event list
+    Seq  Type                              Function  ID
+      0  7   misc_init_f               55a070517c68  ?
+
+Configuration
+-------------
+
+The event command is only available if CONFIG_CMD_EVENT=y.
index 0aacf53..7501028 100644 (file)
@@ -29,6 +29,7 @@ Shell commands
    x86/cbsysinfo
    conitrace
    echo
+   event
    exception
    extension
    exit
index 9a0a6f6..5702268 100644 (file)
 #include <scmi_agent.h>
 #include <scmi_protocols.h>
 #include <asm/types.h>
+#include <linux/clk-provider.h>
+
+static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
+{
+       struct scmi_clk_protocol_attr_out out;
+       struct scmi_msg msg = {
+               .protocol_id = SCMI_PROTOCOL_ID_CLOCK,
+               .message_id = SCMI_PROTOCOL_ATTRIBUTES,
+               .out_msg = (u8 *)&out,
+               .out_msg_sz = sizeof(out),
+       };
+       int ret;
+
+       ret = devm_scmi_process_msg(dev, &msg);
+       if (ret)
+               return ret;
+
+       *num_clocks = out.attributes & SCMI_CLK_PROTO_ATTR_COUNT_MASK;
+
+       return 0;
+}
+
+static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
+{
+       struct scmi_clk_attribute_in in = {
+               .clock_id = clkid,
+       };
+       struct scmi_clk_attribute_out out;
+       struct scmi_msg msg = {
+               .protocol_id = SCMI_PROTOCOL_ID_CLOCK,
+               .message_id = SCMI_CLOCK_ATTRIBUTES,
+               .in_msg = (u8 *)&in,
+               .in_msg_sz = sizeof(in),
+               .out_msg = (u8 *)&out,
+               .out_msg_sz = sizeof(out),
+       };
+       int ret;
+
+       ret = devm_scmi_process_msg(dev, &msg);
+       if (ret)
+               return ret;
+
+       *name = out.clock_name;
+
+       return 0;
+}
 
 static int scmi_clk_gate(struct clk *clk, int enable)
 {
@@ -24,7 +70,7 @@ static int scmi_clk_gate(struct clk *clk, int enable)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(clk->dev->parent, &msg);
+       ret = devm_scmi_process_msg(clk->dev, &msg);
        if (ret)
                return ret;
 
@@ -52,7 +98,7 @@ static ulong scmi_clk_get_rate(struct clk *clk)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(clk->dev->parent, &msg);
+       ret = devm_scmi_process_msg(clk->dev, &msg);
        if (ret < 0)
                return ret;
 
@@ -77,7 +123,7 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(clk->dev->parent, &msg);
+       ret = devm_scmi_process_msg(clk->dev, &msg);
        if (ret < 0)
                return ret;
 
@@ -88,6 +134,49 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
        return scmi_clk_get_rate(clk);
 }
 
+static int scmi_clk_probe(struct udevice *dev)
+{
+       struct clk *clk;
+       size_t num_clocks, i;
+       int ret;
+
+       if (!CONFIG_IS_ENABLED(CLK_CCF))
+               return 0;
+
+       /* register CCF children: CLK UCLASS, no probed again */
+       if (device_get_uclass_id(dev->parent) == UCLASS_CLK)
+               return 0;
+
+       ret = scmi_clk_get_num_clock(dev, &num_clocks);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < num_clocks; i++) {
+               char *name;
+
+               if (!scmi_clk_get_attibute(dev, i, &name)) {
+                       char *clock_name = strdup(name);
+
+                       clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+                       if (!clk || !clock_name)
+                               ret = -ENOMEM;
+                       else
+                               ret = clk_register(clk, dev->driver->name,
+                                                  clock_name, dev->name);
+
+                       if (ret) {
+                               free(clk);
+                               free(clock_name);
+                               return ret;
+                       }
+
+                       clk_dm(i, clk);
+               }
+       }
+
+       return 0;
+}
+
 static const struct clk_ops scmi_clk_ops = {
        .enable = scmi_clk_enable,
        .disable = scmi_clk_disable,
@@ -99,4 +188,5 @@ U_BOOT_DRIVER(scmi_clock) = {
        .name = "scmi_clk",
        .id = UCLASS_CLK,
        .ops = &scmi_clk_ops,
+       .probe = &scmi_clk_probe,
 };
index 8f7703c..5c34004 100644 (file)
@@ -77,6 +77,16 @@ config DM_DEVICE_REMOVE
          it causes unplugged devices to linger around in the dm-tree, and it
          causes USB host controllers to not be stopped when booting the OS.
 
+config DM_EVENT
+       bool "Support events with driver model"
+       depends on DM
+       imply EVENT
+       default y if SANDBOX
+       help
+         This enables support for generating events related to driver model
+         operations, such as prbing or removing a device. Subsystems can
+         register a 'spy' function that is called when the event occurs.
+
 config SPL_DM_DEVICE_REMOVE
        bool "Support device removal in SPL"
        depends on SPL_DM
index e6ec6ff..73d2e9e 100644 (file)
@@ -207,6 +207,10 @@ int device_remove(struct udevice *dev, uint flags)
        if (!(dev_get_flags(dev) & DM_FLAG_ACTIVATED))
                return 0;
 
+       ret = device_notify(dev, EVT_DM_PRE_REMOVE);
+       if (ret)
+               return ret;
+
        /*
         * If the child returns EKEYREJECTED, continue. It just means that it
         * didn't match the flags.
@@ -256,6 +260,10 @@ int device_remove(struct udevice *dev, uint flags)
 
        dev_bic_flags(dev, DM_FLAG_ACTIVATED);
 
+       ret = device_notify(dev, EVT_DM_POST_REMOVE);
+       if (ret)
+               goto err_remove;
+
        return 0;
 
 err_remove:
index 901c1e2..1b356f1 100644 (file)
@@ -10,6 +10,7 @@
 
 #include <common.h>
 #include <cpu_func.h>
+#include <event.h>
 #include <log.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
@@ -493,6 +494,10 @@ int device_probe(struct udevice *dev)
        if (dev_get_flags(dev) & DM_FLAG_ACTIVATED)
                return 0;
 
+       ret = device_notify(dev, EVT_DM_PRE_PROBE);
+       if (ret)
+               return ret;
+
        drv = dev->driver;
        assert(drv);
 
@@ -597,6 +602,10 @@ int device_probe(struct udevice *dev)
                                  dev->name, ret, errno_str(ret));
        }
 
+       ret = device_notify(dev, EVT_DM_POST_PROBE);
+       if (ret)
+               return ret;
+
        return 0;
 fail_uclass:
        if (device_remove(dev, DM_REMOVE_NORMAL)) {
index e3f8795..8efb425 100644 (file)
@@ -404,6 +404,11 @@ int dm_init_and_scan(bool pre_reloc_only)
                        return ret;
                }
        }
+       if (CONFIG_IS_ENABLED(DM_EVENT)) {
+               ret = event_notify_null(EVT_DM_POST_INIT);
+               if (ret)
+                       return log_msg_ret("ev", ret);
+       }
 
        return 0;
 }
index b0e6df8..2771670 100644 (file)
@@ -49,6 +49,10 @@ config SYS_NUM_DDR_CTLRS
                        ARCH_LX2162A
        default 1
 
+config CHIP_SELECTS_PER_CTRL
+       int "Number of chip selects per controller"
+       default 4
+
 config SYS_FSL_DDR_VER
        int
        default 50 if SYS_FSL_DDR_VER_50
index 4b96820..c555164 100644 (file)
  * The sandbox SCMI agent driver simulates to some extend a SCMI message
  * processing. It simulates few of the SCMI services for some of the
  * SCMI protocols embedded in U-Boot. Currently:
- * - SCMI clock protocol: emulate 2 agents each exposing few clocks
- * - SCMI reset protocol: emulate 1 agent exposing a reset controller
- * - SCMI voltage domain protocol: emulate 1 agent exposing 2 regulators
+ * - SCMI clock protocol emulates an agent exposing 2 clocks
+ * - SCMI reset protocol emulates an agent exposing a reset controller
+ * - SCMI voltage domain protocol emulates an agent exposing 2 regulators
  *
- * Agent #0 simulates 2 clocks, 1 reset domain and 1 voltage domain.
- * See IDs in scmi0_clk[]/scmi0_reset[] and "sandbox-scmi-agent@0" in test.dts.
- *
- * Agent #1 simulates 1 clock.
- * See IDs in scmi1_clk[] and "sandbox-scmi-agent@1" in test.dts.
+ * As per DT bindings, the device node name shall be scmi.
  *
  * All clocks and regulators are default disabled and reset controller down.
  *
- * This Driver exports sandbox_scmi_service_ctx() for the test sequence to
+ * This driver exports sandbox_scmi_service_ctx() for the test sequence to
  * get the state of the simulated services (clock state, rate, ...) and
  * check back-end device state reflects the request send through the
  * various uclass devices, as clocks and reset controllers.
  */
 
-#define SANDBOX_SCMI_AGENT_COUNT       2
-
-static struct sandbox_scmi_clk scmi0_clk[] = {
-       { .id = 7, .rate = 1000 },
-       { .id = 3, .rate = 333 },
+static struct sandbox_scmi_clk scmi_clk[] = {
+       { .rate = 333 },
+       { .rate = 200 },
+       { .rate = 1000 },
 };
 
-static struct sandbox_scmi_reset scmi0_reset[] = {
+static struct sandbox_scmi_reset scmi_reset[] = {
        { .id = 3 },
 };
 
-static struct sandbox_scmi_voltd scmi0_voltd[] = {
+static struct sandbox_scmi_voltd scmi_voltd[] = {
        { .id = 0, .voltage_uv = 3300000 },
        { .id = 1, .voltage_uv = 1800000 },
 };
 
-static struct sandbox_scmi_clk scmi1_clk[] = {
-       { .id = 1, .rate = 44 },
-};
-
-/* The list saves to simulted end devices references for test purpose */
-struct sandbox_scmi_agent *sandbox_scmi_agent_list[SANDBOX_SCMI_AGENT_COUNT];
-
-static struct sandbox_scmi_service sandbox_scmi_service_state = {
-       .agent = sandbox_scmi_agent_list,
-       .agent_count = SANDBOX_SCMI_AGENT_COUNT,
-};
+static struct sandbox_scmi_service sandbox_scmi_service_state;
 
 struct sandbox_scmi_service *sandbox_scmi_service_ctx(void)
 {
@@ -74,9 +59,8 @@ static void debug_print_agent_state(struct udevice *dev, char *str)
 {
        struct sandbox_scmi_agent *agent = dev_get_priv(dev);
 
-       dev_dbg(dev, "Dump sandbox_scmi_agent %u: %s\n", agent->idx, str);
-       dev_dbg(dev, " scmi%u_clk   (%zu): %d/%ld, %d/%ld, %d/%ld, ...\n",
-               agent->idx,
+       dev_dbg(dev, "Dump sandbox_scmi_agent: %s\n", str);
+       dev_dbg(dev, " scmi_clk   (%zu): %d/%ld, %d/%ld, %d/%ld, ...\n",
                agent->clk_count,
                agent->clk_count ? agent->clk[0].enabled : -1,
                agent->clk_count ? agent->clk[0].rate : -1,
@@ -84,13 +68,11 @@ static void debug_print_agent_state(struct udevice *dev, char *str)
                agent->clk_count > 1 ? agent->clk[1].rate : -1,
                agent->clk_count > 2 ? agent->clk[2].enabled : -1,
                agent->clk_count > 2 ? agent->clk[2].rate : -1);
-       dev_dbg(dev, " scmi%u_reset (%zu): %d, %d, ...\n",
-               agent->idx,
+       dev_dbg(dev, " scmi_reset (%zu): %d, %d, ...\n",
                agent->reset_count,
                agent->reset_count ? agent->reset[0].asserted : -1,
                agent->reset_count > 1 ? agent->reset[1].asserted : -1);
-       dev_dbg(dev, " scmi%u_voltd (%zu): %u/%d, %u/%d, ...\n",
-               agent->idx,
+       dev_dbg(dev, " scmi_voltd (%zu): %u/%d, %u/%d, ...\n",
                agent->voltd_count,
                agent->voltd_count ? agent->voltd[0].enabled : -1,
                agent->voltd_count ? agent->voltd[0].voltage_uv : -1,
@@ -98,56 +80,32 @@ static void debug_print_agent_state(struct udevice *dev, char *str)
                agent->voltd_count ? agent->voltd[1].voltage_uv : -1);
 };
 
-static struct sandbox_scmi_clk *get_scmi_clk_state(uint agent_id, uint clock_id)
+static struct sandbox_scmi_clk *get_scmi_clk_state(uint clock_id)
 {
-       struct sandbox_scmi_clk *target = NULL;
-       size_t target_count = 0;
-       size_t n;
-
-       switch (agent_id) {
-       case 0:
-               target = scmi0_clk;
-               target_count = ARRAY_SIZE(scmi0_clk);
-               break;
-       case 1:
-               target = scmi1_clk;
-               target_count = ARRAY_SIZE(scmi1_clk);
-               break;
-       default:
-               return NULL;
-       }
-
-       for (n = 0; n < target_count; n++)
-               if (target[n].id == clock_id)
-                       return target + n;
+       if (clock_id < ARRAY_SIZE(scmi_clk))
+               return scmi_clk + clock_id;
 
        return NULL;
 }
 
-static struct sandbox_scmi_reset *get_scmi_reset_state(uint agent_id,
-                                                      uint reset_id)
+static struct sandbox_scmi_reset *get_scmi_reset_state(uint reset_id)
 {
        size_t n;
 
-       if (agent_id == 0) {
-               for (n = 0; n < ARRAY_SIZE(scmi0_reset); n++)
-                       if (scmi0_reset[n].id == reset_id)
-                               return scmi0_reset + n;
-       }
+       for (n = 0; n < ARRAY_SIZE(scmi_reset); n++)
+               if (scmi_reset[n].id == reset_id)
+                       return scmi_reset + n;
 
        return NULL;
 }
 
-static struct sandbox_scmi_voltd *get_scmi_voltd_state(uint agent_id,
-                                                      uint domain_id)
+static struct sandbox_scmi_voltd *get_scmi_voltd_state(uint domain_id)
 {
        size_t n;
 
-       if (agent_id == 0) {
-               for (n = 0; n < ARRAY_SIZE(scmi0_voltd); n++)
-                       if (scmi0_voltd[n].id == domain_id)
-                               return scmi0_voltd + n;
-       }
+       for (n = 0; n < ARRAY_SIZE(scmi_voltd); n++)
+               if (scmi_voltd[n].id == domain_id)
+                       return scmi_voltd + n;
 
        return NULL;
 }
@@ -156,10 +114,58 @@ static struct sandbox_scmi_voltd *get_scmi_voltd_state(uint agent_id,
  * Sandbox SCMI agent ops
  */
 
+static int sandbox_scmi_clock_protocol_attribs(struct udevice *dev,
+                                              struct scmi_msg *msg)
+{
+       struct scmi_clk_protocol_attr_out *out = NULL;
+
+       if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+               return -EINVAL;
+
+       out = (struct scmi_clk_protocol_attr_out *)msg->out_msg;
+       out->attributes = ARRAY_SIZE(scmi_clk);
+       out->status = SCMI_SUCCESS;
+
+       return 0;
+}
+
+static int sandbox_scmi_clock_attribs(struct udevice *dev, struct scmi_msg *msg)
+{
+       struct scmi_clk_attribute_in *in = NULL;
+       struct scmi_clk_attribute_out *out = NULL;
+       struct sandbox_scmi_clk *clk_state = NULL;
+       int ret;
+
+       if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+           !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+               return -EINVAL;
+
+       in = (struct scmi_clk_attribute_in *)msg->in_msg;
+       out = (struct scmi_clk_attribute_out *)msg->out_msg;
+
+       clk_state = get_scmi_clk_state(in->clock_id);
+       if (!clk_state) {
+               dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
+
+               out->status = SCMI_NOT_FOUND;
+       } else {
+               memset(out, 0, sizeof(*out));
+
+               if (clk_state->enabled)
+                       out->attributes = 1;
+
+               ret = snprintf(out->clock_name, sizeof(out->clock_name),
+                              "clk%u", in->clock_id);
+               assert(ret > 0 && ret < sizeof(out->clock_name));
+
+               out->status = SCMI_SUCCESS;
+       }
+
+       return 0;
+}
 static int sandbox_scmi_clock_rate_set(struct udevice *dev,
                                       struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_clk_rate_set_in *in = NULL;
        struct scmi_clk_rate_set_out *out = NULL;
        struct sandbox_scmi_clk *clk_state = NULL;
@@ -171,7 +177,7 @@ static int sandbox_scmi_clock_rate_set(struct udevice *dev,
        in = (struct scmi_clk_rate_set_in *)msg->in_msg;
        out = (struct scmi_clk_rate_set_out *)msg->out_msg;
 
-       clk_state = get_scmi_clk_state(agent->idx, in->clock_id);
+       clk_state = get_scmi_clk_state(in->clock_id);
        if (!clk_state) {
                dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
 
@@ -190,7 +196,6 @@ static int sandbox_scmi_clock_rate_set(struct udevice *dev,
 static int sandbox_scmi_clock_rate_get(struct udevice *dev,
                                       struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_clk_rate_get_in *in = NULL;
        struct scmi_clk_rate_get_out *out = NULL;
        struct sandbox_scmi_clk *clk_state = NULL;
@@ -202,7 +207,7 @@ static int sandbox_scmi_clock_rate_get(struct udevice *dev,
        in = (struct scmi_clk_rate_get_in *)msg->in_msg;
        out = (struct scmi_clk_rate_get_out *)msg->out_msg;
 
-       clk_state = get_scmi_clk_state(agent->idx, in->clock_id);
+       clk_state = get_scmi_clk_state(in->clock_id);
        if (!clk_state) {
                dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
 
@@ -219,7 +224,6 @@ static int sandbox_scmi_clock_rate_get(struct udevice *dev,
 
 static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_clk_state_in *in = NULL;
        struct scmi_clk_state_out *out = NULL;
        struct sandbox_scmi_clk *clk_state = NULL;
@@ -231,7 +235,7 @@ static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg)
        in = (struct scmi_clk_state_in *)msg->in_msg;
        out = (struct scmi_clk_state_out *)msg->out_msg;
 
-       clk_state = get_scmi_clk_state(agent->idx, in->clock_id);
+       clk_state = get_scmi_clk_state(in->clock_id);
        if (!clk_state) {
                dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
 
@@ -249,7 +253,6 @@ static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg)
 
 static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_rd_attr_in *in = NULL;
        struct scmi_rd_attr_out *out = NULL;
        struct sandbox_scmi_reset *reset_state = NULL;
@@ -261,7 +264,7 @@ static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg)
        in = (struct scmi_rd_attr_in *)msg->in_msg;
        out = (struct scmi_rd_attr_out *)msg->out_msg;
 
-       reset_state = get_scmi_reset_state(agent->idx, in->domain_id);
+       reset_state = get_scmi_reset_state(in->domain_id);
        if (!reset_state) {
                dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id);
 
@@ -278,7 +281,6 @@ static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg)
 
 static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_rd_reset_in *in = NULL;
        struct scmi_rd_reset_out *out = NULL;
        struct sandbox_scmi_reset *reset_state = NULL;
@@ -290,7 +292,7 @@ static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg)
        in = (struct scmi_rd_reset_in *)msg->in_msg;
        out = (struct scmi_rd_reset_out *)msg->out_msg;
 
-       reset_state = get_scmi_reset_state(agent->idx, in->domain_id);
+       reset_state = get_scmi_reset_state(in->domain_id);
        if (!reset_state) {
                dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id);
 
@@ -321,7 +323,6 @@ static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg)
 
 static int sandbox_scmi_voltd_attribs(struct udevice *dev, struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_voltd_attr_in *in = NULL;
        struct scmi_voltd_attr_out *out = NULL;
        struct sandbox_scmi_voltd *voltd_state = NULL;
@@ -333,7 +334,7 @@ static int sandbox_scmi_voltd_attribs(struct udevice *dev, struct scmi_msg *msg)
        in = (struct scmi_voltd_attr_in *)msg->in_msg;
        out = (struct scmi_voltd_attr_out *)msg->out_msg;
 
-       voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id);
+       voltd_state = get_scmi_voltd_state(in->domain_id);
        if (!voltd_state) {
                dev_err(dev, "Unexpected domain ID %u\n", in->domain_id);
 
@@ -351,7 +352,6 @@ static int sandbox_scmi_voltd_attribs(struct udevice *dev, struct scmi_msg *msg)
 static int sandbox_scmi_voltd_config_set(struct udevice *dev,
                                         struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_voltd_config_set_in *in = NULL;
        struct scmi_voltd_config_set_out *out = NULL;
        struct sandbox_scmi_voltd *voltd_state = NULL;
@@ -363,7 +363,7 @@ static int sandbox_scmi_voltd_config_set(struct udevice *dev,
        in = (struct scmi_voltd_config_set_in *)msg->in_msg;
        out = (struct scmi_voltd_config_set_out *)msg->out_msg;
 
-       voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id);
+       voltd_state = get_scmi_voltd_state(in->domain_id);
        if (!voltd_state) {
                dev_err(dev, "Unexpected domain ID %u\n", in->domain_id);
 
@@ -388,7 +388,6 @@ static int sandbox_scmi_voltd_config_set(struct udevice *dev,
 static int sandbox_scmi_voltd_config_get(struct udevice *dev,
                                         struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_voltd_config_get_in *in = NULL;
        struct scmi_voltd_config_get_out *out = NULL;
        struct sandbox_scmi_voltd *voltd_state = NULL;
@@ -400,7 +399,7 @@ static int sandbox_scmi_voltd_config_get(struct udevice *dev,
        in = (struct scmi_voltd_config_get_in *)msg->in_msg;
        out = (struct scmi_voltd_config_get_out *)msg->out_msg;
 
-       voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id);
+       voltd_state = get_scmi_voltd_state(in->domain_id);
        if (!voltd_state) {
                dev_err(dev, "Unexpected domain ID %u\n", in->domain_id);
 
@@ -420,7 +419,6 @@ static int sandbox_scmi_voltd_config_get(struct udevice *dev,
 static int sandbox_scmi_voltd_level_set(struct udevice *dev,
                                         struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_voltd_level_set_in *in = NULL;
        struct scmi_voltd_level_set_out *out = NULL;
        struct sandbox_scmi_voltd *voltd_state = NULL;
@@ -432,7 +430,7 @@ static int sandbox_scmi_voltd_level_set(struct udevice *dev,
        in = (struct scmi_voltd_level_set_in *)msg->in_msg;
        out = (struct scmi_voltd_level_set_out *)msg->out_msg;
 
-       voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id);
+       voltd_state = get_scmi_voltd_state(in->domain_id);
        if (!voltd_state) {
                dev_err(dev, "Unexpected domain ID %u\n", in->domain_id);
 
@@ -448,7 +446,6 @@ static int sandbox_scmi_voltd_level_set(struct udevice *dev,
 static int sandbox_scmi_voltd_level_get(struct udevice *dev,
                                        struct scmi_msg *msg)
 {
-       struct sandbox_scmi_agent *agent = dev_get_priv(dev);
        struct scmi_voltd_level_get_in *in = NULL;
        struct scmi_voltd_level_get_out *out = NULL;
        struct sandbox_scmi_voltd *voltd_state = NULL;
@@ -460,7 +457,7 @@ static int sandbox_scmi_voltd_level_get(struct udevice *dev,
        in = (struct scmi_voltd_level_get_in *)msg->in_msg;
        out = (struct scmi_voltd_level_get_out *)msg->out_msg;
 
-       voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id);
+       voltd_state = get_scmi_voltd_state(in->domain_id);
        if (!voltd_state) {
                dev_err(dev, "Unexpected domain ID %u\n", in->domain_id);
 
@@ -479,6 +476,10 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev,
        switch (msg->protocol_id) {
        case SCMI_PROTOCOL_ID_CLOCK:
                switch (msg->message_id) {
+               case SCMI_PROTOCOL_ATTRIBUTES:
+                       return sandbox_scmi_clock_protocol_attribs(dev, msg);
+               case SCMI_CLOCK_ATTRIBUTES:
+                       return sandbox_scmi_clock_attribs(dev, msg);
                case SCMI_CLOCK_RATE_SET:
                        return sandbox_scmi_clock_rate_set(dev, msg);
                case SCMI_CLOCK_RATE_GET:
@@ -541,52 +542,37 @@ static int sandbox_scmi_test_remove(struct udevice *dev)
 {
        struct sandbox_scmi_agent *agent = dev_get_priv(dev);
 
+       if (agent != sandbox_scmi_service_ctx()->agent)
+               return -EINVAL;
+
        debug_print_agent_state(dev, "removed");
 
        /* We only need to dereference the agent in the context */
-       sandbox_scmi_service_ctx()->agent[agent->idx] = NULL;
+       sandbox_scmi_service_ctx()->agent = NULL;
 
        return 0;
 }
 
 static int sandbox_scmi_test_probe(struct udevice *dev)
 {
-       static const char basename[] = "sandbox-scmi-agent@";
        struct sandbox_scmi_agent *agent = dev_get_priv(dev);
-       const size_t basename_size = sizeof(basename) - 1;
-
-       if (strncmp(basename, dev->name, basename_size))
-               return -ENOENT;
-
-       switch (dev->name[basename_size]) {
-       case '0':
-               *agent = (struct sandbox_scmi_agent){
-                       .idx = 0,
-                       .clk = scmi0_clk,
-                       .clk_count = ARRAY_SIZE(scmi0_clk),
-                       .reset = scmi0_reset,
-                       .reset_count = ARRAY_SIZE(scmi0_reset),
-                       .voltd = scmi0_voltd,
-                       .voltd_count = ARRAY_SIZE(scmi0_voltd),
-               };
-               break;
-       case '1':
-               *agent = (struct sandbox_scmi_agent){
-                       .idx = 1,
-                       .clk = scmi1_clk,
-                       .clk_count = ARRAY_SIZE(scmi1_clk),
-               };
-               break;
-       default:
-               dev_err(dev, "%s(): Unexpected agent ID %s\n",
-                       __func__, dev->name + basename_size);
-               return -ENOENT;
-       }
+
+       if (sandbox_scmi_service_ctx()->agent)
+               return -EINVAL;
+
+       *agent = (struct sandbox_scmi_agent){
+               .clk = scmi_clk,
+               .clk_count = ARRAY_SIZE(scmi_clk),
+               .reset = scmi_reset,
+               .reset_count = ARRAY_SIZE(scmi_reset),
+               .voltd = scmi_voltd,
+               .voltd_count = ARRAY_SIZE(scmi_voltd),
+       };
 
        debug_print_agent_state(dev, "probed");
 
        /* Save reference for tests purpose */
-       sandbox_scmi_service_ctx()->agent[agent->idx] = agent;
+       sandbox_scmi_service_ctx()->agent = agent;
 
        return 0;
 };
index 66a6792..9baeb46 100644 (file)
@@ -23,7 +23,7 @@
  * and reset controllers.
  */
 
-#define SCMI_TEST_DEVICES_CLK_COUNT            3
+#define SCMI_TEST_DEVICES_CLK_COUNT            2
 #define SCMI_TEST_DEVICES_RD_COUNT             1
 #define SCMI_TEST_DEVICES_VOLTD_COUNT          2
 
@@ -135,7 +135,7 @@ U_BOOT_DRIVER(sandbox_scmi_devices) = {
        .name = "sandbox-scmi_devices",
        .id = UCLASS_MISC,
        .of_match = sandbox_scmi_devices_ids,
-       .priv_auto      = sizeof(struct sandbox_scmi_device_priv),
+       .priv_auto = sizeof(struct sandbox_scmi_device_priv),
        .remove = sandbox_scmi_devices_remove,
        .probe = sandbox_scmi_devices_probe,
 };
index 4f5870b..3819f2f 100644 (file)
@@ -116,10 +116,23 @@ static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev)
 
 int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg)
 {
-       const struct scmi_agent_ops *ops = transport_dev_ops(dev);
+       const struct scmi_agent_ops *ops;
+       struct udevice *parent = dev;
+
+       /* Find related SCMI agent device */
+       do {
+               parent = dev_get_parent(parent);
+       } while (parent && device_get_uclass_id(parent) != UCLASS_SCMI_AGENT);
+
+       if (!parent) {
+               dev_err(dev, "Invalid SCMI device, agent not found\n");
+               return -ENODEV;
+       }
+
+       ops = transport_dev_ops(parent);
 
        if (ops->process_msg)
-               return ops->process_msg(dev, msg);
+               return ops->process_msg(parent, msg);
 
        return -EPROTONOSUPPORT;
 }
index a9e9b30..c3f1109 100644 (file)
@@ -87,7 +87,8 @@ config ALTERA_PIO
 config BCM6345_GPIO
        bool "BCM6345 GPIO driver"
        depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \
-                              ARCH_BCM6858 || ARCH_BCM63158)
+                              ARCH_BCM6858 || ARCH_BCM63158 || \
+                              ARCH_BCM6753)
        help
          This driver supports the GPIO banks on BCM6345 SoCs.
 
@@ -126,6 +127,13 @@ config ATMEL_PIO4
          may be dedicated as a general purpose I/O or be assigned to
          a function of an embedded peripheral.
 
+config ASPEED_GPIO
+       bool "Aspeed GPIO Driver"
+       help
+         Say yes here to support the Aspeed GPIO driver. The controller
+         is found in the AST2400, AST2500 and AST2600 BMC SoCs and
+         provides access to over 200 GPIOs on each chip.
+
 config DA8XX_GPIO
        bool "DA8xx GPIO Driver"
        help
index b2e78b0..b39dde1 100644 (file)
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o
 
 obj-$(CONFIG_$(SPL_)DM_PCA953X)        += pca953x_gpio.o
 
+obj-$(CONFIG_ASPEED_GPIO)      += gpio-aspeed.o
 obj-$(CONFIG_AT91_GPIO)        += at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)       += atmel_pio4.o
 obj-$(CONFIG_BCM6345_GPIO)     += bcm6345_gpio.o
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
new file mode 100644 (file)
index 0000000..a8a2afc
--- /dev/null
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2015 IBM Corp.
+ * Joel Stanley <joel@jms.id.au>
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ * Implementation extracted from the Linux kernel and adapted for u-boot.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <config.h>
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/sizes.h>
+
+struct aspeed_gpio_priv {
+       void *regs;
+};
+
+struct aspeed_gpio_bank {
+       u16             val_regs;       /* +0: Rd: read input value, Wr: set write latch
+                                        * +4: Rd/Wr: Direction (0=in, 1=out)
+                                        */
+       u16             rdata_reg;      /*     Rd: read write latch, Wr: <none>  */
+       u16             irq_regs;
+       u16             debounce_regs;
+       u16             tolerance_regs;
+       u16             cmdsrc_regs;
+       const char      names[4][3];
+};
+
+static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
+       {
+               .val_regs = 0x0000,
+               .rdata_reg = 0x00c0,
+               .irq_regs = 0x0008,
+               .debounce_regs = 0x0040,
+               .tolerance_regs = 0x001c,
+               .cmdsrc_regs = 0x0060,
+               .names = { "A", "B", "C", "D" },
+       },
+       {
+               .val_regs = 0x0020,
+               .rdata_reg = 0x00c4,
+               .irq_regs = 0x0028,
+               .debounce_regs = 0x0048,
+               .tolerance_regs = 0x003c,
+               .cmdsrc_regs = 0x0068,
+               .names = { "E", "F", "G", "H" },
+       },
+       {
+               .val_regs = 0x0070,
+               .rdata_reg = 0x00c8,
+               .irq_regs = 0x0098,
+               .debounce_regs = 0x00b0,
+               .tolerance_regs = 0x00ac,
+               .cmdsrc_regs = 0x0090,
+               .names = { "I", "J", "K", "L" },
+       },
+       {
+               .val_regs = 0x0078,
+               .rdata_reg = 0x00cc,
+               .irq_regs = 0x00e8,
+               .debounce_regs = 0x0100,
+               .tolerance_regs = 0x00fc,
+               .cmdsrc_regs = 0x00e0,
+               .names = { "M", "N", "O", "P" },
+       },
+       {
+               .val_regs = 0x0080,
+               .rdata_reg = 0x00d0,
+               .irq_regs = 0x0118,
+               .debounce_regs = 0x0130,
+               .tolerance_regs = 0x012c,
+               .cmdsrc_regs = 0x0110,
+               .names = { "Q", "R", "S", "T" },
+       },
+       {
+               .val_regs = 0x0088,
+               .rdata_reg = 0x00d4,
+               .irq_regs = 0x0148,
+               .debounce_regs = 0x0160,
+               .tolerance_regs = 0x015c,
+               .cmdsrc_regs = 0x0140,
+               .names = { "U", "V", "W", "X" },
+       },
+       {
+               .val_regs = 0x01E0,
+               .rdata_reg = 0x00d8,
+               .irq_regs = 0x0178,
+               .debounce_regs = 0x0190,
+               .tolerance_regs = 0x018c,
+               .cmdsrc_regs = 0x0170,
+               .names = { "Y", "Z", "AA", "AB" },
+       },
+       {
+               .val_regs = 0x01e8,
+               .rdata_reg = 0x00dc,
+               .irq_regs = 0x01a8,
+               .debounce_regs = 0x01c0,
+               .tolerance_regs = 0x01bc,
+               .cmdsrc_regs = 0x01a0,
+               .names = { "AC", "", "", "" },
+       },
+};
+
+enum aspeed_gpio_reg {
+       reg_val,
+       reg_rdata,
+       reg_dir,
+       reg_irq_enable,
+       reg_irq_type0,
+       reg_irq_type1,
+       reg_irq_type2,
+       reg_irq_status,
+       reg_debounce_sel1,
+       reg_debounce_sel2,
+       reg_tolerance,
+       reg_cmdsrc0,
+       reg_cmdsrc1,
+};
+
+#define GPIO_VAL_VALUE 0x00
+#define GPIO_VAL_DIR   0x04
+
+#define GPIO_IRQ_ENABLE        0x00
+#define GPIO_IRQ_TYPE0 0x04
+#define GPIO_IRQ_TYPE1 0x08
+#define GPIO_IRQ_TYPE2 0x0c
+#define GPIO_IRQ_STATUS        0x10
+
+#define GPIO_DEBOUNCE_SEL1 0x00
+#define GPIO_DEBOUNCE_SEL2 0x04
+
+#define GPIO_CMDSRC_0  0x00
+#define GPIO_CMDSRC_1  0x04
+#define  GPIO_CMDSRC_ARM               0
+#define  GPIO_CMDSRC_LPC               1
+#define  GPIO_CMDSRC_COLDFIRE          2
+#define  GPIO_CMDSRC_RESERVED          3
+
+/* This will be resolved at compile time */
+static inline void __iomem *bank_reg(struct aspeed_gpio_priv *gpio,
+                                    const struct aspeed_gpio_bank *bank,
+                                    const enum aspeed_gpio_reg reg)
+{
+       switch (reg) {
+       case reg_val:
+               return gpio->regs + bank->val_regs + GPIO_VAL_VALUE;
+       case reg_rdata:
+               return gpio->regs + bank->rdata_reg;
+       case reg_dir:
+               return gpio->regs + bank->val_regs + GPIO_VAL_DIR;
+       case reg_irq_enable:
+               return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE;
+       case reg_irq_type0:
+               return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0;
+       case reg_irq_type1:
+               return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1;
+       case reg_irq_type2:
+               return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE2;
+       case reg_irq_status:
+               return gpio->regs + bank->irq_regs + GPIO_IRQ_STATUS;
+       case reg_debounce_sel1:
+               return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
+       case reg_debounce_sel2:
+               return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
+       case reg_tolerance:
+               return gpio->regs + bank->tolerance_regs;
+       case reg_cmdsrc0:
+               return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_0;
+       case reg_cmdsrc1:
+               return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_1;
+       }
+       BUG();
+}
+
+#define GPIO_BANK(x)   ((x) >> 5)
+#define GPIO_OFFSET(x) ((x) & 0x1f)
+#define GPIO_BIT(x)    BIT(GPIO_OFFSET(x))
+
+static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
+{
+       unsigned int bank = GPIO_BANK(offset);
+
+       WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
+       return &aspeed_gpio_banks[bank];
+}
+
+static int
+aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+       struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+       const struct aspeed_gpio_bank *bank = to_bank(offset);
+       u32 dir = readl(bank_reg(priv, bank, reg_dir));
+
+       dir &= ~GPIO_BIT(offset);
+       writel(dir, bank_reg(priv, bank, reg_dir));
+
+       return 0;
+}
+
+static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset,
+                                       int value)
+{
+       struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+       const struct aspeed_gpio_bank *bank = to_bank(offset);
+       u32 dir = readl(bank_reg(priv, bank, reg_dir));
+       u32 output = readl(bank_reg(priv, bank, reg_val));
+
+       dir |= GPIO_BIT(offset);
+       writel(dir, bank_reg(priv, bank, reg_dir));
+
+       if (value)
+               output |= GPIO_BIT(offset);
+       else
+               output &= ~GPIO_BIT(offset);
+
+       writel(output, bank_reg(priv, bank, reg_val));
+
+       return 0;
+}
+
+static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+       struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+       const struct aspeed_gpio_bank *bank = to_bank(offset);
+
+       return !!(readl(bank_reg(priv, bank, reg_val)) & GPIO_BIT(offset));
+}
+
+static int
+aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
+{
+       struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+       const struct aspeed_gpio_bank *bank = to_bank(offset);
+       u32 data = readl(bank_reg(priv, bank, reg_val));
+
+       if (value)
+               data |= GPIO_BIT(offset);
+       else
+               data &= ~GPIO_BIT(offset);
+
+       writel(data, bank_reg(priv, bank, reg_val));
+
+       return 0;
+}
+
+static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+       struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+       const struct aspeed_gpio_bank *bank = to_bank(offset);
+
+       if (readl(bank_reg(priv, bank, reg_dir)) & GPIO_BIT(offset))
+               return GPIOF_OUTPUT;
+
+       return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops aspeed_gpio_ops = {
+       .direction_input        = aspeed_gpio_direction_input,
+       .direction_output       = aspeed_gpio_direction_output,
+       .get_value              = aspeed_gpio_get_value,
+       .set_value              = aspeed_gpio_set_value,
+       .get_function           = aspeed_gpio_get_function,
+};
+
+static int aspeed_gpio_probe(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+       struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+
+       uc_priv->bank_name = dev->name;
+       ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count);
+       priv->regs = devfdt_get_addr_ptr(dev);
+
+       return 0;
+}
+
+static const struct udevice_id aspeed_gpio_ids[] = {
+       { .compatible = "aspeed,ast2400-gpio",  },
+       { .compatible = "aspeed,ast2500-gpio",  },
+       { .compatible = "aspeed,ast2600-gpio",  },
+       { }
+};
+
+U_BOOT_DRIVER(gpio_aspeed) = {
+       .name   = "gpio-aspeed",
+       .id     = UCLASS_GPIO,
+       .of_match = aspeed_gpio_ids,
+       .ops    = &aspeed_gpio_ops,
+       .probe  = aspeed_gpio_probe,
+       .priv_auto = sizeof(struct aspeed_gpio_priv),
+};
index cc87fbf..430d076 100644 (file)
@@ -28,6 +28,13 @@ config LED_BCM6358
          LED HW controller accessed via MMIO registers.
          HW has no blinking capabilities and up to 32 LEDs can be controlled.
 
+config LED_BCM6753
+       bool "LED Support for BCM6753"
+       depends on LED && ARCH_BCM6753
+       help
+         This option enables support for LEDs connected to the BCM6753
+         HW has blinking and fading capabilities and up to 32 LEDs can be controlled.
+
 config LED_BCM6858
        bool "LED Support for BCM6858"
        depends on LED && (ARCH_BCM68360 || ARCH_BCM6858 || ARCH_BCM63158)
index 8e3ae7f..2aa2c21 100644 (file)
@@ -6,6 +6,7 @@
 obj-y += led-uclass.o
 obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o
 obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o
+obj-$(CONFIG_LED_BCM6753) += led_bcm6753.o
 obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o
 obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o
 obj-$(CONFIG_LED_CORTINA) += led_cortina.o
diff --git a/drivers/led/led_bcm6753.c b/drivers/led/led_bcm6753.c
new file mode 100644 (file)
index 0000000..a32bd82
--- /dev/null
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * based on:
+ * drivers/led/led_bcm6858.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <led.h>
+#include <log.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <linux/bitops.h>
+
+#define LEDS_MAX               32
+#define LEDS_WAIT              100
+
+/* LED Mode register */
+#define LED_MODE_REG           0x0
+#define LED_MODE_OFF           0
+#define LED_MODE_ON            1
+#define LED_MODE_MASK          1
+
+/* LED Controller Global settings register */
+#define CLED_CTRL_REG                  0x00
+#define CLED_CTRL_SERIAL_LED_DATA_PPOL BIT(1)
+#define CLED_CTRL_SERIAL_LED_CLK_POL   BIT(2)
+#define CLED_CTRL_SERIAL_LED_EN_POL    BIT(3)
+#define CLED_CTRL_SERIAL_LED_MSB_FIRST BIT(4)
+#define CLED_CTRL_MASK                 0x1E
+/* LED Controller IP LED source select register */
+#define CLED_HW_LED_EN_REG             0x04
+/* Hardware LED Polarity register */
+#define CLED_HW_LED_IP_PPOL_REG                0x0c
+/* Soft LED Set Register */
+#define CLED_SW_LED_IP_SET_REG         0x10
+/* Parallel LED Output Polarity Register */
+#define CLED_PLED_OP_PPOL_REG          0x18
+/* LED Channel activate register */
+#define CLED_LED_CH_ACTIVATE_REG       0x1c
+/* LED 0 Config 0 reg */
+#define CLED_LED_0_CONFIG_0            0x20
+/* Soft LED Clear Register */
+#define CLED_SW_LED_IP_CLEAR_REG       0x444
+/* Soft LED Status Register */
+#define CLED_SW_LED_IP_STATUS_REG      0x448
+
+/* Size of all registers used for the config of one LED */
+#define CLED_CONFIG_SIZE               (4 * sizeof(u32))
+
+#define CLED_CONFIG0_MODE              0
+#define CLED_CONFIG0_MODE_MASK         (BIT(0) | BIT(1))
+#define CLED_CONFIG0_MODE_STEADY       0
+#define CLED_CONFIG0_MODE_FADING       1
+#define CLED_CONFIG0_MODE_PULSATING    2
+
+#define CLED_CONFIG0_FLASH_CTRL_SHIFT  3
+#define CLED_CONFIG0_FLASH_CTRL_MASK   (BIT(3) | BIT(4) | BIT(5))
+
+struct bcm6753_led_priv {
+       void __iomem *regs;
+       u8 pin;
+};
+
+/*
+ * The value for flash rate are:
+ * 0 : no blinking
+ * 1 : rate is 25 Hz => 40 ms (period)
+ * 2 : rate is 12.5 Hz => 80 ms (period)
+ * 3 : rate is 6.25 Hz => 160 ms (period)
+ * 4 : rate is 3.125 Hz => 320 ms (period)
+ * 5 : rate is 1.5625 Hz => 640 ms (period)
+ * 6 : rate is 0.7815 Hz => 1280 ms (period)
+ * 7 : rate is 0.390625 Hz => 2560 ms (period)
+ */
+static const int bcm6753_flash_rate[8] = {
+       0, 40, 80, 160, 320, 640, 1280, 2560
+};
+
+static u32 bcm6753_flash_rate_value(int period_ms)
+{
+       unsigned long value = 7;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(bcm6753_flash_rate); i++) {
+               if (period_ms <= bcm6753_flash_rate[i]) {
+                       value = i;
+                       break;
+               }
+       }
+
+       return value;
+}
+
+static int bcm6753_led_set_period(struct udevice *dev, int period_ms)
+{
+       struct bcm6753_led_priv *priv = dev_get_priv(dev);
+       u32 offset, shift, value;
+
+       offset = CLED_LED_0_CONFIG_0 + (CLED_CONFIG_SIZE * priv->pin);
+       value  = bcm6753_flash_rate_value(period_ms);
+       shift  = CLED_CONFIG0_FLASH_CTRL_SHIFT;
+
+       /* set mode steady */
+       clrbits_32(priv->regs + offset, CLED_CONFIG0_MODE_MASK);
+       setbits_32(priv->regs + offset, CLED_CONFIG0_MODE_STEADY);
+
+       /* set flash rate */
+       clrbits_32(priv->regs + offset, CLED_CONFIG0_FLASH_CTRL_MASK);
+       setbits_32(priv->regs + offset, value << shift);
+
+       /* enable config */
+       setbits_32(priv->regs + CLED_LED_CH_ACTIVATE_REG, 1 << priv->pin);
+
+       return 0;
+}
+
+static enum led_state_t bcm6753_led_get_state(struct udevice *dev)
+{
+       struct bcm6753_led_priv *priv = dev_get_priv(dev);
+       enum led_state_t state = LEDST_OFF;
+       u32 sw_led_ip_status;
+
+       sw_led_ip_status = readl(priv->regs + CLED_SW_LED_IP_STATUS_REG);
+       if (sw_led_ip_status & (1 << priv->pin))
+               state = LEDST_ON;
+
+       return state;
+}
+
+static int bcm6753_led_set_state(struct udevice *dev, enum led_state_t state)
+{
+       struct bcm6753_led_priv *priv = dev_get_priv(dev);
+
+       switch (state) {
+       case LEDST_OFF:
+               setbits_32(priv->regs + CLED_SW_LED_IP_CLEAR_REG, (1 << priv->pin));
+               if (IS_ENABLED(CONFIG_LED_BLINK))
+                       bcm6753_led_set_period(dev, 0);
+               break;
+       case LEDST_ON:
+               setbits_32(priv->regs + CLED_SW_LED_IP_SET_REG, (1 << priv->pin));
+               if (IS_ENABLED(CONFIG_LED_BLINK))
+                       bcm6753_led_set_period(dev, 0);
+               break;
+       case LEDST_TOGGLE:
+               if (bcm6753_led_get_state(dev) == LEDST_OFF)
+                       return bcm6753_led_set_state(dev, LEDST_ON);
+               else
+                       return bcm6753_led_set_state(dev, LEDST_OFF);
+               break;
+#ifdef CONFIG_LED_BLINK
+       case LEDST_BLINK:
+               setbits_32(priv->regs + CLED_SW_LED_IP_SET_REG, (1 << priv->pin));
+               break;
+#endif
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static const struct led_ops bcm6753_led_ops = {
+       .get_state = bcm6753_led_get_state,
+       .set_state = bcm6753_led_set_state,
+#ifdef CONFIG_LED_BLINK
+       .set_period = bcm6753_led_set_period,
+#endif
+};
+
+static int bcm6753_led_probe(struct udevice *dev)
+{
+       struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+       /* Top-level LED node */
+       if (!uc_plat->label) {
+               void __iomem *regs;
+               u32 set_bits = 0;
+
+               regs = dev_remap_addr(dev);
+               if (!regs)
+                       return -EINVAL;
+
+               if (dev_read_bool(dev, "brcm,serial-led-msb-first"))
+                       set_bits |= CLED_CTRL_SERIAL_LED_MSB_FIRST;
+               if (dev_read_bool(dev, "brcm,serial-led-en-pol"))
+                       set_bits |= CLED_CTRL_SERIAL_LED_EN_POL;
+               if (dev_read_bool(dev, "brcm,serial-led-clk-pol"))
+                       set_bits |= CLED_CTRL_SERIAL_LED_CLK_POL;
+               if (dev_read_bool(dev, "brcm,serial-led-data-ppol"))
+                       set_bits |= CLED_CTRL_SERIAL_LED_DATA_PPOL;
+
+               clrsetbits_32(regs + CLED_CTRL_REG, CLED_CTRL_MASK, set_bits);
+       } else {
+               struct bcm6753_led_priv *priv = dev_get_priv(dev);
+               void __iomem *regs;
+               unsigned int pin;
+
+               regs = dev_remap_addr(dev_get_parent(dev));
+               if (!regs)
+                       return -EINVAL;
+
+               pin = dev_read_u32_default(dev, "reg", LEDS_MAX);
+               if (pin >= LEDS_MAX)
+                       return -EINVAL;
+
+               priv->regs = regs;
+               priv->pin = pin;
+
+               /* this led is managed by software */
+               clrbits_32(regs + CLED_HW_LED_EN_REG, 1 << pin);
+
+               /* configure the polarity */
+               if (dev_read_bool(dev, "active-low"))
+                       clrbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin);
+               else
+                       setbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin);
+       }
+
+       return 0;
+}
+
+static int bcm6753_led_bind(struct udevice *parent)
+{
+       ofnode node;
+
+       dev_for_each_subnode(node, parent) {
+               struct led_uc_plat *uc_plat;
+               struct udevice *dev;
+               const char *label;
+               int ret;
+
+               label = ofnode_read_string(node, "label");
+               if (!label) {
+                       debug("%s: node %s has no label\n", __func__,
+                             ofnode_get_name(node));
+                       return -EINVAL;
+               }
+
+               ret = device_bind_driver_to_node(parent, "bcm6753-led",
+                                                ofnode_get_name(node),
+                                                node, &dev);
+               if (ret)
+                       return ret;
+
+               uc_plat = dev_get_uclass_plat(dev);
+               uc_plat->label = label;
+       }
+
+       return 0;
+}
+
+static const struct udevice_id bcm6753_led_ids[] = {
+       { .compatible = "brcm,bcm6753-leds" },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6753_led) = {
+       .name = "bcm6753-led",
+       .id = UCLASS_LED,
+       .of_match = bcm6753_led_ids,
+       .bind = bcm6753_led_bind,
+       .probe = bcm6753_led_probe,
+       .priv_auto = sizeof(struct bcm6753_led_priv),
+       .ops = &bcm6753_led_ops,
+};
index 8200658..b2f4a4e 100644 (file)
@@ -2019,6 +2019,7 @@ static const struct udevice_id omap_hsmmc_ids[] = {
        { .compatible = "ti,omap3-hsmmc" },
        { .compatible = "ti,omap4-hsmmc" },
        { .compatible = "ti,am33xx-hsmmc" },
+       { .compatible = "ti,am335-sdhci" },
        { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
        { }
 };
index 2784738..b91df05 100644 (file)
@@ -90,9 +90,33 @@ struct rockchip_sdhc {
 };
 
 struct sdhci_data {
-       int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
        int (*emmc_phy_init)(struct udevice *dev);
        int (*get_phy)(struct udevice *dev);
+
+       /**
+        * set_control_reg() - Set SDHCI control registers
+        *
+        * This is the set_control_reg() SDHCI operation that should be
+        * used for the hardware this driver data is associated with.
+        * Normally, this is used to set up control registers for
+        * voltage level and UHS speed mode.
+        *
+        * @host: SDHCI host structure
+        */
+       void (*set_control_reg)(struct sdhci_host *host);
+
+       /**
+        * set_ios_post() - Host specific hook after set_ios() calls
+        *
+        * This is the set_ios_post() SDHCI operation that should be
+        * used for the hardware this driver data is associated with.
+        * Normally, this is a hook that is called after sdhci_set_ios()
+        * that does any necessary host-specific configuration.
+        *
+        * @host: SDHCI host structure
+        * Return: 0 if successful, -ve on error
+        */
+       int (*set_ios_post)(struct sdhci_host *host);
 };
 
 static int rk3399_emmc_phy_init(struct udevice *dev)
@@ -182,15 +206,28 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
        return 0;
 }
 
-static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
+static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
 {
        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct mmc *mmc = host->mmc;
+       uint clock = mmc->tran_speed;
        int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
 
        if (cycle_phy)
                rk3399_emmc_phy_power_off(priv->phy);
 
-       sdhci_set_clock(host->mmc, clock);
+       sdhci_set_control_reg(host);
+};
+
+static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
+{
+       struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct mmc *mmc = host->mmc;
+       uint clock = mmc->tran_speed;
+       int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
+
+       if (!clock)
+               clock = mmc->clock;
 
        if (cycle_phy)
                rk3399_emmc_phy_power_on(priv->phy, clock);
@@ -269,10 +306,8 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
        return 0;
 }
 
-static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
+static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 {
-       struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-       struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
        struct mmc *mmc = host->mmc;
        uint clock = mmc->tran_speed;
        u32 reg;
@@ -280,8 +315,7 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
        if (!clock)
                clock = mmc->clock;
 
-       if (data->emmc_set_clock)
-               data->emmc_set_clock(host, clock);
+       rk3568_sdhci_emmc_set_clock(host, clock);
 
        if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
                reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
@@ -295,6 +329,26 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
        return 0;
 }
 
+static void rockchip_sdhci_set_control_reg(struct sdhci_host *host)
+{
+       struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+
+       if (data->set_control_reg)
+               data->set_control_reg(host);
+}
+
+static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
+{
+       struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+
+       if (data->set_ios_post)
+               return data->set_ios_post(host);
+
+       return 0;
+}
+
 static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 {
        struct sdhci_host *host = dev_get_priv(mmc->dev);
@@ -358,6 +412,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 static struct sdhci_ops rockchip_sdhci_ops = {
        .set_ios_post   = rockchip_sdhci_set_ios_post,
        .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
+       .set_control_reg = rockchip_sdhci_set_control_reg,
 };
 
 static int rockchip_sdhci_probe(struct udevice *dev)
@@ -436,15 +491,16 @@ static int rockchip_sdhci_bind(struct udevice *dev)
 }
 
 static const struct sdhci_data rk3399_data = {
-       .emmc_set_clock = rk3399_sdhci_emmc_set_clock,
        .get_phy = rk3399_emmc_get_phy,
        .emmc_phy_init = rk3399_emmc_phy_init,
+       .set_control_reg = rk3399_sdhci_set_control_reg,
+       .set_ios_post = rk3399_sdhci_set_ios_post,
 };
 
 static const struct sdhci_data rk3568_data = {
-       .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
        .get_phy = rk3568_emmc_get_phy,
        .emmc_phy_init = rk3568_emmc_phy_init,
+       .set_ios_post = rk3568_sdhci_set_ios_post,
 };
 
 static const struct udevice_id sdhci_ids[] = {
index bde3004..588ebe9 100644 (file)
@@ -52,6 +52,13 @@ config CFI_FLASH
          option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
          for more information on CFI.
 
+config CFI_FLASH_USE_WEAK_ACCESSORS
+       bool "Allow read/write functions to be overridden"
+       depends on FLASH_CFI_DRIVER
+       help
+         Enable this option to allow for the flash_{read,write}{8,16,32,64}
+         functions to be overridden by the platform.
+
 config SYS_FLASH_USE_BUFFER_WRITE
        bool "Enable buffered writes to flash"
        depends on FLASH_CFI_DRIVER
index 0e826c1..1eab21e 100644 (file)
@@ -91,6 +91,12 @@ config NAND_BRCMNAND_6368
        help
          Enable support for broadcom nand driver on bcm6368.
 
+config NAND_BRCMNAND_6753
+       bool "Support Broadcom NAND controller on bcm6753"
+       depends on NAND_BRCMNAND && ARCH_BCM6753
+       help
+         Enable support for broadcom nand driver on bcm6753.
+
 config NAND_BRCMNAND_68360
        bool "Support Broadcom NAND controller on bcm68360"
        depends on NAND_BRCMNAND && ARCH_BCM68360
index 5d9e7e3..f46a7ed 100644 (file)
@@ -2,6 +2,7 @@
 
 obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o
+obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c
new file mode 100644 (file)
index 0000000..feae66e
--- /dev/null
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+
+struct bcm6753_nand_soc {
+       struct brcmnand_soc soc;
+       void __iomem *base;
+};
+
+#define BCM6753_NAND_INT               0x00
+#define BCM6753_NAND_STATUS_SHIFT      0
+#define BCM6753_NAND_STATUS_MASK       (0xfff << BCM6753_NAND_STATUS_SHIFT)
+
+#define BCM6753_NAND_INT_EN            0x04
+#define BCM6753_NAND_ENABLE_SHIFT      0
+#define BCM6753_NAND_ENABLE_MASK       (0xffff << BCM6753_NAND_ENABLE_SHIFT)
+
+enum {
+       BCM6753_NP_READ         = BIT(0),
+       BCM6753_BLOCK_ERASE     = BIT(1),
+       BCM6753_COPY_BACK       = BIT(2),
+       BCM6753_PAGE_PGM        = BIT(3),
+       BCM6753_CTRL_READY      = BIT(4),
+       BCM6753_DEV_RBPIN       = BIT(5),
+       BCM6753_ECC_ERR_UNC     = BIT(6),
+       BCM6753_ECC_ERR_CORR    = BIT(7),
+};
+
+static bool bcm6753_nand_intc_ack(struct brcmnand_soc *soc)
+{
+       struct bcm6753_nand_soc *priv =
+                       container_of(soc, struct bcm6753_nand_soc, soc);
+       void __iomem *mmio = priv->base + BCM6753_NAND_INT;
+       u32 val = brcmnand_readl(mmio);
+
+       if (val & (BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT)) {
+               /* Ack interrupt */
+               val &= ~BCM6753_NAND_STATUS_MASK;
+               val |= BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT;
+               brcmnand_writel(val, mmio);
+               return true;
+       }
+
+       return false;
+}
+
+static void bcm6753_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+       struct bcm6753_nand_soc *priv =
+                       container_of(soc, struct bcm6753_nand_soc, soc);
+       void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN;
+       u32 val = brcmnand_readl(mmio);
+
+       /* Don't ack any interrupts */
+       val &= ~BCM6753_NAND_STATUS_MASK;
+
+       if (en)
+               val |= BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT;
+       else
+               val &= ~(BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT);
+
+       brcmnand_writel(val, mmio);
+}
+
+static int bcm6753_nand_probe(struct udevice *dev)
+{
+       struct udevice *pdev = dev;
+       struct bcm6753_nand_soc *priv = dev_get_priv(dev);
+       struct brcmnand_soc *soc;
+       struct resource res;
+
+       soc = &priv->soc;
+
+       dev_read_resource_byname(pdev, "nand-int-base", &res);
+       priv->base = devm_ioremap(dev, res.start, resource_size(&res));
+       if (IS_ERR(priv->base))
+               return PTR_ERR(priv->base);
+
+       soc->ctlrdy_ack = bcm6753_nand_intc_ack;
+       soc->ctlrdy_set_enabled = bcm6753_nand_intc_set;
+
+       /* Disable and ack all interrupts  */
+       brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN);
+       brcmnand_writel(0, priv->base + BCM6753_NAND_INT);
+
+       return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id bcm6753_nand_dt_ids[] = {
+       {
+               .compatible = "brcm,nand-bcm6753",
+       },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6753_nand) = {
+       .name = "bcm6753-nand",
+       .id = UCLASS_MTD,
+       .of_match = bcm6753_nand_dt_ids,
+       .probe = bcm6753_nand_probe,
+       .priv_auto = sizeof(struct bcm6753_nand_soc),
+};
+
+void board_nand_init(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device_by_driver(UCLASS_MTD,
+                                         DM_DRIVER_GET(bcm6753_nand), &dev);
+       if (ret && ret != -ENODEV)
+               pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+                      ret);
+}
index b551ebd..763bab0 100644 (file)
@@ -119,7 +119,7 @@ const struct flash_info spi_nor_ids[] = {
        },
        {
                INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
-                       SECT_4K | SPI_NOR_DUAL_READ |
+                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
                        SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
        },
        {
index 1e180ee..8a81a74 100644 (file)
@@ -6,7 +6,6 @@
  */
 #include <common.h>
 #include <asm/bitops.h>
-#include <asm/cpm_85xx.h>
 #include <pci.h>
 #include <dm.h>
 #include <asm/fsl_law.h>
index d95d4b4..fc5044f 100644 (file)
@@ -358,26 +358,10 @@ static inline int cdns_reset_deassert(struct reset_control *rst)
                return 0;
 }
 
-static inline struct cdns_sierra_inst *phy_get_drvdata(struct phy *phy)
+static int cdns_sierra_link_init(struct phy *gphy)
 {
-       struct cdns_sierra_phy *sp = dev_get_priv(phy->dev);
-       int index;
-
-       if (phy->id >= SIERRA_MAX_LANES)
-               return NULL;
-
-       for (index = 0; index < sp->nsubnodes; index++) {
-               if (phy->id == sp->phys[index]->mlane)
-                       return sp->phys[index];
-       }
-
-       return NULL;
-}
-
-static int cdns_sierra_phy_init(struct phy *gphy)
-{
-       struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
-       struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
+       struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev);
+       struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev->parent);
        struct cdns_sierra_data *init_data = phy->init_data;
        struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
        enum cdns_sierra_phy_type phy_type = ins->phy_type;
@@ -443,10 +427,11 @@ static int cdns_sierra_phy_init(struct phy *gphy)
        return 0;
 }
 
-static int cdns_sierra_phy_on(struct phy *gphy)
+static int cdns_sierra_link_on(struct phy *gphy)
 {
-       struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
-       struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
+       struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev);
+       struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent);
+
        struct udevice *dev = gphy->dev;
        u32 val;
        int ret;
@@ -503,16 +488,16 @@ static int cdns_sierra_phy_on(struct phy *gphy)
        return ret;
 }
 
-static int cdns_sierra_phy_off(struct phy *gphy)
+static int cdns_sierra_link_off(struct phy *gphy)
 {
-       struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
+       struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev);
 
        return reset_assert_bulk(ins->lnk_rst);
 }
 
-static int cdns_sierra_phy_reset(struct phy *gphy)
+static int cdns_sierra_link_reset(struct phy *gphy)
 {
-       struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
+       struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent);
 
        reset_control_assert(sp->phy_rst);
        reset_control_deassert(sp->phy_rst);
@@ -520,10 +505,10 @@ static int cdns_sierra_phy_reset(struct phy *gphy)
 };
 
 static const struct phy_ops ops = {
-       .init           = cdns_sierra_phy_init,
-       .power_on       = cdns_sierra_phy_on,
-       .power_off      = cdns_sierra_phy_off,
-       .reset          = cdns_sierra_phy_reset,
+       .init           = cdns_sierra_link_init,
+       .power_on       = cdns_sierra_link_on,
+       .power_off      = cdns_sierra_link_off,
+       .reset          = cdns_sierra_link_reset,
 };
 
 struct cdns_sierra_pll_mux_sel {
@@ -580,7 +565,7 @@ static const struct clk_ops cdns_sierra_pll_mux_ops = {
        .set_parent = cdns_sierra_pll_mux_set_parent,
 };
 
-int cdns_sierra_pll_mux_probe(struct udevice *dev)
+static int cdns_sierra_pll_mux_probe(struct udevice *dev)
 {
        struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
        struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
@@ -1012,9 +997,8 @@ static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
        return 0;
 }
 
-static int cdns_sierra_bind_link_nodes(struct  cdns_sierra_phy *sp)
+static int cdns_sierra_phy_bind(struct udevice *dev)
 {
-       struct udevice *dev = sp->dev;
        struct driver *link_drv;
        ofnode child;
        int rc;
@@ -1079,6 +1063,7 @@ U_BOOT_DRIVER(sierra_phy_link) = {
        .name           = "sierra_phy_link",
        .id             = UCLASS_PHY,
        .probe          = cdns_sierra_link_probe,
+       .ops            = &ops,
        .priv_auto      = sizeof(struct cdns_sierra_inst),
 };
 
@@ -1141,10 +1126,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
        }
 
        sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
-       /* Binding link nodes as children to serdes */
-       ret = cdns_sierra_bind_link_nodes(sp);
-       if (ret)
-               goto clk_disable;
 
        dev_info(dev, "sierra probed\n");
        return 0;
@@ -1971,10 +1952,10 @@ static const struct udevice_id cdns_sierra_id_table[] = {
 
 U_BOOT_DRIVER(sierra_phy_provider) = {
        .name           = "cdns,sierra",
-       .id             = UCLASS_PHY,
+       .id             = UCLASS_MISC,
        .of_match       = cdns_sierra_id_table,
        .probe          = cdns_sierra_phy_probe,
        .remove         = cdns_sierra_phy_remove,
-       .ops            = &ops,
+       .bind           = cdns_sierra_phy_bind,
        .priv_auto      = sizeof(struct cdns_sierra_phy),
 };
index 3ddeaf4..2966bdc 100644 (file)
@@ -38,7 +38,7 @@ static int scmi_voltd_set_enable(struct udevice *dev, bool enable)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(dev->parent->parent, &msg);
+       ret = devm_scmi_process_msg(dev, &msg);
        if (ret)
                return ret;
 
@@ -61,7 +61,7 @@ static int scmi_voltd_get_enable(struct udevice *dev)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(dev->parent->parent, &msg);
+       ret = devm_scmi_process_msg(dev, &msg);
        if (ret < 0)
                return ret;
 
@@ -85,7 +85,7 @@ static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(dev->parent->parent, &msg);
+       ret = devm_scmi_process_msg(dev, &msg);
        if (ret < 0)
                return ret;
 
@@ -104,7 +104,7 @@ static int scmi_voltd_get_voltage_level(struct udevice *dev)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(dev->parent->parent, &msg);
+       ret = devm_scmi_process_msg(dev, &msg);
        if (ret < 0)
                return ret;
 
@@ -147,7 +147,7 @@ static int scmi_regulator_probe(struct udevice *dev)
        /* Check voltage domain is known from SCMI server */
        in.domain_id = pdata->domain_id;
 
-       ret = devm_scmi_process_msg(dev->parent->parent, &scmi_msg);
+       ret = devm_scmi_process_msg(dev, &scmi_msg);
        if (ret) {
                dev_err(dev, "Failed to query voltage domain %u: %d\n",
                        pdata->domain_id, ret);
index 576d5af..0deab86 100644 (file)
@@ -1,66 +1,77 @@
-if RAM || SPL_RAM
+menuconfig ASPEED_RAM
+       bool "ASPEED SDRAM configuration"
+       depends on RAM && ARCH_ASPEED
+       default ARCH_ASPEED
+       help
+        Configuration options for DDR SDRAM on ASPEED systems.
+
+        RAM initialisation is always built in for the platform. This menu
+        allows customisation of the configuration used.
+
+if ASPEED_RAM
 
 config ASPEED_DDR4_DUALX8
        bool "Enable Dual X8 DDR4 die"
-       depends on DM && OF_CONTROL && ARCH_ASPEED
+       depends on ASPEED_RAM
+       help
+        Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM
+        SRAM controller needs to know if the memory chip mounted on the
+        board is dual x8 die or not, otherwise it may get the wrong
+        size of the memory space.
+
+config ASPEED_BYPASS_SELFTEST
+       depends on ASPEED_RAM
+       depends on ASPEED_AST2600
+       bool "Bypass self test during initialization"
+       help
+         Say Y here to bypass DRAM self test to speed up the boot time.
+
+config ASPEED_ECC
+       bool "ASPEED SDRAM ECC"
+       depends on ASPEED_RAM
+       depends on ASPEED_AST2600
        help
-               Say Y if dual X8 DDR4 die is used on the board.  The aspeed ddr sdram
-               controller needs to know if the memory chip mounted on the board is dual
-                x8 die or not.  Or it may get the wrong size of the memory space.
+         Enable SDRAM ECC function. This configures the SDRAM controller to
+         perform error detection and correction, sacrificing 1/9th of the
+         installed RAM to do so.
 
-if ASPEED_AST2600
+
+config ASPEED_ECC_SIZE
+       int "ECC size: 0=driver auto-caluated"
+       depends on ASPEED_ECC
+       default 0
+       help
+         SDRAM size with the error correcting code enabled. The unit is
+         in Megabytes.  Noted that only the 8/9 of the configured size
+         can be used by the system.  The remaining 1/9 will be used by
+         the ECC engine.  If the size is set to 0, the sdram driver will
+         calculate the SDRAM size and set the whole range be ECC enabled.
 
 choice
-       prompt "DDR4 target date rate"
+       prompt "AST2600 DDR4 target date rate"
        default ASPEED_DDR4_1600
+       depends on ASPEED_RAM
+       depends on ASPEED_AST2600
 
 config ASPEED_DDR4_400
-       bool "DDR4 targets at 400Mbps"
-       depends on DM && OF_CONTROL && ARCH_ASPEED
+       bool "400Mbps"
        help
          select DDR4 target data rate at 400M
 
 config ASPEED_DDR4_800
-       bool "DDR4 targets at 800Mbps"
-       depends on DM && OF_CONTROL && ARCH_ASPEED
+       bool "800Mbps"
        help
          select DDR4 target data rate at 800M
 
 config ASPEED_DDR4_1333
-       bool "DDR4 targets at 1333Mbps"
-       depends on DM && OF_CONTROL && ARCH_ASPEED
+       bool "1333Mbps"
        help
          select DDR4 target data rate at 1333M
 
 config ASPEED_DDR4_1600
-       bool "DDR4 targets at 1600Mbps"
-       depends on DM && OF_CONTROL && ARCH_ASPEED
+       bool "1600Mbps"
        help
          select DDR4 target data rate at 1600M
 endchoice
 
-config ASPEED_BYPASS_SELFTEST
-       bool "bypass self test during DRAM initialization"
-       help
-         Say Y here to bypass DRAM self test to speed up the boot time
-
-config ASPEED_ECC
-       bool "aspeed SDRAM error correcting code"
-       depends on DM && OF_CONTROL && ARCH_ASPEED
-       help
-         enable SDRAM ECC function
-
-if ASPEED_ECC
-config ASPEED_ECC_SIZE
-       int "ECC size: 0=driver auto-caluated"
-       depends on ASPEED_ECC
-       default 0
-       help
-         SDRAM size with the error correcting code enabled. The unit is
-         in Megabytes.  Noted that only the 8/9 of the configured size
-         can be used by the system.  The remaining 1/9 will be used by
-         the ECC engine.  If the size is set to 0, the sdram driver will
-         calculate the SDRAM size and set the whole range be ECC enabled.
-endif # end of ASPEED_ECC
-endif # end of ASPEED_AST2600
-endif # end of RAM || SPL_RAM
+endif # End of ASPEED_RAM
index ca0135a..850cb18 100644 (file)
@@ -26,7 +26,7 @@ static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert)
                                          in, out);
        int ret;
 
-       ret = devm_scmi_process_msg(rst->dev->parent, &msg);
+       ret = devm_scmi_process_msg(rst->dev, &msg);
        if (ret)
                return ret;
 
@@ -58,7 +58,7 @@ static int scmi_reset_request(struct reset_ctl *rst)
         * We don't really care about the attribute, just check
         * the reset domain exists.
         */
-       ret = devm_scmi_process_msg(rst->dev->parent, &msg);
+       ret = devm_scmi_process_msg(rst->dev, &msg);
        if (ret)
                return ret;
 
index 362cedd..f30f352 100644 (file)
@@ -66,7 +66,8 @@ static int serial_check_stdout(const void *blob, struct udevice **devp)
         */
        if (node > 0 && !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
                                        devp, NULL, false)) {
-               if (!device_probe(*devp))
+               if (device_get_uclass_id(*devp) == UCLASS_SERIAL &&
+                   !device_probe(*devp))
                        return 0;
        }
 
index 0a6a85f..423a757 100644 (file)
@@ -185,6 +185,12 @@ config ICH_SPI
          access the SPI NOR flash on platforms embedding this Intel
          ICH IP core.
 
+config IPROC_QSPI
+       bool "Broadcom iProc QSPI Flash Controller driver"
+       help
+         Enable Broadcom iProc QSPI Flash Controller driver.
+         This driver can be used to access the SPI NOR flash.
+
 config KIRKWOOD_SPI
        bool "Marvell Kirkwood SPI Driver"
        help
index bea746f..7f43f84 100644 (file)
@@ -34,6 +34,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
+obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
 obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
index d1b3808..db68061 100644 (file)
@@ -201,11 +201,9 @@ static int cadence_spi_probe(struct udevice *bus)
                }
        }
 
-       ret = reset_get_bulk(bus, &priv->resets);
-       if (ret)
-               dev_warn(bus, "Can't get reset: %d\n", ret);
-       else
-               reset_deassert_bulk(&priv->resets);
+       priv->resets = devm_reset_bulk_get_optional(bus);
+       if (priv->resets)
+               reset_deassert_bulk(priv->resets);
 
        if (!priv->qspi_is_init) {
                cadence_qspi_apb_controller_init(plat);
@@ -220,8 +218,12 @@ static int cadence_spi_probe(struct udevice *bus)
 static int cadence_spi_remove(struct udevice *dev)
 {
        struct cadence_spi_priv *priv = dev_get_priv(dev);
+       int ret = 0;
+
+       if (priv->resets)
+               ret = reset_release_bulk(priv->resets);
 
-       return reset_release_bulk(&priv->resets);
+       return ret;
 }
 
 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
index 49b4011..19345ca 100644 (file)
@@ -56,7 +56,7 @@ struct cadence_spi_priv {
        unsigned int    qspi_calibrated_cs;
        unsigned int    previous_hz;
 
-       struct reset_ctl_bulk resets;
+       struct reset_ctl_bulk *resets;
 };
 
 /* Functions call declaration */
index 7421211..fc22f54 100644 (file)
@@ -572,7 +572,7 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
        int pos, i, ret = 0;
        struct udevice *bus = slave->dev->parent;
        struct dw_spi_priv *priv = dev_get_priv(bus);
-       u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+       u8 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
        u8 op_buf[op_len];
        u32 cr0;
 
diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c
new file mode 100644 (file)
index 0000000..b5c2743
--- /dev/null
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020-2021 Broadcom
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/log2.h>
+
+/* Delay required to change the mode of operation */
+#define BUSY_DELAY_US                          1
+#define BUSY_TIMEOUT_US                                200000
+#define DWORD_ALIGNED(a)                       (!(((ulong)(a)) & 3))
+
+/* Chip attributes */
+#define QSPI_AXI_CLK                           175000000
+#define SPBR_MIN                               8U
+#define SPBR_MAX                               255U
+#define NUM_CDRAM                              16U
+
+#define CDRAM_PCS0                             2
+#define CDRAM_CONT                             BIT(7)
+#define CDRAM_BITS_EN                          BIT(6)
+#define CDRAM_QUAD_MODE                                BIT(8)
+#define CDRAM_RBIT_INPUT                       BIT(10)
+#define MSPI_SPE                               BIT(6)
+#define MSPI_CONT_AFTER_CMD                    BIT(7)
+#define MSPI_MSTR                              BIT(7)
+
+/* Register fields */
+#define MSPI_SPCR0_MSB_BITS_8                  0x00000020
+#define BSPI_RAF_CONTROL_START_MASK            0x00000001
+#define BSPI_RAF_STATUS_SESSION_BUSY_MASK      0x00000001
+#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK                0x00000002
+#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT    3
+#define BSPI_STRAP_OVERRIDE_4BYTE_SHIFT        2
+#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT    1
+#define BSPI_STRAP_OVERRIDE_SHIFT              0
+#define BSPI_BPC_DATA_SHIFT                    0
+#define BSPI_BPC_MODE_SHIFT                    8
+#define BSPI_BPC_ADDR_SHIFT                    16
+#define BSPI_BPC_CMD_SHIFT                     24
+#define BSPI_BPP_ADDR_SHIFT                    16
+
+/* MSPI registers */
+#define MSPI_SPCR0_LSB_REG                     0x000
+#define MSPI_SPCR0_MSB_REG                     0x004
+#define MSPI_SPCR1_LSB_REG                     0x008
+#define MSPI_SPCR1_MSB_REG                     0x00c
+#define MSPI_NEWQP_REG                         0x010
+#define MSPI_ENDQP_REG                         0x014
+#define MSPI_SPCR2_REG                         0x018
+#define MSPI_STATUS_REG                                0x020
+#define MSPI_CPTQP_REG                         0x024
+#define MSPI_TX_REG                            0x040
+#define MSPI_RX_REG                            0x0c0
+#define MSPI_CDRAM_REG                         0x140
+#define MSPI_WRITE_LOCK_REG                    0x180
+#define MSPI_DISABLE_FLUSH_GEN_REG             0x184
+
+/* BSPI registers */
+#define BSPI_REVISION_ID_REG                   0x000
+#define BSPI_SCRATCH_REG                       0x004
+#define BSPI_MAST_N_BOOT_CTRL_REG              0x008
+#define BSPI_BUSY_STATUS_REG                   0x00c
+#define BSPI_INTR_STATUS_REG                   0x010
+#define BSPI_B0_STATUS_REG                     0x014
+#define BSPI_B0_CTRL_REG                       0x018
+#define BSPI_B1_STATUS_REG                     0x01c
+#define BSPI_B1_CTRL_REG                       0x020
+#define BSPI_STRAP_OVERRIDE_CTRL_REG           0x024
+#define BSPI_FLEX_MODE_ENABLE_REG              0x028
+#define BSPI_BITS_PER_CYCLE_REG                        0x02C
+#define BSPI_BITS_PER_PHASE_REG                        0x030
+#define BSPI_CMD_AND_MODE_BYTE_REG             0x034
+#define BSPI_FLASH_UPPER_ADDR_BYTE_REG         0x038
+#define BSPI_XOR_VALUE_REG                     0x03C
+#define BSPI_XOR_ENABLE_REG                    0x040
+#define BSPI_PIO_MODE_ENABLE_REG               0x044
+#define BSPI_PIO_IODIR_REG                     0x048
+#define BSPI_PIO_DATA_REG                      0x04C
+
+/* RAF registers */
+#define BSPI_RAF_START_ADDRESS_REG             0x00
+#define BSPI_RAF_NUM_WORDS_REG                 0x04
+#define BSPI_RAF_CTRL_REG                      0x08
+#define BSPI_RAF_FULLNESS_REG                  0x0C
+#define BSPI_RAF_WATERMARK_REG                 0x10
+#define BSPI_RAF_STATUS_REG                    0x14
+#define BSPI_RAF_READ_DATA_REG                 0x18
+#define BSPI_RAF_WORD_CNT_REG                  0x1C
+#define BSPI_RAF_CURR_ADDR_REG                 0x20
+
+#define XFER_DUAL                              BIT(30)
+#define XFER_QUAD                              BIT(31)
+
+#define FLUSH_BIT                              BIT(0)
+#define MAST_N_BOOT_BIT                                BIT(0)
+#define WRITE_LOCK_BIT                         BIT(0)
+
+#define CEIL(m, n)                             (((m) + (n) - 1) / (n))
+#define UPPER_BYTE_MASK                                0xFF000000
+#define SIZE_16MB                              0x001000000
+
+/*
+ * struct bcmspi_priv - qspi private structure
+ *
+ * @bspi_addr: bspi read address
+ * @bspi_4byte_addr: bspi 4 byte address mode
+ * @mspi: mspi registers block address
+ * @bspi: bspi registers block address
+ * @bspi_raf: bspi raf registers block address
+ */
+struct bcmspi_priv {
+       u32 bspi_addr;
+       bool bspi_4byte_addr;
+       fdt_addr_t mspi;
+       fdt_addr_t bspi;
+       fdt_addr_t bspi_raf;
+};
+
+/* BSPI mode */
+
+static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
+{
+       writel(0, priv->bspi + BSPI_B0_CTRL_REG);
+       writel(0, priv->bspi + BSPI_B1_CTRL_REG);
+       writel(FLUSH_BIT, priv->bspi + BSPI_B0_CTRL_REG);
+       writel(FLUSH_BIT, priv->bspi + BSPI_B1_CTRL_REG);
+}
+
+static int bspi_enable(struct bcmspi_priv *priv)
+{
+       /* Disable write lock */
+       writel(0, priv->mspi + MSPI_WRITE_LOCK_REG);
+       /* Flush prefetch buffers */
+       bspi_flush_prefetch_buffers(priv);
+       /* Switch to BSPI */
+       writel(0, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
+
+       return 0;
+}
+
+static int bspi_disable(struct bcmspi_priv *priv)
+{
+       int ret;
+       uint val;
+
+       if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
+               ret = readl_poll_timeout(priv->bspi + BSPI_BUSY_STATUS_REG, val, !(val & 1),
+                                        BUSY_TIMEOUT_US);
+               if (ret) {
+                       printf("%s: Failed to disable bspi, device busy\n", __func__);
+                       return ret;
+               }
+
+               /* Switch to MSPI */
+               writel(MAST_N_BOOT_BIT, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
+               udelay(BUSY_DELAY_US);
+
+               val = readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
+               if (!(val & 1)) {
+                       printf("%s: Failed to enable mspi\n", __func__);
+                       return -EBUSY;
+               }
+       }
+
+       /* Enable write lock */
+       writel(WRITE_LOCK_BIT, priv->mspi + MSPI_WRITE_LOCK_REG);
+
+       return 0;
+}
+
+static int bspi_read_via_raf(struct bcmspi_priv *priv, u8 *rx, uint bytes)
+{
+       u32 status;
+       uint words;
+       int aligned;
+       int ret;
+
+       /*
+        * Flush data from the previous session (unlikely)
+        * Read outstanding bits in the poll condition to empty FIFO
+        */
+       ret = readl_poll_timeout(priv->bspi_raf + BSPI_RAF_STATUS_REG,
+                                status,
+                                (!readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG) &&
+                                 status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK) &&
+                                 !(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK),
+                                 BUSY_TIMEOUT_US);
+       if (ret) {
+               printf("%s: Failed to flush fifo\n", __func__);
+               return ret;
+       }
+
+       /* Transfer is in words */
+       words = CEIL(bytes, 4);
+
+       /* Setup hardware */
+       if (priv->bspi_4byte_addr) {
+               u32 val = priv->bspi_addr & UPPER_BYTE_MASK;
+
+               if (val != readl(priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG)) {
+                       writel(val, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
+                       bspi_flush_prefetch_buffers(priv);
+               }
+       }
+
+       writel(priv->bspi_addr & ~UPPER_BYTE_MASK, priv->bspi_raf + BSPI_RAF_START_ADDRESS_REG);
+       writel(words, priv->bspi_raf + BSPI_RAF_NUM_WORDS_REG);
+       writel(0, priv->bspi_raf + BSPI_RAF_WATERMARK_REG);
+
+       /* Start reading */
+       writel(BSPI_RAF_CONTROL_START_MASK, priv->bspi_raf + BSPI_RAF_CTRL_REG);
+       aligned = DWORD_ALIGNED(rx);
+       while (bytes) {
+               status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG);
+               if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
+                       /* RAF is LE only, convert data to host endianness */
+                       u32 data = le32_to_cpu(readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG));
+
+                       /* Check if we can use the whole word */
+                       if (aligned && bytes >= 4) {
+                               *(u32 *)rx = data;
+                               rx += 4;
+                               bytes -= 4;
+                       } else {
+                               uint chunk = min(bytes, 4U);
+
+                               /* Read out bytes one by one */
+                               while (chunk) {
+                                       *rx++ = (u8)data;
+                                       data >>= 8;
+                                       chunk--;
+                                       bytes--;
+                               }
+                       }
+
+                       continue;
+               }
+               if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK)) {
+                       /* FIFO is empty and the session is done */
+                       break;
+               }
+       }
+
+       return 0;
+}
+
+static int bspi_read(struct bcmspi_priv *priv, u8 *rx, uint bytes)
+{
+       int ret;
+
+       /* Transfer data */
+       while (bytes > 0) {
+               /* Special handing since RAF cannot go across 16MB boundary */
+               uint trans = bytes;
+               /* Divide into multiple transfers if it goes across the 16MB boundary */
+               if (priv->bspi_4byte_addr && (priv->bspi_addr >> 24) !=
+                   ((priv->bspi_addr + bytes) >> 24))
+                       trans = SIZE_16MB - (priv->bspi_addr & ~UPPER_BYTE_MASK);
+
+               ret = bspi_read_via_raf(priv, rx, trans);
+               if (ret)
+                       return ret;
+
+               priv->bspi_addr += trans;
+               rx += trans;
+               bytes -= trans;
+       }
+
+       bspi_flush_prefetch_buffers(priv);
+       return 0;
+}
+
+static void bspi_set_flex_mode(struct bcmspi_priv *priv, const struct spi_mem_op *op)
+{
+       int bpp = (op->dummy.nbytes * 8) / op->dummy.buswidth;
+       int cmd = op->cmd.opcode;
+       int bpc = ilog2(op->data.buswidth) << BSPI_BPC_DATA_SHIFT |
+                         ilog2(op->addr.buswidth) << BSPI_BPC_ADDR_SHIFT |
+                         ilog2(op->cmd.buswidth) << BSPI_BPC_CMD_SHIFT;
+       int so =  BIT(BSPI_STRAP_OVERRIDE_SHIFT) |
+                         (op->data.buswidth > 1) << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT |
+                         (op->addr.nbytes > 3) << BSPI_STRAP_OVERRIDE_4BYTE_SHIFT |
+                         (op->data.buswidth > 3) << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT;
+
+       /* Disable flex mode first */
+       writel(0, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
+
+       /* Configure single, dual or quad mode */
+       writel(bpc, priv->bspi + BSPI_BITS_PER_CYCLE_REG);
+
+       /* Opcode */
+       writel(cmd, priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG);
+
+       /* Count of dummy cycles */
+       writel(bpp, priv->bspi + BSPI_BITS_PER_PHASE_REG);
+
+       /* Enable 4-byte address */
+       if (priv->bspi_4byte_addr) {
+               setbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
+       } else {
+               clrbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
+               writel(0, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
+       }
+
+       /* Enable flex mode to take effect */
+       writel(1, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
+
+       /* Flush prefetch buffers since 32MB window BSPI could be used */
+       bspi_flush_prefetch_buffers(priv);
+
+       /* Override the strap settings */
+       writel(so, priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG);
+}
+
+static int bspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+       struct udevice *bus = dev_get_parent(slave->dev);
+       struct bcmspi_priv *priv = dev_get_priv(bus);
+       int ret = -ENOTSUPP;
+
+       /* BSPI read */
+       if (op->data.dir == SPI_MEM_DATA_IN &&
+           op->data.nbytes && op->addr.nbytes) {
+               priv->bspi_4byte_addr = (op->addr.nbytes > 3);
+               priv->bspi_addr = op->addr.val;
+               bspi_set_flex_mode(priv, op);
+               ret = bspi_read(priv, op->data.buf.in, op->data.nbytes);
+       }
+
+       return ret;
+}
+
+static const struct spi_controller_mem_ops bspi_mem_ops = {
+       .exec_op = bspi_exec_op,
+};
+
+/* MSPI mode */
+
+static int mspi_exec(struct bcmspi_priv *priv, uint bytes, const u8 *tx, u8 *rx, ulong flags)
+{
+       u32 cdr = CDRAM_PCS0 | CDRAM_CONT;
+       bool use_16bits = !(bytes & 1);
+
+       if (flags & XFER_QUAD) {
+               cdr |= CDRAM_QUAD_MODE;
+
+               if (!tx)
+                       cdr |= CDRAM_RBIT_INPUT;
+       }
+
+       while (bytes) {
+               uint chunk;
+               uint queues;
+               uint i;
+               uint val;
+               int ret;
+
+               if (use_16bits) {
+                       chunk = min(bytes, NUM_CDRAM * 2);
+                       queues = (chunk + 1) / 2;
+                       bytes -= chunk;
+
+                       /* Fill CDRAMs */
+                       for (i = 0; i < queues; i++)
+                               writel(cdr | CDRAM_BITS_EN, priv->mspi + MSPI_CDRAM_REG + 4 * i);
+
+                       /* Fill TXRAMs */
+                       for (i = 0; i < chunk; i++)
+                               writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 4 * i);
+               } else {
+                       /* Determine how many bytes to process this time */
+                       chunk = min(bytes, NUM_CDRAM);
+                       queues = chunk;
+                       bytes -= chunk;
+
+                       /* Fill CDRAMs and TXRAMS */
+                       for (i = 0; i < chunk; i++) {
+                               writel(cdr, priv->mspi + MSPI_CDRAM_REG + 4 * i);
+                               writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 8 * i);
+                       }
+               }
+
+               /* Setup queue pointers */
+               writel(0, priv->mspi + MSPI_NEWQP_REG);
+               writel(queues - 1, priv->mspi + MSPI_ENDQP_REG);
+
+               /* Deassert CS if requested and it's the last transfer */
+               if (bytes == 0 && (flags & SPI_XFER_END))
+                       clrbits_le32(priv->mspi + MSPI_CDRAM_REG + ((queues - 1) << 2), CDRAM_CONT);
+
+               /* Kick off */
+               writel(0, priv->mspi + MSPI_STATUS_REG);
+               if (bytes == 0 && (flags & SPI_XFER_END))
+                       writel(MSPI_SPE, priv->mspi + MSPI_SPCR2_REG);
+               else
+                       writel(MSPI_SPE | MSPI_CONT_AFTER_CMD,
+                              priv->mspi + MSPI_SPCR2_REG);
+
+               ret = readl_poll_timeout(priv->mspi + MSPI_STATUS_REG, val, (val & 1),
+                                        BUSY_TIMEOUT_US);
+               if (ret) {
+                       printf("%s: Failed to disable bspi, device busy\n", __func__);
+                       return ret;
+               }
+
+               /* Read data out */
+               if (rx) {
+                       if (use_16bits) {
+                               for (i = 0; i < chunk; i++)
+                                       rx[i] = readl(priv->mspi + MSPI_RX_REG + 4 * i) & 0xff;
+                       } else {
+                               for (i = 0; i < chunk; i++)
+                                       rx[i] = readl(priv->mspi + MSPI_RX_REG + 8 * i + 4) & 0xff;
+                       }
+               }
+
+               /* Advance pointers */
+               if (tx)
+                       tx += chunk;
+               if (rx)
+                       rx += chunk;
+       }
+
+       return 0;
+}
+
+static int mspi_xfer(struct udevice *dev, uint bitlen, const void *dout, void *din, ulong flags)
+{
+       struct udevice *bus = dev_get_parent(dev);
+       struct bcmspi_priv *priv = dev_get_priv(bus);
+       uint bytes;
+       int ret = 0;
+
+       /* we can only transfer multiples of 8 bits */
+       if (bitlen % 8)
+               return -EPROTONOSUPPORT;
+
+       bytes = bitlen / 8;
+
+       if (flags & SPI_XFER_BEGIN) {
+               /* Switch to MSPI */
+               ret = bspi_disable(priv);
+               if (ret)
+                       return ret;
+       }
+
+       /* MSPI: Transfer */
+       if (bytes)
+               ret = mspi_exec(priv, bytes, dout, din, flags);
+
+       if (flags & SPI_XFER_END) {
+               /* Switch back to BSPI */
+               ret = bspi_enable(priv);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
+/* iProc interface */
+
+static int iproc_qspi_set_speed(struct udevice *bus, uint speed)
+{
+       struct bcmspi_priv *priv = dev_get_priv(bus);
+       uint spbr;
+
+       /* MSPI: SCK configuration */
+       spbr = (QSPI_AXI_CLK - 1) / (2 * speed) + 1;
+       writel(max(min(spbr, SPBR_MAX), SPBR_MIN), priv->mspi + MSPI_SPCR0_LSB_REG);
+
+       return 0;
+}
+
+static int iproc_qspi_set_mode(struct udevice *bus, uint mode)
+{
+       struct bcmspi_priv *priv = dev_get_priv(bus);
+
+       /* MSPI: set master bit and mode */
+       writel(MSPI_MSTR /* Master */ | (mode & 3), priv->mspi + MSPI_SPCR0_MSB_REG);
+
+       return 0;
+}
+
+static int iproc_qspi_claim_bus(struct udevice *dev)
+{
+       /* Nothing to do */
+       return 0;
+}
+
+static int iproc_qspi_release_bus(struct udevice *dev)
+{
+       struct udevice *bus = dev_get_parent(dev);
+       struct bcmspi_priv *priv = dev_get_priv(bus);
+
+       /* Make sure no operation is in progress */
+       writel(0, priv->mspi + MSPI_SPCR2_REG);
+       udelay(BUSY_DELAY_US);
+
+       return 0;
+}
+
+static int iproc_qspi_of_to_plat(struct udevice *bus)
+{
+       struct bcmspi_priv *priv = dev_get_priv(bus);
+
+       priv->bspi = dev_read_addr_name(bus, "bspi");
+       if (IS_ERR((void *)priv->bspi)) {
+               printf("%s: Failed to get bspi base address\n", __func__);
+               return PTR_ERR((void *)priv->bspi);
+       }
+
+       priv->bspi_raf = dev_read_addr_name(bus, "bspi_raf");
+       if (IS_ERR((void *)priv->bspi_raf)) {
+               printf("%s: Failed to get bspi_raf base address\n", __func__);
+               return PTR_ERR((void *)priv->bspi_raf);
+       }
+
+       priv->mspi = dev_read_addr_name(bus, "mspi");
+       if (IS_ERR((void *)priv->mspi)) {
+               printf("%s: Failed to get mspi base address\n", __func__);
+               return PTR_ERR((void *)priv->mspi);
+       }
+
+       return 0;
+}
+
+static int iproc_qspi_probe(struct udevice *bus)
+{
+       struct bcmspi_priv *priv = dev_get_priv(bus);
+
+       /* configure mspi */
+       writel(0, priv->mspi + MSPI_SPCR1_LSB_REG);
+       writel(0, priv->mspi + MSPI_SPCR1_MSB_REG);
+       writel(0, priv->mspi + MSPI_NEWQP_REG);
+       writel(0, priv->mspi + MSPI_ENDQP_REG);
+       writel(0, priv->mspi + MSPI_SPCR2_REG);
+
+       /* configure bspi */
+       bspi_enable(priv);
+
+       return 0;
+}
+
+static const struct dm_spi_ops iproc_qspi_ops = {
+       .claim_bus      = iproc_qspi_claim_bus,
+       .release_bus    = iproc_qspi_release_bus,
+       .xfer           = mspi_xfer,
+       .set_speed      = iproc_qspi_set_speed,
+       .set_mode       = iproc_qspi_set_mode,
+       .mem_ops        = &bspi_mem_ops,
+};
+
+static const struct udevice_id iproc_qspi_ids[] = {
+       { .compatible = "brcm,iproc-qspi" },
+       { }
+};
+
+U_BOOT_DRIVER(iproc_qspi) = {
+       .name   = "iproc_qspi",
+       .id     = UCLASS_SPI,
+       .of_match = iproc_qspi_ids,
+       .ops    = &iproc_qspi_ops,
+       .of_to_plat = iproc_qspi_of_to_plat,
+       .priv_auto = sizeof(struct bcmspi_priv),
+       .probe  = iproc_qspi_probe,
+};
index f90f0ca..5b614cf 100644 (file)
@@ -129,7 +129,8 @@ config WDT_AT91
 config WDT_BCM6345
        bool "BCM6345 watchdog timer support"
        depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \
-                          ARCH_BCM6858 || ARCH_BCM63158)
+                          ARCH_BCM6858 || ARCH_BCM63158 || \
+                          ARCH_BCM6753)
        help
          Select this to enable watchdog timer for BCM6345 SoCs.
          The watchdog timer is stopped when initialized.
index 2e119b9..bacebbc 100644 (file)
@@ -58,13 +58,11 @@ static void counter_disable(struct a37xx_wdt *priv, int id)
        clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
 }
 
-static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
+static void init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
 {
        u32 reg;
 
        reg = readl(priv->reg + CNTR_CTRL(id));
-       if (reg & CNTR_CTRL_ACTIVE)
-               return -EBUSY;
 
        reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
                 CNTR_CTRL_TRIG_SRC_MASK);
@@ -79,8 +77,6 @@ static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
        reg |= trig_src;
 
        writel(reg, priv->reg + CNTR_CTRL(id));
-
-       return 0;
 }
 
 static int a37xx_wdt_reset(struct udevice *dev)
@@ -116,16 +112,9 @@ static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)
 static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
 {
        struct a37xx_wdt *priv = dev_get_priv(dev);
-       int err;
-
-       err = init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
-       if (err < 0)
-               return err;
 
-       err = init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG,
-                          CNTR_CTRL_TRIG_SRC_PREV_CNTR);
-       if (err < 0)
-               return err;
+       init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
+       init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG, CNTR_CTRL_TRIG_SRC_PREV_CNTR);
 
        priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
 
index 253286d..8d93f19 100644 (file)
@@ -41,7 +41,7 @@
 
 struct rti_wdt_priv {
        phys_addr_t regs;
-       unsigned int clk_khz;
+       unsigned int clk_hz;
 };
 
 #ifdef CONFIG_WDT_K3_RTI_LOAD_FW
@@ -139,7 +139,7 @@ static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
        if (ret < 0)
                return ret;
 
-       timer_margin = timeout_ms * priv->clk_khz / 1000;
+       timer_margin = timeout_ms * priv->clk_hz / 1000;
        timer_margin >>= WDT_PRELOAD_SHIFT;
        if (timer_margin > WDT_PRELOAD_MAX)
                timer_margin = WDT_PRELOAD_MAX;
@@ -185,7 +185,15 @@ static int rti_wdt_probe(struct udevice *dev)
        if (ret)
                return ret;
 
-       priv->clk_khz = clk_get_rate(&clk);
+       priv->clk_hz = clk_get_rate(&clk);
+
+       /*
+        * If watchdog is running at 32k clock, it is not accurate.
+        * Adjust frequency down in this case so that it does not expire
+        * earlier than expected.
+        */
+       if (priv->clk_hz < 32768)
+               priv->clk_hz = priv->clk_hz * 9 / 10;
 
        return 0;
 }
index 6d0f473..dbf5564 100644 (file)
@@ -36,6 +36,8 @@ struct wdt_priv {
        ulong next_reset;
        /* Whether watchdog_start() has been called on the device. */
        bool running;
+       /* No autostart */
+       bool noautostart;
 };
 
 static void init_watchdog_dev(struct udevice *dev)
@@ -52,7 +54,7 @@ static void init_watchdog_dev(struct udevice *dev)
                               dev->name);
        }
 
-       if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) {
+       if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART) || priv->noautostart) {
                printf("WDT:   Not starting %s\n", dev->name);
                return;
        }
@@ -256,16 +258,19 @@ static int wdt_pre_probe(struct udevice *dev)
         * indicated by a hw_margin_ms property.
         */
        ulong reset_period = 1000;
+       bool noautostart = false;
        struct wdt_priv *priv;
 
        if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
                timeout = dev_read_u32_default(dev, "timeout-sec", timeout);
                reset_period = dev_read_u32_default(dev, "hw_margin_ms",
                                                    4 * reset_period) / 4;
+               noautostart = dev_read_bool(dev, "u-boot,noautostart");
        }
        priv = dev_get_uclass_priv(dev);
        priv->timeout = timeout;
        priv->reset_period = reset_period;
+       priv->noautostart = noautostart;
        /*
         * Pretend this device was last reset "long" ago so the first
         * watchdog_reset will actually call its ->reset method.
index 6dc8d8d..443f2f7 100644 (file)
@@ -320,6 +320,7 @@ config ENV_IS_IN_SPI_FLASH
        default y if NORTHBRIDGE_INTEL_IVYBRIDGE
        default y if INTEL_QUARK
        default y if INTEL_QUEENSBAY
+       default y if ARCH_SUNXI
        help
          Define this if you have a SPI Flash memory device which you
          want to use for the environment.
@@ -536,7 +537,7 @@ config ENV_OFFSET
                    ENV_IS_IN_SPI_FLASH
        default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
        default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
-       default 0x88000 if ARCH_SUNXI
+       default 0xF0000 if ARCH_SUNXI
        default 0xE0000 if ARCH_ZYNQ
        default 0x1E00000 if ARCH_ZYNQMP
        default 0x7F40000 if ARCH_VERSAL
@@ -559,7 +560,8 @@ config ENV_OFFSET_REDUND
 config ENV_SIZE
        hex "Environment Size"
        default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
-       default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
+       default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
+       default 0x10000 if ARCH_SUNXI
        default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
        default 0x2000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
        default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL
@@ -575,6 +577,7 @@ config ENV_SECT_SIZE
        default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL
        default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
        default 0x20000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH
+       default 0x10000 if ARCH_SUNXI && ENV_IS_IN_SPI_FLASH
        help
          Size of the sector containing the environment.
 
@@ -819,6 +822,19 @@ config TPL_ENV_IS_IN_FLASH
 
 endif
 
+config USE_BOOTFILE
+       bool "Add a 'bootfile' environment variable"
+       help
+         The "bootfile" variable is used in some cases to allow for
+         controlling what file U-Boot will attempt to load and boot.  To set
+         this, enable this option and set the value in the next question.
+
+config BOOTFILE
+       string "'bootfile' environment variable value"
+       depends on USE_BOOTFILE
+       help
+         The value to set the "bootfile" variable to.
+
 config VERSION_VARIABLE
        bool "Add a 'ver' environment variable with the U-Boot version"
        help
index 620af7f..cda9f66 100644 (file)
@@ -24,4 +24,6 @@ source "fs/yaffs2/Kconfig"
 
 source "fs/squashfs/Kconfig"
 
+source "fs/erofs/Kconfig"
+
 endmenu
index 937cbcf..f05a21c 100644 (file)
@@ -25,5 +25,6 @@ obj-$(CONFIG_CMD_UBIFS) += ubifs/
 obj-$(CONFIG_YAFFS2) += yaffs2/
 obj-$(CONFIG_CMD_ZFS) += zfs/
 obj-$(CONFIG_FS_SQUASHFS) += squashfs/
+obj-$(CONFIG_FS_EROFS) += erofs/
 endif
 obj-y += fs_internal.o
diff --git a/fs/erofs/Kconfig b/fs/erofs/Kconfig
new file mode 100644 (file)
index 0000000..ee4e777
--- /dev/null
@@ -0,0 +1,21 @@
+config FS_EROFS
+       bool "Enable EROFS filesystem support"
+       help
+         This provides support for reading images from EROFS filesystem.
+         EROFS (Enhanced Read-Only File System) is a lightweight read-only
+         file system for scenarios which need high-performance read-only
+         requirements.
+
+         It also provides fixed-sized output compression support, which
+         improves storage density, keeps relatively higher compression
+         ratios, which is more useful to achieve high performance for
+         embedded devices with limited memory.
+
+config FS_EROFS_ZIP
+       bool "EROFS Data Compression Support"
+       depends on FS_EROFS
+       select LZ4
+       default y
+       help
+         Enable fixed-sized output compression for EROFS.
+         If you don't want to enable compression feature, say N.
diff --git a/fs/erofs/Makefile b/fs/erofs/Makefile
new file mode 100644 (file)
index 0000000..58af6a6
--- /dev/null
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_$(SPL_)FS_EROFS) = fs.o \
+                               super.o \
+                               namei.o \
+                               data.o \
+                               decompress.o \
+                               zmap.o
diff --git a/fs/erofs/data.c b/fs/erofs/data.c
new file mode 100644 (file)
index 0000000..7618960
--- /dev/null
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "internal.h"
+#include "decompress.h"
+
+static int erofs_map_blocks_flatmode(struct erofs_inode *inode,
+                                    struct erofs_map_blocks *map,
+                                    int flags)
+{
+       int err = 0;
+       erofs_blk_t nblocks, lastblk;
+       u64 offset = map->m_la;
+       struct erofs_inode *vi = inode;
+       bool tailendpacking = (vi->datalayout == EROFS_INODE_FLAT_INLINE);
+
+       nblocks = DIV_ROUND_UP(inode->i_size, EROFS_BLKSIZ);
+       lastblk = nblocks - tailendpacking;
+
+       /* there is no hole in flatmode */
+       map->m_flags = EROFS_MAP_MAPPED;
+
+       if (offset < blknr_to_addr(lastblk)) {
+               map->m_pa = blknr_to_addr(vi->u.i_blkaddr) + map->m_la;
+               map->m_plen = blknr_to_addr(lastblk) - offset;
+       } else if (tailendpacking) {
+               /* 2 - inode inline B: inode, [xattrs], inline last blk... */
+               map->m_pa = iloc(vi->nid) + vi->inode_isize +
+                       vi->xattr_isize + erofs_blkoff(map->m_la);
+               map->m_plen = inode->i_size - offset;
+
+               /* inline data should be located in one meta block */
+               if (erofs_blkoff(map->m_pa) + map->m_plen > PAGE_SIZE) {
+                       erofs_err("inline data cross block boundary @ nid %" PRIu64,
+                                 vi->nid);
+                       DBG_BUGON(1);
+                       err = -EFSCORRUPTED;
+                       goto err_out;
+               }
+
+               map->m_flags |= EROFS_MAP_META;
+       } else {
+               erofs_err("internal error @ nid: %" PRIu64 " (size %llu), m_la 0x%" PRIx64,
+                         vi->nid, (unsigned long long)inode->i_size, map->m_la);
+               DBG_BUGON(1);
+               err = -EIO;
+               goto err_out;
+       }
+
+       map->m_llen = map->m_plen;
+err_out:
+       return err;
+}
+
+int erofs_map_blocks(struct erofs_inode *inode,
+                    struct erofs_map_blocks *map, int flags)
+{
+       struct erofs_inode *vi = inode;
+       struct erofs_inode_chunk_index *idx;
+       u8 buf[EROFS_BLKSIZ];
+       u64 chunknr;
+       unsigned int unit;
+       erofs_off_t pos;
+       int err = 0;
+
+       map->m_deviceid = 0;
+       if (map->m_la >= inode->i_size) {
+               /* leave out-of-bound access unmapped */
+               map->m_flags = 0;
+               map->m_plen = 0;
+               goto out;
+       }
+
+       if (vi->datalayout != EROFS_INODE_CHUNK_BASED)
+               return erofs_map_blocks_flatmode(inode, map, flags);
+
+       if (vi->u.chunkformat & EROFS_CHUNK_FORMAT_INDEXES)
+               unit = sizeof(*idx);                    /* chunk index */
+       else
+               unit = EROFS_BLOCK_MAP_ENTRY_SIZE;      /* block map */
+
+       chunknr = map->m_la >> vi->u.chunkbits;
+       pos = roundup(iloc(vi->nid) + vi->inode_isize +
+                     vi->xattr_isize, unit) + unit * chunknr;
+
+       err = erofs_blk_read(buf, erofs_blknr(pos), 1);
+       if (err < 0)
+               return -EIO;
+
+       map->m_la = chunknr << vi->u.chunkbits;
+       map->m_plen = min_t(erofs_off_t, 1UL << vi->u.chunkbits,
+                           roundup(inode->i_size - map->m_la, EROFS_BLKSIZ));
+
+       /* handle block map */
+       if (!(vi->u.chunkformat & EROFS_CHUNK_FORMAT_INDEXES)) {
+               __le32 *blkaddr = (void *)buf + erofs_blkoff(pos);
+
+               if (le32_to_cpu(*blkaddr) == EROFS_NULL_ADDR) {
+                       map->m_flags = 0;
+               } else {
+                       map->m_pa = blknr_to_addr(le32_to_cpu(*blkaddr));
+                       map->m_flags = EROFS_MAP_MAPPED;
+               }
+               goto out;
+       }
+       /* parse chunk indexes */
+       idx = (void *)buf + erofs_blkoff(pos);
+       switch (le32_to_cpu(idx->blkaddr)) {
+       case EROFS_NULL_ADDR:
+               map->m_flags = 0;
+               break;
+       default:
+               map->m_deviceid = le16_to_cpu(idx->device_id) &
+                       sbi.device_id_mask;
+               map->m_pa = blknr_to_addr(le32_to_cpu(idx->blkaddr));
+               map->m_flags = EROFS_MAP_MAPPED;
+               break;
+       }
+out:
+       map->m_llen = map->m_plen;
+       return err;
+}
+
+int erofs_map_dev(struct erofs_sb_info *sbi, struct erofs_map_dev *map)
+{
+       struct erofs_device_info *dif;
+       int id;
+
+       if (map->m_deviceid) {
+               if (sbi->extra_devices < map->m_deviceid)
+                       return -ENODEV;
+       } else if (sbi->extra_devices) {
+               for (id = 0; id < sbi->extra_devices; ++id) {
+                       erofs_off_t startoff, length;
+
+                       dif = sbi->devs + id;
+                       if (!dif->mapped_blkaddr)
+                               continue;
+                       startoff = blknr_to_addr(dif->mapped_blkaddr);
+                       length = blknr_to_addr(dif->blocks);
+
+                       if (map->m_pa >= startoff &&
+                           map->m_pa < startoff + length) {
+                               map->m_pa -= startoff;
+                               break;
+                       }
+               }
+       }
+       return 0;
+}
+
+static int erofs_read_raw_data(struct erofs_inode *inode, char *buffer,
+                              erofs_off_t size, erofs_off_t offset)
+{
+       struct erofs_map_blocks map = {
+               .index = UINT_MAX,
+       };
+       struct erofs_map_dev mdev;
+       int ret;
+       erofs_off_t ptr = offset;
+
+       while (ptr < offset + size) {
+               char *const estart = buffer + ptr - offset;
+               erofs_off_t eend;
+
+               map.m_la = ptr;
+               ret = erofs_map_blocks(inode, &map, 0);
+               if (ret)
+                       return ret;
+
+               DBG_BUGON(map.m_plen != map.m_llen);
+
+               mdev = (struct erofs_map_dev) {
+                       .m_deviceid = map.m_deviceid,
+                       .m_pa = map.m_pa,
+               };
+               ret = erofs_map_dev(&sbi, &mdev);
+               if (ret)
+                       return ret;
+
+               /* trim extent */
+               eend = min(offset + size, map.m_la + map.m_llen);
+               DBG_BUGON(ptr < map.m_la);
+
+               if (!(map.m_flags & EROFS_MAP_MAPPED)) {
+                       if (!map.m_llen) {
+                               /* reached EOF */
+                               memset(estart, 0, offset + size - ptr);
+                               ptr = offset + size;
+                               continue;
+                       }
+                       memset(estart, 0, eend - ptr);
+                       ptr = eend;
+                       continue;
+               }
+
+               if (ptr > map.m_la) {
+                       mdev.m_pa += ptr - map.m_la;
+                       map.m_la = ptr;
+               }
+
+               ret = erofs_dev_read(mdev.m_deviceid, estart, mdev.m_pa,
+                                    eend - map.m_la);
+               if (ret < 0)
+                       return -EIO;
+               ptr = eend;
+       }
+       return 0;
+}
+
+static int z_erofs_read_data(struct erofs_inode *inode, char *buffer,
+                            erofs_off_t size, erofs_off_t offset)
+{
+       erofs_off_t end, length, skip;
+       struct erofs_map_blocks map = {
+               .index = UINT_MAX,
+       };
+       struct erofs_map_dev mdev;
+       bool partial;
+       unsigned int bufsize = 0;
+       char *raw = NULL;
+       int ret = 0;
+
+       end = offset + size;
+       while (end > offset) {
+               map.m_la = end - 1;
+
+               ret = z_erofs_map_blocks_iter(inode, &map, 0);
+               if (ret)
+                       break;
+
+               /* no device id here, thus it will always succeed */
+               mdev = (struct erofs_map_dev) {
+                       .m_pa = map.m_pa,
+               };
+               ret = erofs_map_dev(&sbi, &mdev);
+               if (ret) {
+                       DBG_BUGON(1);
+                       break;
+               }
+
+               /*
+                * trim to the needed size if the returned extent is quite
+                * larger than requested, and set up partial flag as well.
+                */
+               if (end < map.m_la + map.m_llen) {
+                       length = end - map.m_la;
+                       partial = true;
+               } else {
+                       DBG_BUGON(end != map.m_la + map.m_llen);
+                       length = map.m_llen;
+                       partial = !(map.m_flags & EROFS_MAP_FULL_MAPPED);
+               }
+
+               if (map.m_la < offset) {
+                       skip = offset - map.m_la;
+                       end = offset;
+               } else {
+                       skip = 0;
+                       end = map.m_la;
+               }
+
+               if (!(map.m_flags & EROFS_MAP_MAPPED)) {
+                       memset(buffer + end - offset, 0, length);
+                       end = map.m_la;
+                       continue;
+               }
+
+               if (map.m_plen > bufsize) {
+                       bufsize = map.m_plen;
+                       raw = realloc(raw, bufsize);
+                       if (!raw) {
+                               ret = -ENOMEM;
+                               break;
+                       }
+               }
+               ret = erofs_dev_read(mdev.m_deviceid, raw, mdev.m_pa, map.m_plen);
+               if (ret < 0)
+                       break;
+
+               ret = z_erofs_decompress(&(struct z_erofs_decompress_req) {
+                                       .in = raw,
+                                       .out = buffer + end - offset,
+                                       .decodedskip = skip,
+                                       .inputsize = map.m_plen,
+                                       .decodedlength = length,
+                                       .alg = map.m_algorithmformat,
+                                       .partial_decoding = partial
+                                        });
+               if (ret < 0)
+                       break;
+       }
+       if (raw)
+               free(raw);
+       return ret < 0 ? ret : 0;
+}
+
+int erofs_pread(struct erofs_inode *inode, char *buf,
+               erofs_off_t count, erofs_off_t offset)
+{
+       switch (inode->datalayout) {
+       case EROFS_INODE_FLAT_PLAIN:
+       case EROFS_INODE_FLAT_INLINE:
+       case EROFS_INODE_CHUNK_BASED:
+               return erofs_read_raw_data(inode, buf, count, offset);
+       case EROFS_INODE_FLAT_COMPRESSION_LEGACY:
+       case EROFS_INODE_FLAT_COMPRESSION:
+               return z_erofs_read_data(inode, buf, count, offset);
+       default:
+               break;
+       }
+       return -EINVAL;
+}
diff --git a/fs/erofs/decompress.c b/fs/erofs/decompress.c
new file mode 100644 (file)
index 0000000..2be3b84
--- /dev/null
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "decompress.h"
+
+#if IS_ENABLED(CONFIG_LZ4)
+#include <u-boot/lz4.h>
+static int z_erofs_decompress_lz4(struct z_erofs_decompress_req *rq)
+{
+       int ret = 0;
+       char *dest = rq->out;
+       char *src = rq->in;
+       char *buff = NULL;
+       bool support_0padding = false;
+       unsigned int inputmargin = 0;
+
+       if (erofs_sb_has_lz4_0padding()) {
+               support_0padding = true;
+
+               while (!src[inputmargin & ~PAGE_MASK])
+                       if (!(++inputmargin & ~PAGE_MASK))
+                               break;
+
+               if (inputmargin >= rq->inputsize)
+                       return -EIO;
+       }
+
+       if (rq->decodedskip) {
+               buff = malloc(rq->decodedlength);
+               if (!buff)
+                       return -ENOMEM;
+               dest = buff;
+       }
+
+       if (rq->partial_decoding || !support_0padding)
+               ret = LZ4_decompress_safe_partial(src + inputmargin, dest,
+                                                 rq->inputsize - inputmargin,
+                                                 rq->decodedlength, rq->decodedlength);
+       else
+               ret = LZ4_decompress_safe(src + inputmargin, dest,
+                                         rq->inputsize - inputmargin,
+                                         rq->decodedlength);
+
+       if (ret != (int)rq->decodedlength) {
+               ret = -EIO;
+               goto out;
+       }
+
+       if (rq->decodedskip)
+               memcpy(rq->out, dest + rq->decodedskip,
+                      rq->decodedlength - rq->decodedskip);
+
+out:
+       if (buff)
+               free(buff);
+
+       return ret;
+}
+#endif
+
+int z_erofs_decompress(struct z_erofs_decompress_req *rq)
+{
+       if (rq->alg == Z_EROFS_COMPRESSION_SHIFTED) {
+               if (rq->inputsize != EROFS_BLKSIZ)
+                       return -EFSCORRUPTED;
+
+               DBG_BUGON(rq->decodedlength > EROFS_BLKSIZ);
+               DBG_BUGON(rq->decodedlength < rq->decodedskip);
+
+               memcpy(rq->out, rq->in + rq->decodedskip,
+                      rq->decodedlength - rq->decodedskip);
+               return 0;
+       }
+
+#if IS_ENABLED(CONFIG_LZ4)
+       if (rq->alg == Z_EROFS_COMPRESSION_LZ4)
+               return z_erofs_decompress_lz4(rq);
+#endif
+       return -EOPNOTSUPP;
+}
diff --git a/fs/erofs/decompress.h b/fs/erofs/decompress.h
new file mode 100644 (file)
index 0000000..81d5fb8
--- /dev/null
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __EROFS_DECOMPRESS_H
+#define __EROFS_DECOMPRESS_H
+
+#include "internal.h"
+
+struct z_erofs_decompress_req {
+       char *in, *out;
+
+       /*
+        * initial decompressed bytes that need to be skipped
+        * when finally copying to output buffer
+        */
+       unsigned int decodedskip;
+       unsigned int inputsize, decodedlength;
+
+       /* indicate the algorithm will be used for decompression */
+       unsigned int alg;
+       bool partial_decoding;
+};
+
+int z_erofs_decompress(struct z_erofs_decompress_req *rq);
+
+#endif
diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h
new file mode 100644 (file)
index 0000000..6b62c7a
--- /dev/null
@@ -0,0 +1,436 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR Apache-2.0 */
+/*
+ * EROFS (Enhanced ROM File System) on-disk format definition
+ *
+ * Copyright (C) 2017-2018 HUAWEI, Inc.
+ *             http://www.huawei.com/
+ * Copyright (C) 2021, Alibaba Cloud
+ */
+#ifndef __EROFS_FS_H
+#define __EROFS_FS_H
+
+#include <asm/unaligned.h>
+#include <fs.h>
+#include <part.h>
+#include <stdint.h>
+#include <compiler.h>
+
+#define EROFS_SUPER_MAGIC_V1    0xE0F5E1E2
+#define EROFS_SUPER_OFFSET      1024
+
+#define EROFS_FEATURE_COMPAT_SB_CHKSUM         0x00000001
+
+/*
+ * Any bits that aren't in EROFS_ALL_FEATURE_INCOMPAT should
+ * be incompatible with this kernel version.
+ */
+#define EROFS_FEATURE_INCOMPAT_LZ4_0PADDING    0x00000001
+#define EROFS_FEATURE_INCOMPAT_COMPR_CFGS      0x00000002
+#define EROFS_FEATURE_INCOMPAT_BIG_PCLUSTER    0x00000002
+#define EROFS_FEATURE_INCOMPAT_CHUNKED_FILE    0x00000004
+#define EROFS_FEATURE_INCOMPAT_DEVICE_TABLE    0x00000008
+#define EROFS_ALL_FEATURE_INCOMPAT             \
+       (EROFS_FEATURE_INCOMPAT_LZ4_0PADDING | \
+        EROFS_FEATURE_INCOMPAT_COMPR_CFGS | \
+        EROFS_FEATURE_INCOMPAT_BIG_PCLUSTER | \
+        EROFS_FEATURE_INCOMPAT_CHUNKED_FILE | \
+        EROFS_FEATURE_INCOMPAT_DEVICE_TABLE)
+
+#define EROFS_SB_EXTSLOT_SIZE  16
+
+struct erofs_deviceslot {
+       union {
+               u8 uuid[16];            /* used for device manager later */
+               u8 userdata[64];        /* digest(sha256), etc. */
+       } u;
+       __le32 blocks;                  /* total fs blocks of this device */
+       __le32 mapped_blkaddr;          /* map starting at mapped_blkaddr */
+       u8 reserved[56];
+};
+
+#define EROFS_DEVT_SLOT_SIZE   sizeof(struct erofs_deviceslot)
+
+/* erofs on-disk super block (currently 128 bytes) */
+struct erofs_super_block {
+       __le32 magic;           /* file system magic number */
+       __le32 checksum;        /* crc32c(super_block) */
+       __le32 feature_compat;
+       __u8 blkszbits;         /* support block_size == PAGE_SIZE only */
+       __u8 sb_extslots;       /* superblock size = 128 + sb_extslots * 16 */
+
+       __le16 root_nid;        /* nid of root directory */
+       __le64 inos;            /* total valid ino # (== f_files - f_favail) */
+
+       __le64 build_time;      /* inode v1 time derivation */
+       __le32 build_time_nsec; /* inode v1 time derivation in nano scale */
+       __le32 blocks;          /* used for statfs */
+       __le32 meta_blkaddr;    /* start block address of metadata area */
+       __le32 xattr_blkaddr;   /* start block address of shared xattr area */
+       __u8 uuid[16];          /* 128-bit uuid for volume */
+       __u8 volume_name[16];   /* volume name */
+       __le32 feature_incompat;
+       union {
+               /* bitmap for available compression algorithms */
+               __le16 available_compr_algs;
+               /* customized sliding window size instead of 64k by default */
+               __le16 lz4_max_distance;
+       } __packed u1;
+       __le16 extra_devices;   /* # of devices besides the primary device */
+       __le16 devt_slotoff;    /* startoff = devt_slotoff * devt_slotsize */
+       __u8 reserved2[38];
+};
+
+/*
+ * erofs inode datalayout (i_format in on-disk inode):
+ * 0 - inode plain without inline data A:
+ * inode, [xattrs], ... | ... | no-holed data
+ * 1 - inode VLE compression B (legacy):
+ * inode, [xattrs], extents ... | ...
+ * 2 - inode plain with inline data C:
+ * inode, [xattrs], last_inline_data, ... | ... | no-holed data
+ * 3 - inode compression D:
+ * inode, [xattrs], map_header, extents ... | ...
+ * 4 - inode chunk-based E:
+ * inode, [xattrs], chunk indexes ... | ...
+ * 5~7 - reserved
+ */
+enum {
+       EROFS_INODE_FLAT_PLAIN                  = 0,
+       EROFS_INODE_FLAT_COMPRESSION_LEGACY     = 1,
+       EROFS_INODE_FLAT_INLINE                 = 2,
+       EROFS_INODE_FLAT_COMPRESSION            = 3,
+       EROFS_INODE_CHUNK_BASED                 = 4,
+       EROFS_INODE_DATALAYOUT_MAX
+};
+
+static inline bool erofs_inode_is_data_compressed(unsigned int datamode)
+{
+       return datamode == EROFS_INODE_FLAT_COMPRESSION ||
+               datamode == EROFS_INODE_FLAT_COMPRESSION_LEGACY;
+}
+
+/* bit definitions of inode i_advise */
+#define EROFS_I_VERSION_BITS            1
+#define EROFS_I_DATALAYOUT_BITS         3
+
+#define EROFS_I_VERSION_BIT             0
+#define EROFS_I_DATALAYOUT_BIT          1
+
+#define EROFS_I_ALL    \
+       ((1 << (EROFS_I_DATALAYOUT_BIT + EROFS_I_DATALAYOUT_BITS)) - 1)
+
+/* indicate chunk blkbits, thus 'chunksize = blocksize << chunk blkbits' */
+#define EROFS_CHUNK_FORMAT_BLKBITS_MASK                0x001F
+/* with chunk indexes or just a 4-byte blkaddr array */
+#define EROFS_CHUNK_FORMAT_INDEXES             0x0020
+
+#define EROFS_CHUNK_FORMAT_ALL \
+       (EROFS_CHUNK_FORMAT_BLKBITS_MASK | EROFS_CHUNK_FORMAT_INDEXES)
+
+struct erofs_inode_chunk_info {
+       __le16 format;          /* chunk blkbits, etc. */
+       __le16 reserved;
+};
+
+/* 32-byte reduced form of an ondisk inode */
+struct erofs_inode_compact {
+       __le16 i_format;        /* inode format hints */
+
+/* 1 header + n-1 * 4 bytes inline xattr to keep continuity */
+       __le16 i_xattr_icount;
+       __le16 i_mode;
+       __le16 i_nlink;
+       __le32 i_size;
+       __le32 i_reserved;
+       union {
+               /* file total compressed blocks for data mapping 1 */
+               __le32 compressed_blocks;
+               __le32 raw_blkaddr;
+
+               /* for device files, used to indicate old/new device # */
+               __le32 rdev;
+
+               /* for chunk-based files, it contains the summary info */
+               struct erofs_inode_chunk_info c;
+       } i_u;
+       __le32 i_ino;           /* only used for 32-bit stat compatibility */
+       __le16 i_uid;
+       __le16 i_gid;
+       __le32 i_reserved2;
+};
+
+/* 32 bytes on-disk inode */
+#define EROFS_INODE_LAYOUT_COMPACT     0
+/* 64 bytes on-disk inode */
+#define EROFS_INODE_LAYOUT_EXTENDED    1
+
+/* 64-byte complete form of an ondisk inode */
+struct erofs_inode_extended {
+       __le16 i_format;        /* inode format hints */
+
+/* 1 header + n-1 * 4 bytes inline xattr to keep continuity */
+       __le16 i_xattr_icount;
+       __le16 i_mode;
+       __le16 i_reserved;
+       __le64 i_size;
+       union {
+               /* file total compressed blocks for data mapping 1 */
+               __le32 compressed_blocks;
+               __le32 raw_blkaddr;
+
+               /* for device files, used to indicate old/new device # */
+               __le32 rdev;
+
+               /* for chunk-based files, it contains the summary info */
+               struct erofs_inode_chunk_info c;
+       } i_u;
+
+       /* only used for 32-bit stat compatibility */
+       __le32 i_ino;
+
+       __le32 i_uid;
+       __le32 i_gid;
+       __le64 i_ctime;
+       __le32 i_ctime_nsec;
+       __le32 i_nlink;
+       __u8   i_reserved2[16];
+};
+
+#define EROFS_MAX_SHARED_XATTRS         (128)
+/* h_shared_count between 129 ... 255 are special # */
+#define EROFS_SHARED_XATTR_EXTENT       (255)
+
+/*
+ * inline xattrs (n == i_xattr_icount):
+ * erofs_xattr_ibody_header(1) + (n - 1) * 4 bytes
+ *          12 bytes           /                   \
+ *                            /                     \
+ *                           /-----------------------\
+ *                           |  erofs_xattr_entries+ |
+ *                           +-----------------------+
+ * inline xattrs must starts in erofs_xattr_ibody_header,
+ * for read-only fs, no need to introduce h_refcount
+ */
+struct erofs_xattr_ibody_header {
+       __le32 h_reserved;
+       __u8   h_shared_count;
+       __u8   h_reserved2[7];
+       __le32 h_shared_xattrs[0];      /* shared xattr id array */
+};
+
+/* Name indexes */
+#define EROFS_XATTR_INDEX_USER              1
+#define EROFS_XATTR_INDEX_POSIX_ACL_ACCESS  2
+#define EROFS_XATTR_INDEX_POSIX_ACL_DEFAULT 3
+#define EROFS_XATTR_INDEX_TRUSTED           4
+#define EROFS_XATTR_INDEX_LUSTRE            5
+#define EROFS_XATTR_INDEX_SECURITY          6
+
+/* xattr entry (for both inline & shared xattrs) */
+struct erofs_xattr_entry {
+       __u8   e_name_len;      /* length of name */
+       __u8   e_name_index;    /* attribute name index */
+       __le16 e_value_size;    /* size of attribute value */
+       /* followed by e_name and e_value */
+       char   e_name[0];       /* attribute name */
+};
+
+static inline unsigned int erofs_xattr_ibody_size(__le16 i_xattr_icount)
+{
+       if (!i_xattr_icount)
+               return 0;
+
+       return sizeof(struct erofs_xattr_ibody_header) +
+               sizeof(__u32) * (le16_to_cpu(i_xattr_icount) - 1);
+}
+
+#define EROFS_XATTR_ALIGN(size) round_up(size, sizeof(struct erofs_xattr_entry))
+
+static inline unsigned int erofs_xattr_entry_size(struct erofs_xattr_entry *e)
+{
+       return EROFS_XATTR_ALIGN(sizeof(struct erofs_xattr_entry) +
+                                e->e_name_len + le16_to_cpu(e->e_value_size));
+}
+
+/* represent a zeroed chunk (hole) */
+#define EROFS_NULL_ADDR                        -1
+
+/* 4-byte block address array */
+#define EROFS_BLOCK_MAP_ENTRY_SIZE     sizeof(__le32)
+
+/* 8-byte inode chunk indexes */
+struct erofs_inode_chunk_index {
+       __le16 advise;          /* always 0, don't care for now */
+       __le16 device_id;       /* back-end storage id (with bits masked) */
+       __le32 blkaddr;         /* start block address of this inode chunk */
+};
+
+/* maximum supported size of a physical compression cluster */
+#define Z_EROFS_PCLUSTER_MAX_SIZE      (1024 * 1024)
+
+/* available compression algorithm types (for h_algorithmtype) */
+enum {
+       Z_EROFS_COMPRESSION_LZ4         = 0,
+       Z_EROFS_COMPRESSION_LZMA        = 1,
+       Z_EROFS_COMPRESSION_MAX
+};
+
+#define Z_EROFS_ALL_COMPR_ALGS         (1 << (Z_EROFS_COMPRESSION_MAX - 1))
+
+/* 14 bytes (+ length field = 16 bytes) */
+struct z_erofs_lz4_cfgs {
+       __le16 max_distance;
+       __le16 max_pclusterblks;
+       u8 reserved[10];
+} __packed;
+
+/* 14 bytes (+ length field = 16 bytes) */
+struct z_erofs_lzma_cfgs {
+       __le32 dict_size;
+       __le16 format;
+       u8 reserved[8];
+} __packed;
+#define Z_EROFS_LZMA_MAX_DICT_SIZE     (8 * Z_EROFS_PCLUSTER_MAX_SIZE)
+
+/*
+ * bit 0 : COMPACTED_2B indexes (0 - off; 1 - on)
+ *  e.g. for 4k logical cluster size,      4B        if compacted 2B is off;
+ *                                  (4B) + 2B + (4B) if compacted 2B is on.
+ * bit 1 : HEAD1 big pcluster (0 - off; 1 - on)
+ * bit 2 : HEAD2 big pcluster (0 - off; 1 - on)
+ */
+#define Z_EROFS_ADVISE_COMPACTED_2B            0x0001
+#define Z_EROFS_ADVISE_BIG_PCLUSTER_1          0x0002
+#define Z_EROFS_ADVISE_BIG_PCLUSTER_2          0x0004
+
+struct z_erofs_map_header {
+       __le32  h_reserved1;
+       __le16  h_advise;
+       /*
+        * bit 0-3 : algorithm type of head 1 (logical cluster type 01);
+        * bit 4-7 : algorithm type of head 2 (logical cluster type 11).
+        */
+       __u8    h_algorithmtype;
+       /*
+        * bit 0-2 : logical cluster bits - 12, e.g. 0 for 4096;
+        * bit 3-7 : reserved.
+        */
+       __u8    h_clusterbits;
+};
+
+#define Z_EROFS_VLE_LEGACY_HEADER_PADDING       8
+
+/*
+ * Fixed-sized output compression ondisk Logical Extent cluster type:
+ *    0 - literal (uncompressed) cluster
+ *    1 - compressed cluster (for the head logical cluster)
+ *    2 - compressed cluster (for the other logical clusters)
+ *
+ * In detail,
+ *    0 - literal (uncompressed) cluster,
+ *        di_advise = 0
+ *        di_clusterofs = the literal data offset of the cluster
+ *        di_blkaddr = the blkaddr of the literal cluster
+ *
+ *    1 - compressed cluster (for the head logical cluster)
+ *        di_advise = 1
+ *        di_clusterofs = the decompressed data offset of the cluster
+ *        di_blkaddr = the blkaddr of the compressed cluster
+ *
+ *    2 - compressed cluster (for the other logical clusters)
+ *        di_advise = 2
+ *        di_clusterofs =
+ *           the decompressed data offset in its own head cluster
+ *        di_u.delta[0] = distance to its corresponding head cluster
+ *        di_u.delta[1] = distance to its corresponding tail cluster
+ *                (di_advise could be 0, 1 or 2)
+ */
+enum {
+       Z_EROFS_VLE_CLUSTER_TYPE_PLAIN          = 0,
+       Z_EROFS_VLE_CLUSTER_TYPE_HEAD           = 1,
+       Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD        = 2,
+       Z_EROFS_VLE_CLUSTER_TYPE_RESERVED       = 3,
+       Z_EROFS_VLE_CLUSTER_TYPE_MAX
+};
+
+#define Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS        2
+#define Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT         0
+
+/*
+ * D0_CBLKCNT will be marked _only_ at the 1st non-head lcluster to store the
+ * compressed block count of a compressed extent (in logical clusters, aka.
+ * block count of a pcluster).
+ */
+#define Z_EROFS_VLE_DI_D0_CBLKCNT              (1 << 11)
+
+struct z_erofs_vle_decompressed_index {
+       __le16 di_advise;
+       /* where to decompress in the head cluster */
+       __le16 di_clusterofs;
+
+       union {
+               /* for the head cluster */
+               __le32 blkaddr;
+               /*
+                * for the rest clusters
+                * eg. for 4k page-sized cluster, maximum 4K*64k = 256M)
+                * [0] - pointing to the head cluster
+                * [1] - pointing to the tail cluster
+                */
+               __le16 delta[2];
+       } di_u;
+};
+
+#define Z_EROFS_VLE_LEGACY_INDEX_ALIGN(size) \
+       (round_up(size, sizeof(struct z_erofs_vle_decompressed_index)) + \
+        sizeof(struct z_erofs_map_header) + Z_EROFS_VLE_LEGACY_HEADER_PADDING)
+
+#define Z_EROFS_VLE_EXTENT_ALIGN(size) round_up(size, \
+       sizeof(struct z_erofs_vle_decompressed_index))
+
+/* dirent sorts in alphabet order, thus we can do binary search */
+struct erofs_dirent {
+       __le64 nid;     /* node number */
+       __le16 nameoff; /* start offset of file name */
+       __u8 file_type; /* file type */
+       __u8 reserved;  /* reserved */
+} __packed;
+
+/* file types used in inode_info->flags */
+enum {
+       EROFS_FT_UNKNOWN,
+       EROFS_FT_REG_FILE,
+       EROFS_FT_DIR,
+       EROFS_FT_CHRDEV,
+       EROFS_FT_BLKDEV,
+       EROFS_FT_FIFO,
+       EROFS_FT_SOCK,
+       EROFS_FT_SYMLINK,
+       EROFS_FT_MAX
+};
+
+#define EROFS_NAME_LEN      255
+
+/* check the EROFS on-disk layout strictly at compile time */
+static inline void erofs_check_ondisk_layout_definitions(void)
+{
+       BUILD_BUG_ON(sizeof(struct erofs_super_block) != 128);
+       BUILD_BUG_ON(sizeof(struct erofs_inode_compact) != 32);
+       BUILD_BUG_ON(sizeof(struct erofs_inode_extended) != 64);
+       BUILD_BUG_ON(sizeof(struct erofs_xattr_ibody_header) != 12);
+       BUILD_BUG_ON(sizeof(struct erofs_xattr_entry) != 4);
+       BUILD_BUG_ON(sizeof(struct erofs_inode_chunk_info) != 4);
+       BUILD_BUG_ON(sizeof(struct erofs_inode_chunk_index) != 8);
+       BUILD_BUG_ON(sizeof(struct z_erofs_map_header) != 8);
+       BUILD_BUG_ON(sizeof(struct z_erofs_vle_decompressed_index) != 8);
+       BUILD_BUG_ON(sizeof(struct erofs_dirent) != 12);
+       /* keep in sync between 2 index structures for better extendibility */
+       BUILD_BUG_ON(sizeof(struct erofs_inode_chunk_index) !=
+                    sizeof(struct z_erofs_vle_decompressed_index));
+       BUILD_BUG_ON(sizeof(struct erofs_deviceslot) != 128);
+
+       BUILD_BUG_ON(BIT(Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) <
+                    Z_EROFS_VLE_CLUSTER_TYPE_MAX - 1);
+}
+
+#endif
diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c
new file mode 100644 (file)
index 0000000..8926975
--- /dev/null
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "internal.h"
+#include <fs_internal.h>
+
+struct erofs_sb_info sbi;
+
+static struct erofs_ctxt {
+       struct disk_partition cur_part_info;
+       struct blk_desc *cur_dev;
+} ctxt;
+
+int erofs_dev_read(int device_id, void *buf, u64 offset, size_t len)
+{
+       lbaint_t sect = offset >> ctxt.cur_dev->log2blksz;
+       int off = offset & (ctxt.cur_dev->blksz - 1);
+
+       if (!ctxt.cur_dev)
+               return -EIO;
+
+       if (fs_devread(ctxt.cur_dev, &ctxt.cur_part_info, sect,
+                      off, len, buf))
+               return 0;
+       return -EIO;
+}
+
+int erofs_blk_read(void *buf, erofs_blk_t start, u32 nblocks)
+{
+       return erofs_dev_read(0, buf, blknr_to_addr(start),
+                        blknr_to_addr(nblocks));
+}
+
+int erofs_probe(struct blk_desc *fs_dev_desc,
+               struct disk_partition *fs_partition)
+{
+       int ret;
+
+       ctxt.cur_dev = fs_dev_desc;
+       ctxt.cur_part_info = *fs_partition;
+
+       ret = erofs_read_superblock();
+       if (ret)
+               goto error;
+
+       return 0;
+error:
+       ctxt.cur_dev = NULL;
+       return ret;
+}
+
+struct erofs_dir_stream {
+       struct fs_dir_stream fs_dirs;
+       struct fs_dirent dirent;
+
+       struct erofs_inode inode;
+       char dblk[EROFS_BLKSIZ];
+       unsigned int maxsize, de_end;
+       erofs_off_t pos;
+};
+
+static int erofs_readlink(struct erofs_inode *vi)
+{
+       size_t len = vi->i_size;
+       char *target;
+       int err;
+
+       target = malloc(len + 1);
+       if (!target)
+               return -ENOMEM;
+       target[len] = '\0';
+
+       err = erofs_pread(vi, target, len, 0);
+       if (err)
+               goto err_out;
+
+       err = erofs_ilookup(target, vi);
+       if (err)
+               goto err_out;
+
+err_out:
+       free(target);
+       return err;
+}
+
+int erofs_opendir(const char *filename, struct fs_dir_stream **dirsp)
+{
+       struct erofs_dir_stream *dirs;
+       int err;
+
+       dirs = calloc(1, sizeof(*dirs));
+       if (!dirs)
+               return -ENOMEM;
+
+       err = erofs_ilookup(filename, &dirs->inode);
+       if (err)
+               goto err_out;
+
+       if (S_ISLNK(dirs->inode.i_mode)) {
+               err = erofs_readlink(&dirs->inode);
+               if (err)
+                       goto err_out;
+       }
+
+       if (!S_ISDIR(dirs->inode.i_mode)) {
+               err = -ENOTDIR;
+               goto err_out;
+       }
+       *dirsp = (struct fs_dir_stream *)dirs;
+       return 0;
+err_out:
+       free(dirs);
+       return err;
+}
+
+int erofs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
+{
+       struct erofs_dir_stream *dirs = (struct erofs_dir_stream *)fs_dirs;
+       struct fs_dirent *dent = &dirs->dirent;
+       erofs_off_t pos = dirs->pos;
+       unsigned int nameoff, de_namelen;
+       struct erofs_dirent *de;
+       char *de_name;
+       int err;
+
+       if (pos >= dirs->inode.i_size)
+               return 1;
+
+       if (!dirs->maxsize) {
+               dirs->maxsize = min_t(unsigned int, EROFS_BLKSIZ,
+                                     dirs->inode.i_size - pos);
+
+               err = erofs_pread(&dirs->inode, dirs->dblk,
+                                 dirs->maxsize, pos);
+               if (err)
+                       return err;
+
+               de = (struct erofs_dirent *)dirs->dblk;
+               dirs->de_end = le16_to_cpu(de->nameoff);
+               if (dirs->de_end < sizeof(struct erofs_dirent) ||
+                   dirs->de_end >= EROFS_BLKSIZ) {
+                       erofs_err("invalid de[0].nameoff %u @ nid %llu",
+                                 dirs->de_end, de->nid | 0ULL);
+                       return -EFSCORRUPTED;
+               }
+       }
+
+       de = (struct erofs_dirent *)(dirs->dblk + erofs_blkoff(pos));
+       nameoff = le16_to_cpu(de->nameoff);
+       de_name = (char *)dirs->dblk + nameoff;
+
+       /* the last dirent in the block? */
+       if (de + 1 >= (struct erofs_dirent *)(dirs->dblk + dirs->de_end))
+               de_namelen = strnlen(de_name, dirs->maxsize - nameoff);
+       else
+               de_namelen = le16_to_cpu(de[1].nameoff) - nameoff;
+
+       /* a corrupted entry is found */
+       if (nameoff + de_namelen > dirs->maxsize ||
+           de_namelen > EROFS_NAME_LEN) {
+               erofs_err("bogus dirent @ nid %llu", de->nid | 0ULL);
+               DBG_BUGON(1);
+               return -EFSCORRUPTED;
+       }
+
+       memcpy(dent->name, de_name, de_namelen);
+       dent->name[de_namelen] = '\0';
+
+       if (de->file_type == EROFS_FT_DIR) {
+               dent->type = FS_DT_DIR;
+       } else if (de->file_type == EROFS_FT_SYMLINK) {
+               dent->type = FS_DT_LNK;
+       } else {
+               struct erofs_inode vi;
+
+               dent->type = FS_DT_REG;
+               vi.nid = de->nid;
+
+               err = erofs_read_inode_from_disk(&vi);
+               if (err)
+                       return err;
+               dent->size = vi.i_size;
+       }
+       *dentp = dent;
+
+       pos += sizeof(*de);
+       if (erofs_blkoff(pos) >= dirs->de_end) {
+               pos = blknr_to_addr(erofs_blknr(pos) + 1);
+               dirs->maxsize = 0;
+       }
+       dirs->pos = pos;
+       return 0;
+}
+
+void erofs_closedir(struct fs_dir_stream *fs_dirs)
+{
+       free(fs_dirs);
+}
+
+int erofs_exists(const char *filename)
+{
+       struct erofs_inode vi;
+       int err;
+
+       err = erofs_ilookup(filename, &vi);
+       return err == 0;
+}
+
+int erofs_size(const char *filename, loff_t *size)
+{
+       struct erofs_inode vi;
+       int err;
+
+       err = erofs_ilookup(filename, &vi);
+       if (err)
+               return err;
+       *size = vi.i_size;
+       return 0;
+}
+
+int erofs_read(const char *filename, void *buf, loff_t offset, loff_t len,
+              loff_t *actread)
+{
+       struct erofs_inode vi;
+       int err;
+
+       err = erofs_ilookup(filename, &vi);
+       if (err)
+               return err;
+
+       if (S_ISLNK(vi.i_mode)) {
+               err = erofs_readlink(&vi);
+               if (err)
+                       return err;
+       }
+
+       if (!len)
+               len = vi.i_size;
+
+       err = erofs_pread(&vi, buf, len, offset);
+       if (err) {
+               *actread = 0;
+               return err;
+       }
+
+       if (offset >= vi.i_size)
+               *actread = 0;
+       else if (offset + len > vi.i_size)
+               *actread = vi.i_size - offset;
+       else
+               *actread = len;
+       return 0;
+}
+
+void erofs_close(void)
+{
+       ctxt.cur_dev = NULL;
+}
+
+int erofs_uuid(char *uuid_str)
+{
+       if (IS_ENABLED(CONFIG_LIB_UUID)) {
+               if (ctxt.cur_dev)
+                       uuid_bin_to_str(sbi.uuid, uuid_str,
+                                       UUID_STR_FORMAT_STD);
+               return 0;
+       }
+       return -ENOSYS;
+}
diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h
new file mode 100644 (file)
index 0000000..4af7c91
--- /dev/null
@@ -0,0 +1,313 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __EROFS_INTERNAL_H
+#define __EROFS_INTERNAL_H
+
+#define __packed __attribute__((__packed__))
+
+#include <linux/stat.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/printk.h>
+#include <linux/log2.h>
+#include <inttypes.h>
+#include "erofs_fs.h"
+
+#define erofs_err(fmt, ...)    \
+       pr_err(fmt "\n", ##__VA_ARGS__)
+
+#define erofs_info(fmt, ...)   \
+       pr_info(fmt "\n", ##__VA_ARGS__)
+
+#define erofs_dbg(fmt, ...)    \
+       pr_debug(fmt "\n", ##__VA_ARGS__)
+
+#define DBG_BUGON(condition)   BUG_ON(condition)
+
+/* no obvious reason to support explicit PAGE_SIZE != 4096 for now */
+#if PAGE_SIZE != 4096
+#error incompatible PAGE_SIZE is already defined
+#endif
+
+#define PAGE_MASK              (~(PAGE_SIZE - 1))
+
+#define LOG_BLOCK_SIZE          (12)
+#define EROFS_BLKSIZ            (1U << LOG_BLOCK_SIZE)
+
+#define EROFS_ISLOTBITS                5
+#define EROFS_SLOTSIZE         (1U << EROFS_ISLOTBITS)
+
+typedef u64 erofs_off_t;
+typedef u64 erofs_nid_t;
+/* data type for filesystem-wide blocks number */
+typedef u32 erofs_blk_t;
+
+#define NULL_ADDR      ((unsigned int)-1)
+#define NULL_ADDR_UL   ((unsigned long)-1)
+
+#define erofs_blknr(addr)       ((addr) / EROFS_BLKSIZ)
+#define erofs_blkoff(addr)      ((addr) % EROFS_BLKSIZ)
+#define blknr_to_addr(nr)       ((erofs_off_t)(nr) * EROFS_BLKSIZ)
+
+#define BLK_ROUND_UP(addr)     DIV_ROUND_UP(addr, EROFS_BLKSIZ)
+
+struct erofs_buffer_head;
+
+struct erofs_device_info {
+       u32 blocks;
+       u32 mapped_blkaddr;
+};
+
+struct erofs_sb_info {
+       struct erofs_device_info *devs;
+
+       u64 total_blocks;
+       u64 primarydevice_blocks;
+
+       erofs_blk_t meta_blkaddr;
+       erofs_blk_t xattr_blkaddr;
+
+       u32 feature_compat;
+       u32 feature_incompat;
+       u64 build_time;
+       u32 build_time_nsec;
+
+       unsigned char islotbits;
+
+       /* what we really care is nid, rather than ino.. */
+       erofs_nid_t root_nid;
+       /* used for statfs, f_files - f_favail */
+       u64 inos;
+
+       u8 uuid[16];
+
+       u16 available_compr_algs;
+       u16 lz4_max_distance;
+       u32 checksum;
+       u16 extra_devices;
+       union {
+               u16 devt_slotoff;               /* used for mkfs */
+               u16 device_id_mask;             /* used for others */
+       };
+};
+
+/* global sbi */
+extern struct erofs_sb_info sbi;
+
+static inline erofs_off_t iloc(erofs_nid_t nid)
+{
+       return blknr_to_addr(sbi.meta_blkaddr) + (nid << sbi.islotbits);
+}
+
+#define EROFS_FEATURE_FUNCS(name, compat, feature) \
+static inline bool erofs_sb_has_##name(void) \
+{ \
+       return sbi.feature_##compat & EROFS_FEATURE_##feature; \
+} \
+static inline void erofs_sb_set_##name(void) \
+{ \
+       sbi.feature_##compat |= EROFS_FEATURE_##feature; \
+} \
+static inline void erofs_sb_clear_##name(void) \
+{ \
+       sbi.feature_##compat &= ~EROFS_FEATURE_##feature; \
+}
+
+EROFS_FEATURE_FUNCS(lz4_0padding, incompat, INCOMPAT_LZ4_0PADDING)
+EROFS_FEATURE_FUNCS(compr_cfgs, incompat, INCOMPAT_COMPR_CFGS)
+EROFS_FEATURE_FUNCS(big_pcluster, incompat, INCOMPAT_BIG_PCLUSTER)
+EROFS_FEATURE_FUNCS(chunked_file, incompat, INCOMPAT_CHUNKED_FILE)
+EROFS_FEATURE_FUNCS(device_table, incompat, INCOMPAT_DEVICE_TABLE)
+EROFS_FEATURE_FUNCS(sb_chksum, compat, COMPAT_SB_CHKSUM)
+
+#define EROFS_I_EA_INITED      (1 << 0)
+#define EROFS_I_Z_INITED       (1 << 1)
+
+struct erofs_inode {
+       struct list_head i_hash, i_subdirs, i_xattrs;
+
+       union {
+               /* (erofsfuse) runtime flags */
+               unsigned int flags;
+               /* (mkfs.erofs) device ID containing source file */
+               u32 dev;
+       };
+       unsigned int i_count;
+       struct erofs_inode *i_parent;
+
+       umode_t i_mode;
+       erofs_off_t i_size;
+
+       u64 i_ino[2];
+       u32 i_uid;
+       u32 i_gid;
+       u64 i_ctime;
+       u32 i_ctime_nsec;
+       u32 i_nlink;
+
+       union {
+               u32 i_blkaddr;
+               u32 i_blocks;
+               u32 i_rdev;
+               struct {
+                       unsigned short  chunkformat;
+                       unsigned char   chunkbits;
+               };
+       } u;
+
+       unsigned char datalayout;
+       unsigned char inode_isize;
+       /* inline tail-end packing size */
+       unsigned short idata_size;
+
+       unsigned int xattr_isize;
+       unsigned int extent_isize;
+
+       erofs_nid_t nid;
+       struct erofs_buffer_head *bh;
+       struct erofs_buffer_head *bh_inline, *bh_data;
+
+       void *idata;
+
+       union {
+               void *compressmeta;
+               void *chunkindexes;
+               struct {
+                       uint16_t z_advise;
+                       uint8_t  z_algorithmtype[2];
+                       uint8_t  z_logical_clusterbits;
+                       uint8_t  z_physical_clusterblks;
+               };
+       };
+};
+
+static inline bool is_inode_layout_compression(struct erofs_inode *inode)
+{
+       return erofs_inode_is_data_compressed(inode->datalayout);
+}
+
+static inline unsigned int erofs_bitrange(unsigned int value, unsigned int bit,
+                                         unsigned int bits)
+{
+       return (value >> bit) & ((1 << bits) - 1);
+}
+
+static inline unsigned int erofs_inode_version(unsigned int value)
+{
+       return erofs_bitrange(value, EROFS_I_VERSION_BIT,
+                             EROFS_I_VERSION_BITS);
+}
+
+static inline unsigned int erofs_inode_datalayout(unsigned int value)
+{
+       return erofs_bitrange(value, EROFS_I_DATALAYOUT_BIT,
+                             EROFS_I_DATALAYOUT_BITS);
+}
+
+#define IS_ROOT(x)     ((x) == (x)->i_parent)
+
+struct erofs_dentry {
+       struct list_head d_child;       /* child of parent list */
+
+       unsigned int type;
+       char name[EROFS_NAME_LEN];
+       union {
+               struct erofs_inode *inode;
+               erofs_nid_t nid;
+       };
+};
+
+static inline bool is_dot_dotdot(const char *name)
+{
+       if (name[0] != '.')
+               return false;
+
+       return name[1] == '\0' || (name[1] == '.' && name[2] == '\0');
+}
+
+enum {
+       BH_Meta,
+       BH_Mapped,
+       BH_Encoded,
+       BH_FullMapped,
+};
+
+/* Has a disk mapping */
+#define EROFS_MAP_MAPPED       (1 << BH_Mapped)
+/* Located in metadata (could be copied from bd_inode) */
+#define EROFS_MAP_META         (1 << BH_Meta)
+/* The extent is encoded */
+#define EROFS_MAP_ENCODED      (1 << BH_Encoded)
+/* The length of extent is full */
+#define EROFS_MAP_FULL_MAPPED  (1 << BH_FullMapped)
+
+struct erofs_map_blocks {
+       char mpage[EROFS_BLKSIZ];
+
+       erofs_off_t m_pa, m_la;
+       u64 m_plen, m_llen;
+
+       unsigned short m_deviceid;
+       char m_algorithmformat;
+       unsigned int m_flags;
+       erofs_blk_t index;
+};
+
+/*
+ * Used to get the exact decompressed length, e.g. fiemap (consider lookback
+ * approach instead if possible since it's more metadata lightweight.)
+ */
+#define EROFS_GET_BLOCKS_FIEMAP        0x0002
+
+enum {
+       Z_EROFS_COMPRESSION_SHIFTED = Z_EROFS_COMPRESSION_MAX,
+       Z_EROFS_COMPRESSION_RUNTIME_MAX
+};
+
+struct erofs_map_dev {
+       erofs_off_t m_pa;
+       unsigned int m_deviceid;
+};
+
+/* fs.c */
+int erofs_blk_read(void *buf, erofs_blk_t start, u32 nblocks);
+int erofs_dev_read(int device_id, void *buf, u64 offset, size_t len);
+
+/* super.c */
+int erofs_read_superblock(void);
+
+/* namei.c */
+int erofs_read_inode_from_disk(struct erofs_inode *vi);
+int erofs_ilookup(const char *path, struct erofs_inode *vi);
+int erofs_read_inode_from_disk(struct erofs_inode *vi);
+
+/* data.c */
+int erofs_pread(struct erofs_inode *inode, char *buf,
+               erofs_off_t count, erofs_off_t offset);
+int erofs_map_blocks(struct erofs_inode *inode,
+                    struct erofs_map_blocks *map, int flags);
+int erofs_map_dev(struct erofs_sb_info *sbi, struct erofs_map_dev *map);
+/* zmap.c */
+int z_erofs_fill_inode(struct erofs_inode *vi);
+int z_erofs_map_blocks_iter(struct erofs_inode *vi,
+                           struct erofs_map_blocks *map, int flags);
+
+#ifdef EUCLEAN
+#define EFSCORRUPTED   EUCLEAN         /* Filesystem is corrupted */
+#else
+#define EFSCORRUPTED   EIO
+#endif
+
+#define CRC32C_POLY_LE 0x82F63B78
+static inline u32 erofs_crc32c(u32 crc, const u8 *in, size_t len)
+{
+       int i;
+
+       while (len--) {
+               crc ^= *in++;
+               for (i = 0; i < 8; i++)
+                       crc = (crc >> 1) ^ ((crc & 1) ? CRC32C_POLY_LE : 0);
+       }
+       return crc;
+}
+
+#endif
diff --git a/fs/erofs/namei.c b/fs/erofs/namei.c
new file mode 100644 (file)
index 0000000..d1d4757
--- /dev/null
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "internal.h"
+
+int erofs_read_inode_from_disk(struct erofs_inode *vi)
+{
+       int ret, ifmt;
+       char buf[sizeof(struct erofs_inode_extended)];
+       struct erofs_inode_compact *dic;
+       struct erofs_inode_extended *die;
+       const erofs_off_t inode_loc = iloc(vi->nid);
+
+       ret = erofs_dev_read(0, buf, inode_loc, sizeof(*dic));
+       if (ret < 0)
+               return -EIO;
+
+       dic = (struct erofs_inode_compact *)buf;
+       ifmt = le16_to_cpu(dic->i_format);
+
+       vi->datalayout = erofs_inode_datalayout(ifmt);
+       if (vi->datalayout >= EROFS_INODE_DATALAYOUT_MAX) {
+               erofs_err("unsupported datalayout %u of nid %llu",
+                         vi->datalayout, vi->nid | 0ULL);
+               return -EOPNOTSUPP;
+       }
+       switch (erofs_inode_version(ifmt)) {
+       case EROFS_INODE_LAYOUT_EXTENDED:
+               vi->inode_isize = sizeof(struct erofs_inode_extended);
+
+               ret = erofs_dev_read(0, buf + sizeof(*dic), inode_loc + sizeof(*dic),
+                                    sizeof(*die) - sizeof(*dic));
+               if (ret < 0)
+                       return -EIO;
+
+               die = (struct erofs_inode_extended *)buf;
+               vi->xattr_isize = erofs_xattr_ibody_size(die->i_xattr_icount);
+               vi->i_mode = le16_to_cpu(die->i_mode);
+
+               switch (vi->i_mode & S_IFMT) {
+               case S_IFREG:
+               case S_IFDIR:
+               case S_IFLNK:
+                       vi->u.i_blkaddr = le32_to_cpu(die->i_u.raw_blkaddr);
+                       break;
+               case S_IFCHR:
+               case S_IFBLK:
+                       vi->u.i_rdev = 0;
+                       break;
+               case S_IFIFO:
+               case S_IFSOCK:
+                       vi->u.i_rdev = 0;
+                       break;
+               default:
+                       goto bogusimode;
+               }
+
+               vi->i_uid = le32_to_cpu(die->i_uid);
+               vi->i_gid = le32_to_cpu(die->i_gid);
+               vi->i_nlink = le32_to_cpu(die->i_nlink);
+
+               vi->i_ctime = le64_to_cpu(die->i_ctime);
+               vi->i_ctime_nsec = le64_to_cpu(die->i_ctime_nsec);
+               vi->i_size = le64_to_cpu(die->i_size);
+               if (vi->datalayout == EROFS_INODE_CHUNK_BASED)
+                       /* fill chunked inode summary info */
+                       vi->u.chunkformat = le16_to_cpu(die->i_u.c.format);
+               break;
+       case EROFS_INODE_LAYOUT_COMPACT:
+               vi->inode_isize = sizeof(struct erofs_inode_compact);
+               vi->xattr_isize = erofs_xattr_ibody_size(dic->i_xattr_icount);
+               vi->i_mode = le16_to_cpu(dic->i_mode);
+
+               switch (vi->i_mode & S_IFMT) {
+               case S_IFREG:
+               case S_IFDIR:
+               case S_IFLNK:
+                       vi->u.i_blkaddr = le32_to_cpu(dic->i_u.raw_blkaddr);
+                       break;
+               case S_IFCHR:
+               case S_IFBLK:
+                       vi->u.i_rdev = 0;
+                       break;
+               case S_IFIFO:
+               case S_IFSOCK:
+                       vi->u.i_rdev = 0;
+                       break;
+               default:
+                       goto bogusimode;
+               }
+
+               vi->i_uid = le16_to_cpu(dic->i_uid);
+               vi->i_gid = le16_to_cpu(dic->i_gid);
+               vi->i_nlink = le16_to_cpu(dic->i_nlink);
+
+               vi->i_ctime = sbi.build_time;
+               vi->i_ctime_nsec = sbi.build_time_nsec;
+
+               vi->i_size = le32_to_cpu(dic->i_size);
+               if (vi->datalayout == EROFS_INODE_CHUNK_BASED)
+                       vi->u.chunkformat = le16_to_cpu(dic->i_u.c.format);
+               break;
+       default:
+               erofs_err("unsupported on-disk inode version %u of nid %llu",
+                         erofs_inode_version(ifmt), vi->nid | 0ULL);
+               return -EOPNOTSUPP;
+       }
+
+       vi->flags = 0;
+       if (vi->datalayout == EROFS_INODE_CHUNK_BASED) {
+               if (vi->u.chunkformat & ~EROFS_CHUNK_FORMAT_ALL) {
+                       erofs_err("unsupported chunk format %x of nid %llu",
+                                 vi->u.chunkformat, vi->nid | 0ULL);
+                       return -EOPNOTSUPP;
+               }
+               vi->u.chunkbits = LOG_BLOCK_SIZE +
+                       (vi->u.chunkformat & EROFS_CHUNK_FORMAT_BLKBITS_MASK);
+       } else if (erofs_inode_is_data_compressed(vi->datalayout))
+               z_erofs_fill_inode(vi);
+       return 0;
+bogusimode:
+       erofs_err("bogus i_mode (%o) @ nid %llu", vi->i_mode, vi->nid | 0ULL);
+       return -EFSCORRUPTED;
+}
+
+struct erofs_dirent *find_target_dirent(erofs_nid_t pnid,
+                                       void *dentry_blk,
+                                       const char *name, unsigned int len,
+                                       unsigned int nameoff,
+                                       unsigned int maxsize)
+{
+       struct erofs_dirent *de = dentry_blk;
+       const struct erofs_dirent *end = dentry_blk + nameoff;
+
+       while (de < end) {
+               const char *de_name;
+               unsigned int de_namelen;
+
+               nameoff = le16_to_cpu(de->nameoff);
+               de_name = (char *)dentry_blk + nameoff;
+
+               /* the last dirent in the block? */
+               if (de + 1 >= end)
+                       de_namelen = strnlen(de_name, maxsize - nameoff);
+               else
+                       de_namelen = le16_to_cpu(de[1].nameoff) - nameoff;
+
+               /* a corrupted entry is found */
+               if (nameoff + de_namelen > maxsize ||
+                   de_namelen > EROFS_NAME_LEN) {
+                       erofs_err("bogus dirent @ nid %llu", pnid | 0ULL);
+                       DBG_BUGON(1);
+                       return ERR_PTR(-EFSCORRUPTED);
+               }
+
+               if (len == de_namelen && !memcmp(de_name, name, de_namelen))
+                       return de;
+               ++de;
+       }
+       return NULL;
+}
+
+struct nameidata {
+       erofs_nid_t     nid;
+       unsigned int    ftype;
+};
+
+int erofs_namei(struct nameidata *nd,
+               const char *name, unsigned int len)
+{
+       erofs_nid_t nid = nd->nid;
+       int ret;
+       char buf[EROFS_BLKSIZ];
+       struct erofs_inode vi = { .nid = nid };
+       erofs_off_t offset;
+
+       ret = erofs_read_inode_from_disk(&vi);
+       if (ret)
+               return ret;
+
+       offset = 0;
+       while (offset < vi.i_size) {
+               erofs_off_t maxsize = min_t(erofs_off_t,
+                                           vi.i_size - offset, EROFS_BLKSIZ);
+               struct erofs_dirent *de = (void *)buf;
+               unsigned int nameoff;
+
+               ret = erofs_pread(&vi, buf, maxsize, offset);
+               if (ret)
+                       return ret;
+
+               nameoff = le16_to_cpu(de->nameoff);
+               if (nameoff < sizeof(struct erofs_dirent) ||
+                   nameoff >= PAGE_SIZE) {
+                       erofs_err("invalid de[0].nameoff %u @ nid %llu",
+                                 nameoff, nid | 0ULL);
+                       return -EFSCORRUPTED;
+               }
+
+               de = find_target_dirent(nid, buf, name, len,
+                                       nameoff, maxsize);
+               if (IS_ERR(de))
+                       return PTR_ERR(de);
+
+               if (de) {
+                       nd->nid = le64_to_cpu(de->nid);
+                       return 0;
+               }
+               offset += maxsize;
+       }
+       return -ENOENT;
+}
+
+static int link_path_walk(const char *name, struct nameidata *nd)
+{
+       nd->nid = sbi.root_nid;
+
+       while (*name == '/')
+               name++;
+
+       /* At this point we know we have a real path component. */
+       while (*name != '\0') {
+               const char *p = name;
+               int ret;
+
+               do {
+                       ++p;
+               } while (*p != '\0' && *p != '/');
+
+               DBG_BUGON(p <= name);
+               ret = erofs_namei(nd, name, p - name);
+               if (ret)
+                       return ret;
+
+               name = p;
+               /* Skip until no more slashes. */
+               for (name = p; *name == '/'; ++name)
+                       ;
+       }
+       return 0;
+}
+
+int erofs_ilookup(const char *path, struct erofs_inode *vi)
+{
+       int ret;
+       struct nameidata nd;
+
+       ret = link_path_walk(path, &nd);
+       if (ret)
+               return ret;
+
+       vi->nid = nd.nid;
+       return erofs_read_inode_from_disk(vi);
+}
diff --git a/fs/erofs/super.c b/fs/erofs/super.c
new file mode 100644 (file)
index 0000000..4cca322
--- /dev/null
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "internal.h"
+
+static bool check_layout_compatibility(struct erofs_sb_info *sbi,
+                                      struct erofs_super_block *dsb)
+{
+       const unsigned int feature = le32_to_cpu(dsb->feature_incompat);
+
+       sbi->feature_incompat = feature;
+
+       /* check if current kernel meets all mandatory requirements */
+       if (feature & (~EROFS_ALL_FEATURE_INCOMPAT)) {
+               erofs_err("unidentified incompatible feature %x, please upgrade kernel version",
+                         feature & ~EROFS_ALL_FEATURE_INCOMPAT);
+               return false;
+       }
+       return true;
+}
+
+static int erofs_init_devices(struct erofs_sb_info *sbi,
+                             struct erofs_super_block *dsb)
+{
+       unsigned int ondisk_extradevs, i;
+       erofs_off_t pos;
+
+       sbi->total_blocks = sbi->primarydevice_blocks;
+
+       if (!erofs_sb_has_device_table())
+               ondisk_extradevs = 0;
+       else
+               ondisk_extradevs = le16_to_cpu(dsb->extra_devices);
+
+       if (ondisk_extradevs != sbi->extra_devices) {
+               erofs_err("extra devices don't match (ondisk %u, given %u)",
+                         ondisk_extradevs, sbi->extra_devices);
+               return -EINVAL;
+       }
+       if (!ondisk_extradevs)
+               return 0;
+
+       sbi->device_id_mask = roundup_pow_of_two(ondisk_extradevs + 1) - 1;
+       sbi->devs = calloc(ondisk_extradevs, sizeof(*sbi->devs));
+       pos = le16_to_cpu(dsb->devt_slotoff) * EROFS_DEVT_SLOT_SIZE;
+       for (i = 0; i < ondisk_extradevs; ++i) {
+               struct erofs_deviceslot dis;
+               int ret;
+
+               ret = erofs_dev_read(0, &dis, pos, sizeof(dis));
+               if (ret < 0)
+                       return ret;
+
+               sbi->devs[i].mapped_blkaddr = dis.mapped_blkaddr;
+               sbi->total_blocks += dis.blocks;
+               pos += EROFS_DEVT_SLOT_SIZE;
+       }
+       return 0;
+}
+
+int erofs_read_superblock(void)
+{
+       char data[EROFS_BLKSIZ];
+       struct erofs_super_block *dsb;
+       unsigned int blkszbits;
+       int ret;
+
+       ret = erofs_blk_read(data, 0, 1);
+       if (ret < 0) {
+               erofs_err("cannot read erofs superblock: %d", ret);
+               return -EIO;
+       }
+       dsb = (struct erofs_super_block *)(data + EROFS_SUPER_OFFSET);
+
+       ret = -EINVAL;
+       if (le32_to_cpu(dsb->magic) != EROFS_SUPER_MAGIC_V1) {
+               erofs_err("cannot find valid erofs superblock");
+               return ret;
+       }
+
+       sbi.feature_compat = le32_to_cpu(dsb->feature_compat);
+
+       blkszbits = dsb->blkszbits;
+       /* 9(512 bytes) + LOG_SECTORS_PER_BLOCK == LOG_BLOCK_SIZE */
+       if (blkszbits != LOG_BLOCK_SIZE) {
+               erofs_err("blksize %u isn't supported on this platform",
+                         1 << blkszbits);
+               return ret;
+       }
+
+       if (!check_layout_compatibility(&sbi, dsb))
+               return ret;
+
+       sbi.primarydevice_blocks = le32_to_cpu(dsb->blocks);
+       sbi.meta_blkaddr = le32_to_cpu(dsb->meta_blkaddr);
+       sbi.xattr_blkaddr = le32_to_cpu(dsb->xattr_blkaddr);
+       sbi.islotbits = EROFS_ISLOTBITS;
+       sbi.root_nid = le16_to_cpu(dsb->root_nid);
+       sbi.inos = le64_to_cpu(dsb->inos);
+       sbi.checksum = le32_to_cpu(dsb->checksum);
+
+       sbi.build_time = le64_to_cpu(dsb->build_time);
+       sbi.build_time_nsec = le32_to_cpu(dsb->build_time_nsec);
+
+       memcpy(&sbi.uuid, dsb->uuid, sizeof(dsb->uuid));
+       return erofs_init_devices(&sbi, dsb);
+}
diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c
new file mode 100644 (file)
index 0000000..be2599a
--- /dev/null
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "internal.h"
+
+int z_erofs_fill_inode(struct erofs_inode *vi)
+{
+       if (!erofs_sb_has_big_pcluster() &&
+           vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY) {
+               vi->z_advise = 0;
+               vi->z_algorithmtype[0] = 0;
+               vi->z_algorithmtype[1] = 0;
+               vi->z_logical_clusterbits = LOG_BLOCK_SIZE;
+
+               vi->flags |= EROFS_I_Z_INITED;
+       }
+       return 0;
+}
+
+static int z_erofs_fill_inode_lazy(struct erofs_inode *vi)
+{
+       int ret;
+       erofs_off_t pos;
+       struct z_erofs_map_header *h;
+       char buf[sizeof(struct z_erofs_map_header)];
+
+       if (vi->flags & EROFS_I_Z_INITED)
+               return 0;
+
+       DBG_BUGON(!erofs_sb_has_big_pcluster() &&
+                 vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY);
+       pos = round_up(iloc(vi->nid) + vi->inode_isize + vi->xattr_isize, 8);
+
+       ret = erofs_dev_read(0, buf, pos, sizeof(buf));
+       if (ret < 0)
+               return -EIO;
+
+       h = (struct z_erofs_map_header *)buf;
+       vi->z_advise = le16_to_cpu(h->h_advise);
+       vi->z_algorithmtype[0] = h->h_algorithmtype & 15;
+       vi->z_algorithmtype[1] = h->h_algorithmtype >> 4;
+
+       if (vi->z_algorithmtype[0] >= Z_EROFS_COMPRESSION_MAX) {
+               erofs_err("unknown compression format %u for nid %llu",
+                         vi->z_algorithmtype[0], (unsigned long long)vi->nid);
+               return -EOPNOTSUPP;
+       }
+
+       vi->z_logical_clusterbits = LOG_BLOCK_SIZE + (h->h_clusterbits & 7);
+       if (vi->datalayout == EROFS_INODE_FLAT_COMPRESSION &&
+           !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1) ^
+           !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_2)) {
+               erofs_err("big pcluster head1/2 of compact indexes should be consistent for nid %llu",
+                         vi->nid * 1ULL);
+               return -EFSCORRUPTED;
+       }
+       vi->flags |= EROFS_I_Z_INITED;
+       return 0;
+}
+
+struct z_erofs_maprecorder {
+       struct erofs_inode *inode;
+       struct erofs_map_blocks *map;
+       void *kaddr;
+
+       unsigned long lcn;
+       /* compression extent information gathered */
+       u8  type, headtype;
+       u16 clusterofs;
+       u16 delta[2];
+       erofs_blk_t pblk, compressedlcs;
+};
+
+static int z_erofs_reload_indexes(struct z_erofs_maprecorder *m,
+                                 erofs_blk_t eblk)
+{
+       int ret;
+       struct erofs_map_blocks *const map = m->map;
+       char *mpage = map->mpage;
+
+       if (map->index == eblk)
+               return 0;
+
+       ret = erofs_blk_read(mpage, eblk, 1);
+       if (ret < 0)
+               return -EIO;
+
+       map->index = eblk;
+
+       return 0;
+}
+
+static int legacy_load_cluster_from_disk(struct z_erofs_maprecorder *m,
+                                        unsigned long lcn)
+{
+       struct erofs_inode *const vi = m->inode;
+       const erofs_off_t ibase = iloc(vi->nid);
+       const erofs_off_t pos =
+               Z_EROFS_VLE_LEGACY_INDEX_ALIGN(ibase + vi->inode_isize +
+                                              vi->xattr_isize) +
+               lcn * sizeof(struct z_erofs_vle_decompressed_index);
+       struct z_erofs_vle_decompressed_index *di;
+       unsigned int advise, type;
+       int err;
+
+       err = z_erofs_reload_indexes(m, erofs_blknr(pos));
+       if (err)
+               return err;
+
+       m->lcn = lcn;
+       di = m->kaddr + erofs_blkoff(pos);
+
+       advise = le16_to_cpu(di->di_advise);
+       type = (advise >> Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT) &
+               ((1 << Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) - 1);
+       switch (type) {
+       case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+               m->clusterofs = 1 << vi->z_logical_clusterbits;
+               m->delta[0] = le16_to_cpu(di->di_u.delta[0]);
+               if (m->delta[0] & Z_EROFS_VLE_DI_D0_CBLKCNT) {
+                       if (!(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1)) {
+                               DBG_BUGON(1);
+                               return -EFSCORRUPTED;
+                       }
+                       m->compressedlcs = m->delta[0] &
+                               ~Z_EROFS_VLE_DI_D0_CBLKCNT;
+                       m->delta[0] = 1;
+               }
+               m->delta[1] = le16_to_cpu(di->di_u.delta[1]);
+               break;
+       case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
+       case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+               m->clusterofs = le16_to_cpu(di->di_clusterofs);
+               m->pblk = le32_to_cpu(di->di_u.blkaddr);
+               break;
+       default:
+               DBG_BUGON(1);
+               return -EOPNOTSUPP;
+       }
+       m->type = type;
+       return 0;
+}
+
+static unsigned int decode_compactedbits(unsigned int lobits,
+                                        unsigned int lomask,
+                                        u8 *in, unsigned int pos, u8 *type)
+{
+       const unsigned int v = get_unaligned_le32(in + pos / 8) >> (pos & 7);
+       const unsigned int lo = v & lomask;
+
+       *type = (v >> lobits) & 3;
+       return lo;
+}
+
+static int get_compacted_la_distance(unsigned int lclusterbits,
+                                    unsigned int encodebits,
+                                    unsigned int vcnt, u8 *in, int i)
+{
+       const unsigned int lomask = (1 << lclusterbits) - 1;
+       unsigned int lo, d1 = 0;
+       u8 type;
+
+       DBG_BUGON(i >= vcnt);
+
+       do {
+               lo = decode_compactedbits(lclusterbits, lomask,
+                                         in, encodebits * i, &type);
+
+               if (type != Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD)
+                       return d1;
+               ++d1;
+       } while (++i < vcnt);
+
+       /* vcnt - 1 (Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) item */
+       if (!(lo & Z_EROFS_VLE_DI_D0_CBLKCNT))
+               d1 += lo - 1;
+       return d1;
+}
+
+static int unpack_compacted_index(struct z_erofs_maprecorder *m,
+                                 unsigned int amortizedshift,
+                                 unsigned int eofs, bool lookahead)
+{
+       struct erofs_inode *const vi = m->inode;
+       const unsigned int lclusterbits = vi->z_logical_clusterbits;
+       const unsigned int lomask = (1 << lclusterbits) - 1;
+       unsigned int vcnt, base, lo, encodebits, nblk;
+       int i;
+       u8 *in, type;
+       bool big_pcluster;
+
+       if (1 << amortizedshift == 4)
+               vcnt = 2;
+       else if (1 << amortizedshift == 2 && lclusterbits == 12)
+               vcnt = 16;
+       else
+               return -EOPNOTSUPP;
+
+       big_pcluster = vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1;
+       encodebits = ((vcnt << amortizedshift) - sizeof(__le32)) * 8 / vcnt;
+       base = round_down(eofs, vcnt << amortizedshift);
+       in = m->kaddr + base;
+
+       i = (eofs - base) >> amortizedshift;
+
+       lo = decode_compactedbits(lclusterbits, lomask,
+                                 in, encodebits * i, &type);
+       m->type = type;
+       if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) {
+               m->clusterofs = 1 << lclusterbits;
+
+               /* figure out lookahead_distance: delta[1] if needed */
+               if (lookahead)
+                       m->delta[1] = get_compacted_la_distance(lclusterbits,
+                                                               encodebits,
+                                                               vcnt, in, i);
+               if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT) {
+                       if (!big_pcluster) {
+                               DBG_BUGON(1);
+                               return -EFSCORRUPTED;
+                       }
+                       m->compressedlcs = lo & ~Z_EROFS_VLE_DI_D0_CBLKCNT;
+                       m->delta[0] = 1;
+                       return 0;
+               } else if (i + 1 != (int)vcnt) {
+                       m->delta[0] = lo;
+                       return 0;
+               }
+               /*
+                * since the last lcluster in the pack is special,
+                * of which lo saves delta[1] rather than delta[0].
+                * Hence, get delta[0] by the previous lcluster indirectly.
+                */
+               lo = decode_compactedbits(lclusterbits, lomask,
+                                         in, encodebits * (i - 1), &type);
+               if (type != Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD)
+                       lo = 0;
+               else if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT)
+                       lo = 1;
+               m->delta[0] = lo + 1;
+               return 0;
+       }
+       m->clusterofs = lo;
+       m->delta[0] = 0;
+       /* figout out blkaddr (pblk) for HEAD lclusters */
+       if (!big_pcluster) {
+               nblk = 1;
+               while (i > 0) {
+                       --i;
+                       lo = decode_compactedbits(lclusterbits, lomask,
+                                                 in, encodebits * i, &type);
+                       if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD)
+                               i -= lo;
+
+                       if (i >= 0)
+                               ++nblk;
+               }
+       } else {
+               nblk = 0;
+               while (i > 0) {
+                       --i;
+                       lo = decode_compactedbits(lclusterbits, lomask,
+                                                 in, encodebits * i, &type);
+                       if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) {
+                               if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT) {
+                                       --i;
+                                       nblk += lo & ~Z_EROFS_VLE_DI_D0_CBLKCNT;
+                                       continue;
+                               }
+                               if (lo == 1) {
+                                       DBG_BUGON(1);
+                                       /* --i; ++nblk; continue; */
+                                       return -EFSCORRUPTED;
+                               }
+                               i -= lo - 2;
+                               continue;
+                       }
+                       ++nblk;
+               }
+       }
+       in += (vcnt << amortizedshift) - sizeof(__le32);
+       m->pblk = le32_to_cpu(*(__le32 *)in) + nblk;
+       return 0;
+}
+
+static int compacted_load_cluster_from_disk(struct z_erofs_maprecorder *m,
+                                           unsigned long lcn, bool lookahead)
+{
+       struct erofs_inode *const vi = m->inode;
+       const unsigned int lclusterbits = vi->z_logical_clusterbits;
+       const erofs_off_t ebase = round_up(iloc(vi->nid) + vi->inode_isize +
+                                          vi->xattr_isize, 8) +
+               sizeof(struct z_erofs_map_header);
+       const unsigned int totalidx = DIV_ROUND_UP(vi->i_size, EROFS_BLKSIZ);
+       unsigned int compacted_4b_initial, compacted_2b;
+       unsigned int amortizedshift;
+       erofs_off_t pos;
+       int err;
+
+       if (lclusterbits != 12)
+               return -EOPNOTSUPP;
+
+       if (lcn >= totalidx)
+               return -EINVAL;
+
+       m->lcn = lcn;
+       /* used to align to 32-byte (compacted_2b) alignment */
+       compacted_4b_initial = (32 - ebase % 32) / 4;
+       if (compacted_4b_initial == 32 / 4)
+               compacted_4b_initial = 0;
+
+       if (vi->z_advise & Z_EROFS_ADVISE_COMPACTED_2B)
+               compacted_2b = rounddown(totalidx - compacted_4b_initial, 16);
+       else
+               compacted_2b = 0;
+
+       pos = ebase;
+       if (lcn < compacted_4b_initial) {
+               amortizedshift = 2;
+               goto out;
+       }
+       pos += compacted_4b_initial * 4;
+       lcn -= compacted_4b_initial;
+
+       if (lcn < compacted_2b) {
+               amortizedshift = 1;
+               goto out;
+       }
+       pos += compacted_2b * 2;
+       lcn -= compacted_2b;
+       amortizedshift = 2;
+out:
+       pos += lcn * (1 << amortizedshift);
+       err = z_erofs_reload_indexes(m, erofs_blknr(pos));
+       if (err)
+               return err;
+       return unpack_compacted_index(m, amortizedshift, erofs_blkoff(pos),
+                                     lookahead);
+}
+
+static int z_erofs_load_cluster_from_disk(struct z_erofs_maprecorder *m,
+                                         unsigned int lcn, bool lookahead)
+{
+       const unsigned int datamode = m->inode->datalayout;
+
+       if (datamode == EROFS_INODE_FLAT_COMPRESSION_LEGACY)
+               return legacy_load_cluster_from_disk(m, lcn);
+
+       if (datamode == EROFS_INODE_FLAT_COMPRESSION)
+               return compacted_load_cluster_from_disk(m, lcn, lookahead);
+
+       return -EINVAL;
+}
+
+static int z_erofs_extent_lookback(struct z_erofs_maprecorder *m,
+                                  unsigned int lookback_distance)
+{
+       struct erofs_inode *const vi = m->inode;
+       struct erofs_map_blocks *const map = m->map;
+       const unsigned int lclusterbits = vi->z_logical_clusterbits;
+       unsigned long lcn = m->lcn;
+       int err;
+
+       if (lcn < lookback_distance) {
+               erofs_err("bogus lookback distance @ nid %llu",
+                         (unsigned long long)vi->nid);
+               DBG_BUGON(1);
+               return -EFSCORRUPTED;
+       }
+
+       /* load extent head logical cluster if needed */
+       lcn -= lookback_distance;
+       err = z_erofs_load_cluster_from_disk(m, lcn, false);
+       if (err)
+               return err;
+
+       switch (m->type) {
+       case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+               if (!m->delta[0]) {
+                       erofs_err("invalid lookback distance 0 @ nid %llu",
+                                 (unsigned long long)vi->nid);
+                       DBG_BUGON(1);
+                       return -EFSCORRUPTED;
+               }
+               return z_erofs_extent_lookback(m, m->delta[0]);
+       case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
+       case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+               m->headtype = m->type;
+               map->m_la = (lcn << lclusterbits) | m->clusterofs;
+               break;
+       default:
+               erofs_err("unknown type %u @ lcn %lu of nid %llu",
+                         m->type, lcn, (unsigned long long)vi->nid);
+               DBG_BUGON(1);
+               return -EOPNOTSUPP;
+       }
+       return 0;
+}
+
+static int z_erofs_get_extent_compressedlen(struct z_erofs_maprecorder *m,
+                                           unsigned int initial_lcn)
+{
+       struct erofs_inode *const vi = m->inode;
+       struct erofs_map_blocks *const map = m->map;
+       const unsigned int lclusterbits = vi->z_logical_clusterbits;
+       unsigned long lcn;
+       int err;
+
+       DBG_BUGON(m->type != Z_EROFS_VLE_CLUSTER_TYPE_PLAIN &&
+                 m->type != Z_EROFS_VLE_CLUSTER_TYPE_HEAD);
+       if (m->headtype == Z_EROFS_VLE_CLUSTER_TYPE_PLAIN ||
+           !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1)) {
+               map->m_plen = 1 << lclusterbits;
+               return 0;
+       }
+
+       lcn = m->lcn + 1;
+       if (m->compressedlcs)
+               goto out;
+
+       err = z_erofs_load_cluster_from_disk(m, lcn, false);
+       if (err)
+               return err;
+
+       /*
+        * If the 1st NONHEAD lcluster has already been handled initially w/o
+        * valid compressedlcs, which means at least it mustn't be CBLKCNT, or
+        * an internal implemenatation error is detected.
+        *
+        * The following code can also handle it properly anyway, but let's
+        * BUG_ON in the debugging mode only for developers to notice that.
+        */
+       DBG_BUGON(lcn == initial_lcn &&
+                 m->type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD);
+
+       switch (m->type) {
+       case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
+       case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+               /*
+                * if the 1st NONHEAD lcluster is actually PLAIN or HEAD type
+                * rather than CBLKCNT, it's a 1 lcluster-sized pcluster.
+                */
+               m->compressedlcs = 1;
+               break;
+       case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+               if (m->delta[0] != 1)
+                       goto err_bonus_cblkcnt;
+               if (m->compressedlcs)
+                       break;
+               /* fallthrough */
+       default:
+               erofs_err("cannot found CBLKCNT @ lcn %lu of nid %llu",
+                         lcn, vi->nid | 0ULL);
+               DBG_BUGON(1);
+               return -EFSCORRUPTED;
+       }
+out:
+       map->m_plen = m->compressedlcs << lclusterbits;
+       return 0;
+err_bonus_cblkcnt:
+       erofs_err("bogus CBLKCNT @ lcn %lu of nid %llu",
+                 lcn, vi->nid | 0ULL);
+       DBG_BUGON(1);
+       return -EFSCORRUPTED;
+}
+
+static int z_erofs_get_extent_decompressedlen(struct z_erofs_maprecorder *m)
+{
+       struct erofs_inode *const vi = m->inode;
+       struct erofs_map_blocks *map = m->map;
+       unsigned int lclusterbits = vi->z_logical_clusterbits;
+       u64 lcn = m->lcn, headlcn = map->m_la >> lclusterbits;
+       int err;
+
+       do {
+               /* handle the last EOF pcluster (no next HEAD lcluster) */
+               if ((lcn << lclusterbits) >= vi->i_size) {
+                       map->m_llen = vi->i_size - map->m_la;
+                       return 0;
+               }
+
+               err = z_erofs_load_cluster_from_disk(m, lcn, true);
+               if (err)
+                       return err;
+
+               if (m->type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) {
+                       DBG_BUGON(!m->delta[1] &&
+                                 m->clusterofs != 1 << lclusterbits);
+               } else if (m->type == Z_EROFS_VLE_CLUSTER_TYPE_PLAIN ||
+                          m->type == Z_EROFS_VLE_CLUSTER_TYPE_HEAD) {
+                       /* go on until the next HEAD lcluster */
+                       if (lcn != headlcn)
+                               break;
+                       m->delta[1] = 1;
+               } else {
+                       erofs_err("unknown type %u @ lcn %llu of nid %llu",
+                                 m->type, lcn | 0ULL,
+                                 (unsigned long long)vi->nid);
+                       DBG_BUGON(1);
+                       return -EOPNOTSUPP;
+               }
+               lcn += m->delta[1];
+       } while (m->delta[1]);
+
+       map->m_llen = (lcn << lclusterbits) + m->clusterofs - map->m_la;
+       return 0;
+}
+
+int z_erofs_map_blocks_iter(struct erofs_inode *vi,
+                           struct erofs_map_blocks *map,
+                           int flags)
+{
+       struct z_erofs_maprecorder m = {
+               .inode = vi,
+               .map = map,
+               .kaddr = map->mpage,
+       };
+       int err = 0;
+       unsigned int lclusterbits, endoff;
+       unsigned long initial_lcn;
+       unsigned long long ofs, end;
+
+       /* when trying to read beyond EOF, leave it unmapped */
+       if (map->m_la >= vi->i_size) {
+               map->m_llen = map->m_la + 1 - vi->i_size;
+               map->m_la = vi->i_size;
+               map->m_flags = 0;
+               goto out;
+       }
+
+       err = z_erofs_fill_inode_lazy(vi);
+       if (err)
+               goto out;
+
+       lclusterbits = vi->z_logical_clusterbits;
+       ofs = map->m_la;
+       initial_lcn = ofs >> lclusterbits;
+       endoff = ofs & ((1 << lclusterbits) - 1);
+
+       err = z_erofs_load_cluster_from_disk(&m, initial_lcn, false);
+       if (err)
+               goto out;
+
+       map->m_flags = EROFS_MAP_MAPPED | EROFS_MAP_ENCODED;
+       end = (m.lcn + 1ULL) << lclusterbits;
+       switch (m.type) {
+       case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
+       case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
+               if (endoff >= m.clusterofs) {
+                       m.headtype = m.type;
+                       map->m_la = (m.lcn << lclusterbits) | m.clusterofs;
+                       break;
+               }
+               /* m.lcn should be >= 1 if endoff < m.clusterofs */
+               if (!m.lcn) {
+                       erofs_err("invalid logical cluster 0 at nid %llu",
+                                 (unsigned long long)vi->nid);
+                       err = -EFSCORRUPTED;
+                       goto out;
+               }
+               end = (m.lcn << lclusterbits) | m.clusterofs;
+               map->m_flags |= EROFS_MAP_FULL_MAPPED;
+               m.delta[0] = 1;
+               /* fallthrough */
+       case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
+               /* get the correspoinding first chunk */
+               err = z_erofs_extent_lookback(&m, m.delta[0]);
+               if (err)
+                       goto out;
+               break;
+       default:
+               erofs_err("unknown type %u @ offset %llu of nid %llu",
+                         m.type, ofs, (unsigned long long)vi->nid);
+               err = -EOPNOTSUPP;
+               goto out;
+       }
+
+       map->m_llen = end - map->m_la;
+       map->m_pa = blknr_to_addr(m.pblk);
+
+       err = z_erofs_get_extent_compressedlen(&m, initial_lcn);
+       if (err)
+               goto out;
+
+       if (m.headtype == Z_EROFS_VLE_CLUSTER_TYPE_PLAIN)
+               map->m_algorithmformat = Z_EROFS_COMPRESSION_SHIFTED;
+       else
+               map->m_algorithmformat = vi->z_algorithmtype[0];
+
+       if (flags & EROFS_GET_BLOCKS_FIEMAP) {
+               err = z_erofs_get_extent_decompressedlen(&m);
+               if (!err)
+                       map->m_flags |= EROFS_MAP_FULL_MAPPED;
+       }
+
+out:
+       erofs_dbg("m_la %" PRIu64 " m_pa %" PRIu64 " m_llen %" PRIu64 " m_plen %" PRIu64 " m_flags 0%o",
+                 map->m_la, map->m_pa,
+                 map->m_llen, map->m_plen, map->m_flags);
+
+       DBG_BUGON(err < 0 && err != -ENOMEM);
+       return err;
+}
diff --git a/fs/fs.c b/fs/fs.c
index 023f89c..99dac0f 100644 (file)
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -26,6 +26,7 @@
 #include <linux/math64.h>
 #include <efi_loader.h>
 #include <squashfs.h>
+#include <erofs.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -305,6 +306,27 @@ static struct fstype_info fstypes[] = {
                .mkdir = fs_mkdir_unsupported,
        },
 #endif
+#if IS_ENABLED(CONFIG_FS_EROFS)
+       {
+               .fstype = FS_TYPE_EROFS,
+               .name = "erofs",
+               .null_dev_desc_ok = false,
+               .probe = erofs_probe,
+               .opendir = erofs_opendir,
+               .readdir = erofs_readdir,
+               .ls = fs_ls_generic,
+               .read = erofs_read,
+               .size = erofs_size,
+               .close = erofs_close,
+               .closedir = erofs_closedir,
+               .exists = erofs_exists,
+               .uuid = fs_uuid_unsupported,
+               .write = fs_write_unsupported,
+               .ln = fs_ln_unsupported,
+               .unlink = fs_unlink_unsupported,
+               .mkdir = fs_mkdir_unsupported,
+       },
+#endif
        {
                .fstype = FS_TYPE_ANY,
                .name = "unsupported",
index c2f8fad..e49f5bf 100644 (file)
@@ -20,6 +20,7 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <event_internal.h>
 #include <fdtdec.h>
 #include <membuff.h>
 #include <linux/list.h>
@@ -467,6 +468,12 @@ struct global_data {
         */
        char *smbios_version;
 #endif
+#if CONFIG_IS_ENABLED(EVENT)
+       /**
+        * @event_state: Points to the current state of events
+        */
+       struct event_state event_state;
+#endif
 };
 #ifndef DO_DEPS_ONLY
 static_assert(sizeof(struct global_data) == GD_SIZE);
@@ -532,6 +539,12 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
 #define gd_set_multi_dtb_fit(_dtb)
 #endif
 
+#if CONFIG_IS_ENABLED(EVENT_DYNAMIC)
+#define gd_event_state()       ((struct event_state *)&gd->event_state)
+#else
+#define gd_event_state()       NULL
+#endif
+
 /**
  * enum gd_flags - global data flags
  *
index 637de0c..1becc66 100644 (file)
@@ -52,12 +52,6 @@ struct bd_info {
        unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
        unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
        unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
-#if defined(CONFIG_CPM2)
-       unsigned long   bi_cpmfreq;     /* CPM_CLK Freq, in MHz */
-       unsigned long   bi_brgfreq;     /* BRG_CLK Freq, in MHz */
-       unsigned long   bi_sccfreq;     /* SCC_CLK Freq, in MHz */
-       unsigned long   bi_vco;         /* VCO Out from PLL, in MHz */
-#endif
 #if defined(CONFIG_M68K)
        unsigned long   bi_pcifreq;     /* PCI Bus Freq, in MHz */
 #endif
index 3b4d1fd..ed971e5 100644 (file)
@@ -31,7 +31,6 @@
 /*
  * BOOTP options
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
 
 /*
  * MEMORY ORGANIZATION
index 763cb8d..c33616b 100644 (file)
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
 /*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
  * MEMORY ORGANIZATION
  * -Monitor at top of sdram.
  * -The heap is placed below the monitor
index 9f4c3af..25f784e 100644 (file)
 
 #define CONFIG_WATCHDOG_TIMEOUT        5000    /* timeout in milliseconds, max timeout is 6.71sec */
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifdef CONFIG_MCFFEC
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
@@ -52,7 +47,6 @@
 #define CONFIG_SYS_I2C_PINMUX_SET      (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
 
 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
-#define CONFIG_BOOTFILE                "u-boot.bin"
 #ifdef CONFIG_MCFFEC
 #      define CONFIG_IPADDR    192.162.1.2
 #      define CONFIG_NETMASK   255.255.255.0
index 3267149..ff02921 100644 (file)
 #undef CONFIG_MONITOR_IS_IN_RAM                /* no pre-loader required!!! ;-) */
 
 /*
- * BOOTP options
- */
-#undef CONFIG_BOOTP_BOOTFILESIZE
-
-/*
  * Clock configuration: enable only one of the following options
  */
 
index df89a0f..c3fcf73 100644 (file)
        . = DEFINED(env_offset) ? env_offset : .; \
        env/embedded.o(.text);
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifdef CONFIG_MCFFEC
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
index 7926ed4..78904ac 100644 (file)
        . = DEFINED(env_offset) ? env_offset : .; \
        env/embedded.o(.text);
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Available command configuration */
 
 #ifdef CONFIG_MCFFEC
index df95eea..cf87795 100644 (file)
        . = DEFINED(env_offset) ? env_offset : .; \
        env/embedded.o(.text*);
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifdef CONFIG_MCFFEC
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
index 538d9c2..8bbc5f4 100644 (file)
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC83xx_ESDHC_ADDR
 #define CONFIG_HOSTNAME                "mpc837x_rdb"
 #define CONFIG_ROOTPATH                "/nfsroot"
 #define CONFIG_RAMDISKFILE     "rootfs.ext2.gz.uboot"
-#define CONFIG_BOOTFILE                "uImage"
                                /* U-Boot image on TFTP server */
 #define CONFIG_UBOOTPATH       "u-boot.bin"
 #define CONFIG_FDTFILE         "mpc8379_rdb.dtb"
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
deleted file mode 100644 (file)
index 57097b1..0000000
+++ /dev/null
@@ -1,303 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- */
-
-/*
- * mpc8540ads board configuration file
- *
- * Please refer to doc/README.mpc85xx for more info.
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * default CCARBAR is at 0xff700000
- * assume U-Boot is less than 0.5MB
- */
-
-#ifndef CONFIG_HAS_FEC
-#define CONFIG_HAS_FEC         1       /* 8540 has FEC */
-#endif
-
-/*
- * sysclk for MPC85xx
- *
- * Two valid values are:
- *    33000000
- *    66000000
- *
- * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here, so that is now the default.
- * The board, however, can run at 66MHz.  In any event, this value
- * must match the settings of some switches.  Details can be found
- * in the README.mpc85xxads.
- *
- * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
- * 33MHz to accommodate, based on a PCI pin.
- * Note that PCI-X won't work at 33MHz.
- */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE                        /* toggle L2 cache */
-#define CONFIG_BTB                     /* toggle branch predition */
-
-#define CONFIG_SYS_CCSRBAR             0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
-
-#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS     0x51    /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE  128             /* DDR is 128MB */
-#define CONFIG_SYS_DDR_CS0_BNDS        0x00000007      /* 0-128MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG      0x80000002
-#define CONFIG_SYS_DDR_TIMING_1        0x37344321
-#define CONFIG_SYS_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_MODE            0x00000062      /* DLL,normal,seq,4/2.5 */
-#define CONFIG_SYS_DDR_INTERVAL        0x05200100      /* autocharge,no open page */
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_FLASH_BASE          0xff000000      /* start of FLASH 16M */
-
-#define CONFIG_SYS_MAX_FLASH_SECT      64              /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef  CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- *    port-size = 32-bits = BR2[19:20] = 11
- *    no parity checking = BR2[21:22] = 00
- *    SDRAM for MSEL = BR2[24:26] = 011
- *    Valid = BR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
- */
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- *    64MB mask for AM, OR2[0:7] = 1111 1100
- *                XAM, OR2[17:18] = 11
- *    9 columns OR2[19-21] = 010
- *    13 rows   OR2[23-25] = 100
- *    EAD set for extra time OR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_LBC_LCRR            0x00030004    /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR            0x00000000    /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_BSMA1516        \
-                               | LSDMR_RFCR5           \
-                               | LSDMR_PRETOACT3       \
-                               | LSDMR_ACTTORW3        \
-                               | LSDMR_BL8             \
-                               | LSDMR_WRC2            \
-                               | LSDMR_CL3             \
-                               | LSDMR_RFEN            \
-                               )
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
-/*
- * 32KB, 8-bit wide for ADS config reg
- */
-#define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
-
-#define CONFIG_SYS_INIT_RAM_LOCK       1
-#define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x4000          /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_NOPROBES                { {0, 0x69} }
-
-/* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_VIRT        0xc0000000      /* base address */
-#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000      /* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS        0xc0000000
-#define CONFIG_SYS_RIO_MEM_SIZE        0x20000000      /* 128M */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCI1_MEM_VIRT       0x80000000
-#define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
-
-#if defined(CONFIG_PCI)
-
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR   0xe0000000
-    #define PCI_ENET0_MEMADDR  0xe0000000
-    #define PCI_IDSEL_NUMBER   0x0c    /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1   1
-#define CONFIG_TSEC1_NAME      "TSEC0"
-#define CONFIG_TSEC2   1
-#define CONFIG_TSEC2_NAME      "TSEC1"
-#define TSEC1_PHY_ADDR         0
-#define TSEC2_PHY_ADDR         1
-#define TSEC1_PHYIDX           0
-#define TSEC2_PHYIDX           0
-#define TSEC1_FLAGS            TSEC_GIGABIT
-#define TSEC2_FLAGS            TSEC_GIGABIT
-
-#if CONFIG_HAS_FEC
-#define CONFIG_MPC85XX_FEC     1
-#define CONFIG_MPC85XX_FEC_NAME                "FEC"
-#define FEC_PHY_ADDR           3
-#define FEC_PHYIDX             0
-#define FEC_FLAGS              0
-#endif
-
-/* Options are: TSEC[0-1], FEC */
-#define CONFIG_ETHPRIME                "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_IPADDR    192.168.1.253
-
-#define CONFIG_HOSTNAME                "unknown"
-#define CONFIG_ROOTPATH                "/nfsroot"
-#define CONFIG_BOOTFILE                "your.uImage"
-
-#define CONFIG_SERVERIP  192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK   255.255.255.0
-
-#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
-   "netdev=eth0\0"                                                      \
-   "consoledev=ttyS0\0"                                                 \
-   "ramdiskaddr=1000000\0"                                             \
-   "ramdiskfile=your.ramdisk.u-boot\0"                                 \
-   "fdtaddr=400000\0"                                                  \
-   "fdtfile=your.fdt.dtb\0"
-
-#endif /* __CONFIG_H */
index e16d870..093061b 100644 (file)
@@ -30,7 +30,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
-#define CONFIG_BTB                     /* toggle branch predition */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
@@ -49,7 +48,6 @@
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS     0x51    /* CTLR 0 DIMM 0 */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 
 /*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
  * Miscellaneous configurable options
  */
 
 
 #define CONFIG_HOSTNAME         "unknown"
 #define CONFIG_ROOTPATH         "/nfsroot"
-#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
 #define CONFIG_UBOOTPATH       8548cds/u-boot.bin      /* TFTP server */
 
 #define CONFIG_SERVERIP         192.168.1.1
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
deleted file mode 100644 (file)
index d23cf0e..0000000
+++ /dev/null
@@ -1,292 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- */
-
-/*
- * mpc8560ads board configuration file
- *
- * Please refer to doc/README.mpc85xx for more info.
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc. in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/delay.h>
-
-/* High Level Configuration Options */
-#define CONFIG_CPM2            1       /* has CPM2 */
-
-/*
- * default CCARBAR is at 0xff700000
- * assume U-Boot is less than 0.5MB
- */
-
-#define CONFIG_RESET_PHY_R     1       /* Call reset_phy() */
-
-/*
- * sysclk for MPC85xx
- *
- * Two valid values are:
- *    33000000
- *    66000000
- *
- * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here, so that is now the default.
- * The board, however, can run at 66MHz.  In any event, this value
- * must match the settings of some switches.  Details can be found
- * in the README.mpc85xxads.
- */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE                        /* toggle L2 cache */
-#define CONFIG_BTB                     /* toggle branch predition */
-
-#define CONFIG_SYS_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions */
-
-#define CONFIG_SYS_CCSRBAR             0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
-
-#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS     0x51    /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE  128             /* DDR is 128MB */
-#define CONFIG_SYS_DDR_CS0_BNDS        0x00000007      /* 0-128MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG      0x80000002
-#define CONFIG_SYS_DDR_TIMING_1        0x37344321
-#define CONFIG_SYS_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_MODE            0x00000062      /* DLL,normal,seq,4/2.5 */
-#define CONFIG_SYS_DDR_INTERVAL        0x05200100      /* autocharge,no open page */
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_FLASH_BASE          0xff000000      /* start of FLASH 16M */
-
-#define CONFIG_SYS_MAX_FLASH_SECT      64              /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef  CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- *    port-size = 32-bits = BR2[19:20] = 11
- *    no parity checking = BR2[21:22] = 00
- *    SDRAM for MSEL = BR2[24:26] = 011
- *    Valid = BR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
- */
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- *    64MB mask for AM, OR2[0:7] = 1111 1100
- *                XAM, OR2[17:18] = 11
- *    9 columns OR2[19-21] = 010
- *    13 rows   OR2[23-25] = 100
- *    EAD set for extra time OR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_LBC_LCRR            0x00030004    /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR            0x00000000    /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_BSMA1516        \
-                               | LSDMR_RFCR5           \
-                               | LSDMR_PRETOACT3       \
-                               | LSDMR_ACTTORW3        \
-                               | LSDMR_BL8             \
-                               | LSDMR_WRC2            \
-                               | LSDMR_CL3             \
-                               | LSDMR_RFEN            \
-                               )
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
-/*
- * 32KB, 8-bit wide for ADS config reg
- */
-#define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
-
-#define CONFIG_SYS_INIT_RAM_LOCK       1
-#define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x4000          /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
-
-/* Serial Port */
-#define CONFIG_CONS_ON_SCC     /* define if console on SCC */
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_NOPROBES                { {0, 0x69} }
-
-/* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_VIRT        0xc0000000      /* base address */
-#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000      /* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS        0xc0000000
-#define CONFIG_SYS_RIO_MEM_SIZE        0x20000000      /* 128M */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCI1_MEM_VIRT       0x80000000
-#define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
-
-#if defined(CONFIG_PCI)
-
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR   0xe0000000
-    #define PCI_ENET0_MEMADDR  0xe0000000
-    #define PCI_IDSEL_NUMBER   0x0c    /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_TSEC1   1
-#define CONFIG_TSEC1_NAME      "TSEC0"
-#define CONFIG_TSEC2   1
-#define CONFIG_TSEC2_NAME      "TSEC1"
-#define TSEC1_PHY_ADDR         0
-#define TSEC2_PHY_ADDR         1
-#define TSEC1_PHYIDX           0
-#define TSEC2_PHYIDX           0
-#define TSEC1_FLAGS            TSEC_GIGABIT
-#define TSEC2_FLAGS            TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME                "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR    192.168.1.253
-
-#define CONFIG_HOSTNAME                "unknown"
-#define CONFIG_ROOTPATH                "/nfsroot"
-#define CONFIG_BOOTFILE                "your.uImage"
-
-#define CONFIG_SERVERIP  192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK   255.255.255.0
-
-#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
-       "netdev=eth0\0"                                                 \
-       "consoledev=ttyCPM\0"                                           \
-       "ramdiskaddr=1000000\0"                                         \
-       "ramdiskfile=your.ramdisk.u-boot\0"                             \
-       "fdtaddr=400000\0"                                              \
-       "fdtfile=mpc8560ads.dtb\0"
-
-#endif /* __CONFIG_H */
index 106d1e6..5f36951 100644 (file)
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
-#define CONFIG_BTB                     /* toggle branch predition */
 
 
 #define CONFIG_ENABLE_36BIT_PHYS
@@ -171,7 +170,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 
 /* DDR3 Controller Settings */
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
@@ -613,7 +611,6 @@ extern unsigned long get_sdram_size(void);
 #endif
 
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin/* U-Boot image on TFTP server */
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                               \
@@ -643,10 +640,10 @@ extern unsigned long get_sdram_size(void);
        "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
        "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
        "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
-       CONFIG_BOOTMODE
+       BOOTMODE
 
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_BOOTMODE \
+#define BOOTMODE \
        "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
        "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
        "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
@@ -655,7 +652,7 @@ extern unsigned long get_sdram_size(void);
        "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_BOOTMODE \
+#define BOOTMODE \
        "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
        "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
        "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
index e6d5321..045d911 100644 (file)
@@ -58,7 +58,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
@@ -94,7 +93,6 @@
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x52
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin
 
 #define __USB_PHY_TYPE utmi
index d24cfce..f803b51 100644 (file)
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #if defined(CONFIG_TARGET_T1024RDB)
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x51
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_DIU_ADDR    (CONFIG_SYS_CCSRBAR + 0x180000)
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 /*
  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  * disable empty flash sector detection, which is I/O-intensive.
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin /* U-Boot image on TFTP server */
 #define __USB_PHY_TYPE         utmi
 
index 9433f14..8a71807 100644 (file)
@@ -98,7 +98,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x51
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       "u-boot.bin"    /* U-Boot image on TFTP server*/
 
 #define __USB_PHY_TYPE utmi
index a41f9f0..76e00cc 100644 (file)
@@ -88,7 +88,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB             /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR     2
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define CONFIG_SYS_SDRAM_SIZE  2048    /* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1    0x51
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH         "/opt/nfsroot"
-#define CONFIG_BOOTFILE         "uImage"
 #define CONFIG_UBOOTPATH "u-boot.bin"  /* U-Boot image on TFTP server */
 
 #define __USB_PHY_TYPE         utmi
index 7165ba0..35064fe 100644 (file)
@@ -83,7 +83,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB             /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define CONFIG_SYS_SDRAM_SIZE  2048    /* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1    0x51
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH         "/opt/nfsroot"
-#define CONFIG_BOOTFILE         "uImage"
 #define CONFIG_UBOOTPATH "u-boot.bin"  /* U-Boot image on TFTP server */
 
 #define __USB_PHY_TYPE         utmi
index daccd81..8c9e580 100644 (file)
@@ -65,7 +65,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
@@ -94,7 +93,6 @@
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 /*
  * IFC Definitions
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       "u-boot.bin"    /* U-Boot image on TFTP server*/
 
 #define HVBOOT                                 \
index 63805d3..456ed43 100644 (file)
@@ -44,9 +44,6 @@
 #endif /* CONFIG_MTD_RAW_NAND */
 
 /* Environment information */
-
-#define CONFIG_BOOTFILE                "uImage"
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "loadaddr=0x82000000\0" \
        "console=ttyS2,115200n8\0" \
index 96526e1..0954bc0 100644 (file)
@@ -33,9 +33,4 @@
  * NS16550 Configuration
  */
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #endif /* __AST_COMMON_CONFIG_H */
index b93c67b..669a8ec 100644 (file)
 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifdef CONFIG_SD_BOOT
 #else
 
index c9344e8..820c6a9 100644 (file)
 #define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
 
 /*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE      1
-
-/*
  * SDRAM: 1 bank, min 32, max 128 MB
  * Initialized before u-boot gets started.
  */
index 7fce98f..995b009 100644 (file)
 #define CONFIG_ATMEL_LCD_BGR555
 #endif
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE          0x20000000
 #define CONFIG_SYS_SDRAM_SIZE          0x04000000
index 485211c..f523d47 100644 (file)
 #define CONFIG_ATMEL_LCD               1
 #define CONFIG_ATMEL_LCD_BGR555                1
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE      1
-
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE          ATMEL_BASE_CS1
 #define CONFIG_SYS_SDRAM_SIZE          0x04000000
index 973e889..a6f0844 100644 (file)
 /* board specific(not enough SRAM) */
 #define CONFIG_AT91SAM9G45_LCD_BASE            0x73E00000
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE           0x70000000
 #define CONFIG_SYS_SDRAM_SIZE          0x08000000
index f102dbe..1771def 100644 (file)
 #define CONFIG_LCD_INFO_BELOW_LOGO
 #define CONFIG_ATMEL_LCD_RGB565
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #define CONFIG_SYS_SDRAM_BASE          0x20000000
 #define CONFIG_SYS_SDRAM_SIZE          0x08000000
 
index e6d5b99..47c55ba 100644 (file)
 #define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
 
 /*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
  * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
  * NB: in this case, USB 1.1 devices won't be recognized.
  */
index c02d25c..8d74df4 100644 (file)
                "; fi\0"
 
 /*
- * Environment configuration
- */
-#define CONFIG_BOOTFILE                        "uImage"
-
-/*
  * Console configuration
  */
 
index 2135ba7..4f8da59 100644 (file)
@@ -29,7 +29,6 @@
 #define CONFIG_SH_QSPI_BASE    0xE6B10000
 #else
 #define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_FLASH_BASE          0x00000000
 #define CONFIG_SYS_FLASH_SIZE          0x04000000      /* 64 MB */
diff --git a/include/configs/broadcom_bcm96753ref.h b/include/configs/broadcom_bcm96753ref.h
new file mode 100644 (file)
index 0000000..c002985
--- /dev/null
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, \
+                                         230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS             24
+
+/*
+ * 6853
+ */
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
+
+/* U-Boot */
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + SZ_16M)
+
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#endif /* CONFIG_MTD_RAW_NAND */
+
+/*
+ * 96753ref
+ */
index 7ab7f55..612999f 100644 (file)
@@ -17,7 +17,6 @@
 #define CONFIG_SYS_PL310_BASE          L2_PL310_BASE
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
 
-#define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_MXC_GPT_HCLK
 
 /* MMC */
index 05915b4..9d5a038 100644 (file)
@@ -27,7 +27,6 @@
 #define CONFIG_NET_RETRY_COUNT         10
 
 /* Network console */
-#define CONFIG_BOOTP_MAY_FAIL          /* if we don't have DHCP environment */
 
 /* As stated above, the following choices are optional. */
 
index 9d5a63c..e29be3f 100644 (file)
@@ -15,9 +15,6 @@
 #include <configs/x86-common.h>
 #include <configs/x86-chromebook.h>
 
-/* We can rely on running natively, and this saves code size */
-#undef CONFIG_BIOSEMU
-
 #undef CONFIG_STD_DEVICES_SETTINGS
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
                                        "stdout=vidconsole,serial\0" \
index 81315f6..9d3ee7f 100644 (file)
        . = DEFINED(env_offset) ? env_offset : .; \
        env/embedded.o(.text);
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifdef CONFIG_MCFFEC
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
index 975f745..6cb75e5 100644 (file)
@@ -51,8 +51,6 @@
 #define DM9000_IO                      (CONFIG_DM9000_BASE)
 #define DM9000_DATA                    (CONFIG_DM9000_BASE + 4)
 #define        CONFIG_NET_RETRY_COUNT          10
-
-#define        CONFIG_BOOTP_BOOTFILESIZE
 #endif
 
 /*
index 7fb96e8..cad5796 100644 (file)
@@ -76,7 +76,6 @@
 
 #define CONFIG_HOSTNAME                "ccdc"
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "ccdc.img"
 
 #define CONFIG_EXTRA_ENV_SETTINGS                                              \
        "netdev=eth1\0"                                         \
index bd26412..c5a8567 100644 (file)
@@ -59,7 +59,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
@@ -97,7 +96,6 @@
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS1    0x51
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin      /* U-Boot image on TFTP server */
 
 #ifdef CONFIG_TARGET_P4080DS
index 27284f7..5347115 100644 (file)
 #define CONFIG_RED_LED         AT91_PIN_PD31   /* this is the user1 led */
 #define CONFIG_GREEN_LED       AT91_PIN_PD0    /* this is the user2 led */
 
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
 #define CONFIG_SYS_SDRAM_SIZE          0x08000000
index 956a965..fa7afab 100644 (file)
 /*
  * U-Boot general configuration
  */
-#define CONFIG_BOOTFILE                "uImage" /* Boot file name */
 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size */
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 
index 7baae3b..41d469d 100644 (file)
@@ -72,6 +72,5 @@
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SPD_EEPROM              0x4e
-#define CONFIG_BOARD_ECC_SUPPORT       /* this board supports ECC */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */
index f30958f..0a701e7 100644 (file)
@@ -94,8 +94,6 @@
  * U-Boot Commands
  */
 
-#define CONFIG_BOOTFILE                        "uImage"
-
 /*
  * SPL specific defines
  */
index 3059bc0..0637c7d 100644 (file)
 /* TWL4030 */
 
 /* BOOTP/DHCP options */
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_TIMEOFFSET
-#undef CONFIG_BOOTP_VENDOREX
 
 /* Environment information */
 #define CONFIG_EXTRA_ENV_SETTINGS \
index e3e2b6a..c66a481 100644 (file)
@@ -19,7 +19,6 @@
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
 #define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
index 9f765fa..43a179f 100644 (file)
@@ -30,9 +30,6 @@
  * it has to be done after each HCD reset */
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #define BOOT_TARGET_DEVICES(func) \
        func(USB, usb, 0) \
        func(MMC, mmc, 1) \
index e71dd24..229e1a3 100644 (file)
@@ -26,9 +26,6 @@
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              19000000
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_bootcmd.h>
 #endif
index 6ad8722..d983cb7 100644 (file)
  * Environment is in the second sector of the first 256k of flash      *
  *----------------------------------------------------------------------*/
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #define CONFIG_MCFTMR
 
 #define        CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
index 178b050..cbd1445 100644 (file)
@@ -21,7 +21,6 @@
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
index 2ceefed..f1b2dda 100644 (file)
@@ -18,7 +18,6 @@
 /*
  * Environment
  */
-#define CONFIG_BOOTFILE                        "app.bin"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "upgrade_image=u-boot.bin\0" \
index 2495db9..d936b7f 100644 (file)
@@ -10,8 +10,6 @@
 
 #include <configs/exynos7420-common.h>
 
-#define CONFIG_BOARD_COMMON
-
 #define CONFIG_ESPRESSO7420
 
 #define CONFIG_SYS_SDRAM_BASE          0x40000000
index d88c14a..ef91146 100644 (file)
 
 /* DHCP/BOOTP options */
 #ifdef CONFIG_CMD_DHCP
-#define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_SYS_AUTOLOAD    "n"
 #endif
 
index 52dcf7a..4202c62 100644 (file)
@@ -12,8 +12,6 @@
 
 #include "exynos-common.h"
 
-#define CONFIG_BOARD_COMMON
-
 /* SD/MMC configuration */
 #define CONFIG_MMC_DEFAULT_DEV 0
 
index 90d095d..410243b 100644 (file)
 
 #define CONFIG_SYS_MONITOR_BASE        0x00000000
 
-#define CONFIG_SECURE_BL1_ONLY
-
-/* Secure FW size configuration */
-#ifdef CONFIG_SECURE_BL1_ONLY
-#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
-#else
-#define CONFIG_SEC_FW_SIZE 0
-#endif
-
-/* Configuration of BL1, BL2, ENV Blocks on mmc */
-#define CONFIG_RES_BLOCK_SIZE  (512)
-#define CONFIG_BL1_SIZE        (16 << 10) /*16 K reserved for BL1*/
-#define CONFIG_BL2_SIZE        (512UL << 10UL) /* 512 KB */
-
-#define CONFIG_BL1_OFFSET      (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
-#define CONFIG_BL2_OFFSET      (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
-
-/* U-Boot copy size from boot Media to DRAM.*/
-#define BL2_START_OFFSET       (CONFIG_BL2_OFFSET/512)
-#define BL2_SIZE_BLOC_COUNT    (CONFIG_BL2_SIZE/512)
-
-#define EXYNOS_COPY_SPI_FNPTR_ADDR     0x02020058
-#define SPI_FLASH_UBOOT_POS    (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-
 /* SPI */
 
 /* Ethernet Controllor Driver */
index 00b6778..bcbdfa7 100644 (file)
@@ -21,8 +21,6 @@
 #define FLASH_SIZE             (4 << 20)
 #define CONFIG_SPI_BOOTING
 
-#define CONFIG_BOARD_COMMON
-
 /* Display */
 #ifdef CONFIG_LCD
 #define CONFIG_EXYNOS_FB
index 8d3449f..6b1df63 100644 (file)
@@ -36,8 +36,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
        {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
 
-#define CONFIG_BOARD_COMMON
-
 #define CONFIG_SYS_SDRAM_BASE          0x40000000
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
 /* DRAM Memory Banks */
index 7e13464..7a08c33 100644 (file)
@@ -83,7 +83,6 @@
 /* TODO: Turn into string option and migrate to Kconfig */
 #define CONFIG_HOSTNAME                "gazerbeam"
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 
 #define CONFIG_EXTRA_ENV_SETTINGS                                      \
        "netdev=eth0\0"                                                 \
index c5f9bce..29a0d94 100644 (file)
@@ -41,9 +41,6 @@
 
 #define CONFIG_HIKEY_GPIO
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Initial environment variables */
 
 /*
index 21a984a..09fbbe9 100644 (file)
@@ -104,7 +104,6 @@ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
 /*
  * Environment configuration
  */
-#define CONFIG_BOOTFILE                        "uImage"
 
 /* Cli configuration */
 #define CONFIG_SYS_CBSIZE              SZ_2K
index c8c28bb..aa00b0f 100644 (file)
@@ -100,11 +100,6 @@ setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
 
-/*
- * Environment configuration
- */
-#define CONFIG_BOOTFILE                        "uImage"
-
 /* Cli configuration */
 #define CONFIG_SYS_CBSIZE              SZ_2K
 
index 8de89a4..08b9ec7 100644 (file)
 /*
  * U-Boot environment setup
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
 
 /*
  * The reserved memory
 #define CONFIG_NETDEV                  eth1
 #define CONFIG_HOSTNAME                "ids8313"
 #define CONFIG_ROOTPATH                "/opt/eldk-4.2/ppc_6xx"
-#define CONFIG_BOOTFILE                "ids8313/uImage"
 #define CONFIG_UBOOTPATH               "ids8313/u-boot.bin"
 #define CONFIG_FDTFILE                 "ids8313/ids8313.dtb"
 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
index 6d7d798..91116f1 100644 (file)
 /* Integrator/AP-specific configuration */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* Timer 1 is clocked at 24Mhz */
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Flash settings */
 #define CONFIG_SYS_FLASH_SIZE          0x02000000 /* 32 MiB */
 #define CONFIG_SYS_MAX_FLASH_SECT      128
index 3ff7bb9..467423d 100644 (file)
@@ -29,7 +29,6 @@
 
 #define CONFIG_SERVERIP 192.168.1.100
 #define CONFIG_IPADDR 192.168.1.104
-#define CONFIG_BOOTFILE "uImage"
 
 /*
  * Miscellaneous configurable options
index a1b8c06..6092933 100644 (file)
                                        CONFIG_SYS_SDRAM_BASE) - \
                                        CONFIG_SYS_MALLOC_LEN - \
                                        CONFIG_ENV_SIZE
-
-/*
- * Environment
- */
-#define CONFIG_BOOTFILE                        "app.bin"
-
 #endif /* _CONFIG_IOT_DEVKIT_H_ */
index e4b167d..5aaa31e 100644 (file)
        "partitions=" PARTS_DEFAULT
 
 /* Set the default list of remote processors to boot */
-#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_TARGET_J7200_A72_EVM)
 #define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY                         \
-       "dorprocboot=1\0"                                               \
        "do_main_cpsw0_qsgmii_phyinit=1\0"                              \
        "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;"               \
                 "gpio clear gpio@22_16\0"                              \
 #ifdef DEFAULT_RPROCS
 #undef DEFAULT_RPROCS
 #endif
+#elif defined(CONFIG_TARGET_J721E_A72_EVM)
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY                         \
+       "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;"               \
+                "gpio clear gpio@22_16\0"                              \
+       "main_cpsw0_qsgmii_phyinit="                                    \
+       "if test $board_name = J721EX-PM1-SOM || test $board_name = J721EX-PM2-SOM " \
+       "|| test $board_name = j721e; then " \
+       "do_main_cpsw0_qsgmii_phyinit=1; else "                 \
+       "do_main_cpsw0_qsgmii_phyinit=0; fi;"                   \
+       "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
+                       "test ${boot} = mmc; then "                     \
+               "run init_main_cpsw0_qsgmii_phy;"                       \
+       "fi;\0"
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
 #endif
 
 #ifdef CONFIG_TARGET_J721E_A72_EVM
index d321ebd..85cf516 100644 (file)
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
 #define CONFIG_KM_DEF_ENV_BOOTPARAMS \
        "actual_bank=0\0"
index 8453be8..57d11d6 100644 (file)
@@ -23,7 +23,6 @@
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define SPD_EEPROM_ADDRESS             0x54
@@ -75,7 +74,6 @@
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE_PHYS }
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20) /* Increase max gunzip size */
 #define CONFIG_SYS_BOOTMAPSZ   (256 << 20) /* Increase map for Linux */
 
-#define CONFIG_MISC_INIT_F
-
 #endif
index ca0cb31..707926f 100644 (file)
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x54
index 448749a..9eeb7ef 100644 (file)
@@ -19,7 +19,6 @@
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
index b912db1..83bd6bc 100644 (file)
@@ -50,7 +50,6 @@
 /*
  * U-Boot general configuration
  */
-#define CONFIG_BOOTFILE                "uImage" /* Boot file name */
 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size */
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 
index 0263bb8..8191c85 100644 (file)
@@ -10,7 +10,6 @@
 
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define CONFIG_SYS_SDRAM_SIZE          0x40000000
 
 /* SATA */
index ef57cf6..7735a00 100644 (file)
@@ -10,9 +10,7 @@
 
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define CONFIG_SYS_SDRAM_SIZE          0x20000000
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 
 #ifndef CONFIG_SPL_BUILD
 #undef BOOT_TARGET_DEVICES
index c61865c..7d8d6ee 100644 (file)
 #define BOARD_REV_MASK                 0x001A0000
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define SYS_SDRAM_SIZE_512             0x20000000
 #define SYS_SDRAM_SIZE_1024            0x40000000
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 
 /* ENV */
 #define CONFIG_SYS_FSL_QSPI_BASE       0x40000000
index cbcb3f7..d57f28e 100644 (file)
@@ -11,7 +11,6 @@
 
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define CONFIG_SYS_SDRAM_SIZE          0x40000000
 
 /*
index c9a152e..c51c4f2 100644 (file)
@@ -11,7 +11,6 @@
 
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define CONFIG_SYS_SDRAM_SIZE          0x40000000
 
 /*
index 2e5b804..4e5228a 100644 (file)
@@ -59,8 +59,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
-
 /*
  * Serial Port
  */
index 8c4cb7b..b6501e8 100644 (file)
@@ -54,7 +54,6 @@
 #define CONFIG_SYS_DDR_RAW_TIMING
 #endif
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
@@ -99,7 +98,6 @@
 
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
index 5f6c2a0..824078d 100644 (file)
@@ -77,8 +77,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
-
 /* Serial Port */
 #define CONFIG_SYS_NS16550_SERIAL
 #ifndef CONFIG_DM_SERIAL
index dcee79d..fada8aa 100644 (file)
@@ -79,8 +79,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
-
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE_PHYS }
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 #endif
 
index a517346..8bdfddc 100644 (file)
@@ -40,7 +40,6 @@
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
index ea6831b..e9919cd 100644 (file)
@@ -12,7 +12,6 @@
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 /* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define SPD_EEPROM_ADDRESS             0x51
 #define CONFIG_SYS_SPD_BUS_NUM         0
@@ -92,7 +91,6 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS, \
                                        CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 /*
index 31b578a..c904c9c 100644 (file)
@@ -12,7 +12,6 @@
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 /* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define CONFIG_SYS_SPD_BUS_NUM         0
 
@@ -62,7 +61,6 @@
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE_PHYS }
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 /*
index 14ad84a..8425d17 100644 (file)
@@ -11,7 +11,6 @@
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define CONFIG_SYS_UBOOT_BASE          0x40100000
 
index 3d72c67..2972e3b 100644 (file)
@@ -12,7 +12,6 @@
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 /* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define SPD_EEPROM_ADDRESS             0x51
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS, \
                                        CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 /*
index 8ed1dce..f6ff690 100644 (file)
@@ -13,7 +13,6 @@
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 /* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define SPD_EEPROM_ADDRESS             0x51
 #define CONFIG_SYS_SPD_BUS_NUM         0
index 33b70c8..965fdfe 100644 (file)
@@ -132,7 +132,6 @@ unsigned long long get_qixis_addr(void);
 #endif
 
 /* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
index f2725af..766da39 100644 (file)
@@ -139,7 +139,6 @@ unsigned long long get_qixis_addr(void);
 
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
index 7554de1..1c59a89 100644 (file)
@@ -27,7 +27,6 @@
 #define SPD_EEPROM_ADDRESS     SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM 0       /* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR             2
-#define CONFIG_CHIP_SELECTS_PER_CTRL           4
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR      1
 #endif
index 1c05b08..de77872 100644 (file)
@@ -37,7 +37,6 @@
 #define SPD_EEPROM_ADDRESS     SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM 0       /* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR             2
-#define CONFIG_CHIP_SELECTS_PER_CTRL           4
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR      1
 #endif
index 4f4b571..469989a 100644 (file)
@@ -34,7 +34,6 @@
 #define SPD_EEPROM_ADDRESS             SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM         0       /* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     2
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
 #define CONFIG_SYS_MONITOR_LEN         (936 * 1024)
 
 /* Miscellaneous configurable options */
index 8486cf8..98fb264 100644 (file)
 /* Watchdog */
 
 /*
- * Boot Linux
- */
-#define CONFIG_BOOTFILE                "boot/fitImage"
-
-/*
  * NAND SPL
  */
 #define CONFIG_SPL_TARGET              "u-boot-with-nand-spl.imx"
index 073c5a5..e4df9d8 100644 (file)
@@ -64,6 +64,5 @@
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SYS_SDRAM_SIZE          SZ_1G
-#define CONFIG_BOARD_ECC_SUPPORT       /* this board supports ECC */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */
index 55f64b5..e841c94 100644 (file)
  */
 
 /*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
  * SDRAM: 1 bank, min 32, max 128 MB
  * Initialized before u-boot gets started.
  */
index fd5a9cf..6bde4c2 100644 (file)
 #define XILINX_DCACHE_BYTE_SIZE        32768
 #endif
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* size of console buffer */
 #define        CONFIG_SYS_CBSIZE       512
 /* max number of command args */
index 370f000..ab466b6 100644 (file)
@@ -22,9 +22,6 @@
 
 /* Ethernet */
 
-/* Booting Linux */
-#define CONFIG_BOOTFILE                "uImage"
-
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "update_sd_firmware_filename=u-boot.sd\0" \
index 552bf5a..3fb0003 100644 (file)
@@ -30,9 +30,6 @@
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
 #endif
 
-/* Boot Linux */
-#define CONFIG_BOOTFILE                "uImage"
-
 /* Extra Environments */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "update_sd_firmware_filename=u-boot.sd\0" \
index caad95b..fe096d4 100644 (file)
@@ -44,9 +44,6 @@
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
 #endif
 
-/* Boot Linux */
-#define CONFIG_BOOTFILE                "uImage"
-
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "ubifs_file=filesystem.ubifs\0" \
index 5ff931e..a0e4817 100644 (file)
@@ -18,7 +18,6 @@
 #endif
 
 #endif
-#define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_MXC_GPT_HCLK
 
 #define CONFIG_SYS_BOOTM_LEN   0x1000000
index 75f5cf0..319de9b 100644 (file)
@@ -15,7 +15,6 @@
 #include "imx7ulp_spl.h"
 #endif
 
-#define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_SYS_BOOTM_LEN           0x1000000
 
 /*
index 8f2cbc6..e80d748 100644 (file)
@@ -11,7 +11,6 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_SYS_BOOTM_LEN           0x1000000
 
 #define CONFIG_MMCROOT                  "/dev/mmcblk0p2"  /* USDHC1 */
index 1ce2f4e..c11d13a 100644 (file)
@@ -25,7 +25,6 @@
  */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE                        "fitImage"
 #define CONFIG_HOSTNAME                        "novena"
 
 /* Physical Memory Map */
index 62169af..16c4935 100644 (file)
 #define CONFIG_SYS_BOOTM_LEN           SZ_32M
 
 /*
- * Environment configuration
- */
-#define CONFIG_BOOTFILE                        "uImage"
-
-/*
  * Console configuration
  */
 
index 536dff2..494f58b 100644 (file)
@@ -21,9 +21,6 @@
 #define CONFIG_BOOT_RETRY_TIME         -1
 #define CONFIG_BOOT_RETRY_MIN          30
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /** Extra environment settings */
 #define CONFIG_EXTRA_ENV_SETTINGS      \
                                        "loadaddr=20080000\0"   \
index 8185f4b..3ad6a59 100644 (file)
@@ -50,9 +50,6 @@
 #define CONFIG_BOOT_RETRY_TIME         -1
 #define CONFIG_BOOT_RETRY_MIN          30
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* AHCI support Definitions */
 #ifdef CONFIG_DM_SCSI
 /** Enable 48-bit SATA addressing */
index a482598..616f25e 100644 (file)
@@ -10,8 +10,6 @@
 #include <configs/exynos5420-common.h>
 #include <configs/exynos5-common.h>
 
-#define CONFIG_BOARD_COMMON
-
 #define CONFIG_SYS_SDRAM_BASE          0x40000000
 
 #define TZPC_BASE_OFFSET               0x10000
index 45297b9..e70f5fc 100644 (file)
 /*
  * U-Boot general configuration
  */
-#define CONFIG_BOOTFILE                "zImage" /* Boot file name */
 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size */
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 
index 1caeed6..2232518 100644 (file)
@@ -58,9 +58,4 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR                0x02040000
 
-/* U-Boot copy size from boot Media to DRAM.*/
-#define COPY_BL2_SIZE          0x80000
-#define BL2_START_OFFSET       ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
-#define BL2_SIZE_BLOC_COUNT    (COPY_BL2_SIZE/512)
-
 #endif /* __CONFIG_H */
index 92008cd..9263189 100644 (file)
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
-#define CONFIG_BTB
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_2G
-#define CONFIG_CHIP_SELECTS_PER_CTRL   2
 #else
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_1G
-#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #endif
 #define CONFIG_SYS_SDRAM_SIZE          (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
  */
 #define CONFIG_HOSTNAME                "unknown"
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin /* U-Boot image on TFTP server */
 
 #ifdef __SW_BOOT_NOR
index bcc0781..00aebb9 100644 (file)
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_ARP_TIMEOUT             500 /* millisec */
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /*--------------------------------------------------
  * USB Configuration
  */
index f3196ee..3960a5c 100644 (file)
 #define CONFIG_ATMEL_LCD               1
 #define CONFIG_ATMEL_LCD_BGR555                1
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE      1
-
 /* SDRAM */
 #define PHYS_SDRAM                             0x20000000
 #define PHYS_SDRAM_SIZE                                0x04000000      /* 64 megs */
index 4856f61..8ee8bbb 100644 (file)
 
 #define CONFIG_LCD_IN_PSRAM            1
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE      1
-
 /* SDRAM */
 #define PHYS_SDRAM             0x20000000
 #define PHYS_SDRAM_SIZE                0x04000000      /* 64 megs */
index b205391..48b6e1c 100644 (file)
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
 
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE           0x70000000
 #define CONFIG_SYS_SDRAM_SIZE          0x08000000
diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h
new file mode 100644 (file)
index 0000000..cdd6cdb
--- /dev/null
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+
+#ifndef __POMELO_CONFIG_H__
+#define __POMELO_CONFIG_H__
+
+/* SDRAM Bank #1 start address */
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
+
+/* SIZE of malloc pool */
+#define CONFIG_SYS_INIT_SP_ADDR                (0x29800000 + 0x1a000)
+
+/*BOOT*/
+#define CONFIG_SYS_BOOTM_LEN           0x3c00000
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+       func(SCSI, scsi, 0) \
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "image=Image\0" \
+       BOOTENV \
+       "scriptaddr=0x90100000\0" \
+       "kernel_addr_r=0x90200000\0" \
+       "fdt_addr_r=0x95000000\0"                       \
+       "boot_fit=no\0" \
+       "fdtfile=phytium-pomelo.dtb\0" \
+
+#endif
+
index 30185b1..3295d43 100644 (file)
@@ -36,9 +36,6 @@
 #define CONFIG_SYS_SERIAL0             PER_UART0_CFG
 #define CONFIG_SYS_SERIAL1             PER_UART1_CFG
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* SDRAM Bank #1 */
 #define DDR_BASE                       0x00000000
 #define PHYS_SDRAM_1                   DDR_BASE
index d45f606..f581107 100644 (file)
@@ -67,6 +67,5 @@
 
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MAX_FLASH_SECT      256 /* Sector: 256K, Bank: 64M */
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 
 #endif /* __CONFIG_H */
index e257c0e..296361a 100644 (file)
@@ -43,8 +43,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_CHIP_SELECTS_PER_CTRL   0
-
 #define CONFIG_SYS_BOOT_BLOCK          0x00000000      /* boot TLB */
 
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
@@ -93,7 +91,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       "u-boot.bin"    /* U-Boot image on TFTP server*/
 
 #endif /* __QEMU_PPCE500_H */
index 9542b0d..1b3aa30 100644 (file)
@@ -19,7 +19,6 @@
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
index eb96e50..7716ac2 100644 (file)
 #define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
 
 /*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
  * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
  * NB: in this case, USB 1.1 devices won't be recognized.
  */
index 8bfd1fc..2a00bfa 100644 (file)
@@ -90,7 +90,6 @@
 #define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* BOOTP and DHCP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
 
 #if !defined(CONFIG_SPL_BUILD)
 /* USB configuration */
index d7e86f2..1ea3b65 100644 (file)
@@ -15,6 +15,4 @@
 #undef CONFIG_EXYNOS_FB
 #undef CONFIG_EXYNOS_DP
 
-#define CONFIG_BOARD_COMMON
-
 #endif /* __CONFIG_SMDK_H */
index 38691b6..f26995d 100644 (file)
@@ -15,8 +15,6 @@
 #undef CONFIG_EXYNOS_FB
 #undef CONFIG_EXYNOS_DP
 
-#define CONFIG_BOARD_COMMON
-
 #define CONFIG_SMDK5420                        /* which is in a SMDK5420 */
 
 #define CONFIG_SYS_SDRAM_BASE  0x20000000
index f113fa4..84b8537 100644 (file)
@@ -10,7 +10,6 @@
 
 #include "exynos4-common.h"
 
-#undef CONFIG_BOARD_COMMON
 #undef CONFIG_USB_GADGET_DWC2_OTG_PHY
 
 /* High Level Configuration Options */
 
 #define CONFIG_SYS_INIT_SP_ADDR                0x02040000
 
-/* U-Boot copy size from boot Media to DRAM.*/
-#define        COPY_BL2_SIZE           0x80000
-#define BL2_START_OFFSET       ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
-#define BL2_SIZE_BLOC_COUNT    (COPY_BL2_SIZE/512)
-
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_ENV_SROM_BANK           1
index 10f8fde..5820423 100644 (file)
@@ -91,8 +91,6 @@
 
 /* Boot options */
 
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Environment settings */
 
 /* Console settings */
index 3889a88..2377190 100644 (file)
@@ -57,8 +57,6 @@
 
 /* Boot options */
 
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Environment settings */
 
 #define        CONFIG_EXTRA_ENV_SETTINGS       \
index c082b2d..00d9b4d 100644 (file)
@@ -15,6 +15,4 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
-#define CONFIG_BOARD_COMMON
-
 #endif /* __CONFIG_SNOW_H */
index 0935eae..5caffa6 100644 (file)
@@ -24,9 +24,6 @@
  */
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 
-/* Booting Linux */
-#define CONFIG_BOOTFILE                "zImage"
-
 #define CONFIG_SYS_BOOTM_LEN           (64 << 20)
 
 /* Environment settings */
index 8acddbe..8f1c2de 100644 (file)
@@ -10,9 +10,6 @@
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB */
 
-/* Booting Linux */
-#define CONFIG_BOOTFILE                "fitImage"
-
 /* Environment is in MMC */
 
 /* Extra Environment */
index 06337d4..f387e40 100644 (file)
@@ -11,9 +11,6 @@
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x10000000
 
-/* Booting Linux */
-#define CONFIG_BOOTFILE                "zImage"
-
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_ARP_TIMEOUT             500UL
index 3aa231c..e76438e 100644 (file)
@@ -10,9 +10,6 @@
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on MCV */
 
-/* Booting Linux */
-#define CONFIG_BOOTFILE                "fitImage"
-
 /* Environment is in MMC */
 
 /* Extra Environment */
index 51dc2e4..a06ac6b 100644 (file)
@@ -72,13 +72,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Environment variable
  */
-
-#ifdef CONFIG_FIT
-#define CONFIG_BOOTFILE "kernel.itb"
-#else
-#define CONFIG_BOOTFILE "Image"
-#endif
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "bootfile=" CONFIG_BOOTFILE "\0" \
index d767492..2d4ce3c 100644 (file)
@@ -11,7 +11,6 @@
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on VINING_FPGA */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE                "fitImage"
 #define CONFIG_SYS_BOOTM_LEN   0x2000000       /* 32 MiB */
 
 /* Extra Environment */
index a51a162..4d562d4 100644 (file)
@@ -42,7 +42,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache              */
-#define CONFIG_BTB                     /* toggle branch predition      */
 
 #define CONFIG_SYS_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions      */
 
@@ -61,7 +60,6 @@
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   2
 
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS     0x50    /* CTLR 0 DIMM 0 */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 
 /*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
  * Miscellaneous configurable options
  */
 
index 0b05245..2f0a580 100644 (file)
@@ -10,6 +10,4 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
-#define CONFIG_BOARD_COMMON
-
 #endif /* __CONFIG_SPRING_H */
index 4c464cf..3e6feae 100644 (file)
@@ -31,7 +31,6 @@
        func(USB, usb, 0) \
        func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
-#define CONFIG_BOOTFILE                        "uImage"
 #define CONFIG_EXTRA_ENV_SETTINGS                              \
                        "kernel_addr_r=0x40000000\0"            \
                        "fdtfile=stih410-b2260.dtb\0"           \
index 6e31bd5..290b5eb 100644 (file)
 #define ETH1_BASE_ADDRESS              0xFE110000
 
 /*
- * Environment configuration
- */
-#define CONFIG_BOOTFILE                        "uImage"
-
-/*
  * Console configuration
  */
 
index 3d770f8..d07a8fe 100644 (file)
@@ -33,9 +33,6 @@
 #define CONFIG_SYS_SERIAL0             0x87e024000000
 #define CONFIG_SYS_SERIAL1             0x87e025000000
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
index ca79b03..57e6863 100644 (file)
@@ -19,7 +19,6 @@
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
index c9d3c2d..834943a 100644 (file)
@@ -79,7 +79,6 @@
 #define CONFIG_ROOTPATH                        "/nfs/root/path"
 
 #ifdef CONFIG_FIT
-#define CONFIG_BOOTFILE                        "fitImage"
 #define KERNEL_ADDR_R_OFFSET           "0x05100000"
 #define LINUXBOOT_ENV_SETTINGS \
        "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
        "__nfsboot=run tftpboot\0"
 #else
 #ifdef CONFIG_ARM64
-#define CONFIG_BOOTFILE                        "Image"
 #define LINUXBOOT_CMD                  "booti"
 #define KERNEL_ADDR_R_OFFSET           "0x02080000"
 #else
-#define CONFIG_BOOTFILE                        "zImage"
 #define LINUXBOOT_CMD                  "bootz"
 #define KERNEL_ADDR_R_OFFSET           "0x00208000"
 #endif
index ffa6900..bc40029 100644 (file)
 /*
  * Hardware drivers
  */
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
 
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE          ATMEL_BASE_CS1
index f0c5ceb..b956bd9 100644 (file)
@@ -99,9 +99,6 @@
 #define CONFIG_PL011_CLOCK             24000000
 #endif
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
index 5f119ae..4b958b4 100644 (file)
 
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   127
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Miscellaneous configurable options */
 #define LINUX_BOOT_PARAM_ADDR          (V2M_BASE + 0x2000)
 
index a43fd81..2f02f96 100644 (file)
  */
 
 /*
- * Boot Linux
- */
-
-#define CONFIG_BOOTFILE                        "uImage"
-
-/*
  * SPL
  */
 
index 0efc715..b45d2bb 100644 (file)
@@ -24,7 +24,6 @@
 #define CONFIG_PCI_IO_PHYS     CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE     0xefff
 
-#define CONFIG_BIOSEMU
 #define VIDEO_IO_OFFSET                                0
 #define CONFIG_X86EMU_RAW_IO
 
index 394978b..15fa864 100644 (file)
  * USB configuration
  */
 
-#define CONFIG_BOOTP_BOOTFILESIZE
-
 /* Default environment */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
 #define CONFIG_HOSTNAME                "x86"
-#define CONFIG_BOOTFILE                "bzImage"
 #define CONFIG_RAMDISK_ADDR    0x4000000
 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB)
 #define CONFIG_OTHBOOTARGS     "othbootargs=\0"
index acaf81d..01942ea 100644 (file)
 #define PHYS_SDRAM_1_SIZE              0x10000000      /* Max 256 MB RAM */
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
 
-/* Environment */
-
-/* Booting Linux */
-#define CONFIG_BOOTFILE                "uImage"
-
 /* Extra Environment */
 #define CONFIG_HOSTNAME                "xea"
 
index bc72f5f..20f5a72 100644 (file)
 #define CONFIG_SYS_BAUDRATE_TABLE \
        { 4800, 9600, 19200, 38400, 57600, 115200 }
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_MAY_FAIL
-
 /* Miscellaneous configurable options */
 
 /* Monitor Command Prompt */
index 00c9718..a94ab1f 100644 (file)
 /* Undef unneeded configs */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 
-/* BOOTP options */
-#undef CONFIG_BOOTP_BOOTFILESIZE
-#undef CONFIG_BOOTP_MAY_FAIL
-
 #undef CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_CBSIZE              1024
 
index e51d92f..1f0da1a 100644 (file)
 #define CONFIG_SYS_BAUDRATE_TABLE \
        { 4800, 9600, 19200, 38400, 57600, 115200 }
 
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_MAY_FAIL
-
 #ifdef CONFIG_NAND_ARASAN
 # define CONFIG_SYS_MAX_NAND_DEVICE    1
 #endif
index c3c8b4c..baef561 100644 (file)
@@ -18,9 +18,6 @@
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #undef CONFIG_SYS_INIT_SP_ADDR
 
-/* BOOTP options */
-#undef CONFIG_BOOTP_BOOTFILESIZE
-#undef CONFIG_BOOTP_MAY_FAIL
 #undef CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_CBSIZE              1024
 
index 8c2cdb5..c8cae59 100644 (file)
@@ -97,9 +97,6 @@
 /* U-Boot general configuration */
 /*==============================*/
 
-#define CONFIG_BOARD_POSTCLK_INIT
-
-#define CONFIG_BOOTFILE                        "uImage"
        /* Console I/O Buffer Size  */
 #define CONFIG_SYS_CBSIZE              1024
        /* Boot Argument Buffer Size */
index 780952c..a668453 100644 (file)
@@ -28,7 +28,6 @@
 /* Ethernet driver */
 #if defined(CONFIG_ZYNQ_GEM)
 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_BOOTP_MAY_FAIL
 #endif
 
 /* NOR */
index 02002ac..c420726 100644 (file)
@@ -10,6 +10,7 @@
 #ifndef _DM_DEVICE_INTERNAL_H
 #define _DM_DEVICE_INTERNAL_H
 
+#include <event.h>
 #include <linker_lists.h>
 #include <dm/ofnode.h>
 
@@ -426,4 +427,13 @@ static inline void devres_release_all(struct udevice *dev)
 }
 
 #endif /* ! CONFIG_DEVRES */
+
+static inline int device_notify(const struct udevice *dev, enum event_t type)
+{
+#if CONFIG_IS_ENABLED(DM_EVENT)
+       return event_notify(type, &dev, sizeof(dev));
+#else
+       return 0;
+#endif
+}
 #endif
index e390d32..110d8ae 100644 (file)
@@ -342,7 +342,7 @@ struct efi_open_protocol_info_item {
  */
 struct efi_handler {
        struct list_head link;
-       const efi_guid_t *guid;
+       const efi_guid_t guid;
        void *protocol_interface;
        struct list_head open_infos;
 };
index 21afd7f..7004a6f 100644 (file)
@@ -77,7 +77,7 @@ const char default_environment[] = {
 #ifdef CONFIG_HOSTNAME
        "hostname="     CONFIG_HOSTNAME "\0"
 #endif
-#ifdef CONFIG_BOOTFILE
+#ifdef CONFIG_USE_BOOTFILE
        "bootfile="     CONFIG_BOOTFILE                 "\0"
 #endif
 #ifdef CONFIG_SYS_LOAD_ADDR
diff --git a/include/erofs.h b/include/erofs.h
new file mode 100644 (file)
index 0000000..1fbe82b
--- /dev/null
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EROFS_H_
+#define _EROFS_H_
+
+struct disk_partition;
+
+int erofs_opendir(const char *filename, struct fs_dir_stream **dirsp);
+int erofs_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
+int erofs_probe(struct blk_desc *fs_dev_desc,
+               struct disk_partition *fs_partition);
+int erofs_read(const char *filename, void *buf, loff_t offset,
+              loff_t len, loff_t *actread);
+int erofs_size(const char *filename, loff_t *size);
+int erofs_exists(const char *filename);
+void erofs_close(void);
+void erofs_closedir(struct fs_dir_stream *dirs);
+int erofs_uuid(char *uuid_str);
+
+#endif /* _EROFS_H */
diff --git a/include/event.h b/include/event.h
new file mode 100644 (file)
index 0000000..62e72a7
--- /dev/null
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Events provide a general-purpose way to react to / subscribe to changes
+ * within U-Boot
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __event_h
+#define __event_h
+
+/**
+ * enum event_t - Types of events supported by U-Boot
+ *
+ * @EVT_DM_PRE_PROBE: Device is about to be probed
+ */
+enum event_t {
+       EVT_NONE,
+       EVT_TEST,
+
+       /* Events related to driver model */
+       EVT_DM_POST_INIT,
+       EVT_DM_PRE_PROBE,
+       EVT_DM_POST_PROBE,
+       EVT_DM_PRE_REMOVE,
+       EVT_DM_POST_REMOVE,
+
+       /* Init hooks */
+       EVT_MISC_INIT_F,
+
+       EVT_COUNT
+};
+
+union event_data {
+       /**
+        * struct event_data_test  - test data
+        *
+        * @signal: A value to update the state with
+        */
+       struct event_data_test {
+               int signal;
+       } test;
+
+       /**
+        * struct event_dm - driver model event
+        *
+        * @dev: Device this event relates to
+        */
+       struct event_dm {
+               struct udevice *dev;
+       } dm;
+};
+
+/**
+ * struct event - an event that can be sent and received
+ *
+ * @type: Event type
+ * @data: Data for this particular event
+ */
+struct event {
+       enum event_t type;
+       union event_data data;
+};
+
+/** Function type for event handlers */
+typedef int (*event_handler_t)(void *ctx, struct event *event);
+
+/**
+ * struct evspy_info - information about an event spy
+ *
+ * @func: Function to call when the event is activated (must be first)
+ * @type: Event type
+ * @id: Event id string
+ */
+struct evspy_info {
+       event_handler_t func;
+       enum event_t type;
+#if CONFIG_IS_ENABLED(EVENT_DEBUG)
+       const char *id;
+#endif
+};
+
+/* Declare a new event spy */
+#if CONFIG_IS_ENABLED(EVENT_DEBUG)
+#define _ESPY_REC(_type, _func)   { _func, _type, #_func, }
+#else
+#define _ESPY_REC(_type, _func)   { _func, _type, }
+#endif
+
+static inline const char *event_spy_id(struct evspy_info *spy)
+{
+#if CONFIG_IS_ENABLED(EVENT_DEBUG)
+       return spy->id;
+#else
+       return "?";
+#endif
+}
+
+/*
+ * It seems that LTO will drop list entries if it decides they are not used,
+ * although the conditions that cause this are unclear.
+ *
+ * The example found is the following:
+ *
+ * static int sandbox_misc_init_f(void *ctx, struct event *event)
+ * {
+ *    return sandbox_early_getopt_check();
+ * }
+ * EVENT_SPY(EVT_MISC_INIT_F, sandbox_misc_init_f);
+ *
+ * where EVENT_SPY uses ll_entry_declare()
+ *
+ * In this case, LTO decides to drop the sandbox_misc_init_f() function
+ * (which is fine) but then drops the linker-list entry too. This means
+ * that the code no longer works, in this case sandbox no-longer checks its
+ * command-line arguments properly.
+ *
+ * Without LTO, the KEEP() command in the .lds file is enough to keep the
+ * entry around. But with LTO it seems that the entry has already been
+ * dropped before the link script is considered.
+ *
+ * The only solution I can think of is to mark linker-list entries as 'used'
+ * using an attribute. This should be safe, since we don't actually want to drop
+ * any of these. However this does slightly limit LTO's optimisation choices.
+ */
+#define EVENT_SPY(_type, _func) \
+       static __attribute__((used)) ll_entry_declare(struct evspy_info, \
+                                                     _type, evspy_info) = \
+       _ESPY_REC(_type, _func)
+
+/**
+ * event_register - register a new spy
+ *
+ * @id: Spy ID
+ * @type: Event type to subscribe to
+ * @func: Function to call when the event is sent
+ * @ctx: Context to pass to the function
+ * @return 0 if OK, -ve on error
+ */
+int event_register(const char *id, enum event_t type, event_handler_t func,
+                  void *ctx);
+
+/** event_show_spy_list( - Show a list of event spies */
+void event_show_spy_list(void);
+
+#if CONFIG_IS_ENABLED(EVENT)
+/**
+ * event_notify() - notify spies about an event
+ *
+ * It is possible to pass in union event_data here but that may not be
+ * convenient if the data is elsewhere, or is one of the members of the union.
+ * So this uses a void * for @data, with a separate @size.
+ *
+ * @type: Event type
+ * @data: Event data to be sent (e.g. union_event_data)
+ * @size: Size of data in bytes
+ * @return 0 if OK, -ve on error
+ */
+int event_notify(enum event_t type, void *data, int size);
+
+/**
+ * event_notify_null() - notify spies about an event
+ *
+ * Data is NULL and the size is 0
+ *
+ * @type: Event type
+ * @return 0 if OK, -ve on error
+ */
+int event_notify_null(enum event_t type);
+#else
+static inline int event_notify(enum event_t type, void *data, int size)
+{
+       return 0;
+}
+
+static inline int event_notify_null(enum event_t type)
+{
+       return 0;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(EVENT_DYNAMIC)
+/**
+ * event_uninit() - Clean up dynamic events
+ *
+ * This removes all dynamic event handlers
+ */
+int event_uninit(void);
+
+/**
+ * event_uninit() - Set up dynamic events
+ *
+ * Init a list of dynamic event handlers, so that these can be added as
+ * needed
+ */
+int event_init(void);
+#else
+static inline int event_uninit(void)
+{
+       return 0;
+}
+
+static inline int event_init(void)
+{
+       return 0;
+}
+#endif
+
+#endif
diff --git a/include/event_internal.h b/include/event_internal.h
new file mode 100644 (file)
index 0000000..8432c6f
--- /dev/null
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Internal definitions for events
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __event_internal_h
+#define __event_internal_h
+
+#include <event.h>
+#include <linux/list.h>
+
+/**
+ * struct event_spy - a spy that watches for an event of a particular type
+ *
+ * @id: Spy ID
+ * @type: Event type to subscribe to
+ * @func: Function to call when the event is sent
+ * @ctx: Context to pass to the function
+ */
+struct event_spy {
+       struct list_head sibling_node;
+       const char *id;
+       enum event_t type;
+       event_handler_t func;
+       void *ctx;
+};
+
+struct event_state {
+       struct list_head spy_head;
+};
+
+#endif
index c8df388..b607b00 100644 (file)
@@ -17,6 +17,7 @@ struct cmd_tbl;
 #define FS_TYPE_UBIFS  4
 #define FS_TYPE_BTRFS  5
 #define FS_TYPE_SQUASHFS 6
+#define FS_TYPE_EROFS   7
 
 struct blk_desc;
 
index 20c3976..7449650 100644 (file)
@@ -46,17 +46,6 @@ void board_init_f(ulong dummy);
 int arch_cpu_init(void);
 
 /**
- * arch_cpu_init_dm() - init CPU after driver model is available
- *
- * This is called immediately after driver model is available before
- * relocation. This is similar to arch_cpu_init() but is able to reference
- * devices
- *
- * Return: 0 if OK, -ve on error
- */
-int arch_cpu_init_dm(void);
-
-/**
  * mach_cpu_init() - SoC/machine dependent CPU setup
  *
  * This is called after arch_cpu_init(). It should handle any
@@ -217,7 +206,6 @@ int init_cache_f_r(void);
 int print_cpuinfo(void);
 #endif
 int timer_init(void);
-int misc_init_f(void);
 
 #if defined(CONFIG_DTB_RESELECT)
 int embedded_dtb_select(void);
index ce48d51..8f35c10 100644 (file)
@@ -98,6 +98,8 @@ enum log_category_t {
        LOGC_ACPI,
        /** @LOGC_BOOT: Related to boot process / boot image processing */
        LOGC_BOOT,
+       /** @LOGC_EVENT: Related to event and event handling */
+       LOGC_EVENT,
        /** @LOGC_COUNT: Number of log categories */
        LOGC_COUNT,
        /** @LOGC_END: Sentinel value for lists of log categories */
index 5015c06..18bcd48 100644 (file)
@@ -51,7 +51,7 @@ struct scmi_msg {
  * Caller sets scmi_msg::out_msg_sz to the output message buffer size.
  * On return, scmi_msg::out_msg_sz stores the response payload size.
  *
- * @dev:       SCMI agent device
+ * @dev:       SCMI device
  * @msg:       Message structure reference
  * Return: 0 on success and a negative errno on failure
  */
index ef26e72..a220cb2 100644 (file)
@@ -41,21 +41,64 @@ enum scmi_status_code {
 };
 
 /*
+ * Generic message IDs
+ */
+enum scmi_discovery_id {
+       SCMI_PROTOCOL_VERSION = 0x0,
+       SCMI_PROTOCOL_ATTRIBUTES = 0x1,
+       SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
+};
+
+/*
  * SCMI Clock Protocol
  */
 
 enum scmi_clock_message_id {
+       SCMI_CLOCK_ATTRIBUTES = 0x3,
        SCMI_CLOCK_RATE_SET = 0x5,
        SCMI_CLOCK_RATE_GET = 0x6,
        SCMI_CLOCK_CONFIG_SET = 0x7,
 };
 
+#define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0)
 #define SCMI_CLK_RATE_ASYNC_NOTIFY     BIT(0)
 #define SCMI_CLK_RATE_ASYNC_NORESP     (BIT(0) | BIT(1))
 #define SCMI_CLK_RATE_ROUND_DOWN       0
 #define SCMI_CLK_RATE_ROUND_UP         BIT(2)
 #define SCMI_CLK_RATE_ROUND_CLOSEST    BIT(3)
 
+#define SCMI_CLOCK_NAME_LENGTH_MAX 16
+
+/**
+ * struct scmi_clk_get_nb_out - Response for SCMI_PROTOCOL_ATTRIBUTES command
+ * @status:    SCMI command status
+ * @attributes:        Attributes of the clock protocol, mainly number of clocks exposed
+ */
+struct scmi_clk_protocol_attr_out {
+       s32 status;
+       u32 attributes;
+};
+
+/**
+ * struct scmi_clk_attribute_in - Message payload for SCMI_CLOCK_ATTRIBUTES command
+ * @clock_id:  SCMI clock ID
+ */
+struct scmi_clk_attribute_in {
+       u32 clock_id;
+};
+
+/**
+ * struct scmi_clk_get_nb_out - Response payload for SCMI_CLOCK_ATTRIBUTES command
+ * @status:    SCMI command status
+ * @attributes:        clock attributes
+ * @clock_name:        name of the clock
+ */
+struct scmi_clk_attribute_out {
+       s32 status;
+       u32 attributes;
+       char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX];
+};
+
 /**
  * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command
  * @clock_id:  SCMI clock ID
index e18b39a..655adbf 100644 (file)
  */
 int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn);
 
+/**
+ * LZ4_decompress_safe() - Decompression protected against buffer overflow
+ * @source: source address of the compressed data
+ * @dest: output buffer address of the uncompressed data
+ *     which must be already allocated
+ * @compressedSize: is the precise full size of the compressed block
+ * @maxDecompressedSize: is the size of 'dest' buffer
+ *
+ * Decompresses data from 'source' into 'dest'.
+ * If the source stream is detected malformed, the function will
+ * stop decoding and return a negative result.
+ * This function is protected against buffer overflow exploits,
+ * including malicious data packets. It never writes outside output buffer,
+ * nor reads outside input buffer.
+ *
+ * Return: number of bytes decompressed into destination buffer
+ *     (necessarily <= maxDecompressedSize)
+ *     or a negative result in case of error
+ */
+int LZ4_decompress_safe(const char *source, char *dest,
+       int compressedSize, int maxDecompressedSize);
+
+/**
+ * LZ4_decompress_safe_partial() - Decompress a block of size 'compressedSize'
+ *     at position 'source' into buffer 'dest'
+ * @source: source address of the compressed data
+ * @dest: output buffer address of the decompressed data which must be
+ *     already allocated
+ * @compressedSize: is the precise full size of the compressed block.
+ * @targetOutputSize: the decompression operation will try
+ *     to stop as soon as 'targetOutputSize' has been reached
+ * @maxDecompressedSize: is the size of destination buffer
+ *
+ * This function decompresses a compressed block of size 'compressedSize'
+ * at position 'source' into destination buffer 'dest'
+ * of size 'maxDecompressedSize'.
+ * The function tries to stop decompressing operation as soon as
+ * 'targetOutputSize' has been reached, reducing decompression time.
+ * This function never writes outside of output buffer,
+ * and never reads outside of input buffer.
+ * It is therefore protected against malicious data packets.
+ *
+ * Return: the number of bytes decoded in the destination buffer
+ *     (necessarily <= maxDecompressedSize)
+ *     or a negative result in case of error
+ *
+ */
+int LZ4_decompress_safe_partial(const char *src, char *dst,
+       int compressedSize, int targetOutputSize, int dstCapacity);
 #endif
index 82128ac..d0f3e05 100644 (file)
@@ -552,7 +552,7 @@ efi_status_t efi_search_protocol(const efi_handle_t handle,
                struct efi_handler *protocol;
 
                protocol = list_entry(lhandle, struct efi_handler, link);
-               if (!guidcmp(protocol->guid, protocol_guid)) {
+               if (!guidcmp(&protocol->guid, protocol_guid)) {
                        if (handler)
                                *handler = protocol;
                        return EFI_SUCCESS;
@@ -604,7 +604,7 @@ efi_status_t efi_remove_all_protocols(const efi_handle_t handle)
        list_for_each_entry_safe(protocol, pos, &efiobj->protocols, link) {
                efi_status_t ret;
 
-               ret = efi_remove_protocol(handle, protocol->guid,
+               ret = efi_remove_protocol(handle, &protocol->guid,
                                          protocol->protocol_interface);
                if (ret != EFI_SUCCESS)
                        return ret;
@@ -1131,7 +1131,7 @@ efi_status_t efi_add_protocol(const efi_handle_t handle,
        handler = calloc(1, sizeof(struct efi_handler));
        if (!handler)
                return EFI_OUT_OF_RESOURCES;
-       handler->guid = protocol;
+       memcpy((void *)&handler->guid, protocol, sizeof(efi_guid_t));
        handler->protocol_interface = protocol_interface;
        INIT_LIST_HEAD(&handler->open_infos);
        list_add_tail(&handler->link, &efiobj->protocols);
@@ -1227,7 +1227,7 @@ static efi_status_t efi_get_drivers(efi_handle_t handle,
 
        /* Count all driver associations */
        list_for_each_entry(handler, &handle->protocols, link) {
-               if (protocol && guidcmp(handler->guid, protocol))
+               if (protocol && guidcmp(&handler->guid, protocol))
                        continue;
                list_for_each_entry(item, &handler->open_infos, link) {
                        if (item->info.attributes &
@@ -1249,7 +1249,7 @@ static efi_status_t efi_get_drivers(efi_handle_t handle,
                return EFI_OUT_OF_RESOURCES;
        /* Collect unique driver handles */
        list_for_each_entry(handler, &handle->protocols, link) {
-               if (protocol && guidcmp(handler->guid, protocol))
+               if (protocol && guidcmp(&handler->guid, protocol))
                        continue;
                list_for_each_entry(item, &handler->open_infos, link) {
                        if (item->info.attributes &
@@ -2446,7 +2446,7 @@ static efi_status_t EFIAPI efi_protocols_per_handle(
 
                        protocol = list_entry(protocol_handle,
                                              struct efi_handler, link);
-                       (*protocol_buffer)[j] = (void *)protocol->guid;
+                       (*protocol_buffer)[j] = (void *)&protocol->guid;
                        ++j;
                }
        }
@@ -3094,7 +3094,7 @@ close_next:
                                    (efi_handle_t)image_obj)
                                        continue;
                                r = EFI_CALL(efi_close_protocol
-                                               (efiobj, protocol->guid,
+                                               (efiobj, &protocol->guid,
                                                 info->info.agent_handle,
                                                 info->info.controller_handle
                                                ));
index 5df3593..9611398 100644 (file)
@@ -91,7 +91,7 @@ void efi_print_image_infos(void *pc)
 
        list_for_each_entry(efiobj, &efi_obj_list, link) {
                list_for_each_entry(handler, &efiobj->protocols, link) {
-                       if (!guidcmp(handler->guid, &efi_guid_loaded_image)) {
+                       if (!guidcmp(&handler->guid, &efi_guid_loaded_image)) {
                                efi_print_image_info(
                                        (struct efi_loaded_image_obj *)efiobj,
                                        handler->protocol_interface, pc);
index 046c34e..5337842 100644 (file)
--- a/lib/lz4.c
+++ b/lib/lz4.c
@@ -1,13 +1,63 @@
-// SPDX-License-Identifier: BSD-2-Clause
+// SPDX-License-Identifier: GPL 2.0+ OR BSD-2-Clause
 /*
-   LZ4 - Fast LZ compression algorithm
-   Copyright (C) 2011-2015, Yann Collet.
+ * LZ4 - Fast LZ compression algorithm
+ * Copyright (C) 2011 - 2016, Yann Collet.
+ * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php)
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * You can contact the author at :
+ *     - LZ4 homepage : http://www.lz4.org
+ *     - LZ4 source repository : https://github.com/lz4/lz4
+ */
+#include <common.h>
+#include <compiler.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/bug.h>
+#include <asm/unaligned.h>
+#include <u-boot/lz4.h>
+
+#define FORCE_INLINE inline __attribute__((always_inline))
+
+static FORCE_INLINE u16 LZ4_readLE16(const void *src)
+{
+       return get_unaligned_le16(src);
+}
 
-   You can contact the author at :
-   - LZ4 source repository : https://github.com/Cyan4973/lz4
-   - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c
-*/
+static FORCE_INLINE void LZ4_copy8(void *dst, const void *src)
+{
+       put_unaligned(get_unaligned((const u64 *)src), (u64 *)dst);
+}
+
+typedef  uint8_t BYTE;
+typedef uint16_t U16;
+typedef uint32_t U32;
+typedef  int32_t S32;
+typedef uint64_t U64;
+typedef uintptr_t uptrval;
 
+static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value)
+{
+       put_unaligned(value, (U32 *)memPtr);
+}
 
 /**************************************
 *  Reading and writing into memory
@@ -28,14 +78,17 @@ static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd)
 **************************************/
 #define MINMATCH 4
 
-#define COPYLENGTH 8
+#define WILDCOPYLENGTH 8
 #define LASTLITERALS 5
-#define MFLIMIT (COPYLENGTH+MINMATCH)
-static const int LZ4_minLength = (MFLIMIT+1);
+#define MFLIMIT (WILDCOPYLENGTH + MINMATCH)
 
-#define KB *(1 <<10)
-#define MB *(1 <<20)
-#define GB *(1U<<30)
+/*
+ * ensure it's possible to write 2 x wildcopyLength
+ * without overflowing output buffer
+ */
+#define MATCH_SAFEGUARD_DISTANCE  ((2 * WILDCOPYLENGTH) - MINMATCH)
+
+#define KB (1 <<10)
 
 #define MAXD_LOG 16
 #define MAX_DISTANCE ((1 << MAXD_LOG) - 1)
@@ -45,198 +98,438 @@ static const int LZ4_minLength = (MFLIMIT+1);
 #define RUN_BITS (8-ML_BITS)
 #define RUN_MASK ((1U<<RUN_BITS)-1)
 
+#define LZ4_STATIC_ASSERT(c)   BUILD_BUG_ON(!(c))
 
 /**************************************
 *  Local Structures and types
 **************************************/
 typedef enum { noDict = 0, withPrefix64k, usingExtDict } dict_directive;
 typedef enum { endOnOutputSize = 0, endOnInputSize = 1 } endCondition_directive;
-typedef enum { full = 0, partial = 1 } earlyEnd_directive;
+typedef enum { decode_full_block = 0, partial_decode = 1 } earlyEnd_directive;
 
+#define DEBUGLOG(l, ...) {}    /* disabled */
 
+#ifndef assert
+#define assert(condition) ((void)0)
+#endif
 
-/*******************************
-*  Decompression functions
-*******************************/
 /*
- * This generic decompression function cover all use cases.
- * It shall be instantiated several times, using different sets of directives
- * Note that it is essential this generic function is really inlined,
+ * LZ4_decompress_generic() :
+ * This generic decompression function covers all use cases.
+ * It shall be instantiated several times, using different sets of directives.
+ * Note that it is important for performance that this function really get inlined,
  * in order to remove useless branches during compilation optimization.
  */
-FORCE_INLINE int LZ4_decompress_generic(
-                 const char* const source,
-                 char* const dest,
-                 int inputSize,
-                 int outputSize,         /* If endOnInput==endOnInputSize, this value is the max size of Output Buffer. */
-
-                 int endOnInput,         /* endOnOutputSize, endOnInputSize */
-                 int partialDecoding,    /* full, partial */
-                 int targetOutputSize,   /* only used if partialDecoding==partial */
-                 int dict,               /* noDict, withPrefix64k, usingExtDict */
-                 const BYTE* const lowPrefix,  /* == dest if dict == noDict */
-                 const BYTE* const dictStart,  /* only if dict==usingExtDict */
-                 const size_t dictSize         /* note : = 0 if noDict */
-                 )
+static FORCE_INLINE int LZ4_decompress_generic(
+        const char * const src,
+        char * const dst,
+        int srcSize,
+               /*
+                * If endOnInput == endOnInputSize,
+                * this value is `dstCapacity`
+                */
+        int outputSize,
+        /* endOnOutputSize, endOnInputSize */
+        endCondition_directive endOnInput,
+        /* full, partial */
+        earlyEnd_directive partialDecoding,
+        /* noDict, withPrefix64k, usingExtDict */
+        dict_directive dict,
+        /* always <= dst, == dst when no prefix */
+        const BYTE * const lowPrefix,
+        /* only if dict == usingExtDict */
+        const BYTE * const dictStart,
+        /* note : = 0 if noDict */
+        const size_t dictSize
+        )
 {
-    /* Local Variables */
-    const BYTE* ip = (const BYTE*) source;
-    const BYTE* const iend = ip + inputSize;
-
-    BYTE* op = (BYTE*) dest;
-    BYTE* const oend = op + outputSize;
-    BYTE* cpy;
-    BYTE* oexit = op + targetOutputSize;
-    const BYTE* const lowLimit = lowPrefix - dictSize;
-
-    const BYTE* const dictEnd = (const BYTE*)dictStart + dictSize;
-    const size_t dec32table[] = {4, 1, 2, 1, 4, 4, 4, 4};
-    const size_t dec64table[] = {0, 0, 0, (size_t)-1, 0, 1, 2, 3};
-
-    const int safeDecode = (endOnInput==endOnInputSize);
-    const int checkOffset = ((safeDecode) && (dictSize < (int)(64 KB)));
-
-
-    /* Special cases */
-    if ((partialDecoding) && (oexit> oend-MFLIMIT)) oexit = oend-MFLIMIT;                         /* targetOutputSize too high => decode everything */
-    if ((endOnInput) && (unlikely(outputSize==0))) return ((inputSize==1) && (*ip==0)) ? 0 : -1;  /* Empty output buffer */
-    if ((!endOnInput) && (unlikely(outputSize==0))) return (*ip==0?1:-1);
-
-
-    /* Main Loop */
-    while (1)
-    {
-        unsigned token;
-        size_t length;
-        const BYTE* match;
-
-        /* get literal length */
-        token = *ip++;
-        if ((length=(token>>ML_BITS)) == RUN_MASK)
-        {
-            unsigned s;
-            do
-            {
-                s = *ip++;
-                length += s;
-            }
-            while (likely((endOnInput)?ip<iend-RUN_MASK:1) && (s==255));
-            if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)(op))) goto _output_error;   /* overflow detection */
-            if ((safeDecode) && unlikely((size_t)(ip+length)<(size_t)(ip))) goto _output_error;   /* overflow detection */
-        }
-
-        /* copy literals */
-        cpy = op+length;
-        if (((endOnInput) && ((cpy>(partialDecoding?oexit:oend-MFLIMIT)) || (ip+length>iend-(2+1+LASTLITERALS))) )
-            || ((!endOnInput) && (cpy>oend-COPYLENGTH)))
-        {
-            if (partialDecoding)
-            {
-                if (cpy > oend) goto _output_error;                           /* Error : write attempt beyond end of output buffer */
-                if ((endOnInput) && (ip+length > iend)) goto _output_error;   /* Error : read attempt beyond end of input buffer */
-            }
-            else
-            {
-                if ((!endOnInput) && (cpy != oend)) goto _output_error;       /* Error : block decoding must stop exactly there */
-                if ((endOnInput) && ((ip+length != iend) || (cpy > oend))) goto _output_error;   /* Error : input must be consumed */
-            }
-            memcpy(op, ip, length);
-            ip += length;
-            op += length;
-            break;     /* Necessarily EOF, due to parsing restrictions */
-        }
-        LZ4_wildCopy(op, ip, cpy);
-        ip += length; op = cpy;
-
-        /* get offset */
-        match = cpy - LZ4_readLE16(ip); ip+=2;
-        if ((checkOffset) && (unlikely(match < lowLimit))) goto _output_error;   /* Error : offset outside destination buffer */
-
-        /* get matchlength */
-        length = token & ML_MASK;
-        if (length == ML_MASK)
-        {
-            unsigned s;
-            do
-            {
-                if ((endOnInput) && (ip > iend-LASTLITERALS)) goto _output_error;
-                s = *ip++;
-                length += s;
-            } while (s==255);
-            if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)op)) goto _output_error;   /* overflow detection */
-        }
-        length += MINMATCH;
-
-        /* check external dictionary */
-        if ((dict==usingExtDict) && (match < lowPrefix))
-        {
-            if (unlikely(op+length > oend-LASTLITERALS)) goto _output_error;   /* doesn't respect parsing restriction */
-
-            if (length <= (size_t)(lowPrefix-match))
-            {
-                /* match can be copied as a single segment from external dictionary */
-                match = dictEnd - (lowPrefix-match);
-                memmove(op, match, length); op += length;
-            }
-            else
-            {
-                /* match encompass external dictionary and current segment */
-                size_t copySize = (size_t)(lowPrefix-match);
-                memcpy(op, dictEnd - copySize, copySize);
-                op += copySize;
-                copySize = length - copySize;
-                if (copySize > (size_t)(op-lowPrefix))   /* overlap within current segment */
-                {
-                    BYTE* const endOfMatch = op + copySize;
-                    const BYTE* copyFrom = lowPrefix;
-                    while (op < endOfMatch) *op++ = *copyFrom++;
-                }
-                else
-                {
-                    memcpy(op, lowPrefix, copySize);
-                    op += copySize;
-                }
-            }
-            continue;
-        }
-
-        /* copy repeated sequence */
-        cpy = op + length;
-        if (unlikely((op-match)<8))
-        {
-            const size_t dec64 = dec64table[op-match];
-            op[0] = match[0];
-            op[1] = match[1];
-            op[2] = match[2];
-            op[3] = match[3];
-            match += dec32table[op-match];
-            LZ4_copy4(op+4, match);
-            op += 8; match -= dec64;
-        } else { LZ4_copy8(op, match); op+=8; match+=8; }
-
-        if (unlikely(cpy>oend-12))
-        {
-            if (cpy > oend-LASTLITERALS) goto _output_error;    /* Error : last LASTLITERALS bytes must be literals */
-            if (op < oend-8)
-            {
-                LZ4_wildCopy(op, match, oend-8);
-                match += (oend-8) - op;
-                op = oend-8;
-            }
-            while (op<cpy) *op++ = *match++;
-        }
-        else
-            LZ4_wildCopy(op, match, cpy);
-        op=cpy;   /* correction */
-    }
-
-    /* end of decoding */
-    if (endOnInput)
-       return (int) (((char*)op)-dest);     /* Nb of output bytes decoded */
-    else
-       return (int) (((const char*)ip)-source);   /* Nb of input bytes read */
-
-    /* Overflow error detected */
+       const BYTE *ip = (const BYTE *) src;
+       const BYTE * const iend = ip + srcSize;
+
+       BYTE *op = (BYTE *) dst;
+       BYTE * const oend = op + outputSize;
+       BYTE *cpy;
+
+       const BYTE * const dictEnd = (const BYTE *)dictStart + dictSize;
+       static const unsigned int inc32table[8] = {0, 1, 2, 1, 0, 4, 4, 4};
+       static const int dec64table[8] = {0, 0, 0, -1, -4, 1, 2, 3};
+
+       const int safeDecode = (endOnInput == endOnInputSize);
+       const int checkOffset = ((safeDecode) && (dictSize < (int)(64 * KB)));
+
+       /* Set up the "end" pointers for the shortcut. */
+       const BYTE *const shortiend = iend -
+               (endOnInput ? 14 : 8) /*maxLL*/ - 2 /*offset*/;
+       const BYTE *const shortoend = oend -
+               (endOnInput ? 14 : 8) /*maxLL*/ - 18 /*maxML*/;
+
+       DEBUGLOG(5, "%s (srcSize:%i, dstSize:%i)", __func__,
+                srcSize, outputSize);
+
+       /* Special cases */
+       assert(lowPrefix <= op);
+       assert(src != NULL);
+
+       /* Empty output buffer */
+       if ((endOnInput) && (unlikely(outputSize == 0)))
+               return ((srcSize == 1) && (*ip == 0)) ? 0 : -1;
+
+       if ((!endOnInput) && (unlikely(outputSize == 0)))
+               return (*ip == 0 ? 1 : -1);
+
+       if ((endOnInput) && unlikely(srcSize == 0))
+               return -1;
+
+       /* Main Loop : decode sequences */
+       while (1) {
+               size_t length;
+               const BYTE *match;
+               size_t offset;
+
+               /* get literal length */
+               unsigned int const token = *ip++;
+               length = token>>ML_BITS;
+
+               /* ip < iend before the increment */
+               assert(!endOnInput || ip <= iend);
+
+               /*
+                * A two-stage shortcut for the most common case:
+                * 1) If the literal length is 0..14, and there is enough
+                * space, enter the shortcut and copy 16 bytes on behalf
+                * of the literals (in the fast mode, only 8 bytes can be
+                * safely copied this way).
+                * 2) Further if the match length is 4..18, copy 18 bytes
+                * in a similar manner; but we ensure that there's enough
+                * space in the output for those 18 bytes earlier, upon
+                * entering the shortcut (in other words, there is a
+                * combined check for both stages).
+                *
+                * The & in the likely() below is intentionally not && so that
+                * some compilers can produce better parallelized runtime code
+                */
+               if ((endOnInput ? length != RUN_MASK : length <= 8)
+                  /*
+                   * strictly "less than" on input, to re-enter
+                   * the loop with at least one byte
+                   */
+                  && likely((endOnInput ? ip < shortiend : 1) &
+                            (op <= shortoend))) {
+                       /* Copy the literals */
+                       memcpy(op, ip, endOnInput ? 16 : 8);
+                       op += length; ip += length;
+
+                       /*
+                        * The second stage:
+                        * prepare for match copying, decode full info.
+                        * If it doesn't work out, the info won't be wasted.
+                        */
+                       length = token & ML_MASK; /* match length */
+                       offset = LZ4_readLE16(ip);
+                       ip += 2;
+                       match = op - offset;
+                       assert(match <= op); /* check overflow */
+
+                       /* Do not deal with overlapping matches. */
+                       if ((length != ML_MASK) &&
+                           (offset >= 8) &&
+                           (dict == withPrefix64k || match >= lowPrefix)) {
+                               /* Copy the match. */
+                               memcpy(op + 0, match + 0, 8);
+                               memcpy(op + 8, match + 8, 8);
+                               memcpy(op + 16, match + 16, 2);
+                               op += length + MINMATCH;
+                               /* Both stages worked, load the next token. */
+                               continue;
+                       }
+
+                       /*
+                        * The second stage didn't work out, but the info
+                        * is ready. Propel it right to the point of match
+                        * copying.
+                        */
+                       goto _copy_match;
+               }
+
+               /* decode literal length */
+               if (length == RUN_MASK) {
+                       unsigned int s;
+
+                       if (unlikely(endOnInput ? ip >= iend - RUN_MASK : 0)) {
+                               /* overflow detection */
+                               goto _output_error;
+                       }
+                       do {
+                               s = *ip++;
+                               length += s;
+                       } while (likely(endOnInput
+                               ? ip < iend - RUN_MASK
+                               : 1) & (s == 255));
+
+                       if ((safeDecode)
+                           && unlikely((uptrval)(op) +
+                                       length < (uptrval)(op))) {
+                               /* overflow detection */
+                               goto _output_error;
+                       }
+                       if ((safeDecode)
+                           && unlikely((uptrval)(ip) +
+                                       length < (uptrval)(ip))) {
+                               /* overflow detection */
+                               goto _output_error;
+                       }
+               }
+
+               /* copy literals */
+               cpy = op + length;
+               LZ4_STATIC_ASSERT(MFLIMIT >= WILDCOPYLENGTH);
+
+               if (((endOnInput) && ((cpy > oend - MFLIMIT)
+                       || (ip + length > iend - (2 + 1 + LASTLITERALS))))
+                       || ((!endOnInput) && (cpy > oend - WILDCOPYLENGTH))) {
+                       if (partialDecoding) {
+                               if (cpy > oend) {
+                                       /*
+                                        * Partial decoding :
+                                        * stop in the middle of literal segment
+                                        */
+                                       cpy = oend;
+                                       length = oend - op;
+                               }
+                               if ((endOnInput)
+                                       && (ip + length > iend)) {
+                                       /*
+                                        * Error :
+                                        * read attempt beyond
+                                        * end of input buffer
+                                        */
+                                       goto _output_error;
+                               }
+                       } else {
+                               if ((!endOnInput)
+                                       && (cpy != oend)) {
+                                       /*
+                                        * Error :
+                                        * block decoding must
+                                        * stop exactly there
+                                        */
+                                       goto _output_error;
+                               }
+                               if ((endOnInput)
+                                       && ((ip + length != iend)
+                                       || (cpy > oend))) {
+                                       /*
+                                        * Error :
+                                        * input must be consumed
+                                        */
+                                       goto _output_error;
+                               }
+                       }
+
+                       /*
+                        * supports overlapping memory regions; only matters
+                        * for in-place decompression scenarios
+                        */
+                       memmove(op, ip, length);
+                       ip += length;
+                       op += length;
+
+                       /* Necessarily EOF, due to parsing restrictions */
+                       if (!partialDecoding || (cpy == oend))
+                               break;
+               } else {
+                       /* may overwrite up to WILDCOPYLENGTH beyond cpy */
+                       LZ4_wildCopy(op, ip, cpy);
+                       ip += length;
+                       op = cpy;
+               }
+
+               /* get offset */
+               offset = LZ4_readLE16(ip);
+               ip += 2;
+               match = op - offset;
+
+               /* get matchlength */
+               length = token & ML_MASK;
+
+_copy_match:
+               if ((checkOffset) && (unlikely(match + dictSize < lowPrefix))) {
+                       /* Error : offset outside buffers */
+                       goto _output_error;
+               }
+
+               /* costs ~1%; silence an msan warning when offset == 0 */
+               /*
+                * note : when partialDecoding, there is no guarantee that
+                * at least 4 bytes remain available in output buffer
+                */
+               if (!partialDecoding) {
+                       assert(oend > op);
+                       assert(oend - op >= 4);
+
+                       LZ4_write32(op, (U32)offset);
+               }
+
+               if (length == ML_MASK) {
+                       unsigned int s;
+
+                       do {
+                               s = *ip++;
+
+                               if ((endOnInput) && (ip > iend - LASTLITERALS))
+                                       goto _output_error;
+
+                               length += s;
+                       } while (s == 255);
+
+                       if ((safeDecode)
+                               && unlikely(
+                                       (uptrval)(op) + length < (uptrval)op)) {
+                               /* overflow detection */
+                               goto _output_error;
+                       }
+               }
+
+               length += MINMATCH;
+
+               /* match starting within external dictionary */
+               if ((dict == usingExtDict) && (match < lowPrefix)) {
+                       if (unlikely(op + length > oend - LASTLITERALS)) {
+                               /* doesn't respect parsing restriction */
+                               if (!partialDecoding)
+                                       goto _output_error;
+                               length = min(length, (size_t)(oend - op));
+                       }
+
+                       if (length <= (size_t)(lowPrefix - match)) {
+                               /*
+                                * match fits entirely within external
+                                * dictionary : just copy
+                                */
+                               memmove(op, dictEnd - (lowPrefix - match),
+                                       length);
+                               op += length;
+                       } else {
+                               /*
+                                * match stretches into both external
+                                * dictionary and current block
+                                */
+                               size_t const copySize = (size_t)(lowPrefix - match);
+                               size_t const restSize = length - copySize;
+
+                               memcpy(op, dictEnd - copySize, copySize);
+                               op += copySize;
+                               if (restSize > (size_t)(op - lowPrefix)) {
+                                       /* overlap copy */
+                                       BYTE * const endOfMatch = op + restSize;
+                                       const BYTE *copyFrom = lowPrefix;
+
+                                       while (op < endOfMatch)
+                                               *op++ = *copyFrom++;
+                               } else {
+                                       memcpy(op, lowPrefix, restSize);
+                                       op += restSize;
+                               }
+                       }
+                       continue;
+               }
+
+               /* copy match within block */
+               cpy = op + length;
+
+               /*
+                * partialDecoding :
+                * may not respect endBlock parsing restrictions
+                */
+               assert(op <= oend);
+               if (partialDecoding &&
+                   (cpy > oend - MATCH_SAFEGUARD_DISTANCE)) {
+                       size_t const mlen = min(length, (size_t)(oend - op));
+                       const BYTE * const matchEnd = match + mlen;
+                       BYTE * const copyEnd = op + mlen;
+
+                       if (matchEnd > op) {
+                               /* overlap copy */
+                               while (op < copyEnd)
+                                       *op++ = *match++;
+                       } else {
+                               memcpy(op, match, mlen);
+                       }
+                       op = copyEnd;
+                       if (op == oend)
+                               break;
+                       continue;
+               }
+
+               if (unlikely(offset < 8)) {
+                       op[0] = match[0];
+                       op[1] = match[1];
+                       op[2] = match[2];
+                       op[3] = match[3];
+                       match += inc32table[offset];
+                       memcpy(op + 4, match, 4);
+                       match -= dec64table[offset];
+               } else {
+                       LZ4_copy8(op, match);
+                       match += 8;
+               }
+
+               op += 8;
+
+               if (unlikely(cpy > oend - MATCH_SAFEGUARD_DISTANCE)) {
+                       BYTE * const oCopyLimit = oend - (WILDCOPYLENGTH - 1);
+
+                       if (cpy > oend - LASTLITERALS) {
+                               /*
+                                * Error : last LASTLITERALS bytes
+                                * must be literals (uncompressed)
+                                */
+                               goto _output_error;
+                       }
+
+                       if (op < oCopyLimit) {
+                               LZ4_wildCopy(op, match, oCopyLimit);
+                               match += oCopyLimit - op;
+                               op = oCopyLimit;
+                       }
+                       while (op < cpy)
+                               *op++ = *match++;
+               } else {
+                       LZ4_copy8(op, match);
+                       if (length > 16)
+                               LZ4_wildCopy(op + 8, match + 8, cpy);
+               }
+               op = cpy; /* wildcopy correction */
+       }
+
+       /* end of decoding */
+       if (endOnInput) {
+               /* Nb of output bytes decoded */
+               return (int) (((char *)op) - dst);
+       } else {
+               /* Nb of input bytes read */
+               return (int) (((const char *)ip) - src);
+       }
+
+       /* Overflow error detected */
 _output_error:
-    return (int) (-(((const char*)ip)-source))-1;
+       return (int) (-(((const char *)ip) - src)) - 1;
+}
+
+int LZ4_decompress_safe(const char *source, char *dest,
+       int compressedSize, int maxDecompressedSize)
+{
+       return LZ4_decompress_generic(source, dest,
+                                     compressedSize, maxDecompressedSize,
+                                     endOnInputSize, decode_full_block,
+                                     noDict, (BYTE *)dest, NULL, 0);
+}
+
+int LZ4_decompress_safe_partial(const char *src, char *dst,
+       int compressedSize, int targetOutputSize, int dstCapacity)
+{
+       dstCapacity = min(targetOutputSize, dstCapacity);
+       return LZ4_decompress_generic(src, dst, compressedSize, dstCapacity,
+                                     endOnInputSize, partial_decode,
+                                     noDict, (BYTE *)dst, NULL, 0);
 }
index ebcb5c0..0d2a365 100644 (file)
 #include <asm/unaligned.h>
 #include <u-boot/lz4.h>
 
-static u16 LZ4_readLE16(const void *src)
-{
-       return get_unaligned_le16(src);
-}
-static void LZ4_copy4(void *dst, const void *src)
-{
-       put_unaligned(get_unaligned((const u32 *)src), (u32 *)dst);
-}
-static void LZ4_copy8(void *dst, const void *src)
-{
-       put_unaligned(get_unaligned((const u64 *)src), (u64 *)dst);
-}
-
-typedef  uint8_t BYTE;
-typedef uint16_t U16;
-typedef uint32_t U32;
-typedef  int32_t S32;
-typedef uint64_t U64;
-
-#define FORCE_INLINE static inline __attribute__((always_inline))
-
 /* lz4.c is unaltered (except removing unrelated code) from github.com/Cyan4973/lz4. */
 #include "lz4.c"       /* #include for inlining, do not link! */
 
@@ -112,7 +91,7 @@ int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn)
                        /* constant folding essential, do not touch params! */
                        ret = LZ4_decompress_generic(in, out, block_size,
                                        end - out, endOnInputSize,
-                                       full, 0, noDict, out, NULL, 0);
+                                       decode_full_block, noDict, out, NULL, 0);
                        if (ret < 0) {
                                ret = -EPROTO;  /* decompression error */
                                break;
index d83e4eb..a896e1e 100644 (file)
@@ -1038,9 +1038,6 @@ static void dhcp_send_request_packet(struct bootp_hdr *bp_offer)
        bcast_ip.s_addr = 0xFFFFFFFFL;
        net_set_udp_header(iphdr, bcast_ip, PORT_BOOTPS, PORT_BOOTPC, iplen);
 
-#ifdef CONFIG_BOOTP_DHCP_REQUEST_DELAY
-       udelay(CONFIG_BOOTP_DHCP_REQUEST_DELAY);
-#endif /* CONFIG_BOOTP_DHCP_REQUEST_DELAY */
        debug("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
        net_send_packet(net_tx_packet, pktlen);
 }
index a6bc234..0b964f6 100644 (file)
@@ -29,26 +29,11 @@ CONFIG_ATMEL_SPI0
 CONFIG_AUTO_ZRELADDR
 CONFIG_BACKSIDE_L2_CACHE
 CONFIG_BCM2835_GPIO
-CONFIG_BIOSEMU
 CONFIG_BITBANGMII_MULTI
-CONFIG_BL1_OFFSET
-CONFIG_BL1_SIZE
-CONFIG_BL2_OFFSET
-CONFIG_BL2_SIZE
 CONFIG_BOARDDIR
 CONFIG_BOARDNAME
-CONFIG_BOARD_COMMON
-CONFIG_BOARD_ECC_SUPPORT
 CONFIG_BOARD_NAME
-CONFIG_BOARD_POSTCLK_INIT
 CONFIG_BOARD_SIZE_LIMIT
-CONFIG_BOOTFILE
-CONFIG_BOOTMODE
-CONFIG_BOOTP_BOOTFILESIZE
-CONFIG_BOOTP_MAY_FAIL
-CONFIG_BOOTP_NISDOMAIN
-CONFIG_BOOTP_TIMEOFFSET
-CONFIG_BOOTP_VENDOREX
 CONFIG_BOOTROM_ERR_REG
 CONFIG_BOOTSCRIPT_ADDR
 CONFIG_BOOTSCRIPT_COPY_RAM
@@ -64,12 +49,9 @@ CONFIG_BS_HDR_ADDR_DEVICE
 CONFIG_BS_HDR_ADDR_RAM
 CONFIG_BS_HDR_SIZE
 CONFIG_BS_SIZE
-CONFIG_BTB
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 CONFIG_CF_DSPI
 CONFIG_CF_SBF
 CONFIG_CHAIN_BOOT_CMD
-CONFIG_CHIP_SELECTS_PER_CTRL
 CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
 CONFIG_CI_UDC_HAS_HOSTPC
 CONFIG_CLK_1000_400_200
@@ -83,7 +65,6 @@ CONFIG_CM_REMAP
 CONFIG_CM_SPD_DETECT
 CONFIG_CM_TCRAM
 CONFIG_COMMON_BOOT
-CONFIG_CONS_ON_SCC
 CONFIG_CONS_SCIF0
 CONFIG_CONS_SCIF1
 CONFIG_CONS_SCIF2
@@ -91,7 +72,6 @@ CONFIG_CONS_SCIF4
 CONFIG_CON_ROT
 CONFIG_CPLD_BR_PRELIM
 CONFIG_CPLD_OR_PRELIM
-CONFIG_CPM2
 CONFIG_CQSPI_REF_CLK
 CONFIG_CUSTOMER_BOARD_SUPPORT
 CONFIG_DB_784MP_GP
@@ -274,7 +254,6 @@ CONFIG_HAS_ETH0
 CONFIG_HAS_ETH1
 CONFIG_HAS_ETH2
 CONFIG_HAS_ETH3
-CONFIG_HAS_FEC
 CONFIG_HAS_FSL_DR_USB
 CONFIG_HAS_FSL_MPH_USB
 CONFIG_HDMI_ENCODER_I2C_ADDR
@@ -689,7 +668,6 @@ CONFIG_RESET_PHY_R
 CONFIG_RESET_TO_RETRY
 CONFIG_RESET_VECTOR_ADDRESS
 CONFIG_RESTORE_FLASH
-CONFIG_RES_BLOCK_SIZE
 CONFIG_RMII
 CONFIG_ROCKCHIP_CHIP_TAG
 CONFIG_ROCKCHIP_MAX_INIT_SIZE
@@ -727,8 +705,6 @@ CONFIG_SC_TIMER_CLK
 CONFIG_SDCARD
 CONFIG_SDRAM_OFFSET_FOR_RT
 CONFIG_SECBOOT
-CONFIG_SECURE_BL1_ONLY
-CONFIG_SEC_FW_SIZE
 CONFIG_SERIAL_BOOT
 CONFIG_SERIAL_FLASH
 CONFIG_SERIAL_SOFTWARE_FIFO
@@ -845,7 +821,6 @@ CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 CONFIG_SYS_AUXCORE_BOOTDATA
 CONFIG_SYS_BARGSIZE
 CONFIG_SYS_BAUDRATE_TABLE
-CONFIG_SYS_BCSR
 CONFIG_SYS_BFTIC3_BASE
 CONFIG_SYS_BFTIC3_SIZE
 CONFIG_SYS_BMAN_CENA_BASE
@@ -1446,11 +1421,6 @@ CONFIG_SYS_LBC_CACHE_BASE
 CONFIG_SYS_LBC_FLASH_BASE
 CONFIG_SYS_LBC_LBCR
 CONFIG_SYS_LBC_LCRR
-CONFIG_SYS_LBC_LSDMR_1
-CONFIG_SYS_LBC_LSDMR_2
-CONFIG_SYS_LBC_LSDMR_3
-CONFIG_SYS_LBC_LSDMR_4
-CONFIG_SYS_LBC_LSDMR_5
 CONFIG_SYS_LBC_LSDMR_COMMON
 CONFIG_SYS_LBC_LSRT
 CONFIG_SYS_LBC_MRTPR
@@ -1535,8 +1505,6 @@ CONFIG_SYS_MPC83xx_ESDHC_OFFSET
 CONFIG_SYS_MPC83xx_USB1_ADDR
 CONFIG_SYS_MPC83xx_USB1_OFFSET
 CONFIG_SYS_MPC85XX_NO_RESETVEC
-CONFIG_SYS_MPC85xx_CPM_ADDR
-CONFIG_SYS_MPC85xx_CPM_OFFSET
 CONFIG_SYS_MPC85xx_DMA
 CONFIG_SYS_MPC85xx_DMA1_OFFSET
 CONFIG_SYS_MPC85xx_DMA2_OFFSET
@@ -1825,10 +1793,6 @@ CONFIG_SYS_RCAR_I2C3_BASE
 CONFIG_SYS_RFD
 CONFIG_SYS_RGMII1_PHY_ADDR
 CONFIG_SYS_RGMII2_PHY_ADDR
-CONFIG_SYS_RIO_MEM_BUS
-CONFIG_SYS_RIO_MEM_PHYS
-CONFIG_SYS_RIO_MEM_SIZE
-CONFIG_SYS_RIO_MEM_VIRT
 CONFIG_SYS_ROM_BASE
 CONFIG_SYS_RSTC_RMR_VAL
 CONFIG_SYS_RTC_BUS_NUM
diff --git a/scripts/event_dump.py b/scripts/event_dump.py
new file mode 100755 (executable)
index 0000000..751f41b
--- /dev/null
@@ -0,0 +1,115 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+
+"""Decode the evspy_info linker list in a U-Boot ELF image"""
+
+from argparse import ArgumentParser
+import os
+import re
+import struct
+import sys
+
+our_path = os.path.dirname(os.path.realpath(__file__))
+src_path = os.path.dirname(our_path)
+
+sys.path.insert(1, os.path.join(our_path, '../tools'))
+
+from binman import elf
+from patman import tools
+
+PREFIX = '_u_boot_list_2_evspy_info_2_'
+RE_EVTYPE = re.compile('%s(.*)' % PREFIX)
+
+def show_sym(fname, data, endian, evtype, sym):
+    """Show information about an evspy entry
+
+    Args:
+        fname (str): Filename of ELF file
+        data (bytes): Data for this symbol
+        endian (str): Endianness to use ('little', 'big', 'auto')
+        evtype (str): Event type, e.g. 'MISC_INIT_F'
+        sym (elf.Symbol): Symbol to show
+    """
+    def _unpack_val(sym_data, offset):
+        start = offset * func_size
+        val_data = sym_data[start:start + func_size]
+        fmt = '%s%s' % ('>' if endian == 'big' else '<',
+                        'L' if func_size == 4 else 'Q')
+        val = struct.unpack(fmt, val_data)[0]
+        return val
+
+    # Get the data, which is a struct evspy_info
+    sym_data = data[sym.offset:sym.offset + sym.size]
+
+    # Figure out the word size of the struct
+    func_size = 4 if sym.size < 16 else 8
+
+    # Read the function name for evspy_info->func
+    while True:
+        # Switch to big-endian if we see a failure
+        func_addr = _unpack_val(sym_data, 0)
+        func_name = elf.GetSymbolFromAddress(fname, func_addr)
+        if not func_name and endian == 'auto':
+            endian = 'big'
+        else:
+            break
+    has_id = sym.size in [12, 24]
+    if has_id:
+        # Find the address of evspy_info->id in the ELF
+        id_addr = _unpack_val(sym_data, 2)
+
+        # Get the file offset for that address
+        id_ofs = elf.GetFileOffset(fname, id_addr)
+
+        # Read out a nul-terminated string
+        id_data = data[id_ofs:id_ofs + 80]
+        pos = id_data.find(0)
+        if pos:
+            id_data = id_data[:pos]
+        id_str = id_data.decode('utf-8')
+    else:
+        id_str = None
+
+    # Find the file/line for the function
+    cmd = ['addr2line', '-e', fname, '%x' % func_addr]
+    out = tools.run(*cmd).strip()
+
+    # Drop the full path if it is the current directory
+    if out.startswith(src_path):
+        out = out[len(src_path) + 1:]
+    print('%-20s  %-30s  %s' % (evtype, id_str or f'f:{func_name}', out))
+
+def show_event_spy_list(fname, endian):
+    """Show a the event-spy- list from a U-Boot image
+
+    Args:
+        fname (str): Filename of ELF file
+        endian (str): Endianness to use ('little', 'big', 'auto')
+    """
+    syms = elf.GetSymbolFileOffset(fname, [PREFIX])
+    data = tools.read_file(fname)
+    print('%-20s  %-30s  %s' % ('Event type', 'Id', 'Source location'))
+    print('%-20s  %-30s  %s' % ('-' * 20, '-' * 30, '-' * 30))
+    for name, sym in syms.items():
+        m_evtype = RE_EVTYPE.search(name)
+        evtype = m_evtype .group(1)
+        show_sym(fname, data, endian, evtype, sym)
+
+def main(argv):
+    """Main program
+
+    Args:
+        argv (list of str): List of program arguments, excluding arvg[0]
+    """
+    epilog = 'Show a list of even spies in a U-Boot EFL file'
+    parser = ArgumentParser(epilog=epilog)
+    parser.add_argument('elf', type=str, help='ELF file to decode')
+    parser.add_argument('-e', '--endian', type=str, default='auto',
+                        help='Big-endian image')
+    parser.add_argument('-t', '--test', action='store_true',
+                        help='Big-endian image')
+    args = parser.parse_args(argv)
+    show_event_spy_list(args.elf, args.endian)
+
+if __name__ == "__main__":
+    main(sys.argv[1:])
index 24c9145..9087788 100644 (file)
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 obj-y += cmd_ut_common.o
 obj-$(CONFIG_AUTOBOOT) += test_autoboot.o
+obj-$(CONFIG_EVENT) += event.o
diff --git a/test/common/event.c b/test/common/event.c
new file mode 100644 (file)
index 0000000..6037ae2
--- /dev/null
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Unit tests for event handling
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <event.h>
+#include <test/common.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+struct test_state {
+       struct udevice *dev;
+       int val;
+};
+
+static int h_adder(void *ctx, struct event *event)
+{
+       struct event_data_test *data = &event->data.test;
+       struct test_state *test_state = ctx;
+
+       test_state->val += data->signal;
+
+       return 0;
+}
+
+static int test_event_base(struct unit_test_state *uts)
+{
+       struct test_state state;
+       int signal;
+
+       state.val = 12;
+       ut_assertok(event_register("wibble", EVT_TEST, h_adder, &state));
+
+       signal = 17;
+
+       /* Check that the handler is called */
+       ut_assertok(event_notify(EVT_TEST, &signal, sizeof(signal)));
+       ut_asserteq(12 + 17, state.val);
+
+       return 0;
+}
+COMMON_TEST(test_event_base, 0);
+
+static int h_probe(void *ctx, struct event *event)
+{
+       struct test_state *test_state = ctx;
+
+       test_state->dev = event->data.dm.dev;
+       switch (event->type) {
+       case EVT_DM_PRE_PROBE:
+               test_state->val |= 1;
+               break;
+       case EVT_DM_POST_PROBE:
+               test_state->val |= 2;
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
+static int test_event_probe(struct unit_test_state *uts)
+{
+       struct test_state state;
+       struct udevice *dev;
+
+       state.val = 0;
+       ut_assertok(event_register("pre", EVT_DM_PRE_PROBE, h_probe, &state));
+       ut_assertok(event_register("post", EVT_DM_POST_PROBE, h_probe, &state));
+
+       /* Probe a device */
+       ut_assertok(uclass_first_device_err(UCLASS_TEST_FDT, &dev));
+
+       /* Check that the handler is called */
+       ut_asserteq(3, state.val);
+
+       return 0;
+}
+COMMON_TEST(test_event_probe, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
index c938e6d..795f207 100644 (file)
@@ -5,7 +5,7 @@
  * Tests scmi_agent uclass and the SCMI drivers implemented in other
  * uclass devices probe when a SCMI server exposes resources.
  *
- * Note in test.dts the protocol@10 node in agent 1. Protocol 0x10 is not
+ * Note in test.dts the protocol@10 node in scmi node. Protocol 0x10 is not
  * implemented in U-Boot SCMI components but the implementation is exepected
  * to not complain on unknown protocol IDs, as long as it is not used. Note
  * in test.dts tests that SCMI drivers probing does not fail for such an
@@ -28,8 +28,7 @@ static int ut_assert_scmi_state_preprobe(struct unit_test_state *uts)
        struct sandbox_scmi_service *scmi_ctx = sandbox_scmi_service_ctx();
 
        ut_assertnonnull(scmi_ctx);
-       if (scmi_ctx->agent_count)
-               ut_asserteq(2, scmi_ctx->agent_count);
+       ut_assertnull(scmi_ctx->agent);
 
        return 0;
 }
@@ -39,35 +38,26 @@ static int ut_assert_scmi_state_postprobe(struct unit_test_state *uts,
 {
        struct sandbox_scmi_devices *scmi_devices;
        struct sandbox_scmi_service *scmi_ctx;
-       struct sandbox_scmi_agent *agent0;
-       struct sandbox_scmi_agent *agent1;
+       struct sandbox_scmi_agent *agent;
 
        /* Device references to check context against test sequence */
        scmi_devices = sandbox_scmi_devices_ctx(dev);
-
        ut_assertnonnull(scmi_devices);
-       ut_asserteq(3, scmi_devices->clk_count);
+       ut_asserteq(2, scmi_devices->clk_count);
        ut_asserteq(1, scmi_devices->reset_count);
        ut_asserteq(2, scmi_devices->regul_count);
 
        /* State of the simulated SCMI server exposed */
        scmi_ctx = sandbox_scmi_service_ctx();
-       agent0 = scmi_ctx->agent[0];
-       agent1 = scmi_ctx->agent[1];
-
-       ut_asserteq(2, scmi_ctx->agent_count);
-
-       ut_assertnonnull(agent0);
-       ut_asserteq(2, agent0->clk_count);
-       ut_assertnonnull(agent0->clk);
-       ut_asserteq(1, agent0->reset_count);
-       ut_assertnonnull(agent0->reset);
-       ut_asserteq(2, agent0->voltd_count);
-       ut_assertnonnull(agent0->voltd);
-
-       ut_assertnonnull(agent1);
-       ut_assertnonnull(agent1->clk);
-       ut_asserteq(1, agent1->clk_count);
+       ut_assertnonnull(scmi_ctx);
+       agent = scmi_ctx->agent;
+       ut_assertnonnull(agent);
+       ut_asserteq(3, agent->clk_count);
+       ut_assertnonnull(agent->clk);
+       ut_asserteq(1, agent->reset_count);
+       ut_assertnonnull(agent->reset);
+       ut_asserteq(2, agent->voltd_count);
+       ut_assertnonnull(agent->voltd);
 
        return 0;
 }
@@ -118,9 +108,8 @@ static int dm_test_scmi_clocks(struct unit_test_state *uts)
 {
        struct sandbox_scmi_devices *scmi_devices;
        struct sandbox_scmi_service *scmi_ctx;
-       struct sandbox_scmi_agent *agent0;
-       struct sandbox_scmi_agent *agent1;
-       struct udevice *dev = NULL;
+       struct sandbox_scmi_agent *agent;
+       struct udevice *dev;
        int ret_dev;
        int ret;
 
@@ -129,48 +118,50 @@ static int dm_test_scmi_clocks(struct unit_test_state *uts)
                return ret;
 
        scmi_devices = sandbox_scmi_devices_ctx(dev);
+       ut_assertnonnull(scmi_devices);
        scmi_ctx = sandbox_scmi_service_ctx();
-       agent0 = scmi_ctx->agent[0];
-       agent1 = scmi_ctx->agent[1];
+       ut_assertnonnull(scmi_ctx);
+       agent = scmi_ctx->agent;
+       ut_assertnonnull(agent);
 
        /* Test SCMI clocks rate manipulation */
+       ut_asserteq(333, agent->clk[0].rate);
+       ut_asserteq(200, agent->clk[1].rate);
+       ut_asserteq(1000, agent->clk[2].rate);
+
        ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0]));
        ut_asserteq(333, clk_get_rate(&scmi_devices->clk[1]));
-       ut_asserteq(44, clk_get_rate(&scmi_devices->clk[2]));
 
        ret_dev = clk_set_rate(&scmi_devices->clk[1], 1088);
        ut_assert(!ret_dev || ret_dev == 1088);
 
-       ut_asserteq(1000, agent0->clk[0].rate);
-       ut_asserteq(1088, agent0->clk[1].rate);
-       ut_asserteq(44, agent1->clk[0].rate);
+       ut_asserteq(1088, agent->clk[0].rate);
+       ut_asserteq(200, agent->clk[1].rate);
+       ut_asserteq(1000, agent->clk[2].rate);
 
        ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0]));
        ut_asserteq(1088, clk_get_rate(&scmi_devices->clk[1]));
-       ut_asserteq(44, clk_get_rate(&scmi_devices->clk[2]));
 
        /* restore original rate for further tests */
        ret_dev = clk_set_rate(&scmi_devices->clk[1], 333);
        ut_assert(!ret_dev || ret_dev == 333);
 
        /* Test SCMI clocks gating manipulation */
-       ut_assert(!agent0->clk[0].enabled);
-       ut_assert(!agent0->clk[1].enabled);
-       ut_assert(!agent1->clk[0].enabled);
+       ut_assert(!agent->clk[0].enabled);
+       ut_assert(!agent->clk[1].enabled);
+       ut_assert(!agent->clk[2].enabled);
 
        ut_asserteq(0, clk_enable(&scmi_devices->clk[1]));
-       ut_asserteq(0, clk_enable(&scmi_devices->clk[2]));
 
-       ut_assert(!agent0->clk[0].enabled);
-       ut_assert(agent0->clk[1].enabled);
-       ut_assert(agent1->clk[0].enabled);
+       ut_assert(agent->clk[0].enabled);
+       ut_assert(!agent->clk[1].enabled);
+       ut_assert(!agent->clk[2].enabled);
 
        ut_assertok(clk_disable(&scmi_devices->clk[1]));
-       ut_assertok(clk_disable(&scmi_devices->clk[2]));
 
-       ut_assert(!agent0->clk[0].enabled);
-       ut_assert(!agent0->clk[1].enabled);
-       ut_assert(!agent1->clk[0].enabled);
+       ut_assert(!agent->clk[0].enabled);
+       ut_assert(!agent->clk[1].enabled);
+       ut_assert(!agent->clk[2].enabled);
 
        return release_sandbox_scmi_test_devices(uts, dev);
 }
@@ -180,7 +171,7 @@ static int dm_test_scmi_resets(struct unit_test_state *uts)
 {
        struct sandbox_scmi_devices *scmi_devices;
        struct sandbox_scmi_service *scmi_ctx;
-       struct sandbox_scmi_agent *agent0;
+       struct sandbox_scmi_agent *agent;
        struct udevice *dev = NULL;
        int ret;
 
@@ -189,17 +180,20 @@ static int dm_test_scmi_resets(struct unit_test_state *uts)
                return ret;
 
        scmi_devices = sandbox_scmi_devices_ctx(dev);
+       ut_assertnonnull(scmi_devices);
        scmi_ctx = sandbox_scmi_service_ctx();
-       agent0 = scmi_ctx->agent[0];
+       ut_assertnonnull(scmi_ctx);
+       agent = scmi_ctx->agent;
+       ut_assertnonnull(agent);
 
        /* Test SCMI resect controller manipulation */
-       ut_assert(!agent0->reset[0].asserted)
+       ut_assert(!agent->reset[0].asserted)
 
        ut_assertok(reset_assert(&scmi_devices->reset[0]));
-       ut_assert(agent0->reset[0].asserted)
+       ut_assert(agent->reset[0].asserted)
 
        ut_assertok(reset_deassert(&scmi_devices->reset[0]));
-       ut_assert(!agent0->reset[0].asserted);
+       ut_assert(!agent->reset[0].asserted);
 
        return release_sandbox_scmi_test_devices(uts, dev);
 }
@@ -209,7 +203,7 @@ static int dm_test_scmi_voltage_domains(struct unit_test_state *uts)
 {
        struct sandbox_scmi_devices *scmi_devices;
        struct sandbox_scmi_service *scmi_ctx;
-       struct sandbox_scmi_agent *agent0;
+       struct sandbox_scmi_agent *agent;
        struct dm_regulator_uclass_plat *uc_pdata;
        struct udevice *dev;
        struct udevice *regul0_dev;
@@ -217,8 +211,11 @@ static int dm_test_scmi_voltage_domains(struct unit_test_state *uts)
        ut_assertok(load_sandbox_scmi_test_devices(uts, &dev));
 
        scmi_devices = sandbox_scmi_devices_ctx(dev);
+       ut_assertnonnull(scmi_devices);
        scmi_ctx = sandbox_scmi_service_ctx();
-       agent0 = scmi_ctx->agent[0];
+       ut_assertnonnull(scmi_ctx);
+       agent = scmi_ctx->agent;
+       ut_assertnonnull(agent);
 
        /* Set/Get an SCMI voltage domain level */
        regul0_dev = scmi_devices->regul[0];
@@ -228,32 +225,32 @@ static int dm_test_scmi_voltage_domains(struct unit_test_state *uts)
        ut_assert(uc_pdata);
 
        ut_assertok(regulator_set_value(regul0_dev, uc_pdata->min_uV));
-       ut_asserteq(agent0->voltd[0].voltage_uv, uc_pdata->min_uV);
+       ut_asserteq(agent->voltd[0].voltage_uv, uc_pdata->min_uV);
 
        ut_assert(regulator_get_value(regul0_dev) == uc_pdata->min_uV);
 
        ut_assertok(regulator_set_value(regul0_dev, uc_pdata->max_uV));
-       ut_asserteq(agent0->voltd[0].voltage_uv, uc_pdata->max_uV);
+       ut_asserteq(agent->voltd[0].voltage_uv, uc_pdata->max_uV);
 
        ut_assert(regulator_get_value(regul0_dev) == uc_pdata->max_uV);
 
        /* Enable/disable SCMI voltage domains */
        ut_assertok(regulator_set_enable(scmi_devices->regul[0], false));
        ut_assertok(regulator_set_enable(scmi_devices->regul[1], false));
-       ut_assert(!agent0->voltd[0].enabled);
-       ut_assert(!agent0->voltd[1].enabled);
+       ut_assert(!agent->voltd[0].enabled);
+       ut_assert(!agent->voltd[1].enabled);
 
        ut_assertok(regulator_set_enable(scmi_devices->regul[0], true));
-       ut_assert(agent0->voltd[0].enabled);
-       ut_assert(!agent0->voltd[1].enabled);
+       ut_assert(agent->voltd[0].enabled);
+       ut_assert(!agent->voltd[1].enabled);
 
        ut_assertok(regulator_set_enable(scmi_devices->regul[1], true));
-       ut_assert(agent0->voltd[0].enabled);
-       ut_assert(agent0->voltd[1].enabled);
+       ut_assert(agent->voltd[0].enabled);
+       ut_assert(agent->voltd[1].enabled);
 
        ut_assertok(regulator_set_enable(scmi_devices->regul[0], false));
-       ut_assert(!agent0->voltd[0].enabled);
-       ut_assert(agent0->voltd[1].enabled);
+       ut_assert(!agent->voltd[0].enabled);
+       ut_assert(agent->voltd[1].enabled);
 
        return release_sandbox_scmi_test_devices(uts, dev);
 }
index a04a7ff..a3f8831 100644 (file)
@@ -66,7 +66,7 @@ def test_avb_mmc_uuid(u_boot_console):
             part_list[cur_partname] = guid_to_check[1]
 
     # lets check all guids with avb get_guid
-    for part, guid in part_list.iteritems():
+    for part, guid in part_list.items():
         avb_guid_resp = u_boot_console.run_command('avb get_uuid %s' % part)
         assert guid == avb_guid_resp.split('UUID: ')[1]
 
index 9f234fb..8ad277d 100644 (file)
@@ -131,7 +131,7 @@ def test_bind_unbind_with_uclass(u_boot_console):
        child2_index = int(child2_line[0].split()[1])
 
        #bind simple_bus as a child of bind-test-child2
-       response = u_boot_console.run_command('bind  {} {} simple_bus'.format(child2_uclass, child2_index, 'simple_bus'))
+       response = u_boot_console.run_command('bind  {} {} simple_bus'.format(child2_uclass, child2_index))
 
        #check that the child is there and its uclass/index pair is right
        tree = u_boot_console.run_command('dm tree')
@@ -152,7 +152,7 @@ def test_bind_unbind_with_uclass(u_boot_console):
        assert child_of_child2_line == ''
 
        #bind simple_bus as a child of bind-test-child2
-       response = u_boot_console.run_command('bind  {} {} simple_bus'.format(child2_uclass, child2_index, 'simple_bus'))
+       response = u_boot_console.run_command('bind  {} {} simple_bus'.format(child2_uclass, child2_index))
 
        #check that the child is there and its uclass/index pair is right
        tree = u_boot_console.run_command('dm tree')
@@ -165,7 +165,7 @@ def test_bind_unbind_with_uclass(u_boot_console):
        assert child_of_child2_index == child2_index + 1
 
        #unbind the child and check it has been removed
-       response = u_boot_console.run_command('unbind  {} {} simple_bus'.format(child2_uclass, child2_index, 'simple_bus'))
+       response = u_boot_console.run_command('unbind  {} {} simple_bus'.format(child2_uclass, child2_index))
        assert response == ''
 
        tree = u_boot_console.run_command('dm tree')
@@ -176,7 +176,7 @@ def test_bind_unbind_with_uclass(u_boot_console):
 
        #unbind the child again and check it doesn't change the tree
        tree_old = u_boot_console.run_command('dm tree')
-       response = u_boot_console.run_command('unbind  {} {} simple_bus'.format(child2_uclass, child2_index, 'simple_bus'))
+       response = u_boot_console.run_command('unbind  {} {} simple_bus'.format(child2_uclass, child2_index))
        tree_new = u_boot_console.run_command('dm tree')
 
        assert response == ''
diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py
new file mode 100644 (file)
index 0000000..b753e80
--- /dev/null
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2021 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+
+import pytest
+import re
+import u_boot_utils as util
+
+# This is only a partial test - coverting 64-bit sandbox. It does not test
+# big-endian images, nor 32-bit images
+@pytest.mark.boardspec('sandbox')
+def test_event_dump(u_boot_console):
+    """Test that the "help" command can be executed."""
+    cons = u_boot_console
+    sandbox = cons.config.build_dir + '/u-boot'
+    out = util.run_and_log(cons, ['scripts/event_dump.py', sandbox])
+    expect = '''.*Event type            Id                              Source location
+--------------------  ------------------------------  ------------------------------
+EVT_MISC_INIT_F       sandbox_misc_init_f             .*arch/sandbox/cpu/start.c:'''
+    assert re.match(expect, out, re.MULTILINE) is not None
diff --git a/test/py/tests/test_fs/test_erofs.py b/test/py/tests/test_fs/test_erofs.py
new file mode 100644 (file)
index 0000000..458a52b
--- /dev/null
@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Huang Jianan <jnhuang95@gmail.com>
+# Author: Huang Jianan <jnhuang95@gmail.com>
+
+import os
+import pytest
+import shutil
+import subprocess
+
+EROFS_SRC_DIR = 'erofs_src_dir'
+EROFS_IMAGE_NAME = 'erofs.img'
+
+def generate_file(name, size):
+    """
+    Generates a file filled with 'x'.
+    """
+    content = 'x' * size
+    file = open(name, 'w')
+    file.write(content)
+    file.close()
+
+def make_erofs_image(build_dir):
+    """
+    Makes the EROFS images used for the test.
+
+    The image is generated at build_dir with the following structure:
+    erofs_src_dir/
+    â”œâ”€â”€ f4096
+    â”œâ”€â”€ f7812
+    â”œâ”€â”€ subdir/
+    â”‚   â””── subdir-file
+    â”œâ”€â”€ symdir -> subdir
+    â””── symfile -> f5096
+    """
+    root = os.path.join(build_dir, EROFS_SRC_DIR)
+    os.makedirs(root)
+
+    # 4096: uncompressed file
+    generate_file(os.path.join(root, 'f4096'), 4096)
+
+    # 7812: Compressed file
+    generate_file(os.path.join(root, 'f7812'), 7812)
+
+    # sub-directory with a single file inside
+    subdir_path = os.path.join(root, 'subdir')
+    os.makedirs(subdir_path)
+    generate_file(os.path.join(subdir_path, 'subdir-file'), 100)
+
+    # symlink
+    os.symlink('subdir', os.path.join(root, 'symdir'))
+    os.symlink('f7812', os.path.join(root, 'symfile'))
+
+    input_path = os.path.join(build_dir, EROFS_SRC_DIR)
+    output_path = os.path.join(build_dir, EROFS_IMAGE_NAME)
+    args = ' '.join([output_path, input_path])
+    subprocess.run(['mkfs.erofs -zlz4 ' + args], shell=True, check=True,
+                   stdout=subprocess.DEVNULL)
+
+def clean_erofs_image(build_dir):
+    """
+    Deletes the image and src_dir at build_dir.
+    """
+    path = os.path.join(build_dir, EROFS_SRC_DIR)
+    shutil.rmtree(path)
+    image_path = os.path.join(build_dir, EROFS_IMAGE_NAME)
+    os.remove(image_path)
+
+def erofs_ls_at_root(u_boot_console):
+    """
+    Test if all the present files and directories were listed.
+    """
+    no_slash = u_boot_console.run_command('erofsls host 0')
+    slash = u_boot_console.run_command('erofsls host 0 /')
+    assert no_slash == slash
+
+    expected_lines = ['./', '../', '4096   f4096', '7812   f7812', 'subdir/',
+                      '<SYM>   symdir', '<SYM>   symfile', '4 file(s), 3 dir(s)']
+
+    output = u_boot_console.run_command('erofsls host 0')
+    for line in expected_lines:
+        assert line in output
+
+def erofs_ls_at_subdir(u_boot_console):
+    """
+    Test if the path resolution works.
+    """
+    expected_lines = ['./', '../', '100   subdir-file', '1 file(s), 2 dir(s)']
+    output = u_boot_console.run_command('erofsls host 0 subdir')
+    for line in expected_lines:
+        assert line in output
+
+def erofs_ls_at_symlink(u_boot_console):
+    """
+    Test if the symbolic link's target resolution works.
+    """
+    output = u_boot_console.run_command('erofsls host 0 symdir')
+    output_subdir = u_boot_console.run_command('erofsls host 0 subdir')
+    assert output == output_subdir
+
+    expected_lines = ['./', '../', '100   subdir-file', '1 file(s), 2 dir(s)']
+    for line in expected_lines:
+        assert line in output
+
+def erofs_ls_at_non_existent_dir(u_boot_console):
+    """
+    Test if the EROFS support will crash when get a nonexistent directory.
+    """
+    out_non_existent = u_boot_console.run_command('erofsls host 0 fff')
+    out_not_dir = u_boot_console.run_command('erofsls host 0 f1000')
+    assert out_non_existent == out_not_dir
+    assert '' in out_non_existent
+
+def erofs_load_files(u_boot_console, files, sizes, address):
+    """
+    Loads files and asserts their checksums.
+    """
+    build_dir = u_boot_console.config.build_dir
+    for (file, size) in zip(files, sizes):
+        out = u_boot_console.run_command('erofsload host 0 {} {}'.format(address, file))
+
+        # check if the right amount of bytes was read
+        assert size in out
+
+        # calculate u-boot file's checksum
+        out = u_boot_console.run_command('md5sum {} {}'.format(address, hex(int(size))))
+        u_boot_checksum = out.split()[-1]
+
+        # calculate original file's checksum
+        original_file_path = os.path.join(build_dir, EROFS_SRC_DIR + '/' + file)
+        out = subprocess.run(['md5sum ' + original_file_path], shell=True, check=True,
+                             capture_output=True, text=True)
+        original_checksum = out.stdout.split()[0]
+
+        # compare checksum
+        assert u_boot_checksum == original_checksum
+
+def erofs_load_files_at_root(u_boot_console):
+    """
+    Test load file from the root directory.
+    """
+    files = ['f4096', 'f7812']
+    sizes = ['4096', '7812']
+    address = '$kernel_addr_r'
+    erofs_load_files(u_boot_console, files, sizes, address)
+
+def erofs_load_files_at_subdir(u_boot_console):
+    """
+    Test load file from the subdirectory.
+    """
+    files = ['subdir/subdir-file']
+    sizes = ['100']
+    address = '$kernel_addr_r'
+    erofs_load_files(u_boot_console, files, sizes, address)
+
+def erofs_load_files_at_symlink(u_boot_console):
+    """
+    Test load file from the symlink.
+    """
+    files = ['symfile']
+    sizes = ['7812']
+    address = '$kernel_addr_r'
+    erofs_load_files(u_boot_console, files, sizes, address)
+
+def erofs_load_non_existent_file(u_boot_console):
+    """
+    Test if the EROFS support will crash when load a nonexistent file.
+    """
+    address = '$kernel_addr_r'
+    file = 'non-existent'
+    out = u_boot_console.run_command('erofsload host 0 {} {}'.format(address, file))
+    assert 'Failed to load' in out
+
+def erofs_run_all_tests(u_boot_console):
+    """
+    Runs all test cases.
+    """
+    erofs_ls_at_root(u_boot_console)
+    erofs_ls_at_subdir(u_boot_console)
+    erofs_ls_at_symlink(u_boot_console)
+    erofs_ls_at_non_existent_dir(u_boot_console)
+    erofs_load_files_at_root(u_boot_console)
+    erofs_load_files_at_subdir(u_boot_console)
+    erofs_load_files_at_symlink(u_boot_console)
+    erofs_load_non_existent_file(u_boot_console)
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_fs_generic')
+@pytest.mark.buildconfigspec('cmd_erofs')
+@pytest.mark.buildconfigspec('fs_erofs')
+@pytest.mark.requiredtool('mkfs.erofs')
+@pytest.mark.requiredtool('md5sum')
+
+def test_erofs(u_boot_console):
+    """
+    Executes the erofs test suite.
+    """
+    build_dir = u_boot_console.config.build_dir
+
+    try:
+        # setup test environment
+        make_erofs_image(build_dir)
+        image_path = os.path.join(build_dir, EROFS_IMAGE_NAME)
+        u_boot_console.run_command('host bind 0 {}'.format(image_path))
+        # run all tests
+        erofs_run_all_tests(u_boot_console)
+    except:
+        clean_erofs_image(build_dir)
+        raise AssertionError
+
+    # clean test environment
+    clean_erofs_image(build_dir)
index 9825c21..e2b0cd6 100644 (file)
@@ -482,4 +482,5 @@ if __name__ == '__main__':
         print('valid attack names: [fakeroot, kernel@]')
         sys.exit(1)
 
-    add_evil_node(sys.argv[1:])
+    in_fname, out_fname, kernel_fname, attack = sys.argv[1:]
+    add_evil_node(in_fname, out_fname, kernel_fname, attack)
index 3938ec1..58ec859 100644 (file)
@@ -115,6 +115,14 @@ class ConsoleBase(object):
         self.at_prompt = False
         self.at_prompt_logevt = None
 
+    def get_spawn(self):
+        # This is not called, ssubclass must define this.
+        # Return a value to avoid:
+        #   u_boot_console_base.py:348:12: E1128: Assigning result of a function
+        #   call, where the function returns None (assignment-from-none)
+        return u_boot_spawn.Spawn([])
+
+
     def eval_bad_patterns(self):
         self.bad_patterns = [pat[PAT_RE] for pat in bad_pattern_defs \
             if self.disable_check_count[pat[PAT_ID]] == 0]
index 8fcb02e..ee38d1f 100644 (file)
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <console.h>
 #include <dm.h>
+#include <event.h>
 #include <dm/root.h>
 #include <dm/test.h>
 #include <dm/uclass-internal.h>
@@ -218,6 +219,8 @@ static int dm_test_restore(struct device_node *of_root)
  */
 static int test_pre_run(struct unit_test_state *uts, struct unit_test *test)
 {
+       ut_assertok(event_init());
+
        if (test->flags & UT_TESTF_DM)
                ut_assertok(dm_test_pre_run(uts));
 
@@ -260,6 +263,7 @@ static int test_post_run(struct unit_test_state *uts, struct unit_test *test)
        ut_unsilence_console(uts);
        if (test->flags & UT_TESTF_DM)
                ut_assertok(dm_test_post_run(uts));
+       ut_assertok(event_uninit());
 
        return 0;
 }
index 0626b85..1d1ca43 100644 (file)
@@ -7,7 +7,7 @@
 
 import argparse
 from argparse import ArgumentParser
-import state
+from binman import state
 
 def make_extract_parser(subparsers):
     """make_extract_parser: Make a subparser for the 'extract' command
index a179f78..c9d7a08 100644 (file)
@@ -20,6 +20,10 @@ from binman import elf
 from patman import command
 from patman import tout
 
+# These are imported if needed since they import libfdt
+state = None
+Image = None
+
 # List of images we plan to create
 # Make this global so that it can be referenced from tests
 images = OrderedDict()
@@ -41,6 +45,8 @@ def _ReadImageDesc(binman_node, use_expanded):
     Returns:
         OrderedDict of Image objects, each of which describes an image
     """
+    # For Image()
+    # pylint: disable=E1102
     images = OrderedDict()
     if 'multiple-images' in binman_node.props:
         for node in binman_node.subnodes:
index 5e7d6ae..3597173 100644 (file)
@@ -85,6 +85,57 @@ def GetSymbols(fname, patterns):
     # Sort dict by address
     return OrderedDict(sorted(syms.items(), key=lambda x: x[1].address))
 
+def _GetFileOffset(elf, addr):
+    """Get the file offset for an address
+
+    Args:
+        elf (ELFFile): ELF file to check
+        addr (int): Address to search for
+
+    Returns
+        int: Offset of that address in the ELF file, or None if not valid
+    """
+    for seg in elf.iter_segments():
+        seg_end = seg['p_vaddr'] + seg['p_filesz']
+        if seg.header['p_type'] == 'PT_LOAD':
+            if addr >= seg['p_vaddr'] and addr < seg_end:
+                return addr - seg['p_vaddr'] + seg['p_offset']
+
+def GetFileOffset(fname, addr):
+    """Get the file offset for an address
+
+    Args:
+        fname (str): Filename of ELF file to check
+        addr (int): Address to search for
+
+    Returns
+        int: Offset of that address in the ELF file, or None if not valid
+    """
+    if not ELF_TOOLS:
+        raise ValueError('Python elftools package is not available')
+    with open(fname, 'rb') as fd:
+        elf = ELFFile(fd)
+        return _GetFileOffset(elf, addr)
+
+def GetSymbolFromAddress(fname, addr):
+    """Get the symbol at a particular address
+
+    Args:
+        fname (str): Filename of ELF file to check
+        addr (int): Address to search for
+
+    Returns:
+        str: Symbol name, or None if no symbol at that address
+    """
+    if not ELF_TOOLS:
+        raise ValueError('Python elftools package is not available')
+    with open(fname, 'rb') as fd:
+        elf = ELFFile(fd)
+        syms = GetSymbols(fname, None)
+    for name, sym in syms.items():
+        if sym.address == addr:
+            return name
+
 def GetSymbolFileOffset(fname, patterns):
     """Get the symbols from an ELF file
 
@@ -97,13 +148,6 @@ def GetSymbolFileOffset(fname, patterns):
           key: Name of symbol
           value: Hex value of symbol
     """
-    def _GetFileOffset(elf, addr):
-        for seg in elf.iter_segments():
-            seg_end = seg['p_vaddr'] + seg['p_filesz']
-            if seg.header['p_type'] == 'PT_LOAD':
-                if addr >= seg['p_vaddr'] and addr < seg_end:
-                    return addr - seg['p_vaddr'] + seg['p_offset']
-
     if not ELF_TOOLS:
         raise ValueError('Python elftools package is not available')
 
index a67915b..5084838 100644 (file)
@@ -116,7 +116,7 @@ class TestElf(unittest.TestCase):
         entry = FakeEntry(10)
         section = FakeSection()
         with self.assertRaises(ValueError) as e:
-            syms = elf.LookupAndWriteSymbols('missing-file', entry, section)
+            elf.LookupAndWriteSymbols('missing-file', entry, section)
         self.assertIn("Filename 'missing-file' not found in input path",
                       str(e.exception))
 
@@ -126,7 +126,7 @@ class TestElf(unittest.TestCase):
         section = FakeSection()
         elf_fname = self.ElfTestFile('u_boot_binman_syms')
         with self.assertRaises(ValueError) as e:
-            syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
+            elf.LookupAndWriteSymbols(elf_fname, entry, section)
         self.assertIn('entry_path has offset 4 (size 8) but the contents size '
                       'is a', str(e.exception))
 
@@ -139,8 +139,7 @@ class TestElf(unittest.TestCase):
         entry = FakeEntry(10)
         section = FakeSection()
         elf_fname = self.ElfTestFile('u_boot_binman_syms_bad')
-        self.assertEqual(elf.LookupAndWriteSymbols(elf_fname, entry, section),
-                         None)
+        elf.LookupAndWriteSymbols(elf_fname, entry, section)
 
     def testBadSymbolSize(self):
         """Test that an attempt to use an 8-bit symbol are detected
@@ -152,7 +151,7 @@ class TestElf(unittest.TestCase):
         section = FakeSection()
         elf_fname =self.ElfTestFile('u_boot_binman_syms_size')
         with self.assertRaises(ValueError) as e:
-            syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
+            elf.LookupAndWriteSymbols(elf_fname, entry, section)
         self.assertIn('has size 1: only 4 and 8 are supported',
                       str(e.exception))
 
@@ -165,7 +164,7 @@ class TestElf(unittest.TestCase):
         entry = FakeEntry(24)
         section = FakeSection(sym_value=None)
         elf_fname = self.ElfTestFile('u_boot_binman_syms')
-        syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
+        elf.LookupAndWriteSymbols(elf_fname, entry, section)
         self.assertEqual(tools.get_bytes(255, 20) + tools.get_bytes(ord('a'), 4),
                                                                   entry.data)
 
@@ -177,7 +176,7 @@ class TestElf(unittest.TestCase):
             section = FakeSection()
             elf_fname = self.ElfTestFile('u_boot_binman_syms')
             with test_util.capture_sys_output() as (stdout, stderr):
-                syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
+                elf.LookupAndWriteSymbols(elf_fname, entry, section)
             self.assertTrue(len(stdout.getvalue()) > 0)
         finally:
             tout.init(tout.WARNING)
index bf68a85..85dc339 100644 (file)
@@ -19,6 +19,8 @@ from patman import tout
 
 modules = {}
 
+# This is imported if needed
+state = None
 
 # An argument which can be passed to entries on the command line, in lieu of
 # device-tree properties.
index 7ed9b26..1d60076 100644 (file)
@@ -5,6 +5,7 @@
 # Test for the Entry class
 
 import collections
+import importlib
 import os
 import sys
 import unittest
@@ -32,11 +33,7 @@ class TestEntry(unittest.TestCase):
     def _ReloadEntry(self):
         global entry
         if entry:
-            if sys.version_info[0] >= 3:
-                import importlib
-                importlib.reload(entry)
-            else:
-                reload(entry)
+            importlib.reload(entry)
         else:
             from binman import entry
 
index 3ce7511..4159e30 100644 (file)
@@ -8,6 +8,9 @@
 from binman.entry import Entry
 from binman.etype.blob import Entry_blob
 
+# This is imported if needed
+state = None
+
 class Entry_blob_dtb(Entry_blob):
     """A blob that holds a device tree
 
index ed25e46..23e2ad6 100644 (file)
@@ -7,6 +7,9 @@
 
 from binman.etype.section import Entry_section
 
+# This is imported if needed
+state = None
+
 class Entry_blob_phase(Entry_section):
     """Section that holds a phase binary
 
index cc1fbdf..4a1837f 100644 (file)
@@ -12,6 +12,9 @@ from binman.cbfs_util import CbfsWriter
 from binman.entry import Entry
 from dtoc import fdt_util
 
+# This is imported if needed
+state = None
+
 class Entry_cbfs(Entry):
     """Coreboot Filesystem (CBFS)
 
index 76e8dbe..33c9d03 100644 (file)
@@ -15,6 +15,11 @@ from patman import tout
 FDTMAP_MAGIC   = b'_FDTMAP_'
 FDTMAP_HDR_LEN = 16
 
+# These is imported if needed
+Fdt = None
+libfdt = None
+state = None
+
 def LocateFdtmap(data):
     """Search an image for an fdt map
 
index 0650a69..13838ec 100644 (file)
@@ -13,6 +13,8 @@ from binman.etype.section import Entry_section
 from dtoc import fdt_util
 from patman import tools
 
+# This is imported if needed
+state = None
 
 class Entry_files(Entry_section):
     """A set of files arranged in a section
index 2515907..639b12d 100644 (file)
@@ -163,6 +163,7 @@ class Entry_section(Entry):
         self._sort = False
         self._skip_at_start = None
         self._end_4gb = False
+        self._ignore_missing = False
 
     def ReadNode(self):
         """Read properties from the section node"""
index 554b3b2..047d310 100644 (file)
@@ -9,6 +9,9 @@ from binman.entry import Entry
 from binman.etype.blob_dtb import Entry_blob_dtb
 from patman import tools
 
+# This is imported if needed
+state = None
+
 class Entry_u_boot_dtb_with_ucode(Entry_blob_dtb):
     """A U-Boot device tree file, with the microcode removed
 
index 8f00db6..8d41ab6 100644 (file)
@@ -991,7 +991,7 @@ class TestFunctional(unittest.TestCase):
         self.assertIn("Section '/binman': Size 0x7 (7) does not match "
                       "align-size 0x8 (8)", str(e.exception))
 
-    def testPackAlignPowerOf2(self):
+    def testPackAlignPowerOf2Inv(self):
         """Test that invalid image alignment is detected"""
         with self.assertRaises(ValueError) as e:
             self._DoTestFile('020_pack_inv_image_align_power2.dts')
@@ -3714,7 +3714,7 @@ class TestFunctional(unittest.TestCase):
         err = stderr.getvalue()
         self.assertRegex(err, "Image 'main-section'.*missing.*: intel-ifwi")
 
-    def testPackOverlap(self):
+    def testPackOverlapZero(self):
         """Test that zero-size overlapping regions are ignored"""
         self._DoTestFile('160_pack_overlap_zero.dts')
 
@@ -4095,13 +4095,6 @@ class TestFunctional(unittest.TestCase):
         self.assertIn("Generator node requires 'fit,fdt-list' property",
                       str(e.exception))
 
-    def testFitFdtEmptyList(self):
-        """Test handling of an empty 'of-list' entry arg"""
-        entry_args = {
-            'of-list': '',
-        }
-        data = self._DoReadFileDtb('170_fit_fdt.dts', entry_args=entry_args)[0]
-
     def testFitFdtMissing(self):
         """Test handling of a missing 'default-dt' entry arg"""
         entry_args = {
@@ -4986,16 +4979,6 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         self.assertEqual('rot-cert', fent.fip_type)
         self.assertEqual(b'aa', fent.data)
 
-    def testFipOther(self):
-        """Basic FIP with something that isn't a external blob"""
-        data = self._DoReadFile('204_fip_other.dts')
-        hdr, fents = fip_util.decode_fip(data)
-
-        self.assertEqual(2, len(fents))
-        fent = fents[1]
-        self.assertEqual('rot-cert', fent.fip_type)
-        self.assertEqual(b'aa', fent.data)
-
     def testFipNoType(self):
         """FIP with an entry of an unknown type"""
         with self.assertRaises(ValueError) as e:
index 0b7208d..e634bbb 100644 (file)
@@ -74,6 +74,7 @@ def CreateBuildmanConfigFile(config_fname):
     print('''[toolchain]
 # name = path
 # e.g. x86 = /opt/gcc-4.6.3-nolibc/x86_64-linux
+other = /
 
 [toolchain-prefix]
 # name = path to prefix
index 754642d..ecbfa3e 100644 (file)
@@ -1763,7 +1763,7 @@ class Builder:
             if self.num_threads:
                 self.queue.put(job)
             else:
-                results = self._single_builder.RunJob(job)
+                self._single_builder.RunJob(job)
 
         if self.num_threads:
             term = threading.Thread(target=self.queue.join)
index 4eba508..ab74a8e 100644 (file)
@@ -123,10 +123,10 @@ def adjust_cfg_file(fname, adjust_cfg):
                  C=val to set the value of C (val must have quotes if C is
                      a string Kconfig)
     """
-    lines = tools.ReadFile(fname, binary=False).splitlines()
+    lines = tools.read_file(fname, binary=False).splitlines()
     out_lines = adjust_cfg_lines(lines, adjust_cfg)
     out = '\n'.join(out_lines) + '\n'
-    tools.WriteFile(fname, out, binary=False)
+    tools.write_file(fname, out, binary=False)
 
 def convert_list_to_dict(adjust_cfg_list):
     """Convert a list of config changes into the dict used by adjust_cfg_file()
@@ -219,7 +219,7 @@ def check_cfg_file(fname, adjust_cfg):
     Returns:
         str: None if OK, else an error string listing the problems
     """
-    lines = tools.ReadFile(fname, binary=False).splitlines()
+    lines = tools.read_file(fname, binary=False).splitlines()
     bad_cfgs = check_cfg_lines(lines, adjust_cfg)
     if bad_cfgs:
         out = [f'{cfg:20}  {line}' for cfg, line in bad_cfgs]
index 6fcceb0..fbf6706 100644 (file)
@@ -524,12 +524,6 @@ class TestFunctional(unittest.TestCase):
         # Each commit has a config and make
         self.assertEqual(self._make_calls, len(boards) * self._commits * 2)
 
-    def testForceReconfigure(self):
-        """The -f flag should force a rebuild"""
-        self._RunControl('-b', TEST_BRANCH, '-C', '-o', self._output_dir)
-        # Each commit has a config and make
-        self.assertEqual(self._make_calls, len(boards) * self._commits * 2)
-
     def testMrproper(self):
         """The -f flag should force a rebuild"""
         self._RunControl('-b', TEST_BRANCH, '-m', '-o', self._output_dir)
index c67895c..b9f3756 100644 (file)
@@ -556,6 +556,7 @@ from os.path import dirname, exists, expandvars, islink, join, realpath
 
 VERSION = (14, 1, 0)
 
+# pylint: disable=E1101
 
 # File layout:
 #
index 0127106..3b6af24 100755 (executable)
@@ -30,8 +30,8 @@ from patman import terminal
 from patman import test_util
 
 def RunTests(skip_net_tests, verboose, args):
-    import func_test
-    import test
+    from buildman import func_test
+    from buildman import test
     import doctest
 
     result = unittest.TestResult()
diff --git a/tools/concurrencytest/__init__.py b/tools/concurrencytest/__init__.py
new file mode 100644 (file)
index 0000000..e69de29
index 7a3f5cb..c51e343 100644 (file)
@@ -2,7 +2,7 @@
 # This Dockerfile is used to build an image containing basic stuff to be used
 # to build U-Boot and run our test suites.
 
-FROM ubuntu:focal-20220113
+FROM ubuntu:focal-20220302
 MAINTAINER Tom Rini <trini@konsulko.com>
 LABEL Description=" This image is for building U-Boot inside a container"
 
@@ -48,6 +48,7 @@ RUN apt-get update && apt-get install -y \
        dosfstools \
        e2fsprogs \
        efitools \
+       erofs-utils \
        expect \
        fakeroot \
        flex \
index ea88954..c81bcc9 100755 (executable)
@@ -16,13 +16,13 @@ import os
 import struct
 import unittest
 
-from dtb_platdata import Ftype
-from dtb_platdata import get_value
-from dtb_platdata import tab_to
 from dtoc import dtb_platdata
 from dtoc import fdt
 from dtoc import fdt_util
 from dtoc import src_scan
+from dtoc.dtb_platdata import Ftype
+from dtoc.dtb_platdata import get_value
+from dtoc.dtb_platdata import tab_to
 from dtoc.src_scan import conv_name_to_c
 from dtoc.src_scan import get_compat_name
 from patman import test_util
index 576d65b..28231e5 100755 (executable)
@@ -25,7 +25,7 @@ sys.path.insert(2, os.path.join(our_path,
 from dtoc import fdt
 from dtoc import fdt_util
 from dtoc.fdt_util import fdt32_to_cpu, fdt64_to_cpu
-from fdt import Type, BytesToValue
+from dtoc.fdt import Type, BytesToValue
 import libfdt
 from patman import command
 from patman import test_util
@@ -119,9 +119,9 @@ class TestFdt(unittest.TestCase):
         """Test that packing a device tree works"""
         self.dtb.Pack()
 
-    def testGetFdt(self):
+    def testGetFdtRaw(self):
         """Tetst that we can access the raw device-tree data"""
-        self.assertTrue(isinstance(self.dtb.GetContents(), bytearray))
+        self.assertTrue(isinstance(self.dtb.GetContents(), bytes))
 
     def testGetProps(self):
         """Tests obtaining a list of properties"""
index 69d1be0..9f2dd2d 100644 (file)
@@ -2073,7 +2073,8 @@ main(int argc, char **argv)
                        bootmsg = 1;
                        if (prev_optind == optind)
                                goto usage;
-                       if (optind < argc - 1 && argv[optind] && argv[optind][0] != '-')
+                       /* Option -b could have optional argument which specify image path */
+                       if (optind < argc && argv[optind] && argv[optind][0] != '-')
                                imgpath = argv[optind++];
                        break;
 
@@ -2128,17 +2129,44 @@ main(int argc, char **argv)
        if (!bootmsg && !term && !debugmsg && !imgpath)
                goto usage;
 
-       ttypath = argv[optind++];
+       /*
+        * If there is no remaining argument but optional imgpath was parsed
+        * then it means that optional imgpath was eaten by getopt parser.
+        * Reassing imgpath to required ttypath argument.
+        */
+       if (optind == argc && imgpath) {
+               ttypath = imgpath;
+               imgpath = NULL;
+       } else if (optind + 1 == argc) {
+               ttypath = argv[optind];
+       } else {
+               goto usage;
+       }
 
-       if (optind != argc)
+       /* boot and debug message use baudrate 115200 */
+       if (((bootmsg && !imgpath) || debugmsg) && baudrate != 115200) {
+               fprintf(stderr, "Baudrate other than 115200 cannot be used for this operation.\n");
                goto usage;
+       }
 
-       tty = kwboot_open_tty(ttypath, imgpath ? 115200 : baudrate);
+       tty = kwboot_open_tty(ttypath, baudrate);
        if (tty < 0) {
                perror(ttypath);
                goto out;
        }
 
+       /*
+        * initial baudrate for image transfer is always 115200,
+        * the change to different baudrate is done only after the header is sent
+        */
+       if (imgpath && baudrate != 115200) {
+               rc = kwboot_tty_change_baudrate(tty, 115200);
+               if (rc) {
+                       perror(ttypath);
+                       goto out;
+               }
+       }
+
        if (baudrate == 115200)
                /* do not change baudrate during Xmodem to the same value */
                baudrate = 0;
index cff1e30..d4a96ef 100755 (executable)
@@ -339,7 +339,7 @@ def read_file(fname, as_lines=True, skip_unicode=False):
                 return inf.read()
         except UnicodeDecodeError as e:
             if not skip_unicode:
-                raises
+                raise
             print("Failed on file %s': %s" % (fname, e))
             return None
 
@@ -790,9 +790,6 @@ class KconfigParser:
                 actlog = "'%s' is the same as the define in Kconfig.  Do nothing." \
                          % value
                 log_color = COLOR_LIGHT_PURPLE
-            elif action == ACTION_SPL_NOT_EXIST:
-                actlog = 'SPL is not enabled for this defconfig.  Skip.'
-                log_color = COLOR_PURPLE
             else:
                 sys.exit('Internal Error. This should not happen.')
 
index dd792ef..70ba561 100644 (file)
@@ -125,7 +125,7 @@ def check_patch_parse(checkpatch_output, verbose=False):
     Returns:
         namedtuple containing:
             ok: False=failure, True=ok
-            problems: List of problems, each a dict:
+            problems (list of problems): each a dict:
                 'type'; error or warning
                 'msg': text message
                 'file' : filename
@@ -252,6 +252,8 @@ def check_patches(verbose, args):
             if (len(result.problems) != result.errors + result.warnings +
                     result.checks):
                 print("Internal error: some problems lost")
+            # Python seems to get confused by this
+            # pylint: disable=E1133
             for item in result.problems:
                 sys.stderr.write(
                     get_warning_msg(col, item.get('type', '<unknown>'),
index 2435878..92c453b 100644 (file)
@@ -17,13 +17,6 @@ class CommandResult:
         return_code: Return code from command
         exception: Exception received, or None if all ok
     """
-    def __init__(self):
-        self.stdout = None
-        self.stderr = None
-        self.combined = None
-        self.return_code = None
-        self.exception = None
-
     def __init__(self, stdout='', stderr='', combined='', return_code=0,
                  exception=None):
         self.stdout = stdout
@@ -72,6 +65,7 @@ def run_pipe(pipe_list, infile=None, outfile=None,
     """
     if test_result:
         if hasattr(test_result, '__call__'):
+            # pylint: disable=E1102
             result = test_result(pipe_list=pipe_list)
             if result:
                 return result
index c331a3b..a645b22 100644 (file)
@@ -31,7 +31,7 @@ class Commit:
     """
     def __init__(self, hash):
         self.hash = hash
-        self.subject = None
+        self.subject = ''
         self.tags = []
         self.changes = {}
         self.cc_list = []
index f1b2608..cd614f3 100644 (file)
@@ -113,7 +113,7 @@ class Popen(subprocess.Popen):
             return b''
         return data
 
-    def communicate_filter(self, output):
+    def communicate_filter(self, output, input_buf=''):
         """Interact with process: Read data from stdout and stderr.
 
         This method runs until end-of-file is reached, then waits for the
@@ -166,7 +166,7 @@ class Popen(subprocess.Popen):
             # Flush stdio buffer.    This might block, if the user has
             # been writing to .stdin in an uncontrolled fashion.
             self.stdin.flush()
-            if input:
+            if input_buf:
                 write_set.append(self.stdin)
             else:
                 self.stdin.close()
@@ -195,10 +195,10 @@ class Popen(subprocess.Popen):
                 # When select has indicated that the file is writable,
                 # we can write up to PIPE_BUF bytes without risk
                 # blocking.    POSIX defines PIPE_BUF >= 512
-                chunk = input[input_offset : input_offset + 512]
+                chunk = input_buf[input_offset : input_offset + 512]
                 bytes_written = os.write(self.stdin.fileno(), chunk)
                 input_offset += bytes_written
-                if input_offset >= len(input):
+                if input_offset >= len(input_buf):
                     self.stdin.close()
                     write_set.remove(self.stdin)
 
@@ -240,16 +240,6 @@ class Popen(subprocess.Popen):
         stderr = self.convert_data(stderr)
         combined = self.convert_data(combined)
 
-        # Translate newlines, if requested.    We cannot let the file
-        # object do the translation: It is based on stdio, which is
-        # impossible to combine with select (unless forcing no
-        # buffering).
-        if self.universal_newlines and hasattr(file, 'newlines'):
-            if stdout:
-                stdout = self._translate_newlines(stdout)
-            if stderr:
-                stderr = self._translate_newlines(stderr)
-
         self.wait()
         return (stdout, stderr, combined)
 
index 59ee90c..7b92bc6 100644 (file)
@@ -341,6 +341,8 @@ Changes in v2:
         tools.write_file(path, text, binary=False)
         index = self.repo.index
         index.add(fname)
+        # pylint doesn't seem to find this
+        # pylint: disable=E1101
         author = pygit2.Signature('Test user', 'test@email.com')
         committer = author
         tree = index.write_tree()
@@ -363,6 +365,8 @@ Changes in v2:
         self.repo = repo
         new_tree = repo.TreeBuilder().write()
 
+        # pylint doesn't seem to find this
+        # pylint: disable=E1101
         author = pygit2.Signature('Test user', 'test@email.com')
         committer = author
         _ = repo.create_commit('HEAD', author, committer, 'Created master',
@@ -414,6 +418,8 @@ better than before''')
         first_target = repo.revparse_single('HEAD')
 
         target = repo.revparse_single('HEAD~2')
+        # pylint doesn't seem to find this
+        # pylint: disable=E1101
         repo.reset(target.oid, pygit2.GIT_CHECKOUT_FORCE)
         self.make_commit_with_file('video: Some video improvements', '''
 Fix up the video so that
@@ -459,6 +465,8 @@ complicated as possible''')
         """Test creating patches from a branch"""
         repo = self.make_git_tree()
         target = repo.lookup_reference('refs/heads/first')
+        # pylint doesn't seem to find this
+        # pylint: disable=E1101
         self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE)
         control.setup()
         try:
@@ -615,6 +623,8 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
         """Test CountCommitsToBranch when there is no upstream"""
         repo = self.make_git_tree()
         target = repo.lookup_reference('refs/heads/base')
+        # pylint doesn't seem to find this
+        # pylint: disable=E1101
         self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE)
 
         # Check that it can detect the current branch
index 9b32fd4..fb6a603 100644 (file)
@@ -597,7 +597,7 @@ class PatchStream:
         if 'prefix' in self.series:
             parts.append(self.series['prefix'])
         if 'postfix' in self.series:
-            parts.append(self.serties['postfix'])
+            parts.append(self.series['postfix'])
         if 'version' in self.series:
             parts.append("v%s" % self.series['version'])
 
index 891f278..3075378 100644 (file)
@@ -122,8 +122,7 @@ class Series(dict):
             cc_list = list(self._generated_cc[commit.patch])
             for email in sorted(set(cc_list) - to_set - cc_set):
                 if email == None:
-                    email = col.build(col.YELLOW, "<alias '%s' not found>"
-                            % tag)
+                    email = col.build(col.YELLOW, '<alias not found>')
                 if email:
                     print('      Cc: ', email)
         print
index 014bb37..7c2b5c1 100644 (file)
@@ -200,12 +200,12 @@ def CreatePatmanConfigFile(gitutil, config_fname):
     """
     name = gitutil.get_default_user_name()
     if name == None:
-        name = raw_input("Enter name: ")
+        name = input("Enter name: ")
 
     email = gitutil.get_default_user_email()
 
     if email == None:
-        email = raw_input("Enter email: ")
+        email = input("Enter email: ")
 
     try:
         f = open(config_fname, 'w')
index 5e4d4ac..2ac814d 100644 (file)
@@ -62,8 +62,8 @@ def prepare_output_dir(dirname, preserve=False):
             try:
                 os.makedirs(outdir)
             except OSError as err:
-                raise CmdError("Cannot make output directory '%s': '%s'" %
-                                (outdir, err.strerror))
+                raise ValueError(
+                    f"Cannot make output directory 'outdir': 'err.strerror'")
         tout.debug("Using output directory '%s'" % outdir)
     else:
         outdir = tempfile.mkdtemp(prefix='binman.')
@@ -160,7 +160,7 @@ def get_input_filename_glob(pattern):
         A list of matching files in all input directories
     """
     if not indir:
-        return glob.glob(fname)
+        return glob.glob(pattern)
     files = []
     for dirname in indir:
         pathname = os.path.join(dirname, pattern)
@@ -201,7 +201,7 @@ def path_has_file(path_spec, fname):
             return True
     return False
 
-def get_host_compile_tool(name):
+def get_host_compile_tool(env, name):
     """Get the host-specific version for a compile tool
 
     This checks the environment variables that specify which version of
@@ -356,7 +356,7 @@ def run_result(name, *args, **kwargs):
             name, extra_args = get_target_compile_tool(name)
             args = tuple(extra_args) + args
         elif for_host:
-            name, extra_args = get_host_compile_tool(name)
+            name, extra_args = get_host_compile_tool(env, name)
             args = tuple(extra_args) + args
         name = os.path.expanduser(name)  # Expand paths containing ~
         all_args = (name,) + args