Changes since U-Boot 1.1.4:
======================================================================
+* Enable Quad UART om MCC200 board.
+
+* Cleanup MCC200 board configuration; omit non-existent stuff.
+
+* Add support for MPC859/866 Rev. A.0
+
+* Add command for handling DDR ECC registers on MPC8349EE MDS board.
+
+* Fix DDR ECC bit definitions for MPC83xx.
+
+* Add initial support for MPC8349E MDS board.
+
+* Add support for ECC DDR initialization on MPC83xx.
+
+* Add DMA support for MPC83xx.
+
+* Add sync in do_reset() routine for MPC83xx after RPR register
+ was written to. It is need on some targets when BAT translation
+ is enabled.
+
+* Add bit definitions for MPC83xx DDR controller registers.
+
+* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
+
+* Correct shift offsets in icache_status and dcache_status for MPC83xx.
+
+* Add support for DS1374 RTC chip.
+
+* Add support for Lite5200B board.
+ Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
+
+* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
+ timer and cpu_reset code from cpu/$(CPU) into the new
+ cpu/$(CPU)/$(SOC) directories
+ Patch by Andreas Engel, 13 Mar 2006
+
+* Change max size of uncompressed uImage's to 8MByte and add
+ CFG_BOOTM_LEN to adjust this setting.
+
+ As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
+ uImages was restricted to 4MBytes. This default size is now
+ increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
+ in the board config file.
+
+ Patch by Stefan Roese, 13 Mar 2006
+
+* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
+ Patch by Stefan Roese, 13 Mar 2006
+
+* cpu/ppc4xx/start.S : exceptions are enabled after relocation
+ Patch by Cedric Vincent, 06 Jul 2005
+
+* au1x00_eth.c: check malloc return value and abort if it failed
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Change the sequence of events in soft_i2c.c:send_ack() to keep from
+ incorrectly generating start/stop conditions on the bus.
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+ should look at LSB of L1CSRn registers to determine if L1 cache is
+ enabled, not the MSB.
+ Patch by Murray Jensen, 19 Jul 2005
+
+* Fix array overflow with fw_setenv on uninitialised environment
+ Patch by Murray Jensen, 15 Jul 2005
+
+* Add support for EmbeddedPlanet EP88x boards
+ Patch by Yuli Barcohen, 13 Jul 2005
+
+* Remove board specific configuration includes from the common xilinx
+ ethernet and iic adapter code.
+ Patch by Michael Libeskind, 12 Jul 2005
+
+* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add (some) definitions for the MPC85xx local bus controller
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add CPM2 I/O pin functions for MPC85xx processors
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Fix compile problem
+
+* Added PCI support for MPC8349ADS board
+ Patch by Kumar Gala 11 Jan 2006
+
+* Enable address translation on MPC83xx
+ Patch by Kumar Gala, 10 Feb 2006
+
+* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
+ Patch by Kumar Gala, 25 Jan 2006
+
+* Fixed defines for MPC83xx SICRL register to match current specs
+ Patch by Kumar Gala, 23 Jan 2006
+
+* Only disable the MPC83xx watchdog if its enabled out of reset.
+ If its disabled out of reset SW can later enable it if so desired
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow config of GPIO direction & data registers at boot on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Enable time handling on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Make System IO Config Registers board configurable on MPC83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Fixed PCI indirect config ops to handle multiple PCI controllers
+ We need to adjust the bus number we are trying to access based
+ on which PCI controller its on
+ Patch by Kumar Gala, 12 Jan 2006
+
+* Report back PCI bus when doing table based device config
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added support for PCI prefetchable region and BARs
+ If a host controller sets up a region as prefetchable and
+ a device's BAR denotes it as prefetchable, allocate the
+ BAR into the prefetch region.
+
+ If a BAR is prefetchable and no prefetchable region has
+ been setup by the controller we fall back to allocating
+ the BAR into the normally memory region.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add helper function for generic flat device tree fixups for mpc83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for passing initrd information via flat device tree
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added OF_STDOUT_PATH and OF_SOC
+
+ OF_STDOUT_PATH specifies the path to the device the kernel can use
+ for console output
+
+ OF_SOC specifies the proper name of the SOC node if one exists.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow board code to fixup the flat device tree before booting a kernel
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added CONFIG_ options for bd_t and env in flat dev tree
+
+ CONFIG_OF_HAS_BD_T will put a copy of the bd_t
+ into the resulting flat device tree.
+
+ CONFIG_OF_HAS_UBOOT_ENV will copy the environment
+ variables from u-boot into the flat device tree
+
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for the DHCP vendor optional bootfile (#67).
+ Ignores the vendor TFTP server name option (#66).
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
+ Patch by Andy Fleming, 14 Jun 2005
+
+* Fix bad register definitions for LTX971 PHY on MPC85xx boards.
+ Patch by Gerhard Jaeger, 21 Jun 2005
+
+* Add netconsole and some more commands to RPXlite_DW board
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix bad declaration on pci_cfgfunc_nothing
+ Patch by Sam Song, 19 Jun 2005
+
+* Adjust "echo" as a default command
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC
+ Patch by KokHow Teh, 16 Jun 2005
+
+* Add crc of data to jffs2 (in jffs2_1pass_build_lists()).
+ Patch by Rick Bronson, 15 Jun 2005
+
+* Coding Style cleanup
+
+* Avoid dereferencing NULL in find_cmd() if no valid commands were found
+ Patch by Andrew Dyer, 13 Jun 2005
+
+* Add ADI Blackfin support
+ - add support for Analog Devices Blackfin BF533 CPU
+ - add support for the ADI BF533 Stamp uClinux board
+ - add support for the ADI BF533 EZKit board
+ Patches by Richard Klingler, 11 Jun 2005
+
+* Add loads of ntohl() in image header handling
+ Patch by Steven Scholz, 10 Jun 2005
+
+* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
+ variable to set clock
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* RPXlite configuration fixes
+ - Use correct flash sector size
+ - Use correct memory test end address
+ - Add support for bzip2 compression
+ - Various small fixes
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Memory configuration changes for ZPC.1900 board
+ - Fix SDRAM timing on both local bus and 60x bus
+ - Add support for second flash bank (SIMM)
+ - Change boot flash base
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Add support for Adder boards with 16MB SDRAM;
+ add support for second FEC on Adder87x board.
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Fix conditional for including ks8695eth driver
+ Patch by Greg Ungerer, 04 Jun 2005
+
+* Fix Makefile: include config.mk only after CROSS_COMPILE is defined
+ Patch by Friedrich Lobenstock, 02 Jun 2005
+
+* Fix comment in common/soft_i2c.c
+ Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005
+
+* Cleanup compiler warnings.
+ Patch by Greg Ungerer, 21 May 2005
+
+* Word alignment fixes for word aligned NS16550 UART
+ Patch by Jean-Paul Saman, 01 Mar 2005
+
+ Fixes bug with UART that only supports word aligned access: removed
+ "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some
+ (broken!) versions of GCC generate byte accesses when encountering
+ the packed attribute regardless if the struct is already correctly
+ aligned for a platform. Peripherals that can only handle word
+ aligned access won't work properly when accessed with byte access.
+ The struct NS16550 is already word aligned for REG_SIZE = 4, so
+ there is no need to packed the struct in that case.
+
+* Fix behaviour if gatewayip is not set
+ Patch by Robin Gilks, 23 Dec 2004
+
+* Fix cleanup for netstart board.
+ Remove build results from repository
+
+* Some code cleanup for GCC 4.x
+
+* Fixes to support environment in NAND flash;
+ enable NAND flash based environment for delta board.
+
* Add support for Intel Monahans CPU on Zylonite and Delta boards
(This is Work in Progress!)
#########################################################################
LIST_5xxx=" \
- cpci5200 icecube_5100 icecube_5200 EVAL5200 \
- mcc200 o2dnt pf5200 PM520 \
- Total5100 Total5200 Total5200_Rev2 TQM5200_auto \
+ cpci5200 EVAL5200 icecube_5100 icecube_5200 \
+ lite5200b mcc200 o2dnt pf5200 \
+ PM520 Total5100 Total5200 Total5200_Rev2 \
+ TQM5200_auto \
"
#########################################################################
CCM IP860 NETPHONE RPXlite_DW \
cogent_mpc8xx IVML24 NETTA RRvision \
ELPT860 IVML24_128 NETTA2 SM850 \
- ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \
- ETX094 IVMS8 NETVIA svm_sc8xx \
- FADS823 IVMS8_128 NETVIA_V2 SXNI855T \
- FADS850SAR IVMS8_256 NX823 TOP860 \
- FADS860T KUP4K pcu_e TQM823L \
- FLAGADM KUP4X QS823 TQM823L_LCD \
- FPS850L LANTEC QS850 TQM850L \
- GEN860T lwmon QS860T TQM855L \
- GEN860T_SC MBX quantum TQM860L \
- uc100 \
+ EP88x IVML24_256 NETTA_ISDN SPD823TS \
+ ESTEEM192E IVMS8 NETVIA svm_sc8xx \
+ ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
+ FADS823 IVMS8_256 NX823 TOP860 \
+ FADS850SAR KUP4K pcu_e TQM823L \
+ FADS860T KUP4X QS823 TQM823L_LCD \
+ FLAGADM LANTEC QS850 TQM850L \
+ FPS850L lwmon QS860T TQM855L \
+ GEN860T MBX quantum TQM860L \
+ GEN860T_SC uc100 \
v37 \
"
#########################################################################
LIST_83xx=" \
- MPC8349ADS TQM834x\
+ MPC8349ADS TQM834x MPC8349EMDS \
"
# load ARCH, BOARD, and CPU configuration
include include/config.mk
export ARCH CPU BOARD VENDOR SOC
-# load other configuration
-include $(TOPDIR)/config.mk
-
ifndef CROSS_COMPILE
ifeq ($(HOSTARCH),ppc)
CROSS_COMPILE =
ifeq ($(ARCH),microblaze)
CROSS_COMPILE = mb-
endif
+ifeq ($(ARCH),blackfin)
+CROSS_COMPILE = bfin-elf-
+endif
endif
endif
export CROSS_COMPILE
+# load other configuration
+include $(TOPDIR)/config.mk
+
+
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
+ifeq ($(CPU),bf533)
+OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
+OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o
+endif
LIBS = lib_generic/libgeneric.a
LIBS += board/$(BOARDDIR)/lib$(BOARD).a
inka4x0_config: unconfig
@./mkconfig inka4x0 ppc mpc5xxx inka4x0
+lite5200b_config \
+lite5200b_LOWBOOT_config: unconfig
+ @ >include/config.h
+ @ echo "#define CONFIG_MPC5200_DDR" >>include/config.h
+ @ echo "... DDR memory revision"
+ @ echo "#define CONFIG_MPC5200" >>include/config.h
+ @ echo "#define CONFIG_LITE5200B" >>include/config.h
+ @[ -z "$(findstring LOWBOOT_,$@)" ] || \
+ { echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+ echo "... with LOWBOOT configuration" ; \
+ }
+ @ echo "... with MPC5200B processor"
+ @./mkconfig -a IceCube ppc mpc5xxx icecube
+
mcc200_config \
mcc200_lowboot_config: unconfig
@ >include/config.h
ELPT860_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
+EP88x_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8xx ep88x
+
ESTEEM192E_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx esteem192e
TQM834x_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx tqm834x
+MPC8349EMDS_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc83xx mpc8349emds
+
#########################################################################
## MPC85xx Systems
#########################################################################
@./mkconfig $(@:_config=) arm arm925t omap1510inn
omap5912osk_config : unconfig
- @./mkconfig $(@:_config=) arm arm926ejs omap5912osk
+ @./mkconfig $(@:_config=) arm arm926ejs omap5912osk NULL omap
omap1610inn_config \
omap1610inn_cs0boot_config \
echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
echo "... configured for CS3 boot"; \
fi;
- @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+ @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
omap730p2_config \
omap730p2_cs0boot_config \
echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
echo "... configured for CS3 boot"; \
fi;
- @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
+ @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
scb9328_config : unconfig
@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
@./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
#########################################################################
+## Blackfin
+#########################################################################
+ezkit533_config : unconfig
+ @./mkconfig $(@:_config=) blackfin bf533 ezkit533
+
+stamp_config : unconfig
+ @./mkconfig $(@:_config=) blackfin bf533 stamp
+
+dspstamp_config : unconfig
+ @./mkconfig $(@:_config=) blackfin bf533 dsp_stamp
+
+#########################################################################
+#########################################################################
#########################################################################
clean:
rm -f examples/hello_world examples/timer \
examples/eepro100_eeprom examples/sched \
examples/mem_to_mem_idma2intr examples/82559_eeprom \
+ examples/smc91111_eeprom \
examples/test_burst
rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
rm -f tools/mpc86x_clk tools/ncb
rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
rm -f tools/env/fw_printenv tools/env/fw_setenv
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
+ rm -f board/netstar/eeprom board/netstar/crcek
+ rm -f board/netstar/*.srec board/netstar/*.bin
rm -f board/trab/trab_fkt board/voiceblue/eeprom
rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
PowerPC based boards:
---------------------
- CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCIPPC2
- CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC6
- CONFIG_AMX860 CONFIG_GTH CONFIG_pcu_e
- CONFIG_AP1000 CONFIG_gw8260 CONFIG_PIP405
- CONFIG_AR405 CONFIG_hermes CONFIG_PM826
- CONFIG_BAB7xx CONFIG_hymod CONFIG_ppmc8260
- CONFIG_c2mon CONFIG_IAD210 CONFIG_QS823
- CONFIG_CANBT CONFIG_ICU862 CONFIG_QS850
- CONFIG_CCM CONFIG_IP860 CONFIG_QS860T
- CONFIG_CMI CONFIG_IPHASE4539 CONFIG_RBC823
- CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RPXClassic
- CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXlite
- CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXsuper
- CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_rsdproto
- CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_sacsng
- CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_Sandpoint8240
- CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8245
- CONFIG_CSB272 CONFIG_LANTEC CONFIG_sbc8260
- CONFIG_CU824 CONFIG_lwmon CONFIG_sbc8560
- CONFIG_DASA_SIM CONFIG_MBX CONFIG_SM850
- CONFIG_DB64360 CONFIG_MBX860T CONFIG_SPD823TS
- CONFIG_DB64460 CONFIG_MHPC CONFIG_STXGP3
- CONFIG_DU405 CONFIG_MIP405 CONFIG_SXNI855T
- CONFIG_DUET_ADS CONFIG_MOUSSE CONFIG_TQM823L
- CONFIG_EBONY CONFIG_MPC8260ADS CONFIG_TQM8260
- CONFIG_ELPPC CONFIG_MPC8540ADS CONFIG_TQM850L
- CONFIG_ELPT860 CONFIG_MPC8540EVAL CONFIG_TQM855L
- CONFIG_ep8260 CONFIG_MPC8560ADS CONFIG_TQM860L
- CONFIG_ERIC CONFIG_MUSENKI CONFIG_TTTech
- CONFIG_ESTEEM192E CONFIG_MVS1 CONFIG_UTX8245
- CONFIG_ETX094 CONFIG_NETPHONE CONFIG_V37
- CONFIG_EVB64260 CONFIG_NETTA CONFIG_W7OLMC
- CONFIG_FADS823 CONFIG_NETVIA CONFIG_W7OLMG
- CONFIG_FADS850SAR CONFIG_NX823 CONFIG_WALNUT
- CONFIG_FADS860T CONFIG_OCRTC CONFIG_ZPC1900
- CONFIG_FLAGADM CONFIG_ORSG CONFIG_ZUMA
- CONFIG_FPS850L CONFIG_OXC
- CONFIG_FPS860L CONFIG_PCI405
+ CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCI405
+ CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC2
+ CONFIG_AMX860 CONFIG_GTH CONFIG_PCIPPC6
+ CONFIG_AP1000 CONFIG_gw8260 CONFIG_pcu_e
+ CONFIG_AR405 CONFIG_hermes CONFIG_PIP405
+ CONFIG_BAB7xx CONFIG_hymod CONFIG_PM826
+ CONFIG_c2mon CONFIG_IAD210 CONFIG_ppmc8260
+ CONFIG_CANBT CONFIG_ICU862 CONFIG_QS823
+ CONFIG_CCM CONFIG_IP860 CONFIG_QS850
+ CONFIG_CMI CONFIG_IPHASE4539 CONFIG_QS860T
+ CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RBC823
+ CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXClassic
+ CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXlite
+ CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_RPXsuper
+ CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_rsdproto
+ CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_sacsng
+ CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8240
+ CONFIG_CSB272 CONFIG_LANTEC CONFIG_Sandpoint8245
+ CONFIG_CU824 CONFIG_LITE5200B CONFIG_sbc8260
+ CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8560
+ CONFIG_DB64360 CONFIG_MBX CONFIG_SM850
+ CONFIG_DB64460 CONFIG_MBX860T CONFIG_SPD823TS
+ CONFIG_DU405 CONFIG_MHPC CONFIG_STXGP3
+ CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_SXNI855T
+ CONFIG_EBONY CONFIG_MOUSSE CONFIG_TQM823L
+ CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM8260
+ CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM850L
+ CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM855L
+ CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM860L
+ CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TTTech
+ CONFIG_ETX094 CONFIG_MVS1 CONFIG_UTX8245
+ CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_V37
+ CONFIG_FADS823 CONFIG_NETTA CONFIG_W7OLMC
+ CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMG
+ CONFIG_FADS860T CONFIG_NX823 CONFIG_WALNUT
+ CONFIG_FLAGADM CONFIG_OCRTC CONFIG_ZPC1900
+ CONFIG_FPS850L CONFIG_ORSG CONFIG_ZUMA
+ CONFIG_FPS860L CONFIG_OXC
ARM based boards:
-----------------
The maximum size of the constructed OF tree.
OF_CPU - The proper name of the cpus node.
+ OF_SOC - The proper name of the soc node.
OF_TBCLK - The timebase frequency.
+ OF_STDOUT_PATH - The path to the console device
+
+ CONFIG_OF_HAS_BD_T
+
+ The resulting flat device tree will have a copy of the bd_t.
+ Space should be pre-allocated in the dts for the bd_t.
+
+ CONFIG_OF_HAS_UBOOT_ENV
+
+ The resulting flat device tree will have a copy of u-boot's
+ environment variables
+
+ CONFIG_OF_BOARD_SETUP
+
+ Board code has addition modification that it wants to make
+ to the flat device tree before handing it off to the kernel
- Serial Ports:
CFG_PL010_SERIAL
CFG_CMD_DIAG * Diagnostics
CFG_CMD_DOC * Disk-On-Chip Support
CFG_CMD_DTT * Digital Therm and Thermostat
- CFG_CMD_ECHO * echo arguments
+ CFG_CMD_ECHO echo arguments
CFG_CMD_EEPROM * EEPROM read/write support
CFG_CMD_ELF * bootelf, bootvx
CFG_CMD_ENV saveenv
- CFG_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
+- CFG_BOOTM_LEN:
+ Normally compressed uImages are limited to an
+ uncompressed size of 8 MBytes. If this is not enough,
+ you can define CFG_BOOTM_LEN in your board config file
+ to adjust this setting to your needs.
+
- CFG_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
--- /dev/null
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__
/*
- * Copyright (C) 2004 Arabella Software Ltd.
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Analogue&Micro Adder boards family.
#include <mpc8xx.h>
/*
- * SDRAM is single Samsung K4S643232F-T70 chip.
+ * SDRAM is single Samsung K4S643232F-T70 chip (8MB)
+ * or single Micron MT48LC4M32B2TG-7 chip (16MB).
* Minimal CPU frequency is 40MHz.
*/
static uint sdram_table[] = {
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* Refresh (offset 0x30 in UPM RAM) */
- 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
long int initdram (int board_type)
{
- long int msize = CFG_SDRAM_SIZE;
+ long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* Configure SDRAM refresh */
memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
- memctl->memc_mamr = (94 << 24) | CFG_MAMR;
- memctl->memc_mar = 0x0;
+ memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
udelay(200);
/* Run precharge from location 0x15 */
+ memctl->memc_mar = 0x0;
memctl->memc_mcr = 0x80002115;
udelay(200);
memctl->memc_mcr = 0x80002830;
udelay(200);
- memctl->memc_mar = 0x88;
- udelay(200);
-
/* Run MRS pattern from location 0x16 */
+ memctl->memc_mar = 0x88;
memctl->memc_mcr = 0x80002116;
udelay(200);
+ memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
+ memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+ memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+ msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+ memctl->memc_or1 |= ~(msize - 1);
+
return msize;
}
if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
return -1;
- if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+ if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK)
return -1;
size -= SizeToRead;
* Copy memory to flash
*/
-volatile static int write_word (flash_info_t * info, ulong dest,
- ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
if ((result & data) != data)
return ERR_NOT_ERASED;
-
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
void load_sernum_ethaddr (void)
{
struct manufacturer_data data;
- unsigned char serial [9];
- unsigned char ethaddr[18];
+ char ethaddr[18];
+ char serial [9];
unsigned short chksum;
unsigned char *p;
unsigned short i, is, id;
return rc;
}
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
}
}
-static void dfc_clear_nddb()
+static void dfc_clear_nddb(void)
{
NDCR &= ~NDCR_ND_RUN;
wait_us(CFG_NAND_OTHER_TO);
}
/* we don't always wan't to do this */
-static void dfc_new_cmd()
+static void dfc_new_cmd(void)
{
int retry = 0;
unsigned long status;
return;
}
-static void dfc_gpio_init()
+static void dfc_gpio_init(void)
{
DFC_DEBUG2("Setting up DFC GPIO's.\n");
--- /dev/null
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2005 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Embedded Planet EP88x boards
+#
+TEXT_BASE = 0xFC000000
--- /dev/null
+/*
+ * Copyright (C) 2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP88x boards.
+ * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM uses two Micron chips.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+ /* Single read (offset 0x00 in UPM RAM) */
+ 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
+ 0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+ /* Burst read (offset 0x08 in UPM RAM) */
+ 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
+ 0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
+ 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+ 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+ /* Single write (offset 0x18 in UPM RAM) */
+ 0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
+ 0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+ /* Burst write (offset 0x20 in UPM RAM) */
+ 0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
+ 0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
+ 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+ 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+ /* Refresh (offset 0x30 in UPM RAM) */
+ 0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
+ 0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
+ 0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
+
+ /* Exception (offset 0x3C in UPM RAM) */
+ 0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
+};
+
+int board_early_init_f (void)
+{
+ vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+ bcsr[0] |= 0x0C; /* Turn the LEDs off */
+ bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
+ flash detection by CFI driver
+ */
+
+#if defined(CONFIG_8xx_CONS_SMC1)
+ bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#if defined(CONFIG_8xx_CONS_SCC2)
+ bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC1
+ bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC2
+ bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
+#endif
+
+ return 0;
+}
+
+long int initdram (int board_type)
+{
+ long int msize;
+ volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+ /* Configure SDRAM refresh */
+ memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
+
+ memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
+ udelay(100);
+
+ /* Run MRS pattern from location 0x36 */
+ memctl->memc_mar = 0x88;
+ memctl->memc_mcr = 0x80002236;
+ udelay(100);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
+ memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+ memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+ msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+ memctl->memc_or1 |= ~(msize - 1);
+
+ return msize;
+}
+
+int checkboard( void )
+{
+ vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+ puts("Board: ");
+ switch (bcsr[15]) {
+ case 0xE7:
+ puts("EP88xC 1.0");
+ break;
+ default:
+ printf("unknown ID=%02X", bcsr[15]);
+ }
+ printf(" CPLD revision %d\n", bcsr[14]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o ezkit533.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
--- /dev/null
+/*
+ * U-boot - ezkit533.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_MISC_INIT_R)
+#include "psd4256.h"
+#endif
+
+int checkboard(void)
+{
+ printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+ printf("Board: ADI BF533 EZ-Kit Lite board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ printf(" Richard Klingler <richard@uclinux.net>\n");
+ return 0;
+}
+
+long int initdram(int board_type)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+ int brate;
+ char *tmp = getenv("baudrate");
+ brate = simple_strtoul(tmp, NULL, 16);
+ printf("Serial Port initialized with Baud rate = %x\n",brate);
+ printf("SDRAM attributes:\n");
+ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+ 3, 3, 6, 2, 3);
+ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+ return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+ /* Set direction bits for Video en/decoder reset as output */
+ *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
+ /* Deactivate Video en/decoder reset lines */
+ *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
+}
+#endif
--- /dev/null
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a) (*(volatile unsigned long *)( a ))
+#define V_BYTE(a) (*(volatile unsigned char *)( a ))
+#define TRUE 0x1
+#define FALSE 0x0
+#define BUFFER_SIZE 0x80000
+#define NO_COMMAND 0
+#define GET_CODES 1
+#define RESET 2
+#define WRITE 3
+#define FILL 4
+#define ERASE_ALL 5
+#define ERASE_SECT 6
+#define READ 7
+#define GET_SECTNUM 8
+#define FLASH_START_L 0x0000
+#define FLASH_START_H 0x2000
+#define FLASH_TOT_SECT 40
+#define FLASH_SIZE 0x220000
+#define FLASH_MAN_ST 2
+#define CFG_FLASH0_BASE 0x20000000
+#define RESET_VAL 0xF0
+
+
+asm("#define FLASH_START_L 0x0000");
+asm("#define FLASH_START_H 0x2000");
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int,unsigned long);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, long lStride, int *pnData);
+int FillData(long lStart, long lCount, long lStride, int *pnData);
+int read_data(long lStart, long lCount, long lStride, int *pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
+#define WRITESEQ1 0x0AAA
+#define WRITESEQ2 0x0554
+#define WRITESEQ3 0x0AAA
+#define WRITESEQ4 0x0AAA
+#define WRITESEQ5 0x0554
+#define WRITESEQ6 0x0AAA
+#define WRITEDATA1 0xaa
+#define WRITEDATA2 0x55
+#define WRITEDATA3 0x80
+#define WRITEDATA4 0xaa
+#define WRITEDATA5 0x55
+#define WRITEDATA6 0x10
+#define PriFlashABegin 0
+#define SecFlashABegin 32
+#define SecFlashBBegin 36
+#define PriFlashAOff 0x0
+#define PriFlashBOff 0x100000
+#define SecFlashAOff 0x200000
+#define SecFlashBOff 0x280000
+#define INVALIDLOCNSTART 0x20270000
+#define INVALIDLOCNEND 0x20280000
+#define BlockEraseVal 0x30
+#define UNLOCKDATA1 0xaa
+#define UNLOCKDATA2 0x55
+#define UNLOCKDATA3 0xa0
+#define GETCODEDATA1 0xaa
+#define GETCODEDATA2 0x55
+#define GETCODEDATA3 0x90
+#define SecFlashASec1Off 0x200000
+#define SecFlashASec2Off 0x204000
+#define SecFlashASec3Off 0x206000
+#define SecFlashASec4Off 0x208000
+#define SecFlashAEndOff 0x210000
+#define SecFlashBSec1Off 0x280000
+#define SecFlashBSec2Off 0x284000
+#define SecFlashBSec3Off 0x286000
+#define SecFlashBSec4Off 0x288000
+#define SecFlashBEndOff 0x290000
+
+#define SECT32 32
+#define SECT33 33
+#define SECT34 34
+#define SECT35 35
+#define SECT36 36
+#define SECT37 37
+#define SECT38 38
+#define SECT39 39
+
+#define FLASH_SUCCESS 0
+#define FLASH_FAIL -1
+
+#endif
--- /dev/null
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "flash-defines.h"
+
+void flash_reset(void)
+{
+ reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
+ int bank_flag)
+{
+ int id = 0, i = 0;
+ static int FlagDev = 1;
+
+ id = get_codes();
+ if(FlagDev) {
+#ifdef DEBUG
+ printf("Device ID of the Flash is %x\n", id);
+#endif
+ FlagDev = 0;
+ }
+ info->flash_id = id;
+
+ switch (bank_flag) {
+ case 0:
+ for (i = PriFlashABegin; i < SecFlashABegin; i++)
+ info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+ info->size = 0x200000;
+ info->sector_count = 32;
+ break;
+ case 1:
+ info->start[0] = baseaddr + SecFlashASec1Off;
+ info->start[1] = baseaddr + SecFlashASec2Off;
+ info->start[2] = baseaddr + SecFlashASec3Off;
+ info->start[3] = baseaddr + SecFlashASec4Off;
+ info->size = 0x10000;
+ info->sector_count = 4;
+ break;
+ case 2:
+ info->start[0] = baseaddr + SecFlashBSec1Off;
+ info->start[1] = baseaddr + SecFlashBSec2Off;
+ info->start[2] = baseaddr + SecFlashBSec3Off;
+ info->start[3] = baseaddr + SecFlashBSec4Off;
+ info->size = 0x10000;
+ info->sector_count = 4;
+ break;
+ }
+ return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1, size_b2;
+ int i;
+
+ size_b0 = size_b1 = size_b2 = 0;
+#ifdef DEBUG
+ printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE);
+ printf("Memory Map for the Flash\n");
+ printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
+ printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
+ printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
+ printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
+ printf("Please type command flinfo for information on Sectors \n");
+#endif
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0);
+ size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1);
+ size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 >> 20);
+ }
+
+ (void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
+
+ return (size_b0 + size_b1 + size_b2);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id) {
+ case FLASH_PSD4256GV:
+ printf("ST Microelectronics ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ int cnt = 0,i;
+ int prot,sect;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ else
+ printf ("\n");
+
+ cnt = s_last - s_first + 1;
+
+ if (cnt == FLASH_TOT_SECT) {
+ printf("Erasing flash, Please Wait \n");
+ if(erase_flash() < 0) {
+ printf("Erasing flash failed \n");
+ return FLASH_FAIL;
+ }
+ } else {
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if(erase_block_flash(i, info->start[i]) < 0) {
+ printf("Error Sector erasing \n");
+ return FLASH_FAIL;
+ }
+ }
+ }
+ }
+ return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ int ret;
+
+ ret = write_data(addr, cnt, 1, (int *) src);
+ if(ret == FLASH_FAIL)
+ return ERR_NOT_ERASED;
+ return FLASH_SUCCESS;
+}
+
+
+int write_data(long lStart, long lCount, long lStride, int *pnData)
+{
+ long i = 0;
+ int j = 0;
+ unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+ int d;
+ int iShift = 0;
+ int iNumWords = 2;
+ int nLeftover = lCount % 4;
+ int nSector = 0;
+
+ for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+ for (iShift = 0, j = 0; (j < iNumWords);
+ j++, ulOffset += (lStride * 2)) {
+ if ((ulOffset >= INVALIDLOCNSTART)
+ && (ulOffset < INVALIDLOCNEND)) {
+ printf("Invalid locations, Try writing to another location \n");
+ return FLASH_FAIL;
+ }
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset,&d);
+ if(d != 0xffff) {
+ printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
+ return FLASH_FAIL;
+ }
+ unlock_flash(ulOffset);
+ if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
+ printf("Error programming the flash \n");
+ return FLASH_FAIL;
+ }
+ iShift += 16;
+ }
+ }
+ if (nLeftover > 0) {
+ if ((ulOffset >= INVALIDLOCNSTART)
+ && (ulOffset < INVALIDLOCNEND))
+ return FLASH_FAIL;
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset,&d);
+ if(d != 0xffff) {
+ printf("Flash already programmed. Please erase to reprogram \n");
+ printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
+ return FLASH_FAIL;
+ }
+ unlock_flash(ulOffset);
+ if(write_flash(ulOffset, pnData[i]) < 0) {
+ printf("Error programming the flash \n");
+ return FLASH_FAIL;
+ }
+ }
+ return FLASH_SUCCESS;
+}
+
+int read_data(long ulStart, long lCount, long lStride, int *pnData)
+{
+ long i = 0;
+ int j = 0;
+ long ulOffset = ulStart;
+ int iShift = 0;
+ int iNumWords = 2;
+ int nLeftover = lCount % 4;
+ int nHi, nLow;
+ int nSector = 0;
+
+ for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+ for (iShift = 0, j = 0; j < iNumWords; j += 2) {
+ if ((ulOffset >= INVALIDLOCNSTART)
+ && (ulOffset < INVALIDLOCNEND))
+ return FLASH_FAIL;
+
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &nLow);
+ ulOffset += (lStride * 2);
+ read_flash(ulOffset, &nHi);
+ ulOffset += (lStride * 2);
+ pnData[i] = (nHi << 16) | nLow;
+ }
+ }
+ if (nLeftover > 0) {
+ if ((ulOffset >= INVALIDLOCNSTART)
+ && (ulOffset < INVALIDLOCNEND))
+ return FLASH_FAIL;
+
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &pnData[i]);
+ }
+ return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+ long addr;
+
+ addr = (CFG_FLASH_BASE + nOffset);
+ asm("ssync;");
+ *(unsigned volatile short *) addr = nValue;
+ asm("ssync;");
+ if(poll_toggle_bit(nOffset) < 0)
+ return FLASH_FAIL;
+ return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+ int nValue = 0x0;
+ long addr = (CFG_FLASH_BASE + nOffset);
+
+ if (nOffset != 0x2)
+ reset_flash();
+ asm("ssync;");
+ nValue = *(volatile unsigned short *) addr;
+ asm("ssync;");
+ *pnValue = nValue;
+ return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+ unsigned int u1,u2;
+ unsigned long timeout = 0xFFFFFFFF;
+ volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
+ while(1) {
+ if(timeout < 0)
+ break;
+ u1 = *(volatile unsigned short *)FB;
+ u2 = *(volatile unsigned short *)FB;
+ if((u1 & 0x0040) == (u2 & 0x0040))
+ return FLASH_SUCCESS;
+ if((u2 & 0x0020) == 0x0000)
+ continue;
+ u1 = *(volatile unsigned short *)FB;
+ if((u2 & 0x0040) == (u1 & 0x0040))
+ return FLASH_SUCCESS;
+ else {
+ reset_flash();
+ return FLASH_FAIL;
+ }
+ timeout--;
+ }
+ printf("Time out occured \n");
+ if(timeout <0) return FLASH_FAIL;
+}
+
+void reset_flash(void)
+{
+ write_flash(WRITESEQ1, RESET_VAL);
+ /* Wait for 10 micro seconds */
+ udelay(10);
+}
+
+int erase_flash(void)
+{
+ write_flash(WRITESEQ1, WRITEDATA1);
+ write_flash(WRITESEQ2, WRITEDATA2);
+ write_flash(WRITESEQ3, WRITEDATA3);
+ write_flash(WRITESEQ4, WRITEDATA4);
+ write_flash(WRITESEQ5, WRITEDATA5);
+ write_flash(WRITESEQ6, WRITEDATA6);
+
+ if(poll_toggle_bit(0x0000) < 0)
+ return FLASH_FAIL;
+
+ write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
+ write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
+ write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
+ write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
+ write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
+ write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
+
+ if(poll_toggle_bit(SecFlashASec1Off) < 0)
+ return FLASH_FAIL;
+
+ write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
+ write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
+ write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
+ write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
+ write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
+ write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
+
+ if(poll_toggle_bit(PriFlashBOff) <0)
+ return FLASH_FAIL;
+
+ write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
+ write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
+ write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
+ write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
+ write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
+ write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
+
+ if(poll_toggle_bit(SecFlashBOff) < 0)
+ return FLASH_FAIL;
+
+ return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+ long ulSectorOff = 0x0;
+
+ if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+ return FALSE;
+
+ ulSectorOff = (address - CFG_FLASH_BASE);
+
+ write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+ write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+ write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+ write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+ write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+ write_flash(ulSectorOff, BlockEraseVal);
+
+ if(poll_toggle_bit(ulSectorOff) < 0)
+ return FLASH_FAIL;
+
+ return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+ unsigned long ulOffsetAddr = ulOffset;
+ ulOffsetAddr &= 0xFFFF0000;
+
+ write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+ write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+ write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+ int dev_id = 0;
+
+ write_flash(WRITESEQ1, GETCODEDATA1);
+ write_flash(WRITESEQ2, GETCODEDATA2);
+ write_flash(WRITESEQ3, GETCODEDATA3);
+
+ read_flash(0x0002, &dev_id);
+ dev_id &= 0x00FF;
+
+ reset_flash();
+
+ return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+ int nSector = 0;
+
+ if (ulOffset >= SecFlashAOff) {
+ if ((ulOffset < SecFlashASec1Off)
+ && (ulOffset < SecFlashASec2Off)) {
+ nSector = SECT32;
+ } else if ((ulOffset >= SecFlashASec2Off)
+ && (ulOffset < SecFlashASec3Off)) {
+ nSector = SECT33;
+ } else if ((ulOffset >= SecFlashASec3Off)
+ && (ulOffset < SecFlashASec4Off)) {
+ nSector = SECT34;
+ } else if ((ulOffset >= SecFlashASec4Off)
+ && (ulOffset < SecFlashAEndOff)) {
+ nSector = SECT35;
+ }
+ } else if (ulOffset >= SecFlashBOff) {
+ if ((ulOffset < SecFlashBSec1Off)
+ && (ulOffset < SecFlashBSec2Off)) {
+ nSector = SECT36;
+ }
+ if ((ulOffset < SecFlashBSec2Off)
+ && (ulOffset < SecFlashBSec3Off)) {
+ nSector = SECT37;
+ }
+ if ((ulOffset < SecFlashBSec3Off)
+ && (ulOffset < SecFlashBSec4Off)) {
+ nSector = SECT38;
+ }
+ if ((ulOffset < SecFlashBSec4Off)
+ && (ulOffset < SecFlashBEndOff)) {
+ nSector = SECT39;
+ }
+ } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
+ nSector = ulOffset & 0xffff0000;
+ nSector = ulOffset >> 16;
+ nSector = nSector & 0x000ff;
+ }
+
+ if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
+ *pnSector = nSector;
+ }
+}
--- /dev/null
+/*
+ * U-boot - psd4256.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Flash A/B Port A configuration registers.
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define PSD_PORTA_DIN 0x070000
+#define PSD_PORTA_DOUT 0x070004
+#define PSD_PORTA_DIR 0x070006
+
+/*
+ * Flash A/B Port B configuration registers
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define PSD_PORTB_DIN 0x070001
+#define PSD_PORTB_DOUT 0x070005
+#define PSD_PORTB_DIR 0x070007
+
+/*
+ * Flash A Port A Bit definitions
+ */
+
+#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
+#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
+#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
+#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
+#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
+
+/*
+ * Flash A Port B Bit definitions
+ */
+
+#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
+#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
+#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
+#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
+#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
+#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */
--- /dev/null
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector before the environment sector. If it throws */
+ /* an error during compilation remove an object here to get */
+ /* it linked after the configuration sector. */
+
+ cpu/bf533/start.o (.text)
+ cpu/bf533/start1.o (.text)
+ cpu/bf533/traps.o (.text)
+ cpu/bf533/interrupt.o (.text)
+ cpu/bf533/serial.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ board/ezkit533/ezkit533.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
int checkboard (void)
{
- /* get revision from BCSR 3 */
+#if defined(CONFIG_MPC86xADS)
+ puts ("Board: MPC86xADS\n");
+#elif defined(CONFIG_MPC885ADS)
+ puts ("Board: MPC885ADS\n");
+#else /* Only old ADS/FADS have got revision ID in BCSR3 */
uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3)
| (((*((uint *) BCSR3) >> 19) & 1) << 2)
| (((*((uint *) BCSR3) >> 16) & 3));
puts ("Board: ");
-
-#if defined(CONFIG_MPC86xADS)
- puts ("MPC86xADS");
-#elif defined(CONFIG_MPC885ADS)
- puts ("MPC885ADS");
- r = 0; /* I've got NR (No Revision) board */
-#elif defined(CONFIG_FADS)
+#if defined(CONFIG_FADS)
puts ("FADS");
checkdboard ();
#else
puts ("ADS");
#endif
+
puts (" rev ");
switch (r) {
puts ("A - warning, read errata \n");
break;
case 0x03:
- puts ("B \n");
+ puts ("B\n");
break;
-#elif defined(CONFIG_MPC885ADS)
- case 0x00:
- puts ("NR\n");
- break;
-#else /* FADS and newer */
+#else /* FADS */
case 0x00:
puts ("ENG\n");
break;
printf ("unknown (0x%x)\n", r);
return -1;
}
+#endif /* CONFIG_MPC86xADS */
return 0;
}
switch ((pcmp->pcmc_pipr >> 14) & 3)
#endif
{
- case 0x00 :
+ case 0x03 :
printf("5V");
v = 5;
break;
v = 5;
#endif
break;
- case 0x03 :
+ case 0x00 :
printf("5V, 3V and x.xV");
#ifdef CONFIG_FADS
v = 3; /* User lower voltage if supported! */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND \
"dhcp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
"bootm"
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
+ "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
/*
- * New MPC86xADS and Duet provide two Ethernet connectivity options:
+ * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
* 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
* motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
* got FEC so FEC is the default.
#ifndef CONFIG_COMMANDS
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_ASKENV \
| CFG_CMD_DHCP \
+ | CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_JFFS2 \
| CFG_CMD_MII \
/*
* Miscellaneous configurable options
*/
-#undef CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=>" /* Monitor Command Prompt */
+#define CFG_PROMPT "=>" /* Monitor Command Prompt */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP /* #undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
+
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_SDRAM_BASE 0x00000000
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
+/*
+ * 2048 SDRAM rows
+ * 1000 factor s -> ms
+ * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
#elif defined(CONFIG_FADS) /* Old/new FADS */
#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
#else /* Old ADS */
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
/*-----------------------------------------------------------------------
* I2C configuration
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
-#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+#define CFG_SCCR SCCR_TBS
/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
+ * DER - Debug Enable Register
*-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control
- */
-#ifndef CFG_PLPRCR
-#define CFG_PLPRCR PLPRCR_TEXPS
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
+ * Set to zero to prevent the processor from entering debug mode
*/
#define CFG_DER 0
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently. Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register. For CS0, you must write the base register
-* first, followed by the option register.
-*/
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register. For CS0, you must write
+ * the base register first, followed by the option register.
+ */
/*
* Init Memory Controller:
/* values according to the manual */
-#define PCMCIA_MEM_ADDR ((uint)0xFF020000)
-#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
-
#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
#define BCSR4_TFPLDL ((uint)0x40000000)
#define BCSR4_TPSQEL ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
-#define BCSR4_FETH_EN ((uint)0x08000000)
-#define BCSR4_FETHCFG0 ((uint)0x04000000)
-#define BCSR4_FETHFDE ((uint)0x02000000)
-#define BCSR4_FETHCFG1 ((uint)0x00400000)
-#define BCSR4_FETHRST ((uint)0x00200000)
-
-#ifdef CONFIG_MPC823
+#if defined(CONFIG_MPC823)
#define BCSR4_USB_EN ((uint)0x08000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860SAR
-#define BCSR4_UTOPIA_EN ((uint)0x08000000)
-#endif /* CONFIG_MPC860SAR */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETH_EN ((uint)0x08000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED ((uint)0x04000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG0 ((uint)0x04000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
#define BCSR4_VCCO ((uint)0x02000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHFDE ((uint)0x02000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON ((uint)0x00800000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG1 ((uint)0x00400000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST ((uint)0x00200000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHRST ((uint)0x00200000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN ((uint)0x00100000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE ((uint)0x00080000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC850
+#elif defined(CONFIG_MPC850)
#define BCSR4_DATA_VOICE ((uint)0x00080000)
-#endif /* CONFIG_MPC850 */
+#elif defined(CONFIG_MPC860SAR)
+#define BCSR4_UTOPIA_EN ((uint)0x08000000)
+#else /* MPC860T and other chips with FEC */
+#define BCSR4_FETH_EN ((uint)0x08000000)
+#define BCSR4_FETHCFG0 ((uint)0x04000000)
+#define BCSR4_FETHFDE ((uint)0x02000000)
+#define BCSR4_FETHCFG1 ((uint)0x00400000)
+#define BCSR4_FETHRST ((uint)0x00200000)
+#endif
-/* BSCR5 exists on MPC86xADS and Duet ADS only */
+/* BSCR5 exists on MPC86xADS and MPC885ADS only */
#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
#define CFG_ATA_ALT_OFFSET 0x0000
#define CONFIG_DISK_SPINUP_TIME 1000000
-#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */
+/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */
#include <common.h>
+#ifndef CFG_FLASH_CFI_DRIVER
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
return (res);
}
+#endif /*CFG_FLASH_CFI_DRIVER*/
#include <mpc5xxx.h>
#include <pci.h>
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
+#if defined(CONFIG_LITE5200B)
+#include "mt46v32m16.h"
#else
+# if defined(CONFIG_MPC5200_DDR)
+# include "mt46v16m16-75.h"
+# else
#include "mt48lc16m16a2-75.h"
+# endif
#endif
-
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
int checkboard (void)
{
-#if defined(CONFIG_MPC5200)
+#if defined (CONFIG_LITE5200B)
+ puts ("Board: Freescale Lite5200B\n");
+#elif defined(CONFIG_MPC5200)
puts ("Board: Motorola MPC5200 (IceCube)\n");
#elif defined(CONFIG_MGT5100)
puts ("Board: Motorola MGT5100 (IceCube)\n");
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
* Copy memory to flash
*/
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)dest;
ulong result;
* Copy memory to flash
*/
-volatile static int write_word (flash_info_t * info, ulong dest,
- ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *) dest;
ulong result;
return rc;
}
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
return rc;
}
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o
+OBJS := $(BOARD).o pci.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
return 0;
}
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxads_config_table[] = {
- {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
- } },
- {}
-}
-#endif
-
-
-volatile static struct pci_controller hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxads_config_table,
-#endif
- },
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxads_config_table,
-#endif
- }
-};
-#endif /* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
-
- pci_mpc83xx_init(hose);
-#endif /* CONFIG_PCI */
-}
-
/*
* if MPC8349ADS is soldered with SDRAM
*/
--- /dev/null
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <common.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+
+#ifdef CONFIG_PCI
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ }
+ },
+ {}
+};
+#endif
+
+static struct pci_controller pci_hose[] = {
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxads_config_table,
+#endif
+ },
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxads_config_table,
+#endif
+ }
+};
+
+/**************************************************************************
+ *
+ * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
+ *
+ */
+void
+pib_init(void)
+{
+ u8 val8;
+ /*
+ * Assign PIB PMC slot to desired PCI bus
+ */
+ mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ val8 = 0;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(PCI_64BIT)
+ val8 = 0xf4; /* PMC2:PCI1/64-bit */
+#elif defined(PCI_ALL_PCI1)
+ val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
+#elif defined(PCI_ONE_PCI1)
+ val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
+#else
+ val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
+#endif
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+ val8 = 0;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+ asm("eieio");
+
+#if defined(PCI_64BIT)
+ printf("PCI1: 64-bit on PMC2\n");
+#elif defined(PCI_ALL_PCI1)
+ printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
+#elif defined(PCI_ONE_PCI1)
+ printf("PCI1: 32-bit on PMC1\n");
+ printf("PCI2: 32-bit on PMC2, PMC3\n");
+#else
+ printf("PCI1: 32-bit on PMC1, PMC2\n");
+ printf("PCI2: 32-bit on PMC3\n");
+#endif
+}
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not currently supported
+ *
+ */
+void
+pci_init_board(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t * immr;
+ volatile clk8349_t * clk;
+ volatile law8349_t * pci_law;
+ volatile pot8349_t * pci_pot;
+ volatile pcictrl8349_t * pci_ctrl;
+ volatile pciconf8349_t * pci_conf;
+ u16 reg16;
+ u32 reg32;
+ u32 dev;
+ struct pci_controller * hose;
+
+ immr = (immap_t *)CFG_IMMRBAR;
+ clk = (clk8349_t *)&immr->clk;
+ pci_law = immr->sysconf.pcilaw;
+ pci_pot = immr->ios.pot;
+ pci_ctrl = immr->pci_ctrl;
+ pci_conf = immr->pci_conf;
+
+ hose = &pci_hose[0];
+
+ pib_init();
+
+ /*
+ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+ */
+
+ reg32 = clk->occr;
+ udelay(2000);
+ clk->occr = 0xff000000;
+ udelay(2000);
+
+ /*
+ * Release PCI RST Output signal
+ */
+ pci_ctrl[0].gcr = 0;
+ udelay(2000);
+ pci_ctrl[0].gcr = 1;
+
+#ifdef CONFIG_MPC83XX_PCI2
+ pci_ctrl[1].gcr = 0;
+ udelay(2000);
+ pci_ctrl[1].gcr = 1;
+#endif
+
+ /* We need to wait at least a 1sec based on PCI specs */
+ {
+ int i;
+
+ for (i = 0; i < 1000; ++i)
+ udelay (1000);
+ }
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI1 mem space - prefetch */
+ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+ /* PCI1 IO space */
+ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+ /* PCI1 mmio - non-prefetch mem space */
+ pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* PCI memory prefetch space */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MMIO_BASE,
+ CFG_PCI1_MMIO_PHYS,
+ CFG_PCI1_MMIO_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose->region_count = 4;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMRBAR+0x8300),
+ (CFG_IMMRBAR+0x8304));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write to Command register
+ */
+ reg16 = 0xff;
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC83XX_PCI2
+ hose = &pci_hose[1];
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI2 mem space - prefetch */
+ pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+ /* PCI2 IO space */
+ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+ /* PCI2 mmio - non-prefetch mem space */
+ pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
+ pci_ctrl[1].pitar1 = 0x0;
+ pci_ctrl[1].pibar1 = 0x0;
+ pci_ctrl[1].piebar1 = 0x0;
+ pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+ hose->first_busno = pci_hose[0].last_busno + 1;
+ hose->last_busno = 0xff;
+
+ /* PCI memory prefetch space */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI2_MEM_BASE,
+ CFG_PCI2_MEM_PHYS,
+ CFG_PCI2_MEM_SIZE,
+ PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI2_MMIO_BASE,
+ CFG_PCI2_MMIO_PHYS,
+ CFG_PCI2_MMIO_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI2_IO_BASE,
+ CFG_PCI2_IO_PHYS,
+ CFG_PCI2_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose->region_count = 4;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMRBAR+0x8380),
+ (CFG_IMMRBAR+0x8384));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write to Command register
+ */
+ reg16 = 0xff;
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+#endif
+
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8349EMDS
+#
+
+TEXT_BASE = 0xFE000000
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+int board_early_init_f (void)
+{
+ volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+
+ /* Enable flash write */
+ bcsr[1] &= ~0x01;
+
+ return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ puts("Initializing\n");
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+ /*
+ * Initialize SDRAM if it is on local bus.
+ */
+ sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+ puts(" DDR RAM: ");
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CFG_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1);
+ ddr_size = ddr_size>>1, ddr_size_log2++) {
+ if (ddr_size & 1) {
+ return -1;
+ }
+ }
+ im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+ im->ddr.csbnds[2].csbnds = 0x0000000f;
+ im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+
+ /* currently we use only one CS, so disable the other banks */
+ im->ddr.cs_config[0] = 0;
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[3] = 0;
+
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+
+ im->ddr.sdram_cfg =
+ SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+ | SDRAM_CFG_2T_EN
+#endif
+ | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+ /* for 32-bit mode burst length is 8 */
+ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+ im->ddr.sdram_mode = CFG_DDR_MODE;
+
+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ return msize;
+}
+#endif/*!CFG_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+ puts("Board: Freescale MPC8349EMDS\n");
+ return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8349emds_config_table[] = {
+ {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
+ } },
+ {}
+}
+#endif
+
+volatile static struct pci_controller hose[] = {
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc8349emds_config_table,
+#endif
+ },
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc8349emds_config_table,
+#endif
+ }
+};
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+
+ pci_mpc83xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+/*
+ * if MPC8349EMDS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM) \
+ && defined(CFG_OR2_PRELIM) \
+ && defined(CFG_LBLAWBAR2_PRELIM) \
+ && defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile lbus8349_t *lbc= &immap->lbus;
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+ puts("\n SDRAM on Local Bus: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+ */
+
+ /* setup mtrpt, lsrt and lbcr for LB bus */
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller Machine Mode Register.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+ lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ asm("sync");
+ /*1 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*2 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*3 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*4 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*5 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*6 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*7 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*8 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ /* 0x58636733; mode register write operation */
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+}
+#else
+void sdram_init(void)
+{
+ put("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+/*
+ * ECC user commands
+ */
+void ecc_print_status(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile ddr8349_t *ddr = &immap->ddr;
+
+ printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+ /* Interrupts */
+ printf("Memory Error Interrupt Enable:\n");
+ printf(" Multiple-Bit Error Interrupt Enable: %d\n",
+ (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+ printf(" Single-Bit Error Interrupt Enable: %d\n",
+ (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+ printf(" Memory Select Error Interrupt Enable: %d\n\n",
+ (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+ /* Error disable */
+ printf("Memory Error Disable:\n");
+ printf(" Multiple-Bit Error Disable: %d\n",
+ (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+ printf(" Sinle-Bit Error Disable: %d\n",
+ (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+ printf(" Memory Select Error Disable: %d\n\n",
+ (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+ /* Error injection */
+ printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
+ ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+ printf("Memory Data Path Error Injection Mask ECC:\n");
+ printf(" ECC Mirror Byte: %d\n",
+ (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+ printf(" ECC Injection Enable: %d\n",
+ (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+ printf(" ECC Error Injection Mask: 0x%02x\n\n",
+ ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+ /* SBE counter/threshold */
+ printf("Memory Single-Bit Error Management (0..255):\n");
+ printf(" Single-Bit Error Threshold: %d\n",
+ (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+ printf(" Single-Bit Error Counter: %d\n\n",
+ (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+ /* Error detect */
+ printf("Memory Error Detect:\n");
+ printf(" Multiple Memory Errors: %d\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+ printf(" Multiple-Bit Error: %d\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+ printf(" Single-Bit Error: %d\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+ printf(" Memory Select Error: %d\n\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+ /* Capture data */
+ printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
+ printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
+ ddr->capture_data_hi, ddr->capture_data_lo);
+ printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+ ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+ printf("Memory Error Attributes Capture:\n");
+ printf(" Data Beat Number: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
+ printf(" Transaction Size: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
+ printf(" Transaction Source: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
+ printf(" Transaction Type: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
+ printf(" Error Information Valid: %d\n\n",
+ ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile ddr8349_t *ddr = &immap->ddr;
+ volatile u32 val;
+ u64 *addr, count, val64;
+ register u64 *i;
+
+ if (argc > 4) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (argc == 2) {
+ if (strcmp(argv[1], "status") == 0) {
+ ecc_print_status();
+ return 0;
+ } else if (strcmp(argv[1], "captureclear") == 0) {
+ ddr->capture_address = 0;
+ ddr->capture_data_hi = 0;
+ ddr->capture_data_lo = 0;
+ ddr->capture_ecc = 0;
+ ddr->capture_attributes = 0;
+ return 0;
+ }
+ }
+
+ if (argc == 3) {
+ if (strcmp(argv[1], "sbecnt") == 0) {
+ val = simple_strtoul(argv[2], NULL, 10);
+ if (val > 255) {
+ printf("Incorrect Counter value, should be 0..255\n");
+ return 1;
+ }
+
+ val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+ val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+ ddr->err_sbe = val;
+ return 0;
+ } else if (strcmp(argv[1], "sbethr") == 0) {
+ val = simple_strtoul(argv[2], NULL, 10);
+ if (val > 255) {
+ printf("Incorrect Counter value, should be 0..255\n");
+ return 1;
+ }
+
+ val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+ val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+ ddr->err_sbe = val;
+ return 0;
+ } else if (strcmp(argv[1], "errdisable") == 0) {
+ val = ddr->err_disable;
+
+ if (strcmp(argv[2], "+sbe") == 0) {
+ val |= ECC_ERROR_DISABLE_SBED;
+ } else if (strcmp(argv[2], "+mbe") == 0) {
+ val |= ECC_ERROR_DISABLE_MBED;
+ } else if (strcmp(argv[2], "+mse") == 0) {
+ val |= ECC_ERROR_DISABLE_MSED;
+ } else if (strcmp(argv[2], "+all") == 0) {
+ val |= (ECC_ERROR_DISABLE_SBED |
+ ECC_ERROR_DISABLE_MBED |
+ ECC_ERROR_DISABLE_MSED);
+ } else if (strcmp(argv[2], "-sbe") == 0) {
+ val &= ~ECC_ERROR_DISABLE_SBED;
+ } else if (strcmp(argv[2], "-mbe") == 0) {
+ val &= ~ECC_ERROR_DISABLE_MBED;
+ } else if (strcmp(argv[2], "-mse") == 0) {
+ val &= ~ECC_ERROR_DISABLE_MSED;
+ } else if (strcmp(argv[2], "-all") == 0) {
+ val &= ~(ECC_ERROR_DISABLE_SBED |
+ ECC_ERROR_DISABLE_MBED |
+ ECC_ERROR_DISABLE_MSED);
+ } else {
+ printf("Incorrect err_disable field\n");
+ return 1;
+ }
+
+ ddr->err_disable = val;
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+ return 0;
+ } else if (strcmp(argv[1], "errdetectclr") == 0) {
+ val = ddr->err_detect;
+
+ if (strcmp(argv[2], "mme") == 0) {
+ val |= ECC_ERROR_DETECT_MME;
+ } else if (strcmp(argv[2], "sbe") == 0) {
+ val |= ECC_ERROR_DETECT_SBE;
+ } else if (strcmp(argv[2], "mbe") == 0) {
+ val |= ECC_ERROR_DETECT_MBE;
+ } else if (strcmp(argv[2], "mse") == 0) {
+ val |= ECC_ERROR_DETECT_MSE;
+ } else if (strcmp(argv[2], "all") == 0) {
+ val |= (ECC_ERROR_DETECT_MME |
+ ECC_ERROR_DETECT_MBE |
+ ECC_ERROR_DETECT_SBE |
+ ECC_ERROR_DETECT_MSE);
+ } else {
+ printf("Incorrect err_detect field\n");
+ return 1;
+ }
+
+ ddr->err_detect = val;
+ return 0;
+ } else if (strcmp(argv[1], "injectdatahi") == 0) {
+ val = simple_strtoul(argv[2], NULL, 16);
+
+ ddr->data_err_inject_hi = val;
+ return 0;
+ } else if (strcmp(argv[1], "injectdatalo") == 0) {
+ val = simple_strtoul(argv[2], NULL, 16);
+
+ ddr->data_err_inject_lo = val;
+ return 0;
+ } else if (strcmp(argv[1], "injectecc") == 0) {
+ val = simple_strtoul(argv[2], NULL, 16);
+ if (val > 0xff) {
+ printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
+ return 1;
+ }
+ val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+ ddr->ecc_err_inject = val;
+ return 0;
+ } else if (strcmp(argv[1], "inject") == 0) {
+ val = ddr->ecc_err_inject;
+
+ if (strcmp(argv[2], "en") == 0)
+ val |= ECC_ERR_INJECT_EIEN;
+ else if (strcmp(argv[2], "dis") == 0)
+ val &= ~ECC_ERR_INJECT_EIEN;
+ else
+ printf("Incorrect command\n");
+
+ ddr->ecc_err_inject = val;
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+ return 0;
+ } else if (strcmp(argv[1], "mirror") == 0) {
+ val = ddr->ecc_err_inject;
+
+ if (strcmp(argv[2], "en") == 0)
+ val |= ECC_ERR_INJECT_EMB;
+ else if (strcmp(argv[2], "dis") == 0)
+ val &= ~ECC_ERR_INJECT_EMB;
+ else
+ printf("Incorrect command\n");
+
+ ddr->ecc_err_inject = val;
+ return 0;
+ }
+ }
+
+ if (argc == 4) {
+ if (strcmp(argv[1], "test") == 0) {
+ addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
+ count = simple_strtoul(argv[3], NULL, 16);
+
+ if ((u32)addr % 8) {
+ printf("Address not alligned on double word boundary\n");
+ return 1;
+ }
+
+ disable_interrupts();
+ icache_disable();
+
+ for (i = addr; i < addr + count; i++) {
+ /* enable injects */
+ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ /* write memory location injecting errors */
+ *i = 0x1122334455667788ULL;
+ __asm__ __volatile__ ("sync");
+
+ /* disable injects */
+ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ /* read data, this generates ECC error */
+ val64 = *i;
+ __asm__ __volatile__ ("sync");
+
+ /* disable errors for ECC */
+ ddr->err_disable |= ~ECC_ERROR_ENABLE;
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ /* re-initialize memory, write the location again
+ * NOT injecting errors this time */
+ *i = 0xcafecafecafecafeULL;
+ __asm__ __volatile__ ("sync");
+
+ /* enable errors for ECC */
+ ddr->err_disable &= ECC_ERROR_ENABLE;
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+ }
+
+ icache_enable();
+ enable_interrupts();
+
+ return 0;
+ }
+ }
+
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ ecc, 4, 0, do_ecc,
+ "ecc - support for DDR ECC features\n",
+ "status - print out status info\n"
+ "ecc captureclear - clear capture regs data\n"
+ "ecc sbecnt <val> - set Single-Bit Error counter\n"
+ "ecc sbethr <val> - set Single-Bit Threshold\n"
+ "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
+ " [-|+]sbe - Single-Bit Error\n"
+ " [-|+]mbe - Multiple-Bit Error\n"
+ " [-|+]mse - Memory Select Error\n"
+ " [-|+]all - all errors\n"
+ "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+ " mme - Multiple Memory Errors\n"
+ " sbe - Single-Bit Error\n"
+ " mbe - Multiple-Bit Error\n"
+ " mse - Memory Select Error\n"
+ " all - all errors\n"
+ "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
+ "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
+ "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
+ "ecc inject <en|dis> - enable/disable error injection\n"
+ "ecc mirror <en|dis> - enable/disable mirror byte\n"
+ "ecc test <addr> <cnt> - test mem region:\n"
+ " - enables injects\n"
+ " - writes pattern injecting errors\n"
+ " - disables injects\n"
+ " - reads pattern back, generates error\n"
+ " - re-inits memory"
+);
+#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc83xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
--include .depend
+sinclude .depend
#########################################################################
* Copy memory to flash
*/
-volatile static int write_hword(flash_info_t *info, ulong dest, ushort data)
+static int write_hword(flash_info_t *info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
/*
* chip R/B detection
*/
+/***
static int netstar_nand_ready(struct mtd_info *mtd)
{
return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
}
+***/
void board_nand_init(struct nand_chip *nand)
{
* Copy memory to flash
*/
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)dest;
ulong result;
* Copy memory to flash
*/
-volatile static int write_word (flash_info_t * info, ulong dest,
- ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *) dest;
ulong result;
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o stamp.o
+SOBJS =
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x07FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
--- /dev/null
+/*
+ * U-boot - stamp.c STAMP board specific routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mem_init.h>
+#include "stamp.h"
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON 1
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+int checkboard (void)
+{
+ printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+ printf ("Board: ADI BF533 Stamp board\n");
+ printf (" Support: http://blackfin.uclinux.org/\n");
+ printf (" Richard Klingler <richard@uclinux.net>\n");
+ return 0;
+}
+
+long int initdram (int board_type)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+ printf ("SDRAM attributes:\n");
+ printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
+ "CAS Latency:%d cycles\n",
+ (SDRAM_tRCD >> 15),
+ (SDRAM_tRP >> 11),
+ (SDRAM_tRAS >> 6),
+ (SDRAM_tWR >> 19),
+ (SDRAM_CL >> 2));
+ printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+ printf ("Bank size = %d MB\n", 128);
+#endif
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+ return (gd->bd->bi_memsize);
+}
+
+void swap_to (int device_id)
+{
+
+ if (device_id == ETHERNET) {
+ *pFIO_DIR = PF0;
+ asm ("ssync;");
+ *pFIO_FLAG_S = PF0;
+ asm ("ssync;");
+ } else if (device_id == FLASH) {
+ *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
+ *pFIO_FLAG_S = (PF4 | PF3 | PF2);
+ *pFIO_MASKA_D = (PF8 | PF6 | PF5);
+ *pFIO_MASKB_D = (PF7);
+ *pFIO_POLAR = (PF8 | PF6 | PF5);
+ *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
+ *pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
+ *pFIO_FLAG_D = (PF4 | PF3 | PF2);
+ asm ("ssync;");
+ } else {
+ printf ("Unknown bank to switch\n");
+ }
+
+ return;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r (void)
+{
+ int i;
+ int cf_stat = 0;
+
+ /* Check whether CF card is inserted */
+ *pFIO_EDGE = FIO_EDGE_CF_BITS;
+ *pFIO_POLAR = FIO_POLAR_CF_BITS;
+ for (i = 0; i < 0x300; i++)
+ asm ("nop;");
+
+ if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
+ cf_stat = 0;
+ } else {
+ cf_stat = 1;
+ }
+
+ *pFIO_EDGE = FIO_EDGE_BITS;
+ *pFIO_POLAR = FIO_POLAR_BITS;
+
+
+ if (cf_stat) {
+ printf ("Booting from COMPACT flash\n");
+
+ /* Set cycle time for CF */
+ *(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
+
+ for (i = 0; i < 0x1000; i++)
+ asm ("nop;");
+ for (i = 0; i < 0x1000; i++)
+ asm ("nop;");
+ for (i = 0; i < 0x1000; i++)
+ asm ("nop;");
+
+ serial_setbrg ();
+ ide_init ();
+
+ setenv ("bootargs", "");
+ setenv ("bootcmd",
+ "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
+ } else {
+ printf ("Booting from FLASH\n");
+ }
+
+ return 1;
+}
+#endif
+
+#ifdef CONFIG_STAMP_CF
+
+void cf_outb (unsigned char val, volatile unsigned char *addr)
+{
+ /*
+ * Set PF1 PF0 respectively to 0 1 to divert address
+ * to the expansion memory banks
+ */
+ *pFIO_FLAG_S = CF_PF0;
+ *pFIO_FLAG_C = CF_PF1;
+ asm ("ssync;");
+
+ *(addr) = val;
+ asm ("ssync;");
+
+ /* Setback PF1 PF0 to 0 0 to address external
+ * memory banks */
+ *(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
+ asm ("ssync;");
+}
+
+unsigned char cf_inb (volatile unsigned char *addr)
+{
+ volatile unsigned char c;
+
+ *pFIO_FLAG_S = CF_PF0;
+ *pFIO_FLAG_C = CF_PF1;
+ asm ("ssync;");
+
+ c = *(addr);
+ asm ("ssync;");
+
+ *pFIO_FLAG_C = CF_PF1_PF0;
+ asm ("ssync;");
+
+ return c;
+}
+
+void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
+{
+ int i;
+
+ *pFIO_FLAG_S = CF_PF0;
+ *pFIO_FLAG_C = CF_PF1;
+ asm ("ssync;");
+
+ for (i = 0; i < words; i++) {
+ *(sect_buf + i) = *(addr);
+ asm ("ssync;");
+ }
+
+ *pFIO_FLAG_C = CF_PF1_PF0;
+ asm ("ssync;");
+}
+
+void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
+{
+ int i;
+
+ *pFIO_FLAG_S = CF_PF0;
+ *pFIO_FLAG_C = CF_PF1;
+ asm ("ssync;");
+
+ for (i = 0; i < words; i++) {
+ *(addr) = *(sect_buf + i);
+ asm ("ssync;");
+ }
+
+ *pFIO_FLAG_C = CF_PF1_PF0;
+ asm ("ssync;");
+}
+#endif
+
+void stamp_led_set (int LED1, int LED2, int LED3)
+{
+ *pFIO_INEN &= ~(PF2 | PF3 | PF4);
+ *pFIO_DIR |= (PF2 | PF3 | PF4);
+
+ if (LED1 == STATUS_LED_OFF)
+ *pFIO_FLAG_S = PF2;
+ else
+ *pFIO_FLAG_C = PF2;
+ if (LED2 == STATUS_LED_OFF)
+ *pFIO_FLAG_S = PF3;
+ else
+ *pFIO_FLAG_C = PF3;
+ if (LED3 == STATUS_LED_OFF)
+ *pFIO_FLAG_S = PF4;
+ else
+ *pFIO_FLAG_C = PF4;
+ asm ("ssync;");
+}
+
+void show_boot_progress (int status)
+{
+ switch (status) {
+ case 1:
+ stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
+ break;
+ case 2:
+ stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
+ break;
+ case 3:
+ stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
+ break;
+ case 4:
+ stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
+ break;
+ case 5:
+ case 6:
+ stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
+ break;
+ case 7:
+ case 8:
+ stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
+ break;
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
+ STATUS_LED_OFF);
+ break;
+ default:
+ stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
+ break;
+ }
+}
--- /dev/null
+/*
+ * U-boot - stamp.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __STAMP_H__
+#define __STAMP_H__
+
+extern void init_Flags(void);
+
+extern volatile unsigned long *ambctl0;
+extern volatile unsigned long *ambctl1;
+extern volatile unsigned long *amgctl;
+
+extern unsigned long pll_div_fact;
+extern void serial_setbrg(void);
+extern void pll_set(int vco, int crystal_frq, int pll_div);
+
+/* Definitions used in Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS 0x0000
+#define FIO_POLAR_CF_BITS 0x0000
+#define FIO_EDGE_BITS 0x1E0
+#define FIO_POLAR_BITS 0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS 0x00000060
+
+/* CF Flags used to switch between expansion and external
+ * memory banks
+ */
+#define CF_PF0 0x0001
+#define CF_PF1 0x0002
+#define CF_PF1_PF0 0x0003
+
+#endif
--- /dev/null
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector before the environment sector. If it throws */
+ /* an error during compilation remove an object here to get */
+ /* it linked after the configuration sector. */
+
+ cpu/bf533/start.o (.text)
+ cpu/bf533/start1.o (.text)
+ cpu/bf533/traps.o (.text)
+ cpu/bf533/interrupt.o (.text)
+ cpu/bf533/serial.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
$(OBJCOPY) -O srec $(<:.o=) $@
trab_fkt.bin: trab_fkt.srec
- $(OBJCOPY) -O binary $< $@ 2>/dev/null
+ $(OBJCOPY) -I srec -O binary $< $@
clean:
rm -f $(SOBJS) $(OBJS)
* Copy memory to flash
*/
-volatile static int write_word (flash_info_t * info, ulong dest,
- ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *) dest;
ulong result;
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
-./mkconfig -a versatile arm arm926ejs versatile
+./mkconfig -a versatile arm arm926ejs versatile NULL versatile
echo "Variant:: $variant"
#include <common.h>
#include <net.h>
-#include <configs/ml300.h>
#include "xparameters.h"
#include "xemac.h"
#include <common.h>
#include <environment.h>
#include <net.h>
-#include <configs/ml300.h>
#include "xparameters.h"
#ifdef CFG_ENV_IS_IN_EEPROM
# ZPC.1900 board
#
-TEXT_BASE = 0xFFE00000
+TEXT_BASE = 0xFE000000
* (C) Copyright 2001-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2003 Arabella Software Ltd.
+ * (C) Copyright 2003-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
#include <miiphy.h>
/*
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
vu_char *ramaddr;
uchar c = 0xFF;
long int msize = CFG_SDRAM_SIZE;
- uint psdmr = CFG_PSDMR;
int i;
if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
- immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+ immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
immap->im_siu_conf.sc_siumcr =
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
*/
if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
memctl->memc_lsrt = CFG_LSRT;
- memctl->memc_or4 = 0xFFC01480;
- memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
- memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
+ memctl->memc_or4 = CFG_LSDRAM_OR;
+ memctl->memc_br4 = CFG_LSDRAM_BR;
ramaddr = (vu_char *)CFG_LSDRAM_BASE;
+ memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
/* Initialise 60x bus SDRAM */
memctl->memc_psrt = CFG_PSRT;
- memctl->memc_or2 = 0xFC0028C0;
- memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
+ memctl->memc_or2 = CFG_PSDRAM_OR;
+ memctl->memc_br2 = CFG_PSDRAM_BR;
/*
* The mode data for Mode Register Write command must appear on
* the address lines during a mode-set cycle. It is driven by
* length must be 4.
*/
ramaddr = (vu_char *)(CFG_SDRAM_BASE |
- ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+ ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
*ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
for (i = 0; i < 8; i++)
*ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */
*ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */
*ramaddr = c;
#endif /* CFG_RAMBOOT */
/*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
extern void lynxkdi_boot( image_header_t * );
#endif
+#ifndef CFG_BOOTM_LEN
+#define CFG_BOOTM_LEN 0x800000 /* use 8MByte as default max gunzip size */
+#endif
+
image_header_t header;
ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */
ulong addr;
ulong data, len, checksum;
ulong *len_ptr;
- uint unc_len = 0x400000;
+ uint unc_len = CFG_BOOTM_LEN;
int i, verify;
char *name, *s;
int (*appl)(int, char *[]);
if (hdr->ih_arch != IH_CPU_MICROBLAZE)
#elif defined(__nios2__)
if (hdr->ih_arch != IH_CPU_NIOS2)
+#elif defined(__blackfin__)
+ if (hdr->ih_arch != IH_CPU_BLACKFIN)
#else
# error Unknown CPU type
#endif
#endif /* CONFIG_MPC5xxx */
}
- kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep;
+ kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong)) ntohl(hdr->ih_ep);
/*
* Check if there is an initrd image
/* Copy header so we can blank CRC field for re-calculation */
memmove (&header, (char *)addr, sizeof(image_header_t));
- if (hdr->ih_magic != IH_MAGIC) {
+ if (ntohl(hdr->ih_magic) != IH_MAGIC) {
puts ("Bad Magic Number\n");
SHOW_BOOT_PROGRESS (-10);
do_reset (cmdtp, flag, argc, argv);
data = (ulong)&header;
len = sizeof(image_header_t);
- checksum = hdr->ih_hcrc;
+ checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
if (crc32 (0, (uchar *)data, len) != checksum) {
print_image_hdr (hdr);
data = addr + sizeof(image_header_t);
- len = hdr->ih_size;
+ len = ntohl(hdr->ih_size);
if (verify) {
ulong csum = 0;
csum = crc32 (0, (uchar *)data, len);
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
- if (csum != hdr->ih_dcrc) {
+ if (csum != ntohl(hdr->ih_dcrc)) {
puts ("Bad Data CRC\n");
SHOW_BOOT_PROGRESS (-12);
do_reset (cmdtp, flag, argc, argv);
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
#else
- ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd);
+ ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end);
/* ft_dump_blob(of_flat_tree); */
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
/*
* Linux Kernel Parameters:
* r3: ptr to OF flat tree, followed by the board info data
- * r4: initrd_start or 0 if no initrd
- * r5: initrd_end - unused if r4 is 0
- * r6: Start of command line string
- * r7: End of command line string
+ * r4: physical pointer to the kernel itself
+ * r5: NULL
+ * r6: NULL
+ * r7: NULL
*/
- (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, cmd_start, cmd_end);
+ if (getenv("disable_of") != NULL)
+ (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end,
+ cmd_start, cmd_end);
+ else
+ (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
#endif
}
cmdline = "";
}
- loader = (void (*)(bd_t *, image_header_t *, char *, char *)) hdr->ih_ep;
+ loader = (void (*)(bd_t *, image_header_t *, char *, char *)) ntohl(hdr->ih_ep);
printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n",
(ulong)loader);
image_header_t *hdr = &header;
void (*entry_point)(bd_t *);
- entry_point = (void (*)(bd_t *)) hdr->ih_ep;
+ entry_point = (void (*)(bd_t *)) ntohl(hdr->ih_ep);
printf ("## Transferring control to RTEMS (at address %08lx) ...\n",
(ulong)entry_point);
image_header_t *hdr = &header;
char str[80];
- sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */
+ sprintf(str, "%x", ntohl(hdr->ih_ep)); /* write entry-point into string */
setenv("loadaddr", str);
do_bootvx(cmdtp, 0, 0, NULL);
}
char *local_args[2];
char str[16];
- sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */
+ sprintf(str, "%x", ntohl(hdr->ih_ep)); /* write entry-point into string */
local_args[0] = argv[0];
local_args[1] = str; /* and provide it via the arguments */
do_bootelf(cmdtp, 0, 2, local_args);
print_image_hdr (hdr);
- cnt = (hdr->ih_size + sizeof(image_header_t));
+ cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
cnt -= SECTORSIZE;
} else {
puts ("\n** Bad Magic Number **\n");
return 1;
}
hdr = (image_header_t *)addr;
- if (hdr->ih_magic != IH_MAGIC) {
+ if (ntohl(hdr->ih_magic) != IH_MAGIC) {
printf ("Bad Magic Number\n");
return 1;
}
print_image_hdr(hdr);
- imsize= hdr->ih_size+sizeof(image_header_t);
+ imsize= ntohl(hdr->ih_size)+sizeof(image_header_t);
nrofblk=imsize/512;
if((imsize%512)>0)
nrofblk++;
cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
cnt -= SECTORSIZE;
} else {
- printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
+ printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic));
SHOW_BOOT_PROGRESS (-1);
return 1;
}
NULL
);
+#if (CONFIG_COMMANDS & CFG_CMD_ECHO)
+
int
do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
" - echo args to console; \\c suppresses newline\n"
);
+#endif /* CFG_CMD_ECHO */
+
#ifdef CFG_HUSH_PARSER
int
#ifdef CFG_ENV_OFFSET_REDUND
int saveenv(void)
{
- int total, ret = 0;
+ ulong total;
+ int ret = 0;
DECLARE_GLOBAL_DATA_PTR;
#else /* ! CFG_ENV_OFFSET_REDUND */
int saveenv(void)
{
- int total, ret = 0;
+ ulong total;
+ int ret = 0;
puts ("Erasing Nand...");
if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE))
puts ("Writing to Nand... ");
total = CFG_ENV_SIZE;
- ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total,
- (u_char*) env_ptr);
+ ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr);
if (ret || total != CFG_ENV_SIZE)
return 1;
void env_relocate_spec (void)
{
#if !defined(ENV_IS_EMBEDDED)
- int crc1_ok = 0, crc2_ok = 0, total;
+ ulong total;
+ int crc1_ok = 0, crc2_ok = 0;
env_t *tmp_env1, *tmp_env2;
DECLARE_GLOBAL_DATA_PTR;
void env_relocate_spec (void)
{
#if !defined(ENV_IS_EMBEDDED)
- int ret, total;
+ ulong total;
+ int ret;
total = CFG_ENV_SIZE;
- ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total,
- (u_char*) env_ptr);
- if (ret || total != CFG_ENV_SIZE)
+ ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr);
+ if (ret || total != CFG_ENV_SIZE)
return use_default();
if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc)
((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
((u64 *) cxt->pres)[1] = cpu_to_be64(size);
- cxt->pres += 18; /* advance */
+ cxt->pres += 16; /* advance */
((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
((u64 *) cxt->pres)[1] = 0;
#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
+#ifdef CONFIG_OF_HAS_BD_T
static const struct {
const char *name;
int offset;
#endif
BDM(baudrate),
};
+#endif
-void ft_setup(void *blob, int size, bd_t * bd)
+void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end)
{
- DECLARE_GLOBAL_DATA_PTR;
- u8 *end;
u32 *p;
int len;
struct ft_cxt cxt;
- int i, k, nxt;
- static char tmpenv[256];
- char *s, *lval, *rval;
ulong clock;
- uint32_t v;
+#if defined(CONFIG_OF_HAS_UBOOT_ENV)
+ int k, nxt;
+#endif
+#if defined(CONFIG_OF_HAS_BD_T)
+ u8 *end;
+#endif
+#if defined(CONFIG_OF_HAS_UBOOT_ENV) || defined(CONFIG_OF_HAS_BD_T)
+ int i;
+ static char tmpenv[256];
+#endif
/* disable OF tree; booting old kernel */
if (getenv("disable_of") != NULL) {
ft_begin(&cxt, blob, size);
- /* fs_add_rsvmap not used */
+ if (initrd_start && initrd_end)
+ ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1);
ft_begin_tree(&cxt);
/* back into root */
ft_backtrack_node(&cxt);
+#ifdef CONFIG_OF_HAS_UBOOT_ENV
ft_begin_node(&cxt, "u-boot-env");
for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
+ char *s, *lval, *rval;
+
for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ;
s = tmpenv;
for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
}
ft_end_node(&cxt);
+#endif
ft_begin_node(&cxt, "chosen");
ft_prop_str(&cxt, "name", "chosen");
ft_prop_str(&cxt, "bootargs", getenv("bootargs"));
ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */
+ if (initrd_start && initrd_end) {
+ ft_prop_int(&cxt, "linux,initrd-start", initrd_start);
+ ft_prop_int(&cxt, "linux,initrd-end", initrd_end);
+ }
+#ifdef OF_STDOUT_PATH
+ ft_prop_str(&cxt, "linux,stdout-path", OF_STDOUT_PATH);
+#endif
ft_end_node(&cxt);
ft_dump_blob(blob);
*/
+#ifdef CONFIG_OF_HAS_BD_T
/* paste the bd_t at the end of the flat tree */
end = (char *)blob +
be32_to_cpu(((struct boot_param_header *)blob)->totalsize);
memcpy(end, bd, sizeof(*bd));
+#endif
#ifdef CONFIG_PPC
+#ifdef CONFIG_OF_HAS_BD_T
for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
+ uint32_t v;
+
sprintf(tmpenv, "/bd_t/%s", bd_map[i].name);
v = *(uint32_t *)((char *)bd + bd_map[i].offset);
p = ft_get_prop(blob, "/bd_t/ethspeed", &len);
if (p != NULL)
*p = cpu_to_be32((uint32_t) bd->bi_ethspeed);
+#endif
clock = bd->bi_intfreq;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/clock-frequency", &len);
clock = OF_TBCLK;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/timebase-frequency", &len);
if (p != NULL)
- *p = cpu_to_be32(OF_TBCLK);
+ *p = cpu_to_be32(clock);
#endif
-
#endif /* __powerpc__ */
+#ifdef CONFIG_OF_BOARD_SETUP
+ ft_board_setup(blob, bd);
+#endif
+
/*
printf("final OF-tree\n");
ft_dump_blob(blob);
#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
void lynxkdi_boot ( image_header_t *hdr )
{
- void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep;
+ void (*lynxkdi)(void) = (void(*)(void)) ntohl(hdr->ih_ep);
lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020;
bd_t *kbd;
DECLARE_GLOBAL_DATA_PTR;
- u32 *psz = (u32 *)(hdr->ih_load + 0x0204);
+ u32 *psz = (u32 *)(ntohl(hdr->ih_load) + 0x0204);
memset( parms, 0, sizeof(*parms));
kbd = gd->bd;
/* Do a simple check for Bluecat so we can pass the
* kernel command line parameters.
*/
- if( le32_to_cpu(*psz) == hdr->ih_size ){
+ if( le32_to_cpu(*psz) == ntohl(hdr->ih_size) ){ /* FIXME: NOT SURE HERE ! */
char *args;
- char *cmdline = (char *)(hdr->ih_load + 0x020c);
+ char *cmdline = (char *)(ntohl(hdr->ih_load) + 0x020c);
int len;
printf("Booting Bluecat KDI ...\n");
process_macros (token, finaltoken);
/* Extract arguments */
- argc = parse_line (finaltoken, argv);
+ if ((argc = parse_line (finaltoken, argv)) == 0) {
+ rc = -1; /* no command at all */
+ continue;
+ }
/* Look up command in command table */
if ((cmdtp = find_cmd(argv[0])) == NULL) {
puts ("'bootd' recursion detected\n");
rc = -1;
continue;
- }
- else
+ } else {
flag |= CMD_FLAG_BOOTD;
+ }
}
#endif /* CFG_CMD_BOOTD */
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
- I2C_ACTIVE;
I2C_SCL(0);
I2C_DELAY;
-
- I2C_SDA(ack);
-
I2C_ACTIVE;
+ I2C_SDA(ack);
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
{
int rc;
- /* perform 1 byte read transaction */
+ /*
+ * perform 1 byte write transaction with just address byte
+ * (fake write)
+ */
send_start();
rc = write_byte ((addr << 1) | 0);
send_stop();
endif
endif
+ifeq ($(ARCH),blackfin)
+PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore
+endif
+
ifdef ARCH
sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
endif
int
i2c_probe(unsigned char chip)
{
- char buffer[1];
+ unsigned char buffer[1];
return at91_xfer(chip, 0, 0, buffer, 1, 1);
}
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ unsigned char buf;
i2c_read(i2c_addr, reg, 1, &buf, 1);
}
/* FIXME this is a second HC reset; why?? */
- writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+ gohci.hc_control = OHCI_USB_RESET;
+ writel (gohci.hc_control, &gohci.regs->control);
wait_ms (10);
if (hc_start (&gohci) < 0) {
#include <arm926ejs.h>
#include <asm/proc-armv/ptrace.h>
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#ifdef CONFIG_OMAP
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
-#endif
-#ifdef CONFIG_VERSATILE
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
-#endif
-
#ifdef CONFIG_USE_IRQ
/* enable IRQ interrupts */
void enable_interrupts (void)
#else
-static ulong timestamp;
-static ulong lastdec;
-
/* nothing really to do with interrupts, just starts up a counter. */
int interrupt_init (void)
{
-#ifdef CONFIG_OMAP
- int32_t val;
-
- /* Start the decrementer ticking down from 0xffffffff */
- *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
- *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
-#endif /* CONFIG_OMAP */
-
-#ifdef CONFIG_VERSATILE
- *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */
- *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */
- *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
-#endif /* CONFIG_VERSATILE */
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
+ extern void timer_init(void);
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
+ timer_init();
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- }else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer (0); /* get current timestamp */
- if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
- else
- tmo += tmp; /* else, set advancing stamp wake up time */
-
- while (get_timer_masked () < tmo)/* loop till event */
- /*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER; /* capure current decrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (lastdec >= now) { /* normal mode (non roll) */
- /* normal mode */
- timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
- } else { /* we have overflow of the count down timer */
- /* nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll and cause problems.
- */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
- tmo /= (1000*1000);
- }
-
- endtime = get_timer_masked () + tmo;
-
- do {
- ulong now = get_timer_masked ();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return tbclk;
+ return 0;
}
#endif /* CONFIG_INTEGRATOR */
--- /dev/null
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(SOC).a
+
+OBJS = timer.o
+SOBJS = reset.o
+
+all: .depend $(LIB)
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+ ldr r1, rstctl1 /* get clkm1 reset ctl */
+ mov r3, #0x0
+ strh r3, [r1] /* clear it */
+ mov r3, #0x8
+ strh r3, [r1] /* force dsp+arm reset */
+_loop_forever:
+ b _loop_forever
+
+rstctl1:
+ .word 0xfffece10
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm926ejs.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init (void)
+{
+ int32_t val;
+
+ /* Start the decrementer ticking down from 0xffffffff */
+ *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+ val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
+ *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo /= 1000; /* finish normalize. */
+ }else{ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+
+ tmp = get_timer (0); /* get current timestamp */
+ if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
+ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
+ else
+ tmo += tmp; /* else, set advancing stamp wake up time */
+
+ while (get_timer_masked () < tmo)/* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = READ_TIMER; /* capure current decrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+ ulong now = READ_TIMER; /* current tick value */
+
+ if (lastdec >= now) { /* normal mode (non roll) */
+ /* normal mode */
+ timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+ } else { /* we have overflow of the count down timer */
+ /* nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo /= 1000; /* finish normalize. */
+ } else { /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+
+ endtime = get_timer_masked () + tmo;
+
+ do {
+ ulong now = get_timer_masked ();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return tbclk;
+}
bl do_fiq
#endif
-
-# ifdef CONFIG_INTEGRATOR
-
- /* Satisfied by Integrator routine (AP or CP) */
-
-#else
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
-_loop_forever:
- b _loop_forever
-
-rstctl1:
- .word 0xfffece10
-
-#endif /* #ifdef CONFIG_INTEGRATOR */
--- /dev/null
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(SOC).a
+
+OBJS = timer.o
+SOBJS = reset.o
+
+all: .depend $(LIB)
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+ ldr r1, rstctl1 /* get clkm1 reset ctl */
+ mov r3, #0x0
+ strh r3, [r1] /* clear it */
+ mov r3, #0x8
+ strh r3, [r1] /* force dsp+arm reset */
+_loop_forever:
+ b _loop_forever
+
+rstctl1:
+ .word 0xfffece10
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm926ejs.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+
+static ulong timestamp;
+static ulong lastdec;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init (void)
+{
+ *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */
+ *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */
+ *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo /= 1000; /* finish normalize. */
+ }else{ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+
+ tmp = get_timer (0); /* get current timestamp */
+ if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
+ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
+ else
+ tmo += tmp; /* else, set advancing stamp wake up time */
+
+ while (get_timer_masked () < tmo)/* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = READ_TIMER; /* capure current decrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+ ulong now = READ_TIMER; /* current tick value */
+
+ if (lastdec >= now) { /* normal mode (non roll) */
+ /* normal mode */
+ timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+ } else { /* we have overflow of the count down timer */
+ /* nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo /= 1000; /* finish normalize. */
+ } else { /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+
+ endtime = get_timer_masked () + tmo;
+
+ do {
+ ulong now = get_timer_masked ();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return tbclk;
+}
--- /dev/null
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
+OBJS = cpu.o traps.o ints.o serial.o interrupts.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * U-boot - bf533_serial.h Serial Driver defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
+ * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
+ *
+ * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
+ * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328serial.c which was:
+ * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _Bf533_SERIAL_H
+#define _Bf533_SERIAL_H
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+
+#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
+#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
+#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
+
+void serial_setbrg(void);
+static void local_put_char(char ch);
+void calc_baud(void);
+void serial_setbrg(void);
+int serial_init(void);
+void serial_putc(const char c);
+int serial_tstc(void);
+int serial_getc(void);
+void serial_puts(const char *s);
+static void local_put_char(char ch);
+
+extern int get_clock(void);
+int baud_table[5] = {9600, 19200, 38400, 57600, 115200};
+
+struct {
+ unsigned char dl_high;
+ unsigned char dl_low;
+} hw_baud_table[5];
+
+#ifdef CONFIG_STAMP
+extern unsigned long pll_div_fact;
+#endif
+
+#endif
--- /dev/null
+
+
+#define ASSEMBLY
+#include <asm/linkage.h>
+#include <asm/cpu/def_LPBlackfin.h>
+
+.text
+.align 2
+ENTRY(blackfin_icache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ IFLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ IFLUSH[P0];
+ SSYNC;
+ RTS;
+
+ENTRY(blackfin_dcache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ FLUSH[P0];
+ SSYNC;
+ RTS;
+
+ENTRY(_icache_invalidate)
+ENTRY(invalidate_entire_icache)
+ [--SP] = ( R7:5);
+
+ P0.L = (IMEM_CONTROL & 0xFFFF);
+ P0.H = (IMEM_CONTROL >> 16);
+ R7 = [P0];
+
+ /* Clear the IMC bit , All valid bits in the instruction
+ * cache are set to the invalid state
+ */
+ BITCLR(R7,IMC_P);
+ CLI R6;
+ SSYNC; /* SSYNC required before invalidating cache. */
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ /* Configures the instruction cache agian */
+ R6 = (IMC | ENICPLB);
+ R7 = R7 | R6;
+
+ CLI R6;
+ SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ ( R7:5) = [SP++];
+ RTS;
+
+/* Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(invalidate_entire_dcache)
+ENTRY(_dcache_invalidate)
+ [--SP] = ( R7:6);
+
+ P0.L = (DMEM_CONTROL & 0xFFFF);
+ P0.H = (DMEM_CONTROL >> 16);
+ R7 = [P0];
+
+ /* Clear the DMC[1:0] bits, All valid bits in the data
+ * cache are set to the invalid state
+ */
+ BITCLR(R7,DMC0_P);
+ BITCLR(R7,DMC1_P);
+ CLI R6;
+ SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ /* Configures the data cache again */
+
+ R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+ R7 = R7 | R6;
+
+ CLI R6;
+ SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ ( R7:6) = [SP++];
+ RTS;
+
+ENTRY(blackfin_dcache_invalidate_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSHINV[P0++];
+ CC = P0 < P1 (iu);
+ IF CC JUMP 1b (bp);
+
+ /* If the data crosses a cache line, then we'll be pointing to
+ ** the last cache line, but won't have flushed/invalidated it yet, so do
+ ** one more.
+ */
+ FLUSHINV[P0];
+ SSYNC;
+ RTS;
--- /dev/null
+# U-boot - config.mk
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-P5
--- /dev/null
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ */
+
+
+/* Include an exception handler to invoke the CPLB manager
+ */
+
+#include <asm-blackfin/linkage.h>
+#include <asm/cplb.h>
+#include <asm/entry.h>
+
+
+.text
+
+.globl _cplb_hdr;
+.type _cplb_hdr, STT_FUNC;
+.extern _cplb_mgr;
+.type _cplb_mgr, STT_FUNC;
+.extern __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+.extern __cplb_miss_all_locked;
+.type __cplb_miss_all_locked, STT_FUNC;
+.extern __cplb_miss_without_replacement;
+.type __cplb_miss_without_replacement, STT_FUNC;
+.extern __cplb_protection_violation;
+.type __cplb_protection_violation, STT_FUNC;
+.extern panic_pv;
+
+.align 2;
+
+ENTRY(_cplb_hdr)
+ SSYNC;
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = ASTAT;
+ [--SP] = SEQSTAT;
+ [--SP] = I0;
+ [--SP] = I1;
+ [--SP] = I2;
+ [--SP] = I3;
+ [--SP] = LT0;
+ [--SP] = LB0;
+ [--SP] = LC0;
+ [--SP] = LT1;
+ [--SP] = LB1;
+ [--SP] = LC1;
+ R2 = SEQSTAT;
+
+ /*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/
+ R2 <<= 26;
+ R2 >>= 26;
+
+ R1 = 0x23; /* Data access CPLB protection violation */
+ CC = R2 == R1;
+ IF !CC JUMP not_data_write;
+ R0 = 2; /* is a write to data space*/
+ JUMP is_icplb_miss;
+
+not_data_write:
+ R1 = 0x2C; /* CPLB miss on an instruction fetch */
+ CC = R2 == R1;
+ R0 = 0; /* is_data_miss == False*/
+ IF CC JUMP is_icplb_miss;
+
+ R1 = 0x26;
+ CC = R2 == R1;
+ IF !CC JUMP unknown;
+
+ R0 = 1; /* is_data_miss == True*/
+
+is_icplb_miss:
+
+#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
+#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
+ R1 = CPLB_ENABLE_ICACHE;
+#endif
+#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+ R1 = CPLB_ENABLE_DCACHE;
+#endif
+#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+ R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
+#endif
+#else
+ R1 = 0;
+#endif
+
+ [--SP] = RETS;
+ CALL _cplb_mgr;
+ RETS = [SP++];
+ CC = R0 == 0;
+ IF !CC JUMP not_replaced;
+ LC1 = [SP++];
+ LB1 = [SP++];
+ LT1 = [SP++];
+ LC0 = [SP++];
+ LB0 = [SP++];
+ LT0 = [SP++];
+ I3 = [SP++];
+ I2 = [SP++];
+ I1 = [SP++];
+ I0 = [SP++];
+ SEQSTAT = [SP++];
+ ASTAT = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+
+unknown:
+ [--SP] = RETS;
+ CALL __unknown_exception_occurred;
+ RETS = [SP++];
+ JUMP unknown;
+not_replaced:
+ CC = R0 == CPLB_NO_UNLOCKED;
+ IF !CC JUMP next_check;
+ [--SP] = RETS;
+ CALL __cplb_miss_all_locked;
+ RETS = [SP++];
+next_check:
+ CC = R0 == CPLB_NO_ADDR_MATCH;
+ IF !CC JUMP next_check2;
+ [--SP] = RETS;
+ CALL __cplb_miss_without_replacement;
+ RETS = [SP++];
+ JUMP not_replaced;
+next_check2:
+ CC = R0 == CPLB_PROT_VIOL;
+ IF !CC JUMP strange_return_from_cplb_mgr;
+ [--SP] = RETS;
+ CALL __cplb_protection_violation;
+ RETS = [SP++];
+ JUMP not_replaced;
+strange_return_from_cplb_mgr:
+ IDLE;
+ CSYNC;
+ JUMP strange_return_from_cplb_mgr;
+
+/************************************
+ * Diagnostic exception handlers
+ */
+
+__cplb_miss_all_locked:
+ sp += -12;
+ R0 = CPLB_NO_UNLOCKED;
+ call panic_bfin;
+ SP += 12;
+ RTS;
+
+ __cplb_miss_without_replacement:
+ sp += -12;
+ R0 = CPLB_NO_ADDR_MATCH;
+ call panic_bfin;
+ SP += 12;
+ RTS;
+
+__cplb_protection_violation:
+ sp += -12;
+ R0 = CPLB_PROT_VIOL;
+ call panic_bfin;
+ SP += 12;
+ RTS;
+
+__unknown_exception_occurred:
+
+ /* This function is invoked by the default exception
+ * handler, if it does not recognise the kind of
+ * exception that has occurred. In other words, the
+ * default handler only handles some of the system's
+ * exception types, and it does not expect any others
+ * to occur. If your application is going to be using
+ * other kinds of exceptions, you must replace the
+ * default handler with your own, that handles all the
+ * exceptions you will use.
+ *
+ * Since there's nothing we can do, we just loop here
+ * at what we hope is a suitably informative label.
+ */
+
+ IDLE;
+do_not_know_what_to_do:
+ CSYNC;
+ JUMP __unknown_exception_occurred;
+
+ RTS;
+.__unknown_exception_occurred.end:
+.global __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+
+panic_bfin:
+ RTS;
--- /dev/null
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Modification: Dec 07 2004
+ * 1. Correction in icheck_lock. Valid lock entries were
+ * geting victimized, for instruction cplb replacement.
+ * 2. Setup loop's are modified as now toolchain support's P Indexed
+ * addressing
+ * :LG Soft India
+ *
+ */
+
+/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
+ * is_data_miss==2 => Mark as Dirty, write to the clean data page
+ * is_data_miss==1 => Replace a data CPLB.
+ * is_data_miss==0 => Replace an instruction CPLB.
+ *
+ * Returns:
+ * CPLB_RELOADED => Successfully updated CPLB table.
+ * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates
+ * that the CPLBs in the configuration tablei are badly
+ * configured, as this should never occur.
+ * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception,
+ * is not covered by any of the CPLBs in the configuration
+ * table. The application isi presumably misbehaving.
+ * CPLB_PROT_VIOL => The address being accessed, that triggered thei exception,
+ * was not a first-write to a clean Write Back Data page,
+ * and so presumably is a genuine violation of the page's
+ * protection attributes. The application is misbehaving.
+ */
+#define ASSEMBLY
+
+#include <asm-blackfin/linkage.h>
+#include <asm-blackfin/blackfin.h>
+#include <asm-blackfin/cplbtab.h>
+#include <asm-blackfin/cplb.h>
+
+.text
+
+.align 2;
+ENTRY(_cplb_mgr)
+
+ [--SP]=( R7:0,P5:0 );
+
+ CC = R0 == 2;
+ IF CC JUMP dcplb_write;
+
+ CC = R0 == 0;
+ IF !CC JUMP dcplb_miss_compare;
+
+ /* ICPLB Miss Exception. We need to choose one of the
+ * currently-installed CPLBs, and replace it with one
+ * from the configuration table.
+ */
+
+ P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
+ P4.H = (ICPLB_FAULT_ADDR >> 16);
+
+ P1 = 16;
+ P5.L = page_size_table;
+ P5.H = page_size_table;
+
+ P0.L = (ICPLB_DATA0 & 0xFFFF);
+ P0.H = (ICPLB_DATA0 >> 16);
+ R4 = [P4]; /* Get faulting address*/
+ R6 = 64; /* Advance past the fault address, which*/
+ R6 = R6 + R4; /* we'll use if we find a match*/
+ R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/
+
+ R5 = 0;
+isearch:
+
+ R1 = [P0-0x100]; /* Address for this CPLB */
+
+ R0 = [P0++]; /* Info for this CPLB*/
+ CC = BITTST(R0,0); /* Is the CPLB valid?*/
+ IF !CC JUMP nomatch; /* Skip it, if not.*/
+ CC = R4 < R1(IU); /* If fault address less than page start*/
+ IF CC JUMP nomatch; /* then skip this one.*/
+ R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
+ P1 = R2;
+ P1 = P5 + (P1<<2); /* index into page-size table*/
+ R2 = [P1]; /* Get the page size*/
+ R1 = R1 + R2; /* and add to page start, to get page end*/
+ CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
+ IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
+ IF !CC JUMP isearch_done;
+nomatch:
+ /* Go around again*/
+ R5 += 1;
+ CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
+ IF !CC JUMP isearch;
+
+isearch_done:
+ I0 = R4; /* Fault address we'll search for*/
+
+ /* set up pointers */
+ P0.L = (ICPLB_DATA0 & 0xFFFF);
+ P0.H = (ICPLB_DATA0 >> 16);
+
+ /* The replacement procedure for ICPLBs */
+
+ P4.L = (IMEM_CONTROL & 0xFFFF);
+ P4.H = (IMEM_CONTROL >> 16);
+
+ /* disable cplbs */
+ R5 = [P4]; /* Control Register*/
+ BITCLR(R5,ENICPLB_P);
+ CLI R1;
+ SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
+ .align 8;
+ [P4] = R5;
+ SSYNC;
+ STI R1;
+
+ R1 = -1; /* end point comparison */
+ R3 = 16; /* counter */
+
+ /* Search through CPLBs for first non-locked entry */
+ /* Overwrite it by moving everyone else up by 1 */
+icheck_lock:
+ R0 = [P0++];
+ R3 = R3 + R1;
+ CC = R3 == R1;
+ IF CC JUMP all_locked;
+ CC = BITTST(R0, 0); /* an invalid entry is good */
+ IF !CC JUMP ifound_victim;
+ CC = BITTST(R0,1); /* but a locked entry isn't */
+ IF CC JUMP icheck_lock;
+
+ifound_victim:
+#ifdef CONFIG_CPLB_INFO
+ R7 = [P0 - 0x104];
+ P2.L = ipdt_table;
+ P2.H = ipdt_table;
+ P3.L = ipdt_swapcount_table;
+ P3.H = ipdt_swapcount_table;
+ P3 += -4;
+icount:
+ R2 = [P2]; /* address from config table */
+ P2 += 8;
+ P3 += 8;
+ CC = R2==-1;
+ IF CC JUMP icount_done;
+ CC = R7==R2;
+ IF !CC JUMP icount;
+ R7 = [P3];
+ R7 += 1;
+ [P3] = R7;
+ CSYNC;
+icount_done:
+#endif
+ LC0=R3;
+ LSETUP(is_move,ie_move) LC0;
+is_move:
+ R0 = [P0];
+ [P0 - 4] = R0;
+ R0 = [P0 - 0x100];
+ [P0-0x104] = R0;
+ie_move:P0+=4;
+
+ /* We've made space in the ICPLB table, so that ICPLB15
+ * is now free to be overwritten. Next, we have to determine
+ * which CPLB we need to install, from the configuration
+ * table. This is a matter of getting the start-of-page
+ * addresses and page-lengths from the config table, and
+ * determining whether the fault address falls within that
+ * range.
+ */
+
+ P2.L = ipdt_table;
+ P2.H = ipdt_table;
+#ifdef CONFIG_CPLB_INFO
+ P3.L = ipdt_swapcount_table;
+ P3.H = ipdt_swapcount_table;
+ P3 += -8;
+#endif
+ P0.L = page_size_table;
+ P0.H = page_size_table;
+
+ /* Retrieve our fault address (which may have been advanced
+ * because the faulting instruction crossed a page boundary).
+ */
+
+ R0 = I0;
+
+ /* An extraction pattern, to get the page-size bits from
+ * the CPLB data entry. Bits 16-17, so two bits at posn 16.
+ */
+
+ R1 = ((16<<8)|2);
+inext: R4 = [P2++]; /* address from config table */
+ R2 = [P2++]; /* data from config table */
+#ifdef CONFIG_CPLB_INFO
+ P3 += 8;
+#endif
+
+ CC = R4 == -1; /* End of config table*/
+ IF CC JUMP no_page_in_table;
+
+ /* See if failed address > start address */
+ CC = R4 <= R0(IU);
+ IF !CC JUMP inext;
+
+ /* extract page size (17:16)*/
+ R3 = EXTRACT(R2, R1.L) (Z);
+
+ /* add page size to addr to get range */
+
+ P5 = R3;
+ P5 = P0 + (P5 << 2); /* scaled, for int access*/
+ R3 = [P5];
+ R3 = R3 + R4;
+
+ /* See if failed address < (start address + page size) */
+ CC = R0 < R3(IU);
+ IF !CC JUMP inext;
+
+ /* We've found a CPLB in the config table that covers
+ * the faulting address, so install this CPLB into the
+ * last entry of the table.
+ */
+
+ P1.L = (ICPLB_DATA15 & 0xFFFF); /*ICPLB_DATA15*/
+ P1.H = (ICPLB_DATA15 >> 16);
+ [P1] = R2;
+ [P1-0x100] = R4;
+#ifdef CONFIG_CPLB_INFO
+ R3 = [P3];
+ R3 += 1;
+ [P3] = R3;
+#endif
+
+ /* P4 points to IMEM_CONTROL, and R5 contains its old
+ * value, after we disabled ICPLBS. Re-enable them.
+ */
+
+ BITSET(R5,ENICPLB_P);
+ CLI R2;
+ SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
+ .align 8;
+ [P4] = R5;
+ SSYNC;
+ STI R2;
+
+ ( R7:0,P5:0 ) = [SP++];
+ R0 = CPLB_RELOADED;
+ RTS;
+
+/* FAILED CASES*/
+no_page_in_table:
+ ( R7:0,P5:0 ) = [SP++];
+ R0 = CPLB_NO_ADDR_MATCH;
+ RTS;
+all_locked:
+ ( R7:0,P5:0 ) = [SP++];
+ R0 = CPLB_NO_UNLOCKED;
+ RTS;
+prot_violation:
+ ( R7:0,P5:0 ) = [SP++];
+ R0 = CPLB_PROT_VIOL;
+ RTS;
+
+dcplb_write:
+
+ /* if a DCPLB is marked as write-back (CPLB_WT==0), and
+ * it is clean (CPLB_DIRTY==0), then a write to the
+ * CPLB's page triggers a protection violation. We have to
+ * mark the CPLB as dirty, to indicate that there are
+ * pending writes associated with the CPLB.
+ */
+
+ P4.L = (DCPLB_STATUS & 0xFFFF);
+ P4.H = (DCPLB_STATUS >> 16);
+ P3.L = (DCPLB_DATA0 & 0xFFFF);
+ P3.H = (DCPLB_DATA0 >> 16);
+ R5 = [P4];
+
+ /* A protection violation can be caused by more than just writes
+ * to a clean WB page, so we have to ensure that:
+ * - It's a write
+ * - to a clean WB page
+ * - and is allowed in the mode the access occurred.
+ */
+
+ CC = BITTST(R5, 16); /* ensure it was a write*/
+ IF !CC JUMP prot_violation;
+
+ /* to check the rest, we have to retrieve the DCPLB.*/
+
+ /* The low half of DCPLB_STATUS is a bit mask*/
+
+ R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
+ R3 = 30; /* so we can use this to determine the offset*/
+ R2.L = SIGNBITS R2;
+ R2 = R2.L (Z); /* into the DCPLB table.*/
+ R3 = R3 - R2;
+ P4 = R3;
+ P3 = P3 + (P4<<2);
+ R3 = [P3]; /* Retrieve the CPLB*/
+
+ /* Now we can check whether it's a clean WB page*/
+
+ CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
+ IF CC JUMP prot_violation;
+ CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
+ IF CC JUMP prot_violation;
+
+ /* Check whether the write is allowed in the mode that was active.*/
+
+ R2 = 1<<3; /* checking write in user mode*/
+ CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
+ R5 = CC;
+ R2 <<= R5; /* if was super, check write in super mode*/
+ R2 = R3 & R2;
+ CC = R2 == 0;
+ IF CC JUMP prot_violation;
+
+ /* It's a genuine write-to-clean-page.*/
+
+ BITSET(R3, 7); /* mark as dirty*/
+ [P3] = R3; /* and write back.*/
+ CSYNC;
+ ( R7:0,P5:0 ) = [SP++];
+ R0 = CPLB_RELOADED;
+ RTS;
+
+dcplb_miss_compare:
+
+ /* Data CPLB Miss event. We need to choose a CPLB to
+ * evict, and then locate a new CPLB to install from the
+ * config table, that covers the faulting address.
+ */
+
+ P1.L = (DCPLB_DATA15 & 0xFFFF);
+ P1.H = (DCPLB_DATA15 >> 16);
+
+ P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
+ P4.H = (DCPLB_FAULT_ADDR >> 16);
+ R4 = [P4];
+ I0 = R4;
+
+ /* The replacement procedure for DCPLBs*/
+
+ R6 = R1; /* Save for later*/
+
+ /* Turn off CPLBs while we work.*/
+ P4.L = (DMEM_CONTROL & 0xFFFF);
+ P4.H = (DMEM_CONTROL >> 16);
+ R5 = [P4];
+ BITCLR(R5,ENDCPLB_P);
+ CLI R0;
+ SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
+ .align 8;
+ [P4] = R5;
+ SSYNC;
+ STI R0;
+
+ /* Start looking for a CPLB to evict. Our order of preference
+ * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
+ * are no good.
+ */
+
+ I1.L = (DCPLB_DATA0 & 0xFFFF);
+ I1.H = (DCPLB_DATA0 >> 16);
+ P1 = 3;
+ P2 = 16;
+ I2.L = dcplb_preference;
+ I2.H = dcplb_preference;
+ LSETUP(sdsearch1, edsearch1) LC0 = P1;
+sdsearch1:
+ R0 = [I2++]; /* Get the bits we're interested in*/
+ P0 = I1; /* Go back to start of table*/
+ LSETUP (sdsearch2, edsearch2) LC1 = P2;
+sdsearch2:
+ R1 = [P0++]; /* Fetch each installed CPLB in turn*/
+ R2 = R1 & R0; /* and test for interesting bits.*/
+ CC = R2 == 0; /* If none are set, it'll do.*/
+ IF !CC JUMP skip_stack_check;
+
+ R2 = [P0 - 0x104]; /* R2 - PageStart */
+ P3.L = page_size_table; /* retrive end address */
+ P3.H = page_size_table; /* retrive end address */
+ R3 = 0x2; /* 0th - position, 2 bits -length */
+ nop; /*Anamoly 05000209*/
+ R7 = EXTRACT(R1,R3.l);
+ R7 = R7 << 2; /* Page size index offset */
+ P5 = R7;
+ P3 = P3 + P5;
+ R7 = [P3]; /* page size in 1K bytes */
+
+ R7 = R7 << 0xA; /* in bytes * 1024*/
+ R7 = R2 + R7; /* R7 - PageEnd */
+ R4 = SP; /* Test SP is in range */
+
+ CC = R7 < R4; /* if PageEnd < SP */
+ IF CC JUMP dfound_victim;
+ R3 = 0x284; /* stack length from start of trap till the point */
+ /* 20 stack locations for future modifications */
+ R4 = R4 + R3;
+ CC = R4 < R2; /* if SP + stacklen < PageStart */
+ IF CC JUMP dfound_victim;
+skip_stack_check:
+
+edsearch2: NOP;
+edsearch1: NOP;
+
+ /* If we got here, we didn't find a DCPLB we considered
+ * replacable, which means all of them were locked.
+ */
+
+ JUMP all_locked;
+dfound_victim:
+
+#ifdef CONFIG_CPLB_INFO
+ R1 = [P0 - 0x104];
+ P2.L = dpdt_table;
+ P2.H = dpdt_table;
+ P3.L = dpdt_swapcount_table;
+ P3.H = dpdt_swapcount_table;
+ P3 += -4;
+dicount:
+ R2 = [P2];
+ P2 += 8;
+ P3 += 8;
+ CC = R2==-1;
+ IF CC JUMP dicount_done;
+ CC = R1==R2;
+ IF !CC JUMP dicount;
+ R1 = [P3];
+ R1 += 1;
+ [P3] = R1;
+ CSYNC;
+dicount_done:
+#endif
+
+ /* Clean down the hardware loops*/
+ R2 = 0;
+ LC1 = R2;
+ LC0 = R2;
+
+ /* There's a suitable victim in [P0-4] (because we've
+ * advanced already). If it's a valid dirty write-back
+ * CPLB, we need to flush the pending writes first.
+ */
+
+ CC = BITTST(R1, 0); /* Is it valid?*/
+ IF !CC JUMP Ddoverwrite;/* nope.*/
+ CC = BITTST(R1, 7); /* Is it dirty?*/
+ IF !CC JUMP Ddoverwrite (BP); /* Nope.*/
+ CC = BITTST(R1, 14); /* Is it Write-Through?*/
+ IF CC JUMP Ddoverwrite; /* Yep*/
+
+ /* This is a dirty page, so we need to flush all writes
+ * that are pending on the page.
+ */
+
+ /* Retrieve the page start address*/
+ R0 = [P0 - 0x104];
+ [--sp] = rets;
+ CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/
+ rets = [sp++];
+Ddoverwrite:
+
+ /* [P0-4] is a suitable victim CPLB, so we want to
+ * overwrite it by moving all the following CPLBs
+ * one space closer to the start.
+ */
+
+ R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/
+ R1.H = ((DCPLB_DATA15+4) >> 16);
+ R0 = P0;
+
+ /* If the victim happens to be in DCPLB15,
+ * we don't need to move anything.
+ */
+
+ CC = R1 == R0;
+ IF CC JUMP de_moved;
+ R1 = R1 - R0;
+ R1 >>= 2;
+ P1 = R1;
+ LSETUP(ds_move, de_move) LC0=P1;
+ds_move:
+ R0 = [P0++]; /* move data */
+ [P0 - 8] = R0;
+ R0 = [P0-0x104] /* move address */
+de_move: [P0-0x108] = R0;
+
+ /* We've now made space in DCPLB15 for the new CPLB to be
+ * installed. The next stage is to locate a CPLB in the
+ * config table that covers the faulting address.
+ */
+
+de_moved:NOP;
+ R0 = I0; /* Our faulting address */
+
+ P2.L = dpdt_table;
+ P2.H = dpdt_table;
+#ifdef CONFIG_CPLB_INFO
+ P3.L = dpdt_swapcount_table;
+ P3.H = dpdt_swapcount_table;
+ P3 += -8;
+#endif
+
+ P1.L = page_size_table;
+ P1.H = page_size_table;
+
+ /* An extraction pattern, to retrieve bits 17:16.*/
+
+ R1 = (16<<8)|2;
+dnext: R4 = [P2++]; /* address */
+ R2 = [P2++]; /* data */
+#ifdef CONFIG_CPLB_INFO
+ P3 += 8;
+#endif
+
+ CC = R4 == -1;
+ IF CC JUMP no_page_in_table;
+
+ /* See if failed address > start address */
+ CC = R4 <= R0(IU);
+ IF !CC JUMP dnext;
+
+ /* extract page size (17:16)*/
+ R3 = EXTRACT(R2, R1.L) (Z);
+
+ /* add page size to addr to get range */
+
+ P5 = R3;
+ P5 = P1 + (P5 << 2);
+ R3 = [P5];
+ R3 = R3 + R4;
+
+ /* See if failed address < (start address + page size) */
+ CC = R0 < R3(IU);
+ IF !CC JUMP dnext;
+
+ /* We've found the CPLB that should be installed, so
+ * write it into CPLB15, masking off any caching bits
+ * if necessary.
+ */
+
+ P1.L = (DCPLB_DATA15 & 0xFFFF);
+ P1.H = (DCPLB_DATA15 >> 16);
+
+ /* If the DCPLB has cache bits set, but caching hasn't
+ * been enabled, then we want to mask off the cache-in-L1
+ * bit before installing. Moreover, if caching is off, we
+ * also want to ensure that the DCPLB has WT mode set, rather
+ * than WB, since WB pages still trigger first-write exceptions
+ * even when not caching is off, and the page isn't marked as
+ * cachable. Finally, we could mark the page as clean, not dirty,
+ * but we choose to leave that decision to the user; if the user
+ * chooses to have a CPLB pre-defined as dirty, then they always
+ * pay the cost of flushing during eviction, but don't pay the
+ * cost of first-write exceptions to mark the page as dirty.
+ */
+
+#ifdef CONFIG_BLKFIN_WT
+ BITSET(R6, 14); /* Set WT*/
+#endif
+
+ [P1] = R2;
+ [P1-0x100] = R4;
+#ifdef CONFIG_CPLB_INFO
+ R3 = [P3];
+ R3 += 1;
+ [P3] = R3;
+#endif
+
+ /* We've installed the CPLB, so re-enable CPLBs. P4
+ * points to DMEM_CONTROL, and R5 is the value we
+ * last wrote to it, when we were disabling CPLBs.
+ */
+
+ BITSET(R5,ENDCPLB_P);
+ CLI R2;
+ .align 8;
+ [P4] = R5;
+ SSYNC;
+ STI R2;
+
+ ( R7:0,P5:0 ) = [SP++];
+ R0 = CPLB_RELOADED;
+ RTS;
+
+.data
+.align 4;
+page_size_table:
+.byte4 0x00000400; /* 1K */
+.byte4 0x00001000; /* 4K */
+.byte4 0x00100000; /* 1M */
+.byte4 0x00400000; /* 4M */
+
+.align 4;
+dcplb_preference:
+.byte4 0x00000001; /* valid bit */
+.byte4 0x00000082; /* dirty+lock bits */
+.byte4 0x00000002; /* lock bit */
--- /dev/null
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <command.h>
+#include <asm/entry.h>
+
+#define SSYNC() asm("ssync;")
+#define CACHE_ON 1
+#define CACHE_OFF 0
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+#define ANOMALY_05000158 0x200
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+static unsigned int icplb_table[16][2]={
+ {0xFFA00000, L1_IMEMORY},
+ {0x00000000, SDRAM_IKERNEL}, /*SDRAM_Page1*/
+ {0x00400000, SDRAM_IKERNEL}, /*SDRAM_Page1*/
+ {0x07C00000, SDRAM_IKERNEL}, /*SDRAM_Page14*/
+ {0x00800000, SDRAM_IGENERIC}, /*SDRAM_Page2*/
+ {0x00C00000, SDRAM_IGENERIC}, /*SDRAM_Page2*/
+ {0x01000000, SDRAM_IGENERIC}, /*SDRAM_Page4*/
+ {0x01400000, SDRAM_IGENERIC}, /*SDRAM_Page5*/
+ {0x01800000, SDRAM_IGENERIC}, /*SDRAM_Page6*/
+ {0x01C00000, SDRAM_IGENERIC}, /*SDRAM_Page7*/
+ {0x02000000, SDRAM_IGENERIC}, /*SDRAM_Page8*/
+ {0x02400000, SDRAM_IGENERIC}, /*SDRAM_Page9*/
+ {0x02800000, SDRAM_IGENERIC}, /*SDRAM_Page10*/
+ {0x02C00000, SDRAM_IGENERIC}, /*SDRAM_Page11*/
+ {0x03000000, SDRAM_IGENERIC}, /*SDRAM_Page12*/
+ {0x03400000, SDRAM_IGENERIC}, /*SDRAM_Page13*/
+};
+
+static unsigned int dcplb_table[16][2]={
+ {0xFFA00000,L1_DMEMORY},
+ {0x00000000,SDRAM_DKERNEL}, /*SDRAM_Page1*/
+ {0x00400000,SDRAM_DKERNEL}, /*SDRAM_Page1*/
+ {0x07C00000,SDRAM_DKERNEL}, /*SDRAM_Page15*/
+ {0x00800000,SDRAM_DGENERIC}, /*SDRAM_Page2*/
+ {0x00C00000,SDRAM_DGENERIC}, /*SDRAM_Page3*/
+ {0x01000000,SDRAM_DGENERIC}, /*SDRAM_Page4*/
+ {0x01400000,SDRAM_DGENERIC}, /*SDRAM_Page5*/
+ {0x01800000,SDRAM_DGENERIC}, /*SDRAM_Page6*/
+ {0x01C00000,SDRAM_DGENERIC}, /*SDRAM_Page7*/
+ {0x02000000,SDRAM_DGENERIC}, /*SDRAM_Page8*/
+ {0x02400000,SDRAM_DGENERIC}, /*SDRAM_Page9*/
+ {0x02800000,SDRAM_DGENERIC}, /*SDRAM_Page10*/
+ {0x02C00000,SDRAM_DGENERIC}, /*SDRAM_Page11*/
+ {0x03000000,SDRAM_DGENERIC}, /*SDRAM_Page12*/
+ {0x20000000,SDRAM_EBIU}, /*For Network */
+};
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ __asm__ __volatile__
+ ("cli r3;"
+ "P0 = %0;"
+ "JUMP (P0);"
+ :
+ : "r" (L1_ISRAM)
+ );
+
+ return 0;
+}
+
+/* These functions are just used to satisfy the linker */
+int cpu_init(void)
+{
+ return 0;
+}
+
+int cleanup_before_linux(void)
+{
+ return 0;
+}
+
+void icache_enable(void)
+{
+ unsigned int *I0,*I1;
+ int i;
+
+ I0 = (unsigned int *)ICPLB_ADDR0;
+ I1 = (unsigned int *)ICPLB_DATA0;
+
+ for(i=0;i<16;i++){
+ *I0++ = icplb_table[i][0];
+ *I1++ = icplb_table[i][1];
+ }
+ cli();
+ SSYNC();
+ *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+ SSYNC();
+ sti();
+}
+
+void icache_disable(void)
+{
+ cli();
+ SSYNC();
+ *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+ SSYNC();
+ sti();
+}
+
+int icache_status(void)
+{
+ unsigned int value;
+ value = *(unsigned int *)IMEM_CONTROL;
+
+ if( value & (IMC|ENICPLB) )
+ return CACHE_ON;
+ else
+ return CACHE_OFF;
+}
+
+void dcache_enable(void)
+{
+ unsigned int *I0,*I1;
+ unsigned int temp;
+ int i;
+ I0 = (unsigned int *)DCPLB_ADDR0;
+ I1 = (unsigned int *)DCPLB_DATA0;
+
+ for(i=0;i<16;i++){
+ *I0++ = dcplb_table[i][0];
+ *I1++ = dcplb_table[i][1];
+ }
+ cli();
+ temp = *(unsigned int *)DMEM_CONTROL;
+ SSYNC();
+ *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
+ SSYNC();
+ sti();
+}
+
+void dcache_disable(void)
+{
+ cli();
+ SSYNC();
+ *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
+ SSYNC();
+ sti();
+}
+
+int dcache_status(void)
+{
+ unsigned int value;
+ value = *(unsigned int *)DMEM_CONTROL;
+ if( value & (ENDCPLB))
+ return CACHE_ON;
+ else
+ return CACHE_OFF;
+}
--- /dev/null
+/*
+ * U-boot - cpu.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+#define INTERNAL_IRQS (32)
+#define NUM_IRQ_NODES 16
+#define DEF_INTERRUPT_FLAGS 1
+#define MAX_TIM_LOAD 0xFFFFFFFF
+
+void blackfin_irq_panic(int reason, struct pt_regs * reg);
+extern void dump(struct pt_regs * regs);
+void display_excp(void);
+asmlinkage void evt_nmi(void);
+asmlinkage void evt_exception(void);
+asmlinkage void trap(void);
+asmlinkage void evt_ivhw(void);
+asmlinkage void evt_rst(void);
+asmlinkage void evt_timer(void);
+asmlinkage void evt_evt7(void);
+asmlinkage void evt_evt8(void);
+asmlinkage void evt_evt9(void);
+asmlinkage void evt_evt10(void);
+asmlinkage void evt_evt11(void);
+asmlinkage void evt_evt12(void);
+asmlinkage void evt_evt13(void);
+asmlinkage void evt_soft_int1(void);
+asmlinkage void evt_system_call(void);
+void blackfin_irq_panic(int reason, struct pt_regs * regs);
+void blackfin_free_irq(unsigned int irq, void *dev_id);
+void call_isr(int irq, struct pt_regs * fp);
+void blackfin_do_irq(int vec, struct pt_regs *fp);
+void blackfin_init_IRQ(void);
+void blackfin_enable_irq(unsigned int irq);
+void blackfin_disable_irq(unsigned int irq);
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int blackfin_request_irq(unsigned int irq,
+ void (*handler)(int, void *, struct pt_regs *),
+ unsigned long flags,const char *devname,void *dev_id);
+void timer_init(void);
+#endif
--- /dev/null
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2004 LG SOft India. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ */
+#define ASSEMBLY
+
+#include <asm/linkage.h>
+#include <asm/cplb.h>
+#include <asm/blackfin.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the instruction cache.
+ */
+
+ENTRY(flush_instruction_cache)
+ [--SP] = ( R7:6, P5:4 );
+ LINK 12;
+ SP += -12;
+ P5.H = (ICPLB_ADDR0 >> 16);
+ P5.L = (ICPLB_ADDR0 & 0xFFFF);
+ P4.H = (ICPLB_DATA0 >> 16);
+ P4.L = (ICPLB_DATA0 & 0xFFFF);
+ R7 = CPLB_VALID | CPLB_L1_CHBL;
+ R6 = 16;
+inext: R0 = [P5++];
+ R1 = [P4++];
+ [--SP] = RETS;
+ CALL icplb_flush; /* R0 = page, R1 = data*/
+ RETS = [SP++];
+iskip: R6 += -1;
+ CC = R6;
+ IF CC JUMP inext;
+ SSYNC;
+ SP += 12;
+ UNLINK;
+ ( R7:6, P5:4 ) = [SP++];
+ RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular ICPLB.
+ *
+ * R0 - page's start address
+ * R1 - CPLB's data field.
+ */
+
+.align 2
+ENTRY(icplb_flush)
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = LC0;
+ [--SP] = LT0;
+ [--SP] = LB0;
+ [--SP] = LC1;
+ [--SP] = LT1;
+ [--SP] = LB1;
+
+ /* If it's a 1K or 4K page, then it's quickest to
+ * just systematically flush all the addresses in
+ * the page, regardless of whether they're in the
+ * cache, or dirty. If it's a 1M or 4M page, there
+ * are too many addresses, and we have to search the
+ * cache for lines corresponding to the page.
+ */
+
+ CC = BITTST(R1, 17); /* 1MB or 4MB */
+ IF !CC JUMP iflush_whole_page;
+
+ /* We're only interested in the page's size, so extract
+ * this from the CPLB (bits 17:16), and scale to give an
+ * offset into the page_size and page_prefix tables.
+ */
+
+ R1 <<= 14;
+ R1 >>= 30;
+ R1 <<= 2;
+
+ /* We can also determine the sub-bank used, because this is
+ * taken from bits 13:12 of the address.
+ */
+
+ R3 = ((12<<8)|2); /* Extraction pattern */
+ nop; /*Anamoly 05000209*/
+ R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
+ R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
+
+
+ /* So:
+ * R0 = Page start
+ * R1 = Page length (actually, offset into size/prefix tables)
+ * R3 = sub-bank deposit values
+ *
+ * The cache has 2 Ways, and 64 sets, so we iterate through
+ * the sets, accessing the tag for each Way, for our Bank and
+ * sub-bank, looking for dirty, valid tags that match our
+ * address prefix.
+ */
+
+ P5.L = (ITEST_COMMAND & 0xFFFF);
+ P5.H = (ITEST_COMMAND >> 16);
+ P4.L = (ITEST_DATA0 & 0xFFFF);
+ P4.H = (ITEST_DATA0 >> 16);
+
+ P0.L = page_prefix_table;
+ P0.H = page_prefix_table;
+ P1 = R1;
+ R5 = 0; /* Set counter*/
+ P0 = P1 + P0;
+ R4 = [P0]; /* This is the address prefix*/
+
+ /* We're reading (bit 1==0) the tag (bit 2==0), and we
+ * don't care about which double-word, since we're only
+ * fetching tags, so we only have to set Set, Bank,
+ * Sub-bank and Way.
+ */
+
+ P2 = 4;
+ LSETUP (ifs1, ife1) LC1 = P2;
+ifs1: P0 = 32; /* iterate over all sets*/
+ LSETUP (ifs0, ife0) LC0 = P0;
+ifs0: R6 = R5 << 5; /* Combine set*/
+ R6.H = R3.H << 0 ; /* and sub-bank*/
+ [P5] = R6; /* Issue Command*/
+ SSYNC; /* CSYNC will not work here :(*/
+ R7 = [P4]; /* and read Tag.*/
+ CC = BITTST(R7, 0); /* Check if valid*/
+ IF !CC JUMP ifskip; /* and skip if not.*/
+
+ /* Compare against the page address. First, plant bits 13:12
+ * into the tag, since those aren't part of the returned data.
+ */
+
+ R7 = DEPOSIT(R7, R3); /* set 13:12*/
+ R1 = R7 & R4; /* Mask off lower bits*/
+ CC = R1 == R0; /* Compare against page start.*/
+ IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
+
+ /* Tag address matches against page, so this is an entry
+ * we must flush.
+ */
+
+ R7 >>= 10; /* Mask off the non-address bits*/
+ R7 <<= 10;
+ P3 = R7;
+ IFLUSH [P3]; /* And flush the entry*/
+ifskip:
+ife0: R5 += 1; /* Advance to next Set*/
+ife1: NOP;
+
+ifinished:
+ SSYNC; /* Ensure the data gets out to mem.*/
+
+ /*Finished. Restore context.*/
+ LB1 = [SP++];
+ LT1 = [SP++];
+ LC1 = [SP++];
+ LB0 = [SP++];
+ LT0 = [SP++];
+ LC0 = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+
+iflush_whole_page:
+ /* It's a 1K or 4K page, so quicker to just flush the
+ * entire page.
+ */
+
+ P1 = 32; /* For 1K pages*/
+ P2 = P1 << 2; /* For 4K pages*/
+ P0 = R0; /* Start of page*/
+ CC = BITTST(R1, 16); /* Whether 1K or 4K*/
+ IF CC P1 = P2;
+ P1 += -1; /* Unroll one iteration*/
+ SSYNC;
+ IFLUSH [P0++]; /* because CSYNC can't end loops.*/
+ LSETUP (isall, ieall) LC0 = P1;
+isall:IFLUSH [P0++];
+ieall: NOP;
+ SSYNC;
+ JUMP ifinished;
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(flush_data_cache)
+ [--SP] = ( R7:6, P5:4 );
+ LINK 12;
+ SP += -12;
+ P5.H = (DCPLB_ADDR0 >> 16);
+ P5.L = (DCPLB_ADDR0 & 0xFFFF);
+ P4.H = (DCPLB_DATA0 >> 16);
+ P4.L = (DCPLB_DATA0 & 0xFFFF);
+ R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+ R6 = 16;
+next: R0 = [P5++];
+ R1 = [P4++];
+ CC = BITTST(R1, 14); /* Is it write-through?*/
+ IF CC JUMP skip; /* If so, ignore it.*/
+ R2 = R1 & R7; /* Is it a dirty, cached page?*/
+ CC = R2;
+ IF !CC JUMP skip; /* If not, ignore it.*/
+ [--SP] = RETS;
+ CALL dcplb_flush; /* R0 = page, R1 = data*/
+ RETS = [SP++];
+skip: R6 += -1;
+ CC = R6;
+ IF CC JUMP next;
+ SSYNC;
+ SP += 12;
+ UNLINK;
+ ( R7:6, P5:4 ) = [SP++];
+ RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ *
+ * R0 - page's start address
+ * R1 - CPLB's data field.
+ */
+
+.align 2
+ENTRY(dcplb_flush)
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = LC0;
+ [--SP] = LT0;
+ [--SP] = LB0;
+ [--SP] = LC1;
+ [--SP] = LT1;
+ [--SP] = LB1;
+
+ /* If it's a 1K or 4K page, then it's quickest to
+ * just systematically flush all the addresses in
+ * the page, regardless of whether they're in the
+ * cache, or dirty. If it's a 1M or 4M page, there
+ * are too many addresses, and we have to search the
+ * cache for lines corresponding to the page.
+ */
+
+ CC = BITTST(R1, 17); /* 1MB or 4MB */
+ IF !CC JUMP dflush_whole_page;
+
+ /* We're only interested in the page's size, so extract
+ * this from the CPLB (bits 17:16), and scale to give an
+ * offset into the page_size and page_prefix tables.
+ */
+
+ R1 <<= 14;
+ R1 >>= 30;
+ R1 <<= 2;
+
+ /* The page could be mapped into Bank A or Bank B, depending
+ * on (a) whether both banks are configured as cache, and
+ * (b) on whether address bit A[x] is set. x is determined
+ * by DCBS in DMEM_CONTROL
+ */
+
+ R2 = 0; /* Default to Bank A (Bank B would be 1)*/
+
+ P0.L = (DMEM_CONTROL & 0xFFFF);
+ P0.H = (DMEM_CONTROL >> 16);
+
+ R3 = [P0]; /* If Bank B is not enabled as cache*/
+ CC = BITTST(R3, 2); /* then Bank A is our only option.*/
+ IF CC JUMP bank_chosen;
+
+ R4 = 1<<14; /* If DCBS==0, use A[14].*/
+ R5 = R4 << 7; /* If DCBS==1, use A[23];*/
+ CC = BITTST(R3, 4);
+ IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
+ R5 = R0 & R4; /* Use it to test the Page address*/
+ CC = R5; /* and if that bit is set, we use Bank B,*/
+ R2 = CC; /* else we use Bank A.*/
+ R2 <<= 23; /* The Bank selection's at posn 23.*/
+
+bank_chosen:
+
+ /* We can also determine the sub-bank used, because this is
+ * taken from bits 13:12 of the address.
+ */
+
+ R3 = ((12<<8)|2); /* Extraction pattern */
+ nop; /*Anamoly 05000209*/
+ R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
+ R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
+
+ /* So:
+ * R0 = Page start
+ * R1 = Page length (actually, offset into size/prefix tables)
+ * R2 = Bank select mask
+ * R3 = sub-bank deposit values
+ *
+ * The cache has 2 Ways, and 64 sets, so we iterate through
+ * the sets, accessing the tag for each Way, for our Bank and
+ * sub-bank, looking for dirty, valid tags that match our
+ * address prefix.
+ */
+
+ P5.L = (DTEST_COMMAND & 0xFFFF);
+ P5.H = (DTEST_COMMAND >> 16);
+ P4.L = (DTEST_DATA0 & 0xFFFF);
+ P4.H = (DTEST_DATA0 >> 16);
+
+ P0.L = page_prefix_table;
+ P0.H = page_prefix_table;
+ P1 = R1;
+ R5 = 0; /* Set counter*/
+ P0 = P1 + P0;
+ R4 = [P0]; /* This is the address prefix*/
+
+
+ /* We're reading (bit 1==0) the tag (bit 2==0), and we
+ * don't care about which double-word, since we're only
+ * fetching tags, so we only have to set Set, Bank,
+ * Sub-bank and Way.
+ */
+
+ P2 = 2;
+ LSETUP (fs1, fe1) LC1 = P2;
+fs1: P0 = 64; /* iterate over all sets*/
+ LSETUP (fs0, fe0) LC0 = P0;
+fs0: R6 = R5 << 5; /* Combine set*/
+ R6.H = R3.H << 0 ; /* and sub-bank*/
+ R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
+ BITSET(R6,14);
+ [P5] = R6; /* Issue Command*/
+ SSYNC;
+ R7 = [P4]; /* and read Tag.*/
+ CC = BITTST(R7, 0); /* Check if valid*/
+ IF !CC JUMP fskip; /* and skip if not.*/
+ CC = BITTST(R7, 1); /* Check if dirty*/
+ IF !CC JUMP fskip; /* and skip if not.*/
+
+ /* Compare against the page address. First, plant bits 13:12
+ * into the tag, since those aren't part of the returned data.
+ */
+
+ R7 = DEPOSIT(R7, R3); /* set 13:12*/
+ R1 = R7 & R4; /* Mask off lower bits*/
+ CC = R1 == R0; /* Compare against page start.*/
+ IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
+
+ /* Tag address matches against page, so this is an entry
+ * we must flush.
+ */
+
+ R7 >>= 10; /* Mask off the non-address bits*/
+ R7 <<= 10;
+ P3 = R7;
+ SSYNC;
+ FLUSHINV [P3]; /* And flush the entry*/
+fskip:
+fe0: R5 += 1; /* Advance to next Set*/
+fe1: BITSET(R2, 26); /* Go to next Way.*/
+
+dfinished:
+ SSYNC; /* Ensure the data gets out to mem.*/
+
+ /*Finished. Restore context.*/
+ LB1 = [SP++];
+ LT1 = [SP++];
+ LC1 = [SP++];
+ LB0 = [SP++];
+ LT0 = [SP++];
+ LC0 = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+
+dflush_whole_page:
+
+ /* It's a 1K or 4K page, so quicker to just flush the
+ * entire page.
+ */
+
+ P1 = 32; /* For 1K pages*/
+ P2 = P1 << 2; /* For 4K pages*/
+ P0 = R0; /* Start of page*/
+ CC = BITTST(R1, 16); /* Whether 1K or 4K*/
+ IF CC P1 = P2;
+ P1 += -1; /* Unroll one iteration*/
+ SSYNC;
+ FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
+ LSETUP (eall, eall) LC0 = P1;
+eall: FLUSHINV [P0++];
+ SSYNC;
+ JUMP dfinished;
+
+.align 4;
+page_prefix_table:
+.byte4 0xFFFFFC00; /* 1K */
+.byte4 0xFFFFF000; /* 4K */
+.byte4 0xFFF00000; /* 1M */
+.byte4 0xFFC00000; /* 4M */
+.page_prefix_table.end:
--- /dev/null
+/*
+ * U-boot - interrupt.S Processing of interrupts and exception handling
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on interrupt.S
+ *
+ * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
+ * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
+ * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ * Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ *
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * This file is also based on exception.asm
+ * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+
+#include <asm/hw_irq.h>
+#include <asm/entry.h>
+#include <asm/blackfin_defs.h>
+#include <asm/cpu/bf533_irq.h>
+
+.global blackfin_irq_panic;
+
+.text
+.align 2
+
+#ifndef CONFIG_KGDB
+.global evt_emulation
+evt_emulation:
+ SAVE_CONTEXT
+ r0 = IRQ_EMU;
+ r1 = seqstat;
+ sp += -12;
+ call blackfin_irq_panic;
+ sp += 12;
+ rte;
+#endif
+
+.global evt_nmi
+evt_nmi:
+ SAVE_CONTEXT
+ r0 = IRQ_NMI;
+ r1 = RETN;
+ sp += -12;
+ call blackfin_irq_panic;
+ sp += 12;
+
+_evt_nmi_exit:
+ rtn;
+
+.global trap
+trap:
+ [--sp] = r0;
+ [--sp] = r1;
+ [--sp] = p0;
+ [--sp] = p1;
+ [--sp] = astat;
+ r0 = seqstat;
+ R0 <<= 26;
+ R0 >>= 26;
+ p0 = r0;
+ p1.l = EVTABLE;
+ p1.h = EVTABLE;
+ p0 = p1 + (p0 << 1);
+ r1 = W[p0] (Z);
+ p1 = r1;
+ jump (pc + p1);
+
+.global _EVENT1
+_EVENT1:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT2
+_EVENT2:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT3
+_EVENT3:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT4
+_EVENT4:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT5
+_EVENT5:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT6
+_EVENT6:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT7
+_EVENT7:
+ RAISE 15;
+ JUMP.S _EXIT;
+
+.global _EVENT8
+_EVENT8:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT9
+_EVENT9:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT10
+_EVENT10:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT11
+_EVENT11:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT12
+_EVENT12:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT13
+_EVENT13:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT14
+_EVENT14:
+/* RAISE 14; */
+ CALL _cplb_hdr;
+ JUMP.S _EXIT;
+
+.global _EVENT19
+_EVENT19:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT20
+_EVENT20:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EVENT21
+_EVENT21:
+ RAISE 14;
+ JUMP.S _EXIT;
+
+.global _EXIT
+_EXIT:
+ ASTAT = [sp++];
+ p1 = [sp++];
+ p0 = [sp++];
+ r1 = [sp++];
+ r0 = [sp++];
+ RTX;
+
+EVTABLE:
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x0000;
+ .byte2 0x003E;
+ .byte2 0x0042;
+ .byte4 0x0000;
+ .byte4 0x0000;
+ .byte4 0x0000;
+ .byte4 0x0000;
+ .byte4 0x0000;
+ .byte4 0x0000;
+ .byte4 0x0000;
+ .byte2 0x0000;
+ .byte2 0x001E;
+ .byte2 0x0022;
+ .byte2 0x0032;
+ .byte2 0x002e;
+ .byte2 0x0002;
+ .byte2 0x0036;
+ .byte2 0x002A;
+ .byte2 0x001A;
+ .byte2 0x0016;
+ .byte2 0x000A;
+ .byte2 0x000E;
+ .byte2 0x0012;
+ .byte2 0x0006;
+ .byte2 0x0026;
+
+.global evt_rst
+evt_rst:
+ SAVE_CONTEXT
+ r0 = IRQ_RST;
+ r1 = RETN;
+ sp += -12;
+ call do_reset;
+ sp += 12;
+
+_evt_rst_exit:
+ rtn;
+
+irq_panic:
+ r0 = IRQ_EVX;
+ r1 = sp;
+ sp += -12;
+ call blackfin_irq_panic;
+ sp += 12;
+
+.global evt_ivhw
+evt_ivhw:
+ SAVE_CONTEXT
+ RAISE 14;
+
+_evt_ivhw_exit:
+ rti;
+
+.global evt_timer
+evt_timer:
+ SAVE_CONTEXT
+ r0 = IRQ_CORETMR;
+ sp += -12;
+ /* Polling method used now. */
+ /* call timer_int; */
+ sp += 12;
+ RESTORE_CONTEXT
+ rti;
+ nop;
+
+.global evt_evt7
+evt_evt7:
+ SAVE_CONTEXT
+ r0 = 7;
+ sp += -12;
+ call process_int;
+ sp += 12;
+
+evt_evt7_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global evt_evt8
+evt_evt8:
+ SAVE_CONTEXT
+ r0 = 8;
+ sp += -12;
+ call process_int;
+ sp += 12;
+
+evt_evt8_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global evt_evt9
+evt_evt9:
+ SAVE_CONTEXT
+ r0 = 9;
+ sp += -12;
+ call process_int;
+ sp += 12;
+
+evt_evt9_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global evt_evt10
+evt_evt10:
+ SAVE_CONTEXT
+ r0 = 10;
+ sp += -12;
+ call process_int;
+ sp += 12;
+
+evt_evt10_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global evt_evt11
+evt_evt11:
+ SAVE_CONTEXT
+ r0 = 11;
+ sp += -12;
+ call process_int;
+ sp += 12;
+
+evt_evt11_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global evt_evt12
+evt_evt12:
+ SAVE_CONTEXT
+ r0 = 12;
+ sp += -12;
+ call process_int;
+ sp += 12;
+evt_evt12_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global evt_evt13
+evt_evt13:
+ SAVE_CONTEXT
+ r0 = 13;
+ sp += -12;
+ call process_int;
+ sp += 12;
+
+evt_evt13_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global evt_system_call
+evt_system_call:
+ [--sp] = r0;
+ [--SP] = RETI;
+ r0 = [sp++];
+ r0 += 2;
+ [--sp] = r0;
+ RETI = [SP++];
+ r0 = [SP++];
+ SAVE_CONTEXT
+ sp += -12;
+ call display_excp;
+ sp += 12;
+ RESTORE_CONTEXT
+ RTI;
+
+evt_system_call_exit:
+ rti;
+
+.global evt_soft_int1
+evt_soft_int1:
+ [--sp] = r0;
+ [--SP] = RETI;
+ r0 = [sp++];
+ r0 += 2;
+ [--sp] = r0;
+ RETI = [SP++];
+ r0 = [SP++];
+ SAVE_CONTEXT
+ sp += -12;
+ call display_excp;
+ sp += 12;
+ RESTORE_CONTEXT
+ RTI;
+
+evt_soft_int1_exit:
+ rti;
--- /dev/null
+/*
+ * U-boot - interrupts.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on interrupts.c
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/cpu/defBF533.h>
+#include "cpu.h"
+
+static ulong timestamp;
+static ulong last_time;
+static int int_flag;
+
+int irq_flags; /* needed by asm-blackfin/system.h */
+
+/* Functions just to satisfy the linker */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On BF533 it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On BF533 it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return tbclk;
+}
+
+void enable_interrupts(void)
+{
+ restore_flags(int_flag);
+}
+
+int disable_interrupts(void)
+{
+ save_and_cli(int_flag);
+ return 1;
+}
+
+int interrupt_init(void)
+{
+ return (0);
+}
+
+void udelay(unsigned long usec)
+{
+ unsigned long delay, start, stop;
+ unsigned long cclk;
+ cclk = (CONFIG_CCLK_HZ);
+
+ while ( usec > 1 ) {
+ /*
+ * how many clock ticks to delay?
+ * - request(in useconds) * clock_ticks(Hz) / useconds/second
+ */
+ if (usec < 1000) {
+ delay = (usec * (cclk/244)) >> 12 ;
+ usec = 0;
+ } else {
+ delay = (1000 * (cclk/244)) >> 12 ;
+ usec -= 1000;
+ }
+
+ asm volatile (" %0 = CYCLES;": "=g"(start));
+ do {
+ asm volatile (" %0 = CYCLES; ": "=g"(stop));
+ } while (stop - start < delay);
+ }
+
+ return;
+}
+
+void timer_init(void)
+{
+ *pTCNTL = 0x1;
+ *pTSCALE = 0x0;
+ *pTCOUNT = MAX_TIM_LOAD;
+ *pTPERIOD = MAX_TIM_LOAD;
+ *pTCNTL = 0x7;
+ asm("CSYNC;");
+
+ timestamp = 0;
+ last_time = 0;
+}
+
+/* Any network command or flash
+ * command is started get_timer shall
+ * be called before TCOUNT gets reset,
+ * to implement the accurate timeouts.
+ *
+ * How ever milliconds doesn't return
+ * the number that has been elapsed from
+ * the last reset.
+ *
+ * As get_timer is used in the u-boot
+ * only for timeouts this should be
+ * sufficient
+ */
+ulong get_timer(ulong base)
+{
+ ulong milisec;
+
+ /* Number of clocks elapsed */
+ ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
+
+ /* Find if the TCOUNT is reset
+ timestamp gives the number of times
+ TCOUNT got reset */
+ if(clocks < last_time)
+ timestamp++;
+ last_time = clocks;
+
+ /* Get the number of milliseconds */
+ milisec = clocks/(CONFIG_CCLK_HZ / 1000);
+
+ /* Find the number of millisonds
+ that got elapsed before this TCOUNT
+ cycle */
+ milisec += timestamp * (MAX_TIM_LOAD/(CONFIG_CCLK_HZ / 1000));
+
+ return (milisec - base);
+}
--- /dev/null
+/*
+ * U-boot - ints.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on ints.c
+ *
+ * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
+ * drivers
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/traps.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+void blackfin_irq_panic(int reason, struct pt_regs *regs)
+{
+ printf("\n\nException: IRQ 0x%x entered\n", reason);
+ printf("code=[0x%x], ", (unsigned int) (regs->seqstat & 0x3f));
+ printf("stack frame=0x%x, ", (unsigned int) regs);
+ printf("bad PC=0x%04x\n", (unsigned int) regs->pc);
+ dump(regs);
+ printf("Unhandled IRQ or exceptions!\n");
+ printf("Please reset the board \n");
+}
+
+void blackfin_init_IRQ(void)
+{
+ *(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL;
+ cli();
+#ifndef CONFIG_KGDB
+ *(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0;
+#endif
+ *(unsigned volatile long *) (EVT_NMI_ADDR) =
+ (unsigned volatile long) evt_nmi;
+ *(unsigned volatile long *) (EVT_EXCEPTION_ADDR) =
+ (unsigned volatile long) trap;
+ *(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) =
+ (unsigned volatile long) evt_ivhw;
+ *(unsigned volatile long *) (EVT_RESET_ADDR) =
+ (unsigned volatile long) evt_rst;
+ *(unsigned volatile long *) (EVT_TIMER_ADDR) =
+ (unsigned volatile long) evt_timer;
+ *(unsigned volatile long *) (EVT_IVG7_ADDR) =
+ (unsigned volatile long) evt_evt7;
+ *(unsigned volatile long *) (EVT_IVG8_ADDR) =
+ (unsigned volatile long) evt_evt8;
+ *(unsigned volatile long *) (EVT_IVG9_ADDR) =
+ (unsigned volatile long) evt_evt9;
+ *(unsigned volatile long *) (EVT_IVG10_ADDR) =
+ (unsigned volatile long) evt_evt10;
+ *(unsigned volatile long *) (EVT_IVG11_ADDR) =
+ (unsigned volatile long) evt_evt11;
+ *(unsigned volatile long *) (EVT_IVG12_ADDR) =
+ (unsigned volatile long) evt_evt12;
+ *(unsigned volatile long *) (EVT_IVG13_ADDR) =
+ (unsigned volatile long) evt_evt13;
+ *(unsigned volatile long *) (EVT_IVG14_ADDR) =
+ (unsigned volatile long) evt_system_call;
+ *(unsigned volatile long *) (EVT_IVG15_ADDR) =
+ (unsigned volatile long) evt_soft_int1;
+ *(volatile unsigned long *) ILAT = 0;
+ asm("csync;");
+ sti();
+ *(volatile unsigned long *) IMASK = 0xffbf;
+ asm("csync;");
+}
+
+void display_excp(void)
+{
+ printf("Exception!\n");
+}
--- /dev/null
+/*
+ * U-boot - serial.c Serial driver for BF533
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
+ * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on blkfinserial.c
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
+ * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
+ * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/segment.h>
+#include <asm/bitops.h>
+#include <asm/delay.h>
+#include <asm/uaccess.h>
+#include "bf533_serial.h"
+
+unsigned long pll_div_fact;
+
+void calc_baud(void)
+{
+ unsigned char i;
+ int temp;
+
+ for(i = 0; i < sizeof(baud_table)/sizeof(int); i++) {
+ temp = CONFIG_SCLK_HZ/(baud_table[i]*8);
+ if ( temp && 0x1 == 1 ) {
+ temp++;
+ }
+ temp = temp/2;
+ hw_baud_table[i].dl_high = (temp >> 8)& 0xFF;
+ hw_baud_table[i].dl_low = (temp) & 0xFF;
+ }
+}
+
+void serial_setbrg(void)
+{
+ int i;
+ DECLARE_GLOBAL_DATA_PTR;
+
+ calc_baud();
+
+ for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+ if (gd->baudrate == baud_table[i])
+ break;
+ }
+
+ /* Enable UART */
+ *pUART_GCTL |= UART_GCTL_UCEN;
+ asm("ssync;");
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH;
+ asm("ssync;");
+
+ *pUART_DLL = hw_baud_table[i].dl_low;
+ asm("ssync;");
+ *pUART_DLH = hw_baud_table[i].dl_high;
+ asm("ssync;");
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER;
+ asm("ssync;");
+
+ /* Enable ERBFI and ELSI interrupts
+ * to poll SIC_ISR register*/
+ *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
+ asm("ssync;");
+
+ /* Set LCR to Word Lengh 8-bit word select */
+ *pUART_LCR = UART_LCR_WLS8;
+ asm("ssync;");
+
+ return;
+}
+
+int serial_init(void)
+{
+ serial_setbrg();
+ return (0);
+}
+
+void serial_putc(const char c)
+{
+ if ((*pUART_LSR) & UART_LSR_TEMT)
+ {
+ if (c == '\n')
+ serial_putc('\r');
+
+ local_put_char(c);
+ }
+
+ while (!((*pUART_LSR) & UART_LSR_TEMT))
+ SYNC_ALL;
+
+ return;
+}
+
+int serial_tstc(void)
+{
+ if (*pUART_LSR & UART_LSR_DR)
+ return 1;
+ else
+ return 0;
+}
+
+int serial_getc(void)
+{
+ unsigned short uart_lsr_val, uart_rbr_val;
+ unsigned long isr_val;
+ int ret;
+
+ /* Poll for RX Interrupt */
+ while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT));
+ asm("csync;");
+
+ uart_lsr_val = *pUART_LSR; /* Clear status bit */
+ uart_rbr_val = *pUART_RBR; /* getc() */
+
+ if (isr_val & IRQ_UART_ERROR_BIT) {
+ ret = -1;
+ }
+ else
+ {
+ ret = uart_rbr_val & 0xff;
+ }
+
+ return ret;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s) {
+ serial_putc(*s++);
+ }
+}
+
+static void local_put_char(char ch)
+{
+ int flags = 0;
+ unsigned long isr_val;
+
+ save_and_cli(flags);
+
+ /* Poll for TX Interruput */
+ while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
+ asm("csync;");
+
+ *pUART_THR = ch; /* putc() */
+
+ if (isr_val & IRQ_UART_ERROR_BIT) {
+ printf("?");
+ }
+
+ restore_flags(flags);
+
+ return ;
+}
--- /dev/null
+/*
+ * U-boot - start.S Startup file of u-boot for BF533
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003 Metrowerks/Motorola
+ * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ * Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Note: A change in this file subsequently requires a change in
+ * board/$(board_name)/config.mk for a valid u-boot.bin
+ */
+
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+#include <config.h>
+#include <asm/mem_init.h>
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+.global _stext;
+.global __bss_start;
+.global start;
+.global _start;
+.global _rambase;
+.global _ramstart;
+.global _ramend;
+.global _bf533_data_dest;
+.global _bf533_data_size;
+.global edata;
+.global _initialize;
+.global _exit;
+.global flashdataend;
+
+.text
+_start:
+start:
+_stext:
+
+ R0 = 0x30;
+ SYSCFG = R0;
+ SSYNC;
+
+ /* As per HW reference manual DAG registers,
+ * DATA and Address resgister shall be zero'd
+ * in initialization, after a reset state
+ */
+ r1 = 0; /* Data registers zero'd */
+ r2 = 0;
+ r3 = 0;
+ r4 = 0;
+ r5 = 0;
+ r6 = 0;
+ r7 = 0;
+
+ p0 = 0; /* Address registers zero'd */
+ p1 = 0;
+ p2 = 0;
+ p3 = 0;
+ p4 = 0;
+ p5 = 0;
+
+ i0 = 0; /* DAG Registers zero'd */
+ i1 = 0;
+ i2 = 0;
+ i3 = 0;
+ m0 = 0;
+ m1 = 0;
+ m3 = 0;
+ m3 = 0;
+ l0 = 0;
+ l1 = 0;
+ l2 = 0;
+ l3 = 0;
+ b0 = 0;
+ b1 = 0;
+ b2 = 0;
+ b3 = 0;
+
+ /* Set loop counters to zero, to make sure that
+ * hw loops are disabled.
+ */
+ lc0 = 0;
+ lc1 = 0;
+
+ SSYNC;
+
+ /* Check soft reset status */
+ p0.h = SWRST >> 16;
+ p0.l = SWRST & 0xFFFF;
+ r0.l = w[p0];
+
+ cc = bittst(r0, 15);
+ if !cc jump no_soft_reset;
+
+ /* Clear Soft reset */
+ r0 = 0x0000;
+ w[p0] = r0;
+ ssync;
+
+no_soft_reset:
+ nop;
+
+ /* Clear EVT registers */
+ p0.h = (EVT_EMULATION_ADDR >> 16);
+ p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+ p0 += 8;
+ p1 = 14;
+ r1 = 0;
+ LSETUP(4,4) lc0 = p1;
+ [ p0 ++ ] = r1;
+
+ /*
+ * Set PLL_CTL
+ * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+ * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
+ * - [7] = output delay (add 200ps of delay to mem signals)
+ * - [6] = input delay (add 200ps of input delay to mem signals)
+ * - [5] = PDWN : 1=All Clocks off
+ * - [3] = STOPCK : 1=Core Clock off
+ * - [1] = PLL_OFF : 1=Disable Power to PLL
+ * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+ * all other bits set to zero
+ */
+
+ r0 = CONFIG_VCO_MULT; /* Load the VCO multiplier */
+ r0 = r0 << 9; /* Shift it over */
+ r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
+ r0 = r1 | r0;
+ r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
+ r1 = r1 << 8; /* Shift it over */
+ r0 = r1 | r0; /* add them all together */
+
+ p0.h = (PLL_CTL >> 16);
+ p0.l = (PLL_CTL & 0xFFFF); /* Load the address */
+ cli r2; /* Disable interrupts */
+ w[p0] = r0; /* Set the value */
+ idle; /* Wait for the PLL to stablize */
+ sti r2; /* Enable interrupts */
+ ssync;
+
+ /*
+ * Turn on the CYCLES COUNTER
+ */
+ r2 = SYSCFG;
+ BITSET (r2,1);
+ SYSCFG = r2;
+
+ /* Configure SCLK & CCLK Dividers */
+ r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV;
+ p0.h = (PLL_DIV >> 16);
+ p0.l = (PLL_DIV & 0xFFFF);
+ w[p0] = r0;
+ ssync;
+
+wait_for_pll_stab:
+ p0.h = (PLL_STAT >> 16);
+ p0.l = (PLL_STAT & 0xFFFF);
+ r0.l = w[p0];
+ cc = bittst(r0,5);
+ if !cc jump wait_for_pll_stab;
+
+ /* Configure SDRAM if SDRAM is already not enabled */
+ p0.l = (EBIU_SDSTAT & 0xFFFF);
+ p0.h = (EBIU_SDSTAT >> 16);
+ r0.l = w[p0];
+ cc = bittst(r0, 3);
+ if !cc jump skip_sdram_enable;
+
+ /* SDRAM initialization */
+ p0.l = (EBIU_SDGCTL & 0xFFFF);
+ p0.h = (EBIU_SDGCTL >> 16); /* SDRAM Memory Global Control Register */
+ r0.h = (mem_SDGCTL >> 16);
+ r0.l = (mem_SDGCTL & 0xFFFF);
+ [p0] = r0;
+ ssync;
+
+ p0.l = (EBIU_SDBCTL & 0xFFFF);
+ p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
+ r0 = mem_SDBCTL;
+ w[p0] = r0.l;
+ ssync;
+
+ p0.l = (EBIU_SDRRC & 0xFFFF);
+ p0.h = (EBIU_SDRRC >> 16); /* SDRAM Refresh Rate Control Register */
+ r0 = mem_SDRRC;
+ w[p0] = r0.l;
+ ssync;
+
+skip_sdram_enable:
+ nop;
+
+#ifndef CFG_NO_FLASH
+ /* relocate into to RAM */
+ p1.l = (CFG_FLASH_BASE & 0xffff);
+ p1.h = (CFG_FLASH_BASE >> 16);
+ p2.l = (CFG_MONITOR_BASE & 0xffff);
+ p2.h = (CFG_MONITOR_BASE >> 16);
+ r0.l = (CFG_MONITOR_LEN & 0xffff);
+ r0.h = (CFG_MONITOR_LEN >> 16);
+loop1:
+ r1 = [p1];
+ [p2] = r1;
+ p3=0x4;
+ p1=p1+p3;
+ p2=p2+p3;
+ r2=0x4;
+ r0=r0-r2;
+ cc=r0==0x0;
+ if !cc jump loop1;
+#endif
+ /*
+ * configure STACK
+ */
+ r0.h = (CONFIG_STACKBASE >> 16);
+ r0.l = (CONFIG_STACKBASE & 0xFFFF);
+ sp = r0;
+ fp = sp;
+
+ /*
+ * This next section keeps the processor in supervisor mode
+ * during kernel boot. Switches to user mode at end of boot.
+ * See page 3-9 of Hardware Reference manual for documentation.
+ */
+
+ /* To keep ourselves in the supervisor mode */
+ p0.l = (EVT_IVG15_ADDR & 0xFFFF);
+ p0.h = (EVT_IVG15_ADDR >> 16);
+
+ p1.l = _real_start;
+ p1.h = _real_start;
+ [p0] = p1;
+
+ p0.l = (IMASK & 0xFFFF);
+ p0.h = (IMASK >> 16);
+ r0 = IVG15_POS;
+ [p0] = r0;
+ raise 15;
+ p0.l = WAIT_HERE;
+ p0.h = WAIT_HERE;
+ reti = p0;
+ rti;
+
+WAIT_HERE:
+ jump WAIT_HERE;
+
+.global _real_start;
+_real_start:
+ [ -- sp ] = reti;
+
+#ifdef CONFIG_EZKIT533
+ p0.l = (WDOG_CTL & 0xFFFF);
+ p0.h = (WDOG_CTL >> 16);
+ r0 = WATCHDOG_DISABLE(z);
+ w[p0] = r0;
+#endif
+
+ /* Code for initializing Async mem banks */
+ p2.h = (EBIU_AMBCTL1 >> 16);
+ p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+ r0.h = (AMBCTL1VAL >> 16);
+ r0.l = (AMBCTL1VAL & 0xFFFF);
+ [p2] = r0;
+ ssync;
+
+ p2.h = (EBIU_AMBCTL0 >> 16);
+ p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+ r0.h = (AMBCTL0VAL >> 16);
+ r0.l = (AMBCTL0VAL & 0xFFFF);
+ [p2] = r0;
+ ssync;
+
+ p2.h = (EBIU_AMGCTL >> 16);
+ p2.l = (EBIU_AMGCTL & 0xffff);
+ r0 = AMGCTLVAL;
+ w[p2] = r0;
+ ssync;
+
+ /* DMA reset code to Hi of L1 SRAM */
+copy:
+ P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
+ P1.L = lo(SYSMMR_BASE);
+
+ R0.H = reset_start; /* Source Address (high) */
+ R0.L = reset_start; /* Source Address (low) */
+ R1.H = reset_end;
+ R1.L = reset_end;
+ R2 = R1 - R0; /* Count */
+ R1.H = hi(L1_ISRAM); /* Destination Address (high) */
+ R1.L = lo(L1_ISRAM); /* Destination Address (low) */
+ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
+ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
+
+DMA:
+ R6 = 0x1 (Z);
+ W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
+ W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
+
+ [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
+ W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
+ /* Set Source DMAConfig = DMA Enable,
+ Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
+ W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+ [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
+ W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
+ /* Set Destination DMAConfig = DMA Enable,
+ Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+ IDLE; /* Wait for DMA to Complete */
+
+ R0 = 0x1;
+ W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+ /* DMA reset code to DATA BANK A which uses this port
+ * to avoid following problem
+ * " Data from a Data Cache fill can be corrupoted after or during
+ * instruction DMA if certain core stalls exist"
+ */
+
+copy_as_data:
+ R0.H = reset_start; /* Source Address (high) */
+ R0.L = reset_start; /* Source Address (low) */
+ R1.H = reset_end;
+ R1.L = reset_end;
+ R2 = R1 - R0; /* Count */
+ R1.H = hi(DATA_BANKA_SRAM); /* Destination Address (high) */
+ R1.L = lo(DATA_BANKA_SRAM); /* Destination Address (low) */
+ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
+ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
+
+DMA_DATA:
+ R6 = 0x1 (Z);
+ W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
+ W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
+
+ [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
+ W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
+ /* Set Source DMAConfig = DMA Enable,
+ Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
+ W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+ [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
+ W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
+ /* Set Destination DMAConfig = DMA Enable,
+ Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+ IDLE; /* Wait for DMA to Complete */
+
+ R0 = 0x1;
+ W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+copy_end: nop;
+
+ /* Initialize BSS Section with 0 s */
+ p1.l = __bss_start;
+ p1.h = __bss_start;
+ p2.l = _end;
+ p2.h = _end;
+ r1 = p1;
+ r2 = p2;
+ r3 = r2 - r1;
+ r3 = r3 >> 2;
+ p3 = r3;
+ lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
+ CC = p2<=p1;
+ if CC jump _clear_bss_skip;
+ r0 = 0;
+_clear_bss:
+_clear_bss_end:
+ [p1++] = r0;
+_clear_bss_skip:
+
+ p0.l = _start1;
+ p0.h = _start1;
+ jump (p0);
+
+reset_start:
+ p0.h = WDOG_CNT >> 16;
+ p0.l = WDOG_CNT & 0xffff;
+ r0 = 0x0010;
+ w[p0] = r0;
+ p0.h = WDOG_CTL >> 16;
+ p0.l = WDOG_CTL & 0xffff;
+ r0 = 0x0000;
+ w[p0] = r0;
+reset_wait:
+ jump reset_wait;
+
+reset_end: nop;
+
+_exit:
+ jump.s _exit;
--- /dev/null
+/*
+ * U-boot - start1.S Code running out of RAM after relocation
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <linux/config.h>
+#include <asm/blackfin.h>
+#include <config.h>
+
+.global start1;
+.global _start1;
+
+.text
+_start1:
+start1:
+ sp += -12;
+ call board_init_f;
+ sp += 12;
--- /dev/null
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/page.h>
+#include <asm/machdep.h>
+#include "cpu.h"
+
+void init_IRQ(void)
+{
+ blackfin_init_IRQ();
+ return;
+}
+
+void process_int(unsigned long vec, struct pt_regs *fp)
+{
+ return;
+}
+
+void dump(struct pt_regs *fp)
+{
+ printf("PC: %08lx\n", fp->pc);
+ printf("SEQSTAT: %08lx SP: %08lx\n", (long) fp->seqstat,
+ (long) fp);
+ printf("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
+ fp->r0, fp->r1, fp->r2, fp->r3);
+ printf("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
+ fp->r4, fp->r5, fp->r6, fp->r7);
+ printf("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
+ fp->p0, fp->p1, fp->p2, fp->p3);
+ printf("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5,
+ fp->fp);
+ printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
+ fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+ printf("\n");
+}
int au1x00_enet_initialize(bd_t *bis){
struct eth_device* dev;
- dev = (struct eth_device*) malloc(sizeof *dev);
+ if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
+ puts ("malloc failed\n");
+ return 0;
+ }
+
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "Au1X00 ETHERNET");
+ sprintf(dev->name, "Au1X00 ethernet");
dev->iobase = 0;
dev->priv = 0;
dev->init = au1x00_init;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
ulong sccr, dfbrg;
- ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
+ ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
corecnf_t *cp;
sccr = immap->im_clkrst.car_sccr;
cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
+ pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
cp = &corecnf_tab[corecnf];
cp->vco_div, cp->freq_60x, cp->freq_core);
printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
- "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
- pllmf);
+ "plldf %ld, pllmf %ld, pcidf %ld\n",
+ dfbrg, corecnf, busdf, cpmdf,
+ plldf, pllmf, pcidf);
printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
gd->vco_out, gd->scc_clk, gd->brg_clk);
if (sccr & SCCR_PCI_MODE) {
uint pci_div;
-
- pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
- ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+ uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
+
+ if (sccr & SCCR_PCI_MODCK) {
+ pci_div = 2;
+ if (pcidf == 9) {
+ pci_div *= 5;
+ } else if (pcidf == 0xB) {
+ pci_div *= 6;
+ } else {
+ pci_div *= (pcidf + 1);
+ }
+ } else {
+ pci_div = pcidf + 1;
+ }
printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
}
return (0);
}
-
-/* ------------------------------------------------------------------------- */
#include <watchdog.h>
#include <command.h>
#include <mpc83xx.h>
+#include <ft_build.h>
#include <asm/processor.h>
/* enable Reset Control Reg */
immap->reset.rpr = 0x52535445;
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
/* confirm Reset Control Reg is enabled */
while(!((immap->reset.rcer) & RCER_CRE));
hang(); /* FIXME: implement watchdog_reset()? */
}
#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_OF_FLAT_TREE)
+void
+ft_cpu_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+ ulong clock;
+
+ clock = bd->bi_busfreq;
+ p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+#ifdef CONFIG_MPC83XX_TSEC1
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
+ memcpy(p, bd->bi_enetaddr, 6);
+#endif
+
+#ifdef CONFIG_MPC83XX_TSEC2
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
+ memcpy(p, bd->bi_enet1addr, 6);
+#endif
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+void dma_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile dma8349_t *dma = &immap->dma;
+ volatile u32 status = swab32(dma->dmasr0);
+ volatile u32 dmamr0 = swab32(dma->dmamr0);
+
+ debug("DMA-init\n");
+
+ /* initialize DMASARn, DMADAR and DMAABCRn */
+ dma->dmadar0 = (u32)0;
+ dma->dmasar0 = (u32)0;
+ dma->dmabcr0 = 0;
+
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ /* clear CS bit */
+ dmamr0 &= ~DMA_CHANNEL_START;
+ dma->dmamr0 = swab32(dmamr0);
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ /* while the channel is busy, spin */
+ while(status & DMA_CHANNEL_BUSY) {
+ status = swab32(dma->dmasr0);
+ }
+
+ debug("DMA-init end\n");
+}
+
+uint dma_check(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile dma8349_t *dma = &immap->dma;
+ volatile u32 status = swab32(dma->dmasr0);
+ volatile u32 byte_count = swab32(dma->dmabcr0);
+
+ /* while the channel is busy, spin */
+ while (status & DMA_CHANNEL_BUSY) {
+ status = swab32(dma->dmasr0);
+ }
+
+ if (status & DMA_CHANNEL_TRANSFER_ERROR) {
+ printf ("DMA Error: status = %x @ %d\n", status, byte_count);
+ }
+
+ return status;
+}
+
+int dma_xfer(void *dest, u32 count, void *src)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile dma8349_t *dma = &immap->dma;
+ volatile u32 dmamr0;
+
+ /* initialize DMASARn, DMADAR and DMAABCRn */
+ dma->dmadar0 = swab32((u32)dest);
+ dma->dmasar0 = swab32((u32)src);
+ dma->dmabcr0 = swab32(count);
+
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ /* init direct transfer, clear CS bit */
+ dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
+ DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
+ DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
+
+ dma->dmamr0 = swab32(dmamr0);
+
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ /* set CS to start DMA transfer */
+ dmamr0 |= DMA_CHANNEL_START;
+ dma->dmamr0 = swab32(dmamr0);
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+
+ return ((int)dma_check());
+}
+#endif /*CONFIG_DDR_ECC*/
im->sysconf.spcr |= SPCR_TBEN;
/* System General Purpose Register */
- im->sysconf.sicrh = SICRH_TSOBI1;
- im->sysconf.sicrl = SICRL_LDP_A;
+#ifdef CFG_SICRH
+ im->sysconf.sicrh = CFG_SICRH;
+#endif
+#ifdef CFG_SICRL
+ im->sysconf.sicrl = CFG_SICRL;
+#endif
/*
* Memory Controller:
#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
#endif
-#if defined(CFG_BR1_PRELIM) \
- && defined(CFG_OR1_PRELIM) \
- && defined(CFG_LBLAWBAR1_PRELIM) \
- && defined(CFG_LBLAWAR1_PRELIM)
+#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
im->lbus.bank[1].br = CFG_BR1_PRELIM;
im->lbus.bank[1].or = CFG_OR1_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
#endif
-#if defined(CFG_BR2_PRELIM) \
- && defined(CFG_OR2_PRELIM) \
- && defined(CFG_LBLAWBAR2_PRELIM) \
- && defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
im->lbus.bank[2].br = CFG_BR2_PRELIM;
im->lbus.bank[2].or = CFG_OR2_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
#endif
-#if defined(CFG_BR3_PRELIM) \
- && defined(CFG_OR3_PRELIM) \
- && defined(CFG_LBLAWBAR3_PRELIM) \
- && defined(CFG_LBLAWAR3_PRELIM)
+#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
im->lbus.bank[3].br = CFG_BR3_PRELIM;
im->lbus.bank[3].or = CFG_OR3_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
#endif
-#if defined(CFG_BR4_PRELIM) \
- && defined(CFG_OR4_PRELIM) \
- && defined(CFG_LBLAWBAR4_PRELIM) \
- && defined(CFG_LBLAWAR4_PRELIM)
+#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
im->lbus.bank[4].br = CFG_BR4_PRELIM;
im->lbus.bank[4].or = CFG_OR4_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
#endif
-#if defined(CFG_BR5_PRELIM) \
- && defined(CFG_OR5_PRELIM) \
- && defined(CFG_LBLAWBAR5_PRELIM) \
- && defined(CFG_LBLAWAR5_PRELIM)
+#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
im->lbus.bank[5].br = CFG_BR5_PRELIM;
im->lbus.bank[5].or = CFG_OR5_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
#endif
-#if defined(CFG_BR6_PRELIM) \
- && defined(CFG_OR6_PRELIM) \
- && defined(CFG_LBLAWBAR6_PRELIM) \
- && defined(CFG_LBLAWAR6_PRELIM)
+#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
im->lbus.bank[6].br = CFG_BR6_PRELIM;
im->lbus.bank[6].or = CFG_OR6_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
#endif
-#if defined(CFG_BR7_PRELIM) \
- && defined(CFG_OR7_PRELIM) \
- && defined(CFG_LBLAWBAR7_PRELIM) \
- && defined(CFG_LBLAWAR7_PRELIM)
+#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
im->lbus.bank[7].br = CFG_BR7_PRELIM;
im->lbus.bank[7].or = CFG_OR7_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
#endif
+#ifdef CFG_GPIO1_PRELIM
+ im->pgio[0].dir = CFG_GPIO1_DIR;
+ im->pgio[0].dat = CFG_GPIO1_DAT;
+#endif
+#ifdef CFG_GPIO2_PRELIM
+ im->pgio[1].dir = CFG_GPIO2_DIR;
+ im->pgio[1].dat = CFG_GPIO2_DAT;
+#endif
}
int interrupt_init_cpu (unsigned *decrementer_count)
{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile immap_t *immr = (immap_t *) CFG_IMMRBAR;
+
+ *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
+
+ /* Enable e300 time base */
+
+ immr->sysconf.spcr |= 0x00400000;
+
return 0;
}
/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
return clks;
}
-unsigned int
-banksize(unsigned char row_dens)
+unsigned int banksize(unsigned char row_dens)
{
return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
}
-long int spd_sdram(int(read_spd)(uint addr))
+int read_spd(uint addr)
+{
+ return ((int) addr);
+}
+
+#undef SPD_DEBUG
+#ifdef SPD_DEBUG
+static void spd_debug(spd_eeprom_t *spd)
+{
+ printf ("\nDIMM type: %-18.18s\n", spd->mpart);
+ printf ("SPD size: %d\n", spd->info_size);
+ printf ("EEPROM size: %d\n", 1 << spd->chip_size);
+ printf ("Memory type: %d\n", spd->mem_type);
+ printf ("Row addr: %d\n", spd->nrow_addr);
+ printf ("Column addr: %d\n", spd->ncol_addr);
+ printf ("# of rows: %d\n", spd->nrows);
+ printf ("Row density: %d\n", spd->row_dens);
+ printf ("# of banks: %d\n", spd->nbanks);
+ printf ("Data width: %d\n",
+ 256 * spd->dataw_msb + spd->dataw_lsb);
+ printf ("Chip width: %d\n", spd->primw);
+ printf ("Refresh rate: %02X\n", spd->refresh);
+ printf ("CAS latencies: %02X\n", spd->cas_lat);
+ printf ("Write latencies: %02X\n", spd->write_lat);
+ printf ("tRP: %d\n", spd->trp);
+ printf ("tRCD: %d\n", spd->trcd);
+ printf ("\n");
+}
+#endif /* SPD_DEBUG */
+
+long int spd_sdram()
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
volatile ddr8349_t *ddr = &immap->ddr;
unsigned char caslat;
unsigned int trfc, trfc_clk, trfc_low;
-#warning Current spd_sdram does not fit its usage... adjust implementation or API...
-
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
-
+#ifdef SPD_DEBUG
+ spd_debug(&spd);
+#endif
if (spd.nrows > 2) {
puts("DDR:Only two chip selects are supported on ADS.\n");
return 0;
* Only DDR I is supported
* DDR I and II have different mode-register-set definition
*/
-
- /* burst length is always 4 */
switch(caslat) {
case 2:
- ddr->sdram_mode = 0x52; /* 1.5 */
+ tmp = 0x50; /* 1.5 */
break;
case 3:
- ddr->sdram_mode = 0x22; /* 2.0 */
+ tmp = 0x20; /* 2.0 */
break;
case 4:
- ddr->sdram_mode = 0x62; /* 2.5 */
+ tmp = 0x60; /* 2.5 */
break;
case 5:
- ddr->sdram_mode = 0x32; /* 3.0 */
+ tmp = 0x30; /* 3.0 */
break;
default:
puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
return 0;
}
+#if defined (CONFIG_DDR_32BIT)
+ /* set burst length to 8 for 32-bit data path */
+ tmp |= 0x03;
+#else
+ /* set burst length to 4 - default for 64-bit data path */
+ tmp |= 0x02;
+#endif
+ ddr->sdram_mode = tmp;
debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
switch(spd.refresh) {
*/
#if defined(CONFIG_DDR_ECC)
if (spd.config == 0x02) {
- ddr->err_disable = 0x0000000d;
- ddr->err_sbe = 0x00ff0000;
+ /* disable error detection */
+ ddr->err_disable = ~ECC_ERROR_ENABLE;
+
+ /* set single bit error threshold to maximum value,
+ * reset counter to zero */
+ ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
+ (0 << ECC_ERROR_MAN_SBEC_SHIFT);
}
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
* clock cycle after address/command
*/
- ddr->sdram_clk_cntl = 0x82000000;
+ /*ddr->sdram_clk_cntl = 0x82000000;*/
+ ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
/*
* Figure out the settings for the sdram_cfg register. Build up
*/
tmp = 0xc2000000;
+#if defined (CONFIG_DDR_32BIT)
+ /* in 32-Bit mode burst len is 8 beats */
+ tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
/*
* sdram_cfg[3] = RD_EN - registered DIMM enable
* A value of 0x26 indicates micron registered DIMMS (micron.com)
* If the user wanted ECC (enabled via sdram_cfg[2])
*/
if (spd.config == 0x02) {
- tmp |= 0x20000000;
+ tmp |= SDRAM_CFG_ECC_EN;
}
#endif
udelay(500);
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
-
- return memsize;/*in MBytes*/
+ return memsize; /*in MBytes*/
}
#endif /* CONFIG_SPD_EEPROM */
#if defined(CONFIG_DDR_ECC)
/*
- * Initialize all of memory for ECC, then enable errors.
+ * Use timebase counter, get_timer() is not availabe
+ * at this point of initialization yet.
*/
+static __inline__ unsigned long get_tbms (void)
+{
+ unsigned long tbl;
+ unsigned long tbu1, tbu2;
+ unsigned long ms;
+ unsigned long long tmp;
+
+ ulong tbclk = get_tbclk();
+
+ /* get the timebase ticks */
+ do {
+ asm volatile ("mftbu %0":"=r" (tbu1):);
+ asm volatile ("mftb %0":"=r" (tbl):);
+ asm volatile ("mftbu %0":"=r" (tbu2):);
+ } while (tbu1 != tbu2);
+
+ /* convert ticks to ms */
+ tmp = (unsigned long long)(tbu1);
+ tmp = (tmp << 32);
+ tmp += (unsigned long long)(tbl);
+ ms = tmp/(tbclk/1000);
+
+ return ms;
+}
-void
-ddr_enable_ecc(unsigned int dram_size)
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+//#define CONFIG_DDR_ECC_INIT_VIA_DMA
+void ddr_enable_ecc(unsigned int dram_size)
{
-#ifndef FIXME
- uint *p = 0;
- uint i = 0;
+ uint *p;
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ddr8349_t *ddr = &immap->ddr;
+ unsigned long t_start, t_end;
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+ uint i;
+#endif
+
+ debug("Initialize a Cachline in DRAM\n");
+ icache_enable();
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+ /* Initialise DMA for direct Transfers */
dma_init();
+#endif
+
+ t_start = get_tbms();
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
+#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+ debug("DDR init: Cache flush method\n");
+ for (p = 0; p < (uint *)(dram_size); p++) {
if (((unsigned int)p & 0x1f) == 0) {
ppcDcbz((unsigned long) p);
}
+
+ /* write pattern to cache and flush */
*p = (unsigned int)0xdeadbeef;
+
if (((unsigned int)p & 0x1c) == 0x1c) {
ppcDcbf((unsigned long) p);
}
}
+#else
+ printf("DDR init: DMA method\n");
+ for (p = 0; p < (uint *)(8 * 1024); p++) {
+ /* zero one data cache line */
+ if (((unsigned int)p & 0x1f) == 0) {
+ ppcDcbz((unsigned long)p);
+ }
+
+ /* write pattern to it and flush */
+ *p = (unsigned int)0xdeadbeef;
+
+ if (((unsigned int)p & 0x1c) == 0x1c) {
+ ppcDcbf((unsigned long)p);
+ }
+ }
/* 8K */
dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
}
-
- /*
- * Enable errors for ECC.
- */
- ddr->err_disable = 0x00000000;
- asm("sync;isync");
#endif
-}
+ t_end = get_tbms();
+ icache_disable();
+
+ debug("\nREADY!!\n");
+ debug("ddr init duration: %ld ms\n", t_end - t_start);
+
+ /* Clear All ECC Errors */
+ if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
+ ddr->err_detect |= ECC_ERROR_DETECT_MME;
+ if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
+ ddr->err_detect |= ECC_ERROR_DETECT_MBE;
+ if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
+ ddr->err_detect |= ECC_ERROR_DETECT_SBE;
+ if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
+ ddr->err_detect |= ECC_ERROR_DETECT_MSE;
+
+ /* Disable ECC-Interrupts */
+ ddr->err_int_en &= ECC_ERR_INT_DISABLE;
+
+ /* Enable errors for ECC */
+ ddr->err_disable &= ECC_ERROR_ENABLE;
+
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("isync");
+}
#endif /* CONFIG_DDR_ECC */
#endif
#endif /* CFG_RAMBOOT */
- bl setup_stack_in_data_cache_on_r1
+ /* setup the bats */
+ bl setup_bats
+ sync
+
+ /*
+ * Cache must be enabled here for stack-in-cache trick.
+ * This means we need to enable the BATS.
+ * This means:
+ * 1) for the EVB, original gt regs need to be mapped
+ * 2) need to have an IBAT for the 0xf region,
+ * we are running there!
+ * Cache should be turned on after BATs, since by default
+ * everything is write-through.
+ * The init-mem BAT can be reused after reloc. The old
+ * gt-regs BAT can be reused after board_init_f calls
+ * board_early_init_f (EVB only).
+ */
+ /* enable address translation */
+ bl enable_addr_trans
+ sync
+
+ /* enable and invalidate the data cache */
+ bl dcache_enable
+ sync
+#ifdef CFG_INIT_RAM_LOCK
+ bl lock_ram_in_cache
+ sync
+#endif
+
+ /* set up the stack pointer in our newly created
+ * cache-ram (r1) */
+ lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+
+ li r0, 0 /* Make room for stack frame header and */
+ stwu r0, -4(r1) /* clear final stack frame so that */
+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+
/* let the C-code set up the rest */
- /* */
+ /* */
/* Be careful to keep code relocatable & stack humble */
/*------------------------------------------------------*/
#else
/* Disable Wathcdog */
/*-------------------*/
+ lwz r4, SWCRR(r3)
+ /* Check to see if its enabled for disabling
+ once disabled by SW you can't re-enable */
+ andi. r4, r4, 0x4
+ beq 1f
xor r4, r4, r4
stw r4, SWCRR(r3)
+1:
#endif /* CONFIG_WATCHDOG */
/* Initialize the Hardware Implementation-dependent Registers */
/*------------------------------*/
blr
+ .globl invalidate_bats
+invalidate_bats:
+ /* invalidate BATs */
+ mtspr IBAT0U, r0
+ mtspr IBAT1U, r0
+ mtspr IBAT2U, r0
+ mtspr IBAT3U, r0
+#if (CFG_HID2 & HID2_HBE)
+ mtspr IBAT4U, r0
+ mtspr IBAT5U, r0
+ mtspr IBAT6U, r0
+ mtspr IBAT7U, r0
+#endif
+ isync
+ mtspr DBAT0U, r0
+ mtspr DBAT1U, r0
+ mtspr DBAT2U, r0
+ mtspr DBAT3U, r0
+#if (CFG_HID2 & HID2_HBE)
+ mtspr DBAT4U, r0
+ mtspr DBAT5U, r0
+ mtspr DBAT6U, r0
+ mtspr DBAT7U, r0
+#endif
+ isync
+ sync
+ blr
+
+ /* setup_bats - set them up to some initial state */
+ .globl setup_bats
+setup_bats:
+ addis r0, r0, 0x0000
+
+ /* IBAT 0 */
+ addis r4, r0, CFG_IBAT0L@h
+ ori r4, r4, CFG_IBAT0L@l
+ addis r3, r0, CFG_IBAT0U@h
+ ori r3, r3, CFG_IBAT0U@l
+ mtspr IBAT0L, r4
+ mtspr IBAT0U, r3
+ isync
+
+ /* DBAT 0 */
+ addis r4, r0, CFG_DBAT0L@h
+ ori r4, r4, CFG_DBAT0L@l
+ addis r3, r0, CFG_DBAT0U@h
+ ori r3, r3, CFG_DBAT0U@l
+ mtspr DBAT0L, r4
+ mtspr DBAT0U, r3
+ isync
+
+ /* IBAT 1 */
+ addis r4, r0, CFG_IBAT1L@h
+ ori r4, r4, CFG_IBAT1L@l
+ addis r3, r0, CFG_IBAT1U@h
+ ori r3, r3, CFG_IBAT1U@l
+ mtspr IBAT1L, r4
+ mtspr IBAT1U, r3
+ isync
+
+ /* DBAT 1 */
+ addis r4, r0, CFG_DBAT1L@h
+ ori r4, r4, CFG_DBAT1L@l
+ addis r3, r0, CFG_DBAT1U@h
+ ori r3, r3, CFG_DBAT1U@l
+ mtspr DBAT1L, r4
+ mtspr DBAT1U, r3
+ isync
+
+ /* IBAT 2 */
+ addis r4, r0, CFG_IBAT2L@h
+ ori r4, r4, CFG_IBAT2L@l
+ addis r3, r0, CFG_IBAT2U@h
+ ori r3, r3, CFG_IBAT2U@l
+ mtspr IBAT2L, r4
+ mtspr IBAT2U, r3
+ isync
+
+ /* DBAT 2 */
+ addis r4, r0, CFG_DBAT2L@h
+ ori r4, r4, CFG_DBAT2L@l
+ addis r3, r0, CFG_DBAT2U@h
+ ori r3, r3, CFG_DBAT2U@l
+ mtspr DBAT2L, r4
+ mtspr DBAT2U, r3
+ isync
+
+ /* IBAT 3 */
+ addis r4, r0, CFG_IBAT3L@h
+ ori r4, r4, CFG_IBAT3L@l
+ addis r3, r0, CFG_IBAT3U@h
+ ori r3, r3, CFG_IBAT3U@l
+ mtspr IBAT3L, r4
+ mtspr IBAT3U, r3
+ isync
+
+ /* DBAT 3 */
+ addis r4, r0, CFG_DBAT3L@h
+ ori r4, r4, CFG_DBAT3L@l
+ addis r3, r0, CFG_DBAT3U@h
+ ori r3, r3, CFG_DBAT3U@l
+ mtspr DBAT3L, r4
+ mtspr DBAT3U, r3
+ isync
+
+#if (CFG_HID2 & HID2_HBE)
+ /* IBAT 4 */
+ addis r4, r0, CFG_IBAT4L@h
+ ori r4, r4, CFG_IBAT4L@l
+ addis r3, r0, CFG_IBAT4U@h
+ ori r3, r3, CFG_IBAT4U@l
+ mtspr IBAT4L, r4
+ mtspr IBAT4U, r3
+ isync
+
+ /* DBAT 4 */
+ addis r4, r0, CFG_DBAT4L@h
+ ori r4, r4, CFG_DBAT4L@l
+ addis r3, r0, CFG_DBAT4U@h
+ ori r3, r3, CFG_DBAT4U@l
+ mtspr DBAT4L, r4
+ mtspr DBAT4U, r3
+ isync
+
+ /* IBAT 5 */
+ addis r4, r0, CFG_IBAT5L@h
+ ori r4, r4, CFG_IBAT5L@l
+ addis r3, r0, CFG_IBAT5U@h
+ ori r3, r3, CFG_IBAT5U@l
+ mtspr IBAT5L, r4
+ mtspr IBAT5U, r3
+ isync
+
+ /* DBAT 5 */
+ addis r4, r0, CFG_DBAT5L@h
+ ori r4, r4, CFG_DBAT5L@l
+ addis r3, r0, CFG_DBAT5U@h
+ ori r3, r3, CFG_DBAT5U@l
+ mtspr DBAT5L, r4
+ mtspr DBAT5U, r3
+ isync
+
+ /* IBAT 6 */
+ addis r4, r0, CFG_IBAT6L@h
+ ori r4, r4, CFG_IBAT6L@l
+ addis r3, r0, CFG_IBAT6U@h
+ ori r3, r3, CFG_IBAT6U@l
+ mtspr IBAT6L, r4
+ mtspr IBAT6U, r3
+ isync
+
+ /* DBAT 6 */
+ addis r4, r0, CFG_DBAT6L@h
+ ori r4, r4, CFG_DBAT6L@l
+ addis r3, r0, CFG_DBAT6U@h
+ ori r3, r3, CFG_DBAT6U@l
+ mtspr DBAT6L, r4
+ mtspr DBAT6U, r3
+ isync
+
+ /* IBAT 7 */
+ addis r4, r0, CFG_IBAT7L@h
+ ori r4, r4, CFG_IBAT7L@l
+ addis r3, r0, CFG_IBAT7U@h
+ ori r3, r3, CFG_IBAT7U@l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
+
+ /* DBAT 7 */
+ addis r4, r0, CFG_DBAT7L@h
+ ori r4, r4, CFG_DBAT7L@l
+ addis r3, r0, CFG_DBAT7U@h
+ ori r3, r3, CFG_DBAT7U@l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
+#endif
+
+ /* Invalidate TLBs.
+ * -> for (val = 0; val < 0x20000; val+=0x1000)
+ * -> tlbie(val);
+ */
+ lis r3, 0
+ lis r5, 2
+
+1:
+ tlbie r3
+ addi r3, r3, 0x1000
+ cmp 0, 0, r3, r5
+ blt 1b
+
+ blr
+
+ .globl enable_addr_trans
+enable_addr_trans:
+ /* enable address translation */
+ mfmsr r5
+ ori r5, r5, (MSR_IR | MSR_DR)
+ mtmsr r5
+ isync
+ blr
+
+ .globl disable_addr_trans
+disable_addr_trans:
+ /* disable address translation */
+ mflr r4
+ mfmsr r3
+ andi. r0, r3, (MSR_IR | MSR_DR)
+ beqlr
+ andc r3, r3, r0
+ mtspr SRR0, r4
+ mtspr SRR1, r3
+ rfi
+
/* Cache functions.
*
* Note: requires that all cache bits in
.globl icache_status
icache_status:
mfspr r3, HID0
- rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31
+ rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
.globl dcache_enable
dcache_enable:
mfspr r3, HID0
- ori r3, r3, HID0_ENABLE_DATA_CACHE
- lis r4, 0
- ori r4, r4, HID0_LOCK_DATA_CACHE
- andc r3, r3, r4
- ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE
- sync
- mtspr HID0, r4 /* sets enable and invalidate, clears lock */
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ ori r3, r3, HID0_DCE
+ ori r5, r3, HID0_DCFI
+ mtspr HID0, r5 /* enable + invalidate */
+ mtspr HID0, r3 /* enable */
sync
- mtspr HID0, r3 /* clears invalidate */
blr
.globl dcache_disable
dcache_disable:
mfspr r3, HID0
lis r4, 0
- ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE
+ ori r4, r4, HID0_DCE|HID0_DLOCK
andc r3, r3, r4
- ori r4, r3, HID0_INVALIDATE_DATA_CACHE
+ ori r4, r3, HID0_DCI
sync
- mtspr HID0, r4 /* sets invalidate, clears enable and lock */
+ mtspr HID0, r4 /* sets invalidate, clears enable and lock */
sync
mtspr HID0, r3 /* clears invalidate */
blr
.globl dcache_status
dcache_status:
mfspr r3, HID0
- rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31
+ rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
blr
.globl get_pvr
mfspr r3, PVR
blr
+/*------------------------------------------------------------------------------- */
+/* Function: ppcDcbf */
+/* Description: Data Cache block flush */
+/* Input: r3 = effective address */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcDcbf
+ppcDcbf:
+ dcbf r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: ppcDcbi */
+/* Description: Data Cache block Invalidate */
+/* Input: r3 = effective address */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcDcbi
+ppcDcbi:
+ dcbi r0,r3
+ blr
+
+/*--------------------------------------------------------------------------
+ * Function: ppcDcbz
+ * Description: Data Cache block zero.
+ * Input: r3 = effective address
+ * Output: none.
+ *-------------------------------------------------------------------------- */
+
+ .globl ppcDcbz
+ppcDcbz:
+ dcbz r0,r3
+ blr
+
/*-------------------------------------------------------------------*/
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
-4:
- bl un_setup_stack_in_data_cache
- mr r7, r3
- mr r8, r4
- bl dcache_disable
- mr r3, r7
- mr r4, r8
-
- cmpwi r6,0
+4: cmpwi r6,0
add r5,r3,r5
- beq 7f /* Always flush prefetch queue in any case */
+ beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
- mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/
- rlwinm r7,r7,HID0_DCE_SHIFT,31,31
- cmpwi r7,0
- beq 9f
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
- sync /* Wait for all dcbst to complete on bus */
-9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
- rlwinm r7,r7,HID0_DCE_SHIFT,31,31
- cmpwi r7,0
- beq 7f
+ sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
-7: sync /* Wait for all icbi to complete on bus */
+7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
-
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
blr
#ifdef CFG_INIT_RAM_LOCK
+lock_ram_in_cache:
+ /* Allocate Initial RAM in data cache.
+ */
+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+ li r2, ((CFG_INIT_RAM_END & ~31) + \
+ (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r2
+1:
+ dcbz r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+
+ /* Lock the data cache */
+ mfspr r0, HID0
+ ori r0, r0, 0x1000
+ sync
+ mtspr HID0, r0
+ sync
+ blr
+
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync
+
+ /* Unlock the data cache and invalidate it */
+ mfspr r3, HID0
+ li r5, HID0_DLOCK|HID0_DCFI
+ andc r3, r3, r5 /* no invalidate, unlock */
+ ori r5, r3, HID0_DCFI /* invalidate, unlock */
+ mtspr HID0, r5 /* invalidate, unlock */
+ mtspr HID0, r3 /* no invalidate, unlock */
+ sync
blr
#endif
stw r4, LBLAWBAR1(r3)
stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
blr
-
-setup_stack_in_data_cache_on_r1:
- lis r3, (CFG_IMMRBAR)@h
-
- /* setup D-BAT for the D-Cache (with out real memory backup) */
-
- lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
- mtspr DBAT0U, r4
- ori r4, r4, 0x0002
- mtspr DBAT0L, r4
- isync
-
-#if 0
- /* Enable MMU */
- mfmsr r4
- ori r4, r4, (MSR_DR | MSR_IR)@l
- mtmsr r4
-#endif
-
- /* Enable and invalidate data cache. */
- mfspr r4, HID0
- mr r5, r4
- ori r4, r4, HID0_DCE | HID0_DCI
- ori r5, r5, HID0_DCE
- sync
- mtspr HID0, r4
- mtspr HID0, r5
- sync
-
- /* Allocate Initial RAM in data cache.*/
- li r0, 0
- lis r4, (CFG_INIT_RAM_ADDR)@h
- ori r4, r4, (CFG_INIT_RAM_ADDR)@l
- li r5, 128*8 /* 128*8*32=32Kb */
- mtctr r5
-1:
- dcbz r0, r4
- addi r4, r4, 32
- bdnz 1b
- isync
-
- /* Lock all the D-cache, basically leaving the reset of the program without dcache */
- mfspr r4, HID0
- ori r4, r4, (HID0_DLOCK)@l
- sync
- mtspr HID0 , r4
-
- /* setup the stack pointer in r1 */
- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
- li r0, 0 /* Make room for stack frame header and */
-
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
-
- blr
-
-un_setup_stack_in_data_cache:
- blr
- mr r14, r4
- mr r15, r5
-
-
- lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
- mtspr DBAT0U, r4
- ori r4, r4, 0x0002
- mtspr DBAT0L, r4
- isync
-
- /* un lock all the D-cache */
- mfspr r4, HID0
- lis r5, (~(HID0_DLOCK))@h
- ori r5, r5, (~(HID0_DLOCK))@l
- and r4, r4, r5
- sync
- mtspr HID0 , r4
-
- /* Re - Allocate Initial RAM in data cache.*/
- li r0, 0
- lis r4, (CFG_INIT_RAM_ADDR)@h
- ori r4, r4, (CFG_INIT_RAM_ADDR)@l
- li r5, 128*8 /* 128*8*32=32Kb */
- mtctr r5
-1:
- dcbz r0, r4
- addi r4, r4, 32
- bdnz 1b
- isync
-
- mflr r16
- bl dcache_disable
- mtlr r16
-
- blr
-
-#if 0
-#define GREEN_LIGHT 0x2B0D4046
-#define RED_LIGHT 0x250D4046
-#define LIB_CNT 0x4FFF
-
-/*
- * Lib Light
- */
-
- .globl liblight
-liblight:
- lis r3, CFG_IMMRBAR@h
- ori r3, r3, CFG_IMMRBAR@l
- li r4, 0x3002
- mtmsr r4
- xor r4, r4, r4
- mtspr HID0, r4
- mtspr HID2, r4
- lis r4, 0xF8000000@h
- ori r4, r4, 0xF8000000@l
- stw r4, LBLAWBAR1(r3)
- lis r4, 0x8000000E@h
- ori r4, r4, 0x8000000E@l
- stw r4, LBLAWAR1(r3)
- lis r4, 0xF8000801@h
- ori r4, r4, 0xF8000801@l
- stw r4, BR1(r3)
- lis r4, 0xFFFFE8f0@h
- ori r4, r4, 0xFFFFE8f0@l
- stw r4, OR1(r3)
-
- lis r4, 0xF8000000@h
- ori r4, r4, 0xF8000000@l
- lis r5, GREEN_LIGHT@h
- ori r5, r5, GREEN_LIGHT@l
- lis r6, RED_LIGHT@h
- ori r6, r6, RED_LIGHT@l
- lis r7, LIB_CNT@h
- ori r7, r7, LIB_CNT@l
-
-1:
- stw r5, 0(r4)
- mtctr r7
-2: bdnz 2b
- stw r6, 0(r4)
- mtctr r7
-3: bdnz 3b
- b 1b
-
-#endif
.globl icache_status
icache_status:
mfspr r3,L1CSR1
- srwi r3, r3, 31 /* >>31 => select bit 0 */
+ andi. r3,r3,1
blr
.globl dcache_enable
.globl dcache_status
dcache_status:
mfspr r3,L1CSR0
- srwi r3, r3, 31 /* >>31 => select bit 0 */
+ andi. r3,r3,1
blr
.globl get_pir
k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
m = 0;
+ suf = "";
/*
* Some boards use sockets so different CPUs can be used.
* We have to check chip version in run time.
*/
switch (k) {
- case 0x00020001: pre = 'P'; suf = ""; break;
- case 0x00030001: suf = ""; break;
+ case 0x00020001: pre = 'P'; break;
+ case 0x00030001: break;
case 0x00120003: suf = "A"; break;
case 0x00130003: suf = "A3"; break;
/* this value is not documented anywhere */
case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
- case 0x08000003: pre = 'M'; suf = ""; m = 1;
+ case 0x08010004: /* Rev. A.0 */
+ suf = "A";
+ /* fall through */
+ case 0x08000003: /* Rev. 0.3 */
+ pre = 'M'; m = 1;
if (id_str == NULL)
id_str =
# if defined(CONFIG_MPC852T)
{
unsigned int cmdstat = 0;
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
/* always enable io space on vga boards */
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
mtspr tcr,r0 /* disable all */
mtspr esr,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
-#if !defined(CONFIG_440GX)
- lis r1,0x0002 /* set CE bit (Critical Exceptions) */
- ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
- mtmsr r1 /* change MSR */
-#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
- bl __440gx_msr_set
- b __440gx_msr_continue
-
-__440gx_msr_set:
- lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
- ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
- mtspr srr1,r1
- mflr r1
- mtspr srr0,r1
- rfi
-__440gx_msr_continue:
-#endif
/*----------------------------------------------------------------*/
/* Debug setup -- some (not very good) ice's need an event*/
mtspr esr,r0 /* clear Exception Syndrome Reg */
mttcr r0 /* timer control register */
mtexier r0 /* disable all interrupts */
- addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
- oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */
- mtmsr r4 /* change MSR */
addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
mtdbsr r4 /* clear/reset the dbsr */
mttcr r4 /* clear Timer Control Reg */
mtxer r4 /* clear Fixed-Point Exception Reg */
mtevpr r4 /* clear Exception Vector Prefix Reg */
- addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
- oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
- mtmsr r4 /* change MSR */
addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
/* dbsr is cleared by setting bits to 1) */
mtdbsr r4 /* clear/reset the dbsr */
cmplw 0, r7, r8
blt 4b
+#if !defined(CONFIG_440_GX)
+ addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
+ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
+ mtmsr r7 /* change MSR */
+#else
+ bl __440gx_msr_set
+ b __440gx_msr_continue
+
+__440gx_msr_set:
+ addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
+ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
+ mtspr srr1,r7
+ mflr r7
+ mtspr srr0,r7
+ rfi
+__440gx_msr_continue:
+#endif
+
mtlr r4 /* restore link register */
blr
--- /dev/null
+Overview
+========
+
+The overall usage pattern for ECC diagnostic commands is the following:
+
+ * (injecting errors is initially disabled)
+
+ * define inject mask (which tells the DDR controller what type of errors
+ we'll be injecting: single/multiple bit etc.)
+
+ * enable injecting errors - from now on the controller injects errors as
+ indicated in the inject mask
+
+IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially
+dangerous as such errors are NOT corrected by the controller. Therefore caution
+should be taken when enabling the injection of multiple-bit errors: it is only
+safe when used on a carefully selected memory area and used under control of
+the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In
+particular, when you simply set the multiple-bit errors in inject mask and
+enable injection, U-Boot is very likely to hang quickly as the errors will be
+injected when it accesses its code, data etc.
+
+
+Use cases for DDR 'ecc' command:
+================================
+
+Before executing particular tests reset target board or clear status registers:
+
+=> ecc captureclear
+=> ecc errdetectclr all
+=> ecc sbecnt 0
+
+
+Injecting Single-Bit Errors
+---------------------------
+
+1. Set 1 bit in Data Path Error Inject Mask
+
+=> ecc injectdatahi 1
+
+2. Run test over some memory region
+
+=> ecc test 200000 10
+
+3. Check ECC status
+
+=> ecc status
+...
+Memory Data Path Error Injection Mask High/Low: 00000001 00000000
+...
+Memory Single-Bit Error Management (0..255):
+ Single-Bit Error Threshold: 255
+ Single Bit Error Counter: 16
+...
+Memory Error Detect:
+ Multiple Memory Errors: 0
+ Multiple-Bit Error: 0
+ Single-Bit Error: 0
+...
+
+16 errors were generated, Single-Bit Error flag was not set as Single Bit Error
+Counter did not reach Single-Bit Error Threshold.
+
+4. Make sure used memory region got re-initialized with 0xcafecafe pattern
+
+=> md 200000
+00200000: cafecafe cafecafe cafecafe cafecafe ................
+00200010: cafecafe cafecafe cafecafe cafecafe ................
+00200020: cafecafe cafecafe cafecafe cafecafe ................
+00200030: cafecafe cafecafe cafecafe cafecafe ................
+00200040: cafecafe cafecafe cafecafe cafecafe ................
+00200050: cafecafe cafecafe cafecafe cafecafe ................
+00200060: cafecafe cafecafe cafecafe cafecafe ................
+00200070: cafecafe cafecafe cafecafe cafecafe ................
+00200080: deadbeef deadbeef deadbeef deadbeef ................
+00200090: deadbeef deadbeef deadbeef deadbeef ................
+
+
+Injecting Multiple-Bit Errors
+-----------------------------
+
+1. Set more than 1 bit in Data Path Error Inject Mask
+
+=> ecc injectdatahi 5
+
+2. Run test over some memory region
+
+=> ecc test 200000 10
+
+3. Check ECC status
+
+=> ecc status
+...
+Memory Data Path Error Injection Mask High/Low: 00000005 00000000
+...
+Memory Error Detect:
+ Multiple Memory Errors: 1
+ Multiple-Bit Error: 1
+ Single-Bit Error: 0
+...
+
+Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set.
+
+4. Make sure used memory region got re-initialized with 0xcafecafe pattern
+
+=> md 200000
+00200000: cafecafe cafecafe cafecafe cafecafe ................
+00200010: cafecafe cafecafe cafecafe cafecafe ................
+00200020: cafecafe cafecafe cafecafe cafecafe ................
+00200030: cafecafe cafecafe cafecafe cafecafe ................
+00200040: cafecafe cafecafe cafecafe cafecafe ................
+00200050: cafecafe cafecafe cafecafe cafecafe ................
+00200060: cafecafe cafecafe cafecafe cafecafe ................
+00200070: cafecafe cafecafe cafecafe cafecafe ................
+00200080: deadbeef deadbeef deadbeef deadbeef ................
+00200090: deadbeef deadbeef deadbeef deadbeef ................
+
+
+Test Single-Bit Error Counter and Threshold
+-------------------------------------------
+
+1. Set 1 bit in Data Path Error Inject Mask
+
+=> ecc injectdatahi 1
+
+2. Enable error injection
+
+=> ecc inject en
+
+3. Let u-boot run for a with Single-Bit error injection enabled
+
+4. Disable error injection
+
+=> ecc inject dis
+
+4. Check status
+
+=> ecc status
+
+...
+Memory Single-Bit Error Management (0..255):
+ Single-Bit Error Threshold: 255
+ Single Bit Error Counter: 60
+
+Memory Error Detect:
+ Multiple Memory Errors: 1
+ Multiple-Bit Error: 0
+ Single-Bit Error: 1
+...
+
+Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter
+reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that
+is Counter reached Threshold more than one time (it wraps back after reaching
+Threshold).
+
+
debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
*addr.cp = cword.c;
+#ifdef CONFIG_BLACKFIN
+ asm("ssync;");
+#endif
break;
case FLASH_CFI_16BIT:
debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
cmd, cword.w,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
*addr.wp = cword.w;
+#ifdef CONFIG_BLACKFIN
+ asm("ssync;");
+#endif
break;
case FLASH_CFI_32BIT:
debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
cmd, cword.l,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
*addr.lp = cword.l;
+#ifdef CONFIG_BLACKFIN
+ asm("ssync;");
+#endif
break;
case FLASH_CFI_64BIT:
#ifdef DEBUG
}
#endif
*addr.llp = cword.ll;
+#ifdef CONFIG_BLACKFIN
+ asm("ssync;");
+#endif
break;
}
}
/* Function Name : AT91F_DataflashSelect */
/* Object : Select the correct device */
/*------------------------------------------------------------------------------*/
-AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash,
- unsigned int *addr)
+AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, unsigned long *addr)
{
char addr_valid = 0;
int i;
/*------------------------------------------------------------------------------*/
int read_dataflash (unsigned long addr, unsigned long size, char *result)
{
- int AddrToRead = addr;
+ unsigned long AddrToRead = addr;
AT91PS_DataFlash pFlash = &DataFlashInst;
pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead);
int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
unsigned long size)
{
- int AddrToWrite = addr_dest;
+ unsigned long AddrToWrite = addr_dest;
AT91PS_DataFlash pFlash = &DataFlashInst;
pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite);
if (AddrToWrite == -1)
return -1;
- return AT91F_DataFlashWrite (pFlash, (char *) addr_src, AddrToWrite, size);
+ return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size);
}
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#ifdef CONFIG_DRIVER_KS8695ETH
-
/****************************************************************************/
#include <common.h>
+
+#ifdef CONFIG_DRIVER_KS8695ETH
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
packet, len);
dp = &ks8695_tx[next];
- memcpy((void *) dp->addr, packet, len);
+ memcpy((void *) dp->addr, (void *) packet, len);
if (len < 64) {
- memset(dp->addr+len, 0, 64-len);
+ memset((void *) (dp->addr + len), 0, 64-len);
len = 64;
}
. If an EEPROM is present it really should be consulted.
*/
int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(char *v_rom_mac);
+int get_rom_mac(unsigned char *v_rom_mac);
/* ------------------------------------------------------------
* Internal routines
* ------------------------------------------------------------
*/
-static char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
+static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
/*
* This function must be called before smc_open() if you want to override
* the default mac address.
*/
-void smc_set_mac_addr (const char *addr)
+void smc_set_mac_addr (const unsigned char *addr)
{
int i;
char *s = NULL;
char *e = NULL;
char *v_mac, es[] = "11:22:33:44:55:66";
- uchar s_env_mac[64];
+ char s_env_mac[64];
uchar v_env_mac[6];
uchar v_rom_mac[6];
if (!env_present) { /* if NO env */
if (rom_valid) { /* but ROM is valid */
- v_mac = v_rom_mac;
+ v_mac = (char *)v_rom_mac;
sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
v_mac[0], v_mac[1], v_mac[2], v_mac[3],
v_mac[4], v_mac[5]);
return (-1);
}
} else { /* good env, don't care ROM */
- v_mac = v_env_mac; /* always use a good env over a ROM */
+ v_mac = (char *)v_env_mac; /* always use a good env over a ROM */
}
if (env_present && rom_valid) { /* if both env and ROM are good */
}
}
memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
- smc_set_mac_addr (v_mac); /* use old function to update smc default */
+ smc_set_mac_addr ((unsigned char *)v_mac); /* use old function to update smc default */
PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
return (0);
* Note, this has omly been tested for the OMAP730 P2.
*/
-int get_rom_mac (char *v_rom_mac)
+int get_rom_mac (unsigned char *v_rom_mac)
{
#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
* in order to override the default mac address.
*/
-void smc_set_mac_addr(const char *addr);
+void smc_set_mac_addr(const unsigned char *addr);
/* I want some simple types */
int i, status;
u_char ecc_code[32];
int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
- int *oob_config = oobsel->eccpos;
+ uint *oob_config = oobsel->eccpos;
int datidx = 0, eccidx = 0, eccsteps = this->eccsteps;
int eccbytes = 0;
u_char ecc_calc[32];
u_char ecc_code[32];
int eccmode, eccsteps;
- int *oob_config, datidx;
+ unsigned *oob_config;
+ int datidx;
int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1;
int eccbytes;
int compareecc = 1;
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
+ sub_bus = max(sub_bus, hose->current_busno);
#ifdef CONFIG_PCI_PNP
} else {
int n = pciauto_config_device(hose, dev);
void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
+ struct pci_region *prefetch,
struct pci_region *io)
{
unsigned int bar_value, bar_response, bar_size;
found_mem64 = 1;
bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
- bar_res = mem;
+ if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
+ bar_res = prefetch;
+ else
+ bar_res = mem;
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
}
pci_dev_t dev, int sub_bus)
{
struct pci_region *pci_mem = hose->pci_mem;
+ struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
unsigned int cmdstat;
cmdstat |= PCI_COMMAND_MEMORY;
}
+ if (pci_prefetch) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ /* Set up memory and I/O filter limits, assume 32-bit I/O space */
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+ (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ } else {
+ /* We don't support prefetchable memory for now, so disable */
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
+ }
+
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
cmdstat |= PCI_COMMAND_IO;
}
- /* We don't support prefetchable memory for now, so disable */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
-
/* Enable memory and I/O accesses, enable bus master */
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}
pci_dev_t dev, int sub_bus)
{
struct pci_region *pci_mem = hose->pci_mem;
+ struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
/* Configure bus number registers */
(pci_mem->bus_lower-1) >> 16);
}
+ if (pci_prefetch) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
+ (pci_prefetch->bus_lower-1) >> 16);
+ }
+
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
hose->pci_mem->size < hose->regions[i].size)
hose->pci_mem = hose->regions + i;
break;
+ case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
+ if (!hose->pci_prefetch ||
+ hose->pci_prefetch->size < hose->regions[i].size)
+ hose->pci_prefetch = hose->regions + i;
+ break;
}
}
hose->pci_mem->bus_start + hose->pci_mem->size - 1);
}
+ if (hose->pci_prefetch) {
+ pciauto_region_init(hose->pci_prefetch);
+
+ DEBUGF("PCI Autoconfig: Prefetchable Memory region: [%lx-%lx]\n",
+ hose->pci_prefetch->bus_start,
+ hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1);
+ }
+
if (hose->pci_io) {
pciauto_region_init(hose->pci_io);
switch(class) {
case PCI_CLASS_BRIDGE_PCI:
hose->current_busno++;
- pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
return sub_bus;
}
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
break;
case PCI_CLASS_BRIDGE_CARDBUS:
/* just do a minimal setup of the bridge, let the OS take care of the rest */
- pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
* the PIMMR window to be allocated (BAR0 - 1MB size)
*/
DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
- pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
break;
#endif
default:
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
break;
}
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
*(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
if (PCI_BUS(dev) > 0) \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
else \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
extern int eth_rx(void);
extern int eth_send(volatile void *packet, int length);
+#ifdef SHARED_RESOURCES
+ extern void swap_to(int device_id);
+#endif
/*
. This is called by register_netdev(). It is responsible for
. If an EEPROM is present it really should be consulted.
*/
int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(char *v_rom_mac);
+int get_rom_mac(uchar *v_rom_mac);
/*
------------------------------------------------------------
static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
{
+ volatile word *p = (volatile word *)buf;
+
while (len-- > 0) {
- *((word*)buf)++ = SMC_inw(offset);
- barrier(); *((volatile u32*)(0xc0000000));
+ *p++ = SMC_inw(offset);
+ barrier();
+ *((volatile u32*)(0xc0000000));
}
}
static inline void SMC_outsw(dword offset, uchar* buf, dword len)
{
+ volatile word *p = (volatile word *)buf;
+
while (len-- > 0) {
- SMC_outw(*((word*)buf)++, offset);
- barrier(); *(volatile u32*)(0xc0000000);
+ SMC_outw(*p++, offset);
+ barrier();
+ *(volatile u32*)(0xc0000000);
}
}
#endif /* CONFIG_SMC_USE_IOFUNCS */
* the default mac address.
*/
-void smc_set_mac_addr(const char *addr) {
+void smc_set_mac_addr(const unsigned char *addr) {
int i;
for (i=0; i < sizeof(smc_mac_addr); i++){
SMC_SELECT_BANK( 0 );
SMC_outb( RCR_CLEAR, RCR_REG );
SMC_outb( TCR_CLEAR, TCR_REG );
+#ifdef SHARED_RESOURCES
+ swap_to(FLASH);
+#endif
}
#endif
int eth_init(bd_t *bd) {
+#ifdef SHARED_RESOURCES
+ swap_to(ETHERNET);
+#endif
return (smc_open(bd));
}
{
int env_size, rom_valid, env_present = 0, reg;
char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
- uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6];
+ char s_env_mac[64];
+ uchar v_env_mac[6], v_rom_mac[6];
env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */
if (!env_present) { /* if NO env */
if (rom_valid) { /* but ROM is valid */
- v_mac = v_rom_mac;
+ v_mac = (char *)v_rom_mac;
sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
v_mac[0], v_mac[1], v_mac[2], v_mac[3],
v_mac[4], v_mac[5]);
return (-1);
}
} else { /* good env, don't care ROM */
- v_mac = v_env_mac; /* always use a good env over a ROM */
+ v_mac = (char *)v_env_mac; /* always use a good env over a ROM */
}
if (env_present && rom_valid) { /* if both env and ROM are good */
}
}
memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
- smc_set_mac_addr (v_mac); /* use old function to update smc default */
+ smc_set_mac_addr ((uchar *)v_mac); /* use old function to update smc default */
PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
return (0);
}
-int get_rom_mac (char *v_rom_mac)
+int get_rom_mac (uchar *v_rom_mac)
{
#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
* in order to override the default mac address.
*/
-void smc_set_mac_addr(const char *addr);
+void smc_set_mac_addr (const unsigned char *addr);
/* I want some simple types */
#ifdef CONFIG_ADNPESC1
#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
+#elif CONFIG_BLACKFIN
+#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;})
#else
#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
#endif
#ifdef CONFIG_ADNPESC1
#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
+#elif CONFIG_BLACKFIN
+#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");}
#else
#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
#endif
},
};
+/* Parse the DP83865's link and auto-neg status register for speed and duplex
+ * information */
+uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
+{
+ switch (mii_reg & MIIM_DP83865_SPD_MASK) {
+
+ case MIIM_DP83865_SPD_1000:
+ priv->speed = 1000;
+ break;
+
+ case MIIM_DP83865_SPD_100:
+ priv->speed = 100;
+ break;
+
+ default:
+ priv->speed = 10;
+ break;
+
+ }
+
+ if (mii_reg & MIIM_DP83865_DPX_FULL)
+ priv->duplexity = 1;
+ else
+ priv->duplexity = 0;
+
+ return 0;
+}
+
+struct phy_info phy_info_dp83865 = {
+ 0x20005c7,
+ "NatSemi DP83865",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the link and auto-neg status */
+ {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
+
struct phy_info *phy_info[] = {
#if 0
&phy_info_cis8201,
&phy_info_M88E1111S,
&phy_info_dm9161,
&phy_info_lxt971,
+ &phy_info_dp83865,
NULL
};
/* Cicada 8204 Extended PHY Control Register 1 */
#define MIIM_CIS8204_EPHY_CON 0x17
#define MIIM_CIS8204_EPHYCON_INIT 0x0006
-#define MIIM_CIS8204_EPHYCON_RGMII 0x1000
+#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
/* Cicada 8204 Serial LED Control Register */
#define MIIM_CIS8204_SLED_CON 0x1b
#define MIIM_DM9161_10BTCSR_INIT 0x7800
/* LXT971 Status 2 registers */
-#define MIIM_LXT971_SR2 17 /* Status Register 2 */
-#define MIIM_LXT971_SR2_SPEED_MASK 0xf000
-#define MIIM_LXT971_SR2_10HDX 0x1000 /* 10 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_10FDX 0x2000 /* 10 Mbit full duplex selected */
-#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_100FDX 0x8000 /* 100 Mbit full duplex selected */
+#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
+#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
+#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
+#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
+
+/* DP83865 Control register values */
+#define MIIM_DP83865_CR_INIT 0x9200
+
+/* DP83865 Link and Auto-Neg Status Register */
+#define MIIM_DP83865_LANR 0x11
+#define MIIM_DP83865_SPD_MASK 0x0018
+#define MIIM_DP83865_SPD_1000 0x0010
+#define MIIM_DP83865_SPD_100 0x0008
+#define MIIM_DP83865_DPX_FULL 0x0002
#define MIIM_READ_COMMAND 0x00000001
LOAD_ADDR = 0x80F00000
endif
+ifeq ($(ARCH),blackfin)
+LOAD_ADDR = 0x1000
+endif
+
include $(TOPDIR)/config.mk
SREC = hello_world.srec
BIN += sched.bin sched
endif
+ifeq ($(ARCH),blackfin)
+SREC += smc91111_eeprom.srec
+BIN += smc91111_eeprom.bin smc91111_eeprom
+endif
+
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
SREC += timer.srec
switch (what) {
case 1:
- printf ("Writing EEPROM register %02x with %04x\n",
- reg, value);
+ printf ("Writing EEPROM register %02x with %04x\n", reg, value);
write_eeprom_reg (value, reg);
break;
case 2:
- printf ("Writing MAC register bank %i,
- reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
+ printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
SMC_SELECT_BANK (reg >> 4);
SMC_outw (value, reg & 0xE);
break;
" lwi r5, r5, %1\n" \
" bra r5\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5");
+#elif defined(CONFIG_BLACKFIN)
+/*
+ * P5 holds the pointer to the global_data, P0 is a call-clobbered
+ * register
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile ( \
+" .globl " #x "\n" \
+#x ":\n" \
+" P0 = [P5 + %0]\n" \
+" P0 = [P0 + %1]\n" \
+" JUMP (P0)\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");
#else
#error stubs definition missing for this architecture
#endif
if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) {
/* if its a fragment add it */
if (node->nodetype == JFFS2_NODETYPE_INODE &&
- inode_crc((struct jffs2_raw_inode *) node)) {
+ inode_crc((struct jffs2_raw_inode *) node) &&
+ data_crc((struct jffs2_raw_inode *) node)) {
if (insert_node(&pL->frag, (u32) part->offset +
offset) == NULL) {
put_fl_mem(node);
}
}
+static inline int
+data_crc(struct jffs2_raw_inode *node)
+{
+ if (node->data_crc != crc32_no_comp(0, (unsigned char *)
+ ((int) &node->node_crc + sizeof (node->node_crc)),
+ node->csize)) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
#endif /* jffs2_private.h */
void (*m_func)( void *data);
};
-extern struct _irq_handler IRQ_HANDLER[];
-
#endif
#endif /* __S3C4510_h */
--- /dev/null
+/*
+ * U-boot - bitops.h Routines for bit operations
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_BITOPS_H
+#define _BLACKFIN_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+
+#ifdef __KERNEL__
+/*
+ * Function prototypes to keep gcc -Wall happy
+ */
+
+/*
+ * The __ functions are not atomic
+ */
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+ unsigned long result = 0;
+
+ while (word & 1) {
+ result++;
+ word >>= 1;
+ }
+ return result;
+}
+
+static __inline__ void set_bit(int nr, volatile void *addr)
+{
+ int *a = (int *) addr;
+ int mask;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ save_and_cli(flags);
+ *a |= mask;
+ restore_flags(flags);
+}
+
+static __inline__ void __set_bit(int nr, volatile void *addr)
+{
+ int *a = (int *) addr;
+ int mask;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ *a |= mask;
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit() barrier()
+#define smp_mb__after_clear_bit() barrier()
+
+static __inline__ void clear_bit(int nr, volatile void *addr)
+{
+ int *a = (int *) addr;
+ int mask;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ save_and_cli(flags);
+ *a &= ~mask;
+ restore_flags(flags);
+}
+
+static __inline__ void change_bit(int nr, volatile void *addr)
+{
+ int mask, flags;
+ unsigned long *ADDR = (unsigned long *) addr;
+
+ ADDR += nr >> 5;
+ mask = 1 << (nr & 31);
+ save_and_cli(flags);
+ *ADDR ^= mask;
+ restore_flags(flags);
+}
+
+static __inline__ void __change_bit(int nr, volatile void *addr)
+{
+ int mask;
+ unsigned long *ADDR = (unsigned long *) addr;
+
+ ADDR += nr >> 5;
+ mask = 1 << (nr & 31);
+ *ADDR ^= mask;
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *) addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ save_and_cli(flags);
+ retval = (mask & *a) != 0;
+ *a |= mask;
+ restore_flags(flags);
+
+ return retval;
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *) addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a |= mask;
+ return retval;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *) addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ save_and_cli(flags);
+ retval = (mask & *a) != 0;
+ *a &= ~mask;
+ restore_flags(flags);
+
+ return retval;
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *) addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a &= ~mask;
+ return retval;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *) addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ save_and_cli(flags);
+ retval = (mask & *a) != 0;
+ *a ^= mask;
+ restore_flags(flags);
+
+ return retval;
+}
+
+static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *) addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a ^= mask;
+ return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static __inline__ int __constant_test_bit(int nr,
+ const volatile void *addr)
+{
+ return ((1UL << (nr & 31)) &
+ (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int __test_bit(int nr, volatile void *addr)
+{
+ int *a = (int *) addr;
+ int mask;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ return ((mask & *a) != 0);
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#define find_first_zero_bit(addr, size) \
+ find_next_zero_bit((addr), (size), 0)
+
+static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+{
+ unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+ unsigned long result = offset & ~31UL;
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (32 - offset);
+ if (size < 32)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while (size & ~31UL) {
+ if (~(tmp = *(p++)))
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+ found_first:
+ tmp |= ~0UL >> size;
+ found_middle:
+ return result + ffz(tmp);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x) generic_ffs(x)
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+static __inline__ int ext2_set_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ unsigned long flags;
+ volatile unsigned char *ADDR = (unsigned char *) addr;
+
+ ADDR += nr >> 3;
+ mask = 1 << (nr & 0x07);
+ save_and_cli(flags);
+ retval = (mask & *ADDR) != 0;
+ *ADDR |= mask;
+ restore_flags(flags);
+ return retval;
+}
+
+static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ unsigned long flags;
+ volatile unsigned char *ADDR = (unsigned char *) addr;
+
+ ADDR += nr >> 3;
+ mask = 1 << (nr & 0x07);
+ save_and_cli(flags);
+ retval = (mask & *ADDR) != 0;
+ *ADDR &= ~mask;
+ restore_flags(flags);
+ return retval;
+}
+
+static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
+{
+ int mask;
+ const volatile unsigned char *ADDR = (const unsigned char *) addr;
+
+ ADDR += nr >> 3;
+ mask = 1 << (nr & 0x07);
+ return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+ ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+ unsigned long size,
+ unsigned long
+ offset)
+{
+ unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+ unsigned long result = offset & ~31UL;
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (32 - offset);
+ if (size < 32)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while (size & ~31UL) {
+ if (~(tmp = *(p++)))
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+ found_first:
+ tmp |= ~0UL >> size;
+ found_middle:
+ return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - blackfin.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_H_
+#define _BLACKFIN_H_
+
+#include <asm/cpu/defBF533.h>
+#include <asm/cpu/bf533_serial.h>
+
+#ifndef __ASSEMBLY__
+#ifndef ASSEMBLY
+
+#ifdef SHARED_RESOURCES
+ #include <asm/shared_resources.h>
+#endif
+#include <asm/cpu/cdefBF53x.h>
+
+#endif
+#endif
+
+#include <asm/cpu/defBF533.h>
+#include <asm/cpu/defBF533_extn.h>
+#include <asm/cpu/bf533_serial.h>
+
+#endif
--- /dev/null
+/*
+ * U-boot - blackfin_defs.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_DEFS_H__
+#define __BLACKFIN_DEFS_H__
+
+#define TS_MAGICKEY 0x5a5a5a5a
+#define TASK_STATE 0
+#define TASK_FLAGS 4
+#define TASK_PTRACE 24
+#define TASK_BLOCKED 636
+#define TASK_COUNTER 32
+#define TASK_SIGPENDING 8
+#define TASK_NEEDRESCHED 20
+#define TASK_THREAD 600
+#define TASK_MM 44
+#define TASK_ACTIVE_MM 80
+#define THREAD_KSP 0
+#define THREAD_USP 4
+#define THREAD_SR 8
+#define THREAD_ESP0 12
+#define THREAD_PC 16
+#define PT_ORIG_R0 208
+#define PT_R0 204
+#define PT_R1 200
+#define PT_R2 196
+#define PT_R3 192
+#define PT_R4 188
+#define PT_R5 184
+#define PT_R6 180
+#define PT_R7 176
+#define PT_P0 172
+#define PT_P1 168
+#define PT_P2 164
+#define PT_P3 160
+#define PT_P4 156
+#define PT_P5 152
+#define PT_A0w 72
+#define PT_A1w 64
+#define PT_A0x 76
+#define PT_A1x 68
+#define PT_RETS 28
+#define PT_RESERVED 32
+#define PT_ASTAT 36
+#define PT_SEQSTAT 8
+#define PT_PC 24
+#define PT_IPEND 0
+#define PT_USP 144
+#define PT_FP 148
+#define PT_SYSCFG 4
+#define IRQ_HANDLER 0
+#define IRQ_DEVID 8
+#define IRQ_NEXT 16
+#define STAT_IRQ 5148
+#define SIGSEGV 11
+#define SEGV_MAPERR 196609
+#define SIGTRAP 5
+#define PT_PTRACED 1
+#define PT_TRACESYS 2
+#define PT_DTRACE 4
+
+#endif
--- /dev/null
+/*
+ * U-boot - byteorder.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_BYTEORDER_H
+#define _BLACKFIN_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/little_endian.h>
+
+#endif
--- /dev/null
+/************************************************************************
+ *
+ * cplb.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
+ *
+ ************************************************************************/
+
+/* Defines necessary for cplb initialisation routines. */
+
+#ifndef _CPLB_H
+#define _CPLB_H
+
+#define CPLB_ENABLE_ICACHE_P 0
+#define CPLB_ENABLE_DCACHE_P 1
+#define CPLB_ENABLE_DCACHE2_P 2
+#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/
+#define CPLB_ENABLE_ICPLBS_P 4
+#define CPLB_ENABLE_DCPLBS_P 5
+
+#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
+#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
+#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
+#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
+#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
+#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
+#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
+ CPLB_ENABLE_ICPLBS | \
+ CPLB_ENABLE_DCPLBS
+
+#define CPLB_RELOADED 0x0000
+#define CPLB_NO_UNLOCKED 0x0001
+#define CPLB_NO_ADDR_MATCH 0x0002
+#define CPLB_PROT_VIOL 0x0003
+
+#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
+#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
+
+#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
+
+#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
+#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
+#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
+
+#endif /* _CPLB_H */
--- /dev/null
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
+ * shouldn't be victimized. cplbmgr.S search logic is corrected
+ * to findout the appropriate victim.
+ * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
+ * : LG Soft India
+ */
+#include <config.h>
+
+#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
+#define __ARCH_BFINNOMMU_CPLBTAB_H
+
+/*************************************************************************
+ * ICPLB TABLE
+ *************************************************************************/
+
+.data
+
+/* This table is configurable */
+
+.align 4;
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158 0x200
+#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
+ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+ #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+ #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+ #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+ #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else /*Write Through*/
+ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+ #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+ #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+ #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+ #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+.global icplb_table
+icplb_table:
+.byte4 0xFFA00000;
+.byte4 (L1_IMEMORY);
+.byte4 0x00000000;
+.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
+.byte4 0x00400000;
+.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
+.byte4 0x07C00000;
+.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/
+.byte4 0x00800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
+.byte4 0x01000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
+.byte4 0x02000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
+.byte4 0x02400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
+.byte4 0x02800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
+.byte4 0x02C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
+.byte4 0x03000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
+.byte4 0x03400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
+#endif
+.byte4 0xffffffff; /* end of section - termination*/
+
+.align 4;
+.global ipdt_table
+ipdt_table:
+#ifdef CONFIG_CPLB_INFO
+.byte4 0x00000000;
+.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/
+.byte4 0x00400000;
+.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
+#endif
+.byte4 0x00800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/
+.byte4 0x01000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
+.byte4 0x02000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
+.byte4 0x02400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
+.byte4 0x02800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
+.byte4 0x02C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
+.byte4 0x03000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
+.byte4 0x03400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
+.byte4 0x03800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/
+.byte4 0x03C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/
+#endif
+.byte4 0x20200000;
+.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
+.byte4 0x20100000;
+.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
+.byte4 0x20000000;
+.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
+.byte4 0x20300000; /*Fix for Network*/
+.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
+
+#ifdef CONFIG_STAMP
+.byte4 0x04000000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x04400000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x04800000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x04C00000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x05000000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x05400000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x05800000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x05C00000;
+.byte4 (SDRAM_IGENERIC);
+.byte4 0x06000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/
+.byte4 0x06400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/
+.byte4 0x06800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/
+.byte4 0x06C00000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/
+.byte4 0x07000000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/
+.byte4 0x07400000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/
+.byte4 0x07800000;
+.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/
+#ifdef CONFIG_CPLB_INFO
+.byte4 0x07C00000;
+.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/
+#endif
+#endif
+.byte4 0xffffffff; /* end of section - termination*/
+
+/*********************************************************************
+ * DCPLB TABLE
+ ********************************************************************/
+
+.global dcplb_table
+dcplb_table:
+.byte4 0x00000000;
+.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
+.byte4 0x00400000;
+.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
+.byte4 0x07C00000;
+.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/
+.byte4 0x00800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
+.byte4 0x01000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT
+.byte4 0x02000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
+.byte4 0x02400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
+.byte4 0x02800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
+.byte4 0x02C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
+.byte4 0x03000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
+.byte4 0x03400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
+.byte4 0x03800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
+#endif
+.byte4 0xffffffff; /*end of section - termination*/
+
+/**********************************************************************
+ * PAGE DESCRIPTOR TABLE
+ *
+ **********************************************************************/
+
+/* Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ *
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */
+.global dpdt_table
+dpdt_table:
+#ifdef CONFIG_CPLB_INFO
+.byte4 0x00000000;
+.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/
+.byte4 0x00400000;
+.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
+#endif
+.byte4 0x00800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
+.byte4 0x01000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
+
+#ifndef CONFIG_EZKIT
+.byte4 0x02000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
+.byte4 0x02400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
+.byte4 0x02800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
+.byte4 0x02C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
+.byte4 0x03000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
+.byte4 0x03400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
+.byte4 0x03800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
+.byte4 0x03C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/
+#endif
+.byte4 0x20200000;
+.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
+.byte4 0x20100000;
+.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
+.byte4 0x20000000;
+.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
+.byte4 0x20300000; /*Fix for Network*/
+.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
+
+#ifdef CONFIG_STAMP
+.byte4 0x04000000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x04400000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x04800000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x04C00000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x05000000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x05400000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x05800000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x05C00000;
+.byte4 (SDRAM_DGENERIC);
+.byte4 0x06000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/
+.byte4 0x06400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/
+.byte4 0x06800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/
+.byte4 0x06C00000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/
+.byte4 0x07000000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/
+.byte4 0x07400000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/
+.byte4 0x07800000;
+.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/
+#ifdef CONFIG_CPLB_INFO
+.byte4 0x07C00000;
+.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/
+#endif
+#endif
+
+.byte4 0xFF900000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF901000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF902000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF903000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF904000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF905000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF906000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF907000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF800000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF801000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF802000;
+.byte4 (L1_DMEMORY);
+.byte4 0xFF803000;
+.byte4 (L1_DMEMORY);
+
+.byte4 0xffffffff; /*end of section - termination*/
+
+#ifdef CONFIG_CPLB_INFO
+.global ipdt_swapcount_table; /* swapin count first, then swapout count*/
+ipdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 90 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 100 */
+
+.global dpdt_swapcount_table; /* swapin count first, then swapout count*/
+dpdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 100 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 110 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 120 */
+
+#endif
+
+#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
--- /dev/null
+/*
+ * U-boot bf533_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_IRQ_H_
+#define _BF533_IRQ_H_
+
+/*
+ * Interrupt source definitions
+ * Event Source Core Event Name Number
+ * EMU 0
+ * Reset RST 1
+ * NMI NMI 2
+ * Exception EVX 3
+ * Reserved -- 4
+ * Hardware Error IVHW 5
+ * Core Timer IVTMR 6
+ * PLL Wakeup Interrupt IVG7 7
+ * DMA Error (generic) IVG7 8
+ * PPI Error Interrupt IVG7 9
+ * SPORT0 Error Interrupt IVG7 10
+ * SPORT1 Error Interrupt IVG7 11
+ * SPI Error Interrupt IVG7 12
+ * UART Error Interrupt IVG7 13
+ * RTC Interrupt IVG8 14
+ * DMA0 Interrupt (PPI) IVG8 15
+ * DMA1 (SPORT0 RX) IVG9 16
+ * DMA2 (SPORT0 TX) IVG9 17
+ * DMA3 (SPORT1 RX) IVG9 18
+ * DMA4 (SPORT1 TX) IVG9 19
+ * DMA5 (PPI) IVG10 20
+ * DMA6 (UART RX) IVG10 21
+ * DMA7 (UART TX) IVG10 22
+ * Timer0 IVG11 23
+ * Timer1 IVG11 24
+ * Timer2 IVG11 25
+ * PF Interrupt A IVG12 26
+ * PF Interrupt B IVG12 27
+ * DMA8/9 Interrupt IVG13 28
+ * DMA10/11 Interrupt IVG13 29
+ * Watchdog Timer IVG13 30
+ * Software Interrupt 1 IVG14 31
+ * Software Interrupt 2 --
+ * (lowest priority) IVG15 32
+ */
+
+/* The ABSTRACT IRQ definitions */
+
+/* The first seven of the following are fixed,
+ * the rest you change if you need to
+ */
+
+#define IRQ_EMU 0 /* Emulation */
+#define IRQ_RST 1 /* reset */
+#define IRQ_NMI 2 /* Non Maskable */
+#define IRQ_EVX 3 /* Exception */
+#define IRQ_UNUSED 4 /* - unused interrupt */
+#define IRQ_HWERR 5 /* Hardware Error */
+#define IRQ_CORETMR 6 /* Core timer */
+#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
+#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
+#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
+#define IRQ_UART_ERROR 13 /* UART Error Interrupt */
+#define IRQ_RTC 14 /* RTC Interrupt */
+#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */
+#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */
+#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
+#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */
+#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */
+#define IRQ_TMR0 23 /* Timer 0 */
+#define IRQ_TMR1 24 /* Timer 1 */
+#define IRQ_TMR2 25 /* Timer 2 */
+#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
+#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
+#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define IRQ_WATCH 30 /* Watch Dog Timer */
+#define IRQ_SW_INT1 31 /* Software Int 1 */
+#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */
+
+#define IRQ_UART_RX_BIT 0x4000
+#define IRQ_UART_TX_BIT 0x8000
+#define IRQ_UART_ERROR_BIT 0x40
+
+#define IVG7 7
+#define IVG8 8
+#define IVG9 9
+#define IVG10 10
+#define IVG11 11
+#define IVG12 12
+#define IVG13 13
+#define IVG14 14
+#define IVG15 15
+#define SYS_IRQS 33
+
+#endif
--- /dev/null
+/*
+ * U-boot - bf533_rtc.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_RTC_H_
+#define _BF533_RTC_H_
+
+void rtc_init(void);
+void wait_for_complete(void);
+void rtc_reset(void);
+
+#define MIN_TO_SECS(_x_) (60 * _x_)
+#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
+#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
+
+#define NUM_SECS_IN_DAY (24 * 3600)
+#define NUM_SECS_IN_HOUR (3600)
+#define NUM_SECS_IN_MIN (60)
+
+/* Shift values for RTC_STAT register */
+#define DAY_BITS_OFF 17
+#define HOUR_BITS_OFF 12
+#define MIN_BITS_OFF 6
+#define SEC_BITS_OFF 0
+
+#endif
--- /dev/null
+/*
+ * U-boot bf533_serial.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _BF533_SERIAL_H_
+#define _BF533_SERIAL_H_
+
+#define BYTE_REF(addr) (*((volatile char*)addr))
+#define HALFWORD_REF(addr) (*((volatile short*)addr))
+#define WORD_REF(addr) (*((volatile long*)addr))
+
+#define UART_THR_LO HALFWORD_REF(UART_THR)
+#define UART_RBR_LO HALFWORD_REF(UART_RBR)
+#define UART_DLL_LO HALFWORD_REF(UART_DLL)
+#define UART_IER_LO HALFWORD_REF(UART_IER)
+#define UART_IER_ERBFI 0x01
+#define UART_IER_ETBEI 0x02
+#define UART_IER_ELSI 0x04
+#define UART_IER_EDDSI 0x08
+
+#define UART_DLH_LO HALFWORD_REF(UART_DLH)
+#define UART_IIR_LO HALFWORD_REF(UART_IIR)
+#define UART_IIR_NOINT 0x01
+#define UART_IIR_STATUS 0x06
+#define UART_IIR_LSR 0x06
+#define UART_IIR_RBR 0x04
+#define UART_IIR_THR 0x02
+#define UART_IIR_MSR 0x00
+
+#define UART_LCR_LO HALFWORD_REF(UART_LCR)
+#define UART_LCR_WLS5 0
+#define UART_LCR_WLS6 0x01
+#define UART_LCR_WLS7 0x02
+#define UART_LCR_WLS8 0x03
+#define UART_LCR_STB 0x04
+#define UART_LCR_PEN 0x08
+#define UART_LCR_EPS 0x10
+#define UART_LCR_SP 0x20
+#define UART_LCR_SB 0x40
+#define UART_LCR_DLAB 0x80
+
+#define UART_MCR_LO HALFWORD_REF(UART_MCR)
+
+#define UART_LSR_LO HALFWORD_REF(UART_LSR)
+#define UART_LSR_DR 0x01
+#define UART_LSR_OE 0x02
+#define UART_LSR_PE 0x04
+#define UART_LSR_FE 0x08
+#define UART_LSR_BI 0x10
+#define UART_LSR_THRE 0x20
+#define UART_LSR_TEMT 0x40
+
+#define UART_MSR_LO HALFWORD_REF(UART_MSR)
+#define UART_SCR_LO HALFWORD_REF(UART_SCR)
+#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
+#define UART_GCTL_UCEN 0x01
+
+#endif
--- /dev/null
+/*
+ * cdefBF531.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEFBF531_H
+#define _CDEFBF531_H
+
+#include <cdefBF532.h>
+
+#endif /* _CDEFBF531_H */
--- /dev/null
+/*
+ * cdefBF532.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEF_BF532_H
+#define _CDEF_BF532_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning cdefBF532.h should only be included for 532 compatible chips.
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/cpu/defBF532.h>
+
+/* include core specific register pointer definitions */
+#include <asm/cpu/cdef_LPBlackfin.h>
+
+/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+
+/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
+
+/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
+#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
+#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
+#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
+#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
+#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
+#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
+#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
+#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
+#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
+#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
+#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
+#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
+#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
+#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
+#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
+#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
+#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
+
+/* DMA Test Registers */
+#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP)
+#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP)
+#define pDMA_MISR ((volatile unsigned long *)DMA_MISR)
+#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
+#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
+#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE)
+#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN)
+#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT)
+#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD)
+#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D)
+#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D)
+#define pDMA_TMMA ((volatile void **)DMA_TMMA)
+
+/* DMA Controller */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+
+/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
+/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */
+/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */
+
+/*
+ * #define pDB_ACOMP ((volatile void **)DB_ACOMP)
+ * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
+ */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+
+/* UART Controller */
+#define pUART_THR ((volatile unsigned short *)UART_THR)
+#define pUART_RBR ((volatile unsigned short *)UART_RBR)
+#define pUART_DLL ((volatile unsigned short *)UART_DLL)
+#define pUART_IER ((volatile unsigned short *)UART_IER)
+#define pUART_DLH ((volatile unsigned short *)UART_DLH)
+#define pUART_IIR ((volatile unsigned short *)UART_IIR)
+#define pUART_LCR ((volatile unsigned short *)UART_LCR)
+#define pUART_MCR ((volatile unsigned short *)UART_MCR)
+#define pUART_LSR ((volatile unsigned short *)UART_LSR)
+
+/*
+ * #define UART_MSR
+ */
+#define pUART_SCR ((volatile unsigned short *)UART_SCR)
+#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
+
+/* SPI Controller */
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
+
+/* TIMER 0, 1, 2 Registers */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
+
+/* SPORT0 Controller */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+/* SPORT1 Controller */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+/* Parallel Peripheral Interface (PPI) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+#endif /* _CDEF_BF532_H */
--- /dev/null
+/*
+ * cdefBF533.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEFBF533_H
+#define _CDEFBF533_H
+
+#include <asm/cpu/cdefBF532.h>
+
+#endif /* _CDEFBF533_H */
--- /dev/null
+/************************************************************************
+ *
+ * cdefBF53x.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF53x_H
+#define _CDEFBF53x_H
+
+#if defined(__ADSPBF531__)
+ #include <asm/cpu/cdefBF531.h>
+#elif defined(__ADSPBF532__)
+ #include <asm/cpu/cdefBF532.h>
+#elif defined(__ADSPBF533__)
+ #include <asm/cpu/cdefBF533.h>
+#elif defined(__ADSPBF561__)
+ #include <asm/cpu/cdefBF561.h>
+#elif defined(__ADSPBF535__)
+ #include <asm/cpu/cdefBF535.h>
+#elif defined(__AD6532__)
+ #include <sam/cpu/cdefAD6532.h>
+#else
+ #if defined(__ADSPLPBLACKFIN__)
+ #include <asm/cpu/cdefBF532.h>
+ #else
+ #include <asm/cpu/cdefBF535.h>
+ #endif
+#endif
+
+#endif /* _CDEFBF53x_H */
--- /dev/null
+/*
+ * cdef_LPBlackfin.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEF_LPBLACKFIN_H
+#define _CDEF_LPBLACKFIN_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
+ * #endif
+ */
+#include <asm/cpu/def_LPBlackfin.h>
+
+/* Cache & SRAM Memory */
+#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
+#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
+#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
+#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
+
+/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */
+#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
+#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
+#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
+#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
+#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
+#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
+#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
+#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
+#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
+#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
+#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
+#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
+#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
+#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
+#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
+#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
+#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
+#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
+#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
+#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
+#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
+#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
+#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
+#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
+#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
+#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
+#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
+#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
+#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
+#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
+#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
+#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
+#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
+
+/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */
+#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
+#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
+
+/*
+ * # define DTEST_DATA2 0xFFE00408 Data Test Data Register
+ * #define DTEST_DATA3 0xFFE0040C Data Test Data Register
+ */
+#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
+#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
+#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
+#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
+#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
+#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
+#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
+#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
+#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
+#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
+#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
+#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
+#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
+#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
+#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
+#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
+#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
+#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
+#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
+#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
+#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
+#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
+#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
+#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
+#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
+#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
+#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
+#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
+#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
+#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
+#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
+#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
+#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
+#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
+#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
+#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
+
+/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */
+#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
+#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
+
+/* Event/Interrupt Registers */
+#define pEVT0 ((volatile void **)EVT0)
+#define pEVT1 ((volatile void **)EVT1)
+#define pEVT2 ((volatile void **)EVT2)
+#define pEVT3 ((volatile void **)EVT3)
+#define pEVT4 ((volatile void **)EVT4)
+#define pEVT5 ((volatile void **)EVT5)
+#define pEVT6 ((volatile void **)EVT6)
+#define pEVT7 ((volatile void **)EVT7)
+#define pEVT8 ((volatile void **)EVT8)
+#define pEVT9 ((volatile void **)EVT9)
+#define pEVT10 ((volatile void **)EVT10)
+#define pEVT11 ((volatile void **)EVT11)
+#define pEVT12 ((volatile void **)EVT12)
+#define pEVT13 ((volatile void **)EVT13)
+#define pEVT14 ((volatile void **)EVT14)
+#define pEVT15 ((volatile void **)EVT15)
+#define pIMASK ((volatile unsigned long *)IMASK)
+#define pIPEND ((volatile unsigned long *)IPEND)
+#define pILAT ((volatile unsigned long *)ILAT)
+
+/* Core Timer Registers */
+#define pTCNTL ((volatile unsigned long *)TCNTL)
+#define pTPERIOD ((volatile unsigned long *)TPERIOD)
+#define pTSCALE ((volatile unsigned long *)TSCALE)
+#define pTCOUNT ((volatile unsigned long *)TCOUNT)
+
+/* Debug/MP/Emulation Registers */
+#define pDSPID ((volatile unsigned long *)DSPID)
+#define pDBGCTL ((volatile unsigned long *)DBGCTL)
+#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
+#define pEMUDAT ((volatile unsigned long *)EMUDAT)
+
+/* Trace Buffer Registers */
+#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
+#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
+#define pTBUF ((volatile void **)TBUF)
+
+/* Watch Point Control Registers */
+#define pWPIACTL ((volatile unsigned long *)WPIACTL)
+#define pWPIA0 ((volatile void **)WPIA0)
+#define pWPIA1 ((volatile void **)WPIA1)
+#define pWPIA2 ((volatile void **)WPIA2)
+#define pWPIA3 ((volatile void **)WPIA3)
+#define pWPIA4 ((volatile void **)WPIA4)
+#define pWPIA5 ((volatile void **)WPIA5)
+#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
+#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
+#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
+#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
+#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
+#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
+#define pWPDACTL ((volatile unsigned long *)WPDACTL)
+#define pWPDA0 ((volatile void **)WPDA0)
+#define pWPDA1 ((volatile void **)WPDA1)
+#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
+#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
+#define pWPSTAT ((volatile unsigned long *)WPSTAT)
+
+/* Performance Monitor Registers */
+#define pPFCTL ((volatile unsigned long *)PFCTL)
+#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
+#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+
+/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
+
+#endif /* _CDEF_LPBLACKFIN_H */
--- /dev/null
+/*
+ * defBF531.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEFBF531_H
+#define _DEFBF531_H
+
+#include <defBF532.h>
+
+#endif /* _DEFBF531_H */
--- /dev/null
+/*
+ * defBF532.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_BF532_H
+#define _DEF_BF532_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning defBF532.h should only be included for 532 compatible chips
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/cpu/def_LPBlackfin.h>
+
+/* Helper macros
+ * usage:
+ * P0.H = HI(UART_THR);
+ * P0.L = LO(UART_THR);
+ */
+
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
+/*
+ * System MMR Register Map
+ */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
+#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */
+#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
+#define SYSCR 0xFFC00104 /* System Configuration register */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR 0xFFC00400 /* Transmit Holding register */
+#define UART_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART_LCR 0xFFC0040C /* Line Control Register */
+#define UART_MCR 0xFFC00410 /* Modem Control Register */
+#define UART_LSR 0xFFC00414 /* Line Status Register */
+/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */
+#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART_GCTL 0xFFC00424 /* Global Control Register */
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL 0xFFC00500 /* SPI Control Register */
+#define SPI_FLG 0xFFC00504 /* SPI Flag register */
+#define SPI_STAT 0xFFC00508 /* SPI Status register */
+#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+
+#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
+#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
+#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
+#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
+#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+/* DMA Test Registers */
+#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */
+#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */
+#define DMA_MISR 0xFFC00B08 /* MISR Register */
+#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */
+#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */
+#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */
+#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */
+#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */
+#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */
+#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+
+#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+
+#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
+
+#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+
+#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+
+/*
+ * System MMR Register Bits
+ */
+/*
+ * PLL AND RESET MASKS
+ */
+
+/* PLL_CTL Masks */
+#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
+#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
+#define STOPCK_OFF 0x00000008 /* Core clock off */
+#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
+#define BYPASS 0x00000100 /* Bypass the PLL */
+
+/* PLL_DIV Masks */
+#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
+
+#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
+#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
+#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
+#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
+
+/* SWRST Mask */
+#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
+
+/*
+ * SYSTEM INTERRUPT CONTROLLER MASKS
+ */
+
+/* SIC_IAR0 Masks */
+#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Masks */
+#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Masks */
+#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
+
+/*
+ * WATCHDOG TIMER MASKS
+ */
+/* Watchdog Timer WDOG_CTL Register */
+#define ICTL(x) ((x<<1) & 0x0006)
+#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
+#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
+#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
+#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
+
+#define TMR_EN 0x0000
+#define TMR_DIS 0x0AD0
+#define TRO 0x8000
+
+#define ICTL_P0 0x01
+#define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+/* RTC_STAT and RTC_ALARM register */
+#define RTSEC 0x0000003F /* Real-Time Clock Seconds */
+#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
+#define RTHR 0x0001F000 /* Real-Time Clock Hours */
+#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
+
+/* RTC_ICTL register */
+#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
+#define AIE 0x0002 /* Alarm Interrupt Enable */
+#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MIE 0x0008 /* Minutes Interrupt Enable */
+#define HIE 0x0010 /* Hours Interrupt Enable */
+#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WCIE 0x8000 /* Write Complete Interrupt Enable */
+
+/* RTC_ISTAT register */
+#define SWEF 0x0001 /* Stopwatch Event Flag */
+#define AEF 0x0002 /* Alarm Event Flag */
+#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
+#define MEF 0x0008 /* Minutes Event Flag */
+#define HEF 0x0010 /* Hours Event Flag */
+#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
+#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define WPS 0x4000 /* Write Pending Status (RO) */
+#define WCOM 0x8000 /* Write Complete */
+
+/* RTC_FAST Mask (RTC_PREN Mask) */
+#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
+#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */
+
+/*
+ * UART CONTROLLER MASKS
+ */
+
+/* UART_LCR Register */
+#define DLAB 0x80
+#define SB 0x40
+#define STP 0x20
+#define EPS 0x10
+#define PEN 0x08
+#define STB 0x04
+#define WLS(x) ((x-5) & 0x03)
+
+#define DLAB_P 0x07
+#define SB_P 0x06
+#define STP_P 0x05
+#define EPS_P 0x04
+#define PEN_P 0x03
+#define STB_P 0x02
+#define WLS_P1 0x01
+#define WLS_P0 0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA 0x10
+#define LOOP_ENA_P 0x04
+
+/* UART_LSR Register */
+#define TEMT 0x40
+#define THRE 0x20
+#define BI 0x10
+#define FE 0x08
+#define PE 0x04
+#define OE 0x02
+#define DR 0x01
+
+#define TEMP_P 0x06
+#define THRE_P 0x05
+#define BI_P 0x04
+#define FE_P 0x03
+#define PE_P 0x02
+#define OE_P 0x01
+#define DR_P 0x00
+
+/* UART_IER Register */
+#define ELSI 0x04
+#define ETBEI 0x02
+#define ERBFI 0x01
+
+#define ELSI_P 0x02
+#define ETBEI_P 0x01
+#define ERBFI_P 0x00
+
+/* UART_IIR Register */
+#define STATUS(x) ((x << 1) & 0x06)
+#define NINT 0x01
+#define STATUS_P1 0x02
+#define STATUS_P0 0x01
+#define NINT_P 0x00
+
+/* UART_GCTL Register */
+#define FFE 0x20
+#define FPE 0x10
+#define RPOLC 0x08
+#define TPOLC 0x04
+#define IREN 0x02
+#define UCEN 0x01
+
+#define FFE_P 0x05
+#define FPE_P 0x04
+#define RPOLC_P 0x03
+#define TPOLC_P 0x02
+#define IREN_P 0x01
+#define UCEN_P 0x00
+
+/*
+ * SERIAL PORT MASKS
+ */
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* TX enable */
+#define ITCLK 0x0002 /* Internal TX Clock Select */
+#define TDTYPE 0x000C /* TX Data Formatting Select */
+#define TLSBIT 0x0010 /* TX Bit Order */
+#define ITFS 0x0200 /* Internal TX Frame Sync Select */
+#define TFSR 0x0400 /* TX Frame Sync Required Select */
+#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
+#define LTFS 0x1000 /* Low TX Frame Sync Select */
+#define LATFS 0x2000 /* Late TX Frame Sync Select */
+#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN 0x001F /*TX Word Length */
+#define TXSE 0x0100 /*TX Secondary Enable */
+#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
+#define TRFST 0x0400 /*TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* RX enable */
+#define IRCLK 0x0002 /* Internal RX Clock Select */
+#define RDTYPE 0x000C /* RX Data Formatting Select */
+#define RULAW 0x0008 /* u-Law enable */
+#define RALAW 0x000C /* A-Law enable */
+#define RLSBIT 0x0010 /* RX Bit Order */
+#define IRFS 0x0200 /* Internal RX Frame Sync Select */
+#define RFSR 0x0400 /* RX Frame Sync Required Select */
+#define LRFS 0x1000 /* Low RX Frame Sync Select */
+#define LARFS 0x2000 /* Late RX Frame Sync Select */
+#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN 0x001F /* RX Word Length */
+#define RXSE 0x0100 /* RX Secondary Enable */
+#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE 0x0001 /* RX FIFO Not Empty Status */
+#define RUVF 0x0002 /* RX Underflow Status */
+#define ROVF 0x0004 /* RX Overflow Status */
+#define TXF 0x0008 /* TX FIFO Full Status */
+#define TUVF 0x0010 /* TX Underflow Status */
+#define TOVF 0x0020 /* TX Overflow Status */
+#define TXHRE 0x0040 /* TX Hold Register Empty */
+
+/* SPORTx_MCMC1 Masks */
+#define WSIZE 0x0000F000 /* Multichannel Window Size Field */
+#define WOFF 0x000003FF /* /Multichannel Window Offset Field */
+
+/* SPORTx_MCMC2 Masks */
+#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */
+#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */
+#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */
+#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */
+#define MFD 0x0000F000 /* Multichannel Frame Delay */
+
+/*
+ * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS
+ */
+
+/* PPI_CONTROL Masks */
+#define PORT_EN 0x00000001 /* PPI Port Enable */
+#define PORT_DIR 0x00000002 /* PPI Port Direction */
+#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
+#define PORT_CFG 0x00000030 /* PPI Port Configuration */
+#define FLD_SEL 0x00000040 /* PPI Active Field Select */
+#define PACK_EN 0x00000080 /* PPI Packing Mode */
+#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
+#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
+#define DLENGTH 0x00003800 /* PPI Data Length */
+#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
+#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#define POL 0x0000C000 /* PPI Signal Polarities */
+
+/* PPI_STATUS Masks */
+#define FLD 0x00000400 /* Field Indicator */
+#define FT_ERR 0x00000800 /* Frame Track Error */
+#define OVR 0x00001000 /* FIFO Overflow Error */
+#define UNDR 0x00002000 /* FIFO Underrun Error */
+#define ERR_DET 0x00004000 /* Error Detected Indicator */
+#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
+
+/*
+ * DMA CONTROLLER MASKS
+ */
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN 0x00000001 /* Channel Enable */
+#define WNR 0x00000002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
+#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
+#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
+#define DMA2D 0x00000010 /* 2D/1D* Mode */
+#define RESTART 0x00000020 /* Restart */
+#define DI_SEL 0x00000040 /* Data Interrupt Select */
+#define DI_EN 0x00000080 /* Data Interrupt Enable */
+#define NDSIZE 0x00000900 /* Next Descriptor Size */
+#define FLOW 0x00007000 /* Flow Control */
+
+#define DMAEN_P 0 /* Channel Enable */
+#define WNR_P 1 /* Channel Direction (W/R*) */
+#define DMA2D_P 4 /* 2D/1D* Mode */
+#define RESTART_P 5 /* Restart */
+#define DI_SEL_P 6 /* Data Interrupt Select */
+#define DI_EN_P 7 /* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE 0x00000001 /* DMA Done Indicator */
+#define DMA_ERR 0x00000002 /* DMA Error Indicator */
+#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
+#define DMA_RUN 0x00000008 /* DMA Running Indicator */
+
+#define DMA_DONE_P 0 /* DMA Done Indicator */
+#define DMA_ERR_P 1 /* DMA Error Indicator */
+#define DFETCH_P 2 /* Descriptor Fetch Indicator */
+#define DMA_RUN_P 3 /* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
+#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
+#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
+#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
+#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
+#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
+#define PMAP 0x00007000 /* DMA Peripheral Map Field */
+
+/*
+ * GENERAL PURPOSE TIMER MASKS
+ */
+
+/* PWM Timer bit definitions */
+
+/* TIMER_ENABLE Register */
+#define TIMEN0 0x0001
+#define TIMEN1 0x0002
+#define TIMEN2 0x0004
+
+#define TIMEN0_P 0x00
+#define TIMEN1_P 0x01
+#define TIMEN2_P 0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0 0x0001
+#define TIMDIS1 0x0002
+#define TIMDIS2 0x0004
+
+#define TIMDIS0_P 0x00
+#define TIMDIS1_P 0x01
+#define TIMDIS2_P 0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0 0x0001
+#define TIMIL1 0x0002
+#define TIMIL2 0x0004
+#define TOVL_ERR0 0x0010
+#define TOVL_ERR1 0x0020
+#define TOVL_ERR2 0x0040
+#define TRUN0 0x1000
+#define TRUN1 0x2000
+#define TRUN2 0x4000
+
+#define TIMIL0_P 0x00
+#define TIMIL1_P 0x01
+#define TIMIL2_P 0x02
+#define TOVL_ERR0_P 0x04
+#define TOVL_ERR1_P 0x05
+#define TOVL_ERR2_P 0x06
+#define TRUN0_P 0x0C
+#define TRUN1_P 0x0D
+#define TRUN2_P 0x0E
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT 0x0001
+#define WDTH_CAP 0x0002
+#define EXT_CLK 0x0003
+#define PULSE_HI 0x0004
+#define PERIOD_CNT 0x0008
+#define IRQ_ENA 0x0010
+#define TIN_SEL 0x0020
+#define OUT_DIS 0x0040
+#define CLK_SEL 0x0080
+#define TOGGLE_HI 0x0100
+#define EMU_RUN 0x0200
+#define ERR_TYP(x) ((x & 0x03) << 14)
+
+#define TMODE_P0 0x00
+#define TMODE_P1 0x01
+#define PULSE_HI_P 0x02
+#define PERIOD_CNT_P 0x03
+#define IRQ_ENA_P 0x04
+#define TIN_SEL_P 0x05
+#define OUT_DIS_P 0x06
+#define CLK_SEL_P 0x07
+#define TOGGLE_HI_P 0x08
+#define EMU_RUN_P 0x09
+#define ERR_TYP_P0 0x0E
+#define ERR_TYP_P1 0x0F
+
+/*
+ * PROGRAMMABLE FLAG MASKS
+ */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
+#define PF0_P 0
+#define PF1_P 1
+#define PF2_P 2
+#define PF3_P 3
+#define PF4_P 4
+#define PF5_P 5
+#define PF6_P 6
+#define PF7_P 7
+#define PF8_P 8
+#define PF9_P 9
+#define PF10_P 10
+#define PF11_P 11
+#define PF12_P 12
+#define PF13_P 13
+#define PF14_P 14
+#define PF15_P 15
+
+/*
+ * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
+ */
+
+/* SPI_CTL Masks */
+#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
+#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
+#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
+#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
+#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
+#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
+
+/* SPI_FLG Masks */
+#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
+#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */
+#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
+#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
+#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
+
+/*
+ * ASYNCHRONOUS MEMORY CONTROLLER MASKS
+ */
+
+/* AMGCTL Masks */
+#define AMCKEN 0x00000001 /* Enable CLKOUT */
+#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
+#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
+#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
+
+/*
+ * SDRAM CONTROLLER MASKS
+ */
+
+/* SDGCTL Masks */
+#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define PFE 0x00000010 /* Enable SDRAM prefetch */
+#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /* Power-up start delay */
+#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
+#define EBUFE 0x02000000 /* Enable external buffering timing */
+#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
+#define EMREN 0x10000000 /* Extended mode register enable */
+#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
+#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE 0x00000001 /* Enable SDRAM external bank */
+#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
+#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
+#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x00000001 /* SDRAM controller is idle */
+#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
+#define SDPUA 0x00000004 /* SDRAM power up active */
+#define SDRS 0x00000008 /* SDRAM is in reset state */
+#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT 0x00000020 /* Bus granted */
+
+#endif /* _DEF_BF532_H */
--- /dev/null
+/*
+ * defBF533.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEFBF533_H
+#define _DEFBF533_H
+
+#include <asm/cpu/defBF532.h>
+
+#endif /* _DEFBF533_H */
--- /dev/null
+/*
+ * defBF533_extn.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEF_BF533_EXTN_H
+#define _DEF_BF533_EXTN_H
+
+#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
+/* Delay inserted for PLL transition */
+#define DELAY 0x1000
+
+#define L1_ISRAM 0xFFA00000
+#define L1_ISRAM_END 0xFFA10000
+#define DATA_BANKA_SRAM 0xFF800000
+#define DATA_BANKA_SRAM_END 0xFF808000
+#define DATA_BANKB_SRAM 0xFF900000
+#define DATA_BANKB_SRAM_END 0xFF908000
+#define SYSMMR_BASE 0xFFC00000
+#define WDSIZE16 0x00000004
+
+/* Event Vector Table Address */
+#define EVT_EMULATION_ADDR 0xffe02000
+#define EVT_RESET_ADDR 0xffe02004
+#define EVT_NMI_ADDR 0xffe02008
+#define EVT_EXCEPTION_ADDR 0xffe0200c
+#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
+#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
+#define EVT_TIMER_ADDR 0xffe02018
+#define EVT_IVG7_ADDR 0xffe0201c
+#define EVT_IVG8_ADDR 0xffe02020
+#define EVT_IVG9_ADDR 0xffe02024
+#define EVT_IVG10_ADDR 0xffe02028
+#define EVT_IVG11_ADDR 0xffe0202c
+#define EVT_IVG12_ADDR 0xffe02030
+#define EVT_IVG13_ADDR 0xffe02034
+#define EVT_IVG14_ADDR 0xffe02038
+#define EVT_IVG15_ADDR 0xffe0203c
+#define EVT_OVERRIDE_ADDR 0xffe02100
+
+/* IMASK Bit values */
+#define IVG15_POS 0x00008000
+#define IVG14_POS 0x00004000
+#define IVG13_POS 0x00002000
+#define IVG12_POS 0x00001000
+#define IVG11_POS 0x00000800
+#define IVG10_POS 0x00000400
+#define IVG9_POS 0x00000200
+#define IVG8_POS 0x00000100
+#define IVG7_POS 0x00000080
+#define IVGTMR_POS 0x00000040
+#define IVGHW_POS 0x00000020
+
+#define WDOG_TMR_DISABLE (0xAD << 4)
+#define ICTL_RST 0x00000000
+#define ICTL_NMI 0x00000002
+#define ICTL_GP 0x00000004
+#define ICTL_DISABLE 0x00000003
+
+/* Watch Dog timer values setup */
+#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
+
+#endif /* _DEF_BF533_EXTN_H */
--- /dev/null
+/*
+ * def_LPBlackfin.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_LPBLACKFIN_H
+#define _DEF_LPBLACKFIN_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
+ * #endif
+ */
+
+#define MK_BMSK_( x ) (1<<x) /* Make a bit mask from a bit position */
+
+/*
+ * System Register Bits
+ */
+
+/*
+ * ASTAT register
+ */
+
+/* definitions of ASTAT bit positions */
+#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
+#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */
+#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */
+#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */
+#define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */
+
+/* ** Masks */
+#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */
+#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */
+#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */
+
+/*
+ * SEQSTAT register
+ */
+
+/* ** Bit Positions */
+#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
+#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
+#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
+#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
+#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
+#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
+#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */
+#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
+#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
+#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
+#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
+#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
+#define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */
+#define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */
+#define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */
+
+/* ** Masks */
+/* Exception cause */
+#define SEQSTAT_EXCAUSE MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
+ 0
+
+/* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )
+
+/* Last hw error cause */
+#define SEQSTAT_HWERRCAUSE MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \
+ 0
+
+/*
+ * SYSCFG register
+ */
+
+/* ** Bit Positions */
+#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
+
+/* ** Masks */
+#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P /* Self Nesting Interrupt Enable */
+
+/* Backward-compatibility for typos in prior releases */
+#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
+#define SYSCFG_CCCEN SYSCFG_CCEN
+
+/*
+ * Core MMR Register Map
+ */
+
+/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
+#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
+#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
+#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
+
+/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
+#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
+#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
+#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
+#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
+#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
+
+/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
+#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
+#define IMASK 0xFFE02104 /* Interrupt Mask Register */
+#define IPEND 0xFFE02108 /* Interrupt Pending Register */
+#define ILAT 0xFFE0210C /* Interrupt Latch Register */
+#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
+
+/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
+#define TCNTL 0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
+#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
+
+/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
+#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */
+#define DBGSTAT 0xFFE05008 /* Debug Status Register */
+
+/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
+#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF 0xFFE06100 /* Trace Buffer */
+
+/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
+#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */
+#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */
+#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */
+#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */
+#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */
+#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */
+#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */
+#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */
+#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */
+#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */
+#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */
+#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */
+#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */
+#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */
+#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */
+#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */
+#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */
+#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */
+#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */
+
+/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
+#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
+#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */
+#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */
+
+/*
+ * Core MMR Register Bits
+ */
+
+/*
+ * EVT registers (ILAT, IMASK, and IPEND).
+ */
+
+/* ** Bit Positions */
+#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
+#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
+#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
+#define EVT_EVX_P 0x00000003 /* Exception bit position */
+#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
+#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
+#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
+#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
+#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
+#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
+#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
+#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
+#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
+#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
+#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
+
+/* ** Masks */
+#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
+#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
+#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
+#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
+#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
+#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
+#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
+#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
+#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
+#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
+#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
+#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
+#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
+#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
+#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
+#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
+
+/*
+ * DMEM_CONTROL Register
+ */
+
+/* ** Bit Positions */
+#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */
+#define DMCTL_ENDM_P 0x00 /* "" (older define) */
+#define DMC0_P 0x01 /* Data Memory Configuration, 00 - A SRAM, B SRAM */
+#define DMCTL_DMC0_P 0x01 /* "" (older define) */
+#define DMC1_P 0x02 /* Data Memory Configuration, 10 - A SRAM, B SRAM */
+#define DMCTL_DMC1_P 0x02 /* "" (older define) */
+#define DMC2_P 0x03 /* Data Memory Configuration, 11 - A CACHE, B CACHE */
+#define DMCTL_DMC2_P 0x03 /* "" (older define) */
+#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
+#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
+#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
+
+/* ** Masks */
+#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */
+#define ENDCPLB 0x00000002 /* Enable DCPLB */
+#define ASRAM_BSRAM 0x00000000
+#define ACACHE_BSRAM 0x00000008
+#define ACACHE_BCACHE 0x0000000C
+#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
+#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
+#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
+
+/* IMEM_CONTROL Register */
+/* ** Bit Positions */
+#define ENIM_P 0x00 /* Enable L1 Code Memory */
+#define IMCTL_ENIM_P 0x00 /* "" (older define) */
+#define ENICPLB_P 0x01 /* Enable ICPLB */
+#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
+#define IMC_P 0x02 /* Enable */
+#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0_P 0x03 /* Lock Way 0 */
+#define ILOC1_P 0x04 /* Lock Way 1 */
+#define ILOC2_P 0x05 /* Lock Way 2 */
+#define ILOC3_P 0x06 /* Lock Way 3 */
+#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */
+
+/* ** Masks */
+#define ENIM 0x00000001 /* Enable L1 Code Memory */
+#define ENICPLB 0x00000002 /* Enable ICPLB */
+#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0 0x00000008 /* Lock Way 0 */
+#define ILOC1 0x00000010 /* Lock Way 1 */
+#define ILOC2 0x00000020 /* Lock Way 2 */
+#define ILOC3 0x00000040 /* Lock Way 3 */
+#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */
+
+/* TCNTL Masks */
+#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD 0x00000004 /* Timer auto reload */
+#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* TCNTL Bit Positions */
+#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD_P 0x00000002 /* Timer auto reload */
+#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* DCPLB_DATA and ICPLB_DATA Registers */
+/* ** Bit Positions */
+#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
+
+/* ** Masks */
+#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
+#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
+#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
+#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
+#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
+#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
+#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
+
+/* ICPLB_DATA only */
+#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
+
+/* DCPLB_DATA only */
+#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
+#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes */
+ /* 1= allocate cache lines on write-through writes. */
+#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
+
+/* ITEST_COMMAND and DTEST_COMMAND Registers */
+/* ** Masks */
+#define TEST_READ 0x00000000 /* Read Access */
+#define TEST_WRITE 0x00000002 /* Write Access */
+#define TEST_TAG 0x00000000 /* Access TAG */
+#define TEST_DATA 0x00000004 /* Access DATA */
+#define TEST_DW0 0x00000000 /* Select Double Word 0 */
+#define TEST_DW1 0x00000008 /* Select Double Word 1 */
+#define TEST_DW2 0x00000010 /* Select Double Word 2 */
+#define TEST_DW3 0x00000018 /* Select Double Word 3 */
+#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
+#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
+#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
+#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
+#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
+#define TEST_WAY0 0x00000000 /* Access Way0 */
+#define TEST_WAY1 0x04000000 /* Access Way1 */
+
+/* ** ITEST_COMMAND only */
+#define TEST_WAY2 0x08000000 /* Access Way2 */
+#define TEST_WAY3 0x0C000000 /* Access Way3 */
+
+/* ** DTEST_COMMAND only */
+#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
+#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
+
+#endif /* _DEF_LPBLACKFIN_H */
--- /dev/null
+/*
+ * U-boot - current.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_CURRENT_H
+#define _BLACKFIN_CURRENT_H
+/*
+ * current.h
+ * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
+ *
+ * rather than dedicate a register (as the m68k source does), we
+ * just keep a global, we should probably just change it all to be
+ * current and lose _current_task.
+ */
+
+extern struct task_struct *_current_task;
+#define get_current() _current_task
+#define current _current_task
+
+#endif
--- /dev/null
+/*
+ * U-boot - delay.h Routines for introducing delays
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_DELAY_H
+#define _BLACKFIN_DELAY_H
+
+/*
+ * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
+ * Copyright (C) 1994 Hamish Macdonald
+ *
+ * Delay routines, using a pre-computed "loops_per_second" value.
+ */
+
+extern __inline__ void __delay(unsigned long loops)
+{
+ __asm__ __volatile__("1:\t%0 += -1;\n\t"
+ "cc = %0 == 0;\n\t"
+ "if ! cc jump 1b;\n":"=d"(loops)
+ :"0"(loops));
+}
+
+/*
+ * Use only for very small delays ( < 1 msec). Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays. This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+extern __inline__ void udelay(unsigned long usecs)
+{
+ __delay(usecs);
+}
+
+#endif
--- /dev/null
+/*
+ * U-boot - entry.h Routines for context saving and restoring
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_ENTRY_H
+#define __BLACKFIN_ENTRY_H
+
+#include <linux/config.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+/*
+ * Stack layout in 'ret_from_exception':
+ *
+ */
+
+/*
+ * Register %p2 is now set to the current task throughout
+ * the whole kernel.
+ */
+
+#ifdef __ASSEMBLY__
+
+#define LFLUSH_I_AND_D 0x00000808
+#define LSIGTRAP 5
+
+/* process bits for task_struct.flags */
+#define PF_TRACESYS_OFF 3
+#define PF_TRACESYS_BIT 5
+#define PF_PTRACED_OFF 3
+#define PF_PTRACED_BIT 4
+#define PF_DTRACE_OFF 1
+#define PF_DTRACE_BIT 5
+
+#define NEW_PT_REGS
+
+#if defined(NEW_PT_REGS)
+
+#define SAVE_ALL_INT save_context_no_interrupts
+#define SAVE_ALL_SYS save_context_no_interrupts
+#define SAVE_CONTEXT save_context_with_interrupts
+
+#define RESTORE_ALL restore_context_no_interrupts
+#define RESTORE_ALL_SYS restore_context_no_interrupts
+#define RESTORE_CONTEXT restore_context_with_interrupts
+
+#else
+
+#define SAVE_ALL_INT save_all_int
+#define SAVE_ALL_SYS save_all_sys
+#define SAVE_CONTEXT save_context
+#define RESTORE_ALL restore_context
+#define RESTORE_CONTEXT restore_context
+
+#endif
+
+/*
+ * Code to save processor context.
+ * We even save the register which are preserved by a function call
+ * - r4, r5, r6, r7, p3, p4, p5
+ */
+.macro save_context_with_interrupts
+ [--sp] = R0;
+ [--sp] = ( R7:0, P5:0 );
+ [--sp] = fp;
+ [--sp] = usp;
+
+ [--sp] = i0;
+ [--sp] = i1;
+ [--sp] = i2;
+ [--sp] = i3;
+
+ [--sp] = m0;
+ [--sp] = m1;
+ [--sp] = m2;
+ [--sp] = m3;
+
+ [--sp] = l0;
+ [--sp] = l1;
+ [--sp] = l2;
+ [--sp] = l3;
+
+ [--sp] = b0;
+ [--sp] = b1;
+ [--sp] = b2;
+ [--sp] = b3;
+ [--sp] = a0.x;
+ [--sp] = a0.w;
+ [--sp] = a1.x;
+ [--sp] = a1.w;
+
+ [--sp] = LC0;
+ [--sp] = LC1;
+ [--sp] = LT0;
+ [--sp] = LT1;
+ [--sp] = LB0;
+ [--sp] = LB1;
+
+ [--sp] = ASTAT;
+
+ [--sp] = r0; /* Skip reserved */
+ [--sp] = RETS;
+ [--sp] = RETI;
+ [--sp] = RETX;
+ [--sp] = RETN;
+ [--sp] = RETE;
+ [--sp] = SEQSTAT;
+ [--sp] = SYSCFG;
+ [--sp] = r0; /* Skip IPEND as well. */
+.endm
+
+.macro save_context_no_interrupts
+ [--sp] = R0;
+ [--sp] = ( R7:0, P5:0 );
+ [--sp] = fp;
+ [--sp] = usp;
+
+ [--sp] = i0;
+ [--sp] = i1;
+ [--sp] = i2;
+ [--sp] = i3;
+
+ [--sp] = m0;
+ [--sp] = m1;
+ [--sp] = m2;
+ [--sp] = m3;
+
+ [--sp] = l0;
+ [--sp] = l1;
+ [--sp] = l2;
+ [--sp] = l3;
+
+ [--sp] = b0;
+ [--sp] = b1;
+ [--sp] = b2;
+ [--sp] = b3;
+ [--sp] = a0.x;
+ [--sp] = a0.w;
+ [--sp] = a1.x;
+ [--sp] = a1.w;
+
+ [--sp] = LC0;
+ [--sp] = LC1;
+ [--sp] = LT0;
+ [--sp] = LT1;
+ [--sp] = LB0;
+ [--sp] = LB1;
+
+ [--sp] = ASTAT;
+
+ [--sp] = r0; /* Skip reserved */
+ [--sp] = RETS;
+ r0 = RETI;
+ [--sp] = r0;
+ [--sp] = RETX;
+ [--sp] = RETN;
+ [--sp] = RETE;
+ [--sp] = SEQSTAT;
+ [--sp] = SYSCFG;
+ [--sp] = r0; /* Skip IPEND as well. */
+.endm
+
+.macro restore_context_no_interrupts
+ sp += 4;
+ SYSCFG = [sp++];
+ SEQSTAT = [sp++];
+ RETE = [sp++];
+ RETN = [sp++];
+ RETX = [sp++];
+ r0 = [sp++];
+ RETI = r0;
+ RETS = [sp++];
+
+ sp += 4;
+
+ ASTAT = [sp++];
+
+ LB1 = [sp++];
+ LB0 = [sp++];
+ LT1 = [sp++];
+ LT0 = [sp++];
+ LC1 = [sp++];
+ LC0 = [sp++];
+
+ a1.w = [sp++];
+ a1.x = [sp++];
+ a0.w = [sp++];
+ a0.x = [sp++];
+ b3 = [sp++];
+ b2 = [sp++];
+ b1 = [sp++];
+ b0 = [sp++];
+
+ l3 = [sp++];
+ l2 = [sp++];
+ l1 = [sp++];
+ l0 = [sp++];
+
+ m3 = [sp++];
+ m2 = [sp++];
+ m1 = [sp++];
+ m0 = [sp++];
+
+ i3 = [sp++];
+ i2 = [sp++];
+ i1 = [sp++];
+ i0 = [sp++];
+
+ sp += 4;
+ fp = [sp++];
+
+ ( R7 : 0, P5 : 0) = [ SP ++ ];
+ sp += 4;
+.endm
+
+.macro restore_context_with_interrupts
+ sp += 4;
+ SYSCFG = [sp++];
+ SEQSTAT = [sp++];
+ RETE = [sp++];
+ RETN = [sp++];
+ RETX = [sp++];
+ RETI = [sp++];
+ RETS = [sp++];
+
+ sp += 4;
+
+ ASTAT = [sp++];
+
+ LB1 = [sp++];
+ LB0 = [sp++];
+ LT1 = [sp++];
+ LT0 = [sp++];
+ LC1 = [sp++];
+ LC0 = [sp++];
+
+ a1.w = [sp++];
+ a1.x = [sp++];
+ a0.w = [sp++];
+ a0.x = [sp++];
+ b3 = [sp++];
+ b2 = [sp++];
+ b1 = [sp++];
+ b0 = [sp++];
+
+ l3 = [sp++];
+ l2 = [sp++];
+ l1 = [sp++];
+ l0 = [sp++];
+
+ m3 = [sp++];
+ m2 = [sp++];
+ m1 = [sp++];
+ m0 = [sp++];
+
+ i3 = [sp++];
+ i2 = [sp++];
+ i1 = [sp++];
+ i0 = [sp++];
+
+ sp += 4;
+ fp = [sp++];
+
+ ( R7 : 0, P5 : 0) = [ SP ++ ];
+ sp += 4;
+.endm
+
+#if !defined(NEW_PT_REGS)
+/*
+ * a -1 in the orig_r0 field signifies
+ * that the stack frame is NOT for syscall
+ */
+.macro save_all_int
+/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */
+ [--sp] = r0;
+ r0.l = 0x30; /* Errata for BF533 */
+ r0.h = 0x0;
+ syscfg = r0; /* disable single step flag in SYSCFG */
+ r0 = [sp++];
+ [--sp] = syscfg; /* store SYSCFG */
+
+ [--sp] = r0; /* Reserved for IPEND */
+ [--sp] = fp;
+ [--sp] = usp;
+ [--sp] = r0;
+
+ [--sp] = r0;
+ r0 = [sp + 8];
+ [--sp] = a0.x;
+ [--sp] = a1.x;
+ [--sp] = a0.w;
+ [--sp] = a1.w;
+ [--sp] = rets;
+ [--sp] = astat;
+ [--sp] = seqstat;
+ [--sp] = retx; /* current pc when exception happens */
+ [--sp] = ( r7:5, p5:0 );
+ [--sp] = r1;
+ [--sp] = r2;
+ [--sp] = r4;
+ [--sp] = r3;
+.endm
+
+.macro save_all_sys
+ [--sp] = r0;
+ [--sp] = r0;
+ [--sp] = a0.x;
+ [--sp] = a1.x;
+ [--sp] = a0.w;
+ [--sp] = a1.w;
+ [--sp] = rets;
+ [--sp] = astat;
+ [--sp] = seqstat;
+ [--sp] = retx; /* current pc when exception happens */
+ [--sp] = ( r7:5, p5:0 );
+ [--sp] = r1;
+ [--sp] = r2;
+ [--sp] = r4;
+ [--sp] = r3;
+.endm
+
+.macro restore_all
+ r3 = [sp++];
+ r4 = [sp++];
+ r2 = [sp++];
+ r1 = [sp++];
+ ( r7:5, p5:0 ) = [sp++];
+ retx = [sp++];
+ seqstat = [sp++];
+ astat = [sp++];
+ rets = [sp++];
+ a1.w = [sp++];
+ a0.w = [sp++];
+ a1.x = [sp++];
+ a0.x = [sp++];
+ sp += 4; /* orig r0 */
+ r0 = [sp++];
+
+ sp += 4;
+ fp = [sp++];
+ sp +=4; /* Skip the IPEND */
+
+ syscfg = [sp++];
+
+.endm
+
+#endif
+
+#define STR(X) STR1(X)
+#define STR1(X) #X
+
+#if defined(NEW_PT_REGS)
+
+#define PT_OFF_ORIG_R0 208
+#define PT_OFF_SR 8
+
+#else
+
+#define PT_OFF_ORIG_R0 0x54
+#define PT_OFF_SR 0x38 /* seqstat in pt_regs */
+
+#endif
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_ERRNO_H
+#define _BLACKFIN_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+#endif
--- /dev/null
+/*
+ * U-boot - global_data.h Declarations for global data of u-boot
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/irq.h>
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+typedef struct global_data {
+ bd_t *bd;
+ unsigned long flags;
+ unsigned long board_type;
+ unsigned long baudrate;
+ unsigned long have_console; /* serial_init() was called */
+ unsigned long ram_size; /* RAM size */
+ unsigned long reloc_off; /* Relocation Offset */
+ unsigned long env_addr; /* Address of Environment struct */
+ unsigned long env_valid; /* Checksum of Environment valid? */
+ void **jt; /* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
+#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+#define GD_FLG_SILENT 0x00004 /* Silent mode */
+
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5")
+
+#endif
--- /dev/null
+/*
+ * U-boot - hw_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h
+ * BlackFin (ADI) assembler restricted values by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc <mattw@lineo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_EZKIT533
+#include <asm/board/bf533_irq.h>
+#endif
+#ifdef CONFIG_STAMP
+#include <asm/board/bf533_irq.h>
+#endif
--- /dev/null
+/*
+ * U-boot - io-kernel.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the m68k architecture, we just read/write the
+ * memory location directly.
+ */
+/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
+ * two accesses to memory, which may be undesireable for some devices.
+ */
+#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
+#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
+#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+#define memset_io(a,b,c) memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+#define inb(addr) cf_inb((volatile unsigned char*)(addr))
+#define inw(addr) readw(addr)
+#define inl(addr) readl(addr)
+#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
+#define outw(x,addr) ((void) writew(x,addr))
+#define outl(x,addr) ((void) writel(x,addr))
+#define inb_p(addr) inb(addr)
+#define inw_p(addr) inw(addr)
+#define inl_p(addr) inl(addr)
+#define outb_p(x,addr) outb(x,addr)
+#define outw_p(x,addr) outw(x,addr)
+#define outl_p(x,addr) outl(x,addr)
+#define insb(port, addr, count) memcpy((void*)addr, (void*)port, count)
+#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
+#define insl(port, addr, count) memcpy((void*)addr, (void*)port, (4*count))
+#define outsb(port, addr, count) memcpy((void*)port, (void*)addr, count)
+#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
+#define outsl(port, addr, count) memcpy((void*)port, (void*)addr, (4*count))
+#define IO_SPACE_LIMIT 0xffff
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING 0
+#define IOMAP_NOCACHE_SER 1
+#define IOMAP_NOCACHE_NONSER 2
+#define IOMAP_WRITETHROUGH 3
+
+#ifndef __ASSEMBLY__
+extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
+extern void __iounmap(void *addr, unsigned long size);
+extern inline void *ioremap(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+extern void iounmap(void *addr);
+
+/* Nothing to do */
+
+extern void blkfin_inv_cache_all(void);
+
+#endif
+
+#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+#define dma_cache_wback(_start,_size) do { } while (0)
+#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+
+/* Pages to physical address... */
+#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
+#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
+
+#define mm_ptov(vaddr) ((void *) (vaddr))
+#define mm_vtop(vaddr) ((unsigned long) (vaddr))
+#define phys_to_virt(vaddr) ((void *) (vaddr))
+#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
+
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - io.h IO routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/* function prototypes for CF support */
+extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
+extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
+extern unsigned char cf_inb(volatile unsigned char *addr);
+extern void cf_outb(unsigned char val, volatile unsigned char* addr);
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the m68k architecture, we just read/write the
+ * memory location directly.
+ */
+
+
+#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
+#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
+#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
+
+#define writeb(b,addr) {((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");}
+#define writew(b,addr) {((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");}
+#define writel(b,addr) {((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");}
+
+#define memset_io(a,b,c) memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+
+#define inb_p(addr) readb((addr) + BF533_PCIIO_BASE)
+#define inb(addr) cf_inb((volatile unsigned char*)(addr))
+
+#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
+#define outb_p(x,addr) outb(x, (addr) + BF533_PCIIO_BASE)
+
+#define inw(addr) readw((addr) + BF533_PCIIO_BASE)
+#define inl(addr) readl((addr) + BF533_PCIIO_BASE)
+
+#define outw(x,addr) writew(x, (addr) + BF533_PCIIO_BASE)
+#define outl(x,addr) writel(x, (addr) + BF533_PCIIO_BASE)
+
+#define insb(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count)
+#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
+#define insl(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count))
+
+#define outsb(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count)
+#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
+#define outsl(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count))
+
+#define IO_SPACE_LIMIT 0xffff
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING 0
+#define IOMAP_NOCACHE_SER 1
+#define IOMAP_NOCACHE_NONSER 2
+#define IOMAP_WRITETHROUGH 3
+
+extern void *__ioremap(unsigned long physaddr, unsigned long size,
+ int cacheflag);
+extern void __iounmap(void *addr, unsigned long size);
+
+extern inline void *ioremap(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_nocache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_writethrough(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+extern inline void *ioremap_fullcache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+extern void iounmap(void *addr);
+
+extern void blkfin_inv_cache_all(void);
+#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+#define dma_cache_wback(_start,_size) do { } while (0)
+#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+
+#endif
+#endif
--- /dev/null
+/*
+ * U-boot - irq.h Interrupt related header file
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file was based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ *
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IRQ_H_
+#define _BLACKFIN_IRQ_H_
+
+#include <linux/config.h>
+#include <asm/cpu/bf533_irq.h>
+
+/*
+ * On the Blackfin, the interrupt structure allows remmapping of the hardware
+ * levels.
+ * - I'm going to assume that the H/W level is going to stay at the default
+ * settings. If someone wants to go through and abstart this out, feel free
+ * to mod the interrupt numbering scheme.
+ * - I'm abstracting the interrupts so that uClinux does not know anything
+ * about the H/W levels. If you want to change the H/W AND keep the abstracted
+ * levels that uClinux sees, you should be able to do most of it here.
+ * - I've left the "abstract" numbering sparce in case someone wants to pull the
+ * interrupts apart (just the TX/RX for the various devices)
+ */
+
+#define NR_IRQS SYS_IRQS
+/*
+ * "Generic" interrupt sources
+ */
+#define IRQ_SCHED_TIMER (8) /* interrupt source for scheduling timer */
+
+static __inline__ int irq_cannonicalize(int irq)
+{
+ return irq;
+}
+
+/*
+ * Machine specific interrupt sources.
+ *
+ * Adding an interrupt service routine for a source with this bit
+ * set indicates a special machine specific interrupt source.
+ * The machine specific files define these sources.
+ *
+ * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
+ * introduce unnecessary overhead.
+ *
+ * All interrupt handling is actually machine specific so it is better
+ * to use function pointers, as used by the Sparc port, and select the
+ * interrupt handling functions when initializing the kernel. This way
+ * we save some unnecessary overhead at run-time.
+ * 01/11/97 - Jes
+ */
+
+extern void (*mach_enable_irq) (unsigned int);
+extern void (*mach_disable_irq) (unsigned int);
+extern int sys_request_irq(unsigned int,
+ void (*)(int, void *, struct pt_regs *),
+ unsigned long, const char *, void *);
+extern void sys_free_irq(unsigned int, void *);
+
+/*
+ * various flags for request_irq() - the Amiga now uses the standard
+ * mechanism like all other architectures - SA_INTERRUPT and SA_SHIRQ
+ * are your friends.
+ */
+#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */
+#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */
+#define IRQ_FLG_FAST (0x0004)
+#define IRQ_FLG_SLOW (0x0008)
+#define IRQ_FLG_STD (0x8000) /* internally used */
+
+/*
+ * This structure is used to chain together the ISRs for a particular
+ * interrupt source (if it supports chaining).
+ */
+typedef struct irq_node {
+ void (*handler) (int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+ struct irq_node *next;
+} irq_node_t;
+
+/*
+ * This structure has only 4 elements for speed reasons
+ */
+typedef struct irq_handler {
+ void (*handler) (int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+} irq_handler_t;
+
+/* count of spurious interrupts */
+extern volatile unsigned int num_spurious;
+
+/*
+ * This function returns a new irq_node_t
+ */
+extern irq_node_t *new_irq_node(void);
+
+/*
+ * Some drivers want these entry points
+ */
+#define enable_irq(x) (mach_enable_irq ? (*mach_enable_irq)(x) : 0)
+#define disable_irq(x) (mach_disable_irq ? (*mach_disable_irq)(x) : 0)
+
+#define enable_irq_nosync(x) enable_irq(x)
+#define disable_irq_nosync(x) disable_irq(x)
+
+#endif
--- /dev/null
+/*
+ * U-boot - linkage.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <linux/config.h>
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#define asmlinkage CPP_ASMLINKAGE
+
+#define SYMBOL_NAME_STR(X) #X
+#define SYMBOL_NAME(X) X
+#ifdef __STDC__
+#define SYMBOL_NAME_LABEL(X) X##:
+#else
+#define SYMBOL_NAME_LABEL(X) X:
+#endif
+
+#define __ALIGN .align 4
+#define __ALIGN_STR ".align 4"
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN __ALIGN
+#define ALIGN_STR __ALIGN_STR
+
+#define ENTRY(name) \
+ .globl SYMBOL_NAME(name); \
+ ALIGN; \
+ SYMBOL_NAME_LABEL(name)
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - machdep.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_MACHDEP_H
+#define _BLACKFIN_MACHDEP_H
+
+/* Machine dependent initial routines:
+ *
+ * Based on include/asm-m68knommu/machdep.h
+ * For blackfin, just now we only have bfin, so they'd point to the default bfin
+ *
+ */
+
+struct pt_regs;
+struct kbd_repeat;
+struct mktime;
+struct hwclk_time;
+struct gendisk;
+struct buffer_head;
+
+extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
+
+/* machine dependent keyboard functions */
+extern int (*mach_keyb_init) (void);
+extern int (*mach_kbdrate) (struct kbd_repeat *);
+extern void (*mach_kbd_leds) (unsigned int);
+
+/* machine dependent irq functions */
+extern void (*mach_init_IRQ) (void);
+extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *);
+extern int (*mach_request_irq) (unsigned int irq,
+ void (*handler) (int, void *,
+ struct pt_regs *),
+ unsigned long flags, const char *devname,
+ void *dev_id);
+extern void (*mach_free_irq) (unsigned int irq, void *dev_id);
+extern void (*mach_get_model) (char *model);
+extern int (*mach_get_hardware_list) (char *buffer);
+extern int (*mach_get_irq_list) (char *buf);
+extern void (*mach_process_int) (int irq, struct pt_regs * fp);
+
+/* machine dependent timer functions */
+extern unsigned long (*mach_gettimeoffset) (void);
+extern void (*mach_gettod) (int *year, int *mon, int *day, int *hour,
+ int *min, int *sec);
+extern int (*mach_hwclk) (int, struct hwclk_time *);
+extern int (*mach_set_clock_mmss) (unsigned long);
+extern void (*mach_reset) (void);
+extern void (*mach_halt) (void);
+extern void (*mach_power_off) (void);
+extern unsigned long (*mach_hd_init) (unsigned long, unsigned long);
+extern void (*mach_hd_setup) (char *, int *);
+extern long mach_max_dma_address;
+extern void (*mach_floppy_setup) (char *, int *);
+extern void (*mach_floppy_eject) (void);
+extern void (*mach_heartbeat) (int);
+extern void (*mach_l2_flush) (int);
+extern int mach_sysrq_key;
+extern int mach_sysrq_shift_state;
+extern int mach_sysrq_shift_mask;
+extern char *mach_sysrq_xlate;
+
+#ifdef CONFIG_UCLINUX
+extern void config_BSP(char *command, int len);
+extern void (*mach_tick) (void);
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - mem_init.h Header file for memory initialization
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E )
+ #if ( CONFIG_SCLK_HZ > 119402985 )
+ #define SDRAM_tRP TRP_2
+ #define SDRAM_tRP_num 2
+ #define SDRAM_tRAS TRAS_7
+ #define SDRAM_tRAS_num 7
+ #define SDRAM_tRCD TRCD_2
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
+ #define SDRAM_tRP TRP_2
+ #define SDRAM_tRP_num 2
+ #define SDRAM_tRAS TRAS_6
+ #define SDRAM_tRAS_num 6
+ #define SDRAM_tRCD TRCD_2
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
+ #define SDRAM_tRP TRP_2
+ #define SDRAM_tRP_num 2
+ #define SDRAM_tRAS TRAS_5
+ #define SDRAM_tRAS_num 5
+ #define SDRAM_tRCD TRCD_2
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 )
+ #define SDRAM_tRP TRP_2
+ #define SDRAM_tRP_num 2
+ #define SDRAM_tRAS TRAS_4
+ #define SDRAM_tRAS_num 4
+ #define SDRAM_tRCD TRCD_2
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
+ #define SDRAM_tRP TRP_2
+ #define SDRAM_tRP_num 2
+ #define SDRAM_tRAS TRAS_3
+ #define SDRAM_tRAS_num 3
+ #define SDRAM_tRCD TRCD_2
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
+ #define SDRAM_tRP TRP_1
+ #define SDRAM_tRP_num 1
+ #define SDRAM_tRAS TRAS_4
+ #define SDRAM_tRAS_num 3
+ #define SDRAM_tRCD TRCD_1
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 )
+ #define SDRAM_tRP TRP_1
+ #define SDRAM_tRP_num 1
+ #define SDRAM_tRAS TRAS_3
+ #define SDRAM_tRAS_num 3
+ #define SDRAM_tRCD TRCD_1
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 )
+ #define SDRAM_tRP TRP_1
+ #define SDRAM_tRP_num 1
+ #define SDRAM_tRAS TRAS_2
+ #define SDRAM_tRAS_num 2
+ #define SDRAM_tRCD TRCD_1
+ #define SDRAM_tWR TWR_2
+ #endif
+ #if ( CONFIG_SCLK_HZ <= 29850746 )
+ #define SDRAM_tRP TRP_1
+ #define SDRAM_tRP_num 1
+ #define SDRAM_tRAS TRAS_1
+ #define SDRAM_tRAS_num 1
+ #define SDRAM_tRCD TRCD_1
+ #define SDRAM_tWR TWR_2
+ #endif
+#endif
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75)
+ /*SDRAM INFORMATION: */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
+ #define SDRAM_CL CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
+ /*SDRAM INFORMATION: */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
+ #define SDRAM_CL CL_2
+#endif
+
+#if ( CONFIG_MEM_SIZE == 128 )
+ #define SDRAM_SIZE EBSZ_128
+#endif
+#if ( CONFIG_MEM_SIZE == 64 )
+ #define SDRAM_SIZE EBSZ_64
+#endif
+#if ( CONFIG_MEM_SIZE == 32 )
+ #define SDRAM_SIZE EBSZ_32
+#endif
+#if ( CONFIG_MEM_SIZE == 16 )
+ #define SDRAM_SIZE EBSZ_16
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 11 )
+ #define SDRAM_WIDTH EBCAW_11
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 10 )
+ #define SDRAM_WIDTH EBCAW_10
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 9 )
+ #define SDRAM_WIDTH EBCAW_9
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 8 )
+ #define SDRAM_WIDTH EBCAW_8
+#endif
+
+#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE
+
+/* Equation from section 17 (p17-46) of BF533 HRM */
+#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+
+/* Enable SCLK Out */
+#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
+
+#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) )
+#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+
+#if (flash_EBIU_AMBCTL_TT > 3 )
+ #define flash_EBIU_AMBCTL0_TT B0TT_4
+#endif
+#if (flash_EBIU_AMBCTL_TT == 3 )
+ #define flash_EBIU_AMBCTL0_TT B0TT_3
+#endif
+#if (flash_EBIU_AMBCTL_TT == 2 )
+ #define flash_EBIU_AMBCTL0_TT B0TT_2
+#endif
+#if (flash_EBIU_AMBCTL_TT < 2 )
+ #define flash_EBIU_AMBCTL0_TT B0TT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_ST > 3 )
+ #define flash_EBIU_AMBCTL0_ST B0ST_4
+#endif
+#if (flash_EBIU_AMBCTL_ST == 3 )
+ #define flash_EBIU_AMBCTL0_ST B0ST_3
+#endif
+#if (flash_EBIU_AMBCTL_ST == 2 )
+ #define flash_EBIU_AMBCTL0_ST B0ST_2
+#endif
+#if (flash_EBIU_AMBCTL_ST < 2 )
+ #define flash_EBIU_AMBCTL0_ST B0ST_1
+#endif
+
+#if (flash_EBIU_AMBCTL_HT > 2 )
+ #define flash_EBIU_AMBCTL0_HT B0HT_3
+#endif
+#if (flash_EBIU_AMBCTL_HT == 2 )
+ #define flash_EBIU_AMBCTL0_HT B0HT_2
+#endif
+#if (flash_EBIU_AMBCTL_HT == 1 )
+ #define flash_EBIU_AMBCTL0_HT B0HT_1
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
+ #define flash_EBIU_AMBCTL0_HT B0HT_0
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
+ #define flash_EBIU_AMBCTL0_HT B0HT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_WAT > 14)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_15
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 14)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_14
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 13)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_13
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 12)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_12
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 11)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_11
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 10)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_10
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 9)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_9
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 8)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_8
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 7)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_7
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 6)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_6
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 5)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_5
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 4)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_4
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 3)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_3
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 2)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_2
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 1)
+ #define flash_EBIU_AMBCTL0_WAT B0WAT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_RAT > 14)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_15
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 14)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_14
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 13)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_13
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 12)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_12
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 11)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_11
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 10)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_10
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 9)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_9
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 8)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_8
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 7)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_7
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 6)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_6
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 5)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_5
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 4)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_4
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 3)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_3
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 2)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_2
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 1)
+ #define flash_EBIU_AMBCTL0_RAT B0RAT_1
+#endif
+
+#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
--- /dev/null
+/*
+ * U-boot - page.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_PAGE_H
+#define _BLACKFIN_PAGE_H
+
+#include <linux/config.h>
+
+/* PAGE_SHIFT determines the page size */
+
+#define PAGE_SHIFT (12)
+#define PAGE_SIZE (4096)
+#define PAGE_MASK (~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+
+#include <asm/setup.h>
+
+#if PAGE_SHIFT < 13
+#define KTHREAD_SIZE (8192)
+#else
+#define KTHREAD_SIZE PAGE_SIZE
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
+#define free_user_page(page, addr) free_page(addr)
+
+#define clear_page(page) memset((page), 0, PAGE_SIZE)
+#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
+
+#define clear_user_page(page, vaddr) clear_page(page)
+#define copy_user_page(to, from, vaddr) copy_page(to, from)
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct {
+ unsigned long pte;
+} pte_t;
+typedef struct {
+ unsigned long pmd[16];
+} pmd_t;
+typedef struct {
+ unsigned long pgd;
+} pgd_t;
+typedef struct {
+ unsigned long pgprot;
+} pgprot_t;
+
+#define pte_val(x) ((x).pte)
+#define pmd_val(x) ((&x)->pmd[0])
+#define pgd_val(x) ((x).pgd)
+#define pgprot_val(x) ((x).pgprot)
+
+#define __pte(x) ((pte_t) { (x) } )
+#define __pmd(x) ((pmd_t) { (x) } )
+#define __pgd(x) ((pgd_t) { (x) } )
+#define __pgprot(x) ((pgprot_t) { (x) } )
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
+
+/* Pure 2^n version of get_order */
+extern __inline__ int get_order(unsigned long size)
+{
+ int order;
+
+ size = (size - 1) >> (PAGE_SHIFT - 1);
+ order = -1;
+ do {
+ size >>= 1;
+ order++;
+ } while (size);
+ return order;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#include <asm/page_offset.h>
+
+#define PAGE_OFFSET (PAGE_OFFSET_RAW)
+
+#ifndef __ASSEMBLY__
+
+#define __pa(vaddr) virt_to_phys((void *)vaddr)
+#define __va(paddr) phys_to_virt((unsigned long)paddr)
+
+#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
+#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
+#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
+
+#define BUG() do { \
+ \
+ while (1); /* dead-loop */ \
+} while (0)
+
+#define PAGE_BUG(page) do { \
+ BUG(); \
+} while (0)
+
+#endif
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - page_offset.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Changes made by Akbar Hussain April 10, 2001
+ */
+
+#include <linux/config.h>
+
+/* This handles the memory map.. */
+
+#ifdef CONFIG_BLACKFIN
+#define PAGE_OFFSET_RAW 0x00000000
+#endif
--- /dev/null
+/*
+ * U-boot - posix_types.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H
+#define __ARCH_BLACKFIN_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef __FD_CLR
+#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef __FD_ISSET
+#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef __FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif
--- /dev/null
+/*
+ * U-boot - processor.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * include/asm-m68k/processor.h
+ * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN
+ * Copyright (C) 1995 Hamish Macdonald
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_BLACKFIN_PROCESSOR_H
+#define __ASM_BLACKFIN_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#include <linux/config.h>
+#include <asm/segment.h>
+#include <asm/ptrace.h>
+#include <asm/current.h>
+
+extern inline unsigned long rdusp(void)
+{
+ unsigned long usp;
+
+ __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
+ return usp;
+}
+
+extern inline void wrusp(unsigned long usp)
+{
+ __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
+}
+
+/*
+ * User space process size: 3.75GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.
+ */
+#define TASK_SIZE (0xF0000000UL)
+
+/*
+ * Bus types
+ */
+#define EISA_bus 0
+#define MCA_bus 0
+
+/* There is no pc register avaliable for BLACKFIN, so we are going to get
+ * it indirectly
+ */
+
+#if 0
+inline unsigned long obtain_pc_indirectly(void)
+{
+ unsigned long pc;
+ __asm__ __volatile__("%0 = rets;\n":"=d"(pc));
+ return (pc - 4); /* call pcrel24 is 4 bytes long */
+}
+#endif
+
+/*
+ * if you change this structure, you must change the code and offsets
+ * in m68k/machasm.S
+ */
+
+struct thread_struct {
+ unsigned long ksp; /* kernel stack pointer */
+ unsigned long usp; /* user stack pointer */
+ unsigned short seqstat; /* saved status register */
+ unsigned long esp0; /* points to SR of stack frame pt_regs */
+ unsigned long pc; /* instruction pointer */
+};
+
+#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
+
+#define INIT_THREAD { \
+ sizeof(init_stack) + (unsigned long) init_stack, 0, \
+ PS_S, 0\
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ *
+ * pass the data segment into user programs if it exists,
+ * it can't hurt anything as far as I can tell
+ */
+#define start_thread(_regs, _pc, _usp) \
+do { \
+ set_fs(USER_DS); /* reads from user space */ \
+ (_regs)->pc = (_pc); \
+ if (current->mm) \
+ (_regs)->r5 = current->mm->start_data; \
+ (_regs)->seqstat &= ~0x0c00; \
+ wrusp(_usp); \
+ /* Adde by HuTao, May 26, 2003 3:39PM */\
+ if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\
+ (_regs)->ipend = 0x0;\
+} while(0)
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+static inline void release_thread(struct task_struct *dead_task)
+{
+}
+
+extern int kernel_thread(int (*fn) (void *), void *arg,
+ unsigned long flags);
+
+#define copy_segments(tsk, mm) do { } while (0)
+#define release_segments(mm) do { } while (0)
+#define forget_segments() do { } while (0)
+
+/*
+ * Free current thread data structures etc..
+ */
+static inline void exit_thread(void)
+{
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+extern inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+ extern void scheduling_functions_start_here(void);
+ extern void scheduling_functions_end_here(void);
+ return 0;
+}
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk) \
+ ({ \
+ unsigned long eip = 0; \
+ if ((tsk)->thread.esp0 > PAGE_SIZE && \
+ MAP_NR((tsk)->thread.esp0) < max_mapnr) \
+ eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
+ eip; })
+#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
+#define THREAD_SIZE (2*PAGE_SIZE)
+
+/* Allocation and freeing of basic task resources. */
+#define alloc_task_struct() \
+ ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define free_task_struct(p) free_pages((unsigned long)(p),1)
+#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
+
+#define init_task (init_task_union.task)
+#define init_stack (init_task_union.stack)
+
+#endif
--- /dev/null
+/*
+ * U-boot - ptrace.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_PTRACE_H
+#define _BLACKFIN_PTRACE_H
+
+#define NEW_PT_REGS
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ * 0 - 7 are data registers R0-R7
+ * 8 - 15 are address registers P0-P7
+ * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
+ * 32 - 33 A registers A0 & A1
+ * 34 - status register
+ *
+ * We follows above, except:
+ * 32-33 --- Low 32-bit of A0&1
+ * 34-35 --- High 8-bit of A0&1
+ */
+
+#if defined(NEW_PT_REGS)
+
+#define PT_IPEND 0
+#define PT_SYSCFG (PT_IPEND+4)
+#define PT_SEQSTAT (PT_SYSCFG+4)
+#define PT_RETE (PT_SEQSTAT+4)
+#define PT_RETN (PT_RETE+4)
+#define PT_RETX (PT_RETN+4)
+#define PT_RETI (PT_RETX+4)
+#define PT_PC PT_RETI
+#define PT_RETS (PT_RETI+4)
+#define PT_RESERVED (PT_RETS+4)
+#define PT_ASTAT (PT_RESERVED+4)
+#define PT_LB1 (PT_ASTAT+4)
+#define PT_LB0 (PT_LB1+4)
+#define PT_LT1 (PT_LB0+4)
+#define PT_LT0 (PT_LT1+4)
+#define PT_LC1 (PT_LT0+4)
+#define PT_LC0 (PT_LC1+4)
+#define PT_A1W (PT_LC0+4)
+#define PT_A1X (PT_A1W+4)
+#define PT_A0W (PT_A1X+4)
+#define PT_A0X (PT_A0W+4)
+#define PT_B3 (PT_A0X+4)
+#define PT_B2 (PT_B3+4)
+#define PT_B1 (PT_B2+4)
+#define PT_B0 (PT_B1+4)
+#define PT_L3 (PT_B0+4)
+#define PT_L2 (PT_L3+4)
+#define PT_L1 (PT_L2+4)
+#define PT_L0 (PT_L1+4)
+#define PT_M3 (PT_L0+4)
+#define PT_M2 (PT_M3+4)
+#define PT_M1 (PT_M2+4)
+#define PT_M0 (PT_M1+4)
+#define PT_I3 (PT_M0+4)
+#define PT_I2 (PT_I3+4)
+#define PT_I1 (PT_I2+4)
+#define PT_I0 (PT_I1+4)
+#define PT_USP (PT_I0+4)
+#define PT_FP (PT_USP+4)
+#define PT_P5 (PT_FP+4)
+#define PT_P4 (PT_P5+4)
+#define PT_P3 (PT_P4+4)
+#define PT_P2 (PT_P3+4)
+#define PT_P1 (PT_P2+4)
+#define PT_P0 (PT_P1+4)
+#define PT_R7 (PT_P0+4)
+#define PT_R6 (PT_R7+4)
+#define PT_R5 (PT_R6+4)
+#define PT_R4 (PT_R5+4)
+#define PT_R3 (PT_R4+4)
+#define PT_R2 (PT_R3+4)
+#define PT_R1 (PT_R2+4)
+#define PT_R0 (PT_R1+4)
+#define PT_ORIG_R0 (PT_R0+4)
+#define PT_SR PT_SEQSTAT
+
+#else
+/*
+ * Here utilize blackfin : dpregs = [pregs + imm16s4]
+ * [pregs + imm16s4] = dpregs
+ * to access defferent saved reg in stack
+ */
+#define PT_R3 0
+#define PT_R4 4
+#define PT_R2 8
+#define PT_R1 12
+#define PT_P5 16
+#define PT_P4 20
+#define PT_P3 24
+#define PT_P2 28
+#define PT_P1 32
+#define PT_P0 36
+#define PT_R7 40
+#define PT_R6 44
+#define PT_R5 48
+#define PT_PC 52
+#define PT_SEQSTAT 56 /* so-called SR reg */
+#define PT_SR PT_SEQSTAT
+#define PT_ASTAT 60
+#define PT_RETS 64
+#define PT_A1w 68
+#define PT_A0w 72
+#define PT_A1x 76
+#define PT_A0x 80
+#define PT_ORIG_R0 84
+#define PT_R0 88
+#define PT_USP 92
+#define PT_FP 96
+#define PT_SP 100
+
+/* Added by HuTao, May26 2003 3:18PM */
+#define PT_IPEND 100
+
+/* Add SYSCFG register for single stepping support */
+#define PT_SYSCFG 104
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+#if defined(NEW_PT_REGS)
+/* this struct defines the way the registers are stored on the
+ * stack during a system call.
+ */
+struct pt_regs {
+ long ipend;
+ long syscfg;
+ long seqstat;
+ long rete;
+ long retn;
+ long retx;
+ long pc;
+ long rets;
+ long reserved;
+ long astat;
+ long lb1;
+ long lb0;
+ long lt1;
+ long lt0;
+ long lc1;
+ long lc0;
+ long a1w;
+ long a1x;
+ long a0w;
+ long a0x;
+ long b3;
+ long b2;
+ long b1;
+ long b0;
+ long l3;
+ long l2;
+ long l1;
+ long l0;
+ long m3;
+ long m2;
+ long m1;
+ long m0;
+ long i3;
+ long i2;
+ long i1;
+ long i0;
+ long usp;
+ long fp;
+ long p5;
+ long p4;
+ long p3;
+ long p2;
+ long p1;
+ long p0;
+ long r7;
+ long r6;
+ long r5;
+ long r4;
+ long r3;
+ long r2;
+ long r1;
+ long r0;
+ long orig_r0;
+};
+
+#else
+/* now we don't know what regs the system call will use */
+struct pt_regs {
+ long r3;
+ long r4;
+ long r2;
+ long r1;
+ long p5;
+ long p4;
+ long p3;
+ long p2;
+ long p1;
+ long p0;
+ long r7;
+ long r6;
+ long r5;
+ unsigned long pc;
+ unsigned long seqstat;
+ unsigned long astat;
+ unsigned long rets;
+ long a1w;
+ long a0w;
+ long a1x;
+ long a0x;
+ long orig_r0;
+ long r0;
+ long usp;
+ long fp;
+/*
+ * Added for supervisor/user mode switch.
+ *
+ * HuTao May26 03 3:23PM
+ */
+ long ipend;
+ long syscfg;
+};
+
+#endif
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13 /* ptrace signal */
+
+#ifdef __KERNEL__
+
+#ifndef PS_S
+#define PS_S (0x0c00)
+
+/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode
+ * 00: user
+ * 01: supervisor
+ * 1x: debug
+ */
+
+#define PS_M (0x1000) /* I am not sure why this is required here Akbar */
+#endif
+
+#define user_mode(regs) (!((regs)->seqstat & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+#endif
+#endif
+#endif
--- /dev/null
+/*
+ * U-boot - segment.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SEGMENT_H
+#define _BLACKFIN_SEGMENT_H
+
+/* define constants */
+typedef unsigned long mm_segment_t; /* domain register */
+
+#define KERNEL_CS 0x0
+#define KERNEL_DS 0x0
+#define __KERNEL_CS 0x0
+#define __KERNEL_DS 0x0
+
+#define USER_CS 0x1
+#define USER_DS 0x1
+#define __USER_CS 0x1
+#define __USER_DS 0x1
+
+#define get_ds() (KERNEL_DS)
+#define get_fs() (__USER_DS)
+#define segment_eq(a,b) ((a) == (b))
+#define set_fs(val)
+
+#endif
--- /dev/null
+/*
+ * U-boot - setup.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * asm/setup.h -- Definition of the Linux/Blackfin setup information
+ * Copyright Lineo, Inc 2001 Tony Kou
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SETUP_H
+#define _BLACKFIN_SETUP_H
+
+#include <linux/config.h>
+
+/*
+ * Linux/Blackfin Architectures
+ */
+
+#define MACH_BFIN 1
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+extern unsigned long blackfin_machtype;
+#endif
+
+#if defined(CONFIG_BFIN)
+#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN)
+#endif
+
+#ifndef MACH_TYPE
+#define MACH_TYPE (blackfin_machtype)
+#endif
+
+#endif
+
+/*
+ * CPU, FPU and MMU types
+ *
+ * Note: we don't need now:
+ *
+ */
+
+#ifndef __ASSEMBLY__
+extern unsigned long blackfin_cputype;
+#ifdef CONFIG_VME
+extern unsigned long vme_brdtype;
+#endif
+
+/*
+ * Miscellaneous
+ */
+
+#define NUM_MEMINFO 4
+#define CL_SIZE 256
+
+extern int blackfin_num_memory; /* # of memory blocks found (and used) */
+extern int blackfin_realnum_memory; /* real # of memory blocks found */
+extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */
+
+struct mem_info {
+ unsigned long addr; /* physical address of memory chunk */
+ unsigned long size; /* length of memory chunk (in bytes) */
+};
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - setup.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SHARED_RESOURCES_H_
+#define _SHARED_RESOURCES_H_
+
+void swap_to(int device_id);
+
+#define FLASH 0
+#define ETHERNET 1
+
+#endif /* _SHARED_RESOURCES_H_ */
--- /dev/null
+/*
+ * U-boot - string.h String functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Changed by Lineo Inc. May 2001 */
+
+#ifndef _BLACKFINNOMMU_STRING_H_
+#define _BLACKFINNOMMU_STRING_H_
+
+#ifdef __KERNEL__ /* only set these up for kernel code */
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/cpu/defBF533.h>
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRNCMP
+#define __HAVE_ARCH_MEMCPY
+
+extern char *strcpy(char *dest, const char *src);
+extern char *strncpy(char *dest, const char *src, size_t n);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, size_t count);
+extern void * memcpy(void * dest,const void *src,size_t count);
+extern void *memset(void *s, int c, size_t count);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+
+#else /* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY 1
+#define __HAVE_ARCH_STRNCPY 1
+#define __HAVE_ARCH_STRCAT 1
+#define __HAVE_ARCH_STRNCAT 1
+#define __HAVE_ARCH_STRCMP 1
+#define __HAVE_ARCH_STRNCMP 1
+#define __HAVE_ARCH_STRNICMP 1
+#define __HAVE_ARCH_STRCHR 1
+#define __HAVE_ARCH_STRRCHR 1
+#define __HAVE_ARCH_STRSTR 1
+#define __HAVE_ARCH_STRLEN 1
+#define __HAVE_ARCH_STRNLEN 1
+#define __HAVE_ARCH_MEMSET 1
+#define __HAVE_ARCH_MEMCPY 1
+#define __HAVE_ARCH_MEMMOVE 1
+#define __HAVE_ARCH_MEMSCAN 1
+#define __HAVE_ARCH_MEMCMP 1
+#define __HAVE_ARCH_MEMCHR 1
+#define __HAVE_ARCH_STRTOK 1
+
+#endif /* KERNEL */
+
+#endif /* _BLACKFIN_STRING_H_ */
--- /dev/null
+/*
+ * U-boot - system.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SYSTEM_H
+#define _BLACKFIN_SYSTEM_H
+
+#include <linux/config.h> /* get configuration macros */
+#include <asm/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/segment.h>
+#include <asm/entry.h>
+
+#define prepare_to_switch() do { } while(0)
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing. This
+ * also clears the TS-flag if the task we switched to has used the
+ * math co-processor latest.
+ *
+ * 05/25/01 - Tony Kou (tonyko@lineo.ca)
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2003 Metrowerks (www.metrowerks.com)
+ */
+
+asmlinkage void resume(void);
+
+#define switch_to(prev,next,last) { \
+ void *_last; \
+ __asm__ __volatile__( \
+ "r0 = %1;\n\t" \
+ "r1 = %2;\n\t" \
+ "call resume;\n\t" \
+ "%0 = r0;\n\t" \
+ : "=d" (_last) \
+ : "d" (prev), \
+ "d" (next) \
+ : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
+ (last) = _last; \
+}
+
+/* Force kerenl switch to user mode -- Steven Chen */
+#define switch_to_user_mode() { \
+ __asm__ __volatile__( \
+ "call kernel_to_user_mode;\n\t" \
+ :: \
+ : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
+}
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define __sti() { \
+ __asm__ __volatile__ ( \
+ "r3 = %0;" \
+ "sti r3;" \
+ ::"m"(irq_flags):"R3"); \
+}
+
+#define __cli() { \
+ __asm__ __volatile__ ( \
+ "cli r3;" \
+ :::"R3"); \
+}
+
+#define __save_flags(x) { \
+ __asm__ __volatile__ ( \
+ "cli r3;" \
+ "%0 = r3;" \
+ "sti r3;" \
+ ::"m"(x):"R3"); \
+}
+
+#define __save_and_cli(x) { \
+ __asm__ __volatile__ ( \
+ "cli r3;" \
+ "%0 = r3;" \
+ ::"m"(x):"R3"); \
+}
+
+#define __restore_flags(x) { \
+ __asm__ __volatile__ ( \
+ "r3 = %0;" \
+ "sti r3;" \
+ ::"m"(x):"R3"); \
+}
+
+/* For spinlocks etc */
+#define local_irq_save(x) __save_and_cli(x)
+#define local_irq_restore(x) __restore_flags(x)
+#define local_irq_disable() __cli()
+#define local_irq_enable() __sti()
+
+#define cli() __cli()
+#define sti() __sti()
+#define save_flags(x) __save_flags(x)
+#define restore_flags(x) __restore_flags(x)
+#define save_and_cli(x) __save_and_cli(x)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop() asm volatile ("nop;\n\t"::)
+#define mb() asm volatile ("" : : :"memory")
+#define rmb() asm volatile ("" : : :"memory")
+#define wmb() asm volatile ("" : : :"memory")
+#define set_rmb(var, value) do { xchg(&var, value); } while (0)
+#define set_mb(var, value) set_rmb(var, value)
+#define set_wmb(var, value) do { var = value; wmb(); } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb() mb()
+#define smp_rmb() rmb()
+#define smp_wmb() wmb()
+#else
+#define smp_mb() barrier()
+#define smp_rmb() barrier()
+#define smp_wmb() barrier()
+#endif
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define tas(ptr) (xchg((ptr),1))
+
+struct __xchg_dummy {
+ unsigned long a[100];
+};
+#define __xg(x) ((volatile struct __xchg_dummy *)(x))
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+ int size)
+{
+ unsigned long tmp;
+ unsigned long flags = 0;
+
+ save_and_cli(flags);
+
+ switch (size) {
+ case 1:
+ __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+ break;
+ case 2:
+ __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+ break;
+ case 4:
+ __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+ break;
+ }
+ restore_flags(flags);
+ return tmp;
+}
+
+/* Depend on whether Blackfin has hard reset function */
+/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */
+#define HARD_RESET_NOW() ({})
+
+#endif /* _BLACKFIN_SYSTEM_H */
--- /dev/null
+/*
+ * U-boot - traps.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/include/asm/traps.h
+ * Copyright (C) 1993 Hamish Macdonald
+ * Lineo, Inc Jul 2001 Tony Kou
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ */
+
+#ifndef _BLACKFIN_TRAPS_H
+#define _BLACKFIN_TRAPS_H
+
+#ifndef __ASSEMBLY__
+typedef void (*e_vector) (void);
+extern e_vector vectors[];
+#endif
+
+#define VEC_SYS (0)
+#define VEC_EXCPT01 (1)
+#define VEC_EXCPT02 (2)
+#define VEC_EXCPT03 (3)
+#define VEC_EXCPT04 (4)
+#define VEC_EXCPT05 (5)
+#define VEC_EXCPT06 (6)
+#define VEC_EXCPT07 (7)
+#define VEC_EXCPT08 (8)
+#define VEC_EXCPT09 (9)
+#define VEC_EXCPT10 (10)
+#define VEC_EXCPT11 (11)
+#define VEC_EXCPT12 (12)
+#define VEC_EXCPT13 (13)
+#define VEC_EXCPT14 (14)
+#define VEC_EXCPT15 (15)
+#define VEC_STEP (16)
+#define VEC_OVFLOW (17)
+#define VEC_UNDEF_I (33)
+#define VEC_ILGAL_I (34)
+#define VEC_CPLB_VL (35)
+#define VEC_MISALI_D (36)
+#define VEC_UNCOV (37)
+#define VEC_CPLB_M (38)
+#define VEC_CPLB_MHIT (39)
+#define VEC_WATCH (40)
+#define VEC_ISTRU_VL (41)
+#define VEC_MISALI_I (42)
+#define VEC_CPLB_I_VL (43)
+#define VEC_CPLB_I_M (44)
+#define VEC_CPLB_I_MHIT (45)
+#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
+
+#define VECOFF(vec) ((vec)<<2)
+
+#ifndef __ASSEMBLY__
+
+/* Status register bits */
+#define PS_T (0x8000)
+#define PS_S (0x0c00) /* Supervisor mode = 0b01 */
+#define PS_D (0x0c00) /* Debug mode = 0b1x */
+#define PS_M (0x1000)
+#define PS_C (0x0001)
+
+#endif
+#endif
--- /dev/null
+/*
+ * U-boot - types.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_TYPES_H
+#define _BLACKFIN_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue. However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+/* HK0617 -- Changes to unsigned long temporarily */
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - u-boot.h Structure declarations for board specific data
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_ 1
+
+typedef struct bd_info {
+ int bi_baudrate; /* serial console baudrate */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
+ unsigned long bi_arch_number; /* unique id for this board */
+ unsigned long bi_boot_params; /* where this board expects params */
+ unsigned long bi_memstart; /* start of DRAM memory */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+} bd_t;
+
+#define bi_env_data bi_env->data
+#define bi_env_crc bi_env->crc
+
+#endif /* _U_BOOT_H_ */
--- /dev/null
+/*
+ * U-boot - uaccess.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * Based on: include/asm-m68knommu/uaccess.h
+ * Changes made by Lineo Inc. May 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_UACCESS_H
+#define __BLACKFIN_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <asm/segment.h>
+#include <asm/errno.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+/* We let the MMU do all checking */
+static inline int access_ok(int type, const void *addr, unsigned long size)
+{
+ return ((unsigned long) addr < 0x10f00000); /* need final decision - Tony */
+}
+
+static inline int verify_area(int type, const void *addr,
+ unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue. No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path. This means when everything is well,
+ * we don't even have to jump over them. Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+ unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern unsigned long search_exception_table(unsigned long);
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ */
+
+#define put_user(x, ptr) \
+({ \
+ int __pu_err = 0; \
+ typeof(*(ptr)) __pu_val = (x); \
+ switch (sizeof (*(ptr))) { \
+ case 1: \
+ __put_user_asm(__pu_err, __pu_val, ptr, B); \
+ break; \
+ case 2: \
+ __put_user_asm(__pu_err, __pu_val, ptr, W); \
+ break; \
+ case 4: \
+ __put_user_asm(__pu_err, __pu_val, ptr, ); \
+ break; \
+ default: \
+ __pu_err = __put_user_bad(); \
+ break; \
+ } \
+ __pu_err; \
+})
+/*
+ * [pregs] = dregs ==> 32bits
+ * H[pregs] = dregs ==> 16bits
+ * B[pregs] = dregs ==> 8 bits
+ */
+
+#define __put_user(x, ptr) put_user(x, ptr)
+
+static inline int bad_user_access_length(void)
+{
+ panic("bad_user_access_length");
+ return -1;
+}
+
+#define __put_user_bad() (bad_user_access_length(), (-EFAULT))
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define __put_user_asm(err,x,ptr,bhw) \
+ __asm__ (#bhw"[%1] = %0;\n\t" \
+ : /* no outputs */ \
+ :"d" (x),"a" (__ptr(ptr)) : "memory")
+
+#define get_user(x, ptr) \
+({ \
+ int __gu_err = 0; \
+ typeof(*(ptr)) __gu_val = 0; \
+ switch (sizeof(*(ptr))) { \
+ case 1: \
+ __get_user_asm(__gu_err, __gu_val, ptr, B, "=d",(Z)); \
+ break; \
+ case 2: \
+ __get_user_asm(__gu_err, __gu_val, ptr, W, "=r",(Z)); \
+ break; \
+ case 4: \
+ __get_user_asm(__gu_err, __gu_val, ptr, , "=r",); \
+ break; \
+ default: \
+ __gu_val = 0; \
+ __gu_err = __get_user_bad(); \
+ break; \
+ } \
+ (x) = __gu_val; \
+ __gu_err; \
+})
+
+/* dregs = [pregs] ==> 32bits
+ * H[pregs] ==> 16bits
+ * B[pregs] ==> 8 bits
+ */
+
+#define __get_user(x, ptr) get_user(x, ptr)
+#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
+
+#define __get_user_asm(err,x,ptr,bhw,reg,option) \
+ __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \
+ : "=d" (x) \
+ : "a" (__ptr(ptr)))
+
+#define copy_from_user(to, from, n) (memcpy(to, from, n), 0)
+#define copy_to_user(to, from, n) (memcpy(to, from, n), 0)
+
+#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
+#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
+
+#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; })
+#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; })
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+
+static inline long strncpy_from_user(char *dst, const char *src,
+ long count)
+{
+ char *tmp;
+ strncpy(dst, src, count);
+ for (tmp = dst; *tmp && count > 0; tmp++, count--);
+ return (tmp - dst); /* DAVIDM should we count a NUL ? check getname */
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 on exception, a value greater than N if too long
+ */
+static inline long strnlen_user(const char *src, long n)
+{
+ return (strlen(src) + 1); /* DAVIDM make safer */
+}
+
+#define strlen_user(str) strnlen_user(str, 32767)
+
+/*
+ * Zero Userspace
+ */
+
+static inline unsigned long clear_user(void *to, unsigned long n)
+{
+ memset(to, 0, n);
+ return (0);
+}
+
+#endif
--- /dev/null
+/*
+ * U-boot - virtconvert.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_VIRT_CONVERT__
+#define __BLACKFIN_VIRT_CONVERT__
+
+/*
+ * Macros used for converting between virtual and physical mappings.
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+#define mm_vtop(vaddr) ((unsigned long) vaddr)
+#define mm_ptov(vaddr) ((unsigned long) vaddr)
+#define phys_to_virt(vaddr) ((unsigned long) vaddr)
+#define virt_to_phys(vaddr) ((unsigned long) vaddr)
+
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+#endif
+#endif
| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
u32 sicrl; /* System General Purpose Register Low */
#define SICRL_LDP_A 0x80000000
-#define SICRL_USB0 0x40000000
-#define SICRL_USB1 0x20000000
+#define SICRL_USB1 0x40000000
+#define SICRL_USB0 0x20000000
#define SICRL_UART 0x0C000000
#define SICRL_GPIO1_A 0x02000000
#define SICRL_GPIO1_B 0x01000000
u8 res9[8];
u32 sdram_clk_cntl;
#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
u8 res4[0xCCC];
u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */
+#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM_SHIFT 0
u8 res5[0x14];
u32 capture_data_hi; /**< Memory Data Path Read Capture High */
u32 capture_data_lo; /**< Memory Data Path Read Capture Low */
u32 capture_ecc; /**< Memory Data Path Read Capture ECC */
+#define CAPTURE_ECC_ECE (0xff000000>>24)
+#define CAPTURE_ECC_ECE_SHIFT 0
u8 res6[0x14];
u32 err_detect; /**< Memory Error Detect */
+#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
u32 err_disable; /**< Memory Error Disable */
+#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
+#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
u32 err_int_en; /**< Memory Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
u32 capture_attributes; /**< Memory Error Attributes Capture */
+#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM_SHIFT 28
+#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
+#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
+#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
+#define ECC_CAPT_ATTR_TSRC_I2C 0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
+#define ECC_CAPT_ATTR_TSRC_DMA 0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT 16
+#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
+#define ECC_CAPT_ATTR_TTYP_READ 0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT 12
+#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
u32 capture_address; /**< Memory Error Address Capture */
u32 capture_ext_address;/**< Memory Error Extended Address Capture */
u32 err_sbe; /**< Memory Single-Bit ECC Error Management */
+#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255*/
+#define ECC_ERROR_MAN_SBET_SHIFT 16
+#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255*/
+#define ECC_ERROR_MAN_SBEC_SHIFT 0
u8 res7[0xA4];
u32 debug_reg;
u8 res8[0xFC];
u8 res1[0xD8];
} spi8349_t;
+
+/*
+ * DMA/Messaging Unit
+ */
typedef struct dma8349 {
- u8 fixme[0x300];
+ u32 res0[0xC]; /* 0x0-0x29 reseverd */
+ u32 omisr; /* 0x30 Outbound message interrupt status register */
+ u32 omimr; /* 0x34 Outbound message interrupt mask register */
+ u32 res1[0x6]; /* 0x38-0x49 reserved */
+
+ u32 imr0; /* 0x50 Inbound message register 0 */
+ u32 imr1; /* 0x54 Inbound message register 1 */
+ u32 omr0; /* 0x58 Outbound message register 0 */
+ u32 omr1; /* 0x5C Outbound message register 1 */
+
+ u32 odr; /* 0x60 Outbound doorbell register */
+ u32 res2; /* 0x64-0x67 reserved */
+ u32 idr; /* 0x68 Inbound doorbell register */
+ u32 res3[0x5]; /* 0x6C-0x79 reserved */
+
+ u32 imisr; /* 0x80 Inbound message interrupt status register */
+ u32 imimr; /* 0x84 Inbound message interrupt mask register */
+ u32 res4[0x1E]; /* 0x88-0x99 reserved */
+
+ u32 dmamr0; /* 0x100 DMA 0 mode register */
+ u32 dmasr0; /* 0x104 DMA 0 status register */
+ u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
+ u32 res5; /* 0x10C reserved */
+ u32 dmasar0; /* 0x110 DMA 0 source address register */
+ u32 res6; /* 0x114 reserved */
+ u32 dmadar0; /* 0x118 DMA 0 destination address register */
+ u32 res7; /* 0x11C reserved */
+ u32 dmabcr0; /* 0x120 DMA 0 byte count register */
+ u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
+ u32 res8[0x16]; /* 0x128-0x179 reserved */
+
+ u32 dmamr1; /* 0x180 DMA 1 mode register */
+ u32 dmasr1; /* 0x184 DMA 1 status register */
+ u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
+ u32 res9; /* 0x18C reserved */
+ u32 dmasar1; /* 0x190 DMA 1 source address register */
+ u32 res10; /* 0x194 reserved */
+ u32 dmadar1; /* 0x198 DMA 1 destination address register */
+ u32 res11; /* 0x19C reserved */
+ u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
+ u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
+ u32 res12[0x16];/* 0x1A8-0x199 reserved */
+
+ u32 dmamr2; /* 0x200 DMA 2 mode register */
+ u32 dmasr2; /* 0x204 DMA 2 status register */
+ u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
+ u32 res13; /* 0x20C reserved */
+ u32 dmasar2; /* 0x210 DMA 2 source address register */
+ u32 res14; /* 0x214 reserved */
+ u32 dmadar2; /* 0x218 DMA 2 destination address register */
+ u32 res15; /* 0x21C reserved */
+ u32 dmabcr2; /* 0x220 DMA 2 byte count register */
+ u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
+ u32 res16[0x16];/* 0x228-0x279 reserved */
+
+ u32 dmamr3; /* 0x280 DMA 3 mode register */
+ u32 dmasr3; /* 0x284 DMA 3 status register */
+ u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
+ u32 res17; /* 0x28C reserved */
+ u32 dmasar3; /* 0x290 DMA 3 source address register */
+ u32 res18; /* 0x294 reserved */
+ u32 dmadar3; /* 0x298 DMA 3 destination address register */
+ u32 res19; /* 0x29C reserved */
+ u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
+ u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
+
+ u32 dmagsr; /* 0x2A8 DMA general status register */
+ u32 res20[0x15];/* 0x2AC-0x2FF reserved */
} dma8349_t;
+/* DMAMRn bits */
+#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */
+#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */
+#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */
+#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */
+
+/* DMASRn bits */
+#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */
+#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */
+
/*
* PCI Software Configuration Registers
*/
--- /dev/null
+/*
+ * MPC85xx I/O port pin manipulation functions
+ */
+
+#ifndef _ASM_IOPIN_85xx_H_
+#define _ASM_IOPIN_85xx_H_
+
+#include <linux/types.h>
+#include <asm/immap_85xx.h>
+
+#ifdef __KERNEL__
+
+typedef struct {
+ u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
+ u_char pin:5; /* port pin (0-31) */
+ u_char flag:1; /* for whatever */
+} iopin_t;
+
+#define IOPIN_PORTA 0
+#define IOPIN_PORTB 1
+#define IOPIN_PORTC 2
+#define IOPIN_PORTD 3
+
+extern __inline__ void iopin_set_high (iopin_t * iopin)
+{
+ volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_low (iopin_t * iopin)
+{
+ volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_high (iopin_t * iopin)
+{
+ volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_low (iopin_t * iopin)
+{
+ volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_out (iopin_t * iopin)
+{
+ volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_in (iopin_t * iopin)
+{
+ volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_out (iopin_t * iopin)
+{
+ volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_in (iopin_t * iopin)
+{
+ volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_odr (iopin_t * iopin)
+{
+ volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_act (iopin_t * iopin)
+{
+ volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_odr (iopin_t * iopin)
+{
+ volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_act (iopin_t * iopin)
+{
+ volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_ded (iopin_t * iopin)
+{
+ volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_gen (iopin_t * iopin)
+{
+ volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_ded (iopin_t * iopin)
+{
+ volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_gen (iopin_t * iopin)
+{
+ volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
+{
+ volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
+{
+ volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
+{
+ volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
+{
+ volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_85xx_H_ */
#define POCMR_ENABLE 0x80000000
#define POCMR_PCI_IO 0x40000000
#define POCMR_PREFETCH_EN 0x20000000
+#define POCMR_PCI2 0x10000000
/* Soft PCI reset */
CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
- CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_EXT2 | \
defined (CONFIG_75x) || \
defined (CONFIG_74xx) || \
defined (CONFIG_MPC8220) || \
- defined(CONFIG_MPC85xx)
+ defined (CONFIG_MPC85xx) || \
+ defined (CONFIG_MPC83XX)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
unsigned short in16(unsigned int);
/*
- * Copyright (C) 2004 Arabella Software Ltd.
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Analogue&Micro Adder boards family.
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 38400
-#define CONFIG_FEC_ENET /* Ethernet is on FEC */
-#ifdef CONFIG_FEC_ENET
+#define CONFIG_ETHER_ON_FEC1
+#define CONFIG_ETHER_ON_FEC2
+
+#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CFG_DISCOVER_PHY
#define FEC_ENET
-#endif /* CONFIG_FEC_ENET */
+#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#ifdef CONFIG_MPC852T
#define CFG_8xx_CPUCLK_MAX 50000000
#else
-#define CFG_8xx_CPUCLK_MAX 120000000
+#define CFG_8xx_CPUCLK_MAX 133000000
#endif /* CONFIG_MPC852T */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
#define CFG_MAXARGS 16 /* Max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR 0x100000 /* Default load address */
+#define CFG_LOAD_ADDR 0x400000 /* Default load address */
#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
* RAM configuration (note that CFG_SDRAM_BASE must be zero)
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
-
-#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2)
-#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V)
+#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
-#define CFG_MAMR 0x00802114
+#define CFG_MAMR 0x00002114
/*
- * 2048 SDRAM rows
+ * 4096 Up to 4096 SDRAM rows
* 1000 factor s -> ms
- * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 32 PTP (pre-divider from MPTPR)
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
-#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
+#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
+#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
#define CFG_RESET_ADDRESS 0x09900000
#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_OVERWRITE
+
#define CFG_OR0_PRELIM 0xFF000774
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
--- /dev/null
+/*
+ * Copyright (C) 2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP88x boards.
+ * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC885
+
+#define CONFIG_EP88X /* Embedded Planet EP88x board */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */
+#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */
+#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
+#define CFG_DISCOVER_PHY
+#define FEC_ENET
+#endif /* CONFIG_FEC_ENET */
+
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT 100000000
+#define CFG_8xx_CPUCLK_MIN 40000000
+#define CFG_8xx_CPUCLK_MAX 133000000
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_DHCP \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_MII \
+ | CFG_CMD_PING \
+ )
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
+
+#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
+#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP /* #undef to save memory */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* Max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x400000 /* Default load address */
+
+#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * RAM configuration (note that CFG_SDRAM_BASE must be zero)
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */
+
+#define CFG_MAMR 0x00805000
+
+/*
+ * 4096 Up to 4096 SDRAM rows
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR)
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
+
+#define CFG_RESET_ADDRESS 0x09900000
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
+#else
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CFG_FLASH_BASE 0xFC000000
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CFG_OR0_PRELIM 0xFC000160
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
+
+#define CFG_DIRECT_FLASH_TFTP
+
+/*-----------------------------------------------------------------------
+ * BCSR
+ */
+#define CFG_OR3_PRELIM 0xFF0005B0
+#define CFG_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
+
+#define CFG_BCSR 0xFA400000
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Map Register
+ */
+#define CFG_IMMR 0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Configuration registers
+ */
+#ifdef CONFIG_WATCHDOG
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
+ SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
+ SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
+ SYPCR_SWF | SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
+
+/* TBSCR - Time Base Status and Control Register */
+#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
+
+/* PISCR - Periodic Interrupt Status and Control */
+#define CFG_PISCR PISCR_PS
+
+/* SCCR - System Clock and reset Control Register */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR SCCR_RTSEL
+
+#define CFG_DER 0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_DHCP \
- | CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_MII \
| CFG_CMD_PING \
# define CFG_LOWBOOT16 1
#endif
#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
+#if defined(CONFIG_LITE5200B)
+# error CFG_LOWBOOT08 is incompatible with the Lite5200B
+#else
# define CFG_LOWBOOT 1
# define CFG_LOWBOOT08 1
#endif
+#endif
/*
* Autobooting
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#if defined(CONFIG_LITE5200B)
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#else
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#endif
+#endif /* CONFIG_MPC5200 */
/*
* I2C configuration
*/
/*
* Flash configuration
*/
+#if defined(CONFIG_LITE5200B)
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_FLASH_SIZE 0x01000000
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
+#else /* CFG_LOWBOOT */
+#if defined(CFG_LOWBOOT08)
+# error CFG_LOWBOOT08 is incompatible with the Lite5200B
+#endif
+#if defined(CFG_LOWBOOT16)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
+#endif
+#endif /* CFG_LOWBOOT */
+#else /* !CONFIG_LITE5200B (IceCube)*/
#define CFG_FLASH_BASE 0xFF000000
#define CFG_FLASH_SIZE 0x01000000
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
#endif
#endif /* CFG_LOWBOOT */
+#endif /* CONFIG_LITE5200B */
#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
+#if defined(CONFIG_LITE5200B)
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
+#endif
+
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
+#if defined(CONFIG_LITE5200B)
+#define CFG_ENV_SECT_SIZE 0x20000
+#else
#define CFG_ENV_SECT_SIZE 0x10000
+#endif
#define CONFIG_ENV_OVERWRITE 1
/*
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
+#if defined(CONFIG_LITE5200B)
+#define CONFIG_FEC_MII100 1
+#endif
/*
* GPIO configuration
#define CFG_HID0_FINAL 0
#endif
+#if defined(CONFIG_LITE5200B)
+#define CFG_CS1_START CFG_FLASH_BASE
+#define CFG_CS1_SIZE CFG_FLASH_SIZE
+#define CFG_CS1_CFG 0x00047800
+#define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_START CFG_CS0_START
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x00047800
+#else /* IceCube aka Lite5200 */
#ifdef CONFIG_MPC5200_DDR
#define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#endif /* CONFIG_MPC5200_DDR */
+#endif /*CONFIG_LITE5200B */
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
CFG_CMD_CACHE | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */
-/* FIXME: Real PCI support will come in a follow-up update. */
-#undef CONFIG_PCI
-
+#define CONFIG_PCI
+#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
* General PCI
* Addresses are mapped 1-1.
*/
+
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MMIO_BASE 0x90000000
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CFG_PCI2_MEM_BASE 0xA0000000
+#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_MMIO_BASE 0xb0000000
+#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
+#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
#define CFG_PCI2_IO_BASE 0x00000000
-#define CFG_PCI2_IO_PHYS 0xe3000000
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_IO_PHYS 0xe2100000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define PCI_ALL_PCI1
HRCWH_TSEC2M_IN_GMII )
#endif
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
HID0_ENABLE_M_BIT |\
HID0_ENABLE_ADDRESS_BROADCAST ) */
-#define CFG_HID2 0x000000000
+#define CFG_HID2 HID2_HBE
+
+/* DDR 0 - 256MB */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* 2G - 3G PCI */
+#ifdef CONFIG_PCI
+#define CFG_IBAT2L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT2L (0)
+#define CFG_IBAT2U (0)
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT4L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+#define CFG_IBAT5L (0)
+#define CFG_IBAT5U (0)
+#endif
+
+/* IMMRBAR */
+#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM, BCSR & FLASH */
+#define CFG_IBAT7L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
/*
* Internal Definitions
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8349emds board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83XX 1 /* MPC83XX family */
+#define CONFIG_MPC8349 1 /* MPC8349 specific */
+#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
+
+/* FIXME: Real PCI support will come in a follow-up update. */
+#undef CONFIG_PCI
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#else
+#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ 66000000
+#else
+#define CONFIG_SYS_CLK_FREQ 33000000
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+#define CFG_IMMRBAR 0xE0000000
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000 /* memtest region */
+#define CFG_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#undef CONFIG_DDR_2T_TIMING
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE 256 /* MB */
+#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CFG_DDR_TIMING_1 0x36332321
+#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
+#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
+#else
+/* the default burst length is 4 - for 64-bit data path */
+#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CFG_FLASH_SIZE 8 /* flash size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
+ BR_V) /* valid */
+
+#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP 0x7F000000
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
+ */
+#define CFG_BCSR 0xF8000000
+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
+#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ * LCRR: DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR 0x00000000
+
+#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CFG_LBLAWBAR2_PRELIM 0xF0000000
+#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+#define CFG_OR2_PRELIM 0xFC006901
+
+#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
+#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
+ | CFG_LBC_LSDMR_BSMA1516 \
+ | CFG_LBC_LSDMR_RFCR8 \
+ | CFG_LBC_LSDMR_PRETOACT6 \
+ | CFG_LBC_LSDMR_ACTTORW3 \
+ | CFG_LBC_LSDMR_BL8 \
+ | CFG_LBC_LSDMR_WRC3 \
+ | CFG_LBC_LSDMR_CL3 \
+ )
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+
+/* IO Configuration */
+#define CFG_IO_CONF (\
+ IO_CONF_UART |\
+ IO_CONF_TSEC1 |\
+ IO_CONF_IRQ0 |\
+ IO_CONF_IRQ1 |\
+ IO_CONF_IRQ2 |\
+ IO_CONF_IRQ3 |\
+ IO_CONF_IRQ4 |\
+ IO_CONF_IRQ5 |\
+ IO_CONF_IRQ6 |\
+ IO_CONF_IRQ7 )
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#define CFG_PCI2_MEM_BASE 0xA0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe3000000
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_ALL_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_GMII 1 /* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1 1
+#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC83XX_TSEC2 1
+#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C \
+ | CFG_CMD_DATE) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_DATE) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_DATE \
+ )
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII \
+ | CFG_CMD_DATE \
+ )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#if 1 /*528/264*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*396/132*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_3X1)
+#elif 0 /*264/132*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*132/132*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_1X1)
+#elif 0 /*264/264 */
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_1X1)
+#endif
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_32_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+/* #define CFG_HID0_FINAL (\
+ HID0_ENABLE_INSTRUCTION_CACHE |\
+ HID0_ENABLE_M_BIT |\
+ HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT1L (0)
+#define CFG_IBAT1U (0)
+#define CFG_IBAT2L (0)
+#define CFG_IBAT2U (0)
+#endif
+
+/* IMMRBAR @ 0xE0000000 */
+#define CFG_IBAT3L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE (no backing mem) @ 0xE8000000 */
+#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* LBC SDRAM @ 0xF0000000 */
+#define CFG_IBAT5L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT5U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+
+/* BCSR @ 0xF8000000 */
+#define CFG_IBAT6L (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* FLASH @ 0xFE000000 */
+#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:04:9f:ef:23:33
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
+#endif
+
+#define CONFIG_IPADDR 192.168.205.5
+
+#define CONFIG_HOSTNAME mpc8349emds
+#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=mpc8349emds\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "bootfile=/tftpboot/mpc8349emds/uImage\0" \
+ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
+ "update=protect off fe000000 fe03ffff; " \
+ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \
+ "upd=run load;run update\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
#define CONFIG_MPC86xADS 1 /* new ADS */
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
-/* New MPC86xADS - pick one of these */
+/* CPU type - pick one of these */
#define CONFIG_MPC866T 1
#undef CONFIG_MPC866P
#undef CONFIG_MPC859T
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 38400
-#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
+#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
+#define CFG_8xx_CPUCLK_MIN 40000000
+#define CFG_8xx_CPUCLK_MAX 80000000
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ 1
/*
* A collection of structures, addresses, and values associated with
- * the Motorola DUET ADS board. Values common to all FADS family boards
+ * the Motorola MPC885ADS board. Values common to all FADS family boards
* are in board/fads/fads.h
*
- * Copyright (C) 2003 Arabella Software Ltd.
+ * Copyright (C) 2003-2004 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/* Board type */
-#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */
+#define CONFIG_MPC885ADS 1 /* MPC885ADS board */
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
-#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
+#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 38400
-#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
-
-#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
+#define CFG_8xx_CPUCLK_MIN 40000000
+#define CFG_8xx_CPUCLK_MAX 133000000
#define CONFIG_SDRAM_50MHZ 1
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-
#include "fads.h"
-#undef CFG_SCCR
-#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11)
-
#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
CFG_CMD_PCI | \
CFG_CMD_CACHE | \
CFG_CMD_IRQ | \
- CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_REGINFO | \
* MA 02111-1307 USA
*/
-/*
- * board/config.h - configuration options, board specific
- */
-
/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
* U-Boot port on RPXlite board
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_RESET_ADDRESS 0x09900000
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_LOAD_ADDR 0x400000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFC00000
-/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CFG_FLASH_BASE 0xFFC00000
+#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
#else
-#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CFG_MONITOR_BASE 0xFFF00000
-/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
+#endif /* CONFIG_BZIP2 */
/*
* For booting Linux, the board info and command line data
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_DIRECT_FLASH_TFTP
+
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CONFIG_ENV_OVERWRITE
/*-----------------------------------------------------------------------
* Cache Configuration
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
-#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
+#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
#define BCSR0_COLTEST 0x20
#define BCSR0_ETHLPBK 0x40
-#define BCSR0_ETHEN 0x80
+#define BCSR0_ETHEN 0x80
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
#define BCSR1_PCVCTL6 0x02
#define BCSR2_USBSPD 0x40
#define BCSR2_USBSUSP 0x80
-#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
-#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
+#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
+#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
-#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
-#define BCSR3_D27 0x10 /* Dip Switch settings */
-#define BCSR3_D26 0x20
-#define BCSR3_D25 0x40
-#define BCSR3_D24 0x80
-
-
-/*
- * Environment setting
- */
-
-#define CONFIG_ETHADDR 00:10:EC:00:1D:0B
-#define CONFIG_IPADDR 192.168.1.65
-#define CONFIG_SERVERIP 192.168.1.27
+#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
+#define BCSR3_D27 0x10 /* Dip Switch settings */
+#define BCSR3_D26 0x20
+#define BCSR3_D25 0x40
+#define BCSR3_D24 0x80
#endif /* __CONFIG_H */
*/
/* #define DEBUG 1 */
-/* #ifdef DEPLOYMENT 1 */
+/* #define DEPLOYMENT 1 */
#undef CONFIG_MPC860
#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
#ifdef DEBUG
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
-#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */
+#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */
#ifdef DEPLOYMENT
-#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n"
-#define CONFIG_AUTOBOOT_STOP_STR "st"
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n"
+#define CONFIG_AUTOBOOT_STOP_STR "st"
#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY 1
-#define CONFIG_BOOT_RETRY_MIN 1
+#define CONFIG_RESET_TO_RETRY 1
+#define CONFIG_BOOT_RETRY_MIN 1
#endif /* DEPLOYMENT */
#endif /* DEBUG */
/* pre-boot commands */
-#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial"
+#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you
+ don't want the advanced function */
+
+#ifdef CONFIG_SPLASH_SCREEN
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_BMP | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_PING | \
+ CFG_CMD_ELF | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_DHCP )
+#else
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_PING | \
+ CFG_CMD_ELF | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_DHCP )
+#endif /* CONFIG_SPLASH_SCREEN */
+
+/* test-only */
+#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
+
+#define CONFIG_NETCONSOLE
+
+#endif /* 1 */
+
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#if defined(RPXlite_64MHz)
#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
#else
-#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */
+#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */
#endif
/*-----------------------------------------------------------------------
#define CONFIG_SERVERIP 172.16.115.6
#define CONFIG_ROOTPATH /workspace/myfilesystem/target/
#define CONFIG_BOOTFILE uImage.rpxusb
+#define CONFIG_HOSTNAME LITE_H1_DW
#endif /* __CONFIG_H */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_IMMAP | \
CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
CFG_CMD_I2C | \
CFG_CMD_REGINFO & \
~CFG_CMD_KGDB )
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_DHCP \
- | CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_JFFS2 \
| CFG_CMD_MII \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
HRCWH_TSEC2M_IN_GMII )
#endif
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
/* i-cache and d-cache disabled */
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 0x000000000
+/* DDR 0 - 512M */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 512M (no backing mem) */
+#define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI */
+#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+
+/* IMMRBAR */
+#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+/* FLASH */
+#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
/*
* Internal Definitions
*
/*
- * Copyright (C) 2003-2004 Arabella Software Ltd.
+ * Copyright (C) 2003-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* U-Boot configuration for Zephyr Engineering ZPC.1900 board.
#define CPU_ID_STR "MPC8265"
#define CONFIG_CPM2 1 /* Has a CPM2 */
-#undef DEBUG
-
-#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */
-
-/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE
/*
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_DHCP \
- | CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_MII \
| CFG_CMD_PING \
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_LOAD_ADDR 0x400000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CFG_FLASH_BASE 0xFFE00000
-#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
-
-#define CFG_DEFAULT_IMMR 0x0F010000
-
-#define CFG_IMMR 0xF0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 64
-#define CFG_FLSIMM_BASE 0xFC000000
-#define CFG_LSDRAM_BASE 0xFE000000
+
+#define CFG_IMMR 0xF0000000
+#define CFG_LSDRAM_BASE 0xFC000000
+#define CFG_FLASH_BASE 0xFE000000
#define CFG_BCSR 0xFEA00000
#define CFG_EEPROM 0xFEB00000
+#define CFG_FLSIMM_BASE 0xFF000000
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE }
#define BCSR_PCI_MODE 0x01
/* Hard reset configuration word */
#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
- HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
- HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\
- HRCW_MODCK_H0101 \
- ) /* 0x16828605 */
+ HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
+ HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
+ HRCW_MODCK_H0111 \
+ ) /* 0x16848207 */
/* No slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_RAMBOOT
#endif
-#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-#define CFG_HID0_INIT 0
-#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
+#define CFG_HID0_INIT (HID0_ICFI)
+#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
#define CFG_HID2 0
#define CFG_SIUMCR 0x42200000
#define CFG_SYPCR 0xFFFFFFC3
-#define CFG_BCR 0x90400000
+#define CFG_BCR 0x90000000
#define CFG_SCCR SCCR_DFBRG01
#define CFG_RMR RMR_CSRE
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR 0
-#define CFG_PSDMR 0x014EB45A
-#define CFG_PSRT 0x0C
-#define CFG_LSDMR 0x008AB552
-#define CFG_LSRT 0x0E
+#define CFG_PSDMR /* 0x834DA43B */0x014DA43A
+#define CFG_PSRT 0x0F/* 0x0C */
+#define CFG_LSDMR 0x0085A562
+#define CFG_LSRT 0x0F
#define CFG_MPTPR 0x4000
+#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041
+#define CFG_PSDRAM_OR 0xFC0028C0
+#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861
+#define CFG_LSDRAM_OR 0xFF803480
+
#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
#define CFG_OR0_PRELIM 0xFFE00856
#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
#define CFG_OR5_PRELIM 0xFFFF03F6
-#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801
-#define CFG_OR6_PRELIM 0xFE000856
+#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801
+#define CFG_OR6_PRELIM 0xFF000856
#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
#define CFG_OR7_PRELIM 0xFFFF83F6
--- /dev/null
+#ifndef __CONFIG_EZKIT533_H__
+#define __CONFIG_EZKIT533_H__
+
+#define CFG_LONGHELP 1
+#define CONFIG_BAUDRATE 57600
+#define CONFIG_STAMP 1
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20310300
+#if 0
+#define CONFIG_MII
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_RTC_BF533 1
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 27000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 22
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+#endif
+
+#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
+#define CONFIG_MEM_MT48LC16M16A2TG_75 1
+
+#define CONFIG_LOADS_ECHO 1
+
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_PING | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */
+#define CFG_LOAD_ADDR 0x01000000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_MAX_RAM_SIZE 0x02000000
+#define CFG_FLASH_BASE 0x20000000
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE 0x4000
+#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
+
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_FLASH0_BASE 0x20000000
+#define CFG_FLASH1_BASE 0x20200000
+#define CFG_FLASH2_BASE 0x20280000
+#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20020000
+#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* JFFS Partition offset set */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR 11
+
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+
+#define POLL_MODE 1
+#define FLASH_TOT_SECT 40
+#define FLASH_SIZE 0x220000
+#define CFG_FLASH_SIZE 0x220000
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * I2C settings
+ * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL PF0
+#define PF_SDA PF1
+
+#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
+#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SDA; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SDA; \
+ asm("ssync;"); \
+ }
+#define I2C_SCL(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SCL; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SCL; \
+ asm("ssync;"); \
+ }
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xFE
+
+
+#define __ADSPLPBLACKFIN__ 1
+#define __ADSPBF533__ 1
+
+/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
+/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
+ ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
+ B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+*/
+#define AMGCTLVAL 0xFF
+#define AMBCTL0VAL 0x7BB07BB0
+#define AMBCTL1VAL 0xFFC27BB0
+
+#define CONFIG_VDSP 1
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP 0x8
+#define SHT_STRTAB_VDSP 0x1
+#define ELFSHDRSIZE_VDSP 0x2C
+#define VDSP_ENTRY_ADDR 0xFFA00000
+#endif
+
+#endif
CFG_CMD_BEDBUG | \
CFG_CMD_ELF | \
CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
CFG_CMD_REGINFO | \
CFG_CMD_IMMAP | \
CFG_CMD_MII)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
ADD_USB_CMD | \
CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+ CFG_CMD_I2C)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR 0x58
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_BITS 4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR 0x51
-
-/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
*/
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
-#define CFG_GPS_PORT_CONFIG 0x10000004
+#define CFG_GPS_PORT_CONFIG 0x00000004
/*
* Miscellaneous configurable options
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
+/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
+#define CFG_CS2_START 0x80000000
+#define CFG_CS2_SIZE 0x00001000
+#define CFG_CS2_CFG 0x1d800
+
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
CFG_CMD_ELF | \
CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
CFG_CMD_REGINFO | \
CFG_CMD_MEMTEST | \
CFG_CMD_MII | \
# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
CFG_CMD_ELF | \
CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
CFG_CMD_I2C | \
CFG_CMD_SPI | \
CFG_CMD_SDRAM | \
# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
CFG_CMD_ELF | \
CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
CFG_CMD_I2C | \
CFG_CMD_SPI | \
CFG_CMD_SDRAM | \
#ifdef CONFIG_ETHER_ON_FCC
# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IMMAP | \
#else
# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IMMAP | \
--- /dev/null
+/*
+ * U-boot - stamp.h Configuration file for STAMP board
+ * having BF533 processor
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_STAMP_H__
+#define __CONFIG_STAMP_H__
+
+/*
+ * Board settings
+ *
+ */
+
+#define __ADSPLPBLACKFIN__ 1
+#define __ADSPBF533__ 1
+#define CONFIG_STAMP 1
+#define CONFIG_RTC_BF533 1
+
+/* FLASH/ETHERNET uses the same address range */
+#define SHARED_RESOURCES 1
+
+#define CONFIG_VDSP 1
+
+/*
+ * Clock settings
+ *
+ */
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 11059200
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 45
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 6
+
+/*
+ * Network Settings
+ */
+/* network support */
+#define CONFIG_IPADDR 192.168.0.15
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_HOSTNAME STAMP
+#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
+
+/* To remove hardcoding and enable MAC storage in EEPROM */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
+
+/*
+ * Command settings
+ *
+ */
+
+#define CFG_LONGHELP 1
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_PING | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):eth0:off\0" \
+ "ramboot=tftpboot 0x1000000 linux;" \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot 0x1000000 linux;" \
+ "run nfsargs;run addip;bootelf\0" \
+ "flashboot=bootm 0x20100000\0" \
+ ""
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Console settings
+ *
+ */
+
+#define CONFIG_BAUDRATE 57600
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_LOADS_ECHO 1
+
+/*
+ * Network settings
+ *
+ */
+
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20300300
+/* To remove hardcoding and enable MAC storage in EEPROM */
+/* #define HARDCODE_MAC 1 */
+
+/*
+ * Flash settings
+ *
+ */
+
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET
+
+#define CFG_ENV_IS_IN_FLASH 1
+
+#define CFG_FLASH_BASE 0x20000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
+
+#define CFG_ENV_ADDR 0x20020000
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
+
+#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
+#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
+
+/* JFFS Partition offset set */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR 11
+
+/*
+ * following timeouts shall be used once the
+ * Flash real protection is enabled
+ */
+#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
+
+/*
+ * I2C settings
+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL PF3
+#define PF_SDA PF2
+
+#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
+#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SDA; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SDA; \
+ asm("ssync;"); \
+ }
+#define I2C_SCL(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SCL; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SCL; \
+ asm("ssync;"); \
+ }
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xFE
+
+/*
+ * Compact Flash settings
+ */
+
+/* Enabled below option for CF support */
+/* #define CONFIG_STAMP_CF 1 */
+
+#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+
+#define CONFIG_MISC_INIT_R 1
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * IDE/ATA stuff
+ */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#undef CONFIG_IDE_RESET /* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0x20200000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE 2
+#endif
+
+/*
+ * SDRAM settings
+ *
+ */
+
+#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
+#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */
+#define CFG_LOAD_ADDR 0x01000000 /* default load address */
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_MAX_RAM_SIZE 0x08000000
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HZ 1000 /* 1ms time tick */
+
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE 0x4000
+#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
+
+#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+
+/*
+ * FLASH organization and environment definitions
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
+/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
+ B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
+#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
+ B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
+*/
+#define AMGCTLVAL 0xFF
+#define AMBCTL0VAL 0xBBC3BBC3
+#define AMBCTL1VAL 0x99B39983
+#define CF_AMBCTL1VAL 0x99B3ffc2
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP 0x8
+#define SHT_STRTAB_VDSP 0x1
+#define ELFSHDRSIZE_VDSP 0x2C
+#define VDSP_ENTRY_ADDR 0xFFA00000
+#endif
+
+#endif
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)
+#define CONFIG_OF_HAS_BD_T 1
+#define CONFIG_OF_HAS_UBOOT_ENV 1
#endif /* __CONFIG_H */
| CFG_CMD_ENV | CFG_CMD_CONSOLE \
| CFG_CMD_LOADS | CFG_CMD_LOADB \
| CFG_CMD_IMI | CFG_CMD_CACHE \
- | CFG_CMD_RUN | CFG_CMD_ECHO \
| CFG_CMD_REGINFO | CFG_CMD_NET\
| CFG_CMD_DHCP | CFG_CMD_I2C \
| CFG_CMD_DATE)
#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
+#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */
#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
-void ft_setup(void *blob, int size, bd_t * bd);
+void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end);
void ft_dump_blob(const void *bphp);
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
void *ft_get_prop(void *bphp, const char *propname, int *szp);
+void ft_board_setup(void *blob, bd_t *bd);
+
#endif
#define IH_CPU_NIOS 13 /* Nios-32 */
#define IH_CPU_MICROBLAZE 14 /* MicroBlaze */
#define IH_CPU_NIOS2 15 /* Nios-II */
+#define IH_CPU_BLACKFIN 16 /* Blackfin */
/*
* Image Types
#endif /* __PPC__ */
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__)
struct stat {
unsigned short st_dev;
#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
+/*
+ * Local Bus Controller - memory controller registers
+ */
+#define BRx_V 0x00000001 /* Bank Valid */
+#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
+#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */
+#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
+#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
+#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
+#define BRx_PS_8 0x00000800 /* 8 bit port size */
+#define BRx_PS_32 0x00001800 /* 32 bit port size */
+#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
+
+#define ORxG_EAD 0x00000001 /* External addr latch delay */
+#define ORxG_EHTR 0x00000002 /* Extended hold time on read */
+#define ORxG_TRLX 0x00000004 /* Timing relaxed */
+#define ORxG_SETA 0x00000008 /* External address termination */
+#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
+#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
+#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */
+#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
+#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
+
+#define ORxU_BI 0x00000100 /* Burst Inhibit */
+#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
+
+#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
+#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
+#define MxMR_OP_WARR 0x10000000 /* Write to Array */
+#define MxMR_BSEL 0x80000000 /* Bus Select */
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
+#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
+
#endif /* __MPC85xx_H__ */
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == 4)
struct NS16550 {
- unsigned long rbr; /* 0 */
- unsigned long ier; /* 1 */
- unsigned long fcr; /* 2 */
- unsigned long lcr; /* 3 */
- unsigned long mcr; /* 4 */
- unsigned long lsr; /* 5 */
- unsigned long msr; /* 6 */
- unsigned long scr; /* 7 */
-} __attribute__ ((packed));
+ unsigned long rbr; /* 0 r */
+ unsigned long ier; /* 1 rw */
+ unsigned long fcr; /* 2 w */
+ unsigned long lcr; /* 3 rw */
+ unsigned long mcr; /* 4 rw */
+ unsigned long lsr; /* 5 r */
+ unsigned long msr; /* 6 r */
+ unsigned long scr; /* 7 rw */
+}; /* No need to pack an already aligned struct */
#elif (CFG_NS16550_REG_SIZE == -4)
struct NS16550 {
unsigned char rbr; /* 0 */
#define MCR_DMA_EN 0x04
#define MCR_TX_DFR 0x08
-#define LCR_WLS_MSK 0x03 /* character length slect mask */
+#define LCR_WLS_MSK 0x03 /* character length select mask */
#define LCR_WLS_5 0x00 /* 5 bit character length */
#define LCR_WLS_6 0x01 /* 6 bit character length */
#define LCR_WLS_7 0x02 /* 7 bit character length */
#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
#define PCI_REGION_IO 0x00000001 /* PCI IO space */
#define PCI_REGION_TYPE 0x00000001
+#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
#define PCI_REGION_MEMORY 0x00000100 /* System memory */
#define PCI_REGION_RO 0x00000200 /* Read-only memory */
unsigned long priv[3];
};
-extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev,
- struct pci_config_table *);
+extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
+ struct pci_config_table *);
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
/* Used by auto config */
- struct pci_region *pci_mem, *pci_io;
+ struct pci_region *pci_mem, *pci_io, *pci_prefetch;
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
extern void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
+ struct pci_region *prefetch,
struct pci_region *io);
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
#ifndef _SPD_SDRAM_H_
#define _SPD_SDRAM_H_
-long int spd_sdram(int(read_spd)(uint addr));
+long int spd_sdram(void);
#endif
checksum = ntohl (hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *) data, len) != checksum) {
+ if (crc32 (0, (unsigned char *) data, len) != checksum) {
printf ("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS (-11);
do_reset (cmdtp, flag, argc, argv);
ulong csum = 0;
printf (" Verifying Checksum ... ");
- csum = crc32 (0, (char *) data, len);
+ csum = crc32 (0, (unsigned char *) data, len);
if (csum != ntohl (hdr->ih_dcrc)) {
printf ("Bad Data CRC\n");
SHOW_BOOT_PROGRESS (-12);
static int init_baudrate (void)
{
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
? (int) simple_strtoul (tmp, NULL, 10)
void start_armboot (void)
{
- ulong size;
init_fnc_t **init_fnc_ptr;
char *s;
+#ifndef CFG_NO_FLASH
+ ulong size;
+#endif
#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
unsigned long addr;
#endif
int i;
ulong reg;
char *s, *e;
- uchar tmp[64];
+ char tmp[64];
i = getenv_r ("ethaddr", tmp, sizeof (tmp));
s = (i > 0) ? tmp : NULL;
}
#ifdef CONFIG_MODEM_SUPPORT
+static inline void mdm_readline(char *buf, int bufsiz);
+
/* called from main loop (common/main.c) */
extern void dbg(const char *fmt, ...);
int mdm_init (void)
char *init_str;
int i;
extern char console_buffer[];
- static inline void mdm_readline(char *buf, int bufsiz);
extern void enable_putc(void);
extern int hwflow_onoff(int);
--- /dev/null
+#
+# U-boot Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(ARCH).a
+
+AOBJS =
+
+COBJS = board.o bf533_linux.o bf533_string.o cache.o muldi3.o
+OBJS = $(AOBJS) $(COBJS)
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * U-boot - bf533_linux.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Dummy functions, currently not in Use */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <zlib.h>
+#include <asm/byteorder.h>
+
+#define LINUX_MAX_ENVS 256
+#define LINUX_MAX_ARGS 256
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+#define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+#define CMD_LINE_ADDR 0xFF900000 /* L1 scratchpad */
+
+#ifdef SHARED_RESOURCES
+ extern void swap_to(int device_id);
+#endif
+
+static char *make_command_line(void);
+
+extern image_header_t header;
+extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
+ ulong addr, ulong * len_ptr, int verify)
+{
+ int (*appl)(char *cmdline);
+ char *cmdline;
+
+#ifdef SHARED_RESOURCES
+ swap_to(FLASH);
+#endif
+
+ appl = (int (*)(char *))ntohl(header.ih_ep);
+ printf("Starting Kernel at = %x\n", appl);
+ cmdline = make_command_line();
+ if(icache_status()){
+ flush_instruction_cache();
+ icache_disable();
+ }
+ if(dcache_status()){
+ flush_data_cache();
+ dcache_disable();
+ }
+ (*appl)(cmdline);
+}
+
+char *make_command_line(void)
+{
+ char *dest = (char *) CMD_LINE_ADDR;
+ char *bootargs;
+
+ if ( (bootargs = getenv("bootargs")) == NULL )
+ return NULL;
+
+ strncpy(dest, bootargs, 0x1000);
+ dest[0xfff] = 0;
+ return dest;
+}
--- /dev/null
+/*
+ * U-boot - bf533_string.c Contains library routines.
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/cpu/defBF533.h>
+
+void *dma_memcpy(void *,const void *,size_t);
+
+char *strcpy(char *dest, const char *src)
+{
+ char *xdest = dest;
+ char temp = 0;
+
+ __asm__ __volatile__
+ ("1:\t%2 = B [%1++] (Z);\n\t"
+ "B [%0++] = %2;\n\t"
+ "CC = %2;\n\t"
+ "if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp)
+ :"0"(dest), "1"(src), "2"(temp):"memory");
+
+ return xdest;
+}
+
+char *strncpy(char *dest, const char *src, size_t n)
+{
+ char *xdest = dest;
+ char temp = 0;
+
+ if (n == 0)
+ return xdest;
+
+ __asm__ __volatile__
+ ("1:\t%3 = B [%1++] (Z);\n\t"
+ "B [%0++] = %3;\n\t"
+ "CC = %3;\n\t"
+ "if ! cc jump 2f;\n\t"
+ "%2 += -1;\n\t"
+ "CC = %2 == 0;\n\t"
+ "if ! cc jump 1b (bp);\n"
+ "2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
+ :"0"(dest), "1"(src), "2"(n), "3"(temp)
+ :"memory");
+
+ return xdest;
+}
+
+int strcmp(const char *cs, const char *ct)
+{
+ char __res1, __res2;
+
+ __asm__
+ ("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
+ "%3 = B[%1++] (Z);\n\t" /* get *ct */
+ "CC = %2 == %3;\n\t" /* compare a byte */
+ "if ! cc jump 2f;\n\t" /* not equal, break out */
+ "CC = %2;\n\t" /* at end of cs? */
+ "if cc jump 1b (bp);\n\t" /* no, keep going */
+ "jump.s 3f;\n" /* strings are equal */
+ "2:\t%2 = %2 - %3;\n" /* *cs - *ct */
+ "3:\n": "=a"(cs), "=a"(ct), "=d"(__res1),
+ "=d"(__res2)
+ : "0"(cs), "1"(ct));
+
+ return __res1;
+}
+
+int strncmp(const char *cs, const char *ct, size_t count)
+{
+ char __res1, __res2;
+
+ if (!count)
+ return 0;
+
+ __asm__
+ ("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */
+ "%4 = B[%1++] (Z);\n\t" /* get *ct */
+ "CC = %3 == %4;\n\t" /* compare a byte */
+ "if ! cc jump 3f;\n\t" /* not equal, break out */
+ "CC = %3;\n\t" /* at end of cs? */
+ "if ! cc jump 4f;\n\t" /* yes, all done */
+ "%2 += -1;\n\t" /* no, adjust count */
+ "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n" /* more to do, keep going */
+ "2:\t%3 = 0;\n\t" /* strings are equal */
+ "jump.s 4f;\n" "3:\t%3 = %3 - %4;\n" /* *cs - *ct */
+ "4:": "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1),
+ "=d"(__res2)
+ : "0"(cs), "1"(ct), "2"(count));
+
+ return __res1;
+}
+
+/*
+ * memcpy - Copy one area of memory to another
+ * @dest: Where to copy to
+ * @src: Where to copy from
+ * @count: The size of the area.
+ *
+ * You should not use this function to access IO space, use memcpy_toio()
+ * or memcpy_fromio() instead.
+ */
+void * memcpy(void * dest,const void *src,size_t count)
+{
+ char *tmp = (char *) dest, *s = (char *) src;
+
+/* Turn off the cache, if destination in the L1 memory */
+ if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
+ || (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
+ || (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){
+ if(icache_status()){
+ blackfin_icache_flush_range(src, src+count);
+ icache_disable();
+ }
+ if(dcache_status()){
+ blackfin_dcache_flush_range(src, src+count);
+ dcache_disable();
+ }
+ dma_memcpy(dest,src,count);
+ }else{
+ while(count--)
+ *tmp++ = *s++;
+ }
+ return dest;
+}
+
+void *dma_memcpy(void * dest,const void *src,size_t count)
+{
+
+ *pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
+
+ /* Copy sram functions from sdram to sram */
+ /* Setup destination start address */
+ *pMDMA_D0_START_ADDR = (volatile void **)dest;
+ /* Setup destination xcount */
+ *pMDMA_D0_X_COUNT = count ;
+ /* Setup destination xmodify */
+ *pMDMA_D0_X_MODIFY = 1;
+
+ /* Setup Source start address */
+ *pMDMA_S0_START_ADDR = (volatile void **)src;
+ /* Setup Source xcount */
+ *pMDMA_S0_X_COUNT = count;
+ /* Setup Source xmodify */
+ *pMDMA_S0_X_MODIFY = 1;
+
+ /* Enable source DMA */
+ *pMDMA_S0_CONFIG = (DMAEN);
+ asm("ssync;");
+
+ *pMDMA_D0_CONFIG = ( WNR | DMAEN);
+
+ while(*pMDMA_D0_IRQ_STATUS & DMA_RUN){
+ *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
+ }
+ *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
+
+ dest += count;
+ src += count;
+ return dest;
+}
--- /dev/null
+/*
+ * U-boot - blackfin_board.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_BOARD_H__
+#define __BLACKFIN_BOARD_H__
+
+extern void timer_init(void);
+extern void init_IRQ(void);
+extern void rtc_init(void);
+
+extern ulong uboot_end_data;
+extern ulong uboot_end;
+
+ulong monitor_flash_len;
+
+
+#define VERSION_STRING_SIZE 150 /* including 40 bytes buffer to change any string */
+#define VERSION_STRING_FORMAT "%s (%s - %s)\n"
+#define VERSION_STRING U_BOOT_VERSION, __DATE__, __TIME__
+
+char version_string[VERSION_STRING_SIZE];
+
+int *g_addr;
+static ulong mem_malloc_start;
+static ulong mem_malloc_end;
+static ulong mem_malloc_brk;
+extern char _sram_in_sdram_start[];
+extern char _sram_inst_size[];
+#ifdef DEBUG
+static void display_global_data(void);
+#endif
+
+/* definitions used to check the SMC card availability */
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+#define UPPER_BYTE_MASK 0xFF00
+#define SMC_IDENT 0x3300
+
+#endif
--- /dev/null
+/*
+ * U-boot - board.c First C file to be called contains init routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+#include <environment.h>
+#include "blackfin_board.h"
+#include "../drivers/smc91111.h"
+
+extern flash_info_t flash_info[];
+
+
+static void mem_malloc_init(void)
+{
+ mem_malloc_start = CFG_MALLOC_BASE;
+ mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
+ mem_malloc_brk = mem_malloc_start;
+ memset((void *) mem_malloc_start, 0,
+ mem_malloc_end - mem_malloc_start);
+}
+
+void *sbrk(ptrdiff_t increment)
+{
+ ulong old = mem_malloc_brk;
+ ulong new = old + increment;
+
+ if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
+ return (NULL);
+ }
+ mem_malloc_brk = new;
+
+ return ((void *) old);
+}
+
+static int display_banner(void)
+{
+ sprintf(version_string, VERSION_STRING_FORMAT, VERSION_STRING);
+ printf("%s\n", version_string);
+ return (0);
+}
+
+static void display_flash_config(ulong size)
+{
+ puts("FLASH: ");
+ print_size(size, "\n");
+ return;
+}
+
+static int init_baudrate(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ uchar tmp[64];
+ int i = getenv_r("baudrate", tmp, sizeof(tmp));
+ gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+ ? (int) simple_strtoul(tmp, NULL, 10)
+ : CONFIG_BAUDRATE;
+ return (0);
+}
+
+#ifdef DEBUG
+static void display_global_data(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ bd_t *bd;
+ bd = gd->bd;
+ printf("--flags:%x\n", gd->flags);
+ printf("--board_type:%x\n", gd->board_type);
+ printf("--baudrate:%x\n", gd->baudrate);
+ printf("--have_console:%x\n", gd->have_console);
+ printf("--ram_size:%x\n", gd->ram_size);
+ printf("--reloc_off:%x\n", gd->reloc_off);
+ printf("--env_addr:%x\n", gd->env_addr);
+ printf("--env_valid:%x\n", gd->env_valid);
+ printf("--bd:%x %x\n", gd->bd, bd);
+ printf("---bi_baudrate:%x\n", bd->bi_baudrate);
+ printf("---bi_ip_addr:%x\n", bd->bi_ip_addr);
+ printf("---bi_enetaddr:%x %x %x %x %x %x\n",
+ bd->bi_enetaddr[0],
+ bd->bi_enetaddr[1],
+ bd->bi_enetaddr[2],
+ bd->bi_enetaddr[3],
+ bd->bi_enetaddr[4],
+ bd->bi_enetaddr[5]);
+ printf("---bi_arch_number:%x\n", bd->bi_arch_number);
+ printf("---bi_boot_params:%x\n", bd->bi_boot_params);
+ printf("---bi_memstart:%x\n", bd->bi_memstart);
+ printf("---bi_memsize:%x\n", bd->bi_memsize);
+ printf("---bi_flashstart:%x\n", bd->bi_flashstart);
+ printf("---bi_flashsize:%x\n", bd->bi_flashsize);
+ printf("---bi_flashoffset:%x\n", bd->bi_flashoffset);
+ printf("--jt:%x *:%x\n", gd->jt, *(gd->jt));
+}
+#endif
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependend #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+
+void board_init_f(ulong bootflag)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ ulong addr;
+ bd_t *bd;
+
+ gd = (gd_t *) (CFG_GBL_DATA_ADDR);
+ memset((void *) gd, 0, sizeof(gd_t));
+
+ /* Board data initialization */
+ addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t));
+
+ /* Align to 4 byte boundary */
+ addr &= ~(4 - 1);
+ bd = (bd_t*)addr;
+ gd->bd = bd;
+ memset((void *) bd, 0, sizeof(bd_t));
+
+ /* Initialize */
+ init_IRQ();
+ env_init(); /* initialize environment */
+ init_baudrate(); /* initialze baudrate settings */
+ serial_init(); /* serial communications setup */
+ console_init_f();
+ display_banner(); /* say that we are here */
+ checkboard();
+#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+ rtc_init();
+#endif
+ timer_init();
+ printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", \
+ CONFIG_VCO_HZ/1000000, CONFIG_CCLK_HZ/1000000, CONFIG_SCLK_HZ/1000000);
+ printf("SDRAM: ");
+ print_size(initdram(0), "\n");
+ board_init_r((gd_t *) gd, 0x20000010);
+}
+
+void board_init_r(gd_t * id, ulong dest_addr)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ ulong size;
+ extern void malloc_bin_reloc(void);
+ char *s, *e;
+ bd_t *bd;
+ int i;
+ gd = id;
+ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+ bd = gd->bd;
+
+#if CONFIG_STAMP
+ /* There are some other pointer constants we must deal with */
+ /* configure available FLASH banks */
+ size = flash_init();
+ display_flash_config(size);
+ flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
+ bd->bi_flashstart = CFG_FLASH_BASE;
+ bd->bi_flashsize = size;
+ bd->bi_flashoffset = 0;
+#else
+ bd->bi_flashstart = 0;
+ bd->bi_flashsize = 0;
+ bd->bi_flashoffset = 0;
+#endif
+ /* initialize malloc() area */
+ mem_malloc_init();
+ malloc_bin_reloc();
+
+ /* relocate environment function pointers etc. */
+ env_relocate();
+
+ /* board MAC address */
+ s = getenv("ethaddr");
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+
+ /* IP Address */
+ bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+ /* Initialize devices */
+ devices_init();
+ jumptable_init();
+
+ /* Initialize the console (after the relocation and devices init) */
+ console_init_r();
+
+ /* Initialize from environment */
+ if ((s = getenv("loadaddr")) != NULL) {
+ load_addr = simple_strtoul(s, NULL, 16);
+ }
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ if ((s = getenv("bootfile")) != NULL) {
+ copy_filename(BootFile, s, sizeof(BootFile));
+ }
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+ /* miscellaneous platform dependent initialisations */
+ misc_init_r();
+#endif
+
+#ifdef CONFIG_DRIVER_SMC91111
+#ifdef SHARED_RESOURCES
+ /* Switch to Ethernet */
+ swap_to(ETHERNET);
+#endif
+ if ( (SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT ) {
+ printf("ERROR: Can't find SMC91111 at address %x\n", SMC_BASE_ADDRESS);
+ } else {
+ printf("Net: SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS);
+ }
+
+#ifdef SHARED_RESOURCES
+ swap_to(FLASH);
+#endif
+#endif
+#ifdef CONFIG_SOFT_I2C
+ init_func_i2c();
+#endif
+
+#ifdef DEBUG
+ display_global_data(void);
+#endif
+
+ /* main_loop() can return to retry autoboot, if so just run it again. */
+ for (;;) {
+ main_loop();
+ }
+}
+
+#ifdef CONFIG_SOFT_I2C
+static int init_func_i2c (void)
+{
+ puts ("I2C: ");
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ puts ("ready\n");
+ return (0);
+}
+#endif
+
+void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;);
+}
--- /dev/null
+/*
+ * U-boot - cache.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* for now: just dummy functions to satisfy the linker */
+extern void blackfin_icache_range (unsigned long *, unsigned long *);
+extern void blackfin_dcache_range (unsigned long *, unsigned long *);
+void flush_cache (unsigned long dummy1, unsigned long dummy2)
+{
+ if (icache_status ()) {
+ blackfin_icache_flush_range (dummy1, dummy1 + dummy2);
+ }
+ if (dcache_status ()) {
+ blackfin_dcache_flush_range (dummy1, dummy1 + dummy2);
+ }
+ return;
+}
--- /dev/null
+/*
+ * U-boot - muldi3.c contains routines for mult and div
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Generic function got from GNU gcc package, libgcc2.c */
+#ifndef SI_TYPE_SIZE
+#define SI_TYPE_SIZE 32
+#endif
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define BITS_PER_UNIT 8
+
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v) \
+do { \
+ USItype __x0, __x1, __x2, __x3; \
+ USItype __ul, __vl, __uh, __vh; \
+ \
+ __ul = __ll_lowpart (u); \
+ __uh = __ll_highpart (u); \
+ __vl = __ll_lowpart (v); \
+ __vh = __ll_highpart (v); \
+ \
+ __x0 = (USItype) __ul * __vl; \
+ __x1 = (USItype) __ul * __vh; \
+ __x2 = (USItype) __uh * __vl; \
+ __x3 = (USItype) __uh * __vh; \
+ \
+ __x1 += __ll_highpart (__x0);/* this can't give carry */ \
+ __x1 += __x2; /* but this indeed can */ \
+ if (__x1 < __x2) /* did we get it? */ \
+ __x3 += __ll_B; /* yes, add it in the proper pos. */ \
+ \
+ (w1) = __x3 + __ll_highpart (__x1); \
+ (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
+} while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v) \
+ ({DIunion __w; \
+ umul_ppmm (__w.s.high, __w.s.low, u, v); \
+ __w.ll; })
+#endif
+
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype low, high;};
+typedef union
+{
+ struct DIstruct s;
+ DItype ll;
+} DIunion;
+
+DItype __muldi3 (DItype u, DItype v)
+{
+ DIunion w;
+ DIunion uu, vv;
+
+ uu.ll = u,
+ vv.ll = v;
+ /* panic("kernel panic for __muldi3"); */
+ w.ll = __umulsidi3 (uu.s.low, vv.s.low);
+ w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+ + (USItype) uu.s.high * (USItype) vv.s.low);
+
+ return w.ll;
+}
WATCHDOG_RESET();
-#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)
+#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
+ defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
icache_enable (); /* it's time to enable the instruction cache */
#endif
}
#if (CONFIG_COMMANDS & CFG_CMD_DHCP)
-static void DhcpOptionsProcess (uchar * popt)
+static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
{
uchar *end = popt + BOOTP_HDR_SIZE;
int oplen, size;
break;
case 59: /* Ignore Rebinding Time Option */
break;
+ case 66: /* Ignore TFTP server name */
+ break;
+ case 67: /* vendor opt bootfile */
+ /*
+ * I can't use dhcp_vendorex_proc here because I need
+ * to write into the bootp packet - even then I had to
+ * pass the bootp packet pointer into here as the
+ * second arg
+ */
+ size = truncate_sz ("Opt Boot File",
+ sizeof(bp->bp_file),
+ oplen);
+ if (bp->bp_file[0] == '\0' && size > 0) {
+ /*
+ * only use vendor boot file if we didn't
+ * receive a boot file in the main non-vendor
+ * part of the packet - god only knows why
+ * some vendors chose not to use this perfectly
+ * good spot to store the boot file (join on
+ * Tru64 Unix) it seems mind bogglingly crazy
+ * to me
+ */
+ printf("*** WARNING: using vendor "
+ "optional boot file\n");
+ memcpy(bp->bp_file, popt + 2, size);
+ bp->bp_file[size] = '\0';
+ }
+ break;
default:
#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX)
if (dhcp_vendorex_proc (popt))
dhcp_state = REQUESTING;
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
+ DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp);
BootpCopyNetParams(bp); /* Store net params from reply */
char *s;
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
+ DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp);
BootpCopyNetParams(bp); /* Store net params from reply */
dhcp_state = BOUND;
puts ("DHCP client bound to address ");
(NetOurIP & NetOurSubnetMask)) {
if (NetOurGatewayIP == 0) {
puts ("## Warning: gatewayip needed but not set\n");
+ NetArpWaitReplyIP = NetArpWaitPacketIP;
+ } else {
+ NetArpWaitReplyIP = NetOurGatewayIP;
}
- NetArpWaitReplyIP = NetOurGatewayIP;
} else {
NetArpWaitReplyIP = NetArpWaitPacketIP;
}
LIB = librtc.a
OBJS = date.o \
- ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \
- ds1556.o ds164x.o ds174x.o \
+ bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
+ ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o \
m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux
+ *
+ * Copyright (C) 2003 Motorola Corporation. All rights reserved.
+ * Richard Xiao (A2590C@email.mot.com)
+ *
+ * Copyright (C) 1996 Paul Gortmaker
+ *
+ *
+ * Based on other minimal char device drivers, like Alan's
+ * watchdog, Ted's random, etc. etc.
+ *
+ * 1.07 Paul Gortmaker.
+ * 1.08 Miquel van Smoorenburg: disallow certain things on the
+ * DEC Alpha as the CMOS clock is also used for other things.
+ * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup.
+ * 1.09a Pete Zaitcev: Sun SPARC
+ * 1.09b Jeff Garzik: Modularize, init cleanup
+ * 1.09c Jeff Garzik: SMP cleanup
+ * 1.10 Paul Barton-Davis: add support for async I/O
+ * 1.10a Andrea Arcangeli: Alpha updates
+ * 1.10b Andrew Morton: SMP lock fix
+ * 1.10c Cesar Barros: SMP locking fixes and cleanup
+ * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit
+ * 1.10e LG Soft India: Register access is different in BF533.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#include <asm/blackfin.h>
+#include <asm/cpu/bf533_rtc.h>
+
+void rtc_reset (void)
+{
+ return; /* nothing to do */
+}
+
+/* Wait for pending writes to complete */
+void wait_for_complete (void)
+{
+ while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) {
+ printf ("");
+ }
+ *(volatile unsigned short *) RTC_ISTAT = 0x8000;
+}
+
+/* Enable the RTC prescaler enable register */
+void rtc_init ()
+{
+ *(volatile unsigned short *) RTC_PREN = 0x1;
+ wait_for_complete ();
+}
+
+/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
+ * based on this value.
+ */
+void rtc_set (struct rtc_time *tmp)
+{
+ unsigned long n_days_1970 = 0;
+ unsigned long n_secs_rem = 0;
+ unsigned long n_hrs = 0;
+ unsigned long n_mins = 0;
+ unsigned long n_secs = 0;
+ unsigned long time_in_secs;
+
+ if (tmp == NULL) {
+ printf ("Error setting the date/time \n");
+ return;
+ }
+
+ time_in_secs =
+ mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
+ tmp->tm_min, tmp->tm_sec);
+
+ /* Compute no. of days since 1970 */
+ n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY));
+
+ /* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
+ n_secs_rem = (unsigned long) (time_in_secs % (NUM_SECS_IN_DAY));
+ n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR);
+ n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR);
+ n_mins = n_secs_rem / (NUM_SECS_IN_MIN);
+ n_secs = n_secs_rem % (NUM_SECS_IN_MIN);
+
+ /* Store the new time in the RTC_STAT register */
+ *(volatile unsigned long *) RTC_STAT =
+ ((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
+ (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
+
+ wait_for_complete ();
+}
+
+/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
+void rtc_get (struct rtc_time *tmp)
+{
+ unsigned long cur_rtc_stat = 0;
+ unsigned long time_in_sec;
+ unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0;
+
+ if (tmp == NULL) {
+ printf ("Error getting the date/time \n");
+ return;
+ }
+
+ /* Read the RTC_STAT register */
+ cur_rtc_stat = *(volatile unsigned long *) RTC_STAT;
+
+ /* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */
+ tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f;
+ tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f;
+ tm_hour = (cur_rtc_stat >> HOUR_BITS_OFF) & 0x1f;
+ tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff;
+
+ /* Calculate the total number of seconds since Jan 1970 */
+ time_in_sec = (tm_sec) +
+ MIN_TO_SECS (tm_min) +
+ HRS_TO_SECS (tm_hour) +
+ DAYS_TO_SECS (tm_day);
+ to_tm (time_in_sec, tmp);
+}
+#endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */
--- /dev/null
+/*
+ * (C) Copyright 2001, 2002, 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com`
+ * Steven Scholz, steven.scholz@imc-berlin.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
+ * DS1374 Real Time Clock (RTC).
+ *
+ * based on ds1337.c
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+#if (defined(CONFIG_RTC_DS1374)) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_RTC
+#define DEBUG_RTC
+
+#ifdef DEBUG_RTC
+#define DEBUGR(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGR(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+#ifndef CFG_I2C_RTC_ADDR
+# define CFG_I2C_RTC_ADDR 0x68
+#endif
+
+#if defined(CONFIG_RTC_DS1374) && (CFG_I2C_SPEED > 400000)
+# error The DS1374 is specified up to 400kHz in fast mode!
+#endif
+
+/*
+ * RTC register addresses
+ */
+#define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
+#define RTC_TOD_CNT_BYTE1_ADDR 0x01
+#define RTC_TOD_CNT_BYTE2_ADDR 0x02
+#define RTC_TOD_CNT_BYTE3_ADDR 0x03
+
+#define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
+#define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
+#define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
+
+#define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
+#define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
+#define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
+
+#define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
+#define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
+#define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
+#define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
+#define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
+#define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
+#define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
+#define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
+
+#define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
+#define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
+
+typedef unsigned char boolean_t;
+
+#ifndef TRUE
+#define TRUE ((boolean_t)(0==0))
+#endif
+#ifndef FALSE
+#define FALSE (!TRUE)
+#endif
+
+const char RtcTodAddr[] = {
+ RTC_TOD_CNT_BYTE0_ADDR,
+ RTC_TOD_CNT_BYTE1_ADDR,
+ RTC_TOD_CNT_BYTE2_ADDR,
+ RTC_TOD_CNT_BYTE3_ADDR
+};
+
+static uchar rtc_read (uchar reg);
+static void rtc_write (uchar reg, uchar val, boolean_t set);
+static void rtc_write_raw (uchar reg, uchar val);
+
+/*
+ * Get the current time from the RTC
+ */
+void rtc_get (struct rtc_time *tm){
+
+ unsigned long time1, time2;
+ unsigned int limit;
+ unsigned char tmp;
+ unsigned int i;
+
+ /*
+ * Since the reads are being performed one byte at a time,
+ * there is a chance that a carry will occur during the read.
+ * To detect this, 2 reads are performed and compared.
+ */
+ limit = 10;
+ do {
+ i = 4;
+ time1 = 0;
+ while (i--) {
+ tmp = rtc_read(RtcTodAddr[i]);
+ time1 = (time1 << 8) | (tmp & 0xff);
+ }
+
+ i = 4;
+ time2 = 0;
+ while (i--) {
+ tmp = rtc_read(RtcTodAddr[i]);
+ time2 = (time2 << 8) | (tmp & 0xff);
+ }
+ } while ((time1 != time2) && limit--);
+
+ if (time1 != time2) {
+ printf("can't get consistent time from rtc chip\n");
+ }
+
+ DEBUGR ("Get RTC s since 1.1.1970: %d\n", time1);
+
+ to_tm(time1, tm); /* To Gregorian Date */
+
+ if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF)
+ printf ("### Warning: RTC oscillator has stopped\n");
+
+ DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+}
+
+/*
+ * Set the RTC
+ */
+void rtc_set (struct rtc_time *tmp){
+
+ unsigned long time;
+ unsigned i;
+
+ DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
+ printf("WARNING: year should be between 1970 and 2069!\n");
+
+ time = mktime(tmp->tm_year, tmp->tm_mon,
+ tmp->tm_mday, tmp->tm_hour,
+ tmp->tm_min, tmp->tm_sec);
+
+ DEBUGR ("Set RTC s since 1.1.1970: %d (0x%02x)\n", time, time);
+
+ /* write to RTC_TOD_CNT_BYTEn_ADDR */
+ for (i = 0; i <= 3; i++) {
+ rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
+ time = time >> 8;
+ }
+
+ /* Start clock */
+ rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE);
+}
+
+/*
+ * Reset the RTC. We setting the date back to 1970-01-01.
+ * We also enable the oscillator output on the SQW/OUT pin and program
+ * it for 32,768 Hz output. Note that according to the datasheet, turning
+ * on the square wave output increases the current drain on the backup
+ * battery to something between 480nA and 800nA.
+ */
+void rtc_reset (void){
+
+ struct rtc_time tmp;
+
+ /* clear status flags */
+ rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */
+
+ /* Initialise DS1374 oriented to MPC8349E-ADS */
+ rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
+ |RTC_CTL_BIT_WACE
+ |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE
+ - set to 0 */
+ rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
+ |RTC_CTL_BIT_WDSTR
+ |RTC_CTL_BIT_RS1
+ |RTC_CTL_BIT_RS2
+ |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin,
+ set BBSQW and SQW to 32k
+ - set to 1 */
+ tmp.tm_year = 1970;
+ tmp.tm_mon = 1;
+ tmp.tm_mday= 1;
+ tmp.tm_hour = 0;
+ tmp.tm_min = 0;
+ tmp.tm_sec = 0;
+
+ rtc_set(&tmp);
+
+ printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
+ tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+ tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+ rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE);
+ rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE);
+ rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE);
+}
+
+/*
+ * Helper functions
+ */
+static uchar rtc_read (uchar reg)
+{
+ return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg));
+}
+
+static void rtc_write (uchar reg, uchar val, boolean_t set)
+{
+ if (set == TRUE) {
+ val |= i2c_reg_read (CFG_I2C_RTC_ADDR, reg);
+ i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
+ } else {
+ val = i2c_reg_read (CFG_I2C_RTC_ADDR, reg) & ~val;
+ i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
+ }
+}
+
+static void rtc_write_raw (uchar reg, uchar val)
+{
+ i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
+}
+#endif /* (CONFIG_RTC_DS1374) && (CFG_COMMANDS & CFG_CMD_DATE) */
static int setup_done = 0;
static int
-rs5c372_readram(char *buf, int len)
+rs5c372_readram(unsigned char *buf, int len)
{
int ret;
}
static void
-rs5c372_convert_to_time(struct rtc_time *dt, char *buf)
+rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf)
{
/* buf[0] is register 15 */
dt->tm_sec = bcd2bin(buf[1]);
if (!crc1_ok) {
fprintf (stderr,
"Warning: Bad CRC, using default environment\n");
- environment.data = default_environment;
- free (addr1);
+ memcpy(environment.data, default_environment, sizeof default_environment);
}
} else {
flag1 = environment.flags;
} else if (!crc1_ok && !crc2_ok) {
fprintf (stderr,
"Warning: Bad CRC, using default environment\n");
- environment.data = default_environment;
+ memcpy(environment.data, default_environment, sizeof default_environment);
curdev = 0;
- free (addr2);
free (addr1);
} else if (flag1 == active_flag && flag2 == obsolete_flag) {
environment.data = addr1;
{ IH_CPU_SH, "sh", "SuperH", },
{ IH_CPU_SPARC, "sparc", "SPARC", },
{ IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", },
+ { IH_CPU_BLACKFIN, "blackfin", "Blackfin", },
{ -1, "", "", },
};
projects / platform / kernel / u-boot.git / commitdiff