# Grab our configured image. The source for this is found at:
# https://gitlab.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:xenial-20190720-29Jul2019
+image: trini/u-boot-gitlab-ci-runner:xenial-20190720-02Aug2019
# We run some tests in different order, to catch some failures quicker.
stages:
TEST_PY_BD: "qemu_mips"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mips$"
- TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu_mipsel test.py:
TEST_PY_BD: "qemu_mipsel"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mipsel$"
- TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu_mips64 test.py:
TEST_PY_BD: "qemu_mips64"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mips64$"
- TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu_mips64el test.py:
TEST_PY_BD: "qemu_mips64el"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mips64el$"
- TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu-ppce500 test.py:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-ppce500$"
- TOOLCHAIN: "powerpc"
+ <<: *buildman_and_testpy_dfn
+
+qemu-riscv64 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu-riscv64"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-riscv64$"
<<: *buildman_and_testpy_dfn
qemu-x86 test.py:
TEST_PY_BD: "qemu-x86"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-x86$"
- TOOLCHAIN: "i386"
<<: *buildman_and_testpy_dfn
qemu-x86_64 test.py:
TEST_PY_BD: "qemu-x86_64"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-x86_64$"
- TOOLCHAIN: "i386"
<<: *buildman_and_testpy_dfn
zynq_zc702 test.py:
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
BUILDMAN: "^xtfpga$"
- TOOLCHAIN: "xtensa-dc233c-elf"
<<: *buildman_and_testpy_dfn
QEMU_TARGET="ppc-softmmu"
BUILDMAN="^qemu-ppce500$"
TOOLCHAIN="powerpc"
+ - name: "test/py qemu-riscv64"
+ env:
+ - TEST_PY_BD="qemu-riscv64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="riscv64-softmmu"
+ BUILDMAN="^qemu-riscv64$"
+ TOOLCHAIN="riscv"
- name: "test/py qemu-x86"
env:
- TEST_PY_BD="qemu-x86"
ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
+R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
R: Alexander Graf <agraf@csgraf.de>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
-F: doc/README.uefi
-F: doc/README.iscsi
-F: doc/efi.rst
+F: doc/uefi/*
F: include/capitalization.h
F: include/charset.h
F: include/cp1250.h
A better solution is to properly configure the firewall,
but sometimes that is not allowed.
-- Show boot progress:
- CONFIG_SHOW_BOOT_PROGRESS
-
- Defining this option allows to add some board-
- specific code (calling a user-provided function
- "show_boot_progress(int)") that enables you to show
- the system's boot progress on some display (for
- example, some LED's) on your board. At the moment,
- the following checkpoints are implemented:
-
-
-Legacy uImage format:
-
- Arg Where When
- 1 common/cmd_bootm.c before attempting to boot an image
- -1 common/cmd_bootm.c Image header has bad magic number
- 2 common/cmd_bootm.c Image header has correct magic number
- -2 common/cmd_bootm.c Image header has bad checksum
- 3 common/cmd_bootm.c Image header has correct checksum
- -3 common/cmd_bootm.c Image data has bad checksum
- 4 common/cmd_bootm.c Image data has correct checksum
- -4 common/cmd_bootm.c Image is for unsupported architecture
- 5 common/cmd_bootm.c Architecture check OK
- -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi)
- 6 common/cmd_bootm.c Image Type check OK
- -6 common/cmd_bootm.c gunzip uncompression error
- -7 common/cmd_bootm.c Unimplemented compression type
- 7 common/cmd_bootm.c Uncompression OK
- 8 common/cmd_bootm.c No uncompress/copy overwrite error
- -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX)
-
- 9 common/image.c Start initial ramdisk verification
- -10 common/image.c Ramdisk header has bad magic number
- -11 common/image.c Ramdisk header has bad checksum
- 10 common/image.c Ramdisk header is OK
- -12 common/image.c Ramdisk data has bad checksum
- 11 common/image.c Ramdisk data has correct checksum
- 12 common/image.c Ramdisk verification complete, start loading
- -13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
- 13 common/image.c Start multifile image verification
- 14 common/image.c No initial ramdisk, no multifile, continue.
-
- 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
-
- -30 arch/powerpc/lib/board.c Fatal error, hang the system
- -31 post/post.c POST test failed, detected by post_output_backlog()
- -32 post/post.c POST test failed, detected by post_run_single()
-
- 34 common/cmd_doc.c before loading a Image from a DOC device
- -35 common/cmd_doc.c Bad usage of "doc" command
- 35 common/cmd_doc.c correct usage of "doc" command
- -36 common/cmd_doc.c No boot device
- 36 common/cmd_doc.c correct boot device
- -37 common/cmd_doc.c Unknown Chip ID on boot device
- 37 common/cmd_doc.c correct chip ID found, device available
- -38 common/cmd_doc.c Read Error on boot device
- 38 common/cmd_doc.c reading Image header from DOC device OK
- -39 common/cmd_doc.c Image header has bad magic number
- 39 common/cmd_doc.c Image header has correct magic number
- -40 common/cmd_doc.c Error reading Image from DOC device
- 40 common/cmd_doc.c Image header has correct magic number
- 41 common/cmd_ide.c before loading a Image from a IDE device
- -42 common/cmd_ide.c Bad usage of "ide" command
- 42 common/cmd_ide.c correct usage of "ide" command
- -43 common/cmd_ide.c No boot device
- 43 common/cmd_ide.c boot device found
- -44 common/cmd_ide.c Device not available
- 44 common/cmd_ide.c Device available
- -45 common/cmd_ide.c wrong partition selected
- 45 common/cmd_ide.c partition selected
- -46 common/cmd_ide.c Unknown partition table
- 46 common/cmd_ide.c valid partition table found
- -47 common/cmd_ide.c Invalid partition type
- 47 common/cmd_ide.c correct partition type
- -48 common/cmd_ide.c Error reading Image Header on boot device
- 48 common/cmd_ide.c reading Image Header from IDE device OK
- -49 common/cmd_ide.c Image header has bad magic number
- 49 common/cmd_ide.c Image header has correct magic number
- -50 common/cmd_ide.c Image header has bad checksum
- 50 common/cmd_ide.c Image header has correct checksum
- -51 common/cmd_ide.c Error reading Image from IDE device
- 51 common/cmd_ide.c reading Image from IDE device OK
- 52 common/cmd_nand.c before loading a Image from a NAND device
- -53 common/cmd_nand.c Bad usage of "nand" command
- 53 common/cmd_nand.c correct usage of "nand" command
- -54 common/cmd_nand.c No boot device
- 54 common/cmd_nand.c boot device found
- -55 common/cmd_nand.c Unknown Chip ID on boot device
- 55 common/cmd_nand.c correct chip ID found, device available
- -56 common/cmd_nand.c Error reading Image Header on boot device
- 56 common/cmd_nand.c reading Image Header from NAND device OK
- -57 common/cmd_nand.c Image header has bad magic number
- 57 common/cmd_nand.c Image header has correct magic number
- -58 common/cmd_nand.c Error reading Image from NAND device
- 58 common/cmd_nand.c reading Image from NAND device OK
-
- -60 common/env_common.c Environment has a bad CRC, using default
-
- 64 net/eth.c starting with Ethernet configuration.
- -64 net/eth.c no Ethernet found.
- 65 net/eth.c Ethernet found.
-
- -80 common/cmd_net.c usage wrong
- 80 common/cmd_net.c before calling net_loop()
- -81 common/cmd_net.c some error in net_loop() occurred
- 81 common/cmd_net.c net_loop() back without error
- -82 common/cmd_net.c size == 0 (File with size 0 loaded)
- 82 common/cmd_net.c trying automatic boot
- 83 common/cmd_net.c running "source" command
- -83 common/cmd_net.c some error in automatic boot or "source" command
- 84 common/cmd_net.c end without errors
-
-FIT uImage format:
-
- Arg Where When
- 100 common/cmd_bootm.c Kernel FIT Image has correct format
- -100 common/cmd_bootm.c Kernel FIT Image has incorrect format
- 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration
- -101 common/cmd_bootm.c Can't get configuration for kernel subimage
- 102 common/cmd_bootm.c Kernel unit name specified
- -103 common/cmd_bootm.c Can't get kernel subimage node offset
- 103 common/cmd_bootm.c Found configuration node
- 104 common/cmd_bootm.c Got kernel subimage node offset
- -104 common/cmd_bootm.c Kernel subimage hash verification failed
- 105 common/cmd_bootm.c Kernel subimage hash verification OK
- -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
- 106 common/cmd_bootm.c Architecture check OK
- -106 common/cmd_bootm.c Kernel subimage has wrong type
- 107 common/cmd_bootm.c Kernel subimage type OK
- -107 common/cmd_bootm.c Can't get kernel subimage data/size
- 108 common/cmd_bootm.c Got kernel subimage data/size
- -108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
- -109 common/cmd_bootm.c Can't get kernel subimage type
- -110 common/cmd_bootm.c Can't get kernel subimage comp
- -111 common/cmd_bootm.c Can't get kernel subimage os
- -112 common/cmd_bootm.c Can't get kernel subimage load address
- -113 common/cmd_bootm.c Image uncompress/copy overwrite error
-
- 120 common/image.c Start initial ramdisk verification
- -120 common/image.c Ramdisk FIT image has incorrect format
- 121 common/image.c Ramdisk FIT image has correct format
- 122 common/image.c No ramdisk subimage unit name, using configuration
- -122 common/image.c Can't get configuration for ramdisk subimage
- 123 common/image.c Ramdisk unit name specified
- -124 common/image.c Can't get ramdisk subimage node offset
- 125 common/image.c Got ramdisk subimage node offset
- -125 common/image.c Ramdisk subimage hash verification failed
- 126 common/image.c Ramdisk subimage hash verification OK
- -126 common/image.c Ramdisk subimage for unsupported architecture
- 127 common/image.c Architecture check OK
- -127 common/image.c Can't get ramdisk subimage data/size
- 128 common/image.c Got ramdisk subimage data/size
- 129 common/image.c Can't get ramdisk load address
- -129 common/image.c Got ramdisk load address
-
- -130 common/cmd_doc.c Incorrect FIT image format
- 131 common/cmd_doc.c FIT image format OK
-
- -140 common/cmd_ide.c Incorrect FIT image format
- 141 common/cmd_ide.c FIT image format OK
-
- -150 common/cmd_nand.c Incorrect FIT image format
- 151 common/cmd_nand.c FIT image format OK
-
-- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
This option defines a board specific value for the
allowed for use by the bootm command. See also "bootm_low"
environment variable.
+ bootstopkeysha256, bootdelaykey, bootstopkey - See README.autoboot
+
updatefile - Location of the software update file on a TFTP server, used
by the automatic software update feature. Please refer to
documentation in doc/README.update for more details.
meson-gxl-s905x-khadas-vim.dtb \
meson-gxm-khadas-vim2.dtb \
meson-axg-s400.dtb \
- meson-g12a-u200.dtb
+ meson-g12a-u200.dtb \
+ meson-g12b-odroid-n2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
+ avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-zcu104-revC.dtb \
zynqmp-zcu106-revA.dtb \
zynqmp-zcu111-revA.dtb \
+ zynqmp-zcu1275-revA.dtb \
+ zynqmp-zcu1275-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
- zynqmp-zc1275-revA.dtb \
- zynqmp-zc1275-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm017-dc3.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/*
+ * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM)
+ * http://ultrazed.org/product/ultrazed-ev-carrier-card
+ */
+
+/dts-v1/;
+
+#include "avnet-ultrazedev-som-v1.0.dtsi"
+
+/ {
+ model = "Avnet UltraZed EV Carrier Card v1.0";
+ compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0",
+ "xlnx,zynqmp";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
+ };
+ aliases {
+ ethernet0 = &gem3;
+ serial0 = &uart0;
+ };
+};
+
+&uart0 {
+ device_type = "serial";
+ status = "okay";
+};
+
+&i2c_cc {
+ /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
+ eeprom: eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ /* IDT Versa Clock 5P49V5935B */
+ vc5: clock-generator@6a {
+ compatible = "idt,5p49v5935";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+ };
+};
+
+/* Ethernet RJ-45 */
+&gem3 {
+ status = "okay";
+};
+
+/* microSD card slot */
+&sdhci1 {
+ status = "okay";
+ xlnx,mio_bank = <1>;
+ clock-frequency = <199998000>;
+ max-frequency = <50000000>;
+ no-1-8-v;
+ disable-wp;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/*
+ * UltraZed-EV SoM v1
+ * http://ultrazed.org/product/ultrazed-ev
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "Avnet UltraZed EV SoM v1.0";
+ compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
+ <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ i2cswitch@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ /* I2C connected to Carrier Card via JX3A1/JX3C1 */
+ i2c_cc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
+&gem3 {
+ phy-mode = "rgmii-id";
+ phy-handle = <&gem3phy>;
+ gem3phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
+&sdhci0 {
+ status = "okay";
+ xlnx,mio_bank = <0>;
+ clock-frequency = <199998000>;
+};
};
};
+ð0 {
+ pinctrl-0 = <&mii_pins>, <&mdio_pins>;
+};
+
&flash {
compatible = "m25p64", "jedec,spi-nor";
};
dma-coherent;
clocks = <&k3_clks 5 10>;
clock-names = "fck";
- power-domains = <&k3_pds 5>;
+ power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
ti,psil-base = <0x7000>;
dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/ {
- soc {
- ethmac: ethernet@ff3f0000 {
- compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710",
- "snps,dwmac";
- reg = <0x0 0xff3f0000 0x0 0x10000
- 0x0 0xff634540 0x0 0x8>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
- status = "disabled";
-
- mdio0: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- };
- };
-
- sd_emmc_a: sd@ffe03000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe03000 0x0 0x800>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_A>,
- <&clkc CLKID_SD_EMMC_A_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_A>;
- };
-
- sd_emmc_b: sd@ffe05000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe05000 0x0 0x800>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_B>,
- <&clkc CLKID_SD_EMMC_B_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_B>;
- };
-
- sd_emmc_c: mmc@ffe07000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe07000 0x0 0x800>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_C>,
- <&clkc CLKID_SD_EMMC_C_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_C>;
- };
- };
-};
-
-&periphs_pinctrl {
- emmc_pins: emmc {
- mux {
- groups = "emmc_nand_d0",
- "emmc_nand_d1",
- "emmc_nand_d2",
- "emmc_nand_d3",
- "emmc_nand_d4",
- "emmc_nand_d5",
- "emmc_nand_d6",
- "emmc_nand_d7",
- "emmc_clk",
- "emmc_cmd";
- function = "emmc";
- bias-pull-up;
- };
- };
-
- emmc_ds_pins: emmc-ds {
- mux {
- groups = "emmc_nand_ds";
- function = "emmc";
- bias-pull-down;
- };
- };
-
- emmc_clk_gate_pins: emmc_clk_gate {
- mux {
- groups = "BOOT_8";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- eth_leds_pins: eth-leds {
- mux {
- groups = "eth_link_led",
- "eth_act_led";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_rmii_pins: eth-rmii {
- mux {
- groups = "eth_mdio",
- "eth_mdc",
- "eth_rgmii_rx_clk",
- "eth_rx_dv",
- "eth_rxd0",
- "eth_rxd1",
- "eth_txen",
- "eth_txd0",
- "eth_txd1";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_rgmii_pins: eth-rgmii {
- mux {
- groups = "eth_rxd2_rgmii",
- "eth_rxd3_rgmii",
- "eth_rgmii_tx_clk",
- "eth_txd2_rgmii",
- "eth_txd3_rgmii";
- function = "eth";
- bias-disable;
- };
- };
-
- sdcard_c_pins: sdcard_c {
- mux {
- groups = "sdcard_d0_c",
- "sdcard_d1_c",
- "sdcard_d2_c",
- "sdcard_d3_c",
- "sdcard_cmd_c",
- "sdcard_clk_c";
- function = "sdcard";
- bias-pull-up;
- };
- };
-
- sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
- mux {
- groups = "GPIOC_4";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- sdcard_z_pins: sdcard_z {
- mux {
- groups = "sdcard_d0_z",
- "sdcard_d1_z",
- "sdcard_d2_z",
- "sdcard_d3_z",
- "sdcard_cmd_z",
- "sdcard_clk_z";
- function = "sdcard";
- bias-pull-up;
- };
- };
-
- sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
- mux {
- groups = "GPIOZ_6";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-};
-
-&periphs {
- eth_phy: mdio-multiplexer@4c000 {
- compatible = "amlogic,g12a-mdio-mux";
- reg = <0x0 0x4c000 0x0 0xa4>;
- clocks = <&clkc CLKID_ETH_PHY>,
- <&xtal>,
- <&clkc CLKID_MPLL_5OM>;
- clock-names = "pclk", "clkin0", "clkin1";
- mdio-parent-bus = <&mdio0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ext_mdio: mdio@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- int_mdio: mdio@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- internal_ephy: ethernet_phy@8 {
- compatible = "ethernet-phy-id0180.3300",
- "ethernet-phy-ieee802.3-c22";
- reg = <8>;
- max-speed = <100>;
-
- /* FIXME: Add irq support */
- };
- };
- };
-};
-
-
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-g12a-u-boot.dtsi"
-
- / {
- aliases {
- ethernet0 = ðmac;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-};
-
-ðmac {
- status = "okay";
- pinctrl-0 = <ð_leds_pins>;
- pinctrl-names = "default";
- phy-handle = <&internal_ephy>;
- phy-mode = "rmii";
-};
-
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
aliases {
serial0 = &uart_AO;
+ ethernet0 = ðmac;
};
+
chosen {
stdout-path = "serial0:115200n8";
};
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
cvbs-connector {
compatible = "composite-video-connector";
};
};
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
};
};
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-always-on;
};
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
enable-active-high;
};
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
};
};
+ðmac {
+ status = "okay";
+ phy-handle = <&internal_ephy>;
+ phy-mode = "rmii";
+};
+
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
};
};
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+/* i2c Touch */
+&i2c0 {
+ status = "okay";
+ pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>;
+ pinctrl-names = "default";
+};
+
+/* i2c CM */
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>;
+ pinctrl-names = "default";
+};
+
+/* i2c Audio */
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/axg-audio-clkc.h>
#include <dt-bindings/clock/g12a-clkc.h>
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
+ tdmif_a: audio-controller-0 {
+ compatible = "amlogic,axg-tdm-iface";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TDM_A";
+ clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
+ clock-names = "mclk", "sclk", "lrclk";
+ status = "disabled";
+ };
+
+ tdmif_b: audio-controller-1 {
+ compatible = "amlogic,axg-tdm-iface";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TDM_B";
+ clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
+ clock-names = "mclk", "sclk", "lrclk";
+ status = "disabled";
+ };
+
+ tdmif_c: audio-controller-2 {
+ compatible = "amlogic,axg-tdm-iface";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TDM_C";
+ clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
+ clock-names = "mclk", "sclk", "lrclk";
+ status = "disabled";
+ };
+
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
#size-cells = <2>;
ranges;
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,meson-axg-dwmac",
+ "snps,dwmac-3.70a",
+ "snps,dwmac";
+ reg = <0x0 0xff3f0000 0x0 0x10000
+ 0x0 0xff634540 0x0 0x8>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ status = "disabled";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+ };
+
apb: bus@ff600000 {
compatible = "simple-bus";
reg = <0x0 0xff600000 0x0 0x200000>;
clock-names = "isfr", "iahb", "venci";
#address-cells = <1>;
#size-cells = <0>;
+ #sound-dai-cells = <0>;
status = "disabled";
/* VPU VENC Input */
};
};
+ apb_efuse: bus@30000 {
+ compatible = "simple-bus";
+ reg = <0x0 0x30000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
+
+ hwrng: rng@218 {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x218 0x0 0x4>;
+ };
+ };
+
periphs: bus@34400 {
compatible = "simple-bus";
reg = <0x0 0x34400 0x0 0x400>;
gpio-ranges = <&periphs_pinctrl 0 0 86>;
};
- cec_ao_a_h_pins: cec_ao_a_h {
+ cec_ao_a_h_pins: cec_ao_a_h {
+ mux {
+ groups = "cec_ao_a_h";
+ function = "cec_ao_a_h";
+ bias-disable;
+ };
+ };
+
+ cec_ao_b_h_pins: cec_ao_b_h {
+ mux {
+ groups = "cec_ao_b_h";
+ function = "cec_ao_b_h";
+ bias-disable;
+ };
+ };
+
+ emmc_pins: emmc {
+ mux-0 {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ mux-1 {
+ groups = "emmc_clk";
+ function = "emmc";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ emmc_ds_pins: emmc-ds {
+ mux {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "BOOT_8";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ hdmitx_ddc_pins: hdmitx_ddc {
+ mux {
+ groups = "hdmitx_sda",
+ "hdmitx_sck";
+ function = "hdmitx";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ hdmitx_hpd_pins: hdmitx_hpd {
+ mux {
+ groups = "hdmitx_hpd_in";
+ function = "hdmitx";
+ bias-disable;
+ };
+ };
+
+
+ i2c0_sda_c_pins: i2c0-sda-c {
+ mux {
+ groups = "i2c0_sda_c";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+
+ };
+ };
+
+ i2c0_sck_c_pins: i2c0-sck-c {
+ mux {
+ groups = "i2c0_sck_c";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sda_z0_pins: i2c0-sda-z0 {
+ mux {
+ groups = "i2c0_sda_z0";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sck_z1_pins: i2c0-sck-z1 {
+ mux {
+ groups = "i2c0_sck_z1";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sda_z7_pins: i2c0-sda-z7 {
+ mux {
+ groups = "i2c0_sda_z7";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sda_z8_pins: i2c0-sda-z8 {
+ mux {
+ groups = "i2c0_sda_z8";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sda_x_pins: i2c1-sda-x {
+ mux {
+ groups = "i2c1_sda_x";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sck_x_pins: i2c1-sck-x {
+ mux {
+ groups = "i2c1_sck_x";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sda_h2_pins: i2c1-sda-h2 {
+ mux {
+ groups = "i2c1_sda_h2";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sck_h3_pins: i2c1-sck-h3 {
+ mux {
+ groups = "i2c1_sck_h3";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sda_h6_pins: i2c1-sda-h6 {
+ mux {
+ groups = "i2c1_sda_h6";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sck_h7_pins: i2c1-sck-h7 {
+ mux {
+ groups = "i2c1_sck_h7";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sda_x_pins: i2c2-sda-x {
+ mux {
+ groups = "i2c2_sda_x";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sck_x_pins: i2c2-sck-x {
+ mux {
+ groups = "i2c2_sck_x";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sda_z_pins: i2c2-sda-z {
+ mux {
+ groups = "i2c2_sda_z";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sck_z_pins: i2c2-sck-z {
+ mux {
+ groups = "i2c2_sck_z";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sda_h_pins: i2c3-sda-h {
+ mux {
+ groups = "i2c3_sda_h";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sck_h_pins: i2c3-sck-h {
+ mux {
+ groups = "i2c3_sck_h";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sda_a_pins: i2c3-sda-a {
+ mux {
+ groups = "i2c3_sda_a";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sck_a_pins: i2c3-sck-a {
+ mux {
+ groups = "i2c3_sck_a";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk0_a_pins: mclk0-a {
+ mux {
+ groups = "mclk0_a";
+ function = "mclk0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk1_a_pins: mclk1-a {
+ mux {
+ groups = "mclk1_a";
+ function = "mclk1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk1_x_pins: mclk1-x {
+ mux {
+ groups = "mclk1_x";
+ function = "mclk1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk1_z_pins: mclk1-z {
+ mux {
+ groups = "mclk1_z";
+ function = "mclk1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ pdm_din0_a_pins: pdm-din0-a {
+ mux {
+ groups = "pdm_din0_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din0_c_pins: pdm-din0-c {
+ mux {
+ groups = "pdm_din0_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din0_x_pins: pdm-din0-x {
+ mux {
+ groups = "pdm_din0_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din0_z_pins: pdm-din0-z {
+ mux {
+ groups = "pdm_din0_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_a_pins: pdm-din1-a {
+ mux {
+ groups = "pdm_din1_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_c_pins: pdm-din1-c {
+ mux {
+ groups = "pdm_din1_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_x_pins: pdm-din1-x {
+ mux {
+ groups = "pdm_din1_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_z_pins: pdm-din1-z {
+ mux {
+ groups = "pdm_din1_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_a_pins: pdm-din2-a {
+ mux {
+ groups = "pdm_din2_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_c_pins: pdm-din2-c {
+ mux {
+ groups = "pdm_din2_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_x_pins: pdm-din2-x {
+ mux {
+ groups = "pdm_din2_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_z_pins: pdm-din2-z {
+ mux {
+ groups = "pdm_din2_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_a_pins: pdm-din3-a {
+ mux {
+ groups = "pdm_din3_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_c_pins: pdm-din3-c {
+ mux {
+ groups = "pdm_din3_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_x_pins: pdm-din3-x {
+ mux {
+ groups = "pdm_din3_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_z_pins: pdm-din3-z {
+ mux {
+ groups = "pdm_din3_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_dclk_a_pins: pdm-dclk-a {
+ mux {
+ groups = "pdm_dclk_a";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pdm_dclk_c_pins: pdm-dclk-c {
+ mux {
+ groups = "pdm_dclk_c";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pdm_dclk_x_pins: pdm-dclk-x {
+ mux {
+ groups = "pdm_dclk_x";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pdm_dclk_z_pins: pdm-dclk-z {
+ mux {
+ groups = "pdm_dclk_z";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pwm_a_pins: pwm-a {
+ mux {
+ groups = "pwm_a";
+ function = "pwm_a";
+ bias-disable;
+ };
+ };
+
+ pwm_b_x7_pins: pwm-b-x7 {
+ mux {
+ groups = "pwm_b_x7";
+ function = "pwm_b";
+ bias-disable;
+ };
+ };
+
+ pwm_b_x19_pins: pwm-b-x19 {
+ mux {
+ groups = "pwm_b_x19";
+ function = "pwm_b";
+ bias-disable;
+ };
+ };
+
+ pwm_c_c_pins: pwm-c-c {
+ mux {
+ groups = "pwm_c_c";
+ function = "pwm_c";
+ bias-disable;
+ };
+ };
+
+ pwm_c_x5_pins: pwm-c-x5 {
+ mux {
+ groups = "pwm_c_x5";
+ function = "pwm_c";
+ bias-disable;
+ };
+ };
+
+ pwm_c_x8_pins: pwm-c-x8 {
+ mux {
+ groups = "pwm_c_x8";
+ function = "pwm_c";
+ bias-disable;
+ };
+ };
+
+ pwm_d_x3_pins: pwm-d-x3 {
+ mux {
+ groups = "pwm_d_x3";
+ function = "pwm_d";
+ bias-disable;
+ };
+ };
+
+ pwm_d_x6_pins: pwm-d-x6 {
+ mux {
+ groups = "pwm_d_x6";
+ function = "pwm_d";
+ bias-disable;
+ };
+ };
+
+ pwm_e_pins: pwm-e {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ bias-disable;
+ };
+ };
+
+ pwm_f_x_pins: pwm-f-x {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ bias-disable;
+ };
+ };
+
+ pwm_f_h_pins: pwm-f-h {
+ mux {
+ groups = "pwm_f_h";
+ function = "pwm_f";
+ bias-disable;
+ };
+ };
+
+ sdcard_c_pins: sdcard_c {
+ mux-0 {
+ groups = "sdcard_d0_c",
+ "sdcard_d1_c",
+ "sdcard_d2_c",
+ "sdcard_d3_c",
+ "sdcard_cmd_c";
+ function = "sdcard";
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ mux-1 {
+ groups = "sdcard_clk_c";
+ function = "sdcard";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
+ mux {
+ groups = "GPIOC_4";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdcard_z_pins: sdcard_z {
+ mux-0 {
+ groups = "sdcard_d0_z",
+ "sdcard_d1_z",
+ "sdcard_d2_z",
+ "sdcard_d3_z",
+ "sdcard_cmd_z";
+ function = "sdcard";
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ mux-1 {
+ groups = "sdcard_clk_z";
+ function = "sdcard";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
+ mux {
+ groups = "GPIOZ_6";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdio_pins: sdio {
+ mux {
+ groups = "sdio_d0",
+ "sdio_d1",
+ "sdio_d2",
+ "sdio_d3",
+ "sdio_clk",
+ "sdio_cmd";
+ function = "sdio";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdio_clk_gate_pins: sdio_clk_gate {
+ mux {
+ groups = "GPIOX_4";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ spdif_in_a10_pins: spdif-in-a10 {
+ mux {
+ groups = "spdif_in_a10";
+ function = "spdif_in";
+ bias-disable;
+ };
+ };
+
+ spdif_in_a12_pins: spdif-in-a12 {
+ mux {
+ groups = "spdif_in_a12";
+ function = "spdif_in";
+ bias-disable;
+ };
+ };
+
+ spdif_in_h_pins: spdif-in-h {
+ mux {
+ groups = "spdif_in_h";
+ function = "spdif_in";
+ bias-disable;
+ };
+ };
+
+ spdif_out_h_pins: spdif-out-h {
+ mux {
+ groups = "spdif_out_h";
+ function = "spdif_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ spdif_out_a11_pins: spdif-out-a11 {
+ mux {
+ groups = "spdif_out_a11";
+ function = "spdif_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ spdif_out_a13_pins: spdif-out-a13 {
+ mux {
+ groups = "spdif_out_a13";
+ function = "spdif_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ tdm_a_din0_pins: tdm-a-din0 {
+ mux {
+ groups = "tdm_a_din0";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+
+ tdm_a_din1_pins: tdm-a-din1 {
+ mux {
+ groups = "tdm_a_din1";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+ tdm_a_dout0_pins: tdm-a-dout0 {
+ mux {
+ groups = "tdm_a_dout0";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_dout1_pins: tdm-a-dout1 {
+ mux {
+ groups = "tdm_a_dout1";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_fs_pins: tdm-a-fs {
+ mux {
+ groups = "tdm_a_fs";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_sclk_pins: tdm-a-sclk {
+ mux {
+ groups = "tdm_a_sclk";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_slv_fs_pins: tdm-a-slv-fs {
+ mux {
+ groups = "tdm_a_slv_fs";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+
+ tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
+ mux {
+ groups = "tdm_a_slv_sclk";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din0_pins: tdm-b-din0 {
+ mux {
+ groups = "tdm_b_din0";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din1_pins: tdm-b-din1 {
+ mux {
+ groups = "tdm_b_din1";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din2_pins: tdm-b-din2 {
+ mux {
+ groups = "tdm_b_din2";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din3_a_pins: tdm-b-din3-a {
+ mux {
+ groups = "tdm_b_din3_a";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din3_h_pins: tdm-b-din3-h {
+ mux {
+ groups = "tdm_b_din3_h";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_dout0_pins: tdm-b-dout0 {
+ mux {
+ groups = "tdm_b_dout0";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout1_pins: tdm-b-dout1 {
+ mux {
+ groups = "tdm_b_dout1";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout2_pins: tdm-b-dout2 {
+ mux {
+ groups = "tdm_b_dout2";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout3_a_pins: tdm-b-dout3-a {
+ mux {
+ groups = "tdm_b_dout3_a";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout3_h_pins: tdm-b-dout3-h {
+ mux {
+ groups = "tdm_b_dout3_h";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_fs_pins: tdm-b-fs {
+ mux {
+ groups = "tdm_b_fs";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_sclk_pins: tdm-b-sclk {
+ mux {
+ groups = "tdm_b_sclk";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_slv_fs_pins: tdm-b-slv-fs {
+ mux {
+ groups = "tdm_b_slv_fs";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
+ mux {
+ groups = "tdm_b_slv_sclk";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din0_a_pins: tdm-c-din0-a {
+ mux {
+ groups = "tdm_c_din0_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din0_z_pins: tdm-c-din0-z {
+ mux {
+ groups = "tdm_c_din0_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din1_a_pins: tdm-c-din1-a {
+ mux {
+ groups = "tdm_c_din1_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din1_z_pins: tdm-c-din1-z {
+ mux {
+ groups = "tdm_c_din1_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din2_a_pins: tdm-c-din2-a {
+ mux {
+ groups = "tdm_c_din2_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ eth_leds_pins: eth-leds {
+ mux {
+ groups = "eth_link_led",
+ "eth_act_led";
+ function = "eth";
+ bias-disable;
+ };
+ };
+
+ eth_pins: eth {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rgmii_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1";
+ function = "eth";
+ drive-strength-microamp = <4000>;
+ bias-disable;
+ };
+ };
+
+ eth_rgmii_pins: eth-rgmii {
+ mux {
+ groups = "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ drive-strength-microamp = <4000>;
+ bias-disable;
+ };
+ };
+
+ tdm_c_din2_z_pins: tdm-c-din2-z {
+ mux {
+ groups = "tdm_c_din2_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din3_a_pins: tdm-c-din3-a {
+ mux {
+ groups = "tdm_c_din3_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din3_z_pins: tdm-c-din3-z {
+ mux {
+ groups = "tdm_c_din3_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_dout0_a_pins: tdm-c-dout0-a {
+ mux {
+ groups = "tdm_c_dout0_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout0_z_pins: tdm-c-dout0-z {
+ mux {
+ groups = "tdm_c_dout0_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout1_a_pins: tdm-c-dout1-a {
+ mux {
+ groups = "tdm_c_dout1_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout1_z_pins: tdm-c-dout1-z {
+ mux {
+ groups = "tdm_c_dout1_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout2_a_pins: tdm-c-dout2-a {
+ mux {
+ groups = "tdm_c_dout2_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout2_z_pins: tdm-c-dout2-z {
+ mux {
+ groups = "tdm_c_dout2_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout3_a_pins: tdm-c-dout3-a {
+ mux {
+ groups = "tdm_c_dout3_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout3_z_pins: tdm-c-dout3-z {
+ mux {
+ groups = "tdm_c_dout3_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_fs_a_pins: tdm-c-fs-a {
+ mux {
+ groups = "tdm_c_fs_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_fs_z_pins: tdm-c-fs-z {
+ mux {
+ groups = "tdm_c_fs_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_sclk_a_pins: tdm-c-sclk-a {
mux {
- groups = "cec_ao_a_h";
- function = "cec_ao_a_h";
+ groups = "tdm_c_sclk_a";
+ function = "tdm_c";
bias-disable;
+ drive-strength-microamp = <3000>;
};
};
- cec_ao_b_h_pins: cec_ao_b_h {
+ tdm_c_sclk_z_pins: tdm-c-sclk-z {
mux {
- groups = "cec_ao_b_h";
- function = "cec_ao_b_h";
+ groups = "tdm_c_sclk_z";
+ function = "tdm_c";
bias-disable;
+ drive-strength-microamp = <3000>;
};
};
- hdmitx_ddc_pins: hdmitx_ddc {
+ tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
mux {
- groups = "hdmitx_sda",
- "hdmitx_sck";
- function = "hdmitx";
+ groups = "tdm_c_slv_fs_a";
+ function = "tdm_c";
bias-disable;
};
};
- hdmitx_hpd_pins: hdmitx_hpd {
+ tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
mux {
- groups = "hdmitx_hpd_in";
- function = "hdmitx";
+ groups = "tdm_c_slv_fs_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
+ mux {
+ groups = "tdm_c_slv_sclk_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
+ mux {
+ groups = "tdm_c_slv_sclk_z";
+ function = "tdm_c";
bias-disable;
};
};
};
};
+ pdm: audio-controller@40000 {
+ compatible = "amlogic,g12a-pdm",
+ "amlogic,axg-pdm";
+ reg = <0x0 0x40000 0x0 0x34>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "PDM";
+ clocks = <&clkc_audio AUD_CLKID_PDM>,
+ <&clkc_audio AUD_CLKID_PDM_DCLK>,
+ <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
+ clock-names = "pclk", "dclk", "sysclk";
+ status = "disabled";
+ };
+
+ audio: bus@42000 {
+ compatible = "simple-bus";
+ reg = <0x0 0x42000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
+
+ clkc_audio: clock-controller@0 {
+ status = "disabled";
+ compatible = "amlogic,g12a-audio-clkc";
+ reg = <0x0 0x0 0x0 0xb4>;
+ #clock-cells = <1>;
+
+ clocks = <&clkc CLKID_AUDIO>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL3>,
+ <&clkc CLKID_HIFI_PLL>,
+ <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_GP0_PLL>;
+ clock-names = "pclk",
+ "mst_in0",
+ "mst_in1",
+ "mst_in2",
+ "mst_in3",
+ "mst_in4",
+ "mst_in5",
+ "mst_in6",
+ "mst_in7";
+
+ resets = <&reset RESET_AUDIO>;
+ };
+
+ toddr_a: audio-controller@100 {
+ compatible = "amlogic,g12a-toddr",
+ "amlogic,axg-toddr";
+ reg = <0x0 0x100 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_A";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
+ resets = <&arb AXG_ARB_TODDR_A>;
+ status = "disabled";
+ };
+
+ toddr_b: audio-controller@140 {
+ compatible = "amlogic,g12a-toddr",
+ "amlogic,axg-toddr";
+ reg = <0x0 0x140 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_B";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
+ resets = <&arb AXG_ARB_TODDR_B>;
+ status = "disabled";
+ };
+
+ toddr_c: audio-controller@180 {
+ compatible = "amlogic,g12a-toddr",
+ "amlogic,axg-toddr";
+ reg = <0x0 0x180 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_C";
+ interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
+ resets = <&arb AXG_ARB_TODDR_C>;
+ status = "disabled";
+ };
+
+ frddr_a: audio-controller@1c0 {
+ compatible = "amlogic,g12a-frddr",
+ "amlogic,axg-frddr";
+ reg = <0x0 0x1c0 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_A";
+ interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+ resets = <&arb AXG_ARB_FRDDR_A>;
+ status = "disabled";
+ };
+
+ frddr_b: audio-controller@200 {
+ compatible = "amlogic,g12a-frddr",
+ "amlogic,axg-frddr";
+ reg = <0x0 0x200 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_B";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
+ resets = <&arb AXG_ARB_FRDDR_B>;
+ status = "disabled";
+ };
+
+ frddr_c: audio-controller@240 {
+ compatible = "amlogic,g12a-frddr",
+ "amlogic,axg-frddr";
+ reg = <0x0 0x240 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_C";
+ interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
+ resets = <&arb AXG_ARB_FRDDR_C>;
+ status = "disabled";
+ };
+
+ arb: reset-controller@280 {
+ status = "disabled";
+ compatible = "amlogic,meson-axg-audio-arb";
+ reg = <0x0 0x280 0x0 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+ };
+
+ tdmin_a: audio-controller@300 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x300 0x0 0x40>;
+ sound-name-prefix = "TDMIN_A";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmin_b: audio-controller@340 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x340 0x0 0x40>;
+ sound-name-prefix = "TDMIN_B";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmin_c: audio-controller@380 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x380 0x0 0x40>;
+ sound-name-prefix = "TDMIN_C";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmin_lb: audio-controller@3c0 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x3c0 0x0 0x40>;
+ sound-name-prefix = "TDMIN_LB";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ spdifin: audio-controller@400 {
+ compatible = "amlogic,g12a-spdifin",
+ "amlogic,axg-spdifin";
+ reg = <0x0 0x400 0x0 0x30>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFIN";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
+ <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
+ clock-names = "pclk", "refclk";
+ status = "disabled";
+ };
+
+ spdifout: audio-controller@480 {
+ compatible = "amlogic,g12a-spdifout",
+ "amlogic,axg-spdifout";
+ reg = <0x0 0x480 0x0 0x50>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFOUT";
+ clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
+ <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
+ clock-names = "pclk", "mclk";
+ status = "disabled";
+ };
+
+ tdmout_a: audio-controller@500 {
+ compatible = "amlogic,g12a-tdmout";
+ reg = <0x0 0x500 0x0 0x40>;
+ sound-name-prefix = "TDMOUT_A";
+ clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmout_b: audio-controller@540 {
+ compatible = "amlogic,g12a-tdmout";
+ reg = <0x0 0x540 0x0 0x40>;
+ sound-name-prefix = "TDMOUT_B";
+ clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmout_c: audio-controller@580 {
+ compatible = "amlogic,g12a-tdmout";
+ reg = <0x0 0x580 0x0 0x40>;
+ sound-name-prefix = "TDMOUT_C";
+ clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ spdifout_b: audio-controller@680 {
+ compatible = "amlogic,g12a-spdifout",
+ "amlogic,axg-spdifout";
+ reg = <0x0 0x680 0x0 0x50>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFOUT_B";
+ clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>,
+ <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>;
+ clock-names = "pclk", "mclk";
+ status = "disabled";
+ };
+
+ tohdmitx: audio-controller@744 {
+ compatible = "amlogic,g12a-tohdmitx";
+ reg = <0x0 0x744 0x0 0x4>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "TOHDMITX";
+ status = "disabled";
+ };
+ };
+
usb3_pcie_phy: phy@46000 {
compatible = "amlogic,g12a-usb3-pcie-phy";
reg = <0x0 0x46000 0x0 0x2000>;
assigned-clock-rates = <100000000>;
#phy-cells = <1>;
};
+
+ eth_phy: mdio-multiplexer@4c000 {
+ compatible = "amlogic,g12a-mdio-mux";
+ reg = <0x0 0x4c000 0x0 0xa4>;
+ clocks = <&clkc CLKID_ETH_PHY>,
+ <&xtal>,
+ <&clkc CLKID_MPLL_50M>;
+ clock-names = "pclk", "clkin0", "clkin1";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ext_mdio: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_ephy: ethernet_phy@8 {
+ compatible = "ethernet-phy-id0180.3301",
+ "ethernet-phy-ieee802.3-c22";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+ };
};
aobus: bus@ff800000 {
gpio-ranges = <&ao_pinctrl 0 0 15>;
};
+ i2c_ao_sck_pins: i2c_ao_sck_pins {
+ mux {
+ groups = "i2c_ao_sck";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c_ao_sda_pins: i2c_ao_sda {
+ mux {
+ groups = "i2c_ao_sda";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c_ao_sck_e_pins: i2c_ao_sck_e {
+ mux {
+ groups = "i2c_ao_sck_e";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c_ao_sda_e_pins: i2c_ao_sda_e {
+ mux {
+ groups = "i2c_ao_sda_e";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk0_ao_pins: mclk0-ao {
+ mux {
+ groups = "mclk0_ao";
+ function = "mclk0_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_din0_pins: tdm-ao-b-din0 {
+ mux {
+ groups = "tdm_ao_b_din0";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ spdif_ao_out_pins: spdif-ao-out {
+ mux {
+ groups = "spdif_ao_out";
+ function = "spdif_ao_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_din1_pins: tdm-ao-b-din1 {
+ mux {
+ groups = "tdm_ao_b_din1";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_din2_pins: tdm-ao-b-din2 {
+ mux {
+ groups = "tdm_ao_b_din2";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
+ mux {
+ groups = "tdm_ao_b_dout0";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
+ mux {
+ groups = "tdm_ao_b_dout1";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
+ mux {
+ groups = "tdm_ao_b_dout2";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_fs_pins: tdm-ao-b-fs {
+ mux {
+ groups = "tdm_ao_b_fs";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
+ mux {
+ groups = "tdm_ao_b_sclk";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
+ mux {
+ groups = "tdm_ao_b_slv_fs";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
+ mux {
+ groups = "tdm_ao_b_slv_sclk";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
uart_ao_a_pins: uart-a-ao {
mux {
groups = "uart_ao_a_tx",
bias-disable;
};
};
+
+ pwm_ao_a_pins: pwm-ao-a {
+ mux {
+ groups = "pwm_ao_a";
+ function = "pwm_ao_a";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_b_pins: pwm-ao-b {
+ mux {
+ groups = "pwm_ao_b";
+ function = "pwm_ao_b";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_c_4_pins: pwm-ao-c-4 {
+ mux {
+ groups = "pwm_ao_c_4";
+ function = "pwm_ao_c";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_c_6_pins: pwm-ao-c-6 {
+ mux {
+ groups = "pwm_ao_c_6";
+ function = "pwm_ao_c";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_d_5_pins: pwm-ao-d-5 {
+ mux {
+ groups = "pwm_ao_d_5";
+ function = "pwm_ao_d";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_d_10_pins: pwm-ao-d-10 {
+ mux {
+ groups = "pwm_ao_d_10";
+ function = "pwm_ao_d";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_d_e_pins: pwm-ao-d-e {
+ mux {
+ groups = "pwm_ao_d_e";
+ function = "pwm_ao_d";
+ };
+ };
+
+ remote_input_ao_pins: remote-input-ao {
+ mux {
+ groups = "remote_ao_input";
+ function = "remote_ao_input";
+ bias-disable;
+ };
+ };
};
};
status = "disabled";
};
+ pwm_AO_cd: pwm@2000 {
+ compatible = "amlogic,meson-g12a-ao-pwm-cd";
+ reg = <0x0 0x2000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
"amlogic,meson-ao-uart";
reg = <0x0 0x4000 0x0 0x18>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+ i2c_AO: i2c@5000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x05000 0x0 0x20>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ pwm_AO_ab: pwm@7000 {
+ compatible = "amlogic,meson-g12a-ao-pwm-ab";
+ reg = <0x0 0x7000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir: ir@8000 {
+ compatible = "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x8000 0x0 0x20>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
saradc: adc@9000 {
compatible = "amlogic,meson-g12a-saradc",
"amlogic,meson-saradc";
#reset-cells = <1>;
};
+ gpio_intc: interrupt-controller@f080 {
+ compatible = "amlogic,meson-g12a-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0xf080 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+ };
+
+ pwm_ef: pwm@19000 {
+ compatible = "amlogic,meson-g12a-ee-pwm";
+ reg = <0x0 0x19000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@1a000 {
+ compatible = "amlogic,meson-g12a-ee-pwm";
+ reg = <0x0 0x1a000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ab: pwm@1b000 {
+ compatible = "amlogic,meson-g12a-ee-pwm";
+ reg = <0x0 0x1b000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@1c000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1c000 0x0 0x20>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ i2c2: i2c@1d000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1d000 0x0 0x20>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ i2c1: i2c@1e000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1e000 0x0 0x20>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ i2c0: i2c@1f000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1f000 0x0 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
clk_msr: clock-measure@18000 {
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
};
};
+ sd_emmc_a: sd@ffe03000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe03000 0x0 0x800>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_A>,
+ <&clkc CLKID_SD_EMMC_A_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_A>;
+ amlogic,dram-access-quirk;
+ };
+
+ sd_emmc_b: sd@ffe05000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe05000 0x0 0x800>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_B>,
+ <&clkc CLKID_SD_EMMC_B_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_B>;
+ };
+
+ sd_emmc_c: mmc@ffe07000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe07000 0x0 0x800>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_C>,
+ <&clkc CLKID_SD_EMMC_C_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_C>;
+ };
+
usb: usb@ffe09000 {
status = "disabled";
compatible = "amlogic,meson-g12a-usb-ctrl";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "hardkernel,odroid-n2", "amlogic,g12b";
+ model = "Hardkernel ODROID-N2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "n2:blue";
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ tf_io: gpio-regulator-tf_io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0
+ 1800000 1>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&main_12v>;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ hub_5v: regulator-hub_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "HUB_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the Hub CHIPENABLE, LOW sets low power state */
+ gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the microUSB port power enable */
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "G12A-ODROIDN2";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ /*
+ * WARNING: The USB Hub on the Odroid-N2 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&vcc_5v>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&hub_5v>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12a.dtsi"
+
+/ {
+ compatible = "amlogic,g12b";
+
+ cpus {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu100>;
+ };
+
+ core1 {
+ cpu = <&cpu101>;
+ };
+
+ core2 {
+ cpu = <&cpu102>;
+ };
+
+ core3 {
+ cpu = <&cpu103>;
+ };
+ };
+ };
+
+ /delete-node/ cpu@2;
+ /delete-node/ cpu@3;
+
+ cpu100: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu101: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu102: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu103: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+};
+
+&clkc {
+ compatible = "amlogic,g12b-clkc";
+};
status = "disabled";
};
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys", "syscon";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7623-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 = &qspi;
+ spi0 = &snfi;
};
chosen {
};
&pinctrl {
- qspi_pins: qspi-pins {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
-&qspi {
- pinctrl-names = "default";
- pinctrl-0 = <&qspi_pins>;
+&snfi {
+ pinctrl-names = "default", "snfi";
+ pinctrl-0 = <&snor_pins>;
+ pinctrl-1 = <&snfi_pins>;
status = "okay";
spi-flash@0{
status = "disabled";
};
- qspi: qspi@11014000 {
- compatible = "mediatek,mt7629-qspi";
- reg = <0x11014000 0xe0>, <0x30000000 0x10000000>;
- reg-names = "reg_base", "mem_base";
+ snfi: snfi@1100d000 {
+ compatible = "mediatek,mtk-snfi-spi";
+ reg = <0x1100d000 0x2000>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xe6060000 0 0x50c>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a7795-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7795-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a7795-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a7795-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
+ reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
dma-names = "rx", "tx";
};
};
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- };
- };
};
audma0: dma-controller@ec700000 {
reg = <0 0xe6060000 0 0x50c>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77965-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77965-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77965-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77965-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77965-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
};
};
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = <&audma0 0x35>, <&audma1 0x36>;
+ dma-names = "rx", "tx";
+ };
+ ssiu02: ssiu-2 {
+ dmas = <&audma0 0x37>, <&audma1 0x38>;
+ dma-names = "rx", "tx";
+ };
+ ssiu03: ssiu-3 {
+ dmas = <&audma0 0x47>, <&audma1 0x48>;
+ dma-names = "rx", "tx";
+ };
+ ssiu04: ssiu-4 {
+ dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dma-names = "rx", "tx";
+ };
+ ssiu05: ssiu-5 {
+ dmas = <&audma0 0x43>, <&audma1 0x44>;
+ dma-names = "rx", "tx";
+ };
+ ssiu06: ssiu-6 {
+ dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dma-names = "rx", "tx";
+ };
+ ssiu07: ssiu-7 {
+ dmas = <&audma0 0x53>, <&audma1 0x54>;
+ dma-names = "rx", "tx";
+ };
+ ssiu10: ssiu-8 {
+ dmas = <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu11: ssiu-9 {
+ dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu12: ssiu-10 {
+ dmas = <&audma0 0x57>, <&audma1 0x58>;
+ dma-names = "rx", "tx";
+ };
+ ssiu13: ssiu-11 {
+ dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu14: ssiu-12 {
+ dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dma-names = "rx", "tx";
+ };
+ ssiu15: ssiu-13 {
+ dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu16: ssiu-14 {
+ dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu17: ssiu-15 {
+ dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu20: ssiu-16 {
+ dmas = <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx";
+ };
+ ssiu21: ssiu-17 {
+ dmas = <&audma0 0x67>, <&audma1 0x68>;
+ dma-names = "rx", "tx";
+ };
+ ssiu22: ssiu-18 {
+ dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu23: ssiu-19 {
+ dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu24: ssiu-20 {
+ dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu25: ssiu-21 {
+ dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu26: ssiu-22 {
+ dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu27: ssiu-23 {
+ dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dma-names = "rx", "tx";
+ };
+ ssiu30: ssiu-24 {
+ dmas = <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx";
+ };
+ ssiu31: ssiu-25 {
+ dmas = <&audma0 0x21>, <&audma1 0x22>;
+ dma-names = "rx", "tx";
+ };
+ ssiu32: ssiu-26 {
+ dmas = <&audma0 0x23>, <&audma1 0x24>;
+ dma-names = "rx", "tx";
+ };
+ ssiu33: ssiu-27 {
+ dmas = <&audma0 0x25>, <&audma1 0x26>;
+ dma-names = "rx", "tx";
+ };
+ ssiu34: ssiu-28 {
+ dmas = <&audma0 0x27>, <&audma1 0x28>;
+ dma-names = "rx", "tx";
+ };
+ ssiu35: ssiu-29 {
+ dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu36: ssiu-30 {
+ dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu37: ssiu-31 {
+ dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu40: ssiu-32 {
+ dmas = <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx";
+ };
+ ssiu41: ssiu-33 {
+ dmas = <&audma0 0x17>, <&audma1 0x18>;
+ dma-names = "rx", "tx";
+ };
+ ssiu42: ssiu-34 {
+ dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu43: ssiu-35 {
+ dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu44: ssiu-36 {
+ dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu45: ssiu-37 {
+ dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dma-names = "rx", "tx";
+ };
+ ssiu46: ssiu-38 {
+ dmas = <&audma0 0x31>, <&audma1 0x32>;
+ dma-names = "rx", "tx";
+ };
+ ssiu47: ssiu-39 {
+ dmas = <&audma0 0x33>, <&audma1 0x34>;
+ dma-names = "rx", "tx";
+ };
+ ssiu50: ssiu-40 {
+ dmas = <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx";
+ };
+ ssiu60: ssiu-41 {
+ dmas = <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx";
+ };
+ ssiu70: ssiu-42 {
+ dmas = <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu80: ssiu-43 {
+ dmas = <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx";
+ };
+ ssiu90: ssiu-44 {
+ dmas = <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx";
+ };
+ ssiu91: ssiu-45 {
+ dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dma-names = "rx", "tx";
+ };
+ ssiu92: ssiu-46 {
+ dmas = <&audma0 0x81>, <&audma1 0x82>;
+ dma-names = "rx", "tx";
+ };
+ ssiu93: ssiu-47 {
+ dmas = <&audma0 0x83>, <&audma1 0x84>;
+ dma-names = "rx", "tx";
+ };
+ ssiu94: ssiu-48 {
+ dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu95: ssiu-49 {
+ dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dma-names = "rx", "tx";
+ };
+ ssiu96: ssiu-50 {
+ dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu97: ssiu-51 {
+ dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dma-names = "rx", "tx";
+ };
+ };
+
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x01>, <&audma1 0x02>;
+ dma-names = "rx", "tx";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x03>, <&audma1 0x04>;
+ dma-names = "rx", "tx";
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x05>, <&audma1 0x06>;
+ dma-names = "rx", "tx";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x07>, <&audma1 0x08>;
+ dma-names = "rx", "tx";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x09>, <&audma1 0x0a>;
+ dma-names = "rx", "tx";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+ dma-names = "rx", "tx";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+ dma-names = "rx", "tx";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x0f>, <&audma1 0x10>;
+ dma-names = "rx", "tx";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x11>, <&audma1 0x12>;
+ dma-names = "rx", "tx";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x13>, <&audma1 0x14>;
+ dma-names = "rx", "tx";
};
};
};
du: display@feb00000 {
compatible = "renesas,du-r8a77965";
reg = <0 0xfeb00000 0 0x80000>;
- reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the ebisu board
*
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
&i2c0 {
status = "okay";
+ io_expander: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+ };
+
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
};
port@a {
- reg = <0xa>;
+ reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
};
};
+&i2c_dvfs {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ pmic: pmic@30 {
+ pinctrl-0 = <&irq0_pins>;
+ pinctrl-names = "default";
+
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&intc_ex>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rohm,ddr-backup-power = <0x1>;
+ rohm,rstbmode-level;
+ };
+};
+
&lvds0 {
status = "okay";
};
&lvds1 {
+ /*
+ * Even though the LVDS1 output is not connected, the encoder must be
+ * enabled to supply a pixel clock to the DU for the DPAD output when
+ * LVDS0 is in use.
+ */
+ status = "okay";
+
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
function = "du";
};
+ irq0_pins: irq0 {
+ groups = "intc_ex_irq0";
+ function = "intc_ex";
+ };
+
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
status = "okay";
};
+&vin5 {
+ status = "okay";
+};
+
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car E3 (R8A77990) SoC
*
status = "disabled";
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77990-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77990-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77990-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77990-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
};
csi40: csi2@feaa0000 {
- compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
+ compatible = "renesas,r8a77990-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
- phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
};
};
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
};
&lvds1 {
+ /*
+ * Even though the LVDS1 output is not connected, the encoder must be
+ * enabled to supply a pixel clock to the DU for the DPAD output when
+ * LVDS0 is in use.
+ */
+ status = "okay";
+
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
};
};
+ can0_pins: can0 {
+ groups = "can0_data_a";
+ function = "can0";
+ };
+
+ can1_pins: can1 {
+ groups = "can1_data_a";
+ function = "can1";
+ };
+
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
aliases {
};
};
+ keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keys_pins>;
+ pinctrl-names = "default";
+
+ key-1 {
+ gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW4-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW4-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW4-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW4-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-a {
+ gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "TSW0";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-b {
+ gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "TSW1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-c {
+ gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "TSW2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
function = "intc_ex";
};
+ keys_pins: keys {
+ pins = "GP_5_17", "GP_5_20", "GP_5_22";
+ bias-pull-up;
+ };
+
pwm1_pins: pwm1 {
groups = "pwm1_a";
function = "pwm1";
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
status = "okay";
};
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
// SPDX-License-Identifier: GPL-2.0+
/*
- * dts file for Xilinx ZynqMP ZC1275
+ * dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
*
#include "zynqmp-clk-ccf.dtsi"
/ {
- model = "ZynqMP ZC1275 RevA";
- compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+ model = "ZynqMP ZCU1275 RevA";
+ compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
+ "xlnx,zynqmp";
aliases {
serial0 = &uart0;
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP ZC1275 RevB
+ * dts file for Xilinx ZynqMP ZCU1275 RevB
*
* (C) Copyright 2018, Xilinx, Inc.
*
#include "zynqmp-clk-ccf.dtsi"
/ {
- model = "ZynqMP ZC1275 RevB";
- compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+ model = "ZynqMP ZCU1275 RevB";
+ compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
+ "xlnx,zynqmp";
aliases {
serial0 = &uart0;
/* max ticks timeout */
#define BCM2835_WDOG_MAX_TIMEOUT 0x000fffff
-#ifdef CONFIG_BCM2835_WDT
-extern void hw_watchdog_disable(void);
-#else
void hw_watchdog_disable(void) {}
-#endif
__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
phys_size_t get_effective_memsize(void)
{
/* Size is reported in MiB, convert it in bytes */
- return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
- >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
+ return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
+ >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
}
static struct mm_region g12a_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
- .size = 0x80000000UL,
+ .size = 0xf5000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
- .virt = 0xf0000000UL,
- .phys = 0xf0000000UL,
- .size = 0x10000000UL,
+ .virt = 0xf5000000UL,
+ .phys = 0xf5000000UL,
+ .size = 0x0b000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
G12A_ETH_REG_0_TX_RATIO(4) |
G12A_ETH_REG_0_PHY_CLK_EN |
G12A_ETH_REG_0_CLK_EN);
+ g12a_enable_external_mdio();
break;
case PHY_INTERFACE_MODE_RMII:
{
}
#endif /* CONFIG_FASTBOOT_FLASH_MMC */
+
+static void omap_set_fastboot_product(void)
+{
+ const char *board_name;
+
+ board_name = env_get("board_name");
+ if (board_name == NULL)
+ printf("Warning: fastboot.product: unknown board\n");
+
+ env_set("fastboot.product", board_name);
+}
+
void omap_set_fastboot_vars(void)
{
omap_set_fastboot_cpu();
omap_set_fastboot_secure();
omap_set_fastboot_board_rev();
omap_set_fastboot_userdata_size();
+ omap_set_fastboot_product();
}
#endif /* CONFIG_FASTBOOT_FLASH */
imply CMD_GPT
imply CMD_UUID
imply CMD_MMC_SWRITE if MMC
+ imply OF_BOARD_SETUP if PCI
imply SUPPORT_EMMC_RPMB if MMC
imply SPL
imply SPL_BOARD_INIT
Include external PMUFW (Platform Management Unit FirmWare) to
a Xilinx bootable image (boot.bin).
+config ZYNQMP_SPL_PM_CFG_OBJ_FILE
+ string "PMU firmware configuration object to load at runtime by SPL"
+ depends on SPL
+ help
+ Path to a binary PMU firmware configuration object to be linked
+ into U-Boot SPL and loaded at runtime into the PMU firmware.
+
+ The ZynqMP Power Management Unit (PMU) needs a configuration
+ object for most SoC peripherals to work. To have it loaded by
+ U-Boot SPL set here the file name (absolute path or relative to
+ the top source tree) of your configuration, which must be a
+ binary blob. It will be linked in the SPL binary and loaded
+ into the PMU firmware by U-Boot SPL during board
+ initialization.
+
+ Leave this option empty if your PMU firmware has a hard-coded
+ configuration object or you are loading it by any other means.
+
config ZYNQMP_USB
bool "Configure ZynqMP USB"
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
+
+ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
+obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o
+endif
void tcm_init(u8 mode);
#endif
+void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
+
#endif /* _ASM_ARCH_SYS_PROTO_H */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Inter-Processor Communication with the Platform Management Unit (PMU)
+ * firmware.
+ *
+ * (C) Copyright 2019 Luca Ceresoli
+ * Luca Ceresoli <luca@lucaceresoli.net>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+/* IPI bitmasks, register base and register offsets */
+#define IPI_BIT_MASK_APU 0x00001
+#define IPI_BIT_MASK_PMU0 0x10000
+#define IPI_REG_BASE_APU 0xFF300000
+#define IPI_REG_BASE_PMU0 0xFF330000
+#define IPI_REG_OFFSET_TRIG 0x00
+#define IPI_REG_OFFSET_OBR 0x04
+
+/* IPI mailbox buffer offsets */
+#define IPI_BUF_BASE_APU 0xFF990400
+#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0
+#define IPI_BUF_OFFSET_REQ 0x00
+#define IPI_BUF_OFFSET_RESP 0x20
+
+#define PMUFW_PAYLOAD_ARG_CNT 8
+
+/* PMUFW commands */
+#define PMUFW_CMD_SET_CONFIGURATION 2
+
+static void pmu_ipc_send_request(const u32 *req, size_t req_len)
+{
+ u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
+ IPI_BUF_OFFSET_TARGET_PMU +
+ IPI_BUF_OFFSET_REQ);
+ size_t i;
+
+ for (i = 0; i < req_len; i++)
+ writel(req[i], &mbx[i]);
+}
+
+static void pmu_ipc_read_response(unsigned int *value, size_t count)
+{
+ u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
+ IPI_BUF_OFFSET_TARGET_PMU +
+ IPI_BUF_OFFSET_RESP);
+ size_t i;
+
+ for (i = 0; i < count; i++)
+ value[i] = readl(&mbx[i]);
+}
+
+/**
+ * Send request to PMU and get the response.
+ *
+ * @req: Request buffer. Byte 0 is the API ID, other bytes are optional
+ * parameters.
+ * @req_len: Request length in number of 32-bit words.
+ * @res: Response buffer. Byte 0 is the error code, other bytes are
+ * optional parameters. Optional, if @res_maxlen==0 the parameters
+ * will not be read.
+ * @res_maxlen: Space allocated for the response in number of 32-bit words.
+ *
+ * @return Error code returned by the PMU (i.e. the first word of the response)
+ */
+static int pmu_ipc_request(const u32 *req, size_t req_len,
+ u32 *res, size_t res_maxlen)
+{
+ u32 status;
+
+ if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
+ res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
+ return -EINVAL;
+
+ pmu_ipc_send_request(req, req_len);
+
+ /* Raise Inter-Processor Interrupt to PMU and wait for response */
+ writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG);
+ do {
+ status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR);
+ } while (status & IPI_BIT_MASK_PMU0);
+
+ pmu_ipc_read_response(res, res_maxlen);
+
+ return 0;
+}
+
+/**
+ * Send a configuration object to the PMU firmware.
+ *
+ * @cfg_obj: Pointer to the configuration object
+ * @size: Size of @cfg_obj in bytes
+ */
+void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
+{
+ const u32 request[] = {
+ PMUFW_CMD_SET_CONFIGURATION,
+ (u32)((u64)cfg_obj)
+ };
+ u32 response;
+ int err;
+
+ printf("Loading PMUFW cfg obj (%ld bytes)\n", size);
+
+ err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1);
+ if (err)
+ panic("Cannot load PMUFW configuration object (%d)\n", err);
+ if (response != 0)
+ panic("PMUFW returned 0x%08x status!\n", response);
+}
--- /dev/null
+W400
+M: Neil Armstrong <narmstrong@baylibre.com>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/w400/
+F: configs/odroid-n2_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y := w400.o
--- /dev/null
+U-Boot for ODROID-N2
+====================
+
+ODROID-N2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.1 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 3.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - ADC
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make odroid-n2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ > DIR=odroid-n2
+ > git clone --depth 1 \
+ https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
+ $DIR
+
+ > cd odroid-n2
+ > make odroidn2_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+ Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/
+ > cp $UBOOTDIR/fip/g12b/bl2.bin fip/
+ > cp $UBOOTDIR/fip/g12b/bl30.bin fip/
+ > cp $UBOOTDIR/fip/g12b/bl31.img fip/
+ > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
+ > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/piei.fw fip/
+ > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
--- /dev/null
+U-Boot for Amlogic W400
+=======================
+
+U200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connector
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+ - Regulators
+ - Clock controller
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make w400_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make g12b_w400_v1_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+ > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+ > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+ > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+ > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/
+ > cp $FIPDIR/g12b/ddr3_1d.fw fip/
+ > cp $FIPDIR/g12b/ddr4_1d.fw fip/
+ > cp $FIPDIR/g12b/ddr4_2d.fw fip/
+ > cp $FIPDIR/g12b/diag_lpddr4.fw fip/
+ > cp $FIPDIR/g12b/lpddr4_1d.fw fip/
+ > cp $FIPDIR/g12b/lpddr4_2d.fw fip/
+ > cp $FIPDIR/g12b/piei.fw fip/
+ > cp $FIPDIR/g12b/aml_ddr.fw fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ > $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/arch/eth.h>
+
+int misc_init_r(void)
+{
+ meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+
+ return 0;
+}
};
const struct pinmux_resource pinmuxes[] = {
-#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_DRIVER_TI_EMAC
PINMUX_ITEM(emac_pins_mdio),
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
PINMUX_ITEM(emac_pins_rmii),
#else
PINMUX_ITEM(emac_pins_mii),
-#endif /* CONFIG_DRIVER_TI_EMAC */
-#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
-#endif /* CONFIG_SPL_BUILD */
+#endif
+#endif
#ifdef CONFIG_SPI_FLASH
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(spi1_pins_base),
PINMUX_ITEM(spi1_pins_scs0),
#endif
-#endif
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(uart2_pins_rtscts),
-#endif
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(i2c0_pins),
-#endif
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(emifa_pins_cs3),
PINMUX_ITEM(emifa_pins_cs4),
#endif
PINMUX_ITEM(gpio_pins),
#ifdef CONFIG_MMC_DAVINCI
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(mmc0_pins),
#endif
-#endif
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
rev = 2;
else if (maxcpuclk >= 372000000)
rev = 1;
-#ifdef CONFIG_DA850_AM18X_EVM
- rev |= REV_AM18X_EVM;
-#endif
return rev;
}
*/
#include <common.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
#include <asm/arch/rmobile.h>
#ifdef CONFIG_RCAR_GEN3
return 0;
}
+
+#if CONFIG_IS_ENABLED(OF_BOARD_SETUP) && CONFIG_IS_ENABLED(PCI)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ fdt_addr_t regs_addr;
+ int i, off, ret;
+
+ ret = uclass_get(UCLASS_PCI, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(dev, uc) {
+ struct pci_controller hose = { 0 };
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (hose.region_count == MAX_PCI_REGIONS) {
+ printf("maximum number of regions parsed, aborting\n");
+ break;
+ }
+
+ if (bd->bi_dram[i].size) {
+ pci_set_region(&hose.regions[hose.region_count++],
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].size,
+ PCI_REGION_MEM |
+ PCI_REGION_PREFETCH |
+ PCI_REGION_SYS_MEMORY);
+ }
+ }
+
+ regs_addr = devfdt_get_addr_index(dev, 0);
+ off = fdt_node_offset_by_compat_reg(blob,
+ "renesas,pcie-rcar-gen3", regs_addr);
+ if (off < 0) {
+ printf("Failed to find PCIe node@%llx\n", regs_addr);
+ return off;
+ }
+
+ fdt_pci_dma_ranges(blob, off, &hose);
+ }
+
+ return 0;
+}
+#endif
#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+ EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
+ EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+ EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U),
+ EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
F: include/configs/xilinx_zynqmp*
F: configs/xilinx_zynqmp*
F: configs/avnet_ultra96_rev1_defconfig
+
+ARM ZYNQMP AVNET ULTRAZED EV BOARD
+M: Luca Ceresoli <luca@lucaceresoli.net>
+S: Maintained
+F: arch/arm/dts/avnet-ultrazedev-*
+F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
obj-y += $(init-objs)
endif
+ifdef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
+obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o
+$(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE
+endif
+endif
+
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
ifndef CONFIG_SPL_BUILD
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+ psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+ psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ mask_delay(1);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+ mask_delay(5);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+ psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+ psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+ mask_delay(1);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+ mask_delay(5);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+ >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+ if (!pll_locked)
+ return 0;
+
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return 0;
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ int cur_R006_tREFPRD;
+
+ cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_peripherals_pre_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+.section .rodata
+
+.global zynqmp_pm_cfg_obj
+.type zynqmp_pm_cfg_obj, @object
+.global zynqmp_pm_cfg_obj_size
+.type zynqmp_pm_cfg_obj_size, @object
+
+zynqmp_pm_cfg_obj:
+.align 4
+.incbin CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE
+
+zynqmp_pm_cfg_obj_end:
+
+zynqmp_pm_cfg_obj_size:
+.int zynqmp_pm_cfg_obj_end - zynqmp_pm_cfg_obj
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Luca Ceresoli <luca@lucaceresoli.net>
+ *
+ * Declaration of PMU config object binary blob linked in at build time.
+ */
+
+extern const u32 zynqmp_pm_cfg_obj[];
+extern const int zynqmp_pm_cfg_obj_size;
#define xil_printf(...)
-void Xil_Out32(unsigned long addr, unsigned long val)
+static void Xil_Out32(unsigned long addr, unsigned long val)
{
writel(val, addr);
}
-int Xil_In32(unsigned long addr)
+static int Xil_In32(unsigned long addr)
{
return readl(addr);
}
-void usleep(u32 sleep)
+static void __maybe_unused usleep(u32 sleep)
{
udelay(sleep);
}
#include <zynqmppl.h>
#include <g_dnl.h>
+#include "pm_cfg_obj.h"
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
int board_init(void)
{
+#if defined(CONFIG_SPL_BUILD)
+ /* Check *at build time* if the filename is an non-empty string */
+ if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
+ zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
+ zynqmp_pm_cfg_obj_size);
+#endif
+
printf("EL Level:\tEL%d\n", current_el());
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
config AUTOBOOT_ENCRYPTION
bool "Enable encryption in autoboot stopping"
depends on AUTOBOOT_KEYED
- default n
+ help
+ This option allows a string to be entered into U-Boot to stop the
+ autoboot. The string itself is hashed and compared against the hash
+ in the environment variable 'bootstopkeysha256'. If it matches then
+ boot stops and a command-line prompt is presented.
+
+ This provides a way to ship a secure production device which can also
+ be accessed at the U-Boot command line.
config AUTOBOOT_DELAY_STR
string "Delay autobooting via specific input key / string"
string / password matches a values that is encypted via
a SHA256 hash and saved in the environment.
+config AUTOBOOT_USE_MENUKEY
+ bool "Allow a specify key to run a menu from the environment"
+ depends on !AUTOBOOT_KEYED
+ help
+ If a specific key is pressed to stop autoboot, then the commands in
+ the environment variable 'menucmd' are executed before boot starts.
+
+config AUTOBOOT_MENUKEY
+ int "ASCII value of boot key to show a menu"
+ default 0
+ depends on AUTOBOOT_USE_MENUKEY
+ help
+ If this key is pressed to stop autoboot, then the commands in the
+ environment variable 'menucmd' will be executed before boot starts.
+ For example, 33 means "!" in ASCII, so pressing ! at boot would take
+ this action.
+
+config AUTOBOOT_MENU_SHOW
+ bool "Show a menu on boot"
+ help
+ This enables the boot menu, controlled by environment variables
+ defined by the board. The menu starts after running the 'preboot'
+ environmnent variable (if enabled) and before handling the boot delay.
+ See README.bootmenu for more details.
+
endmenu
config BUILD_BIN2C
if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer,
&bytes_read) == AVB_IO_RESULT_OK) {
- printf("Read %ld bytes, value = %s\n", bytes_read,
+ printf("Read %zu bytes, value = %s\n", bytes_read,
(char *)buffer);
free(buffer);
return CMD_RET_SUCCESS;
if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1,
(const uint8_t *)value) ==
AVB_IO_RESULT_OK) {
- printf("Wrote %ld bytes\n", strlen(value) + 1);
+ printf("Wrote %zu bytes\n", strlen(value) + 1);
return CMD_RET_SUCCESS;
}
print_num("reloc off", gd->reloc_off);
print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
print_num("sp start ", gd->start_addr_sp);
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
print_num("FB base ", gd->fb_base);
#endif
/*
puts(ANSI_CLEAR_LINE);
}
-#ifdef CONFIG_MENU_SHOW
+#ifdef CONFIG_AUTOBOOT_MENU_SHOW
int menu_show(int bootdelay)
{
bootmenu_show(bootdelay);
*
* Implement efidebug "boot dump" sub-command.
* Dump information of all UEFI load options defined.
- * - boot dump
+ *
+ * efidebug boot dump
*/
static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
* CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
*
* Implement efidebug "boot" sub-command.
- * See above for details of sub-commands.
*/
static int do_efi_boot_opt(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
*
* Implement efidebug command which allows us to display and
* configure UEFI environment.
- * See above for details of sub-commands.
*/
static int do_efidebug(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
"0-device key, 1-user key, 2-no encryption.\n"
"The optional Userkey address specifies from which address key\n"
"has to be used for decryption if user key is selected.\n"
- "NOTE: the sceure bitstream has to be created using xilinx\n"
+ "NOTE: the secure bitstream has to be created using Xilinx\n"
"bootgen tool only.\n"
#endif
);
This should be large enough to hold the bootstage stash. A value of
4096 (4KiB) is normally plenty.
+config SHOW_BOOT_PROGRESS
+ bool "Show boot progress in a board-specific manner"
+ help
+ Defining this option allows to add some board-specific code (calling
+ a user-provided function show_boot_progress(int) that enables you to
+ show the system's boot progress on some display (for example, some
+ LEDs) on your board. At the moment, the following checkpoints are
+ implemented:
+
+ Legacy uImage format:
+
+ Arg Where When
+ 1 common/cmd_bootm.c before attempting to boot an image
+ -1 common/cmd_bootm.c Image header has bad magic number
+ 2 common/cmd_bootm.c Image header has correct magic number
+ -2 common/cmd_bootm.c Image header has bad checksum
+ 3 common/cmd_bootm.c Image header has correct checksum
+ -3 common/cmd_bootm.c Image data has bad checksum
+ 4 common/cmd_bootm.c Image data has correct checksum
+ -4 common/cmd_bootm.c Image is for unsupported architecture
+ 5 common/cmd_bootm.c Architecture check OK
+ -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi)
+ 6 common/cmd_bootm.c Image Type check OK
+ -6 common/cmd_bootm.c gunzip uncompression error
+ -7 common/cmd_bootm.c Unimplemented compression type
+ 7 common/cmd_bootm.c Uncompression OK
+ 8 common/cmd_bootm.c No uncompress/copy overwrite error
+ -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX)
+
+ 9 common/image.c Start initial ramdisk verification
+ -10 common/image.c Ramdisk header has bad magic number
+ -11 common/image.c Ramdisk header has bad checksum
+ 10 common/image.c Ramdisk header is OK
+ -12 common/image.c Ramdisk data has bad checksum
+ 11 common/image.c Ramdisk data has correct checksum
+ 12 common/image.c Ramdisk verification complete, start loading
+ -13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
+ 13 common/image.c Start multifile image verification
+ 14 common/image.c No initial ramdisk, no multifile, continue.
+
+ 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
+
+ -30 arch/powerpc/lib/board.c Fatal error, hang the system
+ -31 post/post.c POST test failed, detected by post_output_backlog()
+ -32 post/post.c POST test failed, detected by post_run_single()
+
+ 34 common/cmd_doc.c before loading a Image from a DOC device
+ -35 common/cmd_doc.c Bad usage of "doc" command
+ 35 common/cmd_doc.c correct usage of "doc" command
+ -36 common/cmd_doc.c No boot device
+ 36 common/cmd_doc.c correct boot device
+ -37 common/cmd_doc.c Unknown Chip ID on boot device
+ 37 common/cmd_doc.c correct chip ID found, device available
+ -38 common/cmd_doc.c Read Error on boot device
+ 38 common/cmd_doc.c reading Image header from DOC device OK
+ -39 common/cmd_doc.c Image header has bad magic number
+ 39 common/cmd_doc.c Image header has correct magic number
+ -40 common/cmd_doc.c Error reading Image from DOC device
+ 40 common/cmd_doc.c Image header has correct magic number
+ 41 common/cmd_ide.c before loading a Image from a IDE device
+ -42 common/cmd_ide.c Bad usage of "ide" command
+ 42 common/cmd_ide.c correct usage of "ide" command
+ -43 common/cmd_ide.c No boot device
+ 43 common/cmd_ide.c boot device found
+ -44 common/cmd_ide.c Device not available
+ 44 common/cmd_ide.c Device available
+ -45 common/cmd_ide.c wrong partition selected
+ 45 common/cmd_ide.c partition selected
+ -46 common/cmd_ide.c Unknown partition table
+ 46 common/cmd_ide.c valid partition table found
+ -47 common/cmd_ide.c Invalid partition type
+ 47 common/cmd_ide.c correct partition type
+ -48 common/cmd_ide.c Error reading Image Header on boot device
+ 48 common/cmd_ide.c reading Image Header from IDE device OK
+ -49 common/cmd_ide.c Image header has bad magic number
+ 49 common/cmd_ide.c Image header has correct magic number
+ -50 common/cmd_ide.c Image header has bad checksum
+ 50 common/cmd_ide.c Image header has correct checksum
+ -51 common/cmd_ide.c Error reading Image from IDE device
+ 51 common/cmd_ide.c reading Image from IDE device OK
+ 52 common/cmd_nand.c before loading a Image from a NAND device
+ -53 common/cmd_nand.c Bad usage of "nand" command
+ 53 common/cmd_nand.c correct usage of "nand" command
+ -54 common/cmd_nand.c No boot device
+ 54 common/cmd_nand.c boot device found
+ -55 common/cmd_nand.c Unknown Chip ID on boot device
+ 55 common/cmd_nand.c correct chip ID found, device available
+ -56 common/cmd_nand.c Error reading Image Header on boot device
+ 56 common/cmd_nand.c reading Image Header from NAND device OK
+ -57 common/cmd_nand.c Image header has bad magic number
+ 57 common/cmd_nand.c Image header has correct magic number
+ -58 common/cmd_nand.c Error reading Image from NAND device
+ 58 common/cmd_nand.c reading Image from NAND device OK
+
+ -60 common/env_common.c Environment has a bad CRC, using default
+
+ 64 net/eth.c starting with Ethernet configuration.
+ -64 net/eth.c no Ethernet found.
+ 65 net/eth.c Ethernet found.
+
+ -80 common/cmd_net.c usage wrong
+ 80 common/cmd_net.c before calling net_loop()
+ -81 common/cmd_net.c some error in net_loop() occurred
+ 81 common/cmd_net.c net_loop() back without error
+ -82 common/cmd_net.c size == 0 (File with size 0 loaded)
+ 82 common/cmd_net.c trying automatic boot
+ 83 common/cmd_net.c running "source" command
+ -83 common/cmd_net.c some error in automatic boot or "source" command
+ 84 common/cmd_net.c end without errors
+
+ FIT uImage format:
+
+ Arg Where When
+ 100 common/cmd_bootm.c Kernel FIT Image has correct format
+ -100 common/cmd_bootm.c Kernel FIT Image has incorrect format
+ 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration
+ -101 common/cmd_bootm.c Can't get configuration for kernel subimage
+ 102 common/cmd_bootm.c Kernel unit name specified
+ -103 common/cmd_bootm.c Can't get kernel subimage node offset
+ 103 common/cmd_bootm.c Found configuration node
+ 104 common/cmd_bootm.c Got kernel subimage node offset
+ -104 common/cmd_bootm.c Kernel subimage hash verification failed
+ 105 common/cmd_bootm.c Kernel subimage hash verification OK
+ -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
+ 106 common/cmd_bootm.c Architecture check OK
+ -106 common/cmd_bootm.c Kernel subimage has wrong type
+ 107 common/cmd_bootm.c Kernel subimage type OK
+ -107 common/cmd_bootm.c Can't get kernel subimage data/size
+ 108 common/cmd_bootm.c Got kernel subimage data/size
+ -108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
+ -109 common/cmd_bootm.c Can't get kernel subimage type
+ -110 common/cmd_bootm.c Can't get kernel subimage comp
+ -111 common/cmd_bootm.c Can't get kernel subimage os
+ -112 common/cmd_bootm.c Can't get kernel subimage load address
+ -113 common/cmd_bootm.c Image uncompress/copy overwrite error
+
+ 120 common/image.c Start initial ramdisk verification
+ -120 common/image.c Ramdisk FIT image has incorrect format
+ 121 common/image.c Ramdisk FIT image has correct format
+ 122 common/image.c No ramdisk subimage unit name, using configuration
+ -122 common/image.c Can't get configuration for ramdisk subimage
+ 123 common/image.c Ramdisk unit name specified
+ -124 common/image.c Can't get ramdisk subimage node offset
+ 125 common/image.c Got ramdisk subimage node offset
+ -125 common/image.c Ramdisk subimage hash verification failed
+ 126 common/image.c Ramdisk subimage hash verification OK
+ -126 common/image.c Ramdisk subimage for unsupported architecture
+ 127 common/image.c Architecture check OK
+ -127 common/image.c Can't get ramdisk subimage data/size
+ 128 common/image.c Got ramdisk subimage data/size
+ 129 common/image.c Can't get ramdisk load address
+ -129 common/image.c Got ramdisk load address
+
+ -130 common/cmd_doc.c Incorrect FIT image format
+ 131 common/cmd_doc.c FIT image format OK
+
+ -140 common/cmd_ide.c Incorrect FIT image format
+ 141 common/cmd_ide.c FIT image format OK
+
+ -150 common/cmd_nand.c Incorrect FIT image format
+ 151 common/cmd_nand.c FIT image format OK
+
endmenu
menu "Boot media"
#include <cli.h>
#include <console.h>
#include <fdtdec.h>
+#include <hash.h>
+#include <memalign.h>
#include <menu.h>
#include <post.h>
#include <u-boot/sha256.h>
/* Stored value of bootdelay, used by autoboot_command() */
static int stored_bootdelay;
+static int menukey;
+
+#ifdef CONFIG_AUTOBOOT_ENCRYPTION
+#define AUTOBOOT_STOP_STR_SHA256 CONFIG_AUTOBOOT_STOP_STR_SHA256
+#else
+#define AUTOBOOT_STOP_STR_SHA256 ""
+#endif
-#if defined(CONFIG_AUTOBOOT_KEYED)
-#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256)
+#ifdef CONFIG_USE_AUTOBOOT_MENUKEY
+#define AUTOBOOT_MENUKEY CONFIG_USE_AUTOBOOT_MENUKEY
+#else
+#define AUTOBOOT_MENUKEY 0
+#endif
/*
* Use a "constant-length" time compare function for this
return diff == 0;
}
-static int passwd_abort(uint64_t etime)
+/**
+ * passwd_abort_sha256() - check for a hashed key sequence to abort booting
+ *
+ * This checks for the user entering a SHA256 hash within a given time.
+ *
+ * @etime: Timeout value ticks (stop when get_ticks() reachs this)
+ * @return 0 if autoboot should continue, 1 if it should stop
+ */
+static int passwd_abort_sha256(uint64_t etime)
{
const char *sha_env_str = env_get("bootstopkeysha256");
u8 sha_env[SHA256_SUM_LEN];
- u8 sha[SHA256_SUM_LEN];
- char presskey[MAX_DELAY_STOP_STR];
+ u8 *sha;
+ char *presskey;
const char *algo_name = "sha256";
u_int presskey_len = 0;
int abort = 0;
int ret;
if (sha_env_str == NULL)
- sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256;
+ sha_env_str = AUTOBOOT_STOP_STR_SHA256;
/*
* Generate the binary value from the environment hash value
return 0;
}
+ presskey = malloc_cache_aligned(MAX_DELAY_STOP_STR);
+ sha = malloc_cache_aligned(SHA256_SUM_LEN);
+ size = SHA256_SUM_LEN;
/*
* We don't know how long the stop-string is, so we need to
* generate the sha256 hash upon each input character and
do {
if (tstc()) {
/* Check for input string overflow */
- if (presskey_len >= MAX_DELAY_STOP_STR)
+ if (presskey_len >= MAX_DELAY_STOP_STR) {
+ free(presskey);
+ free(sha);
return 0;
+ }
presskey[presskey_len++] = getc();
}
} while (!abort && get_ticks() <= etime);
+ free(presskey);
+ free(sha);
return abort;
}
-#else
-static int passwd_abort(uint64_t etime)
+
+/**
+ * passwd_abort_key() - check for a key sequence to aborted booting
+ *
+ * This checks for the user entering a string within a given time.
+ *
+ * @etime: Timeout value ticks (stop when get_ticks() reachs this)
+ * @return 0 if autoboot should continue, 1 if it should stop
+ */
+static int passwd_abort_key(uint64_t etime)
{
int abort = 0;
struct {
return abort;
}
-#endif
/***************************************************************************
* Watch for 'delay' seconds for autoboot stop or autoboot delay string.
* returns: 0 - no key string, allow autoboot 1 - got key string, abort
*/
-static int __abortboot(int bootdelay)
+static int abortboot_key_sequence(int bootdelay)
{
int abort;
uint64_t etime = endtick(bootdelay);
printf(CONFIG_AUTOBOOT_PROMPT, bootdelay);
# endif
- abort = passwd_abort(etime);
+ if (IS_ENABLED(CONFIG_AUTOBOOT_ENCRYPTION))
+ abort = passwd_abort_sha256(etime);
+ else
+ abort = passwd_abort_key(etime);
if (!abort)
debug_bootkeys("key timeout\n");
return abort;
}
-# else /* !defined(CONFIG_AUTOBOOT_KEYED) */
-
-#ifdef CONFIG_MENUKEY
-static int menukey;
-#endif
-
-static int __abortboot(int bootdelay)
+static int abortboot_single_key(int bootdelay)
{
int abort = 0;
unsigned long ts;
-#ifdef CONFIG_MENUPROMPT
- printf(CONFIG_MENUPROMPT);
-#else
printf("Hit any key to stop autoboot: %2d ", bootdelay);
-#endif
/*
* Check if key already pressed
ts = get_timer(0);
do {
if (tstc()) { /* we got a key press */
+ int key;
+
abort = 1; /* don't auto boot */
bootdelay = 0; /* no more delay */
-# ifdef CONFIG_MENUKEY
- menukey = getc();
-# else
- (void) getc(); /* consume input */
-# endif
+ key = getc(); /* consume input */
+ if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY))
+ menukey = key;
break;
}
udelay(10000);
return abort;
}
-# endif /* CONFIG_AUTOBOOT_KEYED */
static int abortboot(int bootdelay)
{
int abort = 0;
- if (bootdelay >= 0)
- abort = __abortboot(bootdelay);
+ if (bootdelay >= 0) {
+ if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
+ abort = abortboot_key_sequence(bootdelay);
+ else
+ abort = abortboot_single_key(bootdelay);
+ }
-#ifdef CONFIG_SILENT_CONSOLE
- if (abort)
+ if (IS_ENABLED(CONFIG_SILENT_CONSOLE) && abort)
gd->flags &= ~GD_FLG_SILENT;
-#endif
return abort;
}
static void process_fdt_options(const void *blob)
{
-#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_SYS_TEXT_BASE)
+#ifdef CONFIG_SYS_TEXT_BASE
ulong addr;
/* Add an env variable to point to a kernel payload, if available */
addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0);
if (addr)
env_set_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
-#endif /* CONFIG_OF_CONTROL && CONFIG_SYS_TEXT_BASE */
+#endif /* CONFIG_SYS_TEXT_BASE */
}
const char *bootdelay_process(void)
s = env_get("bootdelay");
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
-#ifdef CONFIG_OF_CONTROL
- bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
- bootdelay);
-#endif
+ if (IS_ENABLED(CONFIG_OF_CONTROL))
+ bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
+ bootdelay);
debug("### main_loop entered: bootdelay=%d\n\n", bootdelay);
-#if defined(CONFIG_MENU_SHOW)
- bootdelay = menu_show(bootdelay);
-#endif
+ if (IS_ENABLED(CONFIG_AUTOBOOT_MENU_SHOW))
+ bootdelay = menu_show(bootdelay);
bootretry_init_cmd_timeout();
#ifdef CONFIG_POST
else
s = env_get("bootcmd");
- process_fdt_options(gd->fdt_blob);
+ if (IS_ENABLED(CONFIG_OF_CONTROL))
+ process_fdt_options(gd->fdt_blob);
stored_bootdelay = bootdelay;
return s;
debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) {
-#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
- int prev = disable_ctrlc(1); /* disable Control C checking */
-#endif
+ bool lock;
+ int prev;
+
+ lock = IS_ENABLED(CONFIG_AUTOBOOT_KEYED) &&
+ !IS_ENABLED(CONFIG_AUTOBOOT_KEYED_CTRLC);
+ if (lock)
+ prev = disable_ctrlc(1); /* disable Ctrl-C checking */
run_command_list(s, -1, 0);
-#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
- disable_ctrlc(prev); /* restore Control C checking */
-#endif
+ if (lock)
+ disable_ctrlc(prev); /* restore Ctrl-C checking */
}
-#ifdef CONFIG_MENUKEY
- if (menukey == CONFIG_MENUKEY) {
+ if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY) &&
+ menukey == AUTOBOOT_MENUKEY) {
s = env_get("menucmd");
if (s)
run_command_list(s, -1, 0);
}
-#endif /* CONFIG_MENUKEY */
}
return AVB_IO_RESULT_OK;
}
+#ifdef CONFIG_OPTEE_TA_AVB
static AvbIOResult read_persistent_value(AvbOps *ops,
const char *name,
size_t buffer_size,
return rc;
}
+#endif
+
/**
* ============================================================================
* AVB2.0 AvbOps alloc/initialisation/free
char buf_out[CONFIG_PRE_CON_BUF_SZ + 1];
char *buf_in;
+#ifdef CONFIG_SILENT_CONSOLE
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+#endif
+
buf_in = map_sysmem(CONFIG_PRE_CON_BUF_ADDR, CONFIG_PRE_CON_BUF_SZ);
if (gd->precon_buf_idx > CONFIG_PRE_CON_BUF_SZ)
in = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ;
membuff_putbyte(&gd->console_out, c);
#endif
#ifdef CONFIG_SILENT_CONSOLE
- if (gd->flags & GD_FLG_SILENT)
+ if (gd->flags & GD_FLG_SILENT) {
+ if (!(gd->flags & GD_FLG_DEVINIT))
+ pre_console_putc(c);
return;
+ }
#endif
#ifdef CONFIG_DISABLE_CONSOLE
membuff_put(&gd->console_out, s, strlen(s));
#endif
#ifdef CONFIG_SILENT_CONSOLE
- if (gd->flags & GD_FLG_SILENT)
+ if (gd->flags & GD_FLG_SILENT) {
+ if (!(gd->flags & GD_FLG_DEVINIT))
+ pre_console_puts(s);
return;
+ }
#endif
#ifdef CONFIG_DISABLE_CONSOLE
return -1;
}
-static void console_update_silent(void)
+/* return true if the 'silent' flag is removed */
+static bool console_update_silent(void)
{
#ifdef CONFIG_SILENT_CONSOLE
- if (env_get("silent") != NULL)
+ if (env_get("silent")) {
gd->flags |= GD_FLG_SILENT;
- else
+ } else {
+ unsigned long flags = gd->flags;
+
gd->flags &= ~GD_FLG_SILENT;
+
+ return !!(flags & GD_FLG_SILENT);
+ }
#endif
+
+ return false;
}
int console_announce_r(void)
#if CONFIG_IS_ENABLED(CONSOLE_MUX)
int iomux_err = 0;
#endif
+ int flushpoint;
+
+ /* update silent for env loaded from flash (initr_env) */
+ if (console_update_silent())
+ flushpoint = PRE_CONSOLE_FLUSHPOINT1_SERIAL;
+ else
+ flushpoint = PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL;
/* set default handlers at first */
gd->jt->getc = serial_getc;
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return 0;
#endif
- print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL);
+ print_pre_console_buffer(flushpoint);
return 0;
}
struct list_head *list = stdio_get_list();
struct list_head *pos;
struct stdio_dev *dev;
+ int flushpoint;
- console_update_silent();
+ /* update silent for env loaded from flash (initr_env) */
+ if (console_update_silent())
+ flushpoint = PRE_CONSOLE_FLUSHPOINT1_SERIAL;
+ else
+ flushpoint = PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL;
#ifdef CONFIG_SPLASH_SCREEN
/*
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return 0;
#endif
- print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL);
+ print_pre_console_buffer(flushpoint);
return 0;
}
timing);
else
timing_done = true;
- break;
+
+ if (timing_done)
+ break;
}
}
if (!timing_done)
{
u32 fdt_size;
int root_node_off;
- const char *compatible = NULL;
+ const char *compatible;
- fdt_size = fdt_totalsize(fdt);
root_node_off = fdt_path_offset(fdt, "/");
if (root_node_off < 0) {
printf("Error: Root node not found\n");
- } else {
- compatible = fdt_getprop(fdt, root_node_off, "compatible",
- NULL);
+ return;
}
+ fdt_size = fdt_totalsize(fdt);
+ compatible = fdt_getprop(fdt, root_node_off, "compatible",
+ NULL);
+
printf(" (FDT)size = %d\n", fdt_size);
printf(" (FDT)compatible = %s\n",
compatible ? compatible : "(unknown)");
comp = IH_COMP_NONE;
loadbuf = buf;
/* Kernel images get decompressed later in bootm_load_os(). */
- if (!(image_type == IH_TYPE_KERNEL ||
- image_type == IH_TYPE_KERNEL_NOLOAD) &&
- !fit_image_get_comp(fit, noffset, &comp) &&
- comp != IH_COMP_NONE) {
+ if (!fit_image_get_comp(fit, noffset, &comp) &&
+ comp != IH_COMP_NONE &&
+ !(image_type == IH_TYPE_KERNEL ||
+ image_type == IH_TYPE_KERNEL_NOLOAD ||
+ image_type == IH_TYPE_RAMDISK)) {
ulong max_decomp_len = len * 20;
if (load == data) {
loadbuf = malloc(max_decomp_len);
memcpy(loadbuf, buf, len);
}
+ if (image_type == IH_TYPE_RAMDISK && comp != IH_COMP_NONE)
+ puts("WARNING: 'compression' nodes for ramdisks are deprecated,"
+ " please fix your .its file!\n");
+
/* verify that image data is a proper FDT blob */
if (image_type == IH_TYPE_FLATDT && fdt_check_header(loadbuf)) {
puts("Subimage data is not a FDT");
static void run_preboot_environment_command(void)
{
-#ifdef CONFIG_PREBOOT
char *p;
p = env_get("preboot");
if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
disable_ctrlc(prev); /* restore Ctrl-C checking */
}
-#endif /* CONFIG_PREBOOT */
}
/* We come here after U-Boot is initialised and ready to process commands */
cli_init();
- run_preboot_environment_command();
+ if (IS_ENABLED(CONFIG_USE_PREBOOT))
+ run_preboot_environment_command();
if (IS_ENABLED(CONFIG_UPDATE_TFTP))
update_tftp(0UL, NULL, NULL);
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SATAPWR="PH2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MACH_SUN4I=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_GPIO=y
CONFIG_SATAPWR="PD25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_USB3_VBUS_PIN="PL8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MMC0_CD_PIN="PB3"
CONFIG_USB1_VBUS_PIN="PG12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_BLK is not set
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_DTIMG=y
CONFIG_CMD_SPL=y
+CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_PMIC is not set
CONFIG_SPL_DMA_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_DTIMG=y
+CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_PMIC is not set
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_DTIMG=y
+CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_PMIC is not set
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
# CONFIG_ISO_PARTITION is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
# CONFIG_ISO_PARTITION is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySMX0,115200 mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs) ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run check_flash check_env;"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_TEXT_BASE=0xA0000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=0
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_TEXT_BASE=0xfffc0000
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_EFI_PARTITION=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_CMD_SF=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=567
-CONFIG_DRAM_ZQ=3881979
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2"
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ENV_OFFSET=0x20000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev 1; run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_LOG=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
# CONFIG_USE_PRIVATE_LIBGCC is not set
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
# CONFIG_USE_PRIVATE_LIBGCC is not set
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start;sf probe"
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_TARGET_COREBOOT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS305_1G_4S=y
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_SF is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_TIME is not set
# CONFIG_CMD_EXT4 is not set
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:512k(u-boot.ais),64k(u-boot-env),7552k(kernel-spare),64k(MAC-Address)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:32k(SPL),480k(u-boot),64k(u-boot-env),7552k(kernel-spare),64k(MAC-Address)"
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_USB_OHCI_DA8XX=y
CONFIG_USB_STORAGE=y
# CONFIG_FAT_WRITE is not set
-CONFIG_USE_TINY_PRINTF=y
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda1 ro quiet"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_IDENT_STRING="\nD-Link DNS-325"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_DS109=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_USE_PREBOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start; sf probe"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_TARGET_EFI_APP=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_TARGET_EFI_PAYLOAD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_TARGET_EFI_PAYLOAD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_PRE_CONSOLE_BUFFER=y
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="arch/arm/mach-rockchip/fit_spl_optee.its"
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0x60000000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_OPTEE=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-fennec.dtb"
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="GoFlexHome> "
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nMarvell-gplugD"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_USB1_VBUS_PIN="PL6"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ib62x0 => "
CONFIG_VIDEO_LCD_POWER="PH22"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" Iomega iConnect"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
# CONFIG_CMD_FLASH is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run nfsboot\" to mount root filesystem over NFS;echo"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_IDENT_STRING=" libretech-ac"
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_API=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2"
CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_API=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2"
CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run try_bootscript"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_TEXT_BASE=0x70008000
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=romfs"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo U-BOOT for ${hostname};setenv preboot;echo"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg"
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vga; setenv stderr serial,vga; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DRAM_CLK=408
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DRAM_CLK=408
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_IDENT_STRING="\nNAS 220"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nas220> "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=30
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv mmcnum 1; setenv mmcpart 1;setenv mmcscriptfile bootmenu.scr;if run switchmmc; then setenv mmcdone true;setenv mmctype fat;if run scriptload; then true; else setenv mmctype ext2;if run scriptload; then true; else setenv mmctype ext4;if run scriptload; then true; else setenv mmcdone false;fi;fi;fi;if ${mmcdone}; then run scriptboot;fi;fi;if run slide; then true; else setenv bootmenu_delay 0;setenv bootdelay 0;fi"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "
CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_MENU_SHOW=y
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_SAVEENV is not set
CONFIG_TARGET_NSA310S=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nsa310s => "
CONFIG_MMC0_CD_PIN=""
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_G12A=y
+CONFIG_SYS_BOARD="w400"
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" odroid-n2"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_PHY=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_IDENT_STRING="\nOpenRD-Base"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_IDENT_STRING="\nOpenRD-Client"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run check_env"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DRAM_CLK=672
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MACPWR="PD6"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DRAM_CLK=624
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_SATAPWR="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_VIDEO_DE2 is not set
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1"
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_VIDEO_DE2 is not set
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB1_VBUS_PIN="PD12"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_PINE64_DT_SELECTION=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB3_VBUS_PIN="PL5"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
-CONFIG_USB3_VBUS_PIN="PL5"
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_R_I2C_ENABLE=y
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nPogo E02"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
# CONFIG_CMD_FLASH is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_TEXT_BASE=0x00080000
CONFIG_TARGET_RPI_3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_RTC=y
CONFIG_CLK=y
+CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SANDBOX_CLK_CCF=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
CONFIG_CLK=y
+CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SANDBOX_CLK_CCF=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_TEGRA20=y
CONFIG_TARGET_SEABOARD=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
# CONFIG_CMD_IMI is not set
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SYS_PROMPT="snow # "
+CONFIG_USE_AUTOBOOT_MENUKEY=y
+CONFIG_AUTOBOOT_MENUKEY=33
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run try_bootscript"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; else setenv bootdelay 5 ; setenv boottype norm ; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_USB0_VBUS_DET="axp_vbus_detect"
CONFIG_USB1_VBUS_PIN="PH7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USB0_ID_DET="PH11"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_I2C0_ENABLE=y
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_BOOTDELAY=0
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_BOOTDELAY=0
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_BOOTDELAY=0
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_VENTANA=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
# CONFIG_CMD_IMI is not set
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA"
CONFIG_SPL_DM=y
CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_ZYNQMP=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_XTENSA=y
CONFIG_SYS_CPU="dc233c"
CONFIG_XTFPGA_KC705=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=10
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_TARGET_ZMX25=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_USE_PREBOOT=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_USE_PREBOOT=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_FPGA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
provides an escape sequence from the limited "password"
strings.
+ CONFIG_AUTOBOOT_ENCRYPTION
+
+ "bootstopkeysha256" environment variable
+
+ - Hash value of the input which unlocks the device and
+ stops autoboot.
+
+ This option allows a string to be entered into U-Boot to stop the
+ autoboot. The string itself is hashed and compared against the hash
+ in the environment variable 'bootstopkeysha256'. If it matches then
+ boot stops and a command-line prompt is presented.
+
+ This provides a way to ship a secure production device which can also
+ be accessed at the U-Boot command line.
+
CONFIG_RESET_TO_RETRY
(Only effective when CONFIG_BOOT_RETRY_TIME is also set)
After the countdown timed out, the board will be reset to restart
again.
+
+ CONFIG_AUTOBOOT_USE_MENUKEY
+ CONFIG_AUTOBOOT_MENUKEY
+
+ If this key is pressed to stop autoboot, then the commands in the
+ environment variable 'menucmd' will be executed before boot starts.
+ For example, 33 means "!" in ASCII, so pressing ! at boot would take
+ this action.
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_BOOTDELAY 30
- #define CONFIG_MENU_SHOW
+ #define CONFIG_AUTOBOOT_MENU_SHOW
When you intend to use the bootmenu on color frame buffer console,
make sure to additionally define CONFIG_CFB_CONSOLE_ANSI in the
the menu, and an opaque pointer to data controlled by the consumer.
If you want to show a menu, instead starting the shell, define
-CONFIG_MENU_SHOW. You have to code the int menu_show(int bootdelay)
+CONFIG_AUTOBOOT_MENU_SHOW. You have to code the int menu_show(int bootdelay)
function, which handle your menu. This function returns the remaining
bootdelay.
.. toctree::
:maxdepth: 2
+Unified Extensible Firmware (UEFI)
+----------------------------------
+
+U-Boot provides an implementation of the UEFI API allowing to run UEFI
+compliant software like Linux, GRUB, and iPXE. Furthermore U-Boot itself
+can be run an UEFI payload.
+
+.. toctree::
+ :maxdepth: 2
+
+ uefi/index
+
Driver-Model documentation
--------------------------
+
The following holds information on the U-Boot device driver framework:
driver-model, including the design details of itself and several driver
subsystems.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Unified Extensible Firmware (UEFI)
+==================================
+
+.. toctree::
+ :maxdepth: 2
+
+ uefi.rst
+ u-boot_on_efi.rst
+ iscsi.rst
-# iSCSI booting with U-Boot and iPXE
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2018 Heinrich Schuchardt
-## Motivation
+iSCSI booting with U-Boot and iPXE
+==================================
+
+Motivation
+----------
U-Boot has only a reduced set of supported network protocols. The focus for
network booting has been on UDP based protocols. A TCP stack and HTTP support
iPXE can be built as an EFI application (named snp.efi) which can be loaded and
run by U-Boot.
-## Boot sequence
+Boot sequence
+-------------
U-Boot loads the EFI application iPXE snp.efi using the bootefi command. This
application has network access via the simple network protocol offered by
| |
| ~ ~ ~ ~|
-## Security
+Security
+--------
The iSCSI protocol is not encrypted. The traffic could be secured using IPsec
but neither U-Boot nor iPXE does support this. So we should at least separate
the iSCSI traffic from all other network traffic. This can be achieved using a
virtual local area network (VLAN).
-## Configuration
+Configuration
+-------------
-### iPXE
+iPXE
+~~~~
For running iPXE on arm64 the bin-arm64-efi/snp.efi build target is needed::
iPXE by default will put the CPU to rest when waiting for input. U-Boot does
not wake it up due to missing interrupt support. To avoid this behavior create
-file src/config/local/nap.h::
+file src/config/local/nap.h:
+
+.. code-block:: c
/* nap.h */
#undef NAP_EFIX86
#define NAP_NULL
The supported commands in iPXE are controlled by an include, too. Putting the
-following into src/config/local/general.h is sufficient for most use cases::
+following into src/config/local/general.h is sufficient for most use cases:
+
+.. code-block:: c
/* general.h */
#define NSLOOKUP_CMD /* Name resolution command */
#define DOWNLOAD_PROTO_NFS /* Network File System Protocol */
#define DOWNLOAD_PROTO_FILE /* Local file system access */
-### Open-iSCSI
+Open-iSCSI
+~~~~~~~~~~
When the root file system is on an iSCSI drive you should disable pings and set
-the replacement timer to a high value [3]:
+the replacement timer to a high value in the configuration file [3]::
node.conn[0].timeo.noop_out_interval = 0
node.conn[0].timeo.noop_out_timeout = 0
node.session.timeo.replacement_timeout = 86400
-## Links
+Links
+-----
-* [1](https://ipxe.org) https://ipxe.org - iPXE open source boot firmware
-* [2](https://www.gnu.org/software/grub/) https://www.gnu.org/software/grub/ -
- GNU GRUB (Grand Unified Bootloader)
-* [3](https://github.com/open-iscsi/open-iscsi/blob/master/README)
- https://github.com/open-iscsi/open-iscsi/blob/master/README -
- Open-iSCSI README
+* [1] https://ipxe.org - iPXE open source boot firmware
+* [2] https://www.gnu.org/software/grub/ -
+ GNU GRUB (Grand Unified Bootloader)
+* [3] https://github.com/open-iscsi/open-iscsi/blob/master/README -
+ Open-iSCSI README
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Google, Inc
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2015 Google, Inc
U-Boot on EFI
=============
as an application or just as a means of getting U-Boot onto a new platform.
-=========== Table of Contents ===========
-
-Motivation
-Status
-Build Instructions
-Trying it out
-Inner workings
-EFI Application
-EFI Payload
-Tables
-Interrupts
-32/64-bit
-Future work
-Where is the code?
-
-
Motivation
----------
Running U-Boot on EFI is useful in several situations:
- You have EFI running on a board but U-Boot does not natively support it
-fully yet. You can boot into U-Boot from EFI and use that until U-Boot is
-fully ported
+ fully yet. You can boot into U-Boot from EFI and use that until U-Boot is
+ fully ported
- You need to use an EFI implementation (e.g. UEFI) because your vendor
-requires it in order to provide support
+ requires it in order to provide support
- You plan to use coreboot to boot into U-Boot but coreboot support does
-not currently exist for your platform. In the meantime you can use U-Boot
-on EFI and then move to U-Boot on coreboot when ready
+ not currently exist for your platform. In the meantime you can use U-Boot
+ on EFI and then move to U-Boot on coreboot when ready
- You use EFI but want to experiment with a simpler alternative like U-Boot
To build U-Boot as an EFI application (32-bit EFI required), enable CONFIG_EFI
and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app_defconfig) is set up
-for this. Just build U-Boot as normal, e.g.
+for this. Just build U-Boot as normal, e.g.::
make efi-x86_app_defconfig
make
CONFIG_EFI, CONFIG_EFI_STUB, and select either CONFIG_EFI_STUB_32BIT or
CONFIG_EFI_STUB_64BIT. The efi-x86_payload configs (efi-x86_payload32_defconfig
and efi-x86_payload32_defconfig) are set up for this. Then build U-Boot as
-normal, e.g.
+normal, e.g.::
make efi-x86_payload32_defconfig (or efi-x86_payload64_defconfig)
make
You will end up with one of these files depending on what you build for:
- u-boot-app.efi - U-Boot EFI application
- u-boot-payload.efi - U-Boot EFI payload application
+* u-boot-app.efi - U-Boot EFI application
+* u-boot-payload.efi - U-Boot EFI payload application
Trying it out
-------------
QEMU is an emulator and it can emulate an x86 machine. Please make sure your
QEMU version is 2.3.0 or above to test this. You can run the payload with
-something like this:
+something like this::
mkdir /tmp/efi
cp /path/to/u-boot*.efi /tmp/efi
prebuilt EFI BIOS for QEMU or you can build one from source as well.
To try it on real hardware, put u-boot-app.efi on a suitable boot medium,
-such as a USB stick. Then you can type something like this to start it:
+such as a USB stick. Then you can type something like this to start it::
fs0:u-boot-payload.efi
Inner workings
-==============
+--------------
Here follow a few implementation notes for those who want to fiddle with
this and perhaps contribute patches.
implemented completely differently.
EFI Application
----------------
+~~~~~~~~~~~~~~~
For the application the whole of U-Boot is built as a shared library. The
efi_main() function is in lib/efi/efi_app.c. It sets up some basic EFI
functions with efi_init(), sets up U-Boot global_data, allocates memory for
Use the 'reset' command to get back to EFI.
EFI Payload
------------
+~~~~~~~~~~~
The payload approach is a different kettle of fish. It works by building
U-Boot exactly as normal for your target board, then adding the entire
image (including device tree) into a small EFI stub application responsible
section).
Tables
-------
+~~~~~~
The payload can pass information to U-Boot in the form of EFI tables. At
present this feature is used to pass the EFI memory map, an inordinately
large list of memory regions. You can use the 'efi mem all' command to
below 4GB.
Interrupts
-----------
+~~~~~~~~~~
U-Boot drivers typically don't use interrupts. Since EFI enables interrupts
it is possible that an interrupt will fire that U-Boot cannot handle. This
seems to cause problems. For this reason the U-Boot payload runs with
interrupts disabled at present.
32/64-bit
----------
+~~~~~~~~~
While the EFI application can in principle be built as either 32- or 64-bit,
only 32-bit is currently supported. This means that the application can only
be used with 32-bit EFI.
- Figure out how to solve the interrupt problem
- Add more drivers to the application side (e.g. video, block devices, USB,
-environment access). This would mostly be an academic exercise as a strong
-use case is not readily apparent, but it might be fun.
+ environment access). This would mostly be an academic exercise as a strong
+ use case is not readily apparent, but it might be fun.
- Avoid turning off boot services in the stub. Instead allow U-Boot to make
-use of boot services in case it wants to. It is unclear what it might want
-though.
+ use of boot services in case it wants to. It is unclear what it might want
+ though.
Where is the code?
------------------
Google, Inc
July 2015
-[1] http://www.qemu.org
-[2] http://www.tianocore.org/ovmf/
+* [1] http://www.qemu.org
+* [2] http://www.tianocore.org/ovmf/
-<!--
-SPDX-License-Identifier: GPL-2.0+
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2018 Heinrich Schuchardt
-Copyright (c) 2018 Heinrich Schuchardt
--->
-
-# UEFI on U-Boot
+UEFI on U-Boot
+==============
The Unified Extensible Firmware Interface Specification (UEFI) [1] has become
the default for booting on AArch64 and x86 systems. It provides a stable API for
access to block storage, network, and console to name a few. The Linux kernel
and boot loaders like GRUB or the FreeBSD loader can be executed.
-## Development target
+Development target
+------------------
The implementation of UEFI in U-Boot strives to reach the requirements described
in the "Embedded Base Boot Requirements (EBBR) Specification - Release v1.0"
-[4]. The "Server Base Boot Requirements System Software on ARM Platforms" [5]
+[2]. The "Server Base Boot Requirements System Software on ARM Platforms" [3]
describes a superset of the EBBR specification and may be used as further
reference.
A full blown UEFI implementation would contradict the U-Boot design principle
"keep it small".
-## Building for UEFI
+Building U-Boot for UEFI
+------------------------
The UEFI standard supports only little-endian systems. The UEFI support can be
-activated for ARM and x86 by specifying
+activated for ARM and x86 by specifying::
CONFIG_CMD_BOOTEFI=y
CONFIG_EFI_LOADER=y
in the .config file.
Support for attaching virtual block devices, e.g. iSCSI drives connected by the
-loaded UEFI application [3], requires
+loaded UEFI application [4], requires::
CONFIG_BLK=y
CONFIG_PARTITIONS=y
-### Executing a UEFI binary
+Executing a UEFI binary
+~~~~~~~~~~~~~~~~~~~~~~~
The bootefi command is used to start UEFI applications or to install UEFI
-drivers. It takes two parameters
+drivers. It takes two parameters::
bootefi <image address> [fdt address]
* image address - the memory address of the UEFI binary
* fdt address - the memory address of the flattened device tree
-Below you find the output of an example session starting GRUB.
+Below you find the output of an example session starting GRUB::
=> load mmc 0:2 ${fdt_addr_r} boot/dtb
29830 bytes read in 14 ms (2 MiB/s)
table. The Linux kernel EFI stub uses the load options as command line
arguments.
-### Executing the boot manager
+Executing the boot manager
+~~~~~~~~~~~~~~~~~~~~~~~~~~
The UEFI specification foresees to define boot entries and boot sequence via UEFI
-variables. Booting according to these variables is possible via
+variables. Booting according to these variables is possible via::
bootefi bootmgr [fdt address]
As of U-Boot v2018.03 UEFI variables are not persisted and cannot be set at
runtime.
-### Executing the built in hello world application
+Executing the built in hello world application
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-A hello world UEFI application can be built with
+A hello world UEFI application can be built with::
CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
-It can be embedded into the U-Boot binary with
+It can be embedded into the U-Boot binary with::
CONFIG_CMD_BOOTEFI_HELLO=y
-The bootefi command is used to start the embedded hello world application.
+The bootefi command is used to start the embedded hello world application::
bootefi hello [fdt address]
-Below you find the output of an example session.
+Below you find the output of an example session::
=> bootefi hello ${fdtcontroladdr}
## Starting EFI application at 01000000 ...
The environment variable fdtcontroladdr points to U-Boot's internal device tree
(if available).
-### Executing the built-in self-test
+Executing the built-in self-test
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-An UEFI self-test suite can be embedded in U-Boot by building with
+An UEFI self-test suite can be embedded in U-Boot by building with::
CONFIG_CMD_BOOTEFI_SELFTEST=y
For testing the UEFI implementation the bootefi command can be used to start the
-self-test.
+self-test::
bootefi selftest [fdt address]
it is not provided all tests are executed except those marked as 'on request'.
If the environment variable is set to 'list' a list of all tests is shown.
-Below you can find the output of an example session.
+Below you can find the output of an example session::
=> setenv efi_selftest simple network protocol
=> bootefi selftest
Summary: 0 failures
Preparing for reset. Press any key.
-## The UEFI life cycle
+The UEFI life cycle
+-------------------
After the U-Boot platform has been initialized the UEFI API provides two kinds
-of services
+of services:
-* boot services and
-* runtime services.
+* boot services
+* runtime services
-The API can be extended by loading UEFI drivers which come in two variants
+The API can be extended by loading UEFI drivers which come in two variants:
-* boot drivers and
-* runtime drivers.
+* boot drivers
+* runtime drivers
UEFI drivers are installed with U-Boot's bootefi command. With the same command
UEFI applications can be executed.
So this is a point of no return. Afterwards the UEFI application can only return
to U-Boot by rebooting.
-## The UEFI object model
+The UEFI object model
+---------------------
UEFI offers a flexible and expandable object model. The objects in the UEFI API
are devices, drivers, and loaded images. These objects are referenced by
Loaded images offer the EFI_LOADED_IMAGE_PROTOCOL. This protocol provides meta
information about the image and a pointer to the unload callback function.
-## The UEFI events
+The UEFI events
+---------------
In the UEFI terminology an event is a data object referencing a notification
function which is queued for calling when the event is signaled. The following
Events can be assigned to an event group. If any of the events in a group is
signaled, all other events in the group are also set to the signaled state.
-## The UEFI driver model
+The UEFI driver model
+---------------------
A driver is specific for a single protocol installed on a device. To install a
driver on a device the ConnectController service is called. In this context
A driver can be detached from a device using the DisconnectController service.
-## U-Boot devices mapped as UEFI devices
+U-Boot devices mapped as UEFI devices
+-------------------------------------
Some of the U-Boot devices are mapped as UEFI devices
As of U-Boot 2018.03 the logic for doing this is hard coded.
The development target is to integrate the setup of these UEFI devices with the
-U-Boot driver model. So when a U-Boot device is discovered a handle should be
-created and the device path protocol and the relevant IO protocol should be
+U-Boot driver model [5]. So when a U-Boot device is discovered a handle should
+be created and the device path protocol and the relevant IO protocol should be
installed. The UEFI driver then would be attached by calling ConnectController.
When a U-Boot device is removed DisconnectController should be called.
-## UEFI devices mapped as U-Boot devices
+UEFI devices mapped as U-Boot devices
+-------------------------------------
UEFI drivers binaries and applications may create new (virtual) devices, install
a protocol and call the ConnectController service. Now the matching UEFI driver
In U-Boot 2018.03 this has only been implemented for block IO devices.
-### UEFI uclass
+UEFI uclass
+~~~~~~~~~~~
An UEFI uclass driver (lib/efi_driver/efi_uclass.c) has been created that
takes care of initializing the UEFI drivers and providing the
A linker created list is used to keep track of the UEFI drivers. To create an
entry in the list the UEFI driver uses the U_BOOT_DRIVER macro specifying
-UCLASS_EFI as the ID of its uclass, e.g.
+UCLASS_EFI as the ID of its uclass, e.g::
/* Identify as UEFI driver */
U_BOOT_DRIVER(efi_block) = {
- .name = "EFI block driver",
- .id = UCLASS_EFI,
- .ops = &driver_ops,
+ .name = "EFI block driver",
+ .id = UCLASS_EFI,
+ .ops = &driver_ops,
};
-The available operations are defined via the structure struct efi_driver_ops.
+The available operations are defined via the structure struct efi_driver_ops::
struct efi_driver_ops {
const efi_guid_t *protocol;
controllers created by the UEFI driver and the UEFI driver. (In U-Boot v2013.03
this is not yet completely implemented.)
-### UEFI block IO driver
+UEFI block IO driver
+~~~~~~~~~~~~~~~~~~~~
The UEFI block IO driver supports devices exposing the EFI_BLOCK_IO_PROTOCOL.
When connected it creates a new U-Boot block IO device with interface type
IF_TYPE_EFI, adds child controllers mapping the partitions, and installs the
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the
-software iPXE to boot from iSCSI network drives [3].
+software iPXE to boot from iSCSI network drives [4].
-This driver is only available if U-Boot is configured with
+This driver is only available if U-Boot is configured with::
CONFIG_BLK=y
CONFIG_PARTITIONS=y
-## TODOs as of U-Boot 2019.04
-
-* unimplemented or incompletely implemented boot services
- * Exit - call unload function, unload applications only
- * ProtocolRegisterNotify
- * UnloadImage
-
-* unimplemented or incompletely implemented runtime services
- * SetVariable() ignores attribute EFI_VARIABLE_APPEND_WRITE
- * QueryVariableInfo is not implemented
-
-* unimplemented events
- * EVT_RUNTIME
- * EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
-
-* data model
- * manage configuration tables in a linked list
-
-* UEFI drivers
- * support DisconnectController for UEFI block devices.
-
-* support for CONFIG_EFI_LOADER in the sandbox (CONFIG_SANDBOX=y)
-
-* UEFI variables
- * persistence
- * runtime support
-
-* incompletely implemented protocols
- * support version 0x00020000 of the EFI file protocol
-
-## Links
+Links
+-----
-* [1](http://uefi.org/specifications)
- http://uefi.org/specifications - UEFI specifications
-* [2](./driver-model/README.txt) doc/driver-model/README.txt - Driver model
-* [3](./README.iscsi) doc/README.iscsi - iSCSI booting with U-Boot and iPXE
-* [4](https://github.com/ARM-software/ebbr/releases/download/v1.0/ebbr-v1.0.pdf)
+* [1] http://uefi.org/specifications - UEFI specifications
+* [2] https://github.com/ARM-software/ebbr/releases/download/v1.0/ebbr-v1.0.pdf -
Embedded Base Boot Requirements (EBBR) Specification - Release v1.0
-* [5](https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11)
+* [3] https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11 -
Server Base Boot Requirements System Software on ARM Platforms - Version 1.1
+* [4] :doc:`iscsi`
+* [5] :doc:`../driver-model/index`
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's SPL.
+config SPL_CLK_COMPOSITE_CCF
+ bool "SPL Common Clock Framework [CCF] composite clk support "
+ depends on SPL_CLK_CCF
+ help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] composite code in U-Boot's SPL.
+
config CLK_CCF
bool "Common Clock Framework [CCF] support "
depends on CLK_IMX6Q || SANDBOX_CLK_CCF
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's clock driver.
+config CLK_COMPOSITE_CCF
+ bool "Common Clock Framework [CCF] composite clk support "
+ depends on CLK_CCF
+ help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] composite code in U-Boot's clock driver.
+
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
-obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
obj-y += analogbits/
obj-y += imx/
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_COMPOSITE "clk_composite"
+
+static u8 clk_composite_get_parent(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ struct clk *mux = composite->mux;
+
+ return clk_mux_get_parent(mux);
+}
+
+static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk *mux = composite->mux;
+
+ return mux_ops->set_parent(mux, parent);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *rate_ops = composite->rate_ops;
+ struct clk *rate = composite->rate;
+
+ return rate_ops->get_rate(rate);
+}
+
+static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *rate_ops = composite->rate_ops;
+ struct clk *clk_rate = composite->rate;
+
+ return rate_ops->set_rate(clk_rate, rate);
+}
+
+static int clk_composite_enable(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *gate_ops = composite->gate_ops;
+ struct clk *gate = composite->gate;
+
+ return gate_ops->enable(gate);
+}
+
+static int clk_composite_disable(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *gate_ops = composite->gate_ops;
+ struct clk *gate = composite->gate;
+
+ gate_ops->disable(gate);
+
+ return 0;
+}
+
+struct clk_ops clk_composite_ops = {
+ /* This will be set according to clk_register_composite */
+};
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char * const *parent_names,
+ int num_parents, struct clk *mux,
+ const struct clk_ops *mux_ops,
+ struct clk *rate,
+ const struct clk_ops *rate_ops,
+ struct clk *gate,
+ const struct clk_ops *gate_ops,
+ unsigned long flags)
+{
+ struct clk *clk;
+ struct clk_composite *composite;
+ int ret;
+ struct clk_ops *composite_ops = &clk_composite_ops;
+
+ composite = kzalloc(sizeof(*composite), GFP_KERNEL);
+ if (!composite)
+ return ERR_PTR(-ENOMEM);
+
+ if (mux && mux_ops) {
+ composite->mux = mux;
+ composite->mux_ops = mux_ops;
+ if (mux_ops->set_parent)
+ composite_ops->set_parent = clk_composite_set_parent;
+ mux->data = (ulong)composite;
+ }
+
+ if (rate && rate_ops) {
+ if (!rate_ops->get_rate) {
+ clk = ERR_PTR(-EINVAL);
+ goto err;
+ }
+ composite_ops->get_rate = clk_composite_recalc_rate;
+
+ /* .set_rate requires either .round_rate or .determine_rate */
+ if (rate_ops->set_rate)
+ composite_ops->set_rate = clk_composite_set_rate;
+
+ composite->rate = rate;
+ composite->rate_ops = rate_ops;
+ rate->data = (ulong)composite;
+ }
+
+ if (gate && gate_ops) {
+ if (!gate_ops->enable || !gate_ops->disable) {
+ clk = ERR_PTR(-EINVAL);
+ goto err;
+ }
+
+ composite->gate = gate;
+ composite->gate_ops = gate_ops;
+ composite_ops->enable = clk_composite_enable;
+ composite_ops->disable = clk_composite_disable;
+ gate->data = (ulong)composite;
+ }
+
+ clk = &composite->clk;
+ ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
+ parent_names[clk_composite_get_parent(clk)]);
+ if (ret) {
+ clk = ERR_PTR(ret);
+ goto err;
+ }
+
+ return clk;
+
+err:
+ kfree(composite);
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_composite) = {
+ .name = UBOOT_DM_CLK_COMPOSITE,
+ .id = UCLASS_CLK,
+ .ops = &clk_composite_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
#include <dm/lists.h>
#include <dm/device-internal.h>
#include <linux/clk-provider.h>
+#include <linux/log2.h>
#include <div64.h>
#include <clk.h>
#include "clk.h"
static ulong clk_divider_recalc_rate(struct clk *clk)
{
- struct clk_divider *divider =
- to_clk_divider(dev_get_clk_ptr(clk->dev));
+ struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned int val;
divider->flags, divider->width);
}
+static bool _is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return true;
+ return false;
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
+ unsigned long flags)
+{
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return is_power_of_2(div);
+ if (table)
+ return _is_valid_table_div(table, div);
+ return true;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return clkt->val;
+ return 0;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+ unsigned int div, unsigned long flags, u8 width)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return div;
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return __ffs(div);
+ if (flags & CLK_DIVIDER_MAX_AT_ZERO)
+ return (div == clk_div_mask(width) + 1) ? 0 : div;
+ if (table)
+ return _get_table_val(table, div);
+ return div - 1;
+}
+int divider_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_div_table *table, u8 width,
+ unsigned long flags)
+{
+ unsigned int div, value;
+
+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (!_is_valid_div(table, div, flags))
+ return -EINVAL;
+
+ value = _get_val(table, div, flags, width);
+
+ return min_t(unsigned int, value, clk_div_mask(width));
+}
+
+static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = clk_div_mask(divider->width) << (divider->shift + 16);
+ } else {
+ val = readl(divider->reg);
+ val &= ~(clk_div_mask(divider->width) << divider->shift);
+ }
+ val |= (u32)value << divider->shift;
+ writel(val, divider->reg);
+
+ return clk_get_rate(clk);
+}
+
const struct clk_ops clk_divider_ops = {
.get_rate = clk_divider_recalc_rate,
+ .set_rate = clk_divider_set_rate,
};
static struct clk *_register_divider(struct device *dev, const char *name,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ * Copyright 2019 NXP
+ *
+ * Gated clock implementation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_GATE "clk_gate"
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's output
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent. No clk_set_rate support
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+/*
+ * It works on following logic:
+ *
+ * For enabling clock, enable = 1
+ * set2dis = 1 -> clear bit -> set = 0
+ * set2dis = 0 -> set bit -> set = 1
+ *
+ * For disabling clock, enable = 0
+ * set2dis = 1 -> set bit -> set = 1
+ * set2dis = 0 -> clear bit -> set = 0
+ *
+ * So, result is always: enable xor set2dis.
+ */
+static void clk_gate_endisable(struct clk *clk, int enable)
+{
+ struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+ u32 reg;
+
+ set ^= enable;
+
+ if (gate->flags & CLK_GATE_HIWORD_MASK) {
+ reg = BIT(gate->bit_idx + 16);
+ if (set)
+ reg |= BIT(gate->bit_idx);
+ } else {
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ reg = gate->io_gate_val;
+#else
+ reg = readl(gate->reg);
+#endif
+
+ if (set)
+ reg |= BIT(gate->bit_idx);
+ else
+ reg &= ~BIT(gate->bit_idx);
+ }
+
+ writel(reg, gate->reg);
+}
+
+static int clk_gate_enable(struct clk *clk)
+{
+ clk_gate_endisable(clk, 1);
+
+ return 0;
+}
+
+static int clk_gate_disable(struct clk *clk)
+{
+ clk_gate_endisable(clk, 0);
+
+ return 0;
+}
+
+int clk_gate_is_enabled(struct clk *clk)
+{
+ struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ u32 reg;
+
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ reg = gate->io_gate_val;
+#else
+ reg = readl(gate->reg);
+#endif
+
+ /* if a set bit disables this clk, flip it before masking */
+ if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+ reg ^= BIT(gate->bit_idx);
+
+ reg &= BIT(gate->bit_idx);
+
+ return reg ? 1 : 0;
+}
+
+const struct clk_ops clk_gate_ops = {
+ .enable = clk_gate_enable,
+ .disable = clk_gate_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ struct clk_gate *gate;
+ struct clk *clk;
+ int ret;
+
+ if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
+ if (bit_idx > 15) {
+ pr_err("gate bit exceeds LOWORD field\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ /* struct clk_gate assignments */
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->flags = clk_gate_flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ gate->io_gate_val = *(u32 *)reg;
+#endif
+
+ clk = &gate->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_gate) = {
+ .name = UBOOT_DM_CLK_GATE,
+ .id = UCLASS_CLK,
+ .ops = &clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
unsigned int val)
{
- struct clk_mux *mux = to_clk_mux(clk);
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
int num_parents = mux->num_parents;
if (table) {
return val;
}
-static u8 clk_mux_get_parent(struct clk *clk)
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
{
- struct clk_mux *mux = to_clk_mux(clk);
+ unsigned int val = index;
+
+ if (table) {
+ val = table[index];
+ } else {
+ if (flags & CLK_MUX_INDEX_BIT)
+ val = 1 << index;
+
+ if (flags & CLK_MUX_INDEX_ONE)
+ val++;
+ }
+
+ return val;
+}
+
+u8 clk_mux_get_parent(struct clk *clk)
+{
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
u32 val;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
}
+static int clk_fetch_parent_index(struct clk *clk,
+ struct clk *parent)
+{
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+
+ int i;
+
+ if (!parent)
+ return -EINVAL;
+
+ for (i = 0; i < mux->num_parents; i++) {
+ if (!strcmp(parent->dev->name, mux->parent_names[i]))
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ int index;
+ u32 val;
+ u32 reg;
+
+ index = clk_fetch_parent_index(clk, parent);
+ if (index < 0) {
+ printf("Could not fetch index\n");
+ return index;
+ }
+
+ val = clk_mux_index_to_val(mux->table, mux->flags, index);
+
+ if (mux->flags & CLK_MUX_HIWORD_MASK) {
+ reg = mux->mask << (mux->shift + 16);
+ } else {
+ reg = readl(mux->reg);
+ reg &= ~(mux->mask << mux->shift);
+ }
+ val = val << mux->shift;
+ reg |= val;
+ writel(reg, mux->reg);
+
+ return 0;
+}
+
const struct clk_ops clk_mux_ops = {
- .get_rate = clk_generic_get_rate,
+ .get_rate = clk_generic_get_rate,
+ .set_parent = clk_mux_set_parent,
};
struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
{
int ret;
+ if (!dev_of_valid(dev))
+ return 0;
+
/* If this not in SPL and pre-reloc state, don't take any action. */
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
return 0;
{
return hw->dev->name;
}
+
+bool clk_dev_binded(struct clk *clk)
+{
+ if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
+ return true;
+
+ return false;
+}
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
-
-struct clk_fixed_rate {
- struct clk clk;
- unsigned long fixed_rate;
-};
-
-#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+#include <linux/clk-provider.h>
static ulong clk_fixed_rate_get_rate(struct clk *clk)
{
.ops = &clk_gate2_ops,
};
+static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+ struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+ struct clk_composite *composite = (struct clk_composite *)clk->data;
+ ulong parent_rate = clk_get_parent_rate(&composite->clk);
+ unsigned int val;
+
+ val = divider->io_divider_val;
+ val >>= divider->shift;
+ val &= clk_div_mask(divider->width);
+
+ return divider_recalc_rate(clk, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+static const struct clk_ops sandbox_clk_composite_divider_ops = {
+ .get_rate = sandbox_clk_composite_divider_recalc_rate,
+};
+
+struct clk *sandbox_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+ struct clk *clk = ERR_PTR(-ENOMEM);
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux->reg = reg;
+ mux->shift = 24;
+ mux->mask = 0x7;
+ mux->num_parents = num_parents;
+ mux->flags = flags;
+ mux->parent_names = parent_names;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div->reg = reg;
+ div->shift = 16;
+ div->width = 3;
+ div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate->reg = reg;
+ gate->bit_idx = 28;
+ gate->flags = flags;
+
+ clk = clk_register_composite(NULL, name,
+ parent_names, num_parents,
+ &mux->clk, &clk_mux_ops, &div->clk,
+ &sandbox_clk_composite_divider_ops,
+ &gate->clk, &clk_gate_ops, flags);
+ if (IS_ERR(clk))
+ goto fail;
+
+ return clk;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return ERR_CAST(clk);
+}
+
/* --- Sandbox Gate --- */
/* The CCF core driver itself */
static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
};
static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
+static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
static int sandbox_clk_ccf_probe(struct udevice *dev)
{
sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
ARRAY_SIZE(usdhc_sels)));
+ reg = BIT(28) | BIT(24) | BIT(16);
+ clk_dm(SANDBOX_CLK_I2C,
+ sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
+ ®, 0));
+
return 0;
}
return 0;
}
+static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *parent = clk_get_parent(clk);
+
+ if (parent)
+ return clk_set_rate(parent, rate);
+
+ return -ENODEV;
+}
+
static const struct clk_ops clk_gate2_ops = {
+ .set_rate = clk_gate2_set_rate,
.enable = clk_gate2_enable,
.disable = clk_gate2_disable,
.get_rate = clk_generic_get_rate,
shift, 0x3, 0);
}
+static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate2(NULL, name, parent,
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0x3, 0);
+}
+
+static inline struct clk *imx_clk_gate4_flags(const char *name,
+ const char *parent, void __iomem *reg, u8 shift,
+ unsigned long flags)
+{
+ return clk_register_gate2(NULL, name, parent,
+ flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0x3, 0);
+}
+
static inline struct clk *imx_clk_fixed_factor(const char *name,
const char *parent, unsigned int mult, unsigned int div)
{
reg, shift, width, 0);
}
+static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_register_divider(NULL, name, parent,
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0);
+}
+
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
void __iomem *reg, u8 idx);
u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val));
+static inline struct clk *imx_clk_mux_flags(const char *name,
+ void __iomem *reg, u8 shift, u8 width,
+ const char * const *parents, int num_parents,
+ unsigned long flags)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
+ width, 0);
+}
+
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
width, 0);
}
+static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0);
+}
+
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, unsigned long flags)
+{
+ return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
+ shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate(NULL, name, parent,
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0, NULL);
+}
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg, unsigned long flags);
+
+#define __imx8m_clk_composite(name, parent_names, reg, flags) \
+ imx8m_clk_composite_flags(name, parent_names, \
+ ARRAY_SIZE(parent_names), reg, \
+ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
+#define imx8m_clk_composite(name, parent_names, reg) \
+ __imx8m_clk_composite(name, parent_names, reg, 0)
+
+#define imx8m_clk_composite_critical(name, parent_names, reg) \
+ __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+
#endif /* __MACH_IMX_CLK_H */
GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
};
-/* ethsys */
-static const struct mtk_gate_regs eth_cg_regs = {
+/* ethsys and hifsys */
+static const struct mtk_gate_regs eth_hif_cg_regs = {
.sta_ofs = 0x30,
};
-#define GATE_ETH(_id, _parent, _shift, _flag) { \
+#define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \
.id = _id, \
.parent = _parent, \
- .regs = ð_cg_regs, \
+ .regs = ð_hif_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
}
-#define GATE_ETH0(_id, _parent, _shift) \
- GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
+#define GATE_ETH_HIF0(_id, _parent, _shift) \
+ GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
-#define GATE_ETH1(_id, _parent, _shift) \
- GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
+#define GATE_ETH_HIF1(_id, _parent, _shift) \
+ GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
static const struct mtk_gate eth_cgs[] = {
- GATE_ETH1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
- GATE_ETH1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
- GATE_ETH0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
- GATE_ETH1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
- GATE_ETH1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
- GATE_ETH1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
- GATE_ETH1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
- GATE_ETH1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
+ GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
+ GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
+ GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
+ GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
+ GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
+ GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
+ GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
+ GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
+};
+
+static const struct mtk_gate hif_cgs[] = {
+ GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
+ GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
+ GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
+ GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
+ GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
};
static const struct mtk_clk_tree mt7623_clk_tree = {
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
}
+static int mt7623_hifsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
+}
+
static int mt7623_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
}
-static int mt7623_ethsys_bind(struct udevice *dev)
+static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
{
int ret = 0;
#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
- ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
if (ret)
- debug("Warning: failed to bind ethsys reset controller\n");
+ debug("Warning: failed to bind reset controller\n");
#endif
return ret;
{ }
};
+static const struct udevice_id mt7623_hifsys_compat[] = {
+ { .compatible = "mediatek,mt7623-hifsys" },
+ { }
+};
+
static const struct udevice_id mt7623_mcucfg_compat[] = {
{ .compatible = "mediatek,mt7623-mcucfg" },
{ }
.flags = DM_FLAG_PRE_RELOC,
};
+U_BOOT_DRIVER(mtk_clk_hifsys) = {
+ .name = "mt7623-clock-hifsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7623_hifsys_compat,
+ .probe = mt7623_hifsys_probe,
+ .bind = mt7623_ethsys_hifsys_bind,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
U_BOOT_DRIVER(mtk_clk_ethsys) = {
.name = "mt7623-clock-ethsys",
.id = UCLASS_CLK,
.of_match = mt7623_ethsys_compat,
.probe = mt7623_ethsys_probe,
- .bind = mt7623_ethsys_bind,
+ .bind = mt7623_ethsys_hifsys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
int ret = 0;
#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
- ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
if (ret)
- debug("Warning: failed to bind ethsys reset controller\n");
+ debug("Warning: failed to bind reset controller\n");
#endif
return ret;
#define CLK_PARENT_TOPCKGEN BIT(5)
#define CLK_PARENT_MASK GENMASK(5, 4)
-#define ETHSYS_RST_CTRL_OFS 0x34
+#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
/* struct mtk_pll_data - hardware-specific PLLs data */
struct mtk_pll_data {
case CLKID_MPLL1:
case CLKID_MPLL2:
case CLKID_CLK81:
- if (current_rate != rate)
- return -EINVAL;
-
- return 0;
+ return -EINVAL;
case CLKID_VPU:
return meson_clk_set_rate_by_id(clk,
meson_mux_get_parent(clk, CLKID_VPU), rate,
config FPGA_SPARTAN3
bool "Enable Spartan3 FPGA driver"
+ depends on FPGA_XILINX
help
Enable Spartan3 FPGA driver for loading in BIT format.
+config FPGA_VIRTEX2
+ bool "Enable Xilinx Virtex-II and later FPGA driver"
+ depends on FPGA_XILINX
+ help
+ Enable Virtex-II FPGA driver for loading in BIT format. This driver
+ also supports many newer Xilinx FPGA families.
+
config FPGA_ZYNQPL
bool "Enable Xilinx FPGA for Zynq"
depends on ARCH_ZYNQ
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
-#define PRINTF(fmt,args...)
+#define PRINTF(fmt, args...)
#endif
/* Note: The assumption is that we cannot possibly run fast enough to
#endif
#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
+#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */
#endif
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
switch (desc->iface) {
case passive_serial:
- PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
- ret_val = CYC2_ps_load (desc, buf, bsize);
+ PRINTF("%s: Launching Passive Serial Loader\n", __func__);
+ ret_val = CYC2_ps_load(desc, buf, bsize);
break;
case fast_passive_parallel:
* done in the write() callback. Use the existing PS load
* function for FPP, too.
*/
- PRINTF ("%s: Launching Fast Passive Parallel Loader\n",
- __FUNCTION__);
+ PRINTF("%s: Launching Fast Passive Parallel Loader\n",
+ __func__);
ret_val = CYC2_ps_load(desc, buf, bsize);
break;
/* Add new interface types here */
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
switch (desc->iface) {
case passive_serial:
- PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
- ret_val = CYC2_ps_dump (desc, buf, bsize);
+ PRINTF("%s: Launching Passive Serial Dump\n", __func__);
+ ret_val = CYC2_ps_dump(desc, buf, bsize);
break;
/* Add new interface types here */
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
}
-int CYC2_info( Altera_desc *desc )
+int CYC2_info(Altera_desc *desc)
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
-/* CYCLON2 Passive Serial Generic Implementation */
+/* CYCLON2 Passive Serial Generic Implementation */
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
int ret = 0;
- PRINTF ("%s: start with interface functions @ 0x%p\n",
- __FUNCTION__, fn);
+ PRINTF("%s: start with interface functions @ 0x%p\n",
+ __func__, fn);
if (fn) {
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
- PRINTF ("%s: Function Table:\n"
+ PRINTF("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"write:\t0x%p\n"
"done:\t0x%p\n\n",
- __FUNCTION__, &fn, fn, fn->config, fn->status,
+ __func__, &fn, fn, fn->config, fn->status,
fn->write, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("Loading FPGA Device %d...", cookie);
+ printf("Loading FPGA Device %d...", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
- if (*fn->pre) {
+ if (*fn->pre)
(*fn->pre) (cookie);
- }
/* Establish the initial state */
(*fn->config) (false, true, cookie); /* De-assert nCONFIG */
udelay(2); /* T_cfg > 2us */
/* Wait for nSTATUS to be asserted */
- ts = get_timer (0); /* get current time */
+ ts = get_timer(0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
- puts ("** Timeout waiting for STATUS to go high.\n");
+ CONFIG_FPGA_DELAY();
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ /* check the time */
+ puts("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
} while (!(*fn->status) (cookie));
/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CONFIG_FPGA_DELAY();
ret = (*fn->write) (buf, bsize, true, cookie);
if (ret) {
- puts ("** Write failed.\n");
+ puts("** Write failed.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
puts(" OK? ...");
#endif
- CONFIG_FPGA_DELAY ();
+ CONFIG_FPGA_DELAY();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- putc (' '); /* terminate the dotted line */
+ putc(' '); /* terminate the dotted line */
#endif
- /*
- * Checking FPGA's CONF_DONE signal - correctly booted ?
- */
+ /*
+ * Checking FPGA's CONF_DONE signal - correctly booted ?
+ */
- if ( ! (*fn->done) (cookie) ) {
- puts ("** Booting failed! CONF_DONE is still deasserted.\n");
- (*fn->abort) (cookie);
- return (FPGA_FAIL);
- }
+ if (!(*fn->done) (cookie)) {
+ puts("** Booting failed! CONF_DONE is still deasserted.\n");
+ (*fn->abort) (cookie);
+ return FPGA_FAIL;
+ }
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- puts(" OK\n");
+ puts(" OK\n");
#endif
- ret_val = FPGA_SUCCESS;
+ ret_val = FPGA_SUCCESS;
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if (ret_val == FPGA_SUCCESS) {
- puts ("Done.\n");
- }
- else {
- puts ("Fail.\n");
- }
+ if (ret_val == FPGA_SUCCESS)
+ puts("Done.\n");
+ else
+ puts("Fail.\n");
#endif
- (*fn->post) (cookie);
+ /*
+ * Run the post configuration function if there is one.
+ */
+ if (*fn->post)
+ (*fn->post) (cookie);
} else {
- printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ printf("%s: NULL Interface function table!\n", __func__);
}
return ret_val;
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
- printf ("%s: Passive Serial Dumping is unavailable\n",
- __FUNCTION__);
+ printf("%s: Passive Serial Dumping is unavailable\n", __func__);
return FPGA_FAIL;
}
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com
+ *
+ * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
*/
/*
#endif
#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
-#define PRINTF(fmt,args...)
+#define PRINTF(fmt, args...)
#endif
/*
* If the SelectMap interface can be overrun by the processor, define
- * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
- * file and add board-specific support for checking BUSY status. By default,
- * assume that the SelectMap interface cannot be overrun.
+ * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
+ * configuration file and add board-specific support for checking BUSY status.
+ * By default, assume that the SelectMap interface cannot be overrun.
*/
#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_CHECK_BUSY
* an XC2V1000, if anyone can ever get ahold of one.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */
+#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
#endif
/*
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/
+#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
+#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
#endif
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
switch (desc->iface) {
case slave_serial:
- PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Serial Load\n", __func__);
ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
- PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Parallel Load\n", __func__);
ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
}
switch (desc->iface) {
case slave_serial:
- PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Serial Dump\n", __func__);
ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
- PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
}
}
/*
- * Virtex-II Slave SelectMap configuration loader. Configuration via
- * SelectMap is as follows:
+ * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
+ * is as follows:
* 1. Set the FPGA's PROG_B line low.
* 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
* 3. Write data to the SelectMap port. If INIT_B goes low at any time
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
-static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
{
- int ret_val = FPGA_FAIL;
- xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
+ unsigned long ts;
- PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
- __FUNCTION__, __LINE__, fn);
+ PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
+ __func__, __LINE__, fn);
- if (fn) {
- size_t bytecount = 0;
- unsigned char *data = (unsigned char *) buf;
- int cookie = desc->cookie;
- unsigned long ts;
-
- /* Gotta split this one up (so the stack won't blow??) */
- PRINTF ("%s:%d: Function Table:\n"
- " base 0x%p\n"
- " struct 0x%p\n"
- " pre 0x%p\n"
- " prog 0x%p\n"
- " init 0x%p\n"
- " error 0x%p\n",
- __FUNCTION__, __LINE__,
- &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
- PRINTF (" clock 0x%p\n"
- " cs 0x%p\n"
- " write 0x%p\n"
- " rdata 0x%p\n"
- " wdata 0x%p\n"
- " busy 0x%p\n"
- " abort 0x%p\n"
- " post 0x%p\n\n",
- fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
- fn->busy, fn->abort, fn->post);
+ if (!fn) {
+ printf("%s:%d: NULL Interface function table!\n",
+ __func__, __LINE__);
+ return FPGA_FAIL;
+ }
+
+ /* Gotta split this one up (so the stack won't blow??) */
+ PRINTF("%s:%d: Function Table:\n"
+ " base 0x%p\n"
+ " struct 0x%p\n"
+ " pre 0x%p\n"
+ " prog 0x%p\n"
+ " init 0x%p\n"
+ " error 0x%p\n",
+ __func__, __LINE__,
+ &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
+ PRINTF(" clock 0x%p\n"
+ " cs 0x%p\n"
+ " write 0x%p\n"
+ " rdata 0x%p\n"
+ " wdata 0x%p\n"
+ " busy 0x%p\n"
+ " abort 0x%p\n"
+ " post 0x%p\n\n",
+ fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
+ fn->busy, fn->abort, fn->post);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("Initializing FPGA Device %d...\n", cookie);
+ printf("Initializing FPGA Device %d...\n", cookie);
#endif
- /*
- * Run the pre configuration function if there is one.
- */
- if (*fn->pre) {
- (*fn->pre) (cookie);
+ /*
+ * Run the pre configuration function if there is one.
+ */
+ if (*fn->pre)
+ (*fn->pre)(cookie);
+
+ /*
+ * Assert the program line. The minimum pulse width for
+ * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
+ * There is no maximum value for the pulse width. Check to make
+ * sure that INIT_B goes low after assertion of PROG_B
+ */
+ (*fn->pgm)(true, true, cookie);
+ udelay(10);
+ ts = get_timer(0);
+ do {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
+ __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
+ } while (!(*fn->init)(cookie));
+
+ (*fn->pgm)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ if (fn->clk)
+ (*fn->clk)(true, true, cookie);
+
+ /*
+ * Start a timer and wait for INIT_B to go high
+ */
+ ts = get_timer(0);
+ do {
+ CONFIG_FPGA_DELAY();
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
+ __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
}
+ } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
- /*
- * Assert the program line. The minimum pulse width for
- * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
- * There is no maximum value for the pulse width. Check to make
- * sure that INIT_B goes low after assertion of PROG_B
- */
- (*fn->pgm) (true, true, cookie);
- udelay (10);
- ts = get_timer (0);
- do {
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
- " to assert.\n", __FUNCTION__, __LINE__,
- CONFIG_SYS_FPGA_WAIT_INIT);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
- } while (!(*fn->init) (cookie));
+ if (fn->wr)
+ (*fn->wr)(true, true, cookie);
+ if (fn->cs)
+ (*fn->cs)(true, true, cookie);
- (*fn->pgm) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
- (*fn->clk) (true, true, cookie);
+ mdelay(10);
+ return FPGA_SUCCESS;
+}
- /*
- * Start a timer and wait for INIT_B to go high
- */
- ts = get_timer (0);
- do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
- " to deassert.\n", __FUNCTION__, __LINE__,
- CONFIG_SYS_FPGA_WAIT_INIT);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
- } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
+static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
+ int cookie)
+{
+ int ret_val = FPGA_SUCCESS;
+ int num_done = 0;
+ unsigned long ts;
+
+ /*
+ * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
+ */
+ CONFIG_FPGA_DELAY();
+ if (fn->cs)
+ (*fn->cs)(false, true, cookie);
+ if (fn->wr)
+ (*fn->wr)(false, true, cookie);
- (*fn->wr) (true, true, cookie);
- (*fn->cs) (true, true, cookie);
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ putc('\n');
+#endif
- udelay (10000);
+ /*
+ * Check for successful configuration. FPGA INIT_B and DONE
+ * should both be high upon successful configuration. Continue pulsing
+ * clock with data set to all ones until DONE is asserted and for 8
+ * clock cycles afterwards.
+ */
+ ts = get_timer(0);
+ while (true) {
+ if ((*fn->done)(cookie) == FPGA_SUCCESS &&
+ !((*fn->init)(cookie))) {
+ if (num_done++ >= 8)
+ break;
+ }
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
+ __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+ (*fn->abort)(cookie);
+ ret_val = FPGA_FAIL;
+ break;
+ }
+ if (fn->wbulkdata) {
+ unsigned char dummy = 0xff;
+ (*fn->wbulkdata)(&dummy, 1, true, cookie);
+ } else {
+ (*fn->wdata)(0xff, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(true, true, cookie);
+ }
+ }
+
+ if (ret_val == FPGA_SUCCESS) {
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ printf("Initialization of FPGA device %d complete\n", cookie);
+#endif
/*
- * Load the data byte by byte
+ * Run the post configuration function if there is one.
*/
- while (bytecount < bsize) {
-#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
- if (ctrlc ()) {
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
+ if (*fn->post)
+ (*fn->post)(cookie);
+ } else {
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ printf("** Initialization of FPGA device %d FAILED\n",
+ cookie);
#endif
+ }
+ return ret_val;
+}
- if ((*fn->done) (cookie) == FPGA_SUCCESS) {
- PRINTF ("%s:%d:done went active early, bytecount = %d\n",
- __FUNCTION__, __LINE__, bytecount);
- break;
- }
-
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
- if ((*fn->init) (cookie)) {
- printf ("\n%s:%d: ** Error: INIT asserted during"
- " configuration\n", __FUNCTION__, __LINE__);
- printf ("%d = buffer offset, %d = buffer size\n",
- bytecount, bsize);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL;
+ xilinx_virtex2_slave_fns *fn = desc->iface_fns;
+ size_t bytecount = 0;
+ unsigned char *data = (unsigned char *)buf;
+ int cookie = desc->cookie;
+
+ ret_val = virtex2_slave_pre(fn, cookie);
+ if (ret_val != FPGA_SUCCESS)
+ return ret_val;
+
+ /*
+ * Load the data byte by byte
+ */
+ while (bytecount < bsize) {
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc()) {
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
#endif
- (*fn->wdata) (data[bytecount++], true, cookie);
- CONFIG_FPGA_DELAY ();
-
- /*
- * Cycle the clock pin
- */
- (*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
- (*fn->clk) (true, true, cookie);
+ if ((*fn->done)(cookie) == FPGA_SUCCESS) {
+ PRINTF("%s:%d:done went active early, bytecount = %d\n",
+ __func__, __LINE__, bytecount);
+ break;
+ }
-#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
- ts = get_timer (0);
- while ((*fn->busy) (cookie)) {
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for"
- " BUSY to deassert\n",
- __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
- }
+#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+ if ((*fn->init)(cookie)) {
+ printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
+ __func__, __LINE__);
+ printf("%zu = buffer offset, %zu = buffer size\n",
+ bytecount, bsize);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
#endif
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if (bytecount % (bsize / 40) == 0)
- putc ('.');
-#endif
- }
+ (*fn->wdata)(data[bytecount++], true, cookie);
+ CONFIG_FPGA_DELAY();
/*
- * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
+ * Cycle the clock pin
*/
- CONFIG_FPGA_DELAY ();
- (*fn->cs) (false, true, cookie);
- (*fn->wr) (false, true, cookie);
-
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- putc ('\n');
-#endif
+ (*fn->clk)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(true, true, cookie);
- /*
- * Check for successful configuration. FPGA INIT_B and DONE should
- * both be high upon successful configuration.
- */
- ts = get_timer (0);
- ret_val = FPGA_SUCCESS;
- while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
- "assert and INIT to deassert\n",
- __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
- (*fn->abort) (cookie);
- ret_val = FPGA_FAIL;
- break;
+#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
+ ts = get_timer(0);
+ while ((*fn->busy)(cookie)) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
+ __func__, __LINE__,
+ CONFIG_SYS_FPGA_WAIT_BUSY);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
}
}
-
- if (ret_val == FPGA_SUCCESS) {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("Initialization of FPGA device %d complete\n", cookie);
#endif
- /*
- * Run the post configuration function if there is one.
- */
- if (*fn->post) {
- (*fn->post) (cookie);
- }
- } else {
+
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("** Initialization of FPGA device %d FAILED\n",
- cookie);
+ if (bytecount % (bsize / 40) == 0)
+ putc('.');
#endif
- }
- } else {
- printf ("%s:%d: NULL Interface function table!\n",
- __FUNCTION__, __LINE__);
}
- return ret_val;
+
+ return virtex2_slave_post(fn, cookie);
}
/*
static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_fns *fn = desc->iface_fns;
if (fn) {
- unsigned char *data = (unsigned char *) buf;
+ unsigned char *data = (unsigned char *)buf;
size_t bytecount = 0;
int cookie = desc->cookie;
- printf ("Starting Dump of FPGA Device %d...\n", cookie);
+ printf("Starting Dump of FPGA Device %d...\n", cookie);
- (*fn->cs) (true, true, cookie);
- (*fn->clk) (true, true, cookie);
+ (*fn->cs)(true, true, cookie);
+ (*fn->clk)(true, true, cookie);
while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
- if (ctrlc ()) {
- (*fn->abort) (cookie);
+ if (ctrlc()) {
+ (*fn->abort)(cookie);
return FPGA_FAIL;
}
#endif
/*
* Cycle the clock and read the data
*/
- (*fn->clk) (false, true, cookie);
- (*fn->clk) (true, true, cookie);
- (*fn->rdata) (&(data[bytecount++]), cookie);
+ (*fn->clk)(false, true, cookie);
+ (*fn->clk)(true, true, cookie);
+ (*fn->rdata)(&data[bytecount++], cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
- putc ('.');
+ putc('.');
#endif
}
/*
* Deassert CS_B and cycle the clock to deselect the device.
*/
- (*fn->cs) (false, false, cookie);
- (*fn->clk) (false, true, cookie);
- (*fn->clk) (true, true, cookie);
+ (*fn->cs)(false, false, cookie);
+ (*fn->clk)(false, true, cookie);
+ (*fn->clk)(true, true, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- putc ('\n');
+ putc('\n');
#endif
- puts ("Done.\n");
+ puts("Done.\n");
} else {
- printf ("%s:%d: NULL Interface function table!\n",
- __FUNCTION__, __LINE__);
+ printf("%s:%d: NULL Interface function table!\n",
+ __func__, __LINE__);
}
return ret_val;
}
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
- printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
- return FPGA_FAIL;
+ int ret_val = FPGA_FAIL;
+ xilinx_virtex2_slave_fns *fn = desc->iface_fns;
+ unsigned char *data = (unsigned char *)buf;
+ int cookie = desc->cookie;
+
+ ret_val = virtex2_slave_pre(fn, cookie);
+ if (ret_val != FPGA_SUCCESS)
+ return ret_val;
+
+ if (fn->wbulkdata) {
+ /* Load the data in a single chunk */
+ (*fn->wbulkdata)(data, bsize, true, cookie);
+ } else {
+ size_t bytecount = 0;
+
+ /*
+ * Load the data bit by bit
+ */
+ while (bytecount < bsize) {
+ unsigned char curr_data = data[bytecount++];
+ int bit;
+
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc()) {
+ (*fn->abort) (cookie);
+ return FPGA_FAIL;
+ }
+#endif
+
+ if ((*fn->done)(cookie) == FPGA_SUCCESS) {
+ PRINTF("%s:%d:done went active early, bytecount = %d\n",
+ __func__, __LINE__, bytecount);
+ break;
+ }
+
+#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+ if ((*fn->init)(cookie)) {
+ printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
+ __func__, __LINE__);
+ printf("%zu = buffer offset, %zu = buffer size\n",
+ bytecount, bsize);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
+#endif
+
+ for (bit = 7; bit >= 0; --bit) {
+ unsigned char curr_bit = (curr_data >> bit) & 1;
+ (*fn->wdata)(curr_bit, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(true, true, cookie);
+ }
+
+ /* Slave serial never uses a busy pin */
+
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ if (bytecount % (bsize / 40) == 0)
+ putc('.');
+#endif
+ }
+ }
+
+ return virtex2_slave_post(fn, cookie);
}
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
- printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
+ printf("%s: Slave Serial Dumping is unsupported\n", __func__);
return FPGA_FAIL;
}
MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
#if !defined(CONFIG_MMC_BROKEN_CD)
- /* we pretend there's no card when init is NULL */
no_card = mmc_getcd(mmc) == 0;
#else
no_card = 0;
#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
+ /* we pretend there's no card when init is NULL */
no_card = no_card || (mmc->cfg->ops->init == NULL);
#endif
if (no_card) {
#include <errno.h>
#include <malloc.h>
#include <stdbool.h>
+#include <watchdog.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
u32 size;
int ret;
+ WATCHDOG_RESET();
+
if (data->flags == MMC_DATA_WRITE)
host->last_data_write = 1;
host->name = MVSDH_NAME;
host->ioaddr = (void *)devfdt_get_addr(dev);
host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
sdhci_mvebu_mbus_config(host->ioaddr);
}
- host->mmc = &plat->mmc;
- host->mmc->dev = dev;
- host->mmc->priv = host;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
struct udevice *dev = mmc->dev;
- gpio_request_by_name(dev, "cd-gpio", 0,
+ gpio_request_by_name(dev, "cd-gpios", 0,
&host->cd_gpio, GPIOD_IS_IN);
#endif
layout = &nand_keystone_rbl_4bit_layout_oobfirst;
layout->oobavail = 0;
- for (i = 0; layout->oobfree[i].length &&
- i < ARRAY_SIZE(layout->oobfree); i++)
+ for (i = 0; i < ARRAY_SIZE(layout->oobfree) &&
+ layout->oobfree[i].length; i++)
layout->oobavail += layout->oobfree[i].length;
nand->write_page = nand_davinci_write_page;
int flags = ep_bar->flags;
/* Some basic bar validity checks */
- if (ep_bar->barno > BAR_5 || ep_bar < BAR_0)
+ if (ep_bar->barno > BAR_5 || ep_bar->barno < BAR_0)
return -EINVAL;
if ((ep_bar->barno == BAR_5 &&
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP3_17_15,
GP_0_30_FN, FN_IP3_14_12,
GP_0_29_FN, FN_IP3_11_8,
GP_0_3_FN, FN_IP0_11_9,
GP_0_2_FN, FN_IP0_8_6,
GP_0_1_FN, FN_IP0_5_3,
- GP_0_0_FN, FN_IP0_2_0 }
+ GP_0_0_FN, FN_IP0_2_0 ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
GP_1_29_FN, FN_IP6_13_11,
GP_1_3_FN, FN_IP3_28_26,
GP_1_2_FN, FN_IP3_25_23,
GP_1_1_FN, FN_IP3_22_20,
- GP_1_0_FN, FN_IP3_19_18, }
+ GP_1_0_FN, FN_IP3_19_18, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
0, 0,
0, 0,
GP_2_29_FN, FN_IP7_15_13,
GP_2_3_FN, FN_IP8_3_2,
GP_2_2_FN, FN_IP8_1_0,
GP_2_1_FN, FN_IP7_30_29,
- GP_2_0_FN, FN_IP7_28_27 }
+ GP_2_0_FN, FN_IP7_28_27 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP11_21_18,
GP_3_30_FN, FN_IP11_17_15,
GP_3_29_FN, FN_IP11_14_13,
GP_3_3_FN, FN_IP9_3_2,
GP_3_2_FN, FN_IP9_1_0,
GP_3_1_FN, FN_IP8_30_29,
- GP_3_0_FN, FN_IP8_28 }
+ GP_3_0_FN, FN_IP8_28 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP14_18_16,
GP_4_30_FN, FN_IP14_15_12,
GP_4_29_FN, FN_IP14_11_9,
GP_4_3_FN, FN_IP11_31_30,
GP_4_2_FN, FN_IP11_29_27,
GP_4_1_FN, FN_IP11_26_24,
- GP_4_0_FN, FN_IP11_23_22 }
+ GP_4_0_FN, FN_IP11_23_22 ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP7_24_22,
GP_5_30_FN, FN_IP7_21_19,
GP_5_29_FN, FN_IP7_18_16,
GP_5_3_FN, FN_IP14_30_28,
GP_5_2_FN, FN_IP14_27_25,
GP_5_1_FN, FN_IP14_24_22,
- GP_5_0_FN, FN_IP14_21_19 }
+ GP_5_0_FN, FN_IP14_21_19 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
+ GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
+ GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30_27 [4] */
0, 0, 0,
/* IP0_2_0 [3] */
FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
+ GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
+ GROUP(
/* IP1_31_30 [2] */
0, 0, 0, 0,
/* IP1_29_28 [2] */
/* IP1_3_0 [4] */
FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
+ GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP2_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_28_26 [3] */
/* IP2_5_3 [3] */
FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
/* IP2_2_0 [3] */
- FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
+ FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
- 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
+ GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
+ GROUP(
/* IP3_31_29 [3] */
FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
0, 0, 0,
/* IP3_3_0 [4] */
FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, }
+ 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP4_31_30 [2] */
0, 0, 0, 0,
/* IP4_29_27 [3] */
FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
/* IP4_2_0 [3] */
FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
- }
+ ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
+ GROUP(
/* IP5_31_30 [2] */
0, 0, 0, 0,
/* IP5_29_27 [3] */
FN_INTC_EN0_N, FN_I2C1_SCL,
/* IP5_2_0 [3] */
FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
- FN_VI2_R3, 0, 0, }
+ FN_VI2_R3, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+ GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
+ GROUP(
/* IP6_31_29 [3] */
FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
/* IP6_2_0 [3] */
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
- FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+ FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+ GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
+ GROUP(
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_MDIO, 0, FN_HRTS0_N_E,
- FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+ FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2) {
+ GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2),
+ GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30_29 [2] */
/* IP8_3_2 [2] */
FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
/* IP8_1_0 [2] */
- FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+ GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
+ GROUP(
/* IP9_31_28 [4] */
FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
/* IP9_3_2 [2] */
FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
/* IP9_1_0 [2] */
- FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- 2, 4, 3, 4, 4, 4, 4, 3, 4) {
+ GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
+ GROUP(
/* IP10_31_30 [2] */
0, 0, 0, 0,
/* IP10_29_26 [4] */
/* IP10_3_0 [4] */
FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
- FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+ FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+ GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
+ GROUP(
/* IP11_31_30 [2] */
FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
/* IP11_29_27 [3] */
/* IP11_3_0 [4] */
FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
- FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+ GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
+ GROUP(
/* IP12_31 [1] */
0, 0,
/* IP12_30_28 [3] */
/* IP12_3_2 [2] */
FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
/* IP12_1_0 [2] */
- FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
+ FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
+ GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
+ GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30_29 [2] */
FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_2_0 [3] */
FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
- FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
+ FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
+ GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
+ GROUP(
/* IP14_30 [1] */
0, 0,
/* IP14_30_28 [3] */
/* IP14_2_0 [3] */
FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
- FN_REMOCON, 0, }
+ FN_REMOCON, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
+ GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
+ GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_29_28 [2] */
FN_IIC2_SCL, FN_I2C2_SCL, 0,
/* IP15_2_0 [3] */
FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
- FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
+ FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
+ GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
+ GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
/* IP16_2_0 [3] */
FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
- FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
+ FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+ GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
+ 1, 1, 1, 2, 1, 1, 2, 1, 1),
+ GROUP(
/* SEL_SCIF1 [3] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF1_4, 0, 0, 0,
/* SEL_SOF3 [1] */
FN_SEL_SOF3_0, FN_SEL_SOF3_1,
/* SEL_SOF0 [1] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 1, 2, 1, 2, 1, 2,
- 1, 1, 1, 3, 3, 2, 3, 2, 2) {
+ GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
+ 3, 3, 2, 3, 2, 2),
+ GROUP(
/* RESERVED [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_TMU1 [1] */
/* SEL_SIM [2] */
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
/* SEL_SSI8 [2] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 1, 1, 2, 4, 4, 2, 2,
- 4, 2, 3, 2, 3, 2) {
+ GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
+ GROUP(
/* SEL_IICDVFS [1] */
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
/* SEL_IIC0 [1] */
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
FN_SEL_I2C2_4, 0, 0, 0,
/* SEL_I2C1 [2] */
- FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
},
{ },
};
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP1_22_20,
GP_0_30_FN, FN_IP1_19_17,
GP_0_29_FN, FN_IP1_16_14,
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0, }
+ GP_0_0_FN, FN_IP0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, FN_IP2_2_0,
GP_1_2_FN, FN_IP1_31_29,
GP_1_1_FN, FN_IP1_28_26,
- GP_1_0_FN, FN_IP1_25_23, }
+ GP_1_0_FN, FN_IP1_25_23, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7_6,
GP_2_30_FN, FN_IP6_5_3,
GP_2_29_FN, FN_IP6_2_0,
GP_2_3_FN, FN_IP4_4_2,
GP_2_2_FN, FN_IP4_1_0,
GP_2_1_FN, FN_IP3_30_28,
- GP_2_0_FN, FN_IP3_27_25 }
+ GP_2_0_FN, FN_IP3_27_25 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP9_18_17,
GP_3_30_FN, FN_IP9_16,
GP_3_29_FN, FN_IP9_15_13,
GP_3_3_FN, FN_IP7_12_11,
GP_3_2_FN, FN_IP7_10_9,
GP_3_1_FN, FN_IP7_8_6,
- GP_3_0_FN, FN_IP7_5_3 }
+ GP_3_0_FN, FN_IP7_5_3 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP15_5_4,
GP_4_30_FN, FN_IP15_3_2,
GP_4_29_FN, FN_IP15_1_0,
GP_4_3_FN, FN_IP9_24_23,
GP_4_2_FN, FN_IP9_22_21,
GP_4_1_FN, FN_IP9_20_19,
- GP_4_0_FN, FN_VI0_CLK }
+ GP_4_0_FN, FN_VI0_CLK ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP3_24_22,
GP_5_30_FN, FN_IP13_9_7,
GP_5_29_FN, FN_IP13_6_5,
GP_5_3_FN, FN_IP11_18_17,
GP_5_2_FN, FN_IP11_16_15,
GP_5_1_FN, FN_IP11_14_12,
- GP_5_0_FN, FN_IP11_11_9 }
+ GP_5_0_FN, FN_IP11_11_9 ))
},
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
GP_6_31_FN, FN_DU0_DOTCLKIN,
GP_6_30_FN, FN_USB1_OVC,
GP_6_29_FN, FN_IP14_31_29,
GP_6_3_FN, FN_IP13_13,
GP_6_2_FN, FN_IP13_12,
GP_6_1_FN, FN_IP13_11,
- GP_6_0_FN, FN_IP13_10 }
+ GP_6_0_FN, FN_IP13_10 ))
},
- { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_7_3_FN, FN_IP15_26_24,
GP_7_2_FN, FN_IP15_23_21,
GP_7_1_FN, FN_IP15_20_18,
- GP_7_0_FN, FN_IP15_17_15 }
+ GP_7_0_FN, FN_IP15_17_15 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30_29 [2] */
/* IP0_1 [1] */
FN_D1, 0,
/* IP0_0 [1] */
- FN_D0, 0, }
+ FN_D0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+ GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
+ GROUP(
/* IP1_31_29 [3] */
FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
0, 0, 0,
FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
/* IP1_1_0 [2] */
FN_A7, FN_MSIOF1_SYNC,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
+ GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
+ GROUP(
/* IP2_31_30 [2] */
0, 0, 0, 0,
/* IP2_29_27 [3] */
FN_A20, FN_SPCLK, 0, 0,
/* IP2_2_0 [3] */
FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
- FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
+ FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
- 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
+ GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
+ GROUP(
/* IP3_31 [1] */
0, 0,
/* IP3_30_28 [3] */
FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
/* IP3_2_0 [3] */
FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
+ GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
+ 3, 3, 2),
+ GROUP(
/* IP4_31 [1] */
0, 0,
/* IP4_30_28 [3] */
FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
0, 0, 0,
/* IP4_1_0 [2] */
- FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
+ FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
+ ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
+ GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP5_31_29 [3] */
FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
0, 0, 0, 0, 0,
/* IP5_2_0 [3] */
FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
FN_MSIOF2_TXD_D, FN_VI1_R3_B,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
+ GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
+ GROUP(
/* IP6_31_30 [2] */
0, 0, 0, 0,
/* IP6_29_27 [3] */
/* IP6_2_0 [3] */
FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
+ GROUP(
/* IP7_31_30 [2] */
0, 0, 0, 0,
/* IP7_29_27 [3] */
/* IP7_2_0 [3] */
FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
FN_SCIF_CLK_B, FN_GPS_MAG_D,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30_28 [3] */
0, 0,
/* IP8_2_0 [3] */
FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
+ GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
+ 1, 1, 3, 3),
+ GROUP(
/* IP9_31_29 [3] */
FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
0, 0, 0,
/* IP9_2_0 [3] */
FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
+ GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP10_31_29 [3] */
FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
0, 0, 0,
FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
/* IP10_2_0 [3] */
FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
- FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
+ FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 3, 3, 3, 3, 3) {
+ GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
+ 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP11_31_30 [2] */
FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
/* IP11_29_28 [2] */
0, 0, 0,
/* IP11_2_0 [3] */
FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
- FN_I2C1_SDA_D, 0, 0, 0, }
+ FN_I2C1_SDA_D, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+ GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
+ GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_29_27 [3] */
/* IP12_3_2 [2] */
FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
/* IP12_1_0 [2] */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
+ FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
- 3, 2, 2, 3) {
+ GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
+ 1, 1, 1, 3, 2, 2, 3),
+ GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30_28 [3] */
/* IP13_2_0 [3] */
FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
FN_ADICLK_B, FN_MSIOF0_SS1_C,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
+ GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
+ 1, 1, 2),
+ GROUP(
/* IP14_31_29 [3] */
FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
/* IP14_2 [1] */
FN_SD2_CLK, FN_MMC_CLK,
/* IP14_1_0 [2] */
- FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
+ FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
+ GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
+ GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_29_27 [3] */
/* IP15_3_2 [2] */
FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
/* IP15_1_0 [2] */
- FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
+ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
+ GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
+ GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_2_0 [3] */
FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
FN_GLO_SDATA_C, FN_VI1_DATA6_C,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
- 3, 2, 2, 2, 1, 2, 2, 2) {
+ GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
+ 2, 2, 1, 2, 2, 2),
+ GROUP(
/* RESERVED [1] */
0, 0,
/* SEL_SCIF1 [2] */
/* SEL_TSIF0 [2] */
FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
/* SEL_SOF0 [2] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 3, 2, 1, 1, 2, 2,
- 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+ GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
+ 1, 2, 2, 2, 1, 1, 1),
+ GROUP(
/* SEL_SCIF0 [3] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
/* RESERVED [1] */
0, 0,
/* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 1, 1, 2, 2, 3, 2, 2, 2, 1) {
+ GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
+ 3, 2, 2, 2, 1),
+ GROUP(
/* SEL_HSCIF2 [2] */
FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [1] */
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
- 3, 2, 2, 1, 1, 1, 1, 3, 2,
- 2, 3, 1, 1, 1, 2, 2, 2, 2) {
+ GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
+ 1, 1, 2, 2, 2, 2),
+ GROUP(
/* SEL_SOF1 [3] */
FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
FN_SEL_SOF1_4,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [2] */
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ },
};
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0 }
+ GP_0_0_FN, FN_IP0_0 ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, FN_IP1_8,
GP_1_2_FN, FN_IP1_7,
GP_1_1_FN, FN_IP1_6,
- GP_1_0_FN, FN_IP1_5, }
+ GP_1_0_FN, FN_IP1_5, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_A15,
GP_2_30_FN, FN_A14,
GP_2_29_FN, FN_A13,
GP_2_3_FN, FN_D3,
GP_2_2_FN, FN_D2,
GP_2_1_FN, FN_D1,
- GP_2_0_FN, FN_D0 }
+ GP_2_0_FN, FN_D0 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_3_3_FN, FN_A19,
GP_3_2_FN, FN_A18,
GP_3_1_FN, FN_A17,
- GP_3_0_FN, FN_A16 }
+ GP_3_0_FN, FN_A16 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_4_3_FN, FN_VI0_VSYNC_N,
GP_4_2_FN, FN_VI0_HSYNC_N,
GP_4_1_FN, FN_VI0_CLKENB,
- GP_4_0_FN, FN_VI0_CLK }
+ GP_4_0_FN, FN_VI0_CLK ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, FN_VI1_VSYNC_N,
GP_5_2_FN, FN_VI1_HSYNC_N,
GP_5_1_FN, FN_VI1_CLKENB,
- GP_5_0_FN, FN_VI1_CLK }
+ GP_5_0_FN, FN_VI1_CLK ))
},
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_6_3_FN, FN_IP2_3,
GP_6_2_FN, FN_IP2_2,
GP_6_1_FN, FN_IP2_1,
- GP_6_0_FN, FN_IP2_0 }
+ GP_6_0_FN, FN_IP2_0 ))
},
- { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_7_3_FN, FN_IP3_3,
GP_7_2_FN, FN_IP3_2,
GP_7_1_FN, FN_IP3_1,
- GP_7_0_FN, FN_IP3_0 }
+ GP_7_0_FN, FN_IP3_0 ))
},
- { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
+ { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_8_3_FN, FN_IP4_3_2,
GP_8_2_FN, FN_IP4_1,
GP_8_1_FN, FN_IP4_0,
- GP_8_0_FN, FN_VI4_CLK }
+ GP_8_0_FN, FN_VI4_CLK ))
},
- { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
+ { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_9_3_FN, FN_IP5_2,
GP_9_2_FN, FN_IP5_1,
GP_9_1_FN, FN_IP5_0,
- GP_9_0_FN, FN_VI5_CLK }
+ GP_9_0_FN, FN_VI5_CLK ))
},
- { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
GP_10_31_FN, FN_CAN1_RX,
GP_10_30_FN, FN_CAN1_TX,
GP_10_29_FN, FN_CAN_CLK,
GP_10_3_FN, FN_IP6_2,
GP_10_2_FN, FN_HRTS0_N,
GP_10_1_FN, FN_IP6_1,
- GP_10_0_FN, FN_IP6_0 }
+ GP_10_0_FN, FN_IP6_0 ))
},
- { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
+ { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
0, 0,
0, 0,
GP_11_29_FN, FN_AVS2,
GP_11_3_FN, FN_IP7_6,
GP_11_2_FN, FN_IP7_5_4,
GP_11_1_FN, FN_IP7_3_2,
- GP_11_0_FN, FN_IP7_1_0 }
+ GP_11_0_FN, FN_IP7_1_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
- 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP0_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_27_24 [4] */
/* IP0_1 [1] */
FN_DU0_DR1_DATA1, 0,
/* IP0_0 [1] */
- FN_DU0_DR0_DATA0, 0 }
+ FN_DU0_DR0_DATA0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
- 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP1_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_27_24 [4] */
/* IP1_1 [1] */
FN_DU0_EXVSYNC_DU0_VSYNC, 0,
/* IP1_0 [1] */
- FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
+ FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
- 4, 4,
- 4, 3, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 3, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP2_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_27_24 [4] */
/* IP2_1 [1] */
FN_VI2_CLKENB, FN_AVB_RX_DV,
/* IP2_0 [1] */
- FN_VI2_CLK, FN_AVB_RX_CLK }
+ FN_VI2_CLK, FN_AVB_RX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
- 4, 4,
- 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP3_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_27_24 [4] */
/* IP3_1 [1] */
FN_VI3_CLKENB, FN_AVB_TXD4,
/* IP3_0 [1] */
- FN_VI3_CLK, FN_AVB_TX_CLK }
+ FN_VI3_CLK, FN_AVB_TX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
- 4, 3, 1,
- 1, 1, 1, 2, 2, 2,
- 2, 2, 2, 2, 2, 1, 2, 1, 1) {
+ GROUP(4, 3, 1,
+ 1, 1, 1, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 2, 1, 1),
+ GROUP(
/* IP4_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_27_25 [3] */
/* IP4_1 [1] */
FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
/* IP4_0 [1] */
- FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
+ FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
- 4, 4,
- 4, 4,
- 4, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 4,
+ 4, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP5_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_27_24 [4] */
/* IP5_1 [1] */
FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
/* IP5_0 [1] */
- FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
+ FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
- 4, 4,
- 4, 1, 2, 1,
- 2, 2, 2, 2,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 1, 2, 1,
+ 2, 2, 2, 2,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP6_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_27_24 [4] */
/* IP6_1 [1] */
FN_MSIOF0_SYNC, FN_HCTS0_N,
/* IP6_0 [1] */
- FN_MSIOF0_SCK, FN_HSCK0 }
+ FN_MSIOF0_SCK, FN_HSCK0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
- 4, 4,
- 3, 1, 1, 1, 1, 1,
- 2, 2, 2, 2,
- 1, 1, 2, 2, 2) {
+ GROUP(4, 4,
+ 3, 1, 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 1, 1, 2, 2, 2),
+ GROUP(
/* IP7_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_27_24 [4] */
/* IP7_3_2 [2] */
FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
/* IP7_1_0 [2] */
- FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
+ FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
{ },
};
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP2_17_16,
GP_0_30_FN, FN_IP2_15_14,
GP_0_29_FN, FN_IP2_13_12,
GP_0_3_FN, FN_IP0_27_26,
GP_0_2_FN, FN_IP0_25,
GP_0_1_FN, FN_IP0_24,
- GP_0_0_FN, FN_IP0_23_22, }
+ GP_0_0_FN, FN_IP0_23_22, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, FN_IP2_29_27,
GP_1_2_FN, FN_IP2_26_24,
GP_1_1_FN, FN_IP2_23_21,
- GP_1_0_FN, FN_IP2_20_18, }
+ GP_1_0_FN, FN_IP2_20_18, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7_6,
GP_2_30_FN, FN_IP6_5_4,
GP_2_29_FN, FN_IP6_3_2,
GP_2_3_FN, FN_IP4_11_10,
GP_2_2_FN, FN_IP4_9_8,
GP_2_1_FN, FN_IP4_7_5,
- GP_2_0_FN, FN_IP4_4_2 }
+ GP_2_0_FN, FN_IP4_4_2 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP8_22_20,
GP_3_30_FN, FN_IP8_19_17,
GP_3_29_FN, FN_IP8_16_15,
GP_3_3_FN, FN_IP6_11,
GP_3_2_FN, FN_IP6_10,
GP_3_1_FN, FN_IP6_9,
- GP_3_0_FN, FN_IP6_8 }
+ GP_3_0_FN, FN_IP6_8 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP11_17_16,
GP_4_30_FN, FN_IP11_15_14,
GP_4_29_FN, FN_IP11_13_11,
GP_4_3_FN, FN_IP9_2_0,
GP_4_2_FN, FN_IP8_31_29,
GP_4_1_FN, FN_IP8_28_26,
- GP_4_0_FN, FN_IP8_25_23 }
+ GP_4_0_FN, FN_IP8_25_23 ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, FN_IP11_29_27,
GP_5_2_FN, FN_IP11_26_24,
GP_5_1_FN, FN_IP11_23_21,
- GP_5_0_FN, FN_IP11_20_18 }
+ GP_5_0_FN, FN_IP11_20_18 ))
},
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_6_3_FN, FN_SD0_DATA1,
GP_6_2_FN, FN_SD0_DATA0,
GP_6_1_FN, FN_SD0_CMD,
- GP_6_0_FN, FN_SD0_CLK }
+ GP_6_0_FN, FN_SD0_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
- 2, 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP0_31_30 [2] */
FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
/* IP0_29_28 [2] */
/* IP0_1 [1] */
0, 0,
/* IP0_0 [1] */
- FN_SD1_CD, FN_CAN0_RX, }
+ FN_SD1_CD, FN_CAN0_RX, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
- 2, 2) {
+ GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
+ 3, 2, 2, 2, 2),
+ GROUP(
/* IP1_31_30 [2] */
FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
/* IP1_29_28 [2] */
/* IP1_3_2 [2] */
FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
/* IP1_1_0 [2] */
- FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
+ FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
+ GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
+ GROUP(
/* IP2_31_30 [2] */
FN_A20, FN_SPCLK, 0, 0,
/* IP2_29_27 [3] */
/* IP2_3_2 [2] */
FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
/* IP2_1_0 [2] */
- FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
+ FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
- 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
+ GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
+ 2, 2, 2, 2),
+ GROUP(
/* IP3_31 [1] */
FN_RD_WR_N, FN_ATAG1_N,
/* IP3_30 [1] */
/* IP3_3_2 [2] */
FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
/* IP3_1_0 [2] */
- FN_A21, FN_MOSI_IO0, 0, 0, }
+ FN_A21, FN_MOSI_IO0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
+ GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
+ GROUP(
/* IP4_31_30 [2] */
FN_DU0_DG4, FN_LCDOUT12, 0, 0,
/* IP4_29_28 [2] */
FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
0, 0, 0, 0,
/* IP4_1_0 [2] */
- FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
+ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
+ GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
+ 2, 2, 2),
+ GROUP(
/* IP5_31_30 [2] */
FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
/* IP5_29_28 [2] */
/* IP5_3_2 [2] */
FN_DU0_DG6, FN_LCDOUT14, 0, 0,
/* IP5_1_0 [2] */
- FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
+ FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 2, 2) {
+ GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 2, 2, 2, 2),
+ GROUP(
/* IP6_31_29 [3] */
FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
0,
/* IP6_1_0 [2] */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP7_31 [1] */
FN_DREQ0_N, FN_SCIFB1_RXD,
/* IP7_30 [1] */
FN_AVB_TXD1, FN_ADICLK, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
- FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
+ FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
+ GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP8_31_29 [3] */
FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
/* IP8_2_0 [3] */
FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
- FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
+ FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
+ GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP9_31 [1] */
0, 0,
/* IP9_30_28 [3] */
0, FN_TPUTO1_C, 0, 0,
/* IP9_2_0 [3] */
FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
- 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
+ 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP10_31_30 [2] */
FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
/* IP10_29_27 [3] */
0, 0, 0, 0,
/* IP10_2_0 [3] */
FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
+ GROUP(
/* IP11_31_30 [2] */
0, 0, 0, 0,
/* IP11_29_27 [3] */
0, 0, 0, 0,
/* IP11_2_0 [3] */
FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
+ GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_29_27 [3] */
FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
/* IP12_2_0 [3] */
FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
- 0, FN_DREQ1_N_B, 0, 0, }
+ 0, FN_DREQ1_N_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30 [1] */
FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
/* IP13_2_0 [3] */
FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
- 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
+ 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
- 2, 1) {
+ GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
+ GROUP(
/* SEL_ADG [2] */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
/* RESERVED [1] */
/* SEL_I2C05 [2] */
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
/* RESERVED [1] */
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
- 2, 2, 2, 1, 1, 2) {
+ GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
+ 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
+ GROUP(
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_IIC0 [2] */
/* SEL_HSCIF1 [1] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
/* RESERVED [2] */
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* SEL_SCIF0 [2] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
/* SEL_SCIF1 [2] */
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
- 0, 0, }
+ 0, 0, ))
},
{ },
};
/*
* R8A7795 ES2.0+ processor support - PFC hardware block.
*
- * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ * Copyright (C) 2015-2019 Renesas Electronics Corporation
*/
#include <common.h>
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
/* GPSR7 */
-#define GPSR7_3 FM(HDMI1_CEC)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_3 FM(GP7_03)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
- PINMUX_SINGLE(HDMI0_CEC),
- PINMUX_SINGLE(HDMI1_CEC),
+ PINMUX_SINGLE(GP7_02),
+ PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
DU_DISP_MARK,
};
-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi0_cec_pins[] = {
- /* HDMI0_CEC */
- RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hdmi0_cec_mux[] = {
- HDMI0_CEC_MARK,
-};
-static const unsigned int hdmi1_cec_pins[] = {
- /* HDMI1_CEC */
- RCAR_GP_PIN(7, 3),
-};
-static const unsigned int hdmi1_cec_mux[] = {
- HDMI1_CEC_MARK,
-};
-
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hdmi0_cec),
- SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
"du_disp",
};
-static const char * const hdmi0_groups[] = {
- "hdmi0_cec",
-};
-
-static const char * const hdmi1_groups[] = {
- "hdmi1_cec",
-};
-
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hdmi0),
- SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
- GP_7_0_FN, GPSR7_0, }
+ GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
- { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
IP16_15_12
IP16_11_8
IP16_7_4
- IP16_3_0 }
+ IP16_3_0 ))
},
- { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
IP17_15_12
IP17_11_8
IP17_7_4
- IP17_3_0 }
+ IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
+ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
- IP18_3_0 }
+ IP18_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
+ 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 2, 3, 1, 2, 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
+ 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
- MOD_SEL1_0 }
+ MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
- 4, 4, 4, 3, 1) {
+ GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
+ 1, 4, 4, 4, 3, 1),
+ GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
- MOD_SEL2_0 }
+ MOD_SEL2_0 ))
},
{ },
};
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
- { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
} },
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
- [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
+ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
} },
/*
* R8A7796 processor support - PFC hardware block.
*
- * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
*
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
- PINMUX_SINGLE(HDMI0_CEC),
+ PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
- PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
- PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
- /* I2C */
- PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
-
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
DU_DISP_MARK,
};
-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi0_cec_pins[] = {
- /* HDMI0_CEC */
- RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hdmi0_cec_mux[] = {
- HDMI0_CEC_MARK,
-};
-
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
};
static const struct {
- struct sh_pfc_pin_group common[310];
- struct sh_pfc_pin_group automotive[33];
+ struct sh_pfc_pin_group common[312];
+ struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(vin5_clk),
},
.automotive = {
- SH_PFC_PIN_GROUP(canfd0_data_a),
- SH_PFC_PIN_GROUP(canfd0_data_b),
- SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
"du_disp",
};
-static const char * const hdmi0_groups[] = {
- "hdmi0_cec",
-};
-
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
};
static const struct {
- struct sh_pfc_function common[48];
- struct sh_pfc_function automotive[6];
+ struct sh_pfc_function common[49];
+ struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(vin5),
},
.automotive = {
- SH_PFC_FUNCTION(canfd0),
- SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
- GP_7_0_FN, GPSR7_0, }
+ GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
- { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
IP16_15_12
IP16_11_8
IP16_7_4
- IP16_3_0 }
+ IP16_3_0 ))
},
- { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
IP17_15_12
IP17_11_8
IP17_7_4
- IP17_3_0 }
+ IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
+ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
- IP18_3_0 }
+ IP18_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
+ 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 2, 3, 1, 2, 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
+ 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
- MOD_SEL1_0 }
+ MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
- 4, 4, 4, 3, 1) {
+ GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
+ 1, 4, 4, 4, 3, 1),
+ GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
- MOD_SEL2_0 }
+ MOD_SEL2_0 ))
},
{ },
};
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
* R8A77965 processor support - PFC hardware block.
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
+#define PINMUX_PHYS \
+ FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
enum {
PINMUX_RESERVED = 0,
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+ PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
- PINMUX_SINGLE(HDMI0_CEC),
+ PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
- PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
- PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
- PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
- PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
- PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
- PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
- PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
- PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
- PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
- PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
- PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
- PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
- PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
- /* I2C */
- PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
-
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
};
/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int i2c0_mux[] = {
+ SCL0_MARK, SDA0_MARK,
+};
+
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
};
+
static const unsigned int i2c1_a_mux[] = {
SDA1_A_MARK, SCL1_A_MARK,
};
+
static const unsigned int i2c1_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
};
+
static const unsigned int i2c1_b_mux[] = {
SDA1_B_MARK, SCL1_B_MARK,
};
+
static const unsigned int i2c2_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
+
static const unsigned int i2c2_a_mux[] = {
SDA2_A_MARK, SCL2_A_MARK,
};
+
static const unsigned int i2c2_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
+
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
+
+static const unsigned int i2c3_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+
+static const unsigned int i2c3_mux[] = {
+ SCL3_MARK, SDA3_MARK,
+};
+
+static const unsigned int i2c5_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+};
+
+static const unsigned int i2c5_mux[] = {
+ SCL5_MARK, SDA5_MARK,
+};
+
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
+
static const unsigned int i2c6_a_mux[] = {
SDA6_A_MARK, SCL6_A_MARK,
};
+
static const unsigned int i2c6_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
+
static const unsigned int i2c6_b_mux[] = {
SDA6_B_MARK, SCL6_B_MARK,
};
+
static const unsigned int i2c6_c_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
+
static const unsigned int i2c6_c_mux[] = {
SDA6_C_MARK, SCL6_C_MARK,
};
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
+ SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
"hscif4_data_b",
};
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
"i2c2_b",
};
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
+ SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
- GP_7_0_FN, GPSR7_0, }
+ GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
- { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
IP16_15_12
IP16_11_8
IP16_7_4
- IP16_3_0 }
+ IP16_3_0 ))
},
- { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
IP17_15_12
IP17_11_8
IP17_7_4
- IP17_3_0 }
+ IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
+ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
- IP18_3_0 }
+ IP18_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
+ 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 2, 3, 1, 2, 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
+ 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
- MOD_SEL1_0 }
+ MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
- 4, 4, 4, 3, 1) {
+ GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
+ 1, 4, 4, 4, 3, 1),
+ GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
- MOD_SEL2_0 }
+ MOD_SEL2_0 ))
},
{ },
};
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
- PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
- PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
+ PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
- PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
- PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
+ PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
PINMUX_IPSR_GPSR(IP6_23_20, D12),
PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
- PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
};
static const unsigned int scif0_ctrl_mux[] = {
- RTS0_N_TANS_MARK, CTS0_N_MARK,
+ RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
};
static const unsigned int scif3_ctrl_mux[] = {
- RTS3_N_TANS_MARK, CTS3_N_MARK,
+ RTS3_N_MARK, CTS3_N_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
static const unsigned int scif4_ctrl_mux[] = {
- RTS4_N_TANS_MARK, CTS4_N_MARK,
+ RTS4_N_MARK, CTS4_N_MARK,
};
/* - TMU -------------------------------------------------------------------- */
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_15_12
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 4, 4, 4, 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
/* RESERVED 31, 30, 29, 28 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 27, 26, 25, 24 */
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1
- MOD_SEL0_0 }
+ MOD_SEL0_0 ))
},
{ },
};
enum ioctrl_regs {
- IOCTRL30,
- IOCTRL31,
- IOCTRL32,
+ POCCTRL0,
+ POCCTRL1,
+ POCCTRL2,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [IOCTRL30] = { 0xe6060380 },
- [IOCTRL31] = { 0xe6060384 },
- [IOCTRL32] = { 0xe6060388 },
+ [POCCTRL0] = { 0xe6060380 },
+ [POCCTRL1] = { 0xe6060384 },
+ [POCCTRL2] = { 0xe6060388 },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
return bit;
if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
return bit + 22;
- *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
return bit - 10;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
/*
* R8A77990 processor support - PFC hardware block.
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
#define GPSR5_7 F_(SCK2_A, IP12_7_4)
#define GPSR5_6 F_(TX1, IP12_3_0)
#define GPSR5_5 F_(RX1, IP11_31_28)
-#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
+#define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
#define GPSR5_2 F_(TX0_A, IP11_15_12)
#define GPSR5_1 F_(RX0_A, IP11_11_8)
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
-#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
-#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
-#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
#define PINMUX_MOD_SELS \
\
- MOD_SEL1_31 \
-MOD_SEL0_30_29 MOD_SEL1_30 \
+MOD_SEL0_30_29 \
MOD_SEL1_29 \
MOD_SEL0_28 MOD_SEL1_28 \
MOD_SEL0_27_26 \
PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
PINMUX_IPSR_GPSR(IP3_15_12, A4),
- PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
- PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
PINMUX_IPSR_GPSR(IP5_31_28, D2),
PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
- PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
- PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
- PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
- PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
- PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
- PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
+ PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
+ PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
- PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
+ PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
+ PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
- PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
- PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
- PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
+ PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
- PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
+ PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
- PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
- PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
- PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
- PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
- PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
+ PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
- PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
};
static const unsigned int scif0_ctrl_a_mux[] = {
- RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
+ RTS0_N_A_MARK, CTS0_N_A_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
};
static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
};
static const unsigned int scif3_ctrl_a_mux[] = {
- RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
+ RTS3_N_A_MARK, CTS3_N_A_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
};
static const unsigned int scif4_ctrl_a_mux[] = {
- RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
+ RTS4_N_A_MARK, CTS4_N_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
};
static const unsigned int scif4_ctrl_c_mux[] = {
- RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
+ RTS4_N_C_MARK, CTS4_N_C_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
};
static const struct {
- struct sh_pfc_pin_group common[245];
- struct sh_pfc_pin_group automotive[23];
+ struct sh_pfc_pin_group common[247];
+ struct sh_pfc_pin_group automotive[21];
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data),
+ SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_in_0),
SH_PFC_PIN_GROUP(vin5_clk_b),
},
.automotive = {
- SH_PFC_PIN_GROUP(canfd0_data),
- SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
};
static const struct {
- struct sh_pfc_function common[45];
- struct sh_pfc_function automotive[6];
+ struct sh_pfc_function common[47];
+ struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(vin5),
},
.automotive = {
- SH_PFC_FUNCTION(canfd0),
- SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_15_12
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
- 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
+ GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
+ 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
+ GROUP(
/* RESERVED 31 */
0, 0,
MOD_SEL0_30_29
MOD_SEL0_4
MOD_SEL0_3
MOD_SEL0_2
- MOD_SEL0_1_0 }
+ MOD_SEL0_1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
- 1, 2, 2, 2, 1, 1, 2, 1, 4) {
- MOD_SEL1_31
- MOD_SEL1_30
+ GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
+ 2, 2, 2, 1, 1, 2, 1, 4),
+ GROUP(
+ /* RESERVED 31, 30 */
+ 0, 0, 0, 0,
MOD_SEL1_29
MOD_SEL1_28
/* RESERVED 27 */
MOD_SEL1_6_5
MOD_SEL1_4
/* RESERVED 3, 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ },
};
enum ioctrl_regs {
- IOCTRL30,
+ POCCTRL0,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [IOCTRL30] = { 0xe6060380, },
+ [POCCTRL0] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
{
int bit = -EINVAL;
- *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
- [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */
+ [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */
#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
- PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
- PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
};
static const unsigned int scif0_ctrl_mux[] = {
- RTS0_N_TANS_MARK, CTS0_N_MARK,
+ RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
GP_1_31_FN, GPSR1_31,
GP_1_30_FN, GPSR1_30,
GP_1_29_FN, GPSR1_29,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
GP_2_31_FN, GPSR2_31,
GP_2_30_FN, GPSR2_30,
GP_2_29_FN, GPSR2_29,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
GP_4_31_FN, GPSR4_31,
GP_4_30_FN, GPSR4_30,
GP_4_29_FN, GPSR4_29,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_15_12
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
/* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
- 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
+ GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
+ 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* RESERVED 31 */
0, 0,
MOD_SEL0_30
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1
- MOD_SEL0_0 }
+ MOD_SEL0_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 1, 1, 1, 1, 1, 1, 2, 4, 4,
- 4, 4, 4, 4) {
+ GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
+ GROUP(
MOD_SEL1_31
MOD_SEL1_30
MOD_SEL1_29
/* RESERVED 7, 6, 5, 4 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ },
};
return bit;
}
+enum ioctrl_regs {
+ TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [TDSELCTRL] = { 0xe60603c0, },
+ { /* sentinel */ },
+};
+
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
};
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
const struct sh_pfc_pin *pin = NULL;
int i, ret, idx;
- for (i = 1; i < pfc->info->nr_pins; i++) {
+ for (i = 0; i < pfc->info->nr_pins; i++) {
if (priv->pfc.info->pins[i].pin != pin_selector)
continue;
const struct sh_pfc_pin *pin = NULL;
int i, idx;
- for (i = 1; i < pfc->info->nr_pins; i++) {
+ for (i = 0; i < pfc->info->nr_pins; i++) {
if (priv->pfc.info->pins[i].pin != pin_selector)
continue;
.name = #alias, \
.pins = n##_pins, \
.mux = n##_mux, \
- .nr_pins = ARRAY_SIZE(n##_pins), \
+ .nr_pins = ARRAY_SIZE(n##_pins) + \
+ BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
}
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
struct pinmux_cfg_reg {
u32 reg;
u8 reg_width, field_width;
+#ifdef DEBUG
+ u16 nr_enum_ids; /* for variable width regs only */
+#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
+#else
+#define SET_NR_ENUM_IDS(n)
+#endif
const u16 *enum_ids;
const u8 *var_field_width;
};
+#define GROUP(...) __VA_ARGS__
+
/*
* Describe a config register consisting of several fields of the same width
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - f_width: Width of the fixed-width register fields (in bits)
- * This macro must be followed by initialization data: For each register field
- * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
- * one for each possible combination of the register field bit values.
+ * - ids: For each register field (from left to right, i.e. MSB to LSB),
+ * 2^f_width enum IDs must be specified, one for each possible
+ * combination of the register field bit values, all wrapped using
+ * the GROUP() macro.
*/
-#define PINMUX_CFG_REG(name, r, r_width, f_width) \
- .reg = r, .reg_width = r_width, .field_width = f_width, \
- .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
+#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
+ .reg = r, .reg_width = r_width, \
+ .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
+ BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
+ (r_width / f_width) * (1 << f_width)), \
+ .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
+ { ids }
/*
* Describe a config register consisting of several fields of different widths
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
- * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
- * From left to right (i.e. MSB to LSB)
- * This macro must be followed by initialization data: For each register field
- * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
- * one for each possible combination of the register field bit values.
+ * - f_widths: List of widths of the register fields (in bits), from left
+ * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
+ * - ids: For each register field (from left to right, i.e. MSB to LSB),
+ * 2^f_widths[i] enum IDs must be specified, one for each possible
+ * combination of the register field bit values, all wrapped using
+ * the GROUP() macro.
*/
-#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
- .reg = r, .reg_width = r_width, \
- .var_field_width = (const u8 [r_width]) \
- { var_fw0, var_fwn, 0 }, \
- .enum_ids = (const u16 [])
+#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
+ .reg = r, .reg_width = r_width, \
+ .var_field_width = (const u8 []) { f_widths, 0 }, \
+ SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
+ .enum_ids = (const u16 []) { ids }
struct pinmux_drive_reg_field {
u16 pin;
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
- * This macro must be followed by initialization data: For each register bit
- * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
+ * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
+ * enum ID must be specified, all wrapped using the GROUP() macro.
*/
-#define PINMUX_DATA_REG(name, r, r_width) \
- .reg = r, .reg_width = r_width, \
- .enum_ids = (const u16 [r_width]) \
+#define PINMUX_DATA_REG(name, r, r_width, ids) \
+ .reg = r, .reg_width = r_width + \
+ BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
+ r_width), \
+ .enum_ids = (const u16 [r_width]) { ids }
struct pinmux_irq {
const short *gpios;
/*
* Describe a pinmux configuration in which a pin is physically multiplexed
* with other pins.
- * - ipsr: IPSR field
- * - fn: Function name, also referring to the IPSR field
+ * - ipsr: IPSR field (unused, for documentation purposes only)
+ * - fn: Function name
* - psel: Physical multiplexing selector
*/
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
*/
#define PORTCR(nr, reg) \
{ \
- PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
+ PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
+ GROUP(2, 2, 1, 3), \
+ GROUP( \
/* PULMD[1:0], handled by .set_bias() */ \
0, 0, 0, 0, \
/* IE and OE */ \
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 \
- } \
+ )) \
}
/*
#include "ipu.h"
#include "mxcfb.h"
#include "ipu_regs.h"
+#include "display.h"
+#include <panel.h>
#include <dm.h>
#include <video.h>
ret = mxcfb_probe(gpixfmt, gdisp, gmode);
debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs);
+ gd->fb_base = panel.frameAdrs;
return (void *)&panel;
}
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+#if defined(CONFIG_DISPLAY)
+ struct udevice *disp_dev;
+#endif
+ struct udevice *panel_dev;
u32 fb_start, fb_end;
int ret;
if (ret < 0)
return ret;
+#if defined(CONFIG_DISPLAY)
+ ret = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
+ if (disp_dev) {
+ ret = display_enable(disp_dev, 16, NULL);
+ if (ret < 0)
+ return ret;
+ }
+#endif
+ ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
+ if (panel_dev)
+ panel_enable_backlight(panel_dev);
+
uc_priv->xsize = gmode->xres;
uc_priv->ysize = gmode->yres;
uc_priv->bpix = LCD_MAX_LOG2_BPP;
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
DCACHE_WRITEBACK);
video_set_flush_dcache(dev, true);
+ gd->fb_base = fb_start;
return 0;
}
Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
that the watchdog will not be fed in u-boot.
-config BCM2835_WDT
- bool "Enable BCM2835/2836 watchdog driver"
- select HW_WATCHDOG
- help
- Say Y here to enable the BCM2835/2836 watchdog
-
- This provides basic infrastructure to support BCM2835/2836 watchdog
- hardware, with a max timeout of ~15secs.
-
config IMX_WATCHDOG
bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP"
select HW_WATCHDOG if !WDT
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
-obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Watchdog driver for Broadcom BCM2835
- *
- * Copyright (C) 2017 Paolo Pisati <p.pisati@gmail.com>
- */
-
-#include <common.h>
-#include <efi_loader.h>
-#include <asm/io.h>
-#include <asm/arch/wdog.h>
-
-#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
-#define MAX_TIMEOUT 0xf /* ~15s */
-
-static __efi_runtime_data bool enabled = true;
-
-extern void reset_cpu(ulong ticks);
-
-void hw_watchdog_reset(void)
-{
- if (enabled)
- reset_cpu(SECS_TO_WDOG_TICKS(MAX_TIMEOUT));
-}
-
-void hw_watchdog_init(void)
-{
- hw_watchdog_reset();
-}
-
-void __efi_runtime hw_watchdog_disable(void)
-{
- enabled = false;
-}
return 0;
}
-static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms)
+static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
{
struct mtk_wdt_priv *priv = dev_get_priv(dev);
+ u64 timeout_us;
+ u32 timeout_cc;
+ u32 length;
/*
* One WDT_LENGTH count is 512 ticks of the wdt clock
* The MediaTek docs lack details to know if this is the case here.
* So we enforce a minimum of 1 to guarantee operation.
*/
- if(timeout_ms > 15984) timeout_ms = 15984;
- u64 timeout_us = timeout_ms * 1000;
- u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 );
- if(timeout_cc == 0) timeout_cc = 1;
- u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
+ if (timeout_ms > 15984)
+ timeout_ms = 15984;
+
+ timeout_us = timeout_ms * 1000;
+ timeout_cc = (15624 + timeout_us) / 15625;
+ if (timeout_cc == 0)
+ timeout_cc = 1;
+
+ length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
writel(length, priv->base + MTK_WDT_LENGTH);
}
-static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
struct mtk_wdt_priv *priv = dev_get_priv(dev);
- mtk_wdt_set_timeout(dev, timeout);
+ mtk_wdt_set_timeout(dev, timeout_ms);
- mtk_wdt_reset(dev);
+ mtk_wdt_reset(dev);
/* Enable watchdog reset signal */
setbits_le32(priv->base + MTK_WDT_MODE,
#define Altera_EP2C35_SIZE 883905
#define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */
+#define ALTERA_EP4CE6_SIZE 368011 /* 2944088 Bits */
+#define ALTERA_EP4CE10_SIZE 368011 /* 2944088 Bits */
+#define ALTERA_EP4CE15_SIZE 510856 /* 4086848 Bits */
+#define ALTERA_EP4CE22_SIZE 718569 /* 5748552 Bits */
+#define ALTERA_EP4CE30_SIZE 1191788 /* 9534304 Bits */
+#define ALTERA_EP4CE40_SIZE 1191788 /* 9534304 Bits */
+#define ALTERA_EP4CE55_SIZE 1861195 /* 14889560 Bits */
+#define ALTERA_EP4CE75_SIZE 2495719 /* 19965752 Bits */
+#define ALTERA_EP4CE115_SIZE 3571462 /* 28571696 Bits */
+
/* Descriptor Macros
*********************************************************************/
/* ACEX1K devices */
-/* SPDX-License-Identifier: BSD-2-Clause */
+/* SPDX-License-Identifier: BSD-3-Clause */
/*
* This is from the Android Project,
- * Repository: https://android.googlesource.com/platform/system/core/
- * File: mkbootimg/bootimg.h
- * Commit: d162828814b08ada310846a33205befb69ef5799
+ * Repository: https://android.googlesource.com/platform/system/tools/mkbootimg
+ * File: include/bootimg/bootimg.h
+ * Commit: e55998a0f2b61b685d5eb4a486ca3a0c680b1a2f
*
- * Copyright (C) 2008 The Android Open Source Project
+ * Copyright (C) 2007 The Android Open Source Project
*/
#ifndef _ANDROID_IMAGE_H_
#define _ANDROID_IMAGE_H_
-typedef struct andr_img_hdr andr_img_hdr;
-
#define ANDR_BOOT_MAGIC "ANDROID!"
#define ANDR_BOOT_MAGIC_SIZE 8
#define ANDR_BOOT_NAME_SIZE 16
#define ANDR_BOOT_ARGS_SIZE 512
#define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
+/*
+ * It is expected that callers would explicitly specify which version of the
+ * boot image header they need to use.
+ */
+typedef struct andr_img_hdr andr_img_hdr;
+
+/* The bootloader expects the structure of andr_img_hdr with header
+ * version 0 to be as follows: */
struct andr_img_hdr {
- char magic[ANDR_BOOT_MAGIC_SIZE];
+ /* Must be ANDR_BOOT_MAGIC. */
+ char magic[ANDR_BOOT_MAGIC_SIZE];
- u32 kernel_size; /* size in bytes */
- u32 kernel_addr; /* physical load addr */
+ u32 kernel_size; /* size in bytes */
+ u32 kernel_addr; /* physical load addr */
- u32 ramdisk_size; /* size in bytes */
- u32 ramdisk_addr; /* physical load addr */
+ u32 ramdisk_size; /* size in bytes */
+ u32 ramdisk_addr; /* physical load addr */
- u32 second_size; /* size in bytes */
- u32 second_addr; /* physical load addr */
+ u32 second_size; /* size in bytes */
+ u32 second_addr; /* physical load addr */
- u32 tags_addr; /* physical addr for kernel tags */
- u32 page_size; /* flash page size we assume */
- u32 unused; /* reserved for future expansion: MUST be 0 */
+ u32 tags_addr; /* physical addr for kernel tags */
+ u32 page_size; /* flash page size we assume */
- /* operating system version and security patch level; for
- * version "A.B.C" and patch level "Y-M-D":
- * ver = A << 14 | B << 7 | C (7 bits for each of A, B, C)
- * lvl = ((Y - 2000) & 127) << 4 | M (7 bits for Y, 4 bits for M)
- * os_version = ver << 11 | lvl */
- u32 os_version;
+ /* Version of the boot image header. */
+ u32 header_version;
- char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
+ /* Operating system version and security patch level.
+ * For version "A.B.C" and patch level "Y-M-D":
+ * (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M)
+ * os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0] */
+ u32 os_version;
- char cmdline[ANDR_BOOT_ARGS_SIZE];
+ char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
- u32 id[8]; /* timestamp / checksum / sha1 / etc */
+ char cmdline[ANDR_BOOT_ARGS_SIZE];
- /* Supplemental command line data; kept here to maintain
- * binary compatibility with older versions of mkbootimg */
- char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE];
+ u32 id[8]; /* timestamp / checksum / sha1 / etc */
+
+ /* Supplemental command line data; kept here to maintain
+ * binary compatibility with older versions of mkbootimg. */
+ char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE];
+
+ /* Fields in boot_img_hdr_v1 and newer. */
+ u32 recovery_dtbo_size; /* size in bytes for recovery DTBO/ACPIO image */
+ u64 recovery_dtbo_offset; /* offset to recovery dtbo/acpio in boot image */
+ u32 header_size;
+
+ /* Fields in boot_img_hdr_v2 and newer. */
+ u32 dtb_size; /* size in bytes for DTB image */
+ u64 dtb_addr; /* physical load address for DTB image */
} __attribute__((packed));
-/*
+/* When a boot header is of version 0, the structure of boot image is as
+ * follows:
+ *
* +-----------------+
* | boot header | 1 page
* +-----------------+
* 6. if second_size != 0: jump to second_addr
* else: jump to kernel_addr
*/
+
+/* When the boot image header has a version of 2, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header | 1 page
+ * +---------------------+
+ * | kernel | n pages
+ * +---------------------+
+ * | ramdisk | m pages
+ * +---------------------+
+ * | second stage | o pages
+ * +---------------------+
+ * | recovery dtbo/acpio | p pages
+ * +---------------------+
+ * | dtb | q pages
+ * +---------------------+
+
+ * n = (kernel_size + page_size - 1) / page_size
+ * m = (ramdisk_size + page_size - 1) / page_size
+ * o = (second_size + page_size - 1) / page_size
+ * p = (recovery_dtbo_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ *
+ * 0. all entities are page_size aligned in flash
+ * 1. kernel, ramdisk and DTB are required (size != 0)
+ * 2. recovery_dtbo/recovery_acpio is required for recovery.img in non-A/B
+ * devices(recovery_dtbo_size != 0)
+ * 3. second is optional (second_size == 0 -> no second)
+ * 4. load each element (kernel, ramdisk, second, dtb) at
+ * the specified physical address (kernel_addr, etc)
+ * 5. If booting to recovery mode in a non-A/B device, extract recovery
+ * dtbo/acpio and apply the correct set of overlays on the base device tree
+ * depending on the hardware/product revision.
+ * 6. prepare tags at tag_addr. kernel_args[] is
+ * appended to the kernel commandline in the tags.
+ * 7. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr
+ * 8. if second_size != 0: jump to second_addr
+ * else: jump to kernel_addr
+ */
+
#endif
/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
unsigned long pci_clk;
unsigned long mem_clk;
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
unsigned long fb_base; /* Base address of framebuffer mem */
#endif
#if defined(CONFIG_POST)
* autoboot_command() - run the autoboot command
*
* If enabled, run the autoboot command returned from bootdelay_process().
- * Also do the CONFIG_MENUKEY processing if enabled.
+ * Also do the CONFIG_AUTOBOOT_MENUKEY processing if enabled.
*
* @cmd: Command to run
*/
* @return zero on success, or -ENOENT on error
*/
int clk_get_by_id(ulong id, struct clk **clkp);
+
+/**
+ * clk_dev_binded() - Check whether the clk has a device binded
+ *
+ * @clk A pointer to the clk
+ *
+ * @return true on binded, or false on no
+ */
+bool clk_dev_binded(struct clk *clk);
#endif
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=mpc8349emds\0" \
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=mpc8349emds\0" \
#define CONFIG_CPU_SH7722 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
#define CONFIG_SMC91111
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 400000
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=tqm834x\0" \
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 1
-
-#define CONFIG_SHOW_BOOT_PROGRESS
#endif /* ! __CONFIG_AM335X_SHC_H */
*/
#ifdef CONFIG_USB_AM35X
-
-#ifdef CONFIG_USB_MUSB_HCD
-
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_USB_MUSB_HCD */
-
#ifdef CONFIG_USB_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
-#ifdef CONFIG_USB_MUSB_AM35X
-
-#ifdef CONFIG_USB_MUSB_HOST
-
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_USB_MUSB_HOST */
-
-#endif /* CONFIG_USB_MUSB_AM35X */
-
/* I2C */
/* Ethernet */
#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-#define CONFIG_PREBOOT "run check_flash check_env;"
/*
* Boot Linux
#define BOARD_LATE_INIT
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
-#define CONFIG_PREBOOT
-
#define CONFIG_S5P_PA_SYSRAM 0x02020000
#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
/*
* Save the prior stage provided DTB.
*/
-#define CONFIG_PREBOOT \
- "fdt addr ${fdtcontroladdr};" \
- "fdt move ${fdtcontroladdr} ${fdtsaveaddr};" \
- "fdt addr ${fdtsaveaddr};"
/*
* Enable in-place RFS with this initrd_high setting.
*/
"run manage_userdata; "
/* Enable PREBOOT variable */
-#define CONFIG_PREBOOT
/* Set ARP_TIMEOUT to 500ms */
#define CONFIG_ARP_TIMEOUT 500UL
"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \
"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
-#define CONFIG_PREBOOT "run cfgscr; run brdefaultip"
-
/* Network defines */
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
"echo WARNING: Could not determine dtb to use; fi; \0" \
BOOTENV
-#define CONFIG_PREBOOT "usb start;sf probe"
-
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 2) \
"upd_uboot=tftp 100000 conga/u-boot.rom;" \
"sf probe;sf update 100000 0 800000;saveenv\0"
-#define CONFIG_PREBOOT
-
#endif /* __CONFIG_H */
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "ccdc.img"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth1\0" \
"consoledev=ttyS1\0" \
"upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \
"sf probe;sf update 100000 0 800000;saveenv\0"
-#define CONFIG_PREBOOT
-
#endif /* __CONFIG_H */
/* Default Environment */
#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
#define CONFIG_LOADADDR 0x80000
-#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
-#define CONFIG_PREBOOT "usb start; sf probe"
#endif /* _CONFIG_SYNOLOGY_DS414_H */
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
/* Miscellaneous configurable options */
#define CONFIG_HWCONFIG
-#define CONFIG_PREBOOT
/* Memory configuration */
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_LOADS_ECHO
#define CONFIG_TIMESTAMP
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run nfsboot\\\" " \
- "to mount root filesystem over NFS;echo"
#define CONFIG_BOOTCOMMAND "run boot_cramfs"
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
/* MEMORY */
#define KZM_SDRAM_BASE (0x40000000)
#define PHYS_SDRAM KZM_SDRAM_BASE
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_KIRKWOOD_GPIO
/*
* Extra Environments
*/
-#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_HOSTNAME "m53menlo"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_PREBOOT /* enable preboot variable */
-
/*
* Hardware drivers
*/
#ifdef CONFIG_USB_KEYBOARD
#define STDIN_CFG "usbkbd,serial"
-#define CONFIG_PREBOOT "usb start"
#else
#define STDIN_CFG "serial"
#endif
/* architecture dependent code */
#define CONFIG_SYS_USR_EXCEP /* user exception */
-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
-
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
"nor0=flash-0\0"\
#endif
/* auto boot */
-#define CONFIG_PREBOOT
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_PREBOOT
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_PREBOOT
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
/* Framebuffer and LCD */
-#define CONFIG_PREBOOT
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
/* Framebuffer and LCD */
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_PREBOOT
#endif /* __CONFIG_H */
#endif
/* Framebuffer and LCD */
-#define CONFIG_PREBOOT
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_PREBOOT \
- "if hdmidet; then " \
- "usb start; " \
- "setenv stdin serial,usbkbd; "\
- "setenv stdout serial,vga; " \
- "setenv stderr serial,vga; " \
- "else " \
- "setenv stdin serial; " \
- "setenv stdout serial; " \
- "setenv stderr serial; " \
- "fi;"
/* Command definition */
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_PREBOOT ""
-
#ifdef CONFIG_CMD_MMC
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
"bootmenu_delay=30\0" \
""
-#define CONFIG_PREBOOT \
- "setenv mmcnum 1; setenv mmcpart 1;" \
- "setenv mmcscriptfile bootmenu.scr;" \
- "if run switchmmc; then " \
- "setenv mmcdone true;" \
- "setenv mmctype fat;" \
- "if run scriptload; then true; else " \
- "setenv mmctype ext2;" \
- "if run scriptload; then true; else " \
- "setenv mmctype ext4;" \
- "if run scriptload; then true; else " \
- "setenv mmcdone false;" \
- "fi;" \
- "fi;" \
- "fi;" \
- "if ${mmcdone}; then " \
- "run scriptboot;" \
- "fi;" \
- "fi;" \
- "if run slide; then true; else " \
- "setenv bootmenu_delay 0;" \
- "setenv bootdelay 0;" \
- "fi"
-
#define CONFIG_POSTBOOTMENU \
"echo;" \
"echo Extra commands:;" \
"run attachboot;" \
"echo"
-#define CONFIG_MENU_SHOW
-
/*
* Miscellaneous configurable options
*/
/* TWL4030 LED Support */
-#define CONFIG_PREBOOT "usb start"
-
#define MEM_LAYOUT_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
/* Environment information */
-#define CONFIG_PREBOOT \
- "setenv preboot;" \
- "saveenv;"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
#define ACFG_CONSOLE_DEV ttymxc0
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
-#define CONFIG_PREBOOT "run check_env"
#define CONFIG_BOOTCOMMAND "run emmcboot"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#endif
-#define CONFIG_PREBOOT ""
-
/* Thermal support */
#define CONFIG_IMX_THERMAL
#define CONFIG_BOOTCOMMAND "run bootubi_scr"
/* Miscellaneous configurable options */
-#define CONFIG_PREBOOT
/* MTD/UBI/UBIFS config */
#include <config_distro_bootcmd.h>
-#define CONFIG_PREBOOT "pci enum"
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"ramdisk_addr_r=0x88300000\0" \
BOOTENV
-#define CONFIG_PREBOOT \
- "setenv fdt_addr ${fdtcontroladdr};" \
- "fdt addr ${fdtcontroladdr};"
-
#endif /* __CONFIG_H */
#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec"
#endif
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
#define CONFIG_ARCH_CPU_INIT
#ifndef CONFIG_PINCTRL_PFC
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
#define CONFIG_ARCH_CPU_INIT
/* Generic Interrupt Controller Definitions */
BOOTENV
#endif
-#define CONFIG_PREBOOT
-
#endif
#endif /* CONFIG_SPL_BUILD */
-#define CONFIG_PREBOOT
-
#endif
BOOTENV
#endif
-#define CONFIG_PREBOOT
-
#endif
BOOTENV
#endif
-#define CONFIG_PREBOOT
-
#endif
/* Environment */
#define CONFIG_ENV_SIZE SZ_16K
#define CONFIG_SYS_LOAD_ADDR 0x1000000
-#define CONFIG_PREBOOT "usb start"
/* Shell */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
-#ifdef CONFIG_PCIE1
-#endif
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CPU_SH7752 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7752EVB_SDRAM_BASE (0x40000000)
#define CONFIG_CPU_SH7753 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7753EVB_SDRAM_BASE (0x40000000)
#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7757LCR_SDRAM_BASE (0x80000000)
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
#define CONFIG_CONS_SCIF2 1
/* UBI Support */
/* Commen environment */
-#define CONFIG_PREBOOT
#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \
"setenv bootargs ${bootargs};" \
"mtdparts default;" \
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
* if button B is not pressed, boot normal Linux system immediatelly
* if button B is pressed, wait $bootdelay and boot recovery system
*/
-#define CONFIG_PREBOOT \
- "setenv hostname vining-${unit_serial} ; " \
- "setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \
- "if gpio input 78 ; then " \
- "setenv bootdelay 10 ; " \
- "setenv boottype rcvr ; " \
- "else " \
- "setenv bootdelay 5 ; " \
- "setenv boottype norm ; " \
- "fi"
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome on the ABB Socrates Board;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT
-#endif
-
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_ARM64
#ifdef CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USBD_HS
#endif /* CONFIG_CMD_USB_MASS_STORAGE */
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT \
- "usb start; " \
- "if hdmidet; then " \
- "run set_con_hdmi; " \
- "else " \
- "run set_con_serial; " \
- "fi"
-#endif /* CONFIG_USB_KEYBOARD */
#endif /* CONFIG_CMD_USB */
/* Environment organization */
#ifdef CONFIG_USB_KEYBOARD
#define STDIN_KBD_USB ",usbkbd"
-#define CONFIG_PREBOOT "usb start"
#else
#define STDIN_KBD_USB ""
#endif
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_PREBOOT
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_PREBOOT
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
# define EXTRA_ENV_USB
#endif
-#undef CONFIG_PREBOOT
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_image=uImage\0" \
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_PREBOOT
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
#define CONFIG_PL011_CLOCK 24000000
#endif
-/*#define CONFIG_MENU_SHOW*/
-
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_PHYSMEM
#define CONFIG_LMB
#if defined(CONFIG_ZYNQMP_USB)
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_USB_CABLE_CHECK
#define CONFIG_THOR_RESET_OFF
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
/*==============================*/
#define CONFIG_MX_CYCLIC
-#define CONFIG_SHOW_BOOT_PROGRESS
/*=========================================*/
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
-#define CONFIG_PREBOOT ""
-
/*
* Size of malloc() pool
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
-# define CONFIG_USB_CABLE_CHECK
# define CONFIG_THOR_RESET_OFF
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
#define CONFIG_ENV_OVERWRITE
/* enable preboot to be loaded before CONFIG_BOOTDELAY */
-#define CONFIG_PREBOOT
/* Boot configuration */
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
#define CLKID_AO_SAR_ADC_SEL 8
#define CLKID_AO_SAR_ADC_DIV 9
#define CLKID_AO_SAR_ADC_CLK 10
-#define CLKID_AO_ALT_XTAL 11
+#define CLKID_AO_CTS_OSCIN 11
+#define CLKID_AO_32K_PRE 12
+#define CLKID_AO_32K_DIV 13
+#define CLKID_AO_32K_SEL 14
+#define CLKID_AO_32K 15
+#define CLKID_AO_CTS_RTC_OSCIN 16
#endif
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
#define __AXG_AUDIO_CLKC_BINDINGS_H
-#define AUD_CLKID_SLV_SCLK0 9
-#define AUD_CLKID_SLV_SCLK1 10
-#define AUD_CLKID_SLV_SCLK2 11
-#define AUD_CLKID_SLV_SCLK3 12
-#define AUD_CLKID_SLV_SCLK4 13
-#define AUD_CLKID_SLV_SCLK5 14
-#define AUD_CLKID_SLV_SCLK6 15
-#define AUD_CLKID_SLV_SCLK7 16
-#define AUD_CLKID_SLV_SCLK8 17
-#define AUD_CLKID_SLV_SCLK9 18
-#define AUD_CLKID_SLV_LRCLK0 19
-#define AUD_CLKID_SLV_LRCLK1 20
-#define AUD_CLKID_SLV_LRCLK2 21
-#define AUD_CLKID_SLV_LRCLK3 22
-#define AUD_CLKID_SLV_LRCLK4 23
-#define AUD_CLKID_SLV_LRCLK5 24
-#define AUD_CLKID_SLV_LRCLK6 25
-#define AUD_CLKID_SLV_LRCLK7 26
-#define AUD_CLKID_SLV_LRCLK8 27
-#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_DDR_ARB 29
#define AUD_CLKID_PDM 30
#define AUD_CLKID_TDMIN_A 31
#define AUD_CLKID_TDMOUT_A_LRCLK 134
#define AUD_CLKID_TDMOUT_B_LRCLK 135
#define AUD_CLKID_TDMOUT_C_LRCLK 136
+#define AUD_CLKID_SPDIFOUT_B 151
+#define AUD_CLKID_SPDIFOUT_B_CLK 152
+#define AUD_CLKID_TDM_MCLK_PAD0 155
+#define AUD_CLKID_TDM_MCLK_PAD1 156
+#define AUD_CLKID_TDM_LRCLK_PAD0 157
+#define AUD_CLKID_TDM_LRCLK_PAD1 158
+#define AUD_CLKID_TDM_LRCLK_PAD2 159
+#define AUD_CLKID_TDM_SCLK_PAD0 160
+#define AUD_CLKID_TDM_SCLK_PAD1 161
+#define AUD_CLKID_TDM_SCLK_PAD2 162
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174
#define CLKID_MALI 175
-#define CLKID_MPLL_5OM 177
+#define CLKID_MPLL_50M 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
+#define CLKID_TS 212
#endif /* __G12A_CLKC_H */
#define R8A77965_PD_A3VC 14
#define R8A77965_PD_3DG_A 17
#define R8A77965_PD_3DG_B 18
-#define R8A77965_PD_A3IR 24
#define R8A77965_PD_A2VC1 26
/* Always-on power area */
#define R8A77970_PD_CA53_CPU0 5
#define R8A77970_PD_CA53_CPU1 6
-#define R8A77970_PD_CR7 13
#define R8A77970_PD_CA53_SCU 21
#define R8A77970_PD_A2IR0 23
-#define R8A77970_PD_A3IR 24
+#define R8A77970_PD_A3IR 24
#define R8A77970_PD_A2IR1 27
-#define R8A77970_PD_A2IR2 28
-#define R8A77970_PD_A2IR3 29
+#define R8A77970_PD_A2DP 28
+#define R8A77970_PD_A2CN 29
#define R8A77970_PD_A2SC0 30
#define R8A77970_PD_A2SC1 31
#define ETHSYS_MCM_RST 2
#define ETHSYS_SYS_RST 0
+/* HIFSYS resets */
+#define HIFSYS_PCIE2_RST 26
+#define HIFSYS_PCIE1_RST 25
+#define HIFSYS_PCIE0_RST 24
+#define HIFSYS_UPHY1_RST 22
+#define HIFSYS_UPHY0_RST 21
+#define HIFSYS_UHOST1_RST 4
+#define HIFSYS_UHOST0_RST 3
+
#endif /* _DT_BINDINGS_MTK_RESET_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_MESON_G12A_TOHDMITX_H
+#define __DT_MESON_G12A_TOHDMITX_H
+
+#define TOHDMITX_I2S_IN_A 0
+#define TOHDMITX_I2S_IN_B 1
+#define TOHDMITX_I2S_IN_C 2
+#define TOHDMITX_I2S_OUT 3
+#define TOHDMITX_SPDIF_IN_A 4
+#define TOHDMITX_SPDIF_IN_B 5
+#define TOHDMITX_SPDIF_OUT 6
+
+#endif /* __DT_MESON_G12A_TOHDMITX_H */
efi_status_t (EFIAPI *set_wakeup_time)(char enabled,
struct efi_time *time);
efi_status_t (EFIAPI *set_virtual_address_map)(
- unsigned long memory_map_size,
- unsigned long descriptor_size,
+ efi_uintn_t memory_map_size,
+ efi_uintn_t descriptor_size,
uint32_t descriptor_version,
struct efi_mem_desc *virtmap);
efi_status_t (EFIAPI *convert_pointer)(
#define AB_SELECT ""
#endif
+#define FASTBOOT_CMD \
+ "echo Booting into fastboot ...; " \
+ "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; "
+
#define DEFAULT_COMMON_BOOT_TI_ARGS \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
"setenv mmcroot /dev/mmcblk0p2 rw; " \
"run mmcboot;\0" \
"emmc_android_boot=" \
+ "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \
+ CONTROL_PARTITION "; then " \
+ "if bcb test command = bootonce-bootloader; then " \
+ "echo BCB: Bootloader boot...; " \
+ "bcb clear command; bcb store; " \
+ FASTBOOT_CMD \
+ "elif bcb test command = boot-recovery; then " \
+ "echo BCB: Recovery boot...; " \
+ "echo Warning: recovery is not implemented; " \
+ "echo Performing normal boot for now...; " \
+ "bcb clear command; bcb store; " \
+ "run emmc_android_normal_boot; " \
+ "else " \
+ "echo BCB: Normal boot requested...; " \
+ "run emmc_android_normal_boot; " \
+ "fi; " \
+ "else " \
+ "echo Warning: BCB is corrupted or does not exist; " \
+ "echo Performing normal boot...; " \
+ "run emmc_android_normal_boot; " \
+ "fi;\0" \
+ "emmc_android_normal_boot=" \
"echo Trying to boot Android from eMMC ...; " \
"run update_to_fit; " \
"setenv eval_bootargs setenv bootargs $bootargs; " \
"if test ${dofastboot} -eq 1; then " \
"echo Boot fastboot requested, resetting dofastboot ...;" \
"setenv dofastboot 0; saveenv;" \
- "echo Booting into fastboot ...; " \
- "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \
+ FASTBOOT_CMD \
"fi;" \
"if test ${boot_fit} -eq 1; then " \
"run update_to_fit;" \
/* fpga_xxxx function return value definitions */
#define FPGA_SUCCESS 0
-#define FPGA_FAIL -1
+#define FPGA_FAIL 1
/* device numbers must be non-negative */
#define FPGA_INVALID_DEVICE -1
*/
#ifndef __LINUX_CLK_PROVIDER_H
#define __LINUX_CLK_PROVIDER_H
+#include <clk-uclass.h>
static inline void clk_dm(ulong id, struct clk *clk)
{
};
#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+extern const struct clk_ops clk_mux_ops;
+u8 clk_mux_get_parent(struct clk *clk);
+
+struct clk_gate {
+ struct clk clk;
+ void __iomem *reg;
+ u8 bit_idx;
+ u8 flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ u32 io_gate_val;
+#endif
+};
+
+#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
+
+#define CLK_GATE_SET_TO_DISABLE BIT(0)
+#define CLK_GATE_HIWORD_MASK BIT(1)
+
+extern const struct clk_ops clk_gate_ops;
+struct clk *clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock);
struct clk_div_table {
unsigned int val;
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+extern const struct clk_ops clk_divider_ops;
+unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table,
+ unsigned long flags, unsigned long width);
struct clk_fixed_factor {
struct clk clk;
#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
clk)
+struct clk_fixed_rate {
+ struct clk clk;
+ unsigned long fixed_rate;
+};
+
+#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+
+struct clk_composite {
+ struct clk clk;
+ struct clk_ops ops;
+
+ struct clk *mux;
+ struct clk *rate;
+ struct clk *gate;
+
+ const struct clk_ops *mux_ops;
+ const struct clk_ops *rate_ops;
+ const struct clk_ops *gate_ops;
+};
+
+#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char * const *parent_names, int num_parents,
+ struct clk *mux_clk, const struct clk_ops *mux_ops,
+ struct clk *rate_clk, const struct clk_ops *rate_ops,
+ struct clk *gate_clk, const struct clk_ops *gate_ops,
+ unsigned long flags);
+
int clk_register(struct clk *clk, const char *drv_name, const char *name,
const char *parent_name);
*/
void __assert_fail(const char *assertion, const char *file, unsigned int line,
const char *function);
+
+/**
+ * assert() - assert expression is true
+ *
+ * If the expression x evaluates to false and _DEBUG evaluates to true, a panic
+ * message is written and the system stalls. The value of _DEBUG is set to true
+ * if DEBUG is defined before including common.h.
+ *
+ * The expression x is always executed irrespective of the value of _DEBUG.
+ *
+ * @x: expression to test
+ */
#define assert(x) \
({ if (!(x) && _DEBUG) \
__assert_fail(#x, __FILE__, __LINE__, __func__); })
void menu_display_statusline(struct menu *m);
int menu_default_choice(struct menu *m, void **choice);
-#if defined(CONFIG_MENU_SHOW)
+/**
+ * menu_show() Show a boot menu
+ *
+ * This shows a menu and lets the user select an option. The menu is defined by
+ * environment variables (see README.bootmenu).
+ *
+ * This function doesn't normally return, but if the users requests the command
+ * problem, it will.
+ *
+ * @bootdelay: Delay to wait before running the default menu option (0 to run
+ * the entry immediately)
+ * @return If it returns, it always returns -1 to indicate that the boot should
+ * be aborted and the command prompt should be provided
+ */
int menu_show(int bootdelay);
-#endif
+
#endif /* __MENU_H__ */
SANDBOX_CLK_ECSPI1,
SANDBOX_CLK_USDHC1_SEL,
SANDBOX_CLK_USDHC2_SEL,
+ SANDBOX_CLK_I2C,
};
enum sandbox_pllv3_type {
#include <xilinx.h>
/*
- * Slave SelectMap Implementation function table.
+ * Slave SelectMap or Serial Implementation function table.
*/
typedef struct {
xilinx_pre_fn pre;
xilinx_wr_fn wr;
xilinx_rdata_fn rdata;
xilinx_wdata_fn wdata;
+ xilinx_bwr_fn wbulkdata;
xilinx_busy_fn busy;
xilinx_abort_fn abort;
xilinx_post_fn post;
-} xilinx_virtex2_slave_selectmap_fns;
-
-/* Slave Serial Implementation function table */
-typedef struct {
- xilinx_pgm_fn pgm;
- xilinx_clk_fn clk;
- xilinx_rdata_fn rdata;
- xilinx_wdata_fn wdata;
-} xilinx_virtex2_slave_serial_fns;
+} xilinx_virtex2_slave_fns;
#if defined(CONFIG_FPGA_VIRTEX2)
extern struct xilinx_fpga_op virtex2_op;
default y
depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || SYSRESET_X86
+config EFI_GRUB_ARM32_WORKAROUND
+ bool "Workaround for GRUB on 32bit ARM"
+ default y
+ depends on ARM && !ARM64
+ help
+ GRUB prior to version 2.04 requires U-Boot to disable caches. This
+ workaround currently is also needed on systems with caches that
+ cannot be managed via CP15.
endif
/* Handle of the currently executing image */
static efi_handle_t current_image;
-/*
- * If we're running on nasty systems (32bit ARM booting into non-EFI Linux)
- * we need to do trickery with caches. Since we don't want to break the EFI
- * aware boot path, only apply hacks when loading exiting directly (breaking
- * direct Linux EFI booting along the way - oh well).
- */
-static bool efi_is_direct_boot = true;
-
#ifdef CONFIG_ARM
/*
* The "gd" pointer lives in a register on ARM and AArch64 that we declare
*/
static void efi_exit_caches(void)
{
-#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+#if defined(CONFIG_EFI_GRUB_ARM32_WORKAROUND)
/*
- * Grub on 32bit ARM needs to have caches disabled before jumping into
- * a zImage, but does not know of all cache layers. Give it a hand.
+ * Boooting Linux via GRUB prior to version 2.04 fails on 32bit ARM if
+ * caches are enabled.
+ *
+ * TODO:
+ * According to the UEFI spec caches that can be managed via CP15
+ * operations should be enabled. Caches requiring platform information
+ * to manage should be disabled. This should not happen in
+ * ExitBootServices() but before invoking any UEFI binary is invoked.
+ *
+ * We want to keep the current workaround while GRUB prior to version
+ * 2.04 is still in use.
*/
- if (efi_is_direct_boot)
- cleanup_before_linux();
+ cleanup_before_linux();
#endif
}
if (ret != EFI_SUCCESS)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- efi_is_direct_boot = false;
-
image_obj->exit_data_size = exit_data_size;
image_obj->exit_data = exit_data;
long addend;
};
+static __efi_runtime_data struct efi_mem_desc *efi_virtmap;
+static __efi_runtime_data efi_uintn_t efi_descriptor_count;
+static __efi_runtime_data efi_uintn_t efi_descriptor_size;
+
/*
* EFI runtime code lives in two stages. In the first stage, U-Boot and an EFI
* payload are running concurrently at the same time. In this mode, we can
efi_status_t efi_init_runtime_supported(void)
{
- u16 efi_runtime_services_supported = 0;
+ u16 efi_runtime_services_supported =
+ EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP |
+ EFI_RT_SUPPORTED_CONVERT_POINTER;
/*
* This value must be synced with efi_runtime_detach_list
#ifdef CONFIG_EFI_HAVE_RUNTIME_RESET
efi_runtime_services_supported |= EFI_RT_SUPPORTED_RESET_SYSTEM;
#endif
- efi_runtime_services_supported |=
- EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP;
+
return EFI_CALL(efi_set_variable(L"RuntimeServicesSupported",
&efi_global_variable_guid,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
* Return: status code EFI_UNSUPPORTED
*/
static __efi_runtime efi_status_t EFIAPI efi_set_virtual_address_map_runtime(
- unsigned long memory_map_size,
- unsigned long descriptor_size,
+ efi_uintn_t memory_map_size,
+ efi_uintn_t descriptor_size,
uint32_t descriptor_version,
struct efi_mem_desc *virtmap)
{
return EFI_UNSUPPORTED;
}
+/**
+ * efi_convert_pointer_runtime() - convert from physical to virtual pointer
+ *
+ * This function implements the ConvertPointer() runtime service until
+ * the first call to SetVirtualAddressMap().
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @debug_disposition: indicates if pointer may be converted to NULL
+ * @address: pointer to be converted
+ * Return: status code EFI_UNSUPPORTED
+ */
+static __efi_runtime efi_status_t EFIAPI efi_convert_pointer(
+ efi_uintn_t debug_disposition, void **address)
+{
+ efi_physical_addr_t addr = (uintptr_t)*address;
+ efi_uintn_t i;
+ efi_status_t ret = EFI_NOT_FOUND;
+
+ EFI_ENTRY("%zu %p", debug_disposition, address);
+
+ if (!efi_virtmap) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ if (!address) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ for (i = 0; i < efi_descriptor_count; i++) {
+ struct efi_mem_desc *map = (void *)efi_virtmap +
+ (efi_descriptor_size * i);
+
+ if (addr >= map->physical_start &&
+ (addr < map->physical_start
+ + (map->num_pages << EFI_PAGE_SHIFT))) {
+ *address = (void *)(uintptr_t)
+ (addr + map->virtual_start -
+ map->physical_start);
+
+ ret = EFI_SUCCESS;
+ break;
+ }
+ }
+
+out:
+ return EFI_EXIT(ret);
+}
+
static __efi_runtime void efi_relocate_runtime_table(ulong offset)
{
ulong patchoff;
*/
efi_runtime_services.convert_pointer = &efi_convert_pointer_runtime;
+ /*
+ * TODO: Update UEFI variable RuntimeServicesSupported removing flags
+ * EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP and
+ * EFI_RT_SUPPORTED_CONVERT_POINTER as required by the UEFI spec 2.8.
+ */
+
/* Update CRC32 */
efi_update_table_header_crc32(&efi_runtime_services.hdr);
}
* Return: status code
*/
static efi_status_t EFIAPI efi_set_virtual_address_map(
- unsigned long memory_map_size,
- unsigned long descriptor_size,
+ efi_uintn_t memory_map_size,
+ efi_uintn_t descriptor_size,
uint32_t descriptor_version,
struct efi_mem_desc *virtmap)
{
- int n = memory_map_size / descriptor_size;
- int i;
+ efi_uintn_t n = memory_map_size / descriptor_size;
+ efi_uintn_t i;
int rt_code_sections = 0;
struct efi_event *event;
- EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size,
+ EFI_ENTRY("%zx %zx %x %p", memory_map_size, descriptor_size,
descriptor_version, virtmap);
+ efi_virtmap = virtmap;
+ efi_descriptor_size = descriptor_size;
+ efi_descriptor_count = n;
+
/*
* TODO:
* Further down we are cheating. While really we should implement
.get_wakeup_time = (void *)&efi_unimplemented,
.set_wakeup_time = (void *)&efi_unimplemented,
.set_virtual_address_map = &efi_set_virtual_address_map,
- .convert_pointer = (void *)&efi_unimplemented,
+ .convert_pointer = efi_convert_pointer,
.get_variable = efi_get_variable,
.get_next_variable_name = efi_get_next_variable_name,
.set_variable = efi_set_variable,
static u64 page1;
static u64 page2;
static u32 notify_call_count;
+static bool convert_pointer_failed;
/**
* notify () - notification function
addr = (void *)(uintptr_t)page1;
ret = runtime->convert_pointer(0, &addr);
- if (ret != EFI_SUCCESS)
- efi_st_todo("ConvertPointer failed\n");
- if ((uintptr_t)addr != page1 + EFI_PAGE_SIZE)
- efi_st_todo("ConvertPointer wrong address\n");
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("ConvertPointer failed\n");
+ convert_pointer_failed = true;
+ return;
+ }
+ if ((uintptr_t)addr != page1 + EFI_PAGE_SIZE) {
+ efi_st_error("ConvertPointer wrong address\n");
+ convert_pointer_failed = true;
+ return;
+ }
addr = (void *)(uintptr_t)page2;
ret = runtime->convert_pointer(0, &addr);
- if (ret != EFI_SUCCESS)
- efi_st_todo("ConvertPointer failed\n");
- if ((uintptr_t)addr != page2 + 2 * EFI_PAGE_SIZE)
- efi_st_todo("ConvertPointer wrong address\n");
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("ConvertPointer failed\n");
+ convert_pointer_failed = true;
+ return;
+ }
+ if ((uintptr_t)addr != page2 + 2 * EFI_PAGE_SIZE) {
+ efi_st_error("ConvertPointer wrong address\n");
+ convert_pointer_failed = true;
+ }
}
/**
case EFI_LOADER_DATA:
case EFI_BOOT_SERVICES_CODE:
case EFI_BOOT_SERVICES_DATA:
+ case EFI_CONVENTIONAL_MEMORY:
continue;
}
memcpy(pos1, pos2, desc_size);
notify_call_count);
return EFI_ST_FAILURE;
}
+ if (convert_pointer_failed)
+ return EFI_ST_FAILURE;
return EFI_ST_SUCCESS;
}
EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
-$(obj)/efi_crt0.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_CRT0:.o=.S)
+$(obj)/efi_crt0.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_CRT0:.o=.S) FORCE
$(call if_changed_dep,as_o_S)
$(obj)/efi_reloc.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_RELOC:.o=.c) $(recordmcount_source) FORCE
CONFIG_ATMEL_MCI_8BIT
CONFIG_ATMEL_SPI0
CONFIG_AT_TRANS
+CONFIG_AUTOBOOT_MENU_SHOW
CONFIG_AUTO_ZRELADDR
CONFIG_BACKSIDE_L2_CACHE
CONFIG_BAT_PAIR
CONFIG_CTL_TBE
CONFIG_CUSTOMER_BOARD_SUPPORT
CONFIG_D2NET_V2
-CONFIG_DA850_AM18X_EVM
CONFIG_DA850_EVM_MAX_CPU_CLK
CONFIG_DBGU
CONFIG_DB_784MP_GP
CONFIG_MEM_HOLE_16M
CONFIG_MEM_INIT_VALUE
CONFIG_MEM_REMAP
-CONFIG_MENUKEY
-CONFIG_MENUPROMPT
-CONFIG_MENU_SHOW
CONFIG_MFG_ENV_SETTINGS
CONFIG_MIIM_ADDRESS
CONFIG_MII_DEFAULT_TSEC
CONFIG_SHEEVA_88SV131
CONFIG_SHEEVA_88SV331xV5
CONFIG_SHOW_ACTIVITY
-CONFIG_SHOW_BOOT_PROGRESS
CONFIG_SH_CMT_CLK_FREQ
CONFIG_SH_DSP
CONFIG_SH_ETHER_ALIGNE_SIZE
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_BIN_FIXUP
CONFIG_USB_BOOTING
-CONFIG_USB_CABLE_CHECK
CONFIG_USB_DEVICE
CONFIG_USB_DEV_BASE
CONFIG_USB_DEV_PULLUP_GPIO
pclk = clk_get_parent(clk);
ut_asserteq_str("pll3_80m", pclk->dev->name);
+ /* Test the composite of CCF */
+ ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("i2c", clk->dev->name);
+
+ rate = clk_get_rate(clk);
+ ut_asserteq(rate, 60000000);
+
return 1;
}
def check_equal(expected_fname, actual_fname, failure_msg):
"""Check that a file matches its expected contents
+ This is always used on out-buffers whose size is decided by the test
+ script anyway, which in some cases may be larger than what we're
+ actually looking for. So it's safe to truncate it to the size of the
+ expected data.
+
Args:
expected_fname: Filename containing expected contents
actual_fname: Filename containing actual contents
"""
expected_data = read_file(expected_fname)
actual_data = read_file(actual_fname)
+ if len(expected_data) < len(actual_data):
+ actual_data = actual_data[:len(expected_data)]
assert expected_data == actual_data, failure_msg
def check_not_equal(expected_fname, actual_fname, failure_msg):
output = cons.run_command_list(cmd.splitlines())
check_equal(kernel, kernel_out, 'Kernel not loaded')
check_equal(control_dtb, fdt_out, 'FDT not loaded')
- check_equal(ramdisk, ramdisk_out, 'Ramdisk not loaded')
+ check_not_equal(ramdisk, ramdisk_out, 'Ramdisk got decompressed?')
+ check_equal(ramdisk + '.gz', ramdisk_out, 'Ramdist not loaded')
cons = u_boot_console
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2019, Texas Instrument
+# Author: Jean-Jacques Hiblot <jjhiblot@ti.com>
+
+# Test U-Boot's "mmc write" command. The test generates random data, writes it
+# to the eMMC or SD card, then reads it back and performs a comparison.
+
+import pytest
+import u_boot_utils
+
+"""
+This test relies on boardenv_* to containing configuration values to define
+which MMC devices should be tested. For example:
+
+env__mmc_wr_configs = (
+ {
+ "fixture_id": "emmc-boot0",
+ "is_emmc": True,
+ "devid": 1,
+ "partid": 1,
+ "sector": 0x10,
+ "count": 100,
+ "test_iterations": 50,
+ },
+ {
+ "fixture_id": "emmc-boot1",
+ "is_emmc": True,
+ "devid": 1,
+ "partid": 2,
+ "sector": 0x10,
+ "count": 100,
+ "test_iterations": 50,
+ },
+)
+
+"""
+
+@pytest.mark.buildconfigspec('cmd_mmc','cmd_memory')
+def test_mmc_wr(u_boot_console, env__mmc_wr_config):
+ """Test the "mmc write" command.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ env__mmc_wr_config: The single MMC configuration on which
+ to run the test. See the file-level comment above for details
+ of the format.
+
+ Returns:
+ Nothing.
+ """
+
+ is_emmc = env__mmc_wr_config['is_emmc']
+ devid = env__mmc_wr_config['devid']
+ partid = env__mmc_wr_config.get('partid', 0)
+ sector = env__mmc_wr_config.get('sector', 0)
+ count_sectors = env__mmc_wr_config.get('count', 1)
+ test_iterations = env__mmc_wr_config.get('test_iterations', 1)
+
+
+ count_bytes = count_sectors * 512
+ bcfg = u_boot_console.config.buildconfig
+ ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ src_addr = '0x%08x' % ram_base
+ dst_addr = '0x%08x' % (ram_base + count_bytes)
+
+
+ for i in range(test_iterations):
+ # Generate random data
+ cmd = 'random %s %x' % (src_addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ good_response = '%d bytes filled with random data' % (count_bytes)
+ assert good_response in response
+
+ # Select MMC device
+ cmd = 'mmc dev %d' % devid
+ if is_emmc:
+ cmd += ' %d' % partid
+ response = u_boot_console.run_command(cmd)
+ assert 'no card present' not in response
+ if is_emmc:
+ partid_response = "(part %d)" % partid
+ else:
+ partid_response = ""
+ good_response = 'mmc%d%s is current device' % (devid, partid_response)
+ assert good_response in response
+
+ # Write data
+ cmd = 'mmc write %s %x %x' % (src_addr, sector, count_sectors)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'MMC write: dev # %d, block # %d, count %d ... %d blocks written: OK' % (
+ devid, sector, count_sectors, count_sectors)
+ assert good_response in response
+
+ # Read data
+ cmd = 'mmc read %s %x %x' % (dst_addr, sector, count_sectors)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (
+ devid, sector, count_sectors, count_sectors)
+ assert good_response in response
+
+ # Compare src and dst data
+ cmd = 'cmp.b %s %s %x' % (src_addr, dst_addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'Total of %d byte(s) were the same' % (count_bytes)
+ assert good_response in response
--- /dev/null
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
+
+import sys
+import re
+import struct
+import logging
+import argparse
+
+parser = argparse.ArgumentParser(
+ description='Convert a PMU configuration object from C source to a binary blob.')
+parser.add_argument('-D', '--debug', action="store_true")
+parser.add_argument(
+ "in_file", metavar='INPUT_FILE',
+ help='PMU configuration object (C source as produced by Xilinx XSDK)')
+parser.add_argument(
+ "out_file", metavar='OUTPUT_FILE',
+ help='PMU configuration object binary blob')
+args = parser.parse_args()
+
+logging.basicConfig(format='%(levelname)s:%(message)s',
+ level=(logging.DEBUG if args.debug else logging.WARNING))
+
+pm_define = {
+ 'PM_CAP_ACCESS' : 0x1,
+ 'PM_CAP_CONTEXT' : 0x2,
+ 'PM_CAP_WAKEUP' : 0x4,
+
+ 'NODE_UNKNOWN' : 0,
+ 'NODE_APU' : 1,
+ 'NODE_APU_0' : 2,
+ 'NODE_APU_1' : 3,
+ 'NODE_APU_2' : 4,
+ 'NODE_APU_3' : 5,
+ 'NODE_RPU' : 6,
+ 'NODE_RPU_0' : 7,
+ 'NODE_RPU_1' : 8,
+ 'NODE_PLD' : 9,
+ 'NODE_FPD' : 10,
+ 'NODE_OCM_BANK_0' : 11,
+ 'NODE_OCM_BANK_1' : 12,
+ 'NODE_OCM_BANK_2' : 13,
+ 'NODE_OCM_BANK_3' : 14,
+ 'NODE_TCM_0_A' : 15,
+ 'NODE_TCM_0_B' : 16,
+ 'NODE_TCM_1_A' : 17,
+ 'NODE_TCM_1_B' : 18,
+ 'NODE_L2' : 19,
+ 'NODE_GPU_PP_0' : 20,
+ 'NODE_GPU_PP_1' : 21,
+ 'NODE_USB_0' : 22,
+ 'NODE_USB_1' : 23,
+ 'NODE_TTC_0' : 24,
+ 'NODE_TTC_1' : 25,
+ 'NODE_TTC_2' : 26,
+ 'NODE_TTC_3' : 27,
+ 'NODE_SATA' : 28,
+ 'NODE_ETH_0' : 29,
+ 'NODE_ETH_1' : 30,
+ 'NODE_ETH_2' : 31,
+ 'NODE_ETH_3' : 32,
+ 'NODE_UART_0' : 33,
+ 'NODE_UART_1' : 34,
+ 'NODE_SPI_0' : 35,
+ 'NODE_SPI_1' : 36,
+ 'NODE_I2C_0' : 37,
+ 'NODE_I2C_1' : 38,
+ 'NODE_SD_0' : 39,
+ 'NODE_SD_1' : 40,
+ 'NODE_DP' : 41,
+ 'NODE_GDMA' : 42,
+ 'NODE_ADMA' : 43,
+ 'NODE_NAND' : 44,
+ 'NODE_QSPI' : 45,
+ 'NODE_GPIO' : 46,
+ 'NODE_CAN_0' : 47,
+ 'NODE_CAN_1' : 48,
+ 'NODE_EXTERN' : 49,
+ 'NODE_APLL' : 50,
+ 'NODE_VPLL' : 51,
+ 'NODE_DPLL' : 52,
+ 'NODE_RPLL' : 53,
+ 'NODE_IOPLL' : 54,
+ 'NODE_DDR' : 55,
+ 'NODE_IPI_APU' : 56,
+ 'NODE_IPI_RPU_0' : 57,
+ 'NODE_GPU' : 58,
+ 'NODE_PCIE' : 59,
+ 'NODE_PCAP' : 60,
+ 'NODE_RTC' : 61,
+ 'NODE_LPD' : 62,
+ 'NODE_VCU' : 63,
+ 'NODE_IPI_RPU_1' : 64,
+ 'NODE_IPI_PL_0' : 65,
+ 'NODE_IPI_PL_1' : 66,
+ 'NODE_IPI_PL_2' : 67,
+ 'NODE_IPI_PL_3' : 68,
+ 'NODE_PL' : 69,
+ 'NODE_ID_MA' : 70,
+
+ 'XILPM_RESET_PCIE_CFG' : 1000,
+ 'XILPM_RESET_PCIE_BRIDGE' : 1001,
+ 'XILPM_RESET_PCIE_CTRL' : 1002,
+ 'XILPM_RESET_DP' : 1003,
+ 'XILPM_RESET_SWDT_CRF' : 1004,
+ 'XILPM_RESET_AFI_FM5' : 1005,
+ 'XILPM_RESET_AFI_FM4' : 1006,
+ 'XILPM_RESET_AFI_FM3' : 1007,
+ 'XILPM_RESET_AFI_FM2' : 1008,
+ 'XILPM_RESET_AFI_FM1' : 1009,
+ 'XILPM_RESET_AFI_FM0' : 1010,
+ 'XILPM_RESET_GDMA' : 1011,
+ 'XILPM_RESET_GPU_PP1' : 1012,
+ 'XILPM_RESET_GPU_PP0' : 1013,
+ 'XILPM_RESET_GPU' : 1014,
+ 'XILPM_RESET_GT' : 1015,
+ 'XILPM_RESET_SATA' : 1016,
+ 'XILPM_RESET_ACPU3_PWRON' : 1017,
+ 'XILPM_RESET_ACPU2_PWRON' : 1018,
+ 'XILPM_RESET_ACPU1_PWRON' : 1019,
+ 'XILPM_RESET_ACPU0_PWRON' : 1020,
+ 'XILPM_RESET_APU_L2' : 1021,
+ 'XILPM_RESET_ACPU3' : 1022,
+ 'XILPM_RESET_ACPU2' : 1023,
+ 'XILPM_RESET_ACPU1' : 1024,
+ 'XILPM_RESET_ACPU0' : 1025,
+ 'XILPM_RESET_DDR' : 1026,
+ 'XILPM_RESET_APM_FPD' : 1027,
+ 'XILPM_RESET_SOFT' : 1028,
+ 'XILPM_RESET_GEM0' : 1029,
+ 'XILPM_RESET_GEM1' : 1030,
+ 'XILPM_RESET_GEM2' : 1031,
+ 'XILPM_RESET_GEM3' : 1032,
+ 'XILPM_RESET_QSPI' : 1033,
+ 'XILPM_RESET_UART0' : 1034,
+ 'XILPM_RESET_UART1' : 1035,
+ 'XILPM_RESET_SPI0' : 1036,
+ 'XILPM_RESET_SPI1' : 1037,
+ 'XILPM_RESET_SDIO0' : 1038,
+ 'XILPM_RESET_SDIO1' : 1039,
+ 'XILPM_RESET_CAN0' : 1040,
+ 'XILPM_RESET_CAN1' : 1041,
+ 'XILPM_RESET_I2C0' : 1042,
+ 'XILPM_RESET_I2C1' : 1043,
+ 'XILPM_RESET_TTC0' : 1044,
+ 'XILPM_RESET_TTC1' : 1045,
+ 'XILPM_RESET_TTC2' : 1046,
+ 'XILPM_RESET_TTC3' : 1047,
+ 'XILPM_RESET_SWDT_CRL' : 1048,
+ 'XILPM_RESET_NAND' : 1049,
+ 'XILPM_RESET_ADMA' : 1050,
+ 'XILPM_RESET_GPIO' : 1051,
+ 'XILPM_RESET_IOU_CC' : 1052,
+ 'XILPM_RESET_TIMESTAMP' : 1053,
+ 'XILPM_RESET_RPU_R50' : 1054,
+ 'XILPM_RESET_RPU_R51' : 1055,
+ 'XILPM_RESET_RPU_AMBA' : 1056,
+ 'XILPM_RESET_OCM' : 1057,
+ 'XILPM_RESET_RPU_PGE' : 1058,
+ 'XILPM_RESET_USB0_CORERESET' : 1059,
+ 'XILPM_RESET_USB1_CORERESET' : 1060,
+ 'XILPM_RESET_USB0_HIBERRESET' : 1061,
+ 'XILPM_RESET_USB1_HIBERRESET' : 1062,
+ 'XILPM_RESET_USB0_APB' : 1063,
+ 'XILPM_RESET_USB1_APB' : 1064,
+ 'XILPM_RESET_IPI' : 1065,
+ 'XILPM_RESET_APM_LPD' : 1066,
+ 'XILPM_RESET_RTC' : 1067,
+ 'XILPM_RESET_SYSMON' : 1068,
+ 'XILPM_RESET_AFI_FM6' : 1069,
+ 'XILPM_RESET_LPD_SWDT' : 1070,
+ 'XILPM_RESET_FPD' : 1071,
+ 'XILPM_RESET_RPU_DBG1' : 1072,
+ 'XILPM_RESET_RPU_DBG0' : 1073,
+ 'XILPM_RESET_DBG_LPD' : 1074,
+ 'XILPM_RESET_DBG_FPD' : 1075,
+ 'XILPM_RESET_APLL' : 1076,
+ 'XILPM_RESET_DPLL' : 1077,
+ 'XILPM_RESET_VPLL' : 1078,
+ 'XILPM_RESET_IOPLL' : 1079,
+ 'XILPM_RESET_RPLL' : 1080,
+ 'XILPM_RESET_GPO3_PL_0' : 1081,
+ 'XILPM_RESET_GPO3_PL_1' : 1082,
+ 'XILPM_RESET_GPO3_PL_2' : 1083,
+ 'XILPM_RESET_GPO3_PL_3' : 1084,
+ 'XILPM_RESET_GPO3_PL_4' : 1085,
+ 'XILPM_RESET_GPO3_PL_5' : 1086,
+ 'XILPM_RESET_GPO3_PL_6' : 1087,
+ 'XILPM_RESET_GPO3_PL_7' : 1088,
+ 'XILPM_RESET_GPO3_PL_8' : 1089,
+ 'XILPM_RESET_GPO3_PL_9' : 1090,
+ 'XILPM_RESET_GPO3_PL_10' : 1091,
+ 'XILPM_RESET_GPO3_PL_11' : 1092,
+ 'XILPM_RESET_GPO3_PL_12' : 1093,
+ 'XILPM_RESET_GPO3_PL_13' : 1094,
+ 'XILPM_RESET_GPO3_PL_14' : 1095,
+ 'XILPM_RESET_GPO3_PL_15' : 1096,
+ 'XILPM_RESET_GPO3_PL_16' : 1097,
+ 'XILPM_RESET_GPO3_PL_17' : 1098,
+ 'XILPM_RESET_GPO3_PL_18' : 1099,
+ 'XILPM_RESET_GPO3_PL_19' : 1100,
+ 'XILPM_RESET_GPO3_PL_20' : 1101,
+ 'XILPM_RESET_GPO3_PL_21' : 1102,
+ 'XILPM_RESET_GPO3_PL_22' : 1103,
+ 'XILPM_RESET_GPO3_PL_23' : 1104,
+ 'XILPM_RESET_GPO3_PL_24' : 1105,
+ 'XILPM_RESET_GPO3_PL_25' : 1106,
+ 'XILPM_RESET_GPO3_PL_26' : 1107,
+ 'XILPM_RESET_GPO3_PL_27' : 1108,
+ 'XILPM_RESET_GPO3_PL_28' : 1109,
+ 'XILPM_RESET_GPO3_PL_29' : 1110,
+ 'XILPM_RESET_GPO3_PL_30' : 1111,
+ 'XILPM_RESET_GPO3_PL_31' : 1112,
+ 'XILPM_RESET_RPU_LS' : 1113,
+ 'XILPM_RESET_PS_ONLY' : 1114,
+ 'XILPM_RESET_PL' : 1115,
+ 'XILPM_RESET_GPIO5_EMIO_92' : 1116,
+ 'XILPM_RESET_GPIO5_EMIO_93' : 1117,
+ 'XILPM_RESET_GPIO5_EMIO_94' : 1118,
+ 'XILPM_RESET_GPIO5_EMIO_95' : 1119,
+
+ 'PM_CONFIG_MASTER_SECTION_ID' : 0x101,
+ 'PM_CONFIG_SLAVE_SECTION_ID' : 0x102,
+ 'PM_CONFIG_PREALLOC_SECTION_ID' : 0x103,
+ 'PM_CONFIG_POWER_SECTION_ID' : 0x104,
+ 'PM_CONFIG_RESET_SECTION_ID' : 0x105,
+ 'PM_CONFIG_SHUTDOWN_SECTION_ID' : 0x106,
+ 'PM_CONFIG_SET_CONFIG_SECTION_ID' : 0x107,
+ 'PM_CONFIG_GPO_SECTION_ID' : 0x108,
+
+ 'PM_SLAVE_FLAG_IS_SHAREABLE' : 0x1,
+ 'PM_MASTER_USING_SLAVE_MASK' : 0x2,
+
+ 'PM_CONFIG_GPO1_MIO_PIN_34_MAP' : (1 << 10),
+ 'PM_CONFIG_GPO1_MIO_PIN_35_MAP' : (1 << 11),
+ 'PM_CONFIG_GPO1_MIO_PIN_36_MAP' : (1 << 12),
+ 'PM_CONFIG_GPO1_MIO_PIN_37_MAP' : (1 << 13),
+
+ 'PM_CONFIG_GPO1_BIT_2_MASK' : (1 << 2),
+ 'PM_CONFIG_GPO1_BIT_3_MASK' : (1 << 3),
+ 'PM_CONFIG_GPO1_BIT_4_MASK' : (1 << 4),
+ 'PM_CONFIG_GPO1_BIT_5_MASK' : (1 << 5),
+
+ 'SUSPEND_TIMEOUT' : 0xFFFFFFFF,
+
+ 'PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK' : 0x00000001,
+ 'PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK' : 0x00000100,
+ 'PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK' : 0x00000200,
+}
+
+in_file = open(args.in_file, mode='r')
+out_file = open(args.out_file, mode='wb')
+
+num_re = re.compile(r"^([0-9]+)U?$")
+const_re = re.compile(r"^([A-Z_][A-Z0-9_]*)$")
+
+def process_item(item):
+ logging.debug("* ITEM " + item)
+
+ value = 0
+ for item in item.split('|'):
+ item = item.strip()
+
+ num_match = num_re .match(item)
+ const_match = const_re.match(item)
+
+ if num_match:
+ num = int(num_match.group(1))
+ logging.debug(" - num " + str(num))
+ value |= num
+ elif const_match:
+ name = const_match.group(1)
+ if not name in pm_define:
+ sys.stderr.write("Unknown define " + name + "!\n")
+ exit(1)
+ num = pm_define[name]
+ logging.debug(" - def " + hex(num))
+ value |= num
+
+ logging.debug(" = res " + hex(value))
+ out_file.write(struct.pack('<L', value))
+
+
+# Read all code
+code = in_file.read()
+
+# remove comments
+code = re.sub('//.*?\n|/\*.*?\*/', '', code, flags=re.DOTALL)
+
+# remove everything outside the XPm_ConfigObject array definition
+code = re.search('const u32 XPm_ConfigObject.*= {\n(.*)};',
+ code, flags=re.DOTALL).group(1)
+
+# Process each comma-separated array item
+for item in code.split(','):
+ item = item.strip()
+ if item:
+ process_item(item)
+
+print("Wrote %d bytes" % out_file.tell())
--- /dev/null
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com>
+# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
+
+usage()
+{
+ cat <<EOF
+
+Transform a pair of psu_init_gpl.c and .h files produced by the Xilinx
+Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that is almost
+checkpatch compliant. Minor coding style might still be needed. Must be
+run from the top-level U-Boot source directory.
+
+Usage: zynqmp_psu_init_minimize.sh INPUT_DIR OUTPUT_DIR
+Example: zynqmp_psu_init_minimize.sh \\
+ /path/to/original/psu_init_gpl_c_and_h/ \\
+ board/xilinx/zynqmp/<my_board>/
+
+Notes: INPUT_DIR must contain both .c and .h files.
+ If INPUT_DIR and OUTPUT_DIR are the same directory,
+ psu_init_gpl.c will be overwritten.
+
+EOF
+}
+
+set -o errexit -o errtrace
+set -o nounset
+
+if [ $# -ne 2 ]
+then
+ usage >&2
+ exit 1
+fi
+
+IN="${1}/psu_init_gpl.c"
+OUT="${2}/psu_init_gpl.c"
+TMP=$(mktemp /tmp/psu_init_gpl.XXXXXX)
+trap "rm ${TMP}" ERR
+
+# Step through a temp file to allow both $IN!=$OUT and $IN==$OUT
+sed -e '/sleep.h/d' \
+ -e '/xil_io.h/d' \
+ ${IN} >${TMP}
+cp ${TMP} ${OUT}
+
+# preprocess to expand defines, then remove cpp lines starting with '#'
+gcc -I${1} -E ${OUT} -o ${TMP}
+sed '/^#/d' ${TMP} >${OUT}
+
+# Remove trivial code before psu_pll_init_data()
+sed -ni '/psu_pll_init_data/,$p' ${OUT}
+
+# Functions are lowercase in U-Boot, rename them
+sed -i 's/PSU_Mask_Write/psu_mask_write/g' ${OUT}
+sed -i 's/mask_pollOnValue/mask_pollonvalue/g' ${OUT}
+sed -i 's/RegValue/regvalue/g' ${OUT}
+sed -i 's/MaskStatus/maskstatus/g' ${OUT}
+
+sed -i '/&= psu_peripherals_powerdwn_data()/d' ${OUT}
+
+FUNCS_TO_REMOVE="psu_protection
+psu_..._protection
+psu_init_xppu_aper_ram
+mask_delay(u32
+mask_read(u32
+dpll_prog
+mask_poll(u32
+mask_pollonvalue(u32
+psu_ps_pl_reset_config_data
+psu_ps_pl_isolation_removal_data
+psu_apply_master_tz
+psu_post_config_data
+psu_post_config_data
+psu_peripherals_powerdwn_data
+psu_init_ddr_self_refresh
+xmpu
+xppu
+"
+for i in $FUNCS_TO_REMOVE; do
+sed -i "/$i/,/^}$/d" ${OUT}
+done
+
+scripts/Lindent ${OUT}
+
+# Prepend 'static' to internal functions
+sed -i 's/^.*data(void)$/static &/g' ${OUT}
+sed -i 's/^.*psu_afi_config(void)$/static &/g' ${OUT}
+sed -i 's/^void init_peripheral/static &/g' ${OUT}
+sed -i 's/^int serdes/static &/g' ${OUT}
+sed -i 's/^int init_serdes/static &/g' ${OUT}
+sed -i 's/^unsigned long /static &/g' ${OUT}
+
+sed -i 's/()$/(void)/g' ${OUT}
+sed -i 's/0X/0x/g' ${OUT}
+
+# return (0) -> return 0
+sed -ri 's/return \(([0-9]+)\)/return \1/g' ${OUT}
+
+# Add header
+cat << EOF >${TMP}
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+EOF
+
+cat ${OUT} >>${TMP}
+cp ${TMP} ${OUT}
+
+# Temporarily convert newlines to do some mangling across lines
+tr "\n" "\r" <${OUT} >${TMP}
+
+# Cleanup empty loops. E.g.:
+# |while (e) {|
+# | | ==> |while (e)|
+# | } | | ; |
+# | |
+sed -i -r 's| \{\r+(\t*)\}\r\r|\n\1\t;\n|g' ${TMP}
+
+# Remove empty line between variable declaration
+sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP}
+
+# Remove empty lines at function beginning/end
+sed -i -e 's|\r{\r\r|\r{\r|g' ${TMP}
+sed -i -e 's|\r\r}\r|\r}\r|g' ${TMP}
+
+# Remove empty lines after '{' line
+sed -i -e 's| {\r\r| {\r|g' ${TMP}
+
+# Remove braces {} around single statement blocks. E.g.:
+# | while (e) { | | while (e) |
+# | stg(); | => | stg();|
+# | } |
+sed -i -r 's| \{(\r[^\r]*;)\r\t*\}|\1|g' ${TMP}
+
+# Remove Unnecessary parentheses around 'n_code <= 0x3C' and similar. E.g.:
+# if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...)
+sed -i -r 's|\((._code .= [x[:xdigit:]]+)\)|\1|g' ${TMP}
+
+# Convert back newlines
+tr "\r" "\n" <${TMP} >${OUT}
+
+rm ${TMP}
projects / platform / kernel / u-boot.git / commitdiff