Merge git://www.denx.de/git/u-boot-marvell
authorTom Rini <trini@konsulko.com>
Tue, 8 Aug 2017 21:05:33 +0000 (17:05 -0400)
committerTom Rini <trini@konsulko.com>
Tue, 8 Aug 2017 21:05:33 +0000 (17:05 -0400)
768 files changed:
README
arch/arm/Kconfig
arch/arm/include/asm/arch-bcmcygnus/configs.h
arch/arm/mach-mvebu/include/mach/config.h
arch/powerpc/include/asm/config.h
cmd/net.c
configs/10m50_defconfig
configs/3c120_defconfig
configs/B4420QDS_NAND_defconfig
configs/B4420QDS_SPIFLASH_defconfig
configs/B4420QDS_defconfig
configs/B4860QDS_NAND_defconfig
configs/B4860QDS_SECURE_BOOT_defconfig
configs/B4860QDS_SPIFLASH_defconfig
configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
configs/B4860QDS_defconfig
configs/BSC9131RDB_NAND_SYSCLK100_defconfig
configs/BSC9131RDB_NAND_defconfig
configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
configs/BSC9131RDB_SPIFLASH_defconfig
configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
configs/BSC9132QDS_NAND_DDRCLK100_defconfig
configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
configs/BSC9132QDS_NAND_DDRCLK133_defconfig
configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
configs/BSC9132QDS_NOR_DDRCLK100_defconfig
configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
configs/BSC9132QDS_NOR_DDRCLK133_defconfig
configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
configs/C29XPCIE_NAND_defconfig
configs/C29XPCIE_NOR_SECBOOT_defconfig
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
configs/C29XPCIE_SPIFLASH_defconfig
configs/C29XPCIE_defconfig
configs/Cyrus_P5020_defconfig
configs/Cyrus_P5040_defconfig
configs/MPC8308RDB_defconfig
configs/MPC8313ERDB_33_defconfig
configs/MPC8313ERDB_66_defconfig
configs/MPC8313ERDB_NAND_33_defconfig
configs/MPC8313ERDB_NAND_66_defconfig
configs/MPC8315ERDB_defconfig
configs/MPC8349EMDS_defconfig
configs/MPC8349ITXGP_defconfig
configs/MPC8349ITX_LOWBOOT_defconfig
configs/MPC8349ITX_defconfig
configs/MPC837XEMDS_HOST_defconfig
configs/MPC837XEMDS_defconfig
configs/MPC837XERDB_defconfig
configs/MPC8536DS_36BIT_defconfig
configs/MPC8536DS_SDCARD_defconfig
configs/MPC8536DS_SPIFLASH_defconfig
configs/MPC8536DS_defconfig
configs/MPC8541CDS_defconfig
configs/MPC8541CDS_legacy_defconfig
configs/MPC8544DS_defconfig
configs/MPC8548CDS_36BIT_defconfig
configs/MPC8548CDS_defconfig
configs/MPC8548CDS_legacy_defconfig
configs/MPC8555CDS_defconfig
configs/MPC8555CDS_legacy_defconfig
configs/MPC8568MDS_defconfig
configs/MPC8572DS_36BIT_defconfig
configs/MPC8572DS_defconfig
configs/MPC8641HPCN_36BIT_defconfig
configs/MPC8641HPCN_defconfig
configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
configs/P1010RDB-PA_36BIT_NAND_defconfig
configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
configs/P1010RDB-PA_36BIT_NOR_defconfig
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PA_NAND_SECBOOT_defconfig
configs/P1010RDB-PA_NAND_defconfig
configs/P1010RDB-PA_NOR_SECBOOT_defconfig
configs/P1010RDB-PA_NOR_defconfig
configs/P1010RDB-PA_SDCARD_defconfig
configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
configs/P1010RDB-PA_SPIFLASH_defconfig
configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
configs/P1010RDB-PB_36BIT_NAND_defconfig
configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
configs/P1010RDB-PB_36BIT_NOR_defconfig
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PB_NAND_SECBOOT_defconfig
configs/P1010RDB-PB_NAND_defconfig
configs/P1010RDB-PB_NOR_SECBOOT_defconfig
configs/P1010RDB-PB_NOR_defconfig
configs/P1010RDB-PB_SDCARD_defconfig
configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
configs/P1010RDB-PB_SPIFLASH_defconfig
configs/P1020MBG-PC_36BIT_SDCARD_defconfig
configs/P1020MBG-PC_36BIT_defconfig
configs/P1020MBG-PC_SDCARD_defconfig
configs/P1020MBG-PC_defconfig
configs/P1020RDB-PC_36BIT_NAND_defconfig
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P1020RDB-PC_36BIT_defconfig
configs/P1020RDB-PC_NAND_defconfig
configs/P1020RDB-PC_SDCARD_defconfig
configs/P1020RDB-PC_SPIFLASH_defconfig
configs/P1020RDB-PC_defconfig
configs/P1020RDB-PD_NAND_defconfig
configs/P1020RDB-PD_SDCARD_defconfig
configs/P1020RDB-PD_SPIFLASH_defconfig
configs/P1020RDB-PD_defconfig
configs/P1020UTM-PC_36BIT_SDCARD_defconfig
configs/P1020UTM-PC_36BIT_defconfig
configs/P1020UTM-PC_SDCARD_defconfig
configs/P1020UTM-PC_defconfig
configs/P1021RDB-PC_36BIT_NAND_defconfig
configs/P1021RDB-PC_36BIT_SDCARD_defconfig
configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
configs/P1021RDB-PC_36BIT_defconfig
configs/P1021RDB-PC_NAND_defconfig
configs/P1021RDB-PC_SDCARD_defconfig
configs/P1021RDB-PC_SPIFLASH_defconfig
configs/P1021RDB-PC_defconfig
configs/P1022DS_36BIT_NAND_defconfig
configs/P1022DS_36BIT_SDCARD_defconfig
configs/P1022DS_36BIT_SPIFLASH_defconfig
configs/P1022DS_36BIT_defconfig
configs/P1022DS_NAND_defconfig
configs/P1022DS_SDCARD_defconfig
configs/P1022DS_SPIFLASH_defconfig
configs/P1022DS_defconfig
configs/P1023RDB_defconfig
configs/P1024RDB_36BIT_defconfig
configs/P1024RDB_NAND_defconfig
configs/P1024RDB_SDCARD_defconfig
configs/P1024RDB_SPIFLASH_defconfig
configs/P1024RDB_defconfig
configs/P1025RDB_36BIT_defconfig
configs/P1025RDB_NAND_defconfig
configs/P1025RDB_SDCARD_defconfig
configs/P1025RDB_SPIFLASH_defconfig
configs/P1025RDB_defconfig
configs/P2020RDB-PC_36BIT_NAND_defconfig
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P2020RDB-PC_36BIT_defconfig
configs/P2020RDB-PC_NAND_defconfig
configs/P2020RDB-PC_SDCARD_defconfig
configs/P2020RDB-PC_SPIFLASH_defconfig
configs/P2020RDB-PC_defconfig
configs/P2041RDB_NAND_defconfig
configs/P2041RDB_SDCARD_defconfig
configs/P2041RDB_SECURE_BOOT_defconfig
configs/P2041RDB_SPIFLASH_defconfig
configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
configs/P2041RDB_defconfig
configs/P3041DS_NAND_SECURE_BOOT_defconfig
configs/P3041DS_NAND_defconfig
configs/P3041DS_SDCARD_defconfig
configs/P3041DS_SECURE_BOOT_defconfig
configs/P3041DS_SPIFLASH_defconfig
configs/P3041DS_SRIO_PCIE_BOOT_defconfig
configs/P3041DS_defconfig
configs/P4080DS_SDCARD_defconfig
configs/P4080DS_SECURE_BOOT_defconfig
configs/P4080DS_SPIFLASH_defconfig
configs/P4080DS_SRIO_PCIE_BOOT_defconfig
configs/P4080DS_defconfig
configs/P5020DS_NAND_SECURE_BOOT_defconfig
configs/P5020DS_NAND_defconfig
configs/P5020DS_SDCARD_defconfig
configs/P5020DS_SECURE_BOOT_defconfig
configs/P5020DS_SPIFLASH_defconfig
configs/P5020DS_SRIO_PCIE_BOOT_defconfig
configs/P5020DS_defconfig
configs/P5040DS_NAND_SECURE_BOOT_defconfig
configs/P5040DS_NAND_defconfig
configs/P5040DS_SDCARD_defconfig
configs/P5040DS_SECURE_BOOT_defconfig
configs/P5040DS_SPIFLASH_defconfig
configs/P5040DS_defconfig
configs/T1023RDB_NAND_defconfig
configs/T1023RDB_SDCARD_defconfig
configs/T1023RDB_SECURE_BOOT_defconfig
configs/T1023RDB_SPIFLASH_defconfig
configs/T1023RDB_defconfig
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
configs/T1024QDS_DDR4_defconfig
configs/T1024QDS_NAND_defconfig
configs/T1024QDS_SDCARD_defconfig
configs/T1024QDS_SECURE_BOOT_defconfig
configs/T1024QDS_SPIFLASH_defconfig
configs/T1024QDS_defconfig
configs/T1024RDB_NAND_defconfig
configs/T1024RDB_SDCARD_defconfig
configs/T1024RDB_SECURE_BOOT_defconfig
configs/T1024RDB_SPIFLASH_defconfig
configs/T1024RDB_defconfig
configs/T1040D4RDB_NAND_defconfig
configs/T1040D4RDB_SDCARD_defconfig
configs/T1040D4RDB_SECURE_BOOT_defconfig
configs/T1040D4RDB_SPIFLASH_defconfig
configs/T1040D4RDB_defconfig
configs/T1040QDS_DDR4_defconfig
configs/T1040QDS_SECURE_BOOT_defconfig
configs/T1040QDS_defconfig
configs/T1040RDB_NAND_defconfig
configs/T1040RDB_SDCARD_defconfig
configs/T1040RDB_SECURE_BOOT_defconfig
configs/T1040RDB_SPIFLASH_defconfig
configs/T1040RDB_defconfig
configs/T1042D4RDB_NAND_defconfig
configs/T1042D4RDB_SDCARD_defconfig
configs/T1042D4RDB_SECURE_BOOT_defconfig
configs/T1042D4RDB_SPIFLASH_defconfig
configs/T1042D4RDB_defconfig
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
configs/T1042RDB_PI_NAND_defconfig
configs/T1042RDB_PI_SDCARD_defconfig
configs/T1042RDB_PI_SPIFLASH_defconfig
configs/T1042RDB_PI_defconfig
configs/T1042RDB_SECURE_BOOT_defconfig
configs/T1042RDB_defconfig
configs/T2080QDS_NAND_defconfig
configs/T2080QDS_SDCARD_defconfig
configs/T2080QDS_SECURE_BOOT_defconfig
configs/T2080QDS_SPIFLASH_defconfig
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
configs/T2080QDS_defconfig
configs/T2080RDB_NAND_defconfig
configs/T2080RDB_SDCARD_defconfig
configs/T2080RDB_SECURE_BOOT_defconfig
configs/T2080RDB_SPIFLASH_defconfig
configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
configs/T2080RDB_defconfig
configs/T2081QDS_NAND_defconfig
configs/T2081QDS_SDCARD_defconfig
configs/T2081QDS_SPIFLASH_defconfig
configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
configs/T2081QDS_defconfig
configs/T4160QDS_NAND_defconfig
configs/T4160QDS_SDCARD_defconfig
configs/T4160QDS_SECURE_BOOT_defconfig
configs/T4160QDS_defconfig
configs/T4160RDB_defconfig
configs/T4240QDS_NAND_defconfig
configs/T4240QDS_SDCARD_defconfig
configs/T4240QDS_SECURE_BOOT_defconfig
configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
configs/T4240QDS_defconfig
configs/T4240RDB_SDCARD_defconfig
configs/T4240RDB_defconfig
configs/TQM834x_defconfig
configs/TWR-P1025_defconfig
configs/UCP1020_SPIFLASH_defconfig
configs/UCP1020_defconfig
configs/alt_defconfig
configs/am335x_baltos_defconfig
configs/am335x_boneblack_defconfig
configs/am335x_boneblack_vboot_defconfig
configs/am335x_evm_defconfig
configs/am335x_evm_nor_defconfig
configs/am335x_evm_norboot_defconfig
configs/am335x_evm_spiboot_defconfig
configs/am335x_evm_usbspl_defconfig
configs/am335x_hs_evm_defconfig
configs/am335x_igep003x_defconfig
configs/am335x_shc_defconfig
configs/am335x_shc_ict_defconfig
configs/am335x_shc_netboot_defconfig
configs/am335x_shc_prompt_defconfig
configs/am335x_shc_sdboot_defconfig
configs/am335x_shc_sdboot_prompt_defconfig
configs/am335x_sl50_defconfig
configs/am43xx_evm_defconfig
configs/am43xx_evm_ethboot_defconfig
configs/am43xx_evm_qspiboot_defconfig
configs/am43xx_evm_usbhost_boot_defconfig
configs/am43xx_hs_evm_defconfig
configs/am57xx_evm_defconfig
configs/am57xx_evm_nodt_defconfig
configs/am57xx_hs_evm_defconfig
configs/ap_sh4a_4a_defconfig
configs/apalis_imx6_defconfig
configs/apalis_imx6_nospl_com_defconfig
configs/apalis_imx6_nospl_it_defconfig
configs/aristainetos2_defconfig
configs/aristainetos2b_defconfig
configs/aristainetos_defconfig
configs/armadillo-800eva_defconfig
configs/axm_defconfig
configs/axs101_defconfig
configs/axs103_defconfig
configs/bcm28155_w1d_defconfig
configs/bcm911360_entphn-ns_defconfig
configs/bcm911360_entphn_defconfig
configs/bcm911360k_defconfig
configs/bcm958300k-ns_defconfig
configs/bcm958300k_defconfig
configs/bcm958305k_defconfig
configs/birdland_bav335a_defconfig
configs/birdland_bav335b_defconfig
configs/bk4r1_defconfig
configs/brppt1_mmc_defconfig
configs/brppt1_nand_defconfig
configs/brppt1_spi_defconfig
configs/brxre1_defconfig
configs/cgtqmx6eval_defconfig
configs/chiliboard_defconfig
configs/cl-som-am57x_defconfig
configs/clearfog_defconfig
configs/cm_fx6_defconfig
configs/cm_t335_defconfig
configs/cm_t43_defconfig
configs/colibri_imx6_defconfig
configs/colibri_imx6_nospl_defconfig
configs/colibri_imx7_defconfig
configs/colibri_vf_defconfig
configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
configs/controlcenterd_36BIT_SDCARD_defconfig
configs/controlcenterdc_defconfig
configs/corvus_defconfig
configs/db-88f6720_defconfig
configs/db-88f6820-amc_defconfig
configs/db-88f6820-gp_defconfig
configs/db-mv784mp-gp_defconfig
configs/devkit3250_defconfig
configs/dms-ba16-1g_defconfig
configs/dms-ba16_defconfig
configs/dra7xx_evm_defconfig
configs/dra7xx_hs_evm_defconfig
configs/draco_defconfig
configs/ds414_defconfig
configs/ecovec_defconfig
configs/espt_defconfig
configs/etamin_defconfig
configs/evb-rk3288_defconfig
configs/evb-rk3399_defconfig
configs/flea3_defconfig
configs/gose_defconfig
configs/gurnard_defconfig
configs/hrcon_defconfig
configs/hrcon_dh_defconfig
configs/ids8313_defconfig
configs/imx6q_logic_defconfig
configs/k2e_evm_defconfig
configs/k2e_hs_evm_defconfig
configs/k2g_evm_defconfig
configs/k2g_hs_evm_defconfig
configs/k2hk_evm_defconfig
configs/k2hk_hs_evm_defconfig
configs/k2l_evm_defconfig
configs/kmcoge4_defconfig
configs/kmlion1_defconfig
configs/koelsch_defconfig
configs/lager_defconfig
configs/liteboard_defconfig
configs/ls1021aiot_qspi_defconfig
configs/ls1021aiot_sdcard_defconfig
configs/ls1021aqds_ddr4_nor_defconfig
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
configs/ls1021aqds_nand_defconfig
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
configs/ls1021aqds_nor_defconfig
configs/ls1021aqds_nor_lpuart_defconfig
configs/ls1021aqds_qspi_defconfig
configs/ls1021aqds_sdcard_ifc_defconfig
configs/ls1021aqds_sdcard_qspi_defconfig
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
configs/ls1021atwr_nor_defconfig
configs/ls1021atwr_nor_lpuart_defconfig
configs/ls1021atwr_qspi_defconfig
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
configs/ls1021atwr_sdcard_ifc_defconfig
configs/ls1021atwr_sdcard_qspi_defconfig
configs/ls1043aqds_defconfig
configs/ls1043aqds_lpuart_defconfig
configs/ls1043aqds_nand_defconfig
configs/ls1043aqds_nor_ddr3_defconfig
configs/ls1043aqds_qspi_defconfig
configs/ls1043aqds_sdcard_ifc_defconfig
configs/ls1043aqds_sdcard_qspi_defconfig
configs/ls1043ardb_SECURE_BOOT_defconfig
configs/ls1043ardb_defconfig
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
configs/ls1043ardb_nand_defconfig
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
configs/ls1043ardb_sdcard_defconfig
configs/ls1046aqds_SECURE_BOOT_defconfig
configs/ls1046aqds_defconfig
configs/ls1046aqds_lpuart_defconfig
configs/ls1046aqds_nand_defconfig
configs/ls1046aqds_qspi_defconfig
configs/ls1046aqds_sdcard_ifc_defconfig
configs/ls1046aqds_sdcard_qspi_defconfig
configs/ls1046ardb_emmc_defconfig
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
configs/ls1046ardb_qspi_defconfig
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
configs/ls1046ardb_sdcard_defconfig
configs/ls2080aqds_SECURE_BOOT_defconfig
configs/ls2080aqds_defconfig
configs/ls2080aqds_nand_defconfig
configs/ls2080aqds_qspi_defconfig
configs/ls2080aqds_sdcard_defconfig
configs/ls2080ardb_SECURE_BOOT_defconfig
configs/ls2080ardb_defconfig
configs/ls2080ardb_nand_defconfig
configs/ls2081ardb_defconfig
configs/ls2088ardb_qspi_defconfig
configs/m53evk_defconfig
configs/marsboard_defconfig
configs/maxbcm_defconfig
configs/mccmon6_nor_defconfig
configs/mccmon6_sd_defconfig
configs/microblaze-generic_defconfig
configs/mpc8308_p1m_defconfig
configs/mvebu_db-88f3720_defconfig
configs/mvebu_db_armada8k_defconfig
configs/mvebu_espressobin-88f3720_defconfig
configs/mvebu_mcbin-88f8040_defconfig
configs/mx6cuboxi_defconfig
configs/mx6qsabrelite_defconfig
configs/mx6sabreauto_defconfig
configs/mx6sabresd_defconfig
configs/mx6slevk_defconfig
configs/mx6slevk_spinor_defconfig
configs/mx6slevk_spl_defconfig
configs/mx6sxsabreauto_defconfig
configs/mx6sxsabresd_defconfig
configs/mx6sxsabresd_spl_defconfig
configs/mx6ul_14x14_evk_defconfig
configs/mx6ul_9x9_evk_defconfig
configs/mx7dsabresd_defconfig
configs/mx7dsabresd_secure_defconfig
configs/nitrogen6dl2g_defconfig
configs/nitrogen6dl_defconfig
configs/nitrogen6q2g_defconfig
configs/nitrogen6q_defconfig
configs/nitrogen6s1g_defconfig
configs/nitrogen6s_defconfig
configs/novena_defconfig
configs/ot1200_defconfig
configs/ot1200_spl_defconfig
configs/pcm051_rev1_defconfig
configs/pcm051_rev3_defconfig
configs/pcm052_defconfig
configs/pcm058_defconfig
configs/pengwyn_defconfig
configs/pepper_defconfig
configs/pico-imx6ul_defconfig
configs/pico-imx7d_defconfig
configs/platinum_picon_defconfig
configs/platinum_titanium_defconfig
configs/porter_defconfig
configs/pxm2_defconfig
configs/r0p7734_defconfig
configs/r8a7795_salvator-x_defconfig
configs/r8a7796_salvator-x_defconfig
configs/rastaban_defconfig
configs/riotboard_defconfig
configs/rut_defconfig
configs/sbc8349_PCI_33_defconfig
configs/sbc8349_PCI_66_defconfig
configs/sbc8349_defconfig
configs/sbc8548_PCI_33_PCIE_defconfig
configs/sbc8548_PCI_33_defconfig
configs/sbc8548_PCI_66_PCIE_defconfig
configs/sbc8548_PCI_66_defconfig
configs/sbc8548_defconfig
configs/sbc8641d_defconfig
configs/sc_sps_1_defconfig
configs/secomx6quq7_defconfig
configs/sh7752evb_defconfig
configs/sh7753evb_defconfig
configs/sh7757lcr_defconfig
configs/sh7763rdp_defconfig
configs/silk_defconfig
configs/smartweb_defconfig
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_de0_nano_soc_defconfig
configs/socfpga_de10_nano_defconfig
configs/socfpga_de1_soc_defconfig
configs/socfpga_is1_defconfig
configs/socfpga_mcvevk_defconfig
configs/socfpga_sockit_defconfig
configs/socfpga_socrates_defconfig
configs/socfpga_sr1500_defconfig
configs/socfpga_vining_fpga_defconfig
configs/socrates_defconfig
configs/spear300_defconfig
configs/spear300_nand_defconfig
configs/spear300_usbtty_defconfig
configs/spear300_usbtty_nand_defconfig
configs/spear310_defconfig
configs/spear310_nand_defconfig
configs/spear310_pnor_defconfig
configs/spear310_usbtty_defconfig
configs/spear310_usbtty_nand_defconfig
configs/spear310_usbtty_pnor_defconfig
configs/spear320_defconfig
configs/spear320_nand_defconfig
configs/spear320_pnor_defconfig
configs/spear320_usbtty_defconfig
configs/spear320_usbtty_nand_defconfig
configs/spear320_usbtty_pnor_defconfig
configs/spear600_defconfig
configs/spear600_nand_defconfig
configs/spear600_usbtty_defconfig
configs/spear600_usbtty_nand_defconfig
configs/stout_defconfig
configs/strider_con_defconfig
configs/strider_con_dp_defconfig
configs/strider_cpu_defconfig
configs/strider_cpu_dp_defconfig
configs/stv0991_defconfig
configs/taurus_defconfig
configs/tb100_defconfig
configs/tbs2910_defconfig
configs/theadorable_debug_defconfig
configs/thuban_defconfig
configs/ti814x_evm_defconfig
configs/titanium_defconfig
configs/tplink_wdr4300_defconfig
configs/tqma6dl_mba6_mmc_defconfig
configs/tqma6dl_mba6_spi_defconfig
configs/tqma6q_mba6_mmc_defconfig
configs/tqma6q_mba6_spi_defconfig
configs/tqma6s_mba6_mmc_defconfig
configs/tqma6s_mba6_spi_defconfig
configs/tqma6s_wru4_mmc_defconfig
configs/ts4800_defconfig
configs/turris_omnia_defconfig
configs/udoo_defconfig
configs/udoo_neo_defconfig
configs/ve8313_defconfig
configs/vf610twr_defconfig
configs/vf610twr_nand_defconfig
configs/vining_2000_defconfig
configs/vme8349_defconfig
configs/wandboard_defconfig
configs/woodburn_defconfig
configs/woodburn_sd_defconfig
configs/work_92105_defconfig
configs/x600_defconfig
configs/xilinx_zynqmp_ep_defconfig
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
configs/xilinx_zynqmp_zcu102_revA_defconfig
configs/xilinx_zynqmp_zcu102_revB_defconfig
configs/xpedite517x_defconfig
configs/xpedite520x_defconfig
configs/xpedite537x_defconfig
configs/xpedite550x_defconfig
configs/xpress_defconfig
configs/xpress_spl_defconfig
configs/zc5601_defconfig
drivers/net/Kconfig
drivers/net/ag7xxx.c
drivers/net/bcm-sf2-eth.h
drivers/net/phy/Kconfig
drivers/net/phy/Makefile
drivers/net/phy/broadcom.c
drivers/net/phy/fixed.c
drivers/net/phy/micrel_ksz8xxx.c [new file with mode: 0644]
drivers/net/phy/micrel_ksz90x1.c [moved from drivers/net/phy/micrel.c with 62% similarity]
drivers/net/phy/phy.c
drivers/usb/eth/r8152.c
drivers/video/Kconfig
drivers/video/Makefile
drivers/video/cfb_console.c
drivers/video/ct69000.c [deleted file]
drivers/video/l5f31188.c [deleted file]
drivers/video/rockchip/Makefile
drivers/video/rockchip/rk3288_mipi.c [new file with mode: 0644]
drivers/video/rockchip/rk3399_mipi.c [new file with mode: 0644]
drivers/video/rockchip/rk_mipi.c
drivers/video/rockchip/rk_mipi.h [new file with mode: 0644]
drivers/video/sed156x.c [deleted file]
drivers/video/sm501.c [deleted file]
include/config_phylib_all_drivers.h
include/configs/10m50_devboard.h
include/configs/3c120_devboard.h
include/configs/B4860QDS.h
include/configs/BSC9131RDB.h
include/configs/BSC9132QDS.h
include/configs/C29XPCIE.h
include/configs/MPC8349ITX.h
include/configs/MPC8536DS.h
include/configs/MPC8544DS.h
include/configs/MPC8548CDS.h
include/configs/MPC8572DS.h
include/configs/P1010RDB.h
include/configs/P1022DS.h
include/configs/P1023RDB.h
include/configs/P2041RDB.h
include/configs/T102xQDS.h
include/configs/T102xRDB.h
include/configs/T1040QDS.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240QDS.h
include/configs/T4240RDB.h
include/configs/UCP1020.h
include/configs/advantech_dms-ba16.h
include/configs/alt.h
include/configs/am335x_evm.h
include/configs/am335x_igep003x.h
include/configs/am335x_shc.h
include/configs/am335x_sl50.h
include/configs/am43xx_evm.h
include/configs/am57xx_evm.h
include/configs/ap_sh4a_4a.h
include/configs/apalis_imx6.h
include/configs/aristainetos-common.h
include/configs/aristainetos2.h
include/configs/aristainetos2b.h
include/configs/armadillo-800eva.h
include/configs/axs10x.h
include/configs/baltos.h
include/configs/bav335x.h
include/configs/bur_am335x_common.h
include/configs/cgtqmx6eval.h
include/configs/chiliboard.h
include/configs/cl-som-am57x.h
include/configs/cm_fx6.h
include/configs/cm_t335.h
include/configs/cm_t43.h
include/configs/colibri_imx6.h
include/configs/colibri_imx7.h
include/configs/colibri_vf.h
include/configs/controlcenterd.h
include/configs/corenet_ds.h
include/configs/corvus.h
include/configs/cyrus.h
include/configs/devkit3250.h
include/configs/dra7xx_evm.h
include/configs/draco.h
include/configs/ecovec.h
include/configs/embestmx6boards.h
include/configs/espt.h
include/configs/etamin.h
include/configs/flea3.h
include/configs/ge_bx50v3.h
include/configs/gose.h
include/configs/imx6_logic.h
include/configs/k2g_evm.h
include/configs/km/kmp204x-common.h
include/configs/koelsch.h
include/configs/lager.h
include/configs/liteboard.h
include/configs/ls1021aiot.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/configs/ls1043aqds.h
include/configs/ls1043ardb.h
include/configs/ls1046aqds.h
include/configs/ls1046ardb.h
include/configs/ls2080aqds.h
include/configs/ls2080ardb.h
include/configs/m53evk.h
include/configs/mccmon6.h
include/configs/microblaze-generic.h
include/configs/mvebu_armada-37xx.h
include/configs/mvebu_armada-8k.h
include/configs/mx6cuboxi.h
include/configs/mx6sabre_common.h
include/configs/mx6slevk.h
include/configs/mx6sxsabreauto.h
include/configs/mx6sxsabresd.h
include/configs/mx6ul_14x14_evk.h
include/configs/mx7dsabresd.h
include/configs/nitrogen6x.h
include/configs/novena.h
include/configs/nsa310s.h
include/configs/ot1200.h
include/configs/p1_p2_rdb_pc.h
include/configs/p1_twr.h
include/configs/pcm051.h
include/configs/pcm052.h
include/configs/pcm058.h
include/configs/pengwyn.h
include/configs/pepper.h
include/configs/pico-imx6ul.h
include/configs/pico-imx7d.h
include/configs/platinum.h
include/configs/platinum_titanium.h
include/configs/porter.h
include/configs/r0p7734.h
include/configs/rastaban.h
include/configs/s32v234evb.h
include/configs/salvator-x.h
include/configs/sama5d3xek.h
include/configs/sbc8548.h
include/configs/sc_sps_1.h
include/configs/secomx6quq7.h
include/configs/sh7752evb.h
include/configs/sh7753evb.h
include/configs/sh7757lcr.h
include/configs/sh7763rdp.h
include/configs/siemens-am33x-common.h
include/configs/silk.h
include/configs/smartweb.h
include/configs/snapper9g45.h
include/configs/socfpga_arria10_socdk.h
include/configs/socfpga_arria5_socdk.h
include/configs/socfpga_common.h
include/configs/socfpga_cyclone5_socdk.h
include/configs/socfpga_de0_nano_soc.h
include/configs/socfpga_de10_nano.h
include/configs/socfpga_de1_soc.h
include/configs/socfpga_is1.h
include/configs/socfpga_sockit.h
include/configs/socfpga_socrates.h
include/configs/socfpga_vining_fpga.h
include/configs/socrates.h
include/configs/spear-common.h
include/configs/stout.h
include/configs/stv0991.h
include/configs/sunxi-common.h
include/configs/t4qds.h
include/configs/taurus.h
include/configs/tb100.h
include/configs/tbs2910.h
include/configs/thuban.h
include/configs/ti814x_evm.h
include/configs/ti_armv7_keystone2.h
include/configs/titanium.h
include/configs/tplink_wdr4300.h
include/configs/tqma6.h
include/configs/tqma6_mba6.h
include/configs/ts4800.h
include/configs/udoo.h
include/configs/udoo_neo.h
include/configs/vf610twr.h
include/configs/vining_2000.h
include/configs/wandboard.h
include/configs/woodburn_common.h
include/configs/work_92105.h
include/configs/x600.h
include/configs/xilinx_zynqmp.h
include/configs/xpedite517x.h
include/configs/xpedite520x.h
include/configs/xpedite537x.h
include/configs/xpedite550x.h
include/configs/xpress.h
include/configs/zc5601.h
include/net.h
include/phy.h
include/sed156x.h [deleted file]
include/sm501.h [deleted file]
net/bootp.h
net/dns.h
net/net.c
net/net_rand.h
net/nfs.h
net/sntp.h
net/tftp.c
scripts/config_whitelist.txt

diff --git a/README b/README
index 1edf3db..3735916 100644 (file)
--- a/README
+++ b/README
@@ -1627,11 +1627,6 @@ The following options need to be configured:
 
                The clock frequency of the MII bus
 
-               CONFIG_PHY_GIGE
-
-               If this option is set, support for speed/duplex
-               detection of gigabit PHY is included.
-
                CONFIG_PHY_RESET_DELAY
 
                Some PHY like Intel LXT971A need extra delay after
index 7f6ab4a..9cfeede 100644 (file)
@@ -523,6 +523,9 @@ config TARGET_BCMCYGNUS
        imply CMD_HASH
        imply FAT_WRITE
        imply HASH_VERIFY
+       imply NETDEVICES
+       imply BCM_SF2_ETH
+       imply BCM_SF2_ETH_GMAC
 
 config TARGET_BCMNSP
        bool "Support bcmnsp"
index af7f3bf..92b1c5e 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Broadcom Corporation.
+ * Copyright 2014-2017 Broadcom.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 #define CONFIG_SYS_NS16550_COM3                0x18023000
 
 /* Ethernet */
-#define CONFIG_BCM_SF2_ETH
-#define CONFIG_BCM_SF2_ETH_GMAC
-
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_BROADCOM
 #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
 
index 1b35e08..2dc9b1d 100644 (file)
 #define CONFIG_MII             /* expose smi ove miiphy interface */
 #if !defined(CONFIG_ARMADA_375)
 #define CONFIG_MVNETA          /* Enable Marvell Gbe Controller Driver */
-#define CONFIG_PHYLIB
 #endif
 #define CONFIG_ENV_OVERWRITE   /* ethaddr can be reprogrammed */
-#define CONFIG_PHY_GIGE                /* GbE speed/duplex detect */
 #define CONFIG_ARP_TIMEOUT     200
 #define CONFIG_NET_RETRY_COUNT 50
 #endif /* CONFIG_CMD_NET */
index eaa23d2..6aec815 100644 (file)
 /* The TSEC driver uses the PHYLIB infrastructure */
 #ifndef CONFIG_PHYLIB
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_PHYLIB
-
 #include <config_phylib_all_drivers.h>
 #endif /* TSEC_ENET */
 #endif /* !CONFIG_PHYLIB */
 
 /* The FMAN driver uses the PHYLIB infrastructure */
-#if defined(CONFIG_FMAN_ENET)
-#define CONFIG_PHYLIB
-#endif
 
 /* All PPC boards must swap IDE bytes */
 #define CONFIG_IDE_SWAP_IO
index df8b6c9..5e91d3a 100644 (file)
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -42,7 +42,7 @@ U_BOOT_CMD(
 );
 
 #ifdef CONFIG_CMD_TFTPPUT
-int do_tftpput(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_tftpput(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        return netboot_common(TFTPPUT, cmdtp, argc, argv);
 }
index 465edc5..7cb9ffb 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_ALTERA_QSPI=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ALTERA_TSE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index 601b0b5..df744ea 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ALTERA_TSE=y
 CONFIG_DM_SERIAL=y
 CONFIG_ALTERA_JTAG_UART=y
index e078add..16c34c0 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index eb21541..e8fa408 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 074e94d..8389bb1 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d90be54..4e30b98 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e679d0a..43bb4e5 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e66c7d0..925ff78 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 21bcae4..f21c6ec 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_FSL_CAAM=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 2452337..3f2876c 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 12a242f..6e8ab27 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_FSL_CAAM=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6c82346..577e3ae 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_FSL_CAAM=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 073317b..7f6186d 100644 (file)
@@ -25,6 +25,7 @@ CONFIG_FSL_CAAM=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 49026c1..f12677a 100644 (file)
@@ -25,6 +25,7 @@ CONFIG_FSL_CAAM=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index aea470c..78f3320 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a40e9bb..801468c 100644 (file)
@@ -27,7 +27,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 51e1994..f0c2c90 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 0e5a1c4..08554ca 100644 (file)
@@ -27,7 +27,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index cea3cb4..c600409 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index eeb28b1..9b64e7c 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c5642ab..e12dce4 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 98d92e7..ffd88ab 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e8c5482..4e5d8de 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d6cffb2..039973e 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 3afb011..8a5cb5d 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ec389d0..5c8d26c 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c5d17bc..0c620f4 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index b8e90a2..8a647a9 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ba0772c..07b70ca 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 29e4f7b..340ccad 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index dcfbbf6..c1b4998 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 99e2b33..13982c7 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 26544f4..79dbde7 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 96e5b34..2f24800 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index cd6bffd..7daf125 100644 (file)
@@ -21,7 +21,9 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 149fa4e..239a838 100644 (file)
@@ -24,6 +24,9 @@ CONFIG_CMD_DATE=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
index 23dbaee..ffdaa07 100644 (file)
@@ -24,6 +24,9 @@ CONFIG_CMD_DATE=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
index 10ff9cf..ce131c1 100644 (file)
@@ -17,5 +17,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 13a4fde..c7f6ec2 100644 (file)
@@ -18,5 +18,6 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index c1b5c85..c31e795 100644 (file)
@@ -18,5 +18,6 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index e416ee3..66bc67c 100644 (file)
@@ -21,5 +21,6 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 787b23a..e2491c9 100644 (file)
@@ -21,5 +21,6 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 74d886c..b40b2c1 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
index 8b27b27..aaa4bae 100644 (file)
@@ -13,6 +13,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index fc672be..862013a 100644 (file)
@@ -15,5 +15,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index c7f093e..4f76b88 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
index e508b3d..9b9d5f9 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
index eb3b735..9ad9e0d 100644 (file)
@@ -17,6 +17,7 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
index b32fb38..de46fe1 100644 (file)
@@ -16,6 +16,7 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 0373e0e..5ca6f37 100644 (file)
@@ -17,6 +17,7 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
index 1d40e2f..6940f34 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_SYS_FSL_DDR2=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8fda7bc..a6eb30e 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_SYS_FSL_DDR2=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index bdbb8c0..a5aa82e 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_SYS_FSL_DDR2=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 65a1f9e..03498a8 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_SYS_FSL_DDR2=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 2d4647a..e0cd935 100644 (file)
@@ -13,5 +13,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index cbf9eff..ef3c803 100644 (file)
@@ -14,5 +14,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 8142cf2..3508e0a 100644 (file)
@@ -19,7 +19,9 @@ CONFIG_CMD_EXT2=y
 CONFIG_SCSI=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_RTL8139=y
 CONFIG_SYS_NS16550=y
index fd3b8d6..e5db130 100644 (file)
@@ -14,7 +14,9 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index e090a5b..bab2505 100644 (file)
@@ -13,7 +13,9 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 4ea1b9d..d8daabc 100644 (file)
@@ -13,7 +13,9 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 8410fa4..cb37d9a 100644 (file)
@@ -13,5 +13,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 3ac6035..a74024c 100644 (file)
@@ -14,5 +14,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index b5fb4c2..4924bef 100644 (file)
@@ -15,5 +15,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 521badc..673d7ce 100644 (file)
@@ -19,7 +19,9 @@ CONFIG_CMD_EXT2=y
 CONFIG_SYS_FSL_DDR2=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
index 2821c8c..c5599c9 100644 (file)
@@ -18,7 +18,9 @@ CONFIG_CMD_EXT2=y
 CONFIG_SYS_FSL_DDR2=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
index 074c333..bf7179f 100644 (file)
@@ -16,6 +16,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
index aa2a464..11b2ed2 100644 (file)
@@ -16,6 +16,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
index 28029b8..95b39f0 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 75f62d9..92840f5 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f9109e4..794cc4c 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index cc71f04..3ef45a4 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1ff9d69..9818e7c 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a5cec4b..152d885 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a76a1ab..b1e8f02 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d720c22..070acd7 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 744ebbd..6d77682 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d473d6d..42266b9 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 24d7139..4a403b9 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 4fe4186..2c9d661 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index aa94431..223f15a 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1b8ba8f..eba9cae 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 137a9ff..140e6bb 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c22bd10..3ac7bde 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d1c728b..20bbac4 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6c7a3b1..528be16 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6bf7344..ba83da3 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 2c1f471..5298c13 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index b9dff3e..1708e2e 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 765e460..4a3f654 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 27fa96e..1fbd23a 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 76f28fd..f29114e 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index b2dc667..2c15595 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e671aa6..39cc555 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a0c9a71..530256e 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e7d9ed4..2c0b2ff 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a7d829d..d037985 100644 (file)
@@ -31,7 +31,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 93a9ed4..8cb4b5a 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 16ed38c..63bb57f 100644 (file)
@@ -30,7 +30,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 65b1e9f..6a1777a 100644 (file)
@@ -21,7 +21,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5872353..50aa9d2 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a8d8152..a340ab2 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 13ecc32..47582a3 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 32f1025..85a3b2d 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 4ae1180..fd4e41a 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1ee299f..3dbbe13 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d97be67..a4f5fda 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5cbd2fc..4861649 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d08904b..2ca1233 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index bdbc5d6..29f15c5 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f8a1a58..1e6be96 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5894dd1..fc4ef85 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 4e871ce..454d89b 100644 (file)
@@ -31,7 +31,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8abf174..17eca57 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5992819..d937e8c 100644 (file)
@@ -30,7 +30,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 026a39d..c1e74a3 100644 (file)
@@ -21,7 +21,9 @@ CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c579499..a79b686 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f5e620b..25010b8 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 581a46b..1c55714 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d8138f2..3f15d8e 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 378fd8e..48f8c90 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 9bd5df5..fca77ab 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 306d610..ca4cb28 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 48565f1..ca49738 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 964e5ae..0965cd7 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8e8374c..b029bad 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1773550..9e88f29 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ce33485..c534d38 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 9bf8db1..1a1822f 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8bcdc73..a92a5f1 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5862c61..66bd93a 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6c8fb0c..52f4c8d 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 4819a69..84e89a1 100644 (file)
@@ -21,7 +21,9 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
index 08d0f77..aa7b453 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6a01a85..e007604 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index dee57c4..ed4b855 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 3f7604c..bdb61d3 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f0696d5..459030a 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 08b14fc..4a2ba1a 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 747a8be..28ba22a 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e1af126..45d3448 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index cd240c3..fe12f10 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 044e825..66d306f 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c342fc4..e470f31 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8e52781..d72a8f0 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 032c836..b2e7c8c 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a51b631..595c472 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 26a583a..e1ce591 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e446515..d3069e1 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c596b68..5bae5ee 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 0430762..a16ef43 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8f1f308..5e0ee66 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 7419eae..4ff07ab 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1bc514c..bd70cc5 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 76ee4d0..13a889f 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8b5e4de..1edd5af 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_FAT=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 7324279..f12e388 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1aad2a6..1a43f20 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 13d4ddf..7c2acb9 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d9d8b4f..1cffa32 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c5766ce..6c7a0c3 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 657abb3..961cce8 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 3ea5f5c..039da15 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_FAT=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index b248e98..ea89d9c 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index c7aad06..9922bbc 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 81b14dd..1083f8a 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e72def9..5e9bf97 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5f79200..2bf1299 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_FAT=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d3addc8..71a6993 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index edff3c2..7af118b 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 7f5bcbd..0c7aa23 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 2586891..71f2c89 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 2f4772c..91cfc65 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6993e73..f3f5cb8 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 9ac5931..c2d7313 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_CMD_FAT=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ca7a8c9..9499521 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 71538ad..183344b 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 37a5bbe..00d508e 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 643bc8d..86ea931 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index de7881e..4a80242 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 34df3af..5793781 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8253e0a..13bfaf8 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index eca89cf..805d397 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 60477d3..0b4d256 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 92adbe8..0c33a3d 100644 (file)
@@ -27,7 +27,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d3d3941..0cb278d 100644 (file)
@@ -39,7 +39,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 22dd2dc..da59c26 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 19f1000..e87b085 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6294ce3..454dbf6 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
index 82f4a40..d18068d 100644 (file)
@@ -42,7 +42,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 3d6fc50..729a49b 100644 (file)
@@ -42,7 +42,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f1d0488..402a969 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 04efc8d..c669309 100644 (file)
@@ -43,7 +43,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ac7b316..f7af9d5 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e76d88a..e06fcbd 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ecf54d8..2b1b9a0 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 968d8a8..b0d637c 100644 (file)
@@ -29,7 +29,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index b481c8c..e3d4b06 100644 (file)
@@ -39,7 +39,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 2cfcaed..b2046ee 100644 (file)
@@ -28,7 +28,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 010bc6c..b665786 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f0cb20b..542216d 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 4758257..f761bec 100644 (file)
@@ -27,7 +27,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8e7dd1d..2b45a42 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 961b33b..6dcfe7a 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1e3d0b1..f0c0a54 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a75ee03..15f0a83 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 7521e72..643e1db 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 28277a2..21d060c 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f4bef13..9e0562f 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f16834b..72015c3 100644 (file)
@@ -28,7 +28,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f09f7b4..b52f947 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 395a6cd..6ad61cb 100644 (file)
@@ -27,7 +27,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index f83f43e..c02fc20 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 45949fd..7ef3af0 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 4a94e30..da143fb 100644 (file)
@@ -29,7 +29,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6e6b6a1..52c5d71 100644 (file)
@@ -39,7 +39,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8daff4d..47a614f 100644 (file)
@@ -28,7 +28,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 513bfd3..9a0fa33 100644 (file)
@@ -43,7 +43,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 0606e0c..adae1bf 100644 (file)
@@ -40,7 +40,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 70ab39b..de3da63 100644 (file)
@@ -40,7 +40,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ad88f27..4784015 100644 (file)
@@ -41,7 +41,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5c3cfc7..4c9b816 100644 (file)
@@ -30,7 +30,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index cdea785..c5ad1b8 100644 (file)
@@ -27,7 +27,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8ce7440..8e1e8be 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index d39399d..b429efb 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a6cda56..9540e50 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e1e8c72..6c24de3 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 406715a..46ad719 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 3044236..86cd734 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 89def59..d48a970 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a97a28f..b985cce 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 122f43b..800e938 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 5cc601d..dc91bbc 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 63b2098..6e011f9 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 32feff1..8830228 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_FAT=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 8822537..2673e0d 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e1e0ef4..0e94c70 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 980d1e8..e591d37 100644 (file)
@@ -35,7 +35,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index fc760db..edcb29b 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a49aff5..a4b8870 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6fb0910..d1905fe 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 605076e..885ec05 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a5b0d41..5337f1a 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index ea79cc2..5060921 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 6caffd8..cecff55 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a1c60b2..4c09546 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index fe35461..68bb989 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index a7d681d..be4b1d8 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 3219b0c..3524d0b 100644 (file)
@@ -23,7 +23,9 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index b198ccf..ce1ad88 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_CMD_FAT=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 9632076..db6dfc9 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 98d6c76..1390ce8 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 1c0aa91..dad2001 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e31caca..9d4ea14 100644 (file)
@@ -19,5 +19,6 @@ CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index e48b9bc..e32a060 100644 (file)
@@ -22,7 +22,9 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 686137d..68ef59a 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index be00296..6999db3 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 109b1ab..a220003 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_BAUDRATE=38400
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
index 705d472..180268e 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_ISO_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index ae2adb7..2c153a8 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_DFU_RAM=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 3ff6220..addfd09 100644 (file)
@@ -38,7 +38,9 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
index b68857d..82d5a97 100644 (file)
@@ -36,7 +36,9 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
index ebf155b..3fb220a 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 73354f4..9f7247b 100644 (file)
@@ -26,6 +26,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 35aaeff..607ac07 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_DFU_RAM=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index efc34ff..55c13da 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_DFU_RAM=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 2b35c99..59306ba 100644 (file)
@@ -39,7 +39,9 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
index 2c62887..2ecd1d9 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT=y
index 9b4802e..9361824 100644 (file)
@@ -39,6 +39,7 @@ CONFIG_DOS_PARTITION=y
 CONFIG_ISO_PARTITION=y
 # CONFIG_SPL_ISO_PARTITION is not set
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
index 637306d..160e369 100644 (file)
@@ -39,6 +39,7 @@ CONFIG_DOS_PARTITION=y
 CONFIG_ISO_PARTITION=y
 # CONFIG_SPL_ISO_PARTITION is not set
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
index 5c0c912..9eac46d 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_DOS_PARTITION=y
 CONFIG_ISO_PARTITION=y
 # CONFIG_SPL_ISO_PARTITION is not set
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
index e5903de..a6c6c57 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_DOS_PARTITION=y
 CONFIG_ISO_PARTITION=y
 # CONFIG_SPL_ISO_PARTITION is not set
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
index c8f7632..2be4646 100644 (file)
@@ -39,6 +39,7 @@ CONFIG_DOS_PARTITION=y
 CONFIG_ISO_PARTITION=y
 # CONFIG_SPL_ISO_PARTITION is not set
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
index c8f7632..2be4646 100644 (file)
@@ -39,6 +39,7 @@ CONFIG_DOS_PARTITION=y
 CONFIG_ISO_PARTITION=y
 # CONFIG_SPL_ISO_PARTITION is not set
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
index 5d5c68e..41dd2da 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
index e99ee80..10a9b9e 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
index 7a561fd..cb6a0d3 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_DFU_SF=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
index eefad6c..0130e6b 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_DFU_SF=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
index 90c0c85..b25a3ee 100644 (file)
@@ -55,6 +55,8 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
index 6a4ae33..0a6a9cd 100644 (file)
@@ -46,6 +46,8 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
index 9cae0cb..d5ea25e 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_DM_REGULATOR=y
index 0a898de..03bac80 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
index 676fc50..91baa2b 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_DM_REGULATOR=y
index 400cfd1..48c52ad 100644 (file)
@@ -23,5 +23,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USE_PRIVATE_LIBGCC=y
index 4d88e70..38161d4 100644 (file)
@@ -42,6 +42,10 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index 5dbc960..1a55c1a 100644 (file)
@@ -35,6 +35,10 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index e216781..b02dfc7 100644 (file)
@@ -35,6 +35,10 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index 8506207..347ab4b 100644 (file)
@@ -37,6 +37,10 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
index 678988d..aea2d8e 100644 (file)
@@ -37,6 +37,10 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
index 17cc664..c069d0f 100644 (file)
@@ -37,6 +37,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
index 8b2448b..cb5e150 100644 (file)
@@ -27,5 +27,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_OF_LIBFDT=y
index b0e69e1..b99ddb9 100644 (file)
@@ -37,4 +37,5 @@ CONFIG_OF_EMBED=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_USE_TINY_PRINTF=y
index 2d29d1d..8d36371 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_DM=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index 1c4e973..2ad37ee 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_DM=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index 374d58b..2dc7d19 100644 (file)
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM28155_AP=y
-CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -16,7 +15,6 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
@@ -34,3 +32,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
 CONFIG_G_DNL_PRODUCT_NUM=0x0d02
+CONFIG_NETDEVICES=y
+CONFIG_BCM_SF2_ETH=y
+CONFIG_BCM_SF2_ETH_GMAC=y
index a32472b..8f76b09 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
index c90c0c7..d450fba 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
index 0ceb8ea..f77f50c 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
index ac50b2e..54f3acb 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
index 0ceb8ea..f77f50c 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
index 0ceb8ea..f77f50c 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
index c5d15c6..756f05f 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_DFU_RAM=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 31e077c..6f30ac5 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_DFU_RAM=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 539ed6f..63b9514 100644 (file)
@@ -33,6 +33,8 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_DM_SPI=y
index 4aded16..d0129fb 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index e128fb4..c39d27d 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_NETCONSOLE=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 1e156ca..2227830 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 3dac8a9..f46695a 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index e20e5f8..de61dd3 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_SF=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index 92816e6..5257d70 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 0d1f614..415bc38 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
index 89c0976..5f1c5ae 100644 (file)
@@ -34,6 +34,8 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_MV=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_PCI=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
index 1a6cfc6..0facb9b 100644 (file)
@@ -58,6 +58,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index 7e411a9..a88b2d8 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_LED_STATUS_BIT=64
 CONFIG_LED_STATUS_BOOT_ENABLE=y
 CONFIG_LED_STATUS_BOOT=0
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT=y
index 6f10661..19d10b7 100644 (file)
@@ -64,6 +64,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
index a23975f..21e9f17 100644 (file)
@@ -42,6 +42,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index bed38dc..e6d624a 100644 (file)
@@ -35,6 +35,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index 7aa85d4..8f069b7 100644 (file)
@@ -46,6 +46,8 @@ CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_DM_PMIC=y
index 5fac13d..810a7e3 100644 (file)
@@ -42,6 +42,8 @@ CONFIG_VYBRID_GPIO=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_DM_SPI=y
index 87d212a..d933179 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_TPM_AUTH_SESSIONS=y
index ec98183..c290e09 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_TPM_AUTH_SESSIONS=y
index 62c6546..a36ff30 100644 (file)
@@ -46,6 +46,8 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_MV=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_DEBUG_UART_SHIFT=2
index 6b89abf..cd0f993 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_CLK_AT91=y
 CONFIG_AT91_UTMI=y
 CONFIG_DFU_NAND=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 # CONFIG_SPL_DM_SERIAL is not set
 CONFIG_ATMEL_USART=y
 CONFIG_USB=y
index d54d9c3..ab64826 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_NAND_PXA3XX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_GIGE=y
 CONFIG_MVPP2=y
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
index 323871f..2d2acd4 100644 (file)
@@ -45,6 +45,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_PCI=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=200000000
index 5f072c5..dc73e29 100644 (file)
@@ -45,6 +45,8 @@ CONFIG_MMC_SDHCI_MV=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_PCI=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
index 99533b9..bcd5e77 100644 (file)
@@ -42,6 +42,8 @@ CONFIG_NAND_PXA3XX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_PCI=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
index 8b180f9..09fcdef 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
index 12c39ba..1069177 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
index dd3428e..e5efb21 100644 (file)
@@ -31,6 +31,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
index 6987c35..0c4452a 100644 (file)
@@ -60,7 +60,9 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_SPL_PHY=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
index 72c43f8..75b77fa 100644 (file)
@@ -63,7 +63,9 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_SPL_PHY=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
index fc275da..59ea331 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index bde54b6..6bccfb6 100644 (file)
@@ -35,6 +35,8 @@ CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_PCI=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
index 532b22d..d3ce6e6 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index a41704e..b3a9b43 100644 (file)
@@ -23,5 +23,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USE_PRIVATE_LIBGCC=y
index 2c7286f..d59ef1b 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 98addee..a87ffb9 100644 (file)
@@ -62,6 +62,11 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
+CONFIG_DISPLAY_ROCKCHIP_MIPI=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
index 6081411..55757d2 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
 CONFIG_DISPLAY_ROCKCHIP_MIPI=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_ERRNO_STR=y
index ae7f6a4..11cd196 100644 (file)
@@ -19,6 +19,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_EFI_LOADER is not set
index 12b768c..4427f72 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_BAUDRATE=38400
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
index c32c4a8..e8d1a84 100644 (file)
@@ -22,6 +22,7 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
index 10dbb7d..646a314 100644 (file)
@@ -24,5 +24,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 48456b2..b9751a0 100644 (file)
@@ -22,5 +22,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index b2013e1..4553efd 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_CMD_JFFS2=y
 CONFIG_CMD_UBI=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 0870ae4..526a9f3 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_SYS_I2C_MXC=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_NAND_MXS=y
+CONFIG_PHYLIB=y
 CONFIG_FEC_MXC=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
index b3763e4..d0189d2 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_TI_AEMIF=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index b8bd57c..477221c 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_TI_AEMIF=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index 1eed605..0065d34 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_ETH=y
 CONFIG_REMOTEPROC_TI_POWER=y
 CONFIG_DM_SERIAL=y
index 51c701e..98b9725 100644 (file)
@@ -27,6 +27,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_ETH=y
 CONFIG_REMOTEPROC_TI_POWER=y
 CONFIG_DM_SERIAL=y
index 59cd9ef..02e1007 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_TI_AEMIF=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index a85f029..696368f 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_TI_AEMIF=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index db45fe1..76ae9b7 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_TI_AEMIF=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index 564c5ae..854b4d2 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_DOS_PARTITION=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index 4b25ade..c01d2af 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_DOS_PARTITION=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
index e6eef3f..b8cede2 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_BAUDRATE=38400
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
index ca4f73d..5d2e99d 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_BAUDRATE=38400
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
index 2be4819..b69d519 100644 (file)
@@ -28,5 +28,6 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_OF_LIBFDT=y
index ed8681a..dee0269 100644 (file)
@@ -12,7 +12,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index b1d1fad..1b5da4b 100644 (file)
@@ -16,7 +16,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 4dfe58e..bb03f93 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index f23511f..1cf0dc0 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index f5bbd1d..69551e7 100644 (file)
@@ -48,7 +48,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 794a591..093b109 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index a11daca..5171f27 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index cac1ba4..ba3dcca 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index b776ea0..eaa6397 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index df3fe93..12d30f1 100644 (file)
@@ -46,7 +46,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index ae55f00..13ab20a 100644 (file)
@@ -48,7 +48,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index c8cb215..a7c9ae1 100644 (file)
@@ -31,7 +31,9 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 29d6ea1..02b3030 100644 (file)
@@ -31,7 +31,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index bbc73ad..24573d0 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 7fcb1e3..27e1dcf 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 8689fa7..4e99c69 100644 (file)
@@ -46,7 +46,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 8647365..9baf654 100644 (file)
@@ -44,7 +44,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index b254f3b..abdfb66 100644 (file)
@@ -48,7 +48,9 @@ CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 4ce071c..147c2ae 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 0d9cdbc..73ed2aa 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 598d6f7..1223a8e 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 5d0e0b7..c0bdb79 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 4ffd150..8d1bd11 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 445366a..2765cc6 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index af06553..a2e6aa7 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index c7077fc..216ed16 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index a551867..2639876 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index d694436..df14007 100644 (file)
@@ -41,7 +41,9 @@ CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index dd6762d..5a372a9 100644 (file)
@@ -40,7 +40,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index a96cc56..8791642 100644 (file)
@@ -41,7 +41,9 @@ CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 1b18179..ffea119 100644 (file)
@@ -40,7 +40,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 08637e2..d6cc64d 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 94d0ea9..2daff11 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 6fc5d6e..c07df3a 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_DM_SPI=y
index 802c69c..2bf7e0e 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index c47be08..321a3f4 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index f93854a..bd7525e 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index 62a9b2e..6e965eb 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y
index a315ac1..cc1046c 100644 (file)
@@ -31,7 +31,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 6d40587..bc0b294 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 1dc74de..98a88c4 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 9fdc437..ed9d445 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 16cb8f1..8b24426 100644 (file)
@@ -32,7 +32,9 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index a784d7a..aace6b4 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 0cb377a..d8d2f4a 100644 (file)
@@ -26,7 +26,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 1cae676..76e571b 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index a4b22e4..5560d1a 100644 (file)
@@ -27,7 +27,9 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 798f3bd..55fc51f 100644 (file)
@@ -34,7 +34,9 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index a3d4322..b035e57 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index fe4bb27..ad63173 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 243fcc8..dc8c847 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 21fce98..7b8718e 100644 (file)
@@ -25,7 +25,9 @@ CONFIG_DM=y
 CONFIG_SCSI=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index 4addbaf..860e9c6 100644 (file)
@@ -24,7 +24,9 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index eb9ee54..061c588 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
index 080815d..54b8d7e 100644 (file)
@@ -21,6 +21,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 81d6c92..ec4b47c 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_DEBUG_UART_SHIFT=2
index 449804b..93e582e 100644 (file)
@@ -34,6 +34,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_OF_LIBFDT=y
index 653f258..5a75292 100644 (file)
@@ -35,6 +35,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_OF_LIBFDT=y
index 3d84cf2..12dcd00 100644 (file)
@@ -36,6 +36,8 @@ CONFIG_OF_EMBED=y
 CONFIG_NETCONSOLE=y
 CONFIG_SPL_DM=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_EMACLITE=y
index 0dcdd3b..9303180 100644 (file)
@@ -13,5 +13,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index f0b196a..aa4bf2a 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ARMADA_37XX=y
index 7f4ee05..67ce751 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
 CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
index beaa1cf..66dcac9 100644 (file)
@@ -49,6 +49,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DEBUG_MVEBU_A3700_UART=y
index b533f73..92763c9 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
index f0b6679..766a12c 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DM=y
+CONFIG_PHYLIB=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 47c2b15..8731992 100644 (file)
@@ -35,6 +35,10 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index e834eb1..9832794 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_SF=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index 627bf52..e42e9c8 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_PCI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 5676da1..63867de 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_DM_MMC=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
index 9260677..e4dd692 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_DM_MMC=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
index a241ade..215bde6 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index a9e94c2..84dcbbe 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
index 2522eb7..ed38c68 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_PHYLIB=y
 CONFIG_PCI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 90daa96..93108a3 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_PCI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 87419cd..11e6018 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index c58f6dc..a512ea9 100644 (file)
@@ -39,6 +39,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index dfe55ac..a5e3b18 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_DM_MMC=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
+CONFIG_PHYLIB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_DM_PMIC=y
index c678e75..4e53cd8 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_DM_MMC=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
+CONFIG_PHYLIB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_DM_PMIC=y
index 9b8914b..3b476ca 100644 (file)
@@ -33,6 +33,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index 21a8f3a..51a94f0 100644 (file)
@@ -33,6 +33,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index 5c11254..2e37a92 100644 (file)
@@ -34,6 +34,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index 33c9cdb..b432b95 100644 (file)
@@ -34,6 +34,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index 944afc5..4e39e09 100644 (file)
@@ -33,6 +33,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index e8c1968..4365744 100644 (file)
@@ -33,6 +33,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
index 23c186b..9ffffe0 100644 (file)
@@ -34,6 +34,10 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_PCI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 3ae27da..8d40e52 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 50be468..34331ca 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 6571876..3e61216 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_EFI_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index a622359..f921a9d 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_EFI_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 0307ec1..201d2ae 100644 (file)
@@ -28,5 +28,7 @@ CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
index 0be4cd2..8fa5bfb 100644 (file)
@@ -49,5 +49,9 @@ CONFIG_DM=y
 CONFIG_MTD=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
index 27b3b0b..aca3f46 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_CMD_DIAG=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 106be0d..a7e0574 100644 (file)
@@ -40,6 +40,10 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_SYS_NS16550=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT=y
index f19b2fe..19f8fc4 100644 (file)
@@ -27,6 +27,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DFU_MMC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index f011b5c..02d990b 100644 (file)
@@ -22,6 +22,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
index 0ec8480..dba4cfb 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 8e93e17..93967ed 100644 (file)
@@ -40,6 +40,10 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index e90fbf1..6fbcffa 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_BAUDRATE=38400
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
index f999561..5877f93 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index 91b3605..4389a51 100644 (file)
@@ -23,5 +23,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USE_PRIVATE_LIBGCC=y
index 1a11099..127a4ed 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 CONFIG_SH_SDHI=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_SCIF_CONSOLE=y
index 2c8e7dd..2cf54b3 100644 (file)
@@ -21,6 +21,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 CONFIG_SH_SDHI=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_SCIF_CONSOLE=y
index 600417d..a6deb7d 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index fb9e9b0..04b2653 100644 (file)
@@ -21,6 +21,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 27c14e1..fb4153c 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index a79908a..80789f0 100644 (file)
@@ -12,5 +12,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 0d43ba4..abfedbe 100644 (file)
@@ -12,5 +12,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 5dd1603..7795518 100644 (file)
@@ -11,6 +11,7 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 6348f7d..f351271 100644 (file)
@@ -17,5 +17,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index acb3092..c30a1d2 100644 (file)
@@ -17,5 +17,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 195d472..edd0309 100644 (file)
@@ -17,5 +17,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index c107213..8d9a47c 100644 (file)
@@ -17,5 +17,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 185825e..c31ee2e 100644 (file)
@@ -16,6 +16,7 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 200500f..7174e00 100644 (file)
@@ -12,5 +12,6 @@ CONFIG_CMD_PING=y
 CONFIG_DOS_PARTITION=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 4320421..44c5f51 100644 (file)
@@ -24,6 +24,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MMC_MXS=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
index f06f322..060f463 100644 (file)
@@ -23,4 +23,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_OF_LIBFDT=y
index 1247573..1449e30 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_MAC_PARTITION=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MMC=y
+CONFIG_PHYLIB=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index 68e0c5c..7ba7e0c 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_MAC_PARTITION=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MMC=y
+CONFIG_PHYLIB=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index d43c018..a1ffd2a 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_MAC_PARTITION=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MMC=y
+CONFIG_PHYLIB=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SCIF_CONSOLE=y
index 32cc565..d5348f8 100644 (file)
@@ -24,5 +24,6 @@ CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_CMD_JFFS2=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USE_PRIVATE_LIBGCC=y
index d2d20b9..f25eb9d 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_BAUDRATE=38400
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
index dd83b75..1db2acc 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_CLK=y
 CONFIG_CLK_AT91=y
 CONFIG_DFU_NAND=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
index c0cbd72..fc60f1d 100644 (file)
@@ -52,6 +52,8 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index 45bed87..e69d768 100644 (file)
@@ -52,6 +52,8 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index f56e45e..fbb8f12 100644 (file)
@@ -46,6 +46,8 @@ CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index 2e7a633..5de9c17 100644 (file)
@@ -44,6 +44,8 @@ CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index a121a07..0fe0cad 100644 (file)
@@ -45,6 +45,8 @@ CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index 9b9b929..7d3e653 100644 (file)
@@ -43,6 +43,8 @@ CONFIG_SYS_I2C_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index c7faa96..3e0469f 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
index 493048e..d8efb6f 100644 (file)
@@ -52,6 +52,8 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index a26be88..a338bbd 100644 (file)
@@ -52,6 +52,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index 8ee0498..65fbc9f 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
index 5f4c302..359c6c1 100644 (file)
@@ -67,6 +67,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
index 4c55b8f..d5294f3 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_EXT2=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 # CONFIG_USB_EHCI_HCD is not set
index 7c32b71..4814aa8 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 7e15f15..42a7434 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 28c594d..c5d4761 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index bcd6abc..035a592 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 8dbc8a6..2a2efd9 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 9a9c959..f38f8b4 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index d1955f0..6aad21c 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 8eae19a..5de447b 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index b3640a9..ed2b7b0 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index d31c283..e595e7b 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 6caf3f6..abe0e8d 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 649a5db..afecca3 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index e1874bc..ba5a247 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index cf26003..cf6b3c9 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 9e7822c..f9ab39f 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 5780678..8aae75c 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 00c9776..f12d03e 100644 (file)
@@ -19,4 +19,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 3b95008..4d348d4 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 4e83393..c923582 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index 718cfa7..ffbd401 100644 (file)
@@ -16,4 +16,5 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
index bee7401..ec2bec9 100644 (file)
@@ -24,6 +24,8 @@ CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_BAUDRATE=38400
 CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
index d293d39..68a38e0 100644 (file)
@@ -25,5 +25,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index e0040e9..3adae55 100644 (file)
@@ -25,5 +25,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 7d372ff..5d620c5 100644 (file)
@@ -25,5 +25,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 5d304b3..7bba84a 100644 (file)
@@ -25,5 +25,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_DOS_PARTITION=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 6940696..f03e659 100644 (file)
@@ -23,6 +23,7 @@ CONFIG_OF_CONTROL=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MICREL=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_CADENCE_QSPI=y
index 177b198..09cd284 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_DFU_NAND=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
index 011c876..5b3c84b 100644 (file)
@@ -15,6 +15,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index 15531e4..a6783e0 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_DM=y
+CONFIG_PHYLIB=y
 CONFIG_PCI=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
index 4d07929..375b8e9 100644 (file)
@@ -50,6 +50,8 @@ CONFIG_DM_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_PCI=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
index c523b04..07793c0 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
index d314e50..442af05 100644 (file)
@@ -32,5 +32,6 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 64ab559..85d1fab 100644 (file)
@@ -28,6 +28,10 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 3caa1d4..2469d0b 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_DATAFLASH=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_AG7XXX=y
 CONFIG_PINCTRL=y
 CONFIG_DM_SERIAL=y
index 4e918a8..50cc1fe 100644 (file)
@@ -31,6 +31,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 35b26a3..40e4987 100644 (file)
@@ -32,6 +32,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 75a8874..faa608a 100644 (file)
@@ -30,6 +30,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index e273809..a9e400b 100644 (file)
@@ -31,6 +31,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index ba5525b..09cfdcc 100644 (file)
@@ -31,6 +31,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index dac174d..8ef0bf0 100644 (file)
@@ -32,6 +32,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 8cde18b..2150537 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_LED_STATUS_BIT5=5
 CONFIG_LED_STATUS_STATE5=2
 CONFIG_LED_STATUS_CMD=y
 CONFIG_PCA9551_LED=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 41ff4d5..58156c4 100644 (file)
@@ -14,4 +14,5 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_PHYLIB=y
 CONFIG_OF_LIBFDT=y
index 2eb3d84..6012499 100644 (file)
@@ -32,6 +32,8 @@ CONFIG_MISC=y
 CONFIG_ATSHA204A=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_MV=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_DEBUG_UART_SHIFT=2
index 794e00c..0e32fb8 100644 (file)
@@ -31,5 +31,9 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
index ecc03fc..70b32b7 100644 (file)
@@ -23,4 +23,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_OF_LIBFDT=y
index 5d601d9..9a9d593 100644 (file)
@@ -14,5 +14,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index f7f10a8..5f2fefd 100644 (file)
@@ -27,5 +27,7 @@ CONFIG_VYBRID_GPIO=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
index 1f884c5..2454f32 100644 (file)
@@ -27,5 +27,7 @@ CONFIG_VYBRID_GPIO=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
index 0099cab..c54cfe3 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
 CONFIG_PCI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 244dc7e..b176993 100644 (file)
@@ -13,6 +13,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_BAUDRATE=9600
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 68916a4..fdc135b 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_SATA=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DM=y
+CONFIG_PHYLIB=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index c09f41f..5e4a73c 100644 (file)
@@ -23,3 +23,5 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
index eabe725..458e97c 100644 (file)
@@ -34,3 +34,5 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
index ba2474c..8e7f6c8 100644 (file)
@@ -31,5 +31,6 @@ CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
+CONFIG_PHYLIB=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
index d462891..98b1880 100644 (file)
@@ -36,6 +36,8 @@ CONFIG_CMD_UBI=y
 CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB=y
index d3ae3ec..44f71ac 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_NAND_ARASAN=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
index 8c4931f..dacdee3 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
index c4d8c97..14dc5ba 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
index 8d0752a..b7ed38c 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
index fc14459..072155d 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
index bc9b14e..7db5a8e 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
index aff3bf0..7b1f2b5 100644 (file)
@@ -22,5 +22,6 @@ CONFIG_CMD_IRQ=y
 CONFIG_DS4510=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 0a705f8..003a8e9 100644 (file)
@@ -23,5 +23,6 @@ CONFIG_CMD_JFFS2=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 45fe128..9d17e00 100644 (file)
@@ -24,5 +24,6 @@ CONFIG_SYS_FSL_DDR2=y
 CONFIG_DS4510=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
index 63ce8b2..af56226 100644 (file)
@@ -23,6 +23,7 @@ CONFIG_CMD_JFFS2=y
 # CONFIG_CMD_IRQ is not set
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
index 1954815..6718cd3 100644 (file)
@@ -22,6 +22,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 9991725..817a224 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_PHYLIB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
index 8b7b4a9..501898a 100644 (file)
@@ -27,4 +27,5 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
 CONFIG_OF_LIBFDT=y
index 736aab2..5ceea44 100644 (file)
@@ -47,6 +47,30 @@ config ALTERA_TSE
          Please find details on the "Triple-Speed Ethernet MegaCore Function
          Resource Center" of Altera.
 
+config BCM_SF2_ETH
+       bool "Broadcom SF2 (Starfighter2) Ethernet support"
+       select PHYLIB
+       help
+         This is an abstract framework which provides a generic interface
+         to MAC and DMA management for multiple Broadcom SoCs such as
+         Cygnus, NSP and bcm28155_ap platforms.
+
+config BCM_SF2_ETH_DEFAULT_PORT
+       int "Broadcom SF2 (Starfighter2) Ethernet default port number"
+       depends on BCM_SF2_ETH
+       default 0
+       help
+         Default port number for the Starfighter2 ethernet driver.
+
+config BCM_SF2_ETH_GMAC
+       bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support"
+       depends on BCM_SF2_ETH
+       help
+         This flag enables the ethernet support for Broadcom platforms with
+         GMAC such as Cygnus. This driver is based on the framework provided
+         by the BCM_SF2_ETH driver.
+         Say Y to any bcmcygnus based platforms.
+
 config DWC_ETH_QOS
        bool "Synopsys DWC Ethernet QOS device support"
        depends on DM_ETH
index cf60d11..00e6806 100644 (file)
@@ -26,6 +26,7 @@ enum ag7xxx_model {
        AG7XXX_MODEL_AG934X,
 };
 
+/* MAC Configuration 1 */
 #define AG7XXX_ETH_CFG1                                0x00
 #define AG7XXX_ETH_CFG1_SOFT_RST               BIT(31)
 #define AG7XXX_ETH_CFG1_RX_RST                 BIT(19)
@@ -34,6 +35,7 @@ enum ag7xxx_model {
 #define AG7XXX_ETH_CFG1_RX_EN                  BIT(2)
 #define AG7XXX_ETH_CFG1_TX_EN                  BIT(0)
 
+/* MAC Configuration 2 */
 #define AG7XXX_ETH_CFG2                                0x04
 #define AG7XXX_ETH_CFG2_IF_1000                        BIT(9)
 #define AG7XXX_ETH_CFG2_IF_10_100              BIT(8)
@@ -43,26 +45,34 @@ enum ag7xxx_model {
 #define AG7XXX_ETH_CFG2_PAD_CRC_EN             BIT(2)
 #define AG7XXX_ETH_CFG2_FDX                    BIT(0)
 
+/* MII Configuration */
 #define AG7XXX_ETH_MII_MGMT_CFG                        0x20
 #define AG7XXX_ETH_MII_MGMT_CFG_RESET          BIT(31)
 
+/* MII Command */
 #define AG7XXX_ETH_MII_MGMT_CMD                        0x24
 #define AG7XXX_ETH_MII_MGMT_CMD_READ           0x1
 
+/* MII Address */
 #define AG7XXX_ETH_MII_MGMT_ADDRESS            0x28
 #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT      8
 
+/* MII Control */
 #define AG7XXX_ETH_MII_MGMT_CTRL               0x2c
 
+/* MII Status */
 #define AG7XXX_ETH_MII_MGMT_STATUS             0x30
 
+/* MII Indicators */
 #define AG7XXX_ETH_MII_MGMT_IND                        0x34
 #define AG7XXX_ETH_MII_MGMT_IND_INVALID                BIT(2)
 #define AG7XXX_ETH_MII_MGMT_IND_BUSY           BIT(0)
 
+/* STA Address 1 & 2 */
 #define AG7XXX_ETH_ADDR1                       0x40
 #define AG7XXX_ETH_ADDR2                       0x44
 
+/* ETH Configuration 0 - 5 */
 #define AG7XXX_ETH_FIFO_CFG_0                  0x48
 #define AG7XXX_ETH_FIFO_CFG_1                  0x4c
 #define AG7XXX_ETH_FIFO_CFG_2                  0x50
@@ -70,18 +80,24 @@ enum ag7xxx_model {
 #define AG7XXX_ETH_FIFO_CFG_4                  0x58
 #define AG7XXX_ETH_FIFO_CFG_5                  0x5c
 
+/* DMA Transfer Control for Queue 0 */
 #define AG7XXX_ETH_DMA_TX_CTRL                 0x180
 #define AG7XXX_ETH_DMA_TX_CTRL_TXE             BIT(0)
 
+/* Descriptor Address for Queue 0 Tx */
 #define AG7XXX_ETH_DMA_TX_DESC                 0x184
 
+/* DMA Tx Status */
 #define AG7XXX_ETH_DMA_TX_STATUS               0x188
 
+/* Rx Control */
 #define AG7XXX_ETH_DMA_RX_CTRL                 0x18c
 #define AG7XXX_ETH_DMA_RX_CTRL_RXE             BIT(0)
 
+/* Pointer to Rx Descriptor */
 #define AG7XXX_ETH_DMA_RX_DESC                 0x190
 
+/* Rx Status */
 #define AG7XXX_ETH_DMA_RX_STATUS               0x194
 
 /* Custom register at 0x18070000 */
@@ -269,18 +285,33 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
        return 0;
 }
 
-static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
+static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
 {
        u32 data;
+       unsigned long start;
+       int ret;
+       /* No idea if this is long enough or too long */
+       int timeout_ms = 1000;
 
        /* Dummy read followed by PHY read/write command. */
-       ag7xxx_switch_reg_read(bus, 0x98, &data);
+       ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
+       if (ret < 0)
+               return ret;
        data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
-       ag7xxx_switch_reg_write(bus, 0x98, data);
+       ret = ag7xxx_switch_reg_write(bus, 0x98, data);
+       if (ret < 0)
+               return ret;
+
+       start = get_timer(0);
 
        /* Wait for operation to finish */
        do {
-               ag7xxx_switch_reg_read(bus, 0x98, &data);
+               ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
+               if (ret < 0)
+                       return ret;
+
+               if (get_timer(start) > timeout_ms)
+                       return -ETIMEDOUT;
        } while (data & BIT(31));
 
        return data & 0xffff;
@@ -294,7 +325,11 @@ static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
                             u16 val)
 {
-       ag7xxx_mdio_rw(bus, addr, reg, val);
+       int ret;
+
+       ret = ag7xxx_mdio_rw(bus, addr, reg, val);
+       if (ret < 0)
+               return ret;
        return 0;
 }
 
index c4e2e01..efeff15 100644 (file)
@@ -20,8 +20,6 @@
 /* Support 2 Ethernet ports now */
 #define BCM_ETH_MAX_PORT_NUM   2
 
-#define CONFIG_BCM_SF2_ETH_DEFAULT_PORT        0
-
 enum {
        MAC_DMA_TX = 1,
        MAC_DMA_RX = 2
index 0230852..4d02d8b 100644 (file)
@@ -67,38 +67,40 @@ config PHY_MICREL
 if PHY_MICREL
 
 config PHY_MICREL_KSZ9021
-       bool "Micrel KSZ9021 family support"
+       bool
        select PHY_GIGE
-       help
-         Enable support for the Micrel KSZ9021 GbE PHY family.  If
-         enabled, the extended register read/write for KSZ9021 PHYs
-         is supported through the 'mdio' command and any RGMII signal
-         delays configured in the device tree will be applied to the
-         PHY during initialisation.
-
-         Note that the KSZ9021 uses the same part number os the
-         KSZ8921BL, so enabling this option disables support for the
-         KSZ8721BL.
+       select PHY_MICREL_KSZ90X1
 
 config PHY_MICREL_KSZ9031
-       bool "Micrel KSZ9031 family support"
+       bool
+       select PHY_GIGE
+       select PHY_MICREL_KSZ90X1
+
+config PHY_MICREL_KSZ90X1
+       bool "Micrel KSZ90x1 family support"
        select PHY_GIGE
        help
-         Enable support for the Micrel KSZ9031 GbE PHY family.  If
-         enabled, the extended register read/write for KSZ9021 PHYs
+         Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
+         enabled, the extended register read/write for KSZ90x1 PHYs
          is supported through the 'mdio' command and any RGMII signal
          delays configured in the device tree will be applied to the
-         PHY during initialisatioin.
+         PHY during initialization.
 
-endif # PHY_MICREL
+         This should not be enabled at the same time with PHY_MICREL_KSZ8XXX
+         as the KSZ9021 and KS8721 share the same ID.
 
-config PHY_MICREL_KSZ9021
-       bool "Micrel KSZ9021 Ethernet PHYs support"
-       depends on PHY_MICREL
+config PHY_MICREL_KSZ8XXX
+       bool "Micrel KSZ8xxx family support"
+       default y if !PHY_MICREL_KSZ90X1
        help
-          KSZ9021 is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T)
-         Ethernet Physical Layer Transceiver for transmission and reception of data over
-         standard CAT-5 unshielded twisted pair (UTP) cable.
+         Enable support for the 8000 series GbE PHYs manufactured by Micrel
+         (now a part of Microchip). This includes drivers for the KSZ804,
+         KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
+
+         This should not be enabled at the same time with PHY_MICREL_KSZ90X1
+         as the KSZ9021 and KS8721 share the same ID.
+
+endif # PHY_MICREL
 
 config PHY_MSCC
        bool "Microsemi Corp Ethernet PHYs support"
index 88c00a5..54f32f6 100644 (file)
@@ -19,7 +19,8 @@ obj-$(CONFIG_PHY_DAVICOM) += davicom.o
 obj-$(CONFIG_PHY_ET1011C) += et1011c.o
 obj-$(CONFIG_PHY_LXT) += lxt.o
 obj-$(CONFIG_PHY_MARVELL) += marvell.o
-obj-$(CONFIG_PHY_MICREL) += micrel.o
+obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
+obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
 obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
 obj-$(CONFIG_PHY_REALTEK) += realtek.o
 obj-$(CONFIG_PHY_SMSC) += smsc.o
index 9871cc3..e4afa90 100644 (file)
 #define MIIM_BCM54XX_EXP_SEL_SSD       0x0e00  /* Secondary SerDes select */
 #define MIIM_BCM54XX_EXP_SEL_ER                0x0f00  /* Expansion register select */
 
+#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC  0x0007
+#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800
+
+#define MIIM_BCM_CHANNEL_WIDTH    0x2000
+
+static void bcm_phy_write_misc(struct phy_device *phydev,
+                              u16 reg, u16 chl, u16 value)
+{
+       int reg_val;
+
+       phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
+                 MIIM_BCM_AUXCNTL_SHDWSEL_MISC);
+
+       reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL);
+       reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN;
+       phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val);
+
+       reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg;
+       phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val);
+
+       phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value);
+}
+
 /* Broadcom BCM5461S */
 static int bcm5461_config(struct phy_device *phydev)
 {
@@ -152,11 +175,50 @@ static int bcm_cygnus_startup(struct phy_device *phydev)
        return genphy_parse_link(phydev);
 }
 
+static void bcm_cygnus_afe(struct phy_device *phydev)
+{
+       /* ensures smdspclk is enabled */
+       phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x0c30);
+
+       /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
+       bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
+
+       /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode for all modes*/
+       bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
+
+       /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
+       bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
+
+       /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
+       bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
+
+       /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
+       bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
+
+       /* Adjust bias current trim to overcome digital offSet */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02);
+
+       /* make rcal=100, since rdb default is 000 */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
+
+       /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
+
+       /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0000);
+}
+
 static int bcm_cygnus_config(struct phy_device *phydev)
 {
        genphy_config_aneg(phydev);
-
        phy_reset(phydev);
+       /* AFE settings for PHY stability */
+       bcm_cygnus_afe(phydev);
+       /* Forcing aneg after applying the AFE settings */
+       genphy_restart_aneg(phydev);
 
        return 0;
 }
index df82356..e8e9099 100644 (file)
@@ -34,7 +34,6 @@ int fixedphy_probe(struct phy_device *phydev)
        memset(priv, 0, sizeof(*priv));
 
        phydev->priv = priv;
-       phydev->addr = 0;
 
        priv->link_speed = val;
        priv->duplex = fdtdec_get_bool(gd->fdt_blob, ofnode, "full-duplex");
diff --git a/drivers/net/phy/micrel_ksz8xxx.c b/drivers/net/phy/micrel_ksz8xxx.c
new file mode 100644 (file)
index 0000000..ec628bb
--- /dev/null
@@ -0,0 +1,200 @@
+/*
+ * Micrel PHY drivers
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * author Andy Fleming
+ * (C) 2012 NetModule AG, David Andrey, added KSZ9031
+ */
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <micrel.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct phy_driver KSZ804_driver = {
+       .name = "Micrel KSZ804",
+       .uid = 0x221510,
+       .mask = 0xfffff0,
+       .features = PHY_BASIC_FEATURES,
+       .config = &genphy_config,
+       .startup = &genphy_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+#define MII_KSZPHY_OMSO                0x16
+#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
+
+static int ksz_genconfig_bcastoff(struct phy_device *phydev)
+{
+       int ret;
+
+       ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
+       if (ret < 0)
+               return ret;
+
+       ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
+                       ret | KSZPHY_OMSO_B_CAST_OFF);
+       if (ret < 0)
+               return ret;
+
+       return genphy_config(phydev);
+}
+
+static struct phy_driver KSZ8031_driver = {
+       .name = "Micrel KSZ8021/KSZ8031",
+       .uid = 0x221550,
+       .mask = 0xfffff0,
+       .features = PHY_BASIC_FEATURES,
+       .config = &ksz_genconfig_bcastoff,
+       .startup = &genphy_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+/**
+ * KSZ8051
+ */
+#define MII_KSZ8051_PHY_OMSO                   0x16
+#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON      (1 << 5)
+
+static int ksz8051_config(struct phy_device *phydev)
+{
+       unsigned val;
+
+       /* Disable NAND-tree */
+       val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
+       val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
+       phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
+
+       return genphy_config(phydev);
+}
+
+static struct phy_driver KSZ8051_driver = {
+       .name = "Micrel KSZ8051",
+       .uid = 0x221550,
+       .mask = 0xfffff0,
+       .features = PHY_BASIC_FEATURES,
+       .config = &ksz8051_config,
+       .startup = &genphy_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver KSZ8081_driver = {
+       .name = "Micrel KSZ8081",
+       .uid = 0x221560,
+       .mask = 0xfffff0,
+       .features = PHY_BASIC_FEATURES,
+       .config = &ksz_genconfig_bcastoff,
+       .startup = &genphy_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+/**
+ * KSZ8895
+ */
+
+static unsigned short smireg_to_phy(unsigned short reg)
+{
+       return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
+}
+
+static unsigned short smireg_to_reg(unsigned short reg)
+{
+       return reg & 0x1F;
+}
+
+static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
+{
+       phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
+                                               smireg_to_reg(smireg), val);
+}
+
+#if 0
+static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
+{
+       return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
+                                       MDIO_DEVAD_NONE, smireg_to_reg(smireg));
+}
+#endif
+
+int ksz8895_config(struct phy_device *phydev)
+{
+       /* we are connected directly to the switch without
+        * dedicated PHY. SCONF1 == 001 */
+       phydev->link = 1;
+       phydev->duplex = DUPLEX_FULL;
+       phydev->speed = SPEED_100;
+
+       /* Force the switch to start */
+       ksz8895_write_smireg(phydev, 1, 1);
+
+       return 0;
+}
+
+static int ksz8895_startup(struct phy_device *phydev)
+{
+       return 0;
+}
+
+static struct phy_driver ksz8895_driver = {
+       .name = "Micrel KSZ8895/KSZ8864",
+       .uid  = 0x221450,
+       .mask = 0xffffe1,
+       .features = PHY_BASIC_FEATURES,
+       .config   = &ksz8895_config,
+       .startup  = &ksz8895_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+/* Micrel used the exact same part number for the KSZ9021. */
+static struct phy_driver KS8721_driver = {
+       .name = "Micrel KS8721BL",
+       .uid = 0x221610,
+       .mask = 0xfffff0,
+       .features = PHY_BASIC_FEATURES,
+       .config = &genphy_config,
+       .startup = &genphy_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+int ksz886x_config(struct phy_device *phydev)
+{
+       /* we are connected directly to the switch without
+        * dedicated PHY. */
+       phydev->link = 1;
+       phydev->duplex = DUPLEX_FULL;
+       phydev->speed = SPEED_100;
+       return 0;
+}
+
+static int ksz886x_startup(struct phy_device *phydev)
+{
+       return 0;
+}
+
+static struct phy_driver ksz886x_driver = {
+       .name = "Micrel KSZ886x Switch",
+       .uid  = 0x00221430,
+       .mask = 0xfffff0,
+       .features = PHY_BASIC_FEATURES,
+       .config = &ksz886x_config,
+       .startup = &ksz886x_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+int phy_micrel_ksz8xxx_init(void)
+{
+       phy_register(&KSZ804_driver);
+       phy_register(&KSZ8031_driver);
+       phy_register(&KSZ8051_driver);
+       phy_register(&KSZ8081_driver);
+       phy_register(&KS8721_driver);
+       phy_register(&ksz8895_driver);
+       phy_register(&ksz886x_driver);
+       return 0;
+}
similarity index 62%
rename from drivers/net/phy/micrel.c
rename to drivers/net/phy/micrel_ksz90x1.c
index 0e4a4eb..20f8a55 100644 (file)
@@ -6,6 +6,8 @@
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
  * author Andy Fleming
  * (C) 2012 NetModule AG, David Andrey, added KSZ9031
+ * (C) Copyright 2017 Adaptrum, Inc.
+ * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
  */
 #include <config.h>
 #include <common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct phy_driver KSZ804_driver = {
-       .name = "Micrel KSZ804",
-       .uid = 0x221510,
-       .mask = 0xfffff0,
-       .features = PHY_BASIC_FEATURES,
-       .config = &genphy_config,
-       .startup = &genphy_startup,
-       .shutdown = &genphy_shutdown,
-};
-
-#define MII_KSZPHY_OMSO                0x16
-#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
-
-static int ksz_genconfig_bcastoff(struct phy_device *phydev)
-{
-       int ret;
-
-       ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
-       if (ret < 0)
-               return ret;
-
-       ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
-                       ret | KSZPHY_OMSO_B_CAST_OFF);
-       if (ret < 0)
-               return ret;
-
-       return genphy_config(phydev);
-}
-
-static struct phy_driver KSZ8031_driver = {
-       .name = "Micrel KSZ8021/KSZ8031",
-       .uid = 0x221550,
-       .mask = 0xfffff0,
-       .features = PHY_BASIC_FEATURES,
-       .config = &ksz_genconfig_bcastoff,
-       .startup = &genphy_startup,
-       .shutdown = &genphy_shutdown,
-};
-
-/**
- * KSZ8051
- */
-#define MII_KSZ8051_PHY_OMSO                   0x16
-#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON      (1 << 5)
-
-static int ksz8051_config(struct phy_device *phydev)
-{
-       unsigned val;
-
-       /* Disable NAND-tree */
-       val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
-       val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
-       phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
-
-       return genphy_config(phydev);
-}
-
-static struct phy_driver KSZ8051_driver = {
-       .name = "Micrel KSZ8051",
-       .uid = 0x221550,
-       .mask = 0xfffff0,
-       .features = PHY_BASIC_FEATURES,
-       .config = &ksz8051_config,
-       .startup = &genphy_startup,
-       .shutdown = &genphy_shutdown,
-};
-
-static struct phy_driver KSZ8081_driver = {
-       .name = "Micrel KSZ8081",
-       .uid = 0x221560,
-       .mask = 0xfffff0,
-       .features = PHY_BASIC_FEATURES,
-       .config = &ksz_genconfig_bcastoff,
-       .startup = &genphy_startup,
-       .shutdown = &genphy_shutdown,
-};
-
-/**
- * KSZ8895
- */
-
-static unsigned short smireg_to_phy(unsigned short reg)
-{
-       return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
-}
-
-static unsigned short smireg_to_reg(unsigned short reg)
-{
-       return reg & 0x1F;
-}
-
-static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
-{
-       phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
-                                               smireg_to_reg(smireg), val);
-}
-
-#if 0
-static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
-{
-       return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
-                                       MDIO_DEVAD_NONE, smireg_to_reg(smireg));
-}
-#endif
-
-int ksz8895_config(struct phy_device *phydev)
-{
-       /* we are connected directly to the switch without
-        * dedicated PHY. SCONF1 == 001 */
-       phydev->link = 1;
-       phydev->duplex = DUPLEX_FULL;
-       phydev->speed = SPEED_100;
-
-       /* Force the switch to start */
-       ksz8895_write_smireg(phydev, 1, 1);
-
-       return 0;
-}
-
-static int ksz8895_startup(struct phy_device *phydev)
-{
-       return 0;
-}
-
-static struct phy_driver ksz8895_driver = {
-       .name = "Micrel KSZ8895/KSZ8864",
-       .uid  = 0x221450,
-       .mask = 0xffffe1,
-       .features = PHY_BASIC_FEATURES,
-       .config   = &ksz8895_config,
-       .startup  = &ksz8895_startup,
-       .shutdown = &genphy_shutdown,
-};
-
-#ifndef CONFIG_PHY_MICREL_KSZ9021
-/*
- * I can't believe Micrel used the exact same part number
- * for the KSZ9021. Shame Micrel, Shame!
- */
-static struct phy_driver KS8721_driver = {
-       .name = "Micrel KS8721BL",
-       .uid = 0x221610,
-       .mask = 0xfffff0,
-       .features = PHY_BASIC_FEATURES,
-       .config = &genphy_config,
-       .startup = &genphy_startup,
-       .shutdown = &genphy_shutdown,
-};
-#endif
-
-
 /*
  * KSZ9021 - KSZ9031 common
  */
@@ -178,6 +29,19 @@ static struct phy_driver KS8721_driver = {
 #define MIIM_KSZ90xx_PHYCTL_10         (1 << 4)
 #define MIIM_KSZ90xx_PHYCTL_DUPLEX     (1 << 3)
 
+/* KSZ9021 PHY Registers */
+#define MII_KSZ9021_EXTENDED_CTRL      0x0b
+#define MII_KSZ9021_EXTENDED_DATAW     0x0c
+#define MII_KSZ9021_EXTENDED_DATAR     0x0d
+
+#define CTRL1000_PREFER_MASTER         (1 << 10)
+#define CTRL1000_CONFIG_MASTER         (1 << 11)
+#define CTRL1000_MANUAL_CONFIG         (1 << 12)
+
+/* KSZ9031 PHY Registers */
+#define MII_KSZ9031_MMD_ACCES_CTRL     0x0d
+#define MII_KSZ9031_MMD_REG_DATA       0x0e
+
 static int ksz90xx_startup(struct phy_device *phydev)
 {
        unsigned phy_ctl;
@@ -204,7 +68,6 @@ static int ksz90xx_startup(struct phy_device *phydev)
 }
 
 /* Common OF config bits for KSZ9021 and KSZ9031 */
-#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
 #ifdef CONFIG_DM_ETH
 struct ksz90x1_reg_field {
        const char      *name;
@@ -230,6 +93,19 @@ static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
        { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
 };
 
+static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
+       { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
+       { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
+};
+
+static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
+       { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
+};
+
+static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
+       { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
+};
+
 static int ksz90x1_of_config_group(struct phy_device *phydev,
                                   struct ksz90x1_ofcfg *ofcfg)
 {
@@ -267,29 +143,6 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
 
        return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
 }
-#endif
-#endif
-
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-/*
- * KSZ9021
- */
-
-/* PHY Registers */
-#define MII_KSZ9021_EXTENDED_CTRL      0x0b
-#define MII_KSZ9021_EXTENDED_DATAW     0x0c
-#define MII_KSZ9021_EXTENDED_DATAR     0x0d
-
-#define CTRL1000_PREFER_MASTER         (1 << 10)
-#define CTRL1000_CONFIG_MASTER         (1 << 11)
-#define CTRL1000_MANUAL_CONFIG         (1 << 12)
-
-#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
-                              defined(CONFIG_PHY_MICREL_KSZ9031))
-static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
-       { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
-       { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
-};
 
 static int ksz9021_of_config(struct phy_device *phydev)
 {
@@ -308,20 +161,69 @@ static int ksz9021_of_config(struct phy_device *phydev)
 
        return 0;
 }
-#else
+
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+       struct ksz90x1_ofcfg ofcfg[] = {
+               { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
+               { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
+               { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
+               { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
+       };
+       int i, ret = 0;
+
+       for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
+               ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+       struct phy_driver *drv = phydev->drv;
+       int ret = 0;
+
+       if (!drv || !drv->writeext)
+               return -EOPNOTSUPP;
+
+       ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
+       if (ret)
+               return ret;
+
+       ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
+       return ret;
+}
+
+#else /* !CONFIG_DM_ETH */
 static int ksz9021_of_config(struct phy_device *phydev)
 {
        return 0;
 }
+
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+       return 0;
+}
+
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+       return 0;
+}
 #endif
 
+/*
+ * KSZ9021
+ */
 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
 {
        /* extended registers */
        phy_write(phydev, MDIO_DEVAD_NONE,
-               MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
+                 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
        return phy_write(phydev, MDIO_DEVAD_NONE,
-               MII_KSZ9021_EXTENDED_DATAW, val);
+                        MII_KSZ9021_EXTENDED_DATAW, val);
 }
 
 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
@@ -333,23 +235,22 @@ int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
 
 
 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
-                             int regnum)
+                              int regnum)
 {
        return ksz9021_phy_extended_read(phydev, regnum);
 }
 
 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
-                              int devaddr, int regnum, u16 val)
+                               int devaddr, int regnum, u16 val)
 {
        return ksz9021_phy_extended_write(phydev, regnum, val);
 }
 
-/* Micrel ksz9021 */
 static int ksz9021_config(struct phy_device *phydev)
 {
        unsigned ctrl1000 = 0;
        const unsigned master = CTRL1000_PREFER_MASTER |
-                       CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
+       CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
        unsigned features = phydev->drv->features;
        int ret;
 
@@ -359,13 +260,14 @@ static int ksz9021_config(struct phy_device *phydev)
 
        if (getenv("disable_giga"))
                features &= ~(SUPPORTED_1000baseT_Half |
-                               SUPPORTED_1000baseT_Full);
+               SUPPORTED_1000baseT_Full);
        /* force master mode for 1000BaseT due to chip errata */
        if (features & SUPPORTED_1000baseT_Half)
                ctrl1000 |= ADVERTISE_1000HALF | master;
        if (features & SUPPORTED_1000baseT_Full)
                ctrl1000 |= ADVERTISE_1000FULL | master;
-       phydev->advertising = phydev->supported = features;
+       phydev->advertising = features;
+       phydev->supported = features;
        phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
        genphy_config_aneg(phydev);
        genphy_restart_aneg(phydev);
@@ -383,68 +285,10 @@ static struct phy_driver ksz9021_driver = {
        .writeext = &ksz9021_phy_extwrite,
        .readext = &ksz9021_phy_extread,
 };
-#endif
 
-/**
+/*
  * KSZ9031
  */
-/* PHY Registers */
-#define MII_KSZ9031_MMD_ACCES_CTRL     0x0d
-#define MII_KSZ9031_MMD_REG_DATA       0x0e
-
-#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
-                              defined(CONFIG_PHY_MICREL_KSZ9031))
-static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
-       { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
-static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
-       { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
-
-static int ksz9031_of_config(struct phy_device *phydev)
-{
-       struct ksz90x1_ofcfg ofcfg[] = {
-               { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
-               { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
-               { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
-               { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
-       };
-       int i, ret = 0;
-
-       for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
-               ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
-static int ksz9031_center_flp_timing(struct phy_device *phydev)
-{
-       struct phy_driver *drv = phydev->drv;
-       int ret = 0;
-
-       if (!drv || !drv->writeext)
-               return -EOPNOTSUPP;
-
-       ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
-       if (ret)
-               return ret;
-
-       ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
-       return ret;
-}
-#else
-static int ksz9031_of_config(struct phy_device *phydev)
-{
-       return 0;
-}
-static int ksz9031_center_flp_timing(struct phy_device *phydev)
-{
-       return 0;
-}
-#endif
-
-/* Accessors to extended registers*/
 int ksz9031_phy_extended_write(struct phy_device *phydev,
                               int devaddr, int regnum, u16 mode, u16 val)
 {
@@ -459,7 +303,7 @@ int ksz9031_phy_extended_write(struct phy_device *phydev,
                  MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
        /*write the value*/
        return  phy_write(phydev, MDIO_DEVAD_NONE,
-               MII_KSZ9031_MMD_REG_DATA, val);
+                         MII_KSZ9031_MMD_REG_DATA, val);
 }
 
 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
@@ -479,24 +323,52 @@ static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
 {
        return ksz9031_phy_extended_read(phydev, devaddr, regnum,
                                         MII_KSZ9031_MOD_DATA_NO_POST_INC);
-};
+}
 
 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
                                int devaddr, int regnum, u16 val)
 {
        return ksz9031_phy_extended_write(phydev, devaddr, regnum,
-                                        MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
-};
+                                         MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
+}
 
 static int ksz9031_config(struct phy_device *phydev)
 {
        int ret;
+
        ret = ksz9031_of_config(phydev);
        if (ret)
                return ret;
        ret = ksz9031_center_flp_timing(phydev);
        if (ret)
                return ret;
+
+       /* add an option to disable the gigabit feature of this PHY */
+       if (getenv("disable_giga")) {
+               unsigned features;
+               unsigned bmcr;
+
+               /* disable speed 1000 in features supported by the PHY */
+               features = phydev->drv->features;
+               features &= ~(SUPPORTED_1000baseT_Half |
+                               SUPPORTED_1000baseT_Full);
+               phydev->advertising = phydev->supported = features;
+
+               /* disable speed 1000 in Basic Control Register */
+               bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+               bmcr &= ~(1 << 6);
+               phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
+
+               /* disable speed 1000 in 1000Base-T Control Register */
+               phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
+
+               /* start autoneg */
+               genphy_config_aneg(phydev);
+               genphy_restart_aneg(phydev);
+
+               return 0;
+       }
+
        return genphy_config(phydev);
 }
 
@@ -512,44 +384,9 @@ static struct phy_driver ksz9031_driver = {
        .readext = &ksz9031_phy_extread,
 };
 
-int ksz886x_config(struct phy_device *phydev)
-{
-       /* we are connected directly to the switch without
-        * dedicated PHY. */
-       phydev->link = 1;
-       phydev->duplex = DUPLEX_FULL;
-       phydev->speed = SPEED_100;
-       return 0;
-}
-
-static int ksz886x_startup(struct phy_device *phydev)
+int phy_micrel_ksz90x1_init(void)
 {
-       return 0;
-}
-
-static struct phy_driver ksz886x_driver = {
-       .name = "Micrel KSZ886x Switch",
-       .uid  = 0x00221430,
-       .mask = 0xfffff0,
-       .features = PHY_BASIC_FEATURES,
-       .config = &ksz886x_config,
-       .startup = &ksz886x_startup,
-       .shutdown = &genphy_shutdown,
-};
-
-int phy_micrel_init(void)
-{
-       phy_register(&KSZ804_driver);
-       phy_register(&KSZ8031_driver);
-       phy_register(&KSZ8051_driver);
-       phy_register(&KSZ8081_driver);
-#ifdef CONFIG_PHY_MICREL_KSZ9021
        phy_register(&ksz9021_driver);
-#else
-       phy_register(&KS8721_driver);
-#endif
        phy_register(&ksz9031_driver);
-       phy_register(&ksz8895_driver);
-       phy_register(&ksz886x_driver);
        return 0;
 }
index 97e0bc0..5be51d7 100644 (file)
@@ -488,8 +488,11 @@ int phy_init(void)
 #ifdef CONFIG_PHY_MARVELL
        phy_marvell_init();
 #endif
-#ifdef CONFIG_PHY_MICREL
-       phy_micrel_init();
+#ifdef CONFIG_PHY_MICREL_KSZ8XXX
+       phy_micrel_ksz8xxx_init();
+#endif
+#ifdef CONFIG_PHY_MICREL_KSZ90X1
+       phy_micrel_ksz90x1_init();
 #endif
 #ifdef CONFIG_PHY_NATSEMI
        phy_natsemi_init();
index ed441f3..e09351b 100644 (file)
@@ -26,7 +26,7 @@ struct r8152_dongle {
        unsigned short product;
 };
 
-static const struct r8152_dongle const r8152_dongles[] = {
+static const struct r8152_dongle r8152_dongles[] = {
        /* Realtek */
        { 0x0bda, 0x8050 },
        { 0x0bda, 0x8152 },
@@ -59,7 +59,7 @@ struct r8152_version {
        bool           gmii;
 };
 
-static const struct r8152_version const r8152_versions[] = {
+static const struct r8152_version r8152_versions[] = {
        { 0x4c00, RTL_VER_01, 0 },
        { 0x4c10, RTL_VER_02, 0 },
        { 0x5c00, RTL_VER_03, 1 },
index 61dfed8..082cc4a 100644 (file)
@@ -562,36 +562,9 @@ config CONSOLE_SCROLL_LINES
          console jump but can help speed up operation when scrolling
          is slow.
 
-config VIDEO_CT69000
-       bool "Enable Chips & Technologies 69000 video driver"
-       depends on VIDEO
-       help
-         This enables a frame buffer driver for the Chips & Technologies
-         ct69000, a fairly old graphics device (circa 2000) which is used
-         on some hardware. It operates over the ISA bus, and supports
-         some acceleration features.
-
-         For the CT69000 and SMI_LYNXEM drivers, videomode is
-               selected via environment 'videomode'. Two different ways
-               are possible:
-               - "videomode=num"   'num' is a standard LiLo mode numbers.
-               Following standard modes are supported  (* is default):
-
-                     Colors    640x480 800x600 1024x768 1152x864 1280x1024
-               -------------+---------------------------------------------
-                     8 bits |  0x301*  0x303    0x305    0x161     0x307
-                    15 bits |  0x310   0x313    0x316    0x162     0x319
-                    16 bits |  0x311   0x314    0x317    0x163     0x31A
-                    24 bits |  0x312   0x315    0x318      ?       0x31B
-               -------------+---------------------------------------------
-               (i.e. setenv videomode 317; saveenv; reset;)
-
-               - "videomode=bootargs" all the video parameters are parsed
-               from the bootargs. (See drivers/video/videomodes.c)
-
 config SYS_CONSOLE_BG_COL
        hex "Background colour"
-       depends on CFB_CONSOLE || VIDEO_CT69000
+       depends on CFB_CONSOLE
        default 0x00
        help
          Defines the background colour for the console. The value is from
@@ -602,7 +575,7 @@ config SYS_CONSOLE_BG_COL
 
 config SYS_CONSOLE_FG_COL
        hex "Foreground colour"
-       depends on CFB_CONSOLE || VIDEO_CT69000
+       depends on CFB_CONSOLE
        default 0xa0
        help
          Defines the foreground colour for the console. The value is from
index ac5371f..5cf8909 100644 (file)
@@ -28,16 +28,13 @@ obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
 obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
 obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
-obj-$(CONFIG_L5F31188) += l5f31188.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
 obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
 obj-$(CONFIG_S6E63D6) += s6e63d6.o
 obj-$(CONFIG_LD9040) += ld9040.o
-obj-$(CONFIG_SED156X) += sed156x.o
 obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
 obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
-obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
@@ -49,7 +46,6 @@ obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
 obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
 obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
 obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
-obj-$(CONFIG_VIDEO_SM501) += sm501.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
index f548020..b6fc7e1 100644 (file)
 #include <video.h>
 #include <linux/compiler.h>
 
-/*
- * Defines for the CT69000 driver
- */
-#ifdef CONFIG_VIDEO_CT69000
-
-#define VIDEO_FB_LITTLE_ENDIAN
-#define VIDEO_HW_RECTFILL
-#define VIDEO_HW_BITBLT
-#endif
-
 #if defined(CONFIG_VIDEO_MXS)
 #define VIDEO_FB_16BPP_WORD_SWAP
 #endif
diff --git a/drivers/video/ct69000.c b/drivers/video/ct69000.c
deleted file mode 100644 (file)
index a74e4e6..0000000
+++ /dev/null
@@ -1,1168 +0,0 @@
-/* ported from ctfb.c (linux kernel):
- * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
- *
- * Ported to U-Boot:
- * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-
-#ifdef CONFIG_VIDEO
-
-#include <pci.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-/* debug */
-#undef VGA_DEBUG
-#undef VGA_DUMP_REG
-#ifdef VGA_DEBUG
-#undef _DEBUG
-#define _DEBUG  1
-#else
-#undef _DEBUG
-#define _DEBUG  0
-#endif
-
-/* Macros */
-#ifndef min
-#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
-#endif
-#ifndef max
-#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
-#endif
-#ifdef minmax
-#error "term minmax already used."
-#endif
-#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
-#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
-
-/* CT Register Offsets */
-#define CT_AR_O                        0x3c0   /* Index and Data write port of the attribute Registers */
-#define CT_GR_O                        0x3ce   /* Index port of the Graphic Controller Registers */
-#define CT_SR_O                        0x3c4   /* Index port of the Sequencer Controller */
-#define CT_CR_O                        0x3d4   /* Index port of the CRT Controller */
-#define CT_XR_O                        0x3d6   /* Extended Register index */
-#define CT_MSR_W_O             0x3c2   /* Misc. Output Register (write only) */
-#define CT_LUT_MASK_O          0x3c6   /* Color Palette Mask */
-#define CT_LUT_START_O         0x3c8   /* Color Palette Write Mode Index */
-#define CT_LUT_RGB_O           0x3c9   /* Color Palette Data Port */
-#define CT_STATUS_REG0_O       0x3c2   /* Status Register 0 (read only) */
-#define CT_STATUS_REG1_O       0x3da   /* Input Status Register 1 (read only) */
-
-#define CT_FP_O                        0x3d0   /* Index port of the Flat panel Registers */
-#define CT_MR_O                        0x3d2   /* Index Port of the Multimedia Extension */
-
-/* defines for the memory mapped registers */
-#define BR00_o         0x400000        /* Source and Destination Span Register */
-#define BR01_o         0x400004        /* Pattern/Source Expansion Background Color & Transparency Key Register */
-#define BR02_o         0x400008        /* Pattern/Source Expansion Foreground Color Register */
-#define BR03_o         0x40000C        /* Monochrome Source Control Register */
-#define BR04_o         0x400010        /* BitBLT Control Register */
-#define BR05_o         0x400014        /* Pattern Address Registe */
-#define BR06_o         0x400018        /* Source Address Register */
-#define BR07_o         0x40001C        /* Destination Address Register */
-#define BR08_o         0x400020        /* Destination Width & Height Register */
-#define BR09_o         0x400024        /* Source Expansion Background Color & Transparency Key Register */
-#define BR0A_o         0x400028        /* Source Expansion Foreground Color Register */
-
-#define CURSOR_SIZE    0x1000  /* in KByte for HW Cursor */
-#define PATTERN_ADR    (pGD->dprBase + CURSOR_SIZE)    /* pattern Memory after Cursor Memory */
-#define PATTERN_SIZE   8*8*4   /* 4 Bytes per Pixel 8 x 8 Pixel */
-#define ACCELMEMORY    (CURSOR_SIZE + PATTERN_SIZE)    /* reserved Memory for BITBlt and hw cursor */
-
-/* Some Mode definitions */
-#define FB_SYNC_HOR_HIGH_ACT   1       /* horizontal sync high active  */
-#define FB_SYNC_VERT_HIGH_ACT  2       /* vertical sync high active    */
-#define FB_SYNC_EXT            4       /* external sync                */
-#define FB_SYNC_COMP_HIGH_ACT  8       /* composite sync high active   */
-#define FB_SYNC_BROADCAST      16      /* broadcast video timings      */
-                                       /* vtotal = 144d/288n/576i => PAL  */
-                                       /* vtotal = 121d/242n/484i => NTSC */
-#define FB_SYNC_ON_GREEN       32      /* sync on green */
-
-#define FB_VMODE_NONINTERLACED  0      /* non interlaced */
-#define FB_VMODE_INTERLACED    1       /* interlaced   */
-#define FB_VMODE_DOUBLE                2       /* double scan */
-#define FB_VMODE_MASK          255
-
-#define FB_VMODE_YWRAP         256     /* ywrap instead of panning     */
-#define FB_VMODE_SMOOTH_XPAN   512     /* smooth xpan possible (internally used) */
-#define FB_VMODE_CONUPDATE     512     /* don't update x/yoffset       */
-
-#define text                   0
-#define fntwidth               8
-
-/* table for VGA Initialization  */
-typedef struct {
-       const unsigned char reg;
-       const unsigned char val;
-} CT_CFG_TABLE;
-
-/* this table provides some basic initialisations such as Memory Clock etc */
-static CT_CFG_TABLE xreg[] = {
-       {0x09, 0x01},           /* CRT Controller Extensions Enable */
-       {0x0A, 0x02},           /* Frame Buffer Mapping */
-       {0x0B, 0x01},           /* PCI Write Burst support */
-       {0x20, 0x00},           /* BitBLT Configuration */
-       {0x40, 0x03},           /* Memory Access Control */
-       {0x60, 0x00},           /* Video Pin Control */
-       {0x61, 0x00},           /* DPMS Synch control */
-       {0x62, 0x00},           /* GPIO Pin Control */
-       {0x63, 0xBD},           /* GPIO Pin Data */
-       {0x67, 0x00},           /* Pin Tri-State */
-       {0x80, 0x80},           /* Pixel Pipeline Config 0 register */
-       {0xA0, 0x00},           /* Cursor 1 Control Reg */
-       {0xA1, 0x00},           /* Cursor 1 Vertical Extension Reg */
-       {0xA2, 0x00},           /* Cursor 1 Base Address Low */
-       {0xA3, 0x00},           /* Cursor 1 Base Address High */
-       {0xA4, 0x00},           /* Cursor 1 X-Position Low */
-       {0xA5, 0x00},           /* Cursor 1 X-Position High */
-       {0xA6, 0x00},           /* Cursor 1 Y-Position Low */
-       {0xA7, 0x00},           /* Cursor 1 Y-Position High */
-       {0xA8, 0x00},           /* Cursor 2 Control Reg */
-       {0xA9, 0x00},           /* Cursor 2 Vertical Extension Reg */
-       {0xAA, 0x00},           /* Cursor 2 Base Address Low */
-       {0xAB, 0x00},           /* Cursor 2 Base Address High */
-       {0xAC, 0x00},           /* Cursor 2 X-Position Low */
-       {0xAD, 0x00},           /* Cursor 2 X-Position High */
-       {0xAE, 0x00},           /* Cursor 2 Y-Position Low */
-       {0xAF, 0x00},           /* Cursor 2 Y-Position High */
-       {0xC0, 0x7D},           /* Dot Clock 0 VCO M-Divisor */
-       {0xC1, 0x07},           /* Dot Clock 0 VCO N-Divisor */
-       {0xC3, 0x34},           /* Dot Clock 0 Divisor select */
-       {0xC4, 0x55},           /* Dot Clock 1 VCO M-Divisor */
-       {0xC5, 0x09},           /* Dot Clock 1 VCO N-Divisor */
-       {0xC7, 0x24},           /* Dot Clock 1 Divisor select */
-       {0xC8, 0x7D},           /* Dot Clock 2 VCO M-Divisor */
-       {0xC9, 0x07},           /* Dot Clock 2 VCO N-Divisor */
-       {0xCB, 0x34},           /* Dot Clock 2 Divisor select */
-       {0xCC, 0x38},           /* Memory Clock 0 VCO M-Divisor */
-       {0xCD, 0x03},           /* Memory Clock 0 VCO N-Divisor */
-       {0xCE, 0x90},           /* Memory Clock 0 Divisor select */
-       {0xCF, 0x06},           /* Clock Config */
-       {0xD0, 0x0F},           /* Power Down */
-       {0xD1, 0x01},           /* Power Down BitBLT */
-       {0xFF, 0xFF}            /* end of table */
-};
-/* Clock Config:
- * =============
- *
- * PD Registers:
- * -------------
- * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
- * They are encoded as follows:
- *
- * +---+--------------+
- * | 2 | Loop Divisor |
- * +---+--------------+
- * | 1 | 1            |
- * +---+--------------+
- * | 0 | 4            |
- * +---+--------------+
- * Note: The Memory Clock does not have a Loop Divisor.
- * +---+---+---+--------------+
- * | 6 | 5 | 4 | Post Divisor |
- * +---+---+---+--------------+
- * | 0 | 0 | 0 | 1            |
- * +---+---+---+--------------+
- * | 0 | 0 | 1 | 2            |
- * +---+---+---+--------------+
- * | 0 | 1 | 0 | 4            |
- * +---+---+---+--------------+
- * | 0 | 1 | 1 | 8            |
- * +---+---+---+--------------+
- * | 1 | 0 | 0 | 16           |
- * +---+---+---+--------------+
- * | 1 | 0 | 1 | 32           |
- * +---+---+---+--------------+
- * | 1 | 1 | X | reserved     |
- * +---+---+---+--------------+
- *
- * All other bits are reserved in these registers.
- *
- * Clock VCO M Registers:
- * ----------------------
- * These Registers contain the M Value -2.
- *
- * Clock VCO N Registers:
- * ----------------------
- * These Registers contain the N Value -2.
- *
- * Formulas:
- * ---------
- * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
- * Fout = Fvco / Post Divisor
- *
- * Dot Clk0 (default 25MHz):
- * -------------------------
- * Fvco = 14.318 * 127 / 9 = 202.045MHz
- * Fout = 202.045MHz / 8 = 25.25MHz
- * Post Divisor = 8
- * Loop Divisor = 1
- * XRC0 = (M - 2) = 125 = 0x7D
- * XRC1 = (N - 2) = 7   = 0x07
- * XRC3 =                 0x34
- *
- * Dot Clk1 (default 28MHz):
- * -------------------------
- * Fvco = 14.318 * 87 / 11 = 113.24MHz
- * Fout = 113.24MHz / 4 = 28.31MHz
- * Post Divisor = 4
- * Loop Divisor = 1
- * XRC4 = (M - 2) = 85 = 0x55
- * XRC5 = (N - 2) = 9  = 0x09
- * XRC7 =                0x24
- *
- * Dot Clk2 (variable for extended modes set to 25MHz):
- * ----------------------------------------------------
- * Fvco = 14.318 * 127 / 9 = 202.045MHz
- * Fout = 202.045MHz / 8 = 25.25MHz
- * Post Divisor = 8
- * Loop Divisor = 1
- * XRC8 = (M - 2) = 125 = 0x7D
- * XRC9 = (N - 2) = 7   = 0x07
- * XRCB =                 0x34
- *
- * Memory Clk for most modes >50MHz:
- * ----------------------------------
- * Fvco = 14.318 * 58 / 5 = 166MHz
- * Fout = 166MHz / 2      = 83MHz
- * Post Divisor = 2
- * XRCC = (M - 2) = 57  = 0x38
- * XRCD = (N - 2) = 3   = 0x03
- * XRCE =                 0x90
- *
- * Note Bit7 enables the clock source from the VCO
- *
- */
-
-/*******************************************************************
- * Chips struct
- *******************************************************************/
-struct ctfb_chips_properties {
-       int device_id;          /* PCI Device ID */
-       unsigned long max_mem;  /* memory for frame buffer */
-       int vld_set;            /* value of VLD if bit2 in clock control is set */
-       int vld_not_set;        /* value of VLD if bit2 in clock control is set */
-       int mn_diff;            /* difference between M/N Value + mn_diff = M/N Register */
-       int mn_min;             /* min value of M/N Value */
-       int mn_max;             /* max value of M/N Value */
-       int vco_min;            /* VCO Min in MHz */
-       int vco_max;            /* VCO Max in MHz */
-};
-
-static const struct ctfb_chips_properties chips[] = {
-       {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
-       {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220},  /* NOT TESTED */
-       {0, 0, 0, 0, 0, 0, 0, 0, 0}     /* Terminator */
-};
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-/*******************************************************************************
-*
-* Low Level Routines
-*/
-
-/*******************************************************************************
-*
-* Read CT ISA register
-*/
-#ifdef VGA_DEBUG
-static unsigned char
-ctRead (unsigned short index)
-{
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-       if (index == CT_AR_O)
-               /* synch the Flip Flop */
-               in8 (pGD->isaBase + CT_STATUS_REG1_O);
-
-       return (in8 (pGD->isaBase + index));
-}
-#endif
-/*******************************************************************************
-*
-* Write CT ISA register
-*/
-static void
-ctWrite (unsigned short index, unsigned char val)
-{
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-
-       out8 ((pGD->isaBase + index), val);
-}
-
-/*******************************************************************************
-*
-* Read CT ISA register indexed
-*/
-static unsigned char
-ctRead_i (unsigned short index, char reg)
-{
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-       if (index == CT_AR_O)
-               /* synch the Flip Flop */
-               in8 (pGD->isaBase + CT_STATUS_REG1_O);
-       out8 ((pGD->isaBase + index), reg);
-       return (in8 (pGD->isaBase + index + 1));
-}
-
-/*******************************************************************************
-*
-* Write CT ISA register indexed
-*/
-static void
-ctWrite_i (unsigned short index, char reg, char val)
-{
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-       if (index == CT_AR_O) {
-               /* synch the Flip Flop */
-               in8 (pGD->isaBase + CT_STATUS_REG1_O);
-               out8 ((pGD->isaBase + index), reg);
-               out8 ((pGD->isaBase + index), val);
-       } else {
-               out8 ((pGD->isaBase + index), reg);
-               out8 ((pGD->isaBase + index + 1), val);
-       }
-}
-
-/*******************************************************************************
-*
-* Write a table of CT ISA register
-*/
-static void
-ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab)
-{
-       while (regTab->reg != 0xFF) {
-               ctWrite_i (index, regTab->reg, regTab->val);
-               regTab++;
-       }
-}
-
-/*****************************************************************************/
-static void
-SetArRegs (void)
-{
-       int i, tmp;
-
-       for (i = 0; i < 0x10; i++)
-               ctWrite_i (CT_AR_O, i, i);
-       if (text)
-               tmp = 0x04;
-       else
-               tmp = 0x41;
-
-       ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */
-       ctWrite_i (CT_AR_O, 0x11, 0x00);        /* Overscan Color Register */
-       ctWrite_i (CT_AR_O, 0x12, 0x0f);        /* Memory Plane Enable Register */
-       if (fntwidth == 9)
-               tmp = 0x08;
-       else
-               tmp = 0x00;
-       ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */
-       ctWrite_i (CT_AR_O, 0x14, 0x00);        /* Color Select Register    */
-       ctWrite (CT_AR_O, 0x20);        /* enable video             */
-}
-
-/*****************************************************************************/
-static void
-SetGrRegs (void)
-{                              /* Set Graphics Mode */
-       int i;
-
-       for (i = 0; i < 0x05; i++)
-               ctWrite_i (CT_GR_O, i, 0);
-       if (text) {
-               ctWrite_i (CT_GR_O, 0x05, 0x10);
-               ctWrite_i (CT_GR_O, 0x06, 0x02);
-       } else {
-               ctWrite_i (CT_GR_O, 0x05, 0x40);
-               ctWrite_i (CT_GR_O, 0x06, 0x05);
-       }
-       ctWrite_i (CT_GR_O, 0x07, 0x0f);
-       ctWrite_i (CT_GR_O, 0x08, 0xff);
-}
-
-/*****************************************************************************/
-static void
-SetSrRegs (void)
-{
-       int tmp = 0;
-
-       ctWrite_i (CT_SR_O, 0x00, 0x00);        /* reset */
-       /*rr( sr, 0x01, tmp );
-          if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
-          wr( sr, 0x01, tmp );  */
-       if (fntwidth == 8)
-               ctWrite_i (CT_SR_O, 0x01, 0x01);        /* Clocking Mode Register */
-       else
-               ctWrite_i (CT_SR_O, 0x01, 0x00);        /* Clocking Mode Register */
-       ctWrite_i (CT_SR_O, 0x02, 0x0f);        /* Enable CPU wr access to given memory plane */
-       ctWrite_i (CT_SR_O, 0x03, 0x00);        /* Character Map Select Register */
-       if (text)
-               tmp = 0x02;
-       else
-               tmp = 0x0e;
-       ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB
-                                          total VGA memory beyond the first 64KB and set
-                                          fb mapping mode. */
-       ctWrite_i (CT_SR_O, 0x00, 0x03);        /* enable */
-}
-
-/*****************************************************************************/
-static void
-SetBitsPerPixelIntoXrRegs (int bpp)
-{
-       unsigned int n = (bpp >> 3), tmp;       /* only for 15, 8, 16, 24 bpp */
-       static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
-       static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 };    /* mask */
-       static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
-       if (bpp == 15)
-               n = 0;
-       tmp = ctRead_i (CT_XR_O, 0x20);
-       tmp &= off[n];
-       tmp |= on[n];
-       ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
-       ctWrite_i (CT_XR_O, 0x81, md[n]);
-}
-
-/*****************************************************************************/
-static void
-SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel)
-{                              /* he -le-   ht|0    hd -ri- hs     -h-      he */
-       unsigned char cr[0x7a];
-       int i, tmp;
-       unsigned int hd, hs, he, ht, hbe;       /* Horizontal.  */
-       unsigned int vd, vs, ve, vt;    /* vertical */
-       unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine;
-       unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay;
-       unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl;
-       unsigned int HorizontalEqualizationPulses;
-       unsigned int HorizontalSerration1Start, HorizontalSerration2Start;
-
-       const int LineCompare = 0x3ff;
-       unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor   */
-       unsigned int RAMDAC_BlankPedestalEnable = 0;    /* 1=en-, 0=disable, see XR82 */
-
-       hd = (var->xres) / 8;   /* HDisp.  */
-       hs = (var->xres + var->right_margin) / 8;       /* HsStrt  */
-       he = (var->xres + var->right_margin + var->hsync_len) / 8;      /* HsEnd   */
-       ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8;   /* HTotal  */
-       hbe = ht - 1;           /* HBlankEnable todo docu wants ht here, but it does not work */
-       /* ve -up-  vt|0    vd -lo- vs     -v-      ve */
-       vd = var->yres;         /* VDisplay   */
-       vs = var->yres + var->lower_margin;     /* VSyncStart */
-       ve = var->yres + var->lower_margin + var->vsync_len;    /* VSyncEnd */
-       vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len;        /* VTotal  */
-       bpp = bits_per_pixel;
-       dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
-       interlaced = var->vmode & FB_VMODE_INTERLACED;
-       bcast = var->sync & FB_SYNC_BROADCAST;
-       CrtHalfLine = bcast ? (hd >> 1) : 0;
-       BlDelayCtrl = bcast ? 1 : 0;
-       CompSyncCharClkDelay = 0;       /* 2 bit */
-       CompSyncPixelClkDelay = 0;      /* 3 bit */
-       if (bcast) {
-               NTSC_PAL_HorizontalPulseWidth = 7;      /*( var->hsync_len >> 1 ) + 1 */
-               HorizontalEqualizationPulses = 0;       /* inverse value */
-               HorizontalSerration1Start = 31; /* ( ht >> 1 ) */
-               HorizontalSerration2Start = 89; /* ( ht >> 1 ) */
-       } else {
-               NTSC_PAL_HorizontalPulseWidth = 0;
-               /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
-                * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
-               HorizontalEqualizationPulses = 1;       /* inverse value */
-               HorizontalSerration1Start = 0;  /* ( ht >> 1 ) */
-               HorizontalSerration2Start = 0;  /* ( ht >> 1 ) */
-       }
-
-       if (bpp == 15)
-               bpp = 16;
-       wd = var->xres * bpp / 64;      /* double words per line */
-       if (interlaced) {       /* we divide all vertical timings, exept vd */
-               vs >>= 1;
-               ve >>= 1;
-               vt >>= 1;
-       }
-       memset (cr, 0, sizeof (cr));
-       cr[0x00] = 0xff & (ht - 5);
-       cr[0x01] = hd - 1;      /* soll:4f ist 59 */
-       cr[0x02] = hd;
-       cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd  */
-       cr[0x04] = hs;
-       cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
-       cr[0x06] = (vt - 2) & 0xFF;
-       cr[0x30] = (vt - 2) >> 8;
-       cr[0x07] = ((vt & 0x100) >> 8)
-           | ((vd & 0x100) >> 7)
-           | ((vs & 0x100) >> 6)
-           | ((vs & 0x100) >> 5)
-           | ((LineCompare & 0x100) >> 4)
-           | ((vt & 0x200) >> 4)
-           | ((vd & 0x200) >> 3)
-           | ((vs & 0x200) >> 2);
-       cr[0x08] = 0x00;
-       cr[0x09] = (dblscan << 7)
-           | ((LineCompare & 0x200) >> 3)
-           | ((vs & 0x200) >> 4)
-           | (TextScanLines - 1);
-       cr[0x10] = vs & 0xff;   /* VSyncPulseStart */
-       cr[0x32] = (vs & 0xf00) >> 8;   /* VSyncPulseStart */
-       cr[0x11] = (ve & 0x0f); /* | 0x20;      */
-       cr[0x12] = (vd - 1) & 0xff;     /* LineCount  */
-       cr[0x31] = ((vd - 1) & 0xf00) >> 8;     /* LineCount */
-       cr[0x13] = wd & 0xff;
-       cr[0x41] = (wd & 0xf00) >> 8;
-       cr[0x15] = vs & 0xff;
-       cr[0x33] = (vs & 0xf00) >> 8;
-       cr[0x38] = (0x100 & (ht - 5)) >> 8;
-       cr[0x3C] = 0xc0 & hbe;
-       cr[0x16] = (vt - 1) & 0xff;     /* vbe - docu wants vt here, */
-       cr[0x17] = 0xe3;        /* but it does not work */
-       cr[0x18] = 0xff & LineCompare;
-       cr[0x22] = 0xff;        /* todo? */
-       cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00;    /* check:0xa6  */
-       cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6)
-           | (BlDelayCtrl << 5)
-           | ((0x03 & CompSyncCharClkDelay) << 3)
-           | (0x07 & CompSyncPixelClkDelay);   /* todo: see XR82 */
-       cr[0x72] = HorizontalSerration1Start;
-       cr[0x73] = HorizontalSerration2Start;
-       cr[0x74] = (HorizontalEqualizationPulses << 5)
-           | NTSC_PAL_HorizontalPulseWidth;
-       /* todo: ct69000 has also 0x75-79 */
-       /* now set the registers */
-       for (i = 0; i <= 0x0d; i++) {   /*CR00 .. CR0D */
-               ctWrite_i (CT_CR_O, i, cr[i]);
-       }
-       for (i = 0x10; i <= 0x18; i++) {        /*CR10 .. CR18 */
-               ctWrite_i (CT_CR_O, i, cr[i]);
-       }
-       i = 0x22;               /*CR22 */
-       ctWrite_i (CT_CR_O, i, cr[i]);
-       for (i = 0x30; i <= 0x33; i++) {        /*CR30 .. CR33 */
-               ctWrite_i (CT_CR_O, i, cr[i]);
-       }
-       i = 0x38;               /*CR38 */
-       ctWrite_i (CT_CR_O, i, cr[i]);
-       i = 0x3C;               /*CR3C */
-       ctWrite_i (CT_CR_O, i, cr[i]);
-       for (i = 0x40; i <= 0x41; i++) {        /*CR40 .. CR41 */
-               ctWrite_i (CT_CR_O, i, cr[i]);
-       }
-       for (i = 0x70; i <= 0x74; i++) {        /*CR70 .. CR74 */
-               ctWrite_i (CT_CR_O, i, cr[i]);
-       }
-       tmp = ctRead_i (CT_CR_O, 0x40);
-       tmp &= 0x0f;
-       tmp |= 0x80;
-       ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */
-}
-
-/* pixelclock control */
-
-/*****************************************************************************
- We have a rational number p/q and need an m/n which is very close to p/q
- but has m and n within mnmin and mnmax. We have no floating point in the
- kernel. We can use long long without divide. And we have time to compute...
-******************************************************************************/
-static unsigned int
-FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
-                    unsigned int mnmax, unsigned int *pm, unsigned int *pn)
-{
-       /* this code is not for general purpose usable but good for our number ranges */
-       unsigned int n = mnmin, m = 0;
-       long long int L = 0, P = p, Q = q, H = P >> 1;
-       long long int D = 0x7ffffffffffffffLL;
-       for (n = mnmin; n <= mnmax; n++) {
-               m = mnmin;      /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
-               L = P * n - m * Q;      /* n * vco - m * fref should be near 0 */
-               while (L > 0 && m < mnmax) {
-                       L -= q; /* difference is greater as 0 subtract fref */
-                       m++;    /* and increment m */
-               }
-               /* difference is less or equal than 0 or m > maximum */
-               if (m > mnmax)
-                       break;  /* no solution: if we increase n we get the same situation */
-               /* L is <= 0 now */
-               if (-L > H && m > mnmin) {      /* if difference > the half fref */
-                       L += q; /* we take the situation before */
-                       m--;    /* because its closer to 0 */
-               }
-               L = (L < 0) ? -L : +L;  /* absolute value */
-               if (D < L)      /* if last difference was better take next n */
-                       continue;
-               D = L;
-               *pm = m;
-               *pn = n;        /*  keep improved data */
-               if (D == 0)
-                       break;  /* best result we can get */
-       }
-       return (unsigned int) (0xffffffff & D);
-}
-
-/* that is the hardware < 69000 we have to manage
- +---------+  +-------------------+  +----------------------+  +--+
- | REFCLK  |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
- | 14.3MHz |  |(NTSCDS) (÷1, Ã·5)  |  |Select (RDS) (÷1, Ã·4) |  |  |  |
- +---------+  +-------------------+  +----------------------+  +--+  |
-  ___________________________________________________________________|
- |
- |                                    fvco                      fout
- | +--------+  +------------+  +-----+     +-------------------+   +----+
- +-| Phase  |__|Charge Pump |__| VCO |_____|Post Divisor (PD)  |___|CLK |--->
- +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
- | +--------+  +------------+  +-----+  |  +-------------------+   +----+
- |                                      |
- |    +--+   +---------------+          |
- |____|÷M|___|VCO Loop Divide|__________|
-      |  |   |(VLD)(÷4, Ã·16) |
-      +--+   +---------------+
-****************************************************************************
-  that is the hardware >= 69000 we have to manage
- +---------+  +--+
- | REFCLK  |__|÷N|__
- | 14.3MHz |  |  |  |
- +---------+  +--+  |
-  __________________|
- |
- |                                    fvco                      fout
- | +--------+  +------------+  +-----+     +-------------------+   +----+
- +-| Phase  |__|Charge Pump |__| VCO |_____|Post Divisor (PD)  |___|CLK |--->
- +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
- | +--------+  +------------+  +-----+  |  +-------------------+   +----+
- |                                      |
- |    +--+   +---------------+          |
- |____|÷M|___|VCO Loop Divide|__________|
-      |  |   |(VLD)(÷1, Ã·4)  |
-      +--+   +---------------+
-
-
-*/
-
-#define VIDEO_FREF 14318180;   /* Hz  */
-/*****************************************************************************/
-static int
-ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param)
-{
-       unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock;
-       i = 0;
-       pixclock = -1;
-       fref = VIDEO_FREF;
-       m = ctRead_i (CT_XR_O, 0xc8);
-       n = ctRead_i (CT_XR_O, 0xc9);
-       m -= param->mn_diff;
-       n -= param->mn_diff;
-       xr_cb = ctRead_i (CT_XR_O, 0xcb);
-       PD = (0x70 & xr_cb) >> 4;
-       pd = 1;
-       for (i = 0; i < PD; i++) {
-               pd *= 2;
-       }
-       vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set;
-       if (n * vld * m) {
-               unsigned long long p = 1000000000000LL * pd * n;
-               unsigned long long q = (long long) fref * vld * m;
-               while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) {
-                       p >>= 1;        /* can't divide with long long so we scale down */
-                       q >>= 1;
-               }
-               pixclock = (unsigned) p / (unsigned) q;
-       } else
-               printf ("Invalid data in xr regs.\n");
-       return pixclock;
-}
-
-/*****************************************************************************/
-static void
-FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
-                             struct ctfb_chips_properties *param)
-{
-       unsigned int m, n, vld, pd, PD, fref, xr_cb;
-       unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk;
-       unsigned int pfreq, fvco, new_pixclock;
-       unsigned int D,nback,mback;
-
-       fref = VIDEO_FREF;
-       pd = 1;
-       PD = 0;
-       fvcomin = param->vco_min;
-       fvcomax = param->vco_max;       /* MHz */
-       pclckmin = 1000000 / fvcomax + 1;       /*   4546 */
-       pclckmax = 32000000 / fvcomin - 1;      /* 666665 */
-       pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */
-       pfreq = 250 * (4000000000U / pclk);
-       fvco = pfreq;           /* Hz */
-       new_pixclock = 0;
-       while (fvco < fvcomin * 1000000) {
-               /* double VCO starting with the pixelclock frequency
-                * as long as it is lower than the minimal VCO frequency */
-               fvco *= 2;
-               pd *= 2;
-               PD++;
-       }
-       /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
-       /* first try */
-       vld = param->vld_set;
-       D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */
-       mback=m;
-       nback=n;
-       /* second try */
-       vld = param->vld_not_set;
-       if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) {    /* rds = 1 */
-               /* first try was better */
-               m=mback;
-               n=nback;
-               vld = param->vld_set;
-       }
-       m += param->mn_diff;
-       n += param->mn_diff;
-       debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld);
-       xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
-       /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
-        * written, and in order from XRC8 to XRCB, before the hardware will
-        * update the synthesizer s settings.
-        */
-       ctWrite_i (CT_XR_O, 0xc8, m);
-       ctWrite_i (CT_XR_O, 0xc9, n);   /* xrca does not exist in CT69000 and CT69030 */
-       ctWrite_i (CT_XR_O, 0xca, 0);   /* because of a hw bug I guess, but we write */
-       ctWrite_i (CT_XR_O, 0xcb, xr_cb);       /* 0 to it for savety */
-       new_pixclock = ReadPixClckFromXrRegsBack (param);
-       debug("pixelclock.set = %d, pixelclock.real = %d\n",
-               pixelclock, new_pixclock);
-}
-
-/*****************************************************************************/
-static void
-SetMsrRegs (struct ctfb_res_modes *mode)
-{
-       unsigned char h_synch_high, v_synch_high;
-
-       h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40;  /* horizontal Synch High active */
-       v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
-       ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29));
-       /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
-        * Selects the upper 64KB page.Bit5=1
-        * CLK2 (left reserved in standard VGA) Bit3|2=1|0
-        * Disables CPU access to frame buffer. Bit1=0
-        * Sets the I/O address decode for ST01, FCR, and all CR registers
-        * to the 3Dx I/O address range (CGA emulation). Bit0=1
-        */
-}
-
-/************************************************************************************/
-#ifdef VGA_DUMP_REG
-
-static void
-ctDispRegs (unsigned short index, int from, int to)
-{
-       unsigned char status;
-       int i;
-
-       for (i = from; i < to; i++) {
-               status = ctRead_i (index, i);
-               printf ("%02X: is %02X\n", i, status);
-       }
-}
-
-void
-video_dump_reg (void)
-{
-       int i;
-
-       printf ("Extended Regs:\n");
-       ctDispRegs (CT_XR_O, 0, 0xC);
-       ctDispRegs (CT_XR_O, 0xe, 0xf);
-       ctDispRegs (CT_XR_O, 0x20, 0x21);
-       ctDispRegs (CT_XR_O, 0x40, 0x50);
-       ctDispRegs (CT_XR_O, 0x60, 0x64);
-       ctDispRegs (CT_XR_O, 0x67, 0x68);
-       ctDispRegs (CT_XR_O, 0x70, 0x72);
-       ctDispRegs (CT_XR_O, 0x80, 0x83);
-       ctDispRegs (CT_XR_O, 0xA0, 0xB0);
-       ctDispRegs (CT_XR_O, 0xC0, 0xD3);
-       printf ("Sequencer Regs:\n");
-       ctDispRegs (CT_SR_O, 0, 0x8);
-       printf ("Graphic Regs:\n");
-       ctDispRegs (CT_GR_O, 0, 0x9);
-       printf ("CRT Regs:\n");
-       ctDispRegs (CT_CR_O, 0, 0x19);
-       ctDispRegs (CT_CR_O, 0x22, 0x23);
-       ctDispRegs (CT_CR_O, 0x30, 0x34);
-       ctDispRegs (CT_CR_O, 0x38, 0x39);
-       ctDispRegs (CT_CR_O, 0x3C, 0x3D);
-       ctDispRegs (CT_CR_O, 0x40, 0x42);
-       ctDispRegs (CT_CR_O, 0x70, 0x80);
-       /* don't display the attributes */
-}
-
-#endif
-
-/***************************************************************
- * Wait for BitBlt ready
- */
-static int
-video_wait_bitblt (unsigned long addr)
-{
-       unsigned long br04;
-       int i = 0;
-       br04 = in32r (addr);
-       while (br04 & 0x80000000) {
-               udelay (1);
-               br04 = in32r (addr);
-               if (i++ > 1000000) {
-                       printf ("ERROR Timeout %lx\n", br04);
-                       return 1;
-               }
-       }
-       return 0;
-}
-
-/***************************************************************
- * Set up BitBlt Registrs
- */
-static void
-SetDrawingEngine (int bits_per_pixel)
-{
-       unsigned long br04, br00;
-       unsigned char tmp;
-
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-
-       tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */
-       tmp |= 0x02;            /* reset BitBLT */
-       ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
-       udelay (10);
-       tmp &= 0xfd;            /* release reset BitBLT */
-       ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
-       video_wait_bitblt (pGD->pciBase + BR04_o);
-
-       /* set pattern Address */
-       out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8);
-       br04 = 0;
-       if (bits_per_pixel == 1) {
-               br04 |= 0x00040000;     /* monochome Pattern */
-               br04 |= 0x00001000;     /* monochome source */
-       }
-       br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP);   /* bytes per scanline */
-       out32r (pGD->pciBase + BR00_o, br00);   /* */
-       out32r (pGD->pciBase + BR08_o, (10 << 16) + 10);        /* dummy */
-       out32r (pGD->pciBase + BR04_o, br04);   /* write all 0 */
-       out32r (pGD->pciBase + BR07_o, 0);      /* destination */
-       video_wait_bitblt (pGD->pciBase + BR04_o);
-}
-
-/****************************************************************************
-* supported Video Chips
-*/
-static struct pci_device_id supported[] = {
-       {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
-       {}
-};
-
-/*******************************************************************************
-*
-* Init video chip
-*/
-void *
-video_hw_init (void)
-{
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-       unsigned short device_id;
-       pci_dev_t devbusfn;
-       int videomode;
-       unsigned long t1, hsynch, vsynch;
-       unsigned int pci_mem_base, *vm;
-       int tmp, i, bits_per_pixel;
-       char *penv;
-       struct ctfb_res_modes *res_mode;
-       struct ctfb_res_modes var_mode;
-       struct ctfb_chips_properties *chips_param;
-       /* Search for video chip */
-
-       if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
-#ifdef CONFIG_VIDEO_ONBOARD
-               printf ("Video: Controller not found !\n");
-#endif
-               return (NULL);
-       }
-
-       /* PCI setup */
-       pci_write_config_dword (devbusfn, PCI_COMMAND,
-                               (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
-       pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
-       pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
-       pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
-
-       /* get chips params */
-       for (chips_param = (struct ctfb_chips_properties *) &chips[0];
-            chips_param->device_id != 0; chips_param++) {
-               if (chips_param->device_id == device_id)
-                       break;
-       }
-       if (chips_param->device_id == 0) {
-#ifdef CONFIG_VIDEO_ONBOARD
-               printf ("Video: controller 0x%X not supported\n", device_id);
-#endif
-               return NULL;
-       }
-       /* supported Video controller found */
-       printf ("Video: ");
-
-       tmp = 0;
-       videomode = 0x301;
-       /* get video mode via environment */
-       if ((penv = getenv ("videomode")) != NULL) {
-               /* deceide if it is a string */
-               if (penv[0] <= '9') {
-                       videomode = (int) simple_strtoul (penv, NULL, 16);
-                       tmp = 1;
-               }
-       } else {
-               tmp = 1;
-       }
-       if (tmp) {
-               /* parameter are vesa modes */
-               /* search params */
-               for (i = 0; i < VESA_MODES_COUNT; i++) {
-                       if (vesa_modes[i].vesanr == videomode)
-                               break;
-               }
-               if (i == VESA_MODES_COUNT) {
-                       printf ("no VESA Mode found, switching to mode 0x301 ");
-                       i = 0;
-               }
-               res_mode =
-                   (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
-                                                            resindex];
-               bits_per_pixel = vesa_modes[i].bits_per_pixel;
-       } else {
-
-               res_mode = (struct ctfb_res_modes *) &var_mode;
-               bits_per_pixel = video_get_params (res_mode, penv);
-       }
-
-       /* calculate available color depth for controller memory */
-       if (bits_per_pixel == 15)
-               tmp = 2;
-       else
-               tmp = bits_per_pixel >> 3;      /* /8 */
-       if (((chips_param->max_mem -
-             ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) {
-               tmp =
-                   ((chips_param->max_mem -
-                     ACCELMEMORY) / (res_mode->xres * res_mode->yres));
-               if (tmp == 0) {
-                       printf
-                           ("No matching videomode found .-> reduce resolution\n");
-                       return NULL;
-               } else {
-                       printf ("Switching back to %d Bits per Pixel ",
-                               tmp << 3);
-                       bits_per_pixel = tmp << 3;
-               }
-       }
-
-       /* calculate hsynch and vsynch freq (info only) */
-       t1 = (res_mode->left_margin + res_mode->xres +
-             res_mode->right_margin + res_mode->hsync_len) / 8;
-       t1 *= 8;
-       t1 *= res_mode->pixclock;
-       t1 /= 1000;
-       hsynch = 1000000000L / t1;
-       t1 *=
-           (res_mode->upper_margin + res_mode->yres +
-            res_mode->lower_margin + res_mode->vsync_len);
-       t1 /= 1000;
-       vsynch = 1000000000L / t1;
-
-       /* fill in Graphic device struct */
-       sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
-                res_mode->yres, bits_per_pixel, (hsynch / 1000),
-                (vsynch / 1000));
-       printf ("%s\n", pGD->modeIdent);
-       pGD->winSizeX = res_mode->xres;
-       pGD->winSizeY = res_mode->yres;
-       pGD->plnSizeX = res_mode->xres;
-       pGD->plnSizeY = res_mode->yres;
-       switch (bits_per_pixel) {
-       case 8:
-               pGD->gdfBytesPP = 1;
-               pGD->gdfIndex = GDF__8BIT_INDEX;
-               break;
-       case 15:
-               pGD->gdfBytesPP = 2;
-               pGD->gdfIndex = GDF_15BIT_555RGB;
-               break;
-       case 16:
-               pGD->gdfBytesPP = 2;
-               pGD->gdfIndex = GDF_16BIT_565RGB;
-               break;
-       case 24:
-               pGD->gdfBytesPP = 3;
-               pGD->gdfIndex = GDF_24BIT_888RGB;
-               break;
-       }
-       pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
-       pGD->pciBase = pci_mem_base;
-       pGD->frameAdrs = pci_mem_base;
-       pGD->memSize = chips_param->max_mem;
-       /* Cursor Start Address */
-       pGD->dprBase =
-           (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base;
-       if ((pGD->dprBase & 0x0fff) != 0) {
-               /* allign it */
-               pGD->dprBase &= 0xfffff000;
-               pGD->dprBase += 0x00001000;
-       }
-       debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
-               PATTERN_ADR);
-       pGD->vprBase = pci_mem_base;    /* Dummy */
-       pGD->cprBase = pci_mem_base;    /* Dummy */
-       /* set up Hardware */
-
-       ctWrite (CT_MSR_W_O, 0x01);
-
-       /* set the extended Registers */
-       ctLoadRegs (CT_XR_O, xreg);
-       /* set atribute registers */
-       SetArRegs ();
-       /* set Graphics register */
-       SetGrRegs ();
-       /* set sequencer */
-       SetSrRegs ();
-
-       /* set msr */
-       SetMsrRegs (res_mode);
-
-       /* set CRT Registers */
-       SetCrRegs (res_mode, bits_per_pixel);
-       /* set color mode */
-       SetBitsPerPixelIntoXrRegs (bits_per_pixel);
-
-       /* set PLL */
-       FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param);
-
-       ctWrite_i (CT_SR_O, 0, 0x03);   /* clear synchronous reset */
-       /* Clear video memory */
-       i = pGD->memSize / 4;
-       vm = (unsigned int *) pGD->pciBase;
-       while (i--)
-               *vm++ = 0;
-       SetDrawingEngine (bits_per_pixel);
-#ifdef VGA_DUMP_REG
-       video_dump_reg ();
-#endif
-
-       return ((void *) &ctfb);
-}
-
- /*******************************************************************************
-*
-* Set a RGB color in the LUT (8 bit index)
-*/
-void
-video_set_lut (unsigned int index,     /* color number */
-              unsigned char r, /* red */
-              unsigned char g, /* green */
-              unsigned char b  /* blue */
-    )
-{
-
-       ctWrite (CT_LUT_MASK_O, 0xff);
-
-       ctWrite (CT_LUT_START_O, (char) index);
-
-       ctWrite (CT_LUT_RGB_O, r);      /* red */
-       ctWrite (CT_LUT_RGB_O, g);      /* green */
-       ctWrite (CT_LUT_RGB_O, b);      /* blue */
-       udelay (1);
-       ctWrite (CT_LUT_MASK_O, 0xff);
-}
-
-/*******************************************************************************
-*
-* Drawing engine fill on screen region
-*/
-void
-video_hw_rectfill (unsigned int bpp,   /* bytes per pixel */
-                  unsigned int dst_x,  /* dest pos x */
-                  unsigned int dst_y,  /* dest pos y */
-                  unsigned int dim_x,  /* frame width */
-                  unsigned int dim_y,  /* frame height */
-                  unsigned int color   /* fill color */
-    )
-{
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-       unsigned long *p, br04;
-
-       video_wait_bitblt (pGD->pciBase + BR04_o);
-
-       p = (unsigned long *) PATTERN_ADR;
-       dim_x *= bpp;
-       if (bpp == 3)
-               bpp++;          /* 24Bit needs a 32bit pattern */
-       memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8));      /* 8 x 8 pattern data */
-       out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP);    /* destination */
-       br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00;
-       br04 |= 0xF0;           /* write Pattern P -> D */
-       out32r (pGD->pciBase + BR04_o, br04);   /* */
-       out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x);  /* starts the BITBlt */
-       video_wait_bitblt (pGD->pciBase + BR04_o);
-}
-
-/*******************************************************************************
-*
-* Drawing engine bitblt with screen region
-*/
-void
-video_hw_bitblt (unsigned int bpp,     /* bytes per pixel */
-                unsigned int src_x,    /* source pos x */
-                unsigned int src_y,    /* source pos y */
-                unsigned int dst_x,    /* dest pos x */
-                unsigned int dst_y,    /* dest pos y */
-                unsigned int dim_x,    /* frame width */
-                unsigned int dim_y     /* frame height */
-    )
-{
-       GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-       unsigned long br04;
-
-       br04 = in32r (pGD->pciBase + BR04_o);
-
-       /* to prevent data corruption due to overlap, we have to
-        * find out if, and how the frames overlaps */
-       if (src_x < dst_x) {
-               /* src is more left than dest
-                * the frame may overlap -> start from right to left */
-               br04 |= 0x00000100;     /* set bit 8 */
-               src_x += dim_x;
-               dst_x += dim_x;
-       } else {
-               br04 &= 0xfffffeff;     /* clear bit 8 left to right */
-       }
-       if (src_y < dst_y) {
-               /* src is higher than dst
-                * the frame may overlap => start from bottom */
-               br04 |= 0x00000200;     /* set bit 9 */
-               src_y += dim_y;
-               dst_y += dim_y;
-       } else {
-               br04 &= 0xfffffdff;     /* clear bit 9 top to bottom */
-       }
-       dim_x *= bpp;
-       out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP);    /* source */
-       out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP);    /* destination */
-       br04 &= 0xffffff00;
-       br04 |= 0x000000CC;     /* S -> D */
-       out32r (pGD->pciBase + BR04_o, br04);   /* */
-       out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x);  /* start the BITBlt */
-       video_wait_bitblt (pGD->pciBase + BR04_o);
-}
-#endif                         /* CONFIG_VIDEO */
diff --git a/drivers/video/l5f31188.c b/drivers/video/l5f31188.c
deleted file mode 100644 (file)
index 3312dcf..0000000
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
- * Hyungwon Hwang <human.hwang@samsung.com>
- *
- * SPDX-License-Identifier:      GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/mipi_dsim.h>
-
-#define SCAN_FROM_LEFT_TO_RIGHT 0
-#define SCAN_FROM_RIGHT_TO_LEFT 1
-#define SCAN_FROM_TOP_TO_BOTTOM 0
-#define SCAN_FROM_BOTTOM_TO_TOP 1
-
-static void l5f31188_sleep_in(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x10, 0x00);
-}
-
-static void l5f31188_sleep_out(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
-}
-
-static void l5f31188_set_gamma(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x26, 0x00);
-}
-
-static void l5f31188_display_off(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x28, 0x00);
-}
-
-static void l5f31188_display_on(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
-}
-
-static void l5f31188_ctl_memory_access(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops,
-               int h_direction, int v_direction)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x36,
-                       (((h_direction & 0x1) << 1) | (v_direction & 0x1)));
-}
-
-static void l5f31188_set_pixel_format(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x3A, 0x70);
-}
-
-static void l5f31188_write_disbv(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops, unsigned int brightness)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x51, brightness);
-}
-
-static void l5f31188_write_ctrld(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x53, 0x2C);
-}
-
-static void l5f31188_write_cabc(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops,
-                       unsigned int wm_mode)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x55, wm_mode);
-}
-
-static void l5f31188_write_cabcmb(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops, unsigned int min_brightness)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x5E,
-                       min_brightness);
-}
-
-static void l5f31188_set_extension(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       const unsigned char data_to_send[] = {
-               0xB9, 0xFF, 0x83, 0x94
-       };
-
-       ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
-                       (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void l5f31188_set_dgc_lut(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       const unsigned char data_to_send[] = {
-               0xC1, 0x01, 0x00, 0x04, 0x0E, 0x18, 0x1E, 0x26,
-               0x2F, 0x36, 0x3E, 0x47, 0x4E, 0x56, 0x5D, 0x65,
-               0x6D, 0x75, 0x7D, 0x84, 0x8C, 0x94, 0x9C, 0xA4,
-               0xAD, 0xB5, 0xBD, 0xC5, 0xCC, 0xD4, 0xDE, 0xE5,
-               0xEE, 0xF7, 0xFF, 0x3F, 0x9A, 0xCE, 0xD4, 0x21,
-               0xA1, 0x26, 0x54, 0x00, 0x00, 0x04, 0x0E, 0x19,
-               0x1F, 0x27, 0x30, 0x37, 0x40, 0x48, 0x50, 0x58,
-               0x60, 0x67, 0x6F, 0x77, 0x7F, 0x87, 0x8F, 0x97,
-               0x9F, 0xA7, 0xB0, 0xB8, 0xC0, 0xC8, 0xCE, 0xD8,
-               0xE0, 0xE7, 0xF0, 0xF7, 0xFF, 0x3C, 0xEB, 0xFD,
-               0x2F, 0x66, 0xA8, 0x2C, 0x46, 0x00, 0x00, 0x04,
-               0x0E, 0x18, 0x1E, 0x26, 0x30, 0x38, 0x41, 0x4A,
-               0x52, 0x5A, 0x62, 0x6B, 0x73, 0x7B, 0x83, 0x8C,
-               0x94, 0x9C, 0xA5, 0xAD, 0xB6, 0xBD, 0xC5, 0xCC,
-               0xD4, 0xDD, 0xE3, 0xEB, 0xF2, 0xF9, 0xFF, 0x3F,
-               0xA4, 0x8A, 0x8F, 0xC7, 0x33, 0xF5, 0xE9, 0x00
-       };
-       ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
-                       (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void l5f31188_set_tcon(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       const unsigned char data_to_send[] = {
-               0xC7, 0x00, 0x20
-       };
-       ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
-                       (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void l5f31188_set_ptba(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       const unsigned char data_to_send[] = {
-               0xBF, 0x06, 0x10
-       };
-       ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
-                       (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void l5f31188_set_eco(struct mipi_dsim_device *dev,
-               struct mipi_dsim_master_ops *ops)
-{
-       ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xC6, 0x0C);
-}
-
-static int l5f31188_panel_init(struct mipi_dsim_device *dev)
-{
-       struct mipi_dsim_master_ops *ops = dev->master_ops;
-
-       l5f31188_set_extension(dev, ops);
-       l5f31188_set_dgc_lut(dev, ops);
-
-       l5f31188_set_eco(dev, ops);
-       l5f31188_set_tcon(dev, ops);
-       l5f31188_set_ptba(dev, ops);
-       l5f31188_set_gamma(dev, ops);
-       l5f31188_ctl_memory_access(dev, ops,
-                       SCAN_FROM_LEFT_TO_RIGHT, SCAN_FROM_TOP_TO_BOTTOM);
-       l5f31188_set_pixel_format(dev, ops);
-       l5f31188_write_disbv(dev, ops, 0xFF);
-       l5f31188_write_ctrld(dev, ops);
-       l5f31188_write_cabc(dev, ops, 0x0);
-       l5f31188_write_cabcmb(dev, ops, 0x0);
-
-       l5f31188_sleep_out(dev, ops);
-
-       /* 120 msec */
-       udelay(120 * 1000);
-
-       return 0;
-}
-
-static void l5f31188_display_enable(struct mipi_dsim_device *dev)
-{
-       struct mipi_dsim_master_ops *ops = dev->master_ops;
-       l5f31188_display_on(dev, ops);
-}
-
-static struct mipi_dsim_lcd_driver l5f31188_dsim_ddi_driver = {
-       .name = "l5f31188",
-       .id = -1,
-
-       .mipi_panel_init = l5f31188_panel_init,
-       .mipi_display_on = l5f31188_display_enable,
-};
-
-void l5f31188_init(void)
-{
-       exynos_mipi_dsi_register_lcd_driver(&l5f31188_dsim_ddi_driver);
-}
index 872dc0f..8005003 100644 (file)
@@ -14,5 +14,7 @@ obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
 obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o
 obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y)
-obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o
+obj-mipi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_mipi.o
+obj-mipi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_mipi.o
+obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o $(obj-mipi-y)
 endif
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
new file mode 100644 (file)
index 0000000..953b47f
--- /dev/null
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Eric Gao <eric.gao@rock-chips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <panel.h>
+#include <regmap.h>
+#include "rk_mipi.h"
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass-internal.h>
+#include <linux/kernel.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3288.h>
+#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/rockchip_mipi_dsi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MHz 1000000
+
+/* Select mipi dsi source, big or little vop */
+static int rk_mipi_dsi_source_select(struct udevice *dev)
+{
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+       struct rk3288_grf *grf = priv->grf;
+       struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+
+       /* Select the video source */
+       switch (disp_uc_plat->source_id) {
+       case VOP_B:
+               rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
+                            RK3288_DSI0_LCDC_SEL_BIG
+                            << RK3288_DSI0_LCDC_SEL_SHIFT);
+               break;
+       case VOP_L:
+               rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
+                            RK3288_DSI0_LCDC_SEL_LIT
+                            << RK3288_DSI0_LCDC_SEL_SHIFT);
+               break;
+       default:
+               debug("%s: Invalid VOP id\n", __func__);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+/* Setup mipi dphy working mode */
+static void rk_mipi_dphy_mode_set(struct udevice *dev)
+{
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+       struct rk3288_grf *grf = priv->grf;
+       int val;
+
+       /* Set Controller as TX mode */
+       val = RK3288_DPHY_TX0_RXMODE_DIS << RK3288_DPHY_TX0_RXMODE_SHIFT;
+       rk_clrsetreg(&grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val);
+
+       /* Exit tx stop mode */
+       val |= RK3288_DPHY_TX0_TXSTOPMODE_EN
+                       << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT;
+       rk_clrsetreg(&grf->soc_con8,
+                    RK3288_DPHY_TX0_TXSTOPMODE_MASK, val);
+
+       /* Disable turnequest */
+       val |= RK3288_DPHY_TX0_TURNREQUEST_EN
+               << RK3288_DPHY_TX0_TURNREQUEST_SHIFT;
+       rk_clrsetreg(&grf->soc_con8,
+                    RK3288_DPHY_TX0_TURNREQUEST_MASK, val);
+}
+
+/*
+ * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
+ * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
+ * enable backlight.
+ */
+static int rk_mipi_enable(struct udevice *dev, int panel_bpp,
+                         const struct display_timing *timing)
+{
+       int ret;
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+       /* Fill the mipi controller parameter */
+       priv->ref_clk = 24 * MHz;
+       priv->sys_clk = priv->ref_clk;
+       priv->pix_clk = timing->pixelclock.typ;
+       priv->phy_clk = priv->pix_clk * 6;
+       priv->txbyte_clk = priv->phy_clk / 8;
+       priv->txesc_clk = 20 * MHz;
+
+       /* Select vop port, big or little */
+       rk_mipi_dsi_source_select(dev);
+
+       /* Set mipi dphy work mode */
+       rk_mipi_dphy_mode_set(dev);
+
+       /* Config  and enable mipi dsi according to timing */
+       ret = rk_mipi_dsi_enable(dev, timing);
+       if (ret) {
+               debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
+                     __func__, ret);
+               return ret;
+       }
+
+       /* Config and enable mipi phy */
+       ret = rk_mipi_phy_enable(dev);
+       if (ret) {
+               debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
+                     __func__, ret);
+               return ret;
+       }
+
+       /* Enable backlight */
+       ret = panel_enable_backlight(priv->panel);
+       if (ret) {
+               debug("%s: panel_enable_backlight() failed (err=%d)\n",
+                     __func__, ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
+{
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+       priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+       if (IS_ERR(priv->grf)) {
+               debug("%s: Get syscon grf failed (ret=%p)\n",
+                     __func__, priv->grf);
+               return  -ENXIO;
+       }
+       priv->regs = dev_read_addr(dev);
+       if (priv->regs == FDT_ADDR_T_NONE) {
+               debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__,
+                     priv->regs);
+               return  -ENXIO;
+       }
+
+       return 0;
+}
+
+/*
+ * Probe function: check panel existence and readingit's timing. Then config
+ * mipi dsi controller and enable it according to the timing parameter.
+ */
+static int rk_mipi_probe(struct udevice *dev)
+{
+       int ret;
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+       ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
+                                          &priv->panel);
+       if (ret) {
+               debug("%s: Can not find panel (err=%d)\n", __func__, ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+static const struct dm_display_ops rk_mipi_dsi_ops = {
+       .read_timing = rk_mipi_read_timing,
+       .enable = rk_mipi_enable,
+};
+
+static const struct udevice_id rk_mipi_dsi_ids[] = {
+       { .compatible = "rockchip,rk3288_mipi_dsi" },
+       { }
+};
+
+U_BOOT_DRIVER(rk_mipi_dsi) = {
+       .name   = "rk_mipi_dsi",
+       .id     = UCLASS_DISPLAY,
+       .of_match = rk_mipi_dsi_ids,
+       .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
+       .probe  = rk_mipi_probe,
+       .ops    = &rk_mipi_dsi_ops,
+       .priv_auto_alloc_size   = sizeof(struct rk_mipi_priv),
+};
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
new file mode 100644 (file)
index 0000000..9ef202b
--- /dev/null
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Eric Gao <eric.gao@rock-chips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <panel.h>
+#include <regmap.h>
+#include "rk_mipi.h"
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass-internal.h>
+#include <linux/kernel.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/grf_rk3399.h>
+#include <asm/arch/rockchip_mipi_dsi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Select mipi dsi source, big or little vop */
+static int rk_mipi_dsi_source_select(struct udevice *dev)
+{
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+       struct rk3399_grf_regs *grf = priv->grf;
+       struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+
+       /* Select the video source */
+       switch (disp_uc_plat->source_id) {
+       case VOP_B:
+               rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
+                            GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
+               break;
+       case VOP_L:
+               rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
+                            GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
+               break;
+       default:
+               debug("%s: Invalid VOP id\n", __func__);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+/* Setup mipi dphy working mode */
+static void rk_mipi_dphy_mode_set(struct udevice *dev)
+{
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+       struct rk3399_grf_regs *grf = priv->grf;
+       int val;
+
+       /* Set Controller as TX mode */
+       val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
+       rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
+
+       /* Exit tx stop mode */
+       val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
+       rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
+
+       /* Disable turnequest */
+       val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
+       rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
+}
+
+/*
+ * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
+ * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
+ * enable backlight.
+ */
+static int rk_display_enable(struct udevice *dev, int panel_bpp,
+                         const struct display_timing *timing)
+{
+       int ret;
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+       /* Fill the mipi controller parameter */
+       priv->ref_clk = 24 * MHz;
+       priv->sys_clk = priv->ref_clk;
+       priv->pix_clk = timing->pixelclock.typ;
+       priv->phy_clk = priv->pix_clk * 6;
+       priv->txbyte_clk = priv->phy_clk / 8;
+       priv->txesc_clk = 20 * MHz;
+
+       /* Select vop port, big or little */
+       rk_mipi_dsi_source_select(dev);
+
+       /* Set mipi dphy work mode */
+       rk_mipi_dphy_mode_set(dev);
+
+       /* Config  and enable mipi dsi according to timing */
+       ret = rk_mipi_dsi_enable(dev, timing);
+       if (ret) {
+               debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
+                     __func__, ret);
+               return ret;
+       }
+
+       /* Config and enable mipi phy */
+       ret = rk_mipi_phy_enable(dev);
+       if (ret) {
+               debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
+                     __func__, ret);
+               return ret;
+       }
+
+       /* Enable backlight */
+       ret = panel_enable_backlight(priv->panel);
+       if (ret) {
+               debug("%s: panel_enable_backlight() failed (err=%d)\n",
+                     __func__, ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
+{
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+       priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+       if (priv->grf <= 0) {
+               debug("%s: Get syscon grf failed (ret=%p)\n",
+                     __func__, priv->grf);
+               return  -ENXIO;
+       }
+       priv->regs = dev_read_addr(dev);
+       if (priv->regs == FDT_ADDR_T_NONE) {
+               debug("%s: Get MIPI dsi address failed\n", __func__);
+               return  -ENXIO;
+       }
+
+       return 0;
+}
+
+/*
+ * Probe function: check panel existence and readingit's timing. Then config
+ * mipi dsi controller and enable it according to the timing parameter.
+ */
+static int rk_mipi_probe(struct udevice *dev)
+{
+       int ret;
+       struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+       ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
+                                          &priv->panel);
+       if (ret) {
+               debug("%s: Can not find panel (err=%d)\n", __func__, ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+static const struct dm_display_ops rk_mipi_dsi_ops = {
+       .read_timing = rk_mipi_read_timing,
+       .enable = rk_display_enable,
+};
+
+static const struct udevice_id rk_mipi_dsi_ids[] = {
+       { .compatible = "rockchip,rk3399_mipi_dsi" },
+       { }
+};
+
+U_BOOT_DRIVER(rk_mipi_dsi) = {
+       .name   = "rk_mipi_dsi",
+       .id     = UCLASS_DISPLAY,
+       .of_match = rk_mipi_dsi_ids,
+       .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
+       .probe  = rk_mipi_probe,
+       .ops    = &rk_mipi_dsi_ops,
+       .priv_auto_alloc_size   = sizeof(struct rk_mipi_priv),
+};
index 1199a30..d537755 100644 (file)
@@ -12,6 +12,7 @@
 #include <fdtdec.h>
 #include <panel.h>
 #include <regmap.h>
+#include "rk_mipi.h"
 #include <syscon.h>
 #include <asm/gpio.h>
 #include <asm/hardware.h>
 #include <asm/arch/cru_rk3399.h>
 #include <asm/arch/grf_rk3399.h>
 #include <asm/arch/rockchip_mipi_dsi.h>
-#include <dt-bindings/clock/rk3288-cru.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Private information for rk mipi
- *
- * @regs: mipi controller address
- * @grf: GRF register
- * @panel: panel assined by device tree
- * @ref_clk: reference clock for mipi dsi pll
- * @sysclk: config clock for mipi dsi register
- * @pix_clk: pixel clock for vop->dsi data transmission
- * @phy_clk: mipi dphy output clock
- * @txbyte_clk: clock for dsi->dphy high speed data transmission
- * @txesc_clk: clock for tx esc mode
- */
-struct rk_mipi_priv {
-       uintptr_t regs;
-       struct rk3399_grf_regs *grf;
-       struct udevice *panel;
-       struct mipi_dsi *dsi;
-       u32 ref_clk;
-       u32 sys_clk;
-       u32 pix_clk;
-       u32 phy_clk;
-       u32 txbyte_clk;
-       u32 txesc_clk;
-};
-
-static int rk_mipi_read_timing(struct udevice *dev,
-                              struct display_timing *timing)
+int rk_mipi_read_timing(struct udevice *dev,
+                       struct display_timing *timing)
 {
        int ret;
 
@@ -102,46 +76,18 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
        writel(dat, addr);
 }
 
-static int rk_mipi_dsi_enable(struct udevice *dev,
-                             const struct display_timing *timing)
+int rk_mipi_dsi_enable(struct udevice *dev,
+                      const struct display_timing *timing)
 {
        int node, timing_node;
        int val;
        struct rk_mipi_priv *priv = dev_get_priv(dev);
        uintptr_t regs = priv->regs;
-       struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
        u32 txbyte_clk = priv->txbyte_clk;
        u32 txesc_clk = priv->txesc_clk;
 
        txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
 
-       /* Select the video source */
-       switch (disp_uc_plat->source_id) {
-       case VOP_B:
-               rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
-                            GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
-                break;
-       case VOP_L:
-               rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
-                            GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
-                break;
-       default:
-                debug("%s: Invalid VOP id\n", __func__);
-                return -EINVAL;
-       }
-
-       /* Set Controller as TX mode */
-       val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
-       rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
-
-       /* Exit tx stop mode */
-       val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
-       rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
-
-       /* Disable turnequest */
-       val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
-       rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
-
        /* Set Display timing parameter */
        rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
        rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
@@ -249,7 +195,7 @@ static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,
  * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
  * and then enable phy.
  */
-static int rk_mipi_phy_enable(struct udevice *dev)
+int rk_mipi_phy_enable(struct udevice *dev)
 {
        int i;
        struct rk_mipi_priv *priv = dev_get_priv(dev);
@@ -385,107 +331,3 @@ static int rk_mipi_phy_enable(struct udevice *dev)
        return 0;
 }
 
-/*
- * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
- * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
- * enable backlight.
- */
-static int rk_display_enable(struct udevice *dev, int panel_bpp,
-                         const struct display_timing *timing)
-{
-       int ret;
-       struct rk_mipi_priv *priv = dev_get_priv(dev);
-
-       /* Fill the mipi controller parameter */
-       priv->ref_clk = 24 * MHz;
-       priv->sys_clk = priv->ref_clk;
-       priv->pix_clk = timing->pixelclock.typ;
-       priv->phy_clk = priv->pix_clk * 6;
-       priv->txbyte_clk = priv->phy_clk / 8;
-       priv->txesc_clk = 20 * MHz;
-
-       /* Config  and enable mipi dsi according to timing */
-       ret = rk_mipi_dsi_enable(dev, timing);
-       if (ret) {
-               debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
-                     __func__, ret);
-               return ret;
-       }
-
-       /* Config and enable mipi phy */
-       ret = rk_mipi_phy_enable(dev);
-       if (ret) {
-               debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
-                     __func__, ret);
-               return ret;
-       }
-
-       /* Enable backlight */
-       ret = panel_enable_backlight(priv->panel);
-       if (ret) {
-               debug("%s: panel_enable_backlight() failed (err=%d)\n",
-                     __func__, ret);
-               return ret;
-       }
-
-       return 0;
-}
-
-static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
-{
-       struct rk_mipi_priv *priv = dev_get_priv(dev);
-
-       priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-       if (priv->grf <= 0) {
-               debug("%s: Get syscon grf failed (ret=%p)\n",
-                     __func__, priv->grf);
-               return  -ENXIO;
-       }
-       priv->regs = devfdt_get_addr(dev);
-       if (priv->regs <= 0) {
-               debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__,
-                     priv->regs);
-               return  -ENXIO;
-       }
-
-       return 0;
-}
-
-/*
- * Probe function: check panel existence and readingit's timing. Then config
- * mipi dsi controller and enable it according to the timing parameter.
- */
-static int rk_mipi_probe(struct udevice *dev)
-{
-       int ret;
-       struct rk_mipi_priv *priv = dev_get_priv(dev);
-
-       ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
-                                          &priv->panel);
-       if (ret) {
-               debug("%s: Can not find panel (err=%d)\n", __func__, ret);
-               return ret;
-       }
-
-       return 0;
-}
-
-static const struct dm_display_ops rk_mipi_dsi_ops = {
-       .read_timing = rk_mipi_read_timing,
-       .enable = rk_display_enable,
-};
-
-static const struct udevice_id rk_mipi_dsi_ids[] = {
-       { .compatible = "rockchip,rk3399_mipi_dsi" },
-       { }
-};
-
-U_BOOT_DRIVER(rk_mipi_dsi) = {
-       .name   = "rk_mipi_dsi",
-       .id     = UCLASS_DISPLAY,
-       .of_match = rk_mipi_dsi_ids,
-       .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
-       .probe  = rk_mipi_probe,
-       .ops    = &rk_mipi_dsi_ops,
-       .priv_auto_alloc_size   = sizeof(struct rk_mipi_priv),
-};
diff --git a/drivers/video/rockchip/rk_mipi.h b/drivers/video/rockchip/rk_mipi.h
new file mode 100644 (file)
index 0000000..de6ac52
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Eric Gao <eric.gao@rock-chips.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __RK_MIPI_H
+#define __RK_MIPI_H
+
+struct rk_mipi_priv {
+       uintptr_t regs;
+       void *grf;
+       struct udevice *panel;
+       struct mipi_dsi *dsi;
+       u32 ref_clk;
+       u32 sys_clk;
+       u32 pix_clk;
+       u32 phy_clk;
+       u32 txbyte_clk;
+       u32 txesc_clk;
+};
+
+int rk_mipi_read_timing(struct udevice *dev,
+                              struct display_timing *timing);
+
+int rk_mipi_dsi_enable(struct udevice *dev,
+                             const struct display_timing *timing);
+
+int rk_mipi_phy_enable(struct udevice *dev);
+
+
+#endif
diff --git a/drivers/video/sed156x.c b/drivers/video/sed156x.c
deleted file mode 100644 (file)
index 2c906ec..0000000
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- * (C) Copyright 2003
- *
- * Pantelis Antoniou <panto@intracom.gr>
- * Intracom S.A.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-
-#include <sed156x.h>
-
-/* configure according to the selected display */
-#if defined(CONFIG_SED156X_PG12864Q)
-#define LCD_WIDTH      128
-#define LCD_HEIGHT     64
-#define LCD_LINES      64
-#define LCD_PAGES      9
-#define LCD_COLUMNS    132
-#else
-#error Unsupported SED156x configuration
-#endif
-
-/* include the font data */
-#include <video_font.h>
-
-#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16
-#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16
-#endif
-
-#define LCD_BYTE_WIDTH         (LCD_WIDTH / 8)
-#define VIDEO_FONT_BYTE_WIDTH  (VIDEO_FONT_WIDTH / 8)
-
-#define LCD_TEXT_WIDTH (LCD_WIDTH / VIDEO_FONT_WIDTH)
-#define LCD_TEXT_HEIGHT (LCD_HEIGHT / VIDEO_FONT_HEIGHT)
-
-#define LCD_BYTE_LINESZ                (LCD_BYTE_WIDTH * VIDEO_FONT_HEIGHT)
-
-const int sed156x_text_width = LCD_TEXT_WIDTH;
-const int sed156x_text_height = LCD_TEXT_HEIGHT;
-
-/**************************************************************************************/
-
-#define SED156X_SPI_RXD() (SED156X_SPI_RXD_PORT & SED156X_SPI_RXD_MASK)
-
-#define SED156X_SPI_TXD(x) \
-       do { \
-               if (x) \
-                       SED156X_SPI_TXD_PORT |=  SED156X_SPI_TXD_MASK; \
-               else \
-                       SED156X_SPI_TXD_PORT &= ~SED156X_SPI_TXD_MASK; \
-       } while(0)
-
-#define SED156X_SPI_CLK(x) \
-       do { \
-               if (x) \
-                       SED156X_SPI_CLK_PORT |=  SED156X_SPI_CLK_MASK; \
-               else \
-                       SED156X_SPI_CLK_PORT &= ~SED156X_SPI_CLK_MASK; \
-       } while(0)
-
-#define SED156X_SPI_CLK_TOGGLE() (SED156X_SPI_CLK_PORT ^= SED156X_SPI_CLK_MASK)
-
-#define SED156X_SPI_BIT_DELAY() /* no delay */
-
-#define SED156X_CS(x) \
-       do { \
-               if (x) \
-                       SED156X_CS_PORT |=  SED156X_CS_MASK; \
-               else \
-                       SED156X_CS_PORT &= ~SED156X_CS_MASK; \
-       } while(0)
-
-#define SED156X_A0(x) \
-       do { \
-               if (x) \
-                       SED156X_A0_PORT |=  SED156X_A0_MASK; \
-               else \
-                       SED156X_A0_PORT &= ~SED156X_A0_MASK; \
-       } while(0)
-
-/**************************************************************************************/
-
-/*** LCD Commands ***/
-
-#define LCD_ON         0xAF    /* Display ON                                         */
-#define LCD_OFF                0xAE    /* Display OFF                                        */
-#define LCD_LADDR      0x40    /* Display start line set + (6-bit) address           */
-#define LCD_PADDR      0xB0    /* Page address set + (4-bit) page                    */
-#define LCD_CADRH      0x10    /* Column address set upper + (4-bit) column hi       */
-#define LCD_CADRL      0x00    /* Column address set lower + (4-bit) column lo       */
-#define LCD_ADC_NRM    0xA0    /* ADC select Normal                                  */
-#define LCD_ADC_REV    0xA1    /* ADC select Reverse                                 */
-#define LCD_DSP_NRM    0xA6    /* LCD display Normal                                 */
-#define LCD_DSP_REV    0xA7    /* LCD display Reverse                                */
-#define LCD_DPT_NRM    0xA4    /* Display all points Normal                          */
-#define LCD_DPT_ALL    0xA5    /* Display all points ON                              */
-#define LCD_BIAS9      0xA2    /* LCD bias set 1/9                                   */
-#define LCD_BIAS7      0xA3    /* LCD bias set 1/7                                   */
-#define LCD_CAINC      0xE0    /* Read/modify/write                                  */
-#define LCD_CAEND      0xEE    /* End                                                */
-#define LCD_RESET      0xE2    /* Reset                                              */
-#define LCD_C_NRM      0xC0    /* Common output mode select Normal direction         */
-#define LCD_C_RVS      0xC8    /* Common output mode select Reverse direction        */
-#define LCD_PWRMD      0x28    /* Power control set + (3-bit) mode                   */
-#define LCD_RESRT      0x20    /* V5 v. reg. int. resistor ratio set + (3-bit) ratio */
-#define LCD_EVSET      0x81    /* Electronic volume mode set + byte = (6-bit) volume */
-#define LCD_SIOFF      0xAC    /* Static indicator OFF                               */
-#define LCD_SION       0xAD    /* Static indicator ON + byte = (2-bit) mode          */
-#define LCD_NOP                0xE3    /* NOP                                                */
-#define LCD_TEST       0xF0    /* Test/Test mode reset (Note: *DO NOT USE*)          */
-
-/*-------------------------------------------------------------------------------
-  Compound commands
-  -------------------------------------------------------------------------------
-  Command      Description                     Commands
-  ----------   ------------------------        -------------------------------------
-  POWS_ON      POWER SAVER ON command          LCD_OFF, LCD_D_ALL
-  POWS_OFF     POWER SAVER OFF command         LCD_D_NRM
-  SLEEPON      SLEEP mode                      LCD_SIOFF, POWS_ON
-  SLEEPOFF     SLEEP mode cancel               LCD_D_NRM, LCD_SION, LCD_SIS_???
-  STDBYON      STAND BY mode                   LCD_SION, POWS_ON
-  STDBYOFF     STAND BY mode cancel            LCD_D_NRM
-  -------------------------------------------------------------------------------*/
-
-/*** LCD various parameters ***/
-#define LCD_PPB                8       /* Pixels per byte (display is B/W, 1 bit per pixel) */
-
-/*** LCD Status byte masks ***/
-#define LCD_S_BUSY     0x80    /* Status Read - BUSY mask   */
-#define LCD_S_ADC      0x40    /* Status Read - ADC mask    */
-#define LCD_S_ONOFF    0x20    /* Status Read - ON/OFF mask */
-#define LCD_S_RESET    0x10    /* Status Read - RESET mask  */
-
-/*** LCD commands parameter masks ***/
-#define LCD_M_LADDR    0x3F    /* Display start line (6-bit) address mask           */
-#define LCD_M_PADDR    0x0F    /* Page address (4-bit) page mask                    */
-#define LCD_M_CADRH    0x0F    /* Column address upper (4-bit) column hi mask       */
-#define LCD_M_CADRL    0x0F    /* Column address lower (4-bit) column lo mask       */
-#define LCD_M_PWRMD    0x07    /* Power control (3-bit) mode mask                   */
-#define LCD_M_RESRT    0x07    /* V5 v. reg. int. resistor ratio (3-bit) ratio mask */
-#define LCD_M_EVSET    0x3F    /* Electronic volume mode byte (6-bit) volume mask   */
-#define LCD_M_SION     0x03    /* Static indicator ON (2-bit) mode mask             */
-
-/*** LCD Power control cirquits control masks ***/
-#define LCD_PWRBSTR    0x04    /* Power control mode - Booster cirquit ON           */
-#define LCD_PWRVREG    0x02    /* Power control mode - Voltage regulator cirquit ON */
-#define LCD_PWRVFOL    0x01    /* Power control mode - Voltage follower cirquit ON  */
-
-/*** LCD Static indicator states ***/
-#define LCD_SIS_OFF    0x00    /* Static indicator register set - OFF state             */
-#define LCD_SIS_BL     0x01    /* Static indicator register set - 1s blink state        */
-#define LCD_SIS_RBL    0x02    /* Static indicator register set - .5s rapid blink state */
-#define LCD_SIS_ON     0x03    /* Static indicator register set - constantly on state   */
-
-/*** LCD functions special parameters (commands) ***/
-#define LCD_PREVP      0x80    /* Page number for moving to previous */
-#define LCD_NEXTP      0x81    /* or next page */
-#define LCD_ERR_P      0xFF    /* Error in page number */
-
-/*** LCD initialization settings ***/
-#define LCD_BIAS       LCD_BIAS9       /* Bias: 1/9                  */
-#define LCD_ADCMODE    LCD_ADC_NRM     /* ADC mode: normal           */
-#define LCD_COMDIR     LCD_C_NRM       /* Common output mode: normal */
-#define LCD_RRATIO     0               /* Resistor ratio: 0          */
-#define LCD_CNTRST     0x1C            /* electronic volume: 1Ch     */
-#define LCD_POWERM     (LCD_PWRBSTR | LCD_PWRVREG | LCD_PWRVFOL)       /* Power mode: All on */
-
-/**************************************************************************************/
-
-static inline unsigned int sed156x_transfer(unsigned int val)
-{
-       unsigned int rx;
-       int b;
-
-       rx = 0; b = 8;
-       while (--b >= 0) {
-               SED156X_SPI_TXD(val & 0x80);
-               val <<= 1;
-               SED156X_SPI_CLK_TOGGLE();
-               SED156X_SPI_BIT_DELAY();
-               rx <<= 1;
-               if (SED156X_SPI_RXD())
-                       rx |= 1;
-               SED156X_SPI_CLK_TOGGLE();
-               SED156X_SPI_BIT_DELAY();
-       }
-
-       return rx;
-}
-
-unsigned int sed156x_data_transfer(unsigned int val)
-{
-       unsigned int rx;
-
-       SED156X_SPI_CLK(1);
-       SED156X_CS(0);
-       SED156X_A0(1);
-
-       rx = sed156x_transfer(val);
-
-       SED156X_CS(1);
-
-       return rx;
-}
-
-void sed156x_data_block_transfer(const u8 *p, int size)
-{
-       SED156X_SPI_CLK(1);
-       SED156X_CS(0);
-       SED156X_A0(1);
-
-       while (--size >= 0)
-               sed156x_transfer(*p++);
-
-       SED156X_CS(1);
-}
-
-unsigned int sed156x_cmd_transfer(unsigned int val)
-{
-       unsigned int rx;
-
-       SED156X_SPI_CLK(1);
-       SED156X_CS(0);
-       SED156X_A0(0);
-
-       rx = sed156x_transfer(val);
-
-       SED156X_CS(1);
-       SED156X_A0(1);
-
-       return rx;
-}
-
-/******************************************************************************/
-
-static u8 hw_screen[LCD_PAGES][LCD_COLUMNS];
-static u8 last_hw_screen[LCD_PAGES][LCD_COLUMNS];
-static u8 sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT];
-
-void sed156x_sync(void)
-{
-       int i, j, last_page;
-       u8 *d;
-       const u8 *s, *e, *b, *r;
-       u8 v0, v1, v2, v3, v4, v5, v6, v7;
-
-       /* copy and rotate sw_screen to hw_screen */
-       for (i = 0; i < LCD_HEIGHT / 8; i++) {
-
-               d = &hw_screen[i][0];
-               s = &sw_screen[LCD_BYTE_WIDTH * 8 * i + LCD_BYTE_WIDTH - 1];
-
-               for (j = 0; j < LCD_WIDTH / 8; j++) {
-
-                       v0 = s[0 * LCD_BYTE_WIDTH];
-                       v1 = s[1 * LCD_BYTE_WIDTH];
-                       v2 = s[2 * LCD_BYTE_WIDTH];
-                       v3 = s[3 * LCD_BYTE_WIDTH];
-                       v4 = s[4 * LCD_BYTE_WIDTH];
-                       v5 = s[5 * LCD_BYTE_WIDTH];
-                       v6 = s[6 * LCD_BYTE_WIDTH];
-                       v7 = s[7 * LCD_BYTE_WIDTH];
-
-                       d[0] =  ((v7 & 0x01) << 7) |
-                               ((v6 & 0x01) << 6) |
-                               ((v5 & 0x01) << 5) |
-                               ((v4 & 0x01) << 4) |
-                               ((v3 & 0x01) << 3) |
-                               ((v2 & 0x01) << 2) |
-                               ((v1 & 0x01) << 1) |
-                                (v0 & 0x01)       ;
-
-                       d[1] =  ((v7 & 0x02) << 6) |
-                               ((v6 & 0x02) << 5) |
-                               ((v5 & 0x02) << 4) |
-                               ((v4 & 0x02) << 3) |
-                               ((v3 & 0x02) << 2) |
-                               ((v2 & 0x02) << 1) |
-                               ((v1 & 0x02) << 0) |
-                               ((v0 & 0x02) >> 1) ;
-
-                       d[2] =  ((v7 & 0x04) << 5) |
-                               ((v6 & 0x04) << 4) |
-                               ((v5 & 0x04) << 3) |
-                               ((v4 & 0x04) << 2) |
-                               ((v3 & 0x04) << 1) |
-                                (v2 & 0x04)       |
-                               ((v1 & 0x04) >> 1) |
-                               ((v0 & 0x04) >> 2) ;
-
-                       d[3] =  ((v7 & 0x08) << 4) |
-                               ((v6 & 0x08) << 3) |
-                               ((v5 & 0x08) << 2) |
-                               ((v4 & 0x08) << 1) |
-                                (v3 & 0x08)       |
-                               ((v2 & 0x08) >> 1) |
-                               ((v1 & 0x08) >> 2) |
-                               ((v0 & 0x08) >> 3) ;
-
-                       d[4] =  ((v7 & 0x10) << 3) |
-                               ((v6 & 0x10) << 2) |
-                               ((v5 & 0x10) << 1) |
-                                (v4 & 0x10)       |
-                               ((v3 & 0x10) >> 1) |
-                               ((v2 & 0x10) >> 2) |
-                               ((v1 & 0x10) >> 3) |
-                               ((v0 & 0x10) >> 4) ;
-
-                       d[5] =  ((v7 & 0x20) << 2) |
-                               ((v6 & 0x20) << 1) |
-                                (v5 & 0x20)       |
-                               ((v4 & 0x20) >> 1) |
-                               ((v3 & 0x20) >> 2) |
-                               ((v2 & 0x20) >> 3) |
-                               ((v1 & 0x20) >> 4) |
-                               ((v0 & 0x20) >> 5) ;
-
-                       d[6] =  ((v7 & 0x40) << 1) |
-                                (v6 & 0x40)       |
-                               ((v5 & 0x40) >> 1) |
-                               ((v4 & 0x40) >> 2) |
-                               ((v3 & 0x40) >> 3) |
-                               ((v2 & 0x40) >> 4) |
-                               ((v1 & 0x40) >> 5) |
-                               ((v0 & 0x40) >> 6) ;
-
-                       d[7] =   (v7 & 0x80)       |
-                               ((v6 & 0x80) >> 1) |
-                               ((v5 & 0x80) >> 2) |
-                               ((v4 & 0x80) >> 3) |
-                               ((v3 & 0x80) >> 4) |
-                               ((v2 & 0x80) >> 5) |
-                               ((v1 & 0x80) >> 6) |
-                               ((v0 & 0x80) >> 7) ;
-
-                       d += 8;
-                       s--;
-               }
-       }
-
-       /* and now output only the differences */
-       for (i = 0; i < LCD_PAGES; i++) {
-
-               b = &hw_screen[i][0];
-               e = &hw_screen[i][LCD_COLUMNS];
-
-               d = &last_hw_screen[i][0];
-               s = b;
-
-               last_page = -1;
-
-               /* update only the differences */
-               do {
-                       while (s < e && *s == *d) {
-                               s++;
-                               d++;
-                       }
-                       if (s == e)
-                               break;
-                       r = s;
-                       while (s < e && *s != *d)
-                               *d++ = *s++;
-
-                       j = r - b;
-
-                       if (i != last_page) {
-                               sed156x_cmd_transfer(LCD_PADDR | i);
-                               last_page = i;
-                       }
-
-                       sed156x_cmd_transfer(LCD_CADRH | ((j >> 4) & 0x0F));
-                       sed156x_cmd_transfer(LCD_CADRL | (j & 0x0F));
-                       sed156x_data_block_transfer(r, s - r);
-
-               } while (s < e);
-       }
-
-/********
-       for (i = 0; i < LCD_PAGES; i++) {
-               sed156x_cmd_transfer(LCD_PADDR | i);
-               sed156x_cmd_transfer(LCD_CADRH | 0);
-               sed156x_cmd_transfer(LCD_CADRL | 0);
-               sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS);
-       }
-       memcpy(last_hw_screen, hw_screen, sizeof(last_hw_screen));
-********/
-}
-
-void sed156x_clear(void)
-{
-       memset(sw_screen, 0, sizeof(sw_screen));
-}
-
-void sed156x_output_at(int x, int y, const char *str, int size)
-{
-       int i, j;
-       u8 *p;
-       const u8 *s;
-
-       if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH)
-               return;
-
-       p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH];
-
-       while (--size >= 0) {
-
-               s = &video_fontdata[((int)*str++ & 0xff) * VIDEO_FONT_BYTE_WIDTH * VIDEO_FONT_HEIGHT];
-               for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
-                       for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++)
-                               *p++ = *s++;
-                       p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH;
-               }
-               p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH);
-
-               if (x >= LCD_TEXT_WIDTH)
-                       break;
-               x++;
-       }
-}
-
-void sed156x_reverse_at(int x, int y, int size)
-{
-       int i, j;
-       u8 *p;
-
-       if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH)
-               return;
-
-       p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH];
-
-       while (--size >= 0) {
-
-               for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
-                       for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++, p++)
-                               *p = ~*p;
-                       p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH;
-               }
-               p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH);
-
-               if (x >= LCD_TEXT_WIDTH)
-                       break;
-               x++;
-       }
-}
-
-void sed156x_scroll_line(void)
-{
-       memmove(&sw_screen[0],
-                       &sw_screen[LCD_BYTE_LINESZ],
-                       LCD_BYTE_WIDTH * (LCD_HEIGHT - VIDEO_FONT_HEIGHT));
-}
-
-void sed156x_scroll(int dx, int dy)
-{
-       u8 *p1 = NULL, *p2 = NULL, *p3 = NULL;  /* pacify gcc */
-       int adx, ady, i, sz;
-
-       adx = dx > 0 ? dx : -dx;
-       ady = dy > 0 ? dy : -dy;
-
-       /* overscroll? erase everything */
-       if (adx >= LCD_TEXT_WIDTH || ady >= LCD_TEXT_HEIGHT) {
-               memset(sw_screen, 0, sizeof(sw_screen));
-               return;
-       }
-
-       sz = LCD_BYTE_LINESZ * ady;
-       if (dy > 0) {
-               p1 = &sw_screen[0];
-               p2 = &sw_screen[sz];
-               p3 = &sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT - sz];
-       } else if (dy < 0) {
-               p1 = &sw_screen[sz];
-               p2 = &sw_screen[0];
-               p3 = &sw_screen[0];
-       }
-
-       if (ady > 0) {
-               memmove(p1, p2, LCD_BYTE_WIDTH * LCD_HEIGHT - sz);
-               memset(p3, 0, sz);
-       }
-
-       sz = VIDEO_FONT_BYTE_WIDTH * adx;
-       if (dx > 0) {
-               p1 = &sw_screen[0];
-               p2 = &sw_screen[0] + sz;
-               p3 = &sw_screen[0] + LCD_BYTE_WIDTH - sz;
-       } else if (dx < 0) {
-               p1 = &sw_screen[0] + sz;
-               p2 = &sw_screen[0];
-               p3 = &sw_screen[0];
-       }
-
-       /* xscroll */
-       if (adx > 0) {
-               for (i = 0; i < LCD_HEIGHT; i++) {
-                       memmove(p1, p2, LCD_BYTE_WIDTH - sz);
-                       memset(p3, 0, sz);
-                       p1 += LCD_BYTE_WIDTH;
-                       p2 += LCD_BYTE_WIDTH;
-                       p3 += LCD_BYTE_WIDTH;
-               }
-       }
-}
-
-void sed156x_init(void)
-{
-       int i;
-
-       SED156X_CS(1);
-       SED156X_A0(1);
-
-       /* Send initialization commands to the LCD */
-       sed156x_cmd_transfer(LCD_OFF);                  /* Turn display OFF       */
-       sed156x_cmd_transfer(LCD_BIAS);                 /* set the LCD Bias,      */
-       sed156x_cmd_transfer(LCD_ADCMODE);              /* ADC mode,              */
-       sed156x_cmd_transfer(LCD_COMDIR);               /* common output mode,    */
-       sed156x_cmd_transfer(LCD_RESRT | LCD_RRATIO);   /* resistor ratio,        */
-       sed156x_cmd_transfer(LCD_EVSET);                /* electronic volume,     */
-       sed156x_cmd_transfer(LCD_CNTRST);
-       sed156x_cmd_transfer(LCD_PWRMD | LCD_POWERM);   /* and power mode         */
-       sed156x_cmd_transfer(LCD_PADDR | 0);            /* cursor home            */
-       sed156x_cmd_transfer(LCD_CADRH | 0);
-       sed156x_cmd_transfer(LCD_CADRL | 0);
-       sed156x_cmd_transfer(LCD_LADDR | 0);            /* and display start line */
-       sed156x_cmd_transfer(LCD_DSP_NRM);              /* LCD display Normal     */
-
-       /* clear everything */
-       memset(sw_screen, 0, sizeof(sw_screen));
-       memset(hw_screen, 0, sizeof(hw_screen));
-       memset(last_hw_screen, 0, sizeof(last_hw_screen));
-
-       for (i = 0; i < LCD_PAGES; i++) {
-               sed156x_cmd_transfer(LCD_PADDR | i);
-               sed156x_cmd_transfer(LCD_CADRH | 0);
-               sed156x_cmd_transfer(LCD_CADRL | 0);
-               sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS);
-       }
-
-       sed156x_clear();
-       sed156x_sync();
-       sed156x_cmd_transfer(LCD_ON);                   /* Turn display ON        */
-}
diff --git a/drivers/video/sm501.c b/drivers/video/sm501.c
deleted file mode 100644 (file)
index a468bd9..0000000
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * (C) Copyright 2005
- * Martin Krause TQ-Systems GmbH martin.krause@tqs.de
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Basic video support for SMI SM501 "Voyager" graphic controller
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <pci.h>
-#include <video_fb.h>
-#include <sm501.h>
-
-#define read8(ptrReg)                \
-    *(volatile unsigned char *)(sm501.isaBase + ptrReg)
-
-#define write8(ptrReg,value) \
-    *(volatile unsigned char *)(sm501.isaBase + ptrReg) = value
-
-#define read16(ptrReg) \
-    (*(volatile unsigned short *)(sm501.isaBase + ptrReg))
-
-#define write16(ptrReg,value) \
-    (*(volatile unsigned short *)(sm501.isaBase + ptrReg) = value)
-
-#define read32(ptrReg) \
-    (*(volatile unsigned int *)(sm501.isaBase + ptrReg))
-
-#define write32(ptrReg, value) \
-    (*(volatile unsigned int *)(sm501.isaBase + ptrReg) = value)
-
-GraphicDevice sm501;
-
-void write_be32(int off, unsigned int val)
-{
-       out_be32((unsigned __iomem *)(sm501.isaBase + off), val);
-}
-
-void write_le32(int off, unsigned int val)
-{
-       out_le32((unsigned __iomem *)(sm501.isaBase + off), val);
-}
-
-void (*write_reg32)(int off, unsigned int val) = write_be32;
-
-/*-----------------------------------------------------------------------------
- * SmiSetRegs --
- *-----------------------------------------------------------------------------
- */
-static void SmiSetRegs (void)
-{
-       /*
-        * The content of the chipset register depends on the board (clocks,
-        * ...)
-        */
-       const SMI_REGS *preg = board_get_regs ();
-       while (preg->Index) {
-               write_reg32 (preg->Index, preg->Value);
-               /*
-                * Insert a delay between
-                */
-               udelay (1000);
-               preg ++;
-       }
-}
-
-#ifdef CONFIG_VIDEO_SM501_PCI
-static struct pci_device_id sm501_pci_tbl[] = {
-       { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_501 },
-       {}
-};
-#endif
-
-/*
- * We do not enforce board code to provide empty/unused
- * functions for this driver and define weak default
- * functions here.
- */
-unsigned int __board_video_init (void)
-{
-       return 0;
-}
-
-unsigned int board_video_init (void)
-                       __attribute__((weak, alias("__board_video_init")));
-
-unsigned int __board_video_get_fb (void)
-{
-       return 0;
-}
-
-unsigned int board_video_get_fb (void)
-                       __attribute__((weak, alias("__board_video_get_fb")));
-
-void __board_validate_screen (unsigned int base)
-{
-}
-
-void board_validate_screen (unsigned int base)
-                       __attribute__((weak, alias("__board_validate_screen")));
-
-/*-----------------------------------------------------------------------------
- * video_hw_init --
- *-----------------------------------------------------------------------------
- */
-void *video_hw_init (void)
-{
-#ifdef CONFIG_VIDEO_SM501_PCI
-       unsigned int pci_mem_base, pci_mmio_base;
-       unsigned int id;
-       unsigned short device_id;
-       pci_dev_t devbusfn;
-       int mem;
-#endif
-       unsigned int *vm, i;
-
-       memset (&sm501, 0, sizeof (GraphicDevice));
-
-#ifdef CONFIG_VIDEO_SM501_PCI
-       printf("Video: ");
-
-       /* Look for SM501/SM502 chips */
-       devbusfn = pci_find_devices(sm501_pci_tbl, 0);
-       if (devbusfn < 0) {
-               printf ("PCI Controller not found.\n");
-               goto not_pci;
-       }
-
-       /* Setup */
-       pci_write_config_dword (devbusfn, PCI_COMMAND,
-                               (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
-       pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
-       pci_read_config_dword (devbusfn, PCI_REVISION_ID, &id);
-       pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
-       pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_1, &pci_mmio_base);
-       sm501.frameAdrs = pci_mem_to_phys (devbusfn, pci_mem_base);
-       sm501.isaBase = pci_mem_to_phys (devbusfn, pci_mmio_base);
-
-       if (sm501.isaBase)
-               write_reg32 = write_le32;
-
-       mem = in_le32 ((unsigned __iomem *)(sm501.isaBase + 0x10));
-       mem = (mem & 0x0000e000) >> 13;
-       switch (mem) {
-       case 1:
-               mem = 8;
-               break;
-       case 2:
-               mem = 16;
-               break;
-       case 3:
-               mem = 32;
-               break;
-       case 4:
-               mem = 64;
-               break;
-       case 5:
-               mem = 2;
-               break;
-       case 0:
-       default:
-               mem = 4;
-       }
-       printf ("PCI SM50%d %d MB\n", ((id & 0xff) == 0xC0) ? 2 : 1, mem);
-not_pci:
-#endif
-       /*
-        * Initialization of the access to the graphic chipset Retreive base
-        * address of the chipset (see board/RPXClassic/eccx.c)
-        */
-       if (!sm501.isaBase) {
-               sm501.isaBase = board_video_init ();
-               if (!sm501.isaBase)
-                       return NULL;
-       }
-
-       if (!sm501.frameAdrs) {
-               sm501.frameAdrs = board_video_get_fb ();
-               if (!sm501.frameAdrs)
-                       return NULL;
-       }
-
-       sm501.winSizeX = board_get_width ();
-       sm501.winSizeY = board_get_height ();
-
-#if defined(CONFIG_VIDEO_SM501_8BPP)
-       sm501.gdfIndex = GDF__8BIT_INDEX;
-       sm501.gdfBytesPP = 1;
-
-#elif defined(CONFIG_VIDEO_SM501_16BPP)
-       sm501.gdfIndex = GDF_16BIT_565RGB;
-       sm501.gdfBytesPP = 2;
-
-#elif defined(CONFIG_VIDEO_SM501_32BPP)
-       sm501.gdfIndex = GDF_32BIT_X888RGB;
-       sm501.gdfBytesPP = 4;
-#else
-#error Unsupported SM501 BPP
-#endif
-
-       sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP;
-
-       /* Load Smi registers */
-       SmiSetRegs ();
-
-       /* (see board/RPXClassic/RPXClassic.c) */
-       board_validate_screen (sm501.isaBase);
-
-       /* Clear video memory */
-       i = sm501.memSize/4;
-       vm = (unsigned int *)sm501.frameAdrs;
-       while(i--)
-               *vm++ = 0;
-
-       return (&sm501);
-}
index 12828c6..496ef58 100644 (file)
@@ -16,7 +16,6 @@
 
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_MARVELL
-#define CONFIG_PHY_MICREL
 #define CONFIG_PHY_BROADCOM
 #define CONFIG_PHY_DAVICOM
 #define CONFIG_PHY_REALTEK
index d05cc61..892ceff 100644 (file)
@@ -30,7 +30,6 @@
  * NET options
  */
 #define CONFIG_SYS_RX_ETH_BUFFER       0
-#define CONFIG_PHY_GIGE
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #define CONFIG_PHY_MARVELL
 
index 0d3794d..3869d90 100644 (file)
@@ -33,7 +33,6 @@
  * NET options
  */
 #define CONFIG_SYS_RX_ETH_BUFFER       0
-#define CONFIG_PHY_GIGE
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #define CONFIG_PHY_MARVELL
 
index 4ec6575..90296cd 100644 (file)
@@ -679,7 +679,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
index a7c97a3..57d4bed 100644 (file)
@@ -258,8 +258,6 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_ETHPRIME                "eTSEC1"
 
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
-
 #endif /* CONFIG_TSEC_ENET */
 
 /*
index b0a3cf8..04a5053 100644 (file)
@@ -457,8 +457,6 @@ combinations. this should be removed later
 
 #define CONFIG_ETHPRIME                "eTSEC1"
 
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
-
 /* TBI PHY configuration for SGMII mode */
 #define CONFIG_TSEC_TBICR_SETTINGS ( \
                TBICR_PHY_RESET \
index 050847b..962bf4a 100644 (file)
 #define TSEC2_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
 
 #define CONFIG_ETHPRIME                "eTSEC1"
-
-#define CONFIG_PHY_GIGE
 #endif /* CONFIG_TSEC_ENET */
 
 /*
index 221c35c..cb83d07 100644 (file)
@@ -419,7 +419,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #ifdef CONFIG_TSEC_ENET
 
 #define CONFIG_MII
-#define CONFIG_PHY_GIGE                /* In case CONFIG_CMD_MII is specified */
 
 #define CONFIG_TSEC1
 
index 38a2ca1..6b9c25f 100644 (file)
 
 #define CONFIG_ETHPRIME                "eTSEC1"
 
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
-
 #endif /* CONFIG_TSEC_ENET */
 
 /*
index b4f4c4e..12bcb02 100644 (file)
@@ -318,8 +318,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define TSEC3_PHYIDX           0
 
 #define CONFIG_ETHPRIME                "eTSEC1"
-
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #endif /* CONFIG_TSEC_ENET */
 
 /*
index b415436..c18bf67 100644 (file)
@@ -432,7 +432,6 @@ extern unsigned long get_clock_freq(void);
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME                "eTSEC0"
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #endif /* CONFIG_TSEC_ENET */
 
 /*
index 9062702..49c6e7f 100644 (file)
 #define TSEC4_PHYIDX           0
 
 #define CONFIG_ETHPRIME                "eTSEC1"
-
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #endif /* CONFIG_TSEC_ENET */
 
 /*
index 08288cc..2dee5ac 100644 (file)
@@ -629,8 +629,6 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_ETHPRIME                "eTSEC1"
 
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
-
 /* TBI PHY configuration for SGMII mode */
 #define CONFIG_TSEC_TBICR_SETTINGS ( \
                TBICR_PHY_RESET \
index a1035d6..0fab00f 100644 (file)
 #define TSEC2_PHYIDX           0
 
 #define CONFIG_ETHPRIME                "eTSEC1"
-
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index 75d1efd..3cc5033 100644 (file)
@@ -317,7 +317,6 @@ extern unsigned long get_clock_freq(void);
 
 /* For FM */
 #define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
index 7c139bb..ef7563d 100644 (file)
@@ -558,7 +558,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_TBIPA_VALUE 8
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index 163ec10..767cd22 100644 (file)
@@ -743,7 +743,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC4"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index cdd459e..9c575a9 100644 (file)
@@ -755,7 +755,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC4"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index 0a848b6..8bf32cd 100644 (file)
@@ -617,7 +617,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /* Enable VSC9953 L2 Switch driver */
index 13efcb9..49e88b2 100644 (file)
@@ -753,7 +753,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC4"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index 1e4a49e..f6b8f0b 100644 (file)
@@ -672,7 +672,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC3"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index ecce516..6ab7a12 100644 (file)
@@ -622,7 +622,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC3"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index e041ea0..885dc77 100644 (file)
@@ -485,7 +485,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index f4f025a..4a2ed6a 100644 (file)
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
@@ -667,7 +666,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index 6fd3fa4..56c1f28 100644 (file)
 
 #if defined(CONFIG_TSEC_ENET)
 
-#if defined(CONFIG_UCP1020_REV_1_2)
-#define CONFIG_PHY_MICREL_KSZ9021
-#elif defined(CONFIG_UCP1020_REV_1_3)
-#define CONFIG_PHY_MICREL_KSZ9031
+#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
 #else
 #error "UCP1020 module revision is not defined !!!"
 #endif
 #define TSEC2_PHYIDX   0
 #define TSEC3_PHYIDX   0
 
-#define CONFIG_PHY_GIGE        1       /* Include GbE speed/duplex detection */
-
 #endif
 
 #define CONFIG_HOSTNAME                UCP1020
index 22a4e69..6d40eb4 100644 (file)
@@ -71,7 +71,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         4
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* Serial Flash */
index a61814e..35518da 100644 (file)
@@ -51,8 +51,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
index 2a2e2ba..fbab610 100644 (file)
 #define CONFIG_SF_DEFAULT_SPEED                24000000
 
 /* Network. */
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 /* Enable Atheros phy driver */
 #define CONFIG_PHY_ATHEROS
index 4721b42..3d3d5e7 100644 (file)
 #define CONFIG_CONS_INDEX              1
 
 /* Ethernet support */
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 /* NAND support */
index f3b7767..121beef 100644 (file)
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT         10
 #define CONFIG_NET_MULTI
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR                        0
 #define CONFIG_PHY_SMSC
 
index 75f9bef..13ff2b2 100644 (file)
 #endif
 
 /* Network. */
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #endif /* ! __CONFIG_AM335X_SL50_H */
index 4469167..4f3b605 100644 (file)
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT         10
-#define CONFIG_PHY_GIGE
 #endif
 
 #define CONFIG_DRIVER_TI_CPSW
-#define CONFIG_PHYLIB
 #define PHY_ANEG_TIMEOUT       8000 /* PHY needs longer aneg time at 1G */
 
 #define CONFIG_SYS_RX_ETH_BUFFER       64
index 9976686..9f07bba 100644 (file)
@@ -84,8 +84,6 @@
 #define CONFIG_NET_RETRY_COUNT         10
 #define CONFIG_DRIVER_TI_CPSW          /* Driver for IP block */
 #define CONFIG_MII                     /* Required in net/eth.c */
-#define CONFIG_PHY_GIGE                        /* per-board part of CPSW */
-#define CONFIG_PHYLIB
 #define PHY_ANEG_TIMEOUT       8000    /* PHY needs longer aneg time at 1G */
 
 #define CONFIG_SUPPORT_EMMC_BOOT
index adc7d1f..cbf7782 100644 (file)
@@ -29,8 +29,6 @@
 #define CONFIG_SH_ETHER_PHY_ADDR (0x0)
 #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
 #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL 1
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
index 4a12ac8..16af141 100644 (file)
@@ -86,9 +86,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         6
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE          4096
 #define CONFIG_TFTP_TSIZE
index 6ad956f..1c28fcf 100644 (file)
@@ -32,9 +32,6 @@
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         0
 
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-
 #define CONFIG_SPI_FLASH_MTD
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_SPEED                20000000
index 30abafc..9cd40a7 100644 (file)
@@ -20,7 +20,6 @@
 #define CONSOLE_DEV    "ttymxc1"
 
 #define CONFIG_FEC_XCV_TYPE            RGMII
-#define CONFIG_PHY_MICREL_KSZ9031
 
 #define CONFIG_SF_DEFAULT_BUS          3
 #define CONFIG_SF_DEFAULT_CS           1
index 7a47514..a680e76 100644 (file)
@@ -20,7 +20,6 @@
 #define CONSOLE_DEV    "ttymxc1"
 
 #define CONFIG_FEC_XCV_TYPE            RGMII
-#define CONFIG_PHY_MICREL_KSZ9031
 
 #define CONFIG_SF_DEFAULT_BUS          0
 #define CONFIG_SF_DEFAULT_CS           0
index 643b26b..3b8a250 100644 (file)
 #define CONFIG_SH_ETHER_BASE_ADDR      0xe9a00000
 #define CONFIG_SH_ETHER_SH7734_MII     (0x01)
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
index 07b53b1..e1a30b7 100644 (file)
@@ -55,7 +55,6 @@
  * Ethernet PHY configuration
  */
 #define CONFIG_MII
-#define CONFIG_PHY_GIGE
 
 /*
  * USB 1.1 configuration
index aba7208..598352b 100644 (file)
 #endif
 
 /* Network. */
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR                        0
 #define CONFIG_PHY_SMSC
 #define CONFIG_MII
index fafab8e..6beb347 100644 (file)
@@ -521,8 +521,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #define CONFIG_SF_DEFAULT_SPEED                24000000
 
 /* Network. */
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 /*
index 8d0e0ea..b8c531e 100644 (file)
@@ -31,7 +31,6 @@
 /* Network defines */
 #define CONFIG_DRIVER_TI_CPSW          /* Driver for IP block */
 #define CONFIG_MII                     /* Required in net/eth.c */
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_NATSEMI
 
 /*
index b36cbb9..4996a89 100644 (file)
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         6
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* Command definition */
index 82be3a1..581ab7c 100644 (file)
 #endif
 
 /* Network. */
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #endif /* ! __CONFIG_CHILIBOARD_H */
index 120ac02..4010354 100644 (file)
 #define CONFIG_BOOTP_DEFAULT
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_GATEWAY
-#define CONFIG_PHY_GIGE
 #define CONFIG_PHY_ATHEROS
-#define CONFIG_PHYLIB
 #define CONFIG_SYS_RX_ETH_BUFFER       64
 #define PHY_ANEG_TIMEOUT               8000
 
index e2c43b1..4f45be1 100644 (file)
 #define CONFIG_FEC_MXC_PHYADDR         0
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 #define CONFIG_MII
 #define CONFIG_ETHPRIME                        "FEC0"
index ed7bb1d..6bcc63a 100644 (file)
 #define CONFIG_SPL_LDSCRIPT            "arch/arm/mach-omap2/u-boot-spl.lds"
 
 /* Network. */
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* NAND support */
index 7a61107..4c261f8 100644 (file)
@@ -53,9 +53,7 @@
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_NET_MULTI
-#define CONFIG_PHY_GIGE
 #define CONFIG_PHY_ATHEROS
-#define CONFIG_PHYLIB
 #define CONFIG_SYS_RX_ETH_BUFFER       64
 
 /* USB support */
index 5f73867..fca72f4 100644 (file)
@@ -72,8 +72,6 @@
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         1
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE          16352
 #define CONFIG_TFTP_TSIZE
index 4baa038..30a2d12 100644 (file)
@@ -32,8 +32,6 @@
 #define CONFIG_ETHPRIME                 "FEC"
 #define CONFIG_FEC_MXC_PHYADDR          0
 
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE          16352
 #define CONFIG_TFTP_TSIZE
index 15a0638..cc1f919 100644 (file)
@@ -66,8 +66,6 @@
 #define IMX_FEC_BASE                   ENET1_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 
 #define CONFIG_IPADDR          192.168.10.2
 #define CONFIG_NETMASK         255.255.255.0
index 1ac4162..08def62 100644 (file)
 
 #define CONFIG_ETHPRIME                "eTSEC1"
 
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
-
 /*
  * USB
  */
index 77a997b..668dd06 100644 (file)
 #define CONFIG_SYS_TBIPA_VALUE 8
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index e255a8b..8819602 100644 (file)
@@ -84,7 +84,6 @@
 
 /* Ethernet */
 #define CONFIG_MACB
-#define CONFIG_PHYLIB
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_AT91_WANTS_COMMON_PHY
index ddbaf32..cdabbac 100644 (file)
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 #endif
 
 #ifdef CONFIG_PCI
 #define CONFIG_SYS_TBIPA_VALUE 8
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC4"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index f1a5c6c..6124867 100644 (file)
@@ -73,7 +73,6 @@
 #define CONFIG_RMII
 #define CONFIG_PHY_SMSC
 #define CONFIG_LPC32XX_ETH
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR                        0x1F
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
index b509151..1a58c6e 100644 (file)
 #define CONFIG_NET_RETRY_COUNT         10
 #define CONFIG_DRIVER_TI_CPSW          /* Driver for IP block */
 #define CONFIG_MII                     /* Required in net/eth.c */
-#define CONFIG_PHY_GIGE                        /* per-board part of CPSW */
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_TI
 
 /* SPI */
index ba6a430..2d8cf93 100644 (file)
@@ -40,7 +40,6 @@
 #define EEPROM_ADDR_CHIP 0x120
 
 #undef CONFIG_MII
-#undef CONFIG_PHY_GIGE
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_FACTORYSET
index 2471277..fe56c8f 100644 (file)
@@ -53,7 +53,6 @@
 #define CONFIG_SH_ETHER_USE_PORT (0)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
 #define CONFIG_PHY_SMSC 1
-#define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
index 61f0c95..d1dec80 100644 (file)
@@ -51,7 +51,6 @@
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         4
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 #ifdef CONFIG_CMD_SF
index 07f3275..b9538f3 100644 (file)
@@ -91,7 +91,6 @@
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (1)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x00)
-#define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
index 1662dbf..c9584ad 100644 (file)
@@ -98,7 +98,6 @@
 #define EEPROM_ADDR_CHIP 0x120
 
 #undef CONFIG_MII
-#undef CONFIG_PHY_GIGE
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_FACTORYSET
index 584a2b4..5e5d044 100644 (file)
@@ -77,8 +77,6 @@
  */
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE   FEC_BASE_ADDR
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_FEC_MXC_PHYADDR 0x1
 
 #define CONFIG_MII
index 5e04dd2..cc2b786 100644 (file)
@@ -94,7 +94,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         4
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 #endif
 
index 067e86d..610ba1a 100644 (file)
@@ -50,8 +50,6 @@
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_ALIGNE_SIZE    64
index f56618a..c1e9f5d 100644 (file)
@@ -30,7 +30,6 @@
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_ETHPRIME                "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         0
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
index 7a201b0..6341609 100644 (file)
@@ -84,7 +84,6 @@
 #define CONFIG_KSNET_NETCP_V1_5
 #define CONFIG_KSNET_CPSW_NUM_PORTS    2
 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
-#define CONFIG_PHY_MICREL
 #define PHY_ANEG_TIMEOUT       10000 /* PHY needs longer aneg time */
 
 #define CONFIG_ENV_SIZE                        (256 << 10)  /* 256 KiB */
index 3c66f8a..be4a2d0 100644 (file)
@@ -346,9 +346,7 @@ int get_scl(void);
 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
 #define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_PHYLIB          /* recommended PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC5"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 
 /*
  * Environment
index 988b747..b9214d2 100644 (file)
@@ -50,8 +50,6 @@
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
index 73ea9ac..291b03c 100644 (file)
@@ -51,8 +51,6 @@
 #define CONFIG_SH_ETHER_ALIGNE_SIZE    64
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
index 76ee910..2cad644 100644 (file)
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_ETHPRIME                        "FEC"
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 #endif
 
index 58f893f..56a0754 100644 (file)
 
 #define CONFIG_ETHPRIME                        "eTSEC2"
 
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 #define CONFIG_HAS_ETH0
index bd05b45..56f8c03 100644 (file)
@@ -456,8 +456,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_ETHPRIME                        "eTSEC1"
 
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_REALTEK
 
 #define CONFIG_HAS_ETH0
index 98e902e..af49923 100644 (file)
 
 #define CONFIG_ETHPRIME                        "eTSEC1"
 
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 #define CONFIG_HAS_ETH0
index 2d58b3b..af58e61 100644 (file)
@@ -50,7 +50,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHYLIB_10G
index 937fd93..a4162a6 100644 (file)
 #define AQR105_IRQ_MASK                        0x40000000
 
 #ifdef CONFIG_NET
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #endif
index 9dc74b4..ef2f47c 100644 (file)
@@ -70,7 +70,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHYLIB_10G
index 3d3dfb1..b9f27bb 100644 (file)
 #ifndef SPL_NO_FMAN
 
 #ifdef CONFIG_NET
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #define CONFIG_PHY_REALTEK
 #endif
 
index 6b943cd..1801eca 100644 (file)
@@ -406,7 +406,6 @@ unsigned long get_board_ddr_clk(void);
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 #define CONFIG_FSL_MEMAC
-#define        CONFIG_PHYLIB
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
@@ -435,7 +434,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "DPMAC1@xgmii"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 
 #endif
 
index b86726f..de67e1d 100644 (file)
@@ -468,7 +468,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_AQUANTIA
 #define CONFIG_PHY_CORTINA
-#define CONFIG_PHYLIB
 #define        CONFIG_SYS_CORTINA_FW_IN_NOR
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_CORTINA_FW_ADDR         0x20980000
@@ -489,7 +488,6 @@ unsigned long get_board_sys_clk(void);
 
 #define CONFIG_MII
 #define CONFIG_ETHPRIME                "DPMAC1@xgmii"
-#define CONFIG_PHY_GIGE
 #define CONFIG_PHY_AQUANTIA
 #endif
 
index 138525b..2f7efc7 100644 (file)
 #define CONFIG_MII
 #define CONFIG_DISCOVER_PHY
 #define CONFIG_FEC_XCV_TYPE            RMII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_ETHPRIME                        "FEC0"
 #endif
 
index a4c1035..7ea9839 100644 (file)
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         1
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
index aa007e2..4f77b8e 100644 (file)
 
 #if defined(CONFIG_XILINX_AXIEMAC)
 # define CONFIG_MII            1
-# define CONFIG_PHY_GIGE       1
 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN       1
 # define CONFIG_PHY_ATHEROS    1
 # define CONFIG_PHY_BROADCOM   1
 # define CONFIG_PHY_DAVICOM    1
 # define CONFIG_PHY_LXT                1
 # define CONFIG_PHY_MARVELL    1
-# define CONFIG_PHY_MICREL     1
-# define CONFIG_PHY_MICREL_KSZ9021
 # define CONFIG_PHY_NATSEMI    1
 # define CONFIG_PHY_REALTEK    1
 # define CONFIG_PHY_VITESSE    1
index 1307d21..71975ed 100644 (file)
@@ -88,7 +88,6 @@
  */
 #define CONFIG_MVNETA          /* Enable Marvell Gbe Controller Driver */
 #define CONFIG_ENV_OVERWRITE   /* ethaddr can be reprogrammed */
-#define CONFIG_PHY_GIGE                /* GbE speed/duplex detect */
 #define CONFIG_ARP_TIMEOUT     200
 #define CONFIG_NET_RETRY_COUNT 50
 #define CONFIG_PHY_MARVELL
index 86ae19c..d93a15f 100644 (file)
@@ -93,7 +93,6 @@
  * Ethernet Driver configuration
  */
 #define CONFIG_ENV_OVERWRITE   /* ethaddr can be reprogrammed */
-#define CONFIG_PHY_GIGE                /* GbE speed/duplex detect */
 #define CONFIG_ARP_TIMEOUT     200
 #define CONFIG_NET_RETRY_COUNT 50
 
index 32e898e..5930f59 100644 (file)
@@ -37,7 +37,6 @@
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_FEC_MXC_PHYADDR         0
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
index b3638d5..b849eea 100644 (file)
@@ -28,7 +28,6 @@
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         1
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 #ifdef CONFIG_CMD_SF
index 98797b0..cd9f0b0 100644 (file)
@@ -39,7 +39,6 @@
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_FEC_MXC_PHYADDR         0
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
index 060ebd7..e377c0f 100644 (file)
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_ETHPRIME                 "FEC"
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 #ifdef CONFIG_CMD_USB
index 319fed4..2c0a799 100644 (file)
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_ETHPRIME                 "FEC"
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 #ifdef CONFIG_CMD_USB
index c9b7e7b..47379ca 100644 (file)
 #define CONFIG_FEC_XCV_TYPE            RMII
 #endif
 #define CONFIG_ETHPRIME                        "FEC"
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #endif
 
 #define CONFIG_IMX_THERMAL
index d4dd0b3..fec7e81 100644 (file)
@@ -26,7 +26,6 @@
 #define CONFIG_ETHPRIME                 "FEC"
 #define CONFIG_FEC_MXC_PHYADDR          0
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_BROADCOM
 /* ENET1 */
 #define IMX_FEC_BASE                   ENET_IPS_BASE_ADDR
index a1a0cda..bc17b51 100644 (file)
@@ -65,9 +65,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         6
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 
 /* USB Configs */
 #define CONFIG_USB_HOST_ETHER
index 2bba741..c3005e7 100644 (file)
@@ -72,9 +72,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         0x7
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 #define CONFIG_ARP_TIMEOUT             200UL
 #endif
 
index 2342f74..896c329 100644 (file)
@@ -70,7 +70,6 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_MVGBE_PORTS     {1, 0}  /* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR    1
-#define CONFIG_PHY_GIGE
 #define CONFIG_RESET_PHY_R
 #endif /* CONFIG_CMD_NET */
 
index 373c2d5..8ca6f62 100644 (file)
@@ -82,7 +82,6 @@
 #define CONFIG_FEC_XCV_TYPE             MII100
 #define CONFIG_ETHPRIME                 "FEC"
 #define CONFIG_FEC_MXC_PHYADDR          0x5
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #ifndef CONFIG_SPL
index 6eae41c..5c82779 100644 (file)
 
 #define CONFIG_ETHPRIME        "eTSEC1"
 
-#define CONFIG_PHY_GIGE        1       /* Include GbE speed/duplex detection */
-
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
index d5f5769..df0b608 100644 (file)
@@ -295,8 +295,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_ETHPRIME        "eTSEC1"
 
-#define CONFIG_PHY_GIGE        1       /* Include GbE speed/duplex detection */
-
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #undef CONFIG_HAS_ETH2
index ce80e7e..112f9b8 100644 (file)
 #define CONFIG_USB_ETH_RNDIS
 #endif /* CONFIG_USB_MUSB_GADGET */
 
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #endif /* ! __CONFIG_PCM051_H */
index 71c5078..b4b60ac 100644 (file)
@@ -61,8 +61,6 @@
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 
 /* QSPI Configs*/
 
index e3a84ed..2c1221d 100644 (file)
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         3
 
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_KSZ9031
-
 /* SPI Flash */
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS          0
index dbe0ddd..a76bbce 100644 (file)
 #define CONFIG_NET_MULTI
 
 /* Network */
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET       1
 #define CONFIG_PHY_NATSEMI
 #define CONFIG_PHY_REALTEK
index ff3cd74..1a6981a 100644 (file)
 #define CONFIG_SYS_NS16550_COM1                0x44e09000
 
 /* Ethernet support */
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR                        0
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 #define CONFIG_PHY_RESET_DELAY 1000
 
 /* SPL */
index 7b44752..5cb507f 100644 (file)
@@ -21,8 +21,6 @@
 #define IMX_FEC_BASE                   ENET2_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR         0x1
 #define CONFIG_FEC_XCV_TYPE            RMII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN          (35 * SZ_1M) /* Increase due to DFU */
index e623f48..793ba78 100644 (file)
@@ -25,7 +25,6 @@
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         1
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* ENET1 */
index 1cdab00..4801cb2 100644 (file)
@@ -40,8 +40,6 @@
 #define CONFIG_MII
 #define IMX_FEC_BASE                           ENET_BASE_ADDR
 
-#define CONFIG_PHYLIB
-
 /* USB config */
 #define CONFIG_MXC_USB_PORT                    1
 #define CONFIG_MXC_USB_PORTSC                  (PORT_PTS_UTMI | PORT_PTS_PTW)
index ccb6441..69406a4 100644 (file)
@@ -20,8 +20,6 @@
 #define CONFIG_FEC_XCV_TYPE                    RGMII
 #define CONFIG_FEC_MXC_PHYADDR                 4
 
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 #define CONFIG_PHY_RESET_DELAY                 1000
 
 #define CONFIG_HOSTNAME                                titanium
index fa1fff9..451d9dd 100644 (file)
@@ -52,8 +52,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE    64
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
index d79aa21..2b04521 100644 (file)
@@ -27,7 +27,6 @@
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (0)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x0)
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC 1
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
index 0820f6f..721f94c 100644 (file)
@@ -44,7 +44,6 @@
 #define EEPROM_ADDR_CHIP 0x120
 
 #undef CONFIG_MII
-#undef CONFIG_PHY_GIGE
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_FACTORYSET
index c887771..381082c 100644 (file)
@@ -93,8 +93,6 @@
 #define IMX_FEC_BASE            ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE     RMII
 #define CONFIG_FEC_MXC_PHYADDR  0
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #endif
 
 #if 0                          /* Disable until the FLASH will be implemented */
index f8bfe96..5bf5731 100644 (file)
@@ -26,7 +26,6 @@
 
 /* Ethernet RAVB */
 #define CONFIG_NET_MULTI
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
index 83b527c..d10dc3e 100644 (file)
@@ -85,8 +85,6 @@
 #define CONFIG_PMECC_CAP               4
 #define CONFIG_PMECC_SECTOR_SIZE       512
 
-#define CONFIG_PHY_MICREL_KSZ9021
-
 /* USB */
 
 #ifdef CONFIG_CMD_USB
index cf9809d..abac950 100644 (file)
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME                "eTSEC0"
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #endif /* CONFIG_TSEC_ENET */
 
 /*
index f7aeb64..efed670 100644 (file)
@@ -33,7 +33,6 @@
 /* FEC Ethernet on SoC */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_MXC
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 #endif
 
index c90626f..c3a4961 100644 (file)
@@ -33,8 +33,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         6
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 
 #define CONFIG_EXTRA_ENV_SETTINGS                                      \
        "netdev=eth0\0"                                                 \
index 39e8244..dd3a5fb 100644 (file)
@@ -60,7 +60,6 @@
 #define CONFIG_SH_ETHER_PHY_ADDR       18
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK        1
 #define CONFIG_SH_ETHER_USE_GETHER     1
-#define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
index 24ec076..c53cd17 100644 (file)
@@ -60,7 +60,6 @@
 #define CONFIG_SH_ETHER_PHY_ADDR       18
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK        1
 #define CONFIG_SH_ETHER_USE_GETHER     1
-#define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
index e5084ad..8ec4cd4 100644 (file)
@@ -60,7 +60,6 @@
 #define CONFIG_SH_ETHER_USE_PORT       0
 #define CONFIG_SH_ETHER_PHY_ADDR       1
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK        1
-#define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
index 74bd9fc..3876e07 100644 (file)
@@ -91,7 +91,6 @@
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (1)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
-#define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
index 5a5bf7a..22215fe 100644 (file)
 
 #define CONFIG_DRIVER_TI_CPSW
 #define CONFIG_MII
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_BOOTP_DEFAULT
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_DNS2
index 238783b..0384325 100644 (file)
@@ -52,8 +52,6 @@
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
 #define CONFIG_SH_ETHER_ALIGNE_SIZE    64
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
index cc83b98..a80d290 100644 (file)
  *
  */
 #define CONFIG_MACB
-#define CONFIG_PHYLIB
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_MCS7830
index 13977cb..91a681a 100644 (file)
@@ -52,7 +52,6 @@
 
 /* Ethernet */
 #define CONFIG_MACB
-#define CONFIG_PHYLIB
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_RESET_PHY_R
index 55850bd..b30b44d 100644 (file)
 #define PHYS_SDRAM_1_SIZE              0x40000000
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
-#endif
 
 /*
  * U-Boot environment configurations
index 9f83858..6b6d54b 100644 (file)
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-#endif
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
index 2c23ae5..175b01e 100644 (file)
@@ -97,7 +97,6 @@
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
 #define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHY_GIGE
 #endif
 
 /*
index 86b4a9d..018a0c3 100644 (file)
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-#endif
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
index 6516c45..275ed7f 100644 (file)
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
-#endif
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
index 04be2b1..bb50fcf 100644 (file)
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
-#endif
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
index 9405083..05975c9 100644 (file)
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-#endif
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
index febb8f7..6d12aed 100644 (file)
@@ -25,8 +25,6 @@
 #define CONFIG_ARP_TIMEOUT             500UL
 
 /* PHY */
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 #endif
 
 /* The rest of the configuration is shared */
index 57de60e..b4f31c4 100644 (file)
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-#endif
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
index 6b6cb6a..ebb9ac5 100644 (file)
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-#endif
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
index a86043f..b54097c 100644 (file)
@@ -41,8 +41,6 @@
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_BOOTP_SEND_HOSTNAME
 /* PHY */
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 #endif
 
 /* Extra Environment */
index 406a985..5b8fa3a 100644 (file)
 
 /* Options are: TSEC[0,1] */
 #define CONFIG_ETHPRIME                "TSEC0"
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
index 83060e7..49fdf9c 100644 (file)
@@ -17,7 +17,6 @@
 /* Ethernet driver configuration */
 #define CONFIG_MII
 #define CONFIG_PHY_RESET_DELAY                 10000           /* in usec */
-#define CONFIG_PHY_GIGE                        /* Include GbE speed/duplex detection */
 
 /* USBD driver configuration */
 #if defined(CONFIG_SPEAR_USBTTY)
index 3b8806d..9422c04 100644 (file)
@@ -55,8 +55,6 @@
 #define CONFIG_SH_ETHER_ALIGNE_SIZE    64
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
index 0ac262e..3b5831d 100644 (file)
@@ -49,7 +49,6 @@
 
 #define CONFIG_MII
 #define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_PHY_MICREL
 
 /* Command support defines */
 #define CONFIG_PHY_RESET_DELAY                 10000           /* in usec */
index 681c91c..07c7ffd 100644 (file)
@@ -296,11 +296,9 @@ extern int soft_i2c_gpio_scl;
 #ifdef CONFIG_SUNXI_EMAC
 #define CONFIG_PHY_ADDR                1
 #define CONFIG_MII                     /* MII PHY management           */
-#define CONFIG_PHYLIB
 #endif
 
 #ifdef CONFIG_SUNXI_GMAC
-#define CONFIG_PHY_GIGE                        /* GMAC can use gigabit PHY     */
 #define CONFIG_PHY_ADDR                1
 #define CONFIG_MII                     /* MII PHY management           */
 #define CONFIG_PHY_REALTEK
index 6d8c78f..99c0602 100644 (file)
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 #endif
 
 /*
index 7e1c58f..5a7ef75 100644 (file)
@@ -87,7 +87,6 @@
 
 /* Ethernet */
 #define CONFIG_MACB
-#define CONFIG_PHYLIB
 #define CONFIG_RMII
 #define CONFIG_AT91_WANTS_COMMON_PHY
 
index 67b5774..546f2d3 100644 (file)
 #define CONFIG_SYS_NS16550_CLK         166666666
 
 /*
- * Ethernet PHY configuration
- */
-#define CONFIG_PHY_GIGE
-
-/*
  * Even though the board houses Realtek RTL8211E PHY
  * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly.
  * In particular "parse_status" reports link is down.
index 4baccdc..5271b5c 100644 (file)
@@ -59,7 +59,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         4
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
index cea84ac..23f4dbf 100644 (file)
@@ -37,7 +37,6 @@
 #define EEPROM_ADDR_CHIP 0x120
 
 #undef CONFIG_MII
-#undef CONFIG_PHY_GIGE
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_FACTORYSET
index b5f8177..4d9ec79 100644 (file)
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT         10
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ET1011C
 #define CONFIG_PHY_ET1011C_TX_CLK_FIX
 
index 26290ef..03e28fc 100644 (file)
@@ -97,7 +97,6 @@
 #endif
 
 /* Network Configuration */
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_MARVELL
 #define CONFIG_MII
 #define CONFIG_BOOTP_DEFAULT
index 606da4a..3fb63f3 100644 (file)
@@ -45,9 +45,6 @@
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_FEC_MXC_PHYADDR         4
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORT    1
index a03ad67..b670cc4 100644 (file)
@@ -65,6 +65,5 @@
 #define CONFIG_CMD_MEMTEST
 
 #define CONFIG_CMD_MII
-#define CONFIG_PHY_GIGE
 
 #endif  /* __CONFIG_H */
index b5b7157..8cc0018 100644 (file)
@@ -81,7 +81,6 @@
 
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
-#define CONFIG_PHYLIB
 #define CONFIG_MII
 
 #define CONFIG_ARP_TIMEOUT             200UL
index 69e9079..9c7e5a4 100644 (file)
@@ -14,8 +14,6 @@
 #define CONFIG_ETHPRIME                        "FEC"
 
 #define CONFIG_FEC_MXC_PHYADDR         0x03
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_KSZ9031
 
 #define CONFIG_MXC_UART_BASE           UART2_BASE
 #define CONSOLE_DEV            "ttymxc1"
index 959db5f..0219376 100644 (file)
@@ -61,7 +61,6 @@
  * Eth Configs
  */
 #define CONFIG_MII
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_FEC_MXC
index d3fa5d7..26a1a6f 100644 (file)
@@ -41,9 +41,6 @@
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_ETHPRIME                 "FEC"
 #define CONFIG_FEC_MXC_PHYADDR          6
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
 
 #define CONFIG_SYS_MEMTEST_START       0x10000000
 #define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
index 60b76ed..9b0a20d 100644 (file)
 #define CONFIG_FEC_XCV_TYPE             RMII
 #define CONFIG_ETHPRIME                 "FEC0"
 
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-
 #endif                         /* __CONFIG_H */
index 04abe1e..6aaa4d1 100644 (file)
@@ -59,8 +59,6 @@
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 
 /* QSPI Configs*/
 
index 0fed7f3..77da9e5 100644 (file)
@@ -72,7 +72,6 @@
 #define CONFIG_FEC_XCV_TYPE             RMII
 #define CONFIG_ETHPRIME                 "FEC"
 
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 #ifdef CONFIG_CMD_USB
index a8a48a5..ed25f42 100644 (file)
@@ -60,7 +60,6 @@
 #define CONFIG_FEC_XCV_TYPE            RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         1
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
index dc8008c..f3eba9c 100644 (file)
@@ -88,8 +88,6 @@
  */
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE   FEC_BASE_ADDR
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
 #define CONFIG_FEC_MXC_PHYADDR 0x1
 
 #define CONFIG_MII
index 0ac7b85..f7a3df1 100644 (file)
@@ -57,7 +57,6 @@
 
 #define CONFIG_PHY_SMSC
 #define CONFIG_LPC32XX_ETH
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR 0
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
index a8435d8..18167a8 100644 (file)
@@ -74,9 +74,6 @@
 #define CONFIG_MII
 #define CONFIG_PHY_RESET_DELAY                 10000           /* in usec */
 #define CONFIG_PHY_ADDR                0       /* PHY address */
-#define CONFIG_PHY_GIGE                        /* Include GbE speed/duplex detection */
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
 
 #define CONFIG_SPEAR_GPIO
 
index 363c292..77d7899 100644 (file)
 # define CONFIG_PHY_MARVELL
 # define CONFIG_PHY_NATSEMI
 # define CONFIG_PHY_TI
-# define CONFIG_PHY_GIGE
 # define CONFIG_PHY_VITESSE
 # define CONFIG_PHY_REALTEK
 # define PHY_ANEG_TIMEOUT       20000
index c21c944..478ca50 100644 (file)
@@ -304,7 +304,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Networking options
  */
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_ETHPRIME                "eTSEC1"
 
index eb80154..f54971e 100644 (file)
  * Networking options
  */
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_ETHPRIME                "eTSEC1"
 
index bc42313..c32b63d 100644 (file)
@@ -304,7 +304,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Networking options
  */
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #define CONFIG_TSEC_TBI
 #define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC        1       /* Allow unregistered phys */
index 13be539..7b0a0c6 100644 (file)
@@ -290,7 +290,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Networking options
  */
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
-#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
 #define CONFIG_TSEC_TBI
 #define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC        1       /* Allow unregistered phys */
index 629e3df..fdb504d 100644 (file)
@@ -75,7 +75,6 @@
 #define CONFIG_FEC_MXC_PHYADDR          0x0
 #define CONFIG_FEC_XCV_TYPE             RMII
 #define CONFIG_ETHPRIME                        "FEC"
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_IMX_THERMAL
index 61c6a60..f71cdfb 100644 (file)
@@ -25,7 +25,6 @@
 #define CONFIG_FEC_XCV_TYPE                    RGMII
 #define CONFIG_ETHPRIME                                "FEC"
 #define CONFIG_FEC_MXC_PHYADDR                 0x10
-#define CONFIG_PHYLIB
 #define CONFIG_FEC_FIXED_SPEED                 1000 /* No autoneg, fix Gb */
 
 #endif                         /*__EL6Q_CONFIG_H */
index 2eaa882..e126948 100644 (file)
@@ -308,7 +308,7 @@ struct ethernet_hdr {
        u8              et_dest[ARP_HLEN];      /* Destination node     */
        u8              et_src[ARP_HLEN];       /* Source node          */
        u16             et_protlen;             /* Protocol or length   */
-};
+} __attribute__((packed));
 
 /* Ethernet header size */
 #define ETHER_HDR_SIZE (sizeof(struct ethernet_hdr))
@@ -326,7 +326,7 @@ struct e802_hdr {
        u8              et_snap2;
        u8              et_snap3;
        u16             et_prot;                /* 802 protocol         */
-};
+} __attribute__((packed));
 
 /* 802 + SNAP + ethernet header size */
 #define E802_HDR_SIZE  (sizeof(struct e802_hdr))
@@ -340,7 +340,7 @@ struct vlan_ethernet_hdr {
        u16             vet_vlan_type;          /* PROT_VLAN            */
        u16             vet_tag;                /* TAG of VLAN          */
        u16             vet_type;               /* protocol type        */
-};
+} __attribute__((packed));
 
 /* VLAN Ethernet header size */
 #define VLAN_ETHER_HDR_SIZE    (sizeof(struct vlan_ethernet_hdr))
@@ -369,7 +369,7 @@ struct ip_hdr {
        u16             ip_sum;         /* checksum                     */
        struct in_addr  ip_src;         /* Source IP address            */
        struct in_addr  ip_dst;         /* Destination IP address       */
-};
+} __attribute__((packed));
 
 #define IP_OFFS                0x1fff /* ip offset *= 8 */
 #define IP_FLAGS       0xe000 /* first 3 bits */
@@ -397,7 +397,7 @@ struct ip_udp_hdr {
        u16             udp_dst;        /* UDP destination port         */
        u16             udp_len;        /* Length of UDP packet         */
        u16             udp_xsum;       /* Checksum                     */
-};
+} __attribute__((packed));
 
 #define IP_UDP_HDR_SIZE                (sizeof(struct ip_udp_hdr))
 #define UDP_HDR_SIZE           (IP_UDP_HDR_SIZE - IP_HDR_SIZE)
@@ -435,7 +435,7 @@ struct arp_hdr {
        u8              ar_tha[];       /* Target hardware address      */
        u8              ar_tpa[];       /* Target protocol address      */
 #endif /* 0 */
-};
+} __attribute__((packed));
 
 #define ARP_HDR_SIZE   (8+20)          /* Size assuming ethernet       */
 
@@ -470,7 +470,7 @@ struct icmp_hdr {
                } frag;
                u8 data[0];
        } un;
-};
+} __attribute__((packed));
 
 #define ICMP_HDR_SIZE          (sizeof(struct icmp_hdr))
 #define IP_ICMP_HDR_SIZE       (IP_HDR_SIZE + ICMP_HDR_SIZE)
index 4f2094b..a0b1f12 100644 (file)
@@ -266,7 +266,8 @@ int phy_davicom_init(void);
 int phy_et1011c_init(void);
 int phy_lxt_init(void);
 int phy_marvell_init(void);
-int phy_micrel_init(void);
+int phy_micrel_ksz8xxx_init(void);
+int phy_micrel_ksz90x1_init(void);
 int phy_natsemi_init(void);
 int phy_realtek_init(void);
 int phy_smsc_init(void);
diff --git a/include/sed156x.h b/include/sed156x.h
deleted file mode 100644 (file)
index 4e24e01..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2004
- *
- * Pantelis Antoniou <panto@intracom.gr>
- * Intracom S.A.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/* Video support for Epson SED156x chipset(s) */
-
-#ifndef SED156X_H
-#define SED156X_H
-
-void sed156x_init(void);
-void sed156x_clear(void);
-void sed156x_output_at(int x, int y, const char *str, int size);
-void sed156x_reverse_at(int x, int y, int size);
-void sed156x_sync(void);
-void sed156x_scroll(int dx, int dy);
-
-/* export display */
-extern const int sed156x_text_width;
-extern const int sed156x_text_height;
-
-#endif /* SED156X_H */
diff --git a/include/sm501.h b/include/sm501.h
deleted file mode 100644 (file)
index 34ce350..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * (C) Copyright 2005
- * Martin Krause TQ-Systems GmbH martin.krause@tqs.de
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Basic video support for SMI SM501 "Voyager" graphic controller
- */
-
-#ifndef _SM501_H_
-#define _SM501_H_
-
-#define PCI_VENDOR_SM          0x126f
-#define PCI_DEVICE_SM501       0x0501
-
-typedef struct {
-       unsigned int Index;
-       unsigned int Value;
-} SMI_REGS;
-
-/* Board specific functions                                                  */
-unsigned int board_video_init (void);
-void board_validate_screen (unsigned int base);
-const SMI_REGS *board_get_regs (void);
-int board_get_width (void);
-int board_get_height (void);
-unsigned int board_video_get_fb (void);
-
-#endif /* _SM501_H_ */
index fcb0a64..567340e 100644 (file)
@@ -49,7 +49,7 @@ struct bootp_hdr {
        char            bp_sname[64];   /* Server host name             */
        char            bp_file[128];   /* Boot file name               */
        char            bp_vend[OPT_FIELD_SIZE]; /* Vendor information  */
-};
+} __attribute__((packed));
 
 #define BOOTP_HDR_SIZE sizeof(struct bootp_hdr)
 
index c4e96af..c55a5c1 100644 (file)
--- a/net/dns.h
+++ b/net/dns.h
@@ -29,7 +29,7 @@ struct header {
        uint16_t        nauth;          /* Authority PRs */
        uint16_t        nother;         /* Other PRs */
        unsigned char   data[1];        /* Data, variable length */
-};
+} __attribute__((packed));
 
 void dns_start(void);          /* Begin DNS */
 
index 6e67877..2268890 100644 (file)
--- a/net/net.c
+++ b/net/net.c
@@ -489,7 +489,7 @@ restart:
                        cdp_start();
                        break;
 #endif
-#if defined(CONFIG_NETCONSOLE) && !(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
                case NETCONS:
                        nc_start();
                        break;
@@ -1258,7 +1258,7 @@ void net_process_received_packet(uchar *in_packet, int len)
                }
 #endif
 
-#if defined(CONFIG_NETCONSOLE) && !(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
                nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE,
                                src_ip,
                                ntohs(ip->udp_dst),
index ba9d064..4bf9bd8 100644 (file)
  */
 static inline unsigned int seed_mac(void)
 {
-       unsigned char enetaddr[6];
+       unsigned char enetaddr[ARP_HLEN];
        unsigned int seed;
 
        /* get our mac */
-       eth_getenv_enetaddr("ethaddr", enetaddr);
+       memcpy(enetaddr, eth_get_ethaddr(), ARP_HLEN);
 
        seed = enetaddr[5];
        seed ^= enetaddr[4] << 8;
index 45da246..70a1a6d 100644 (file)
--- a/net/nfs.h
+++ b/net/nfs.h
@@ -79,7 +79,7 @@ struct rpc_t {
                        uint32_t data[NFS_READ_SIZE];
                } reply;
        } u;
-};
+} __attribute__((packed));
 void nfs_start(void);  /* Begin NFS */
 
 
index 6a9c6bb..c38bcee 100644 (file)
@@ -51,7 +51,7 @@ struct sntp_pkt_t {
        unsigned long long originate_timestamp;
        unsigned long long receive_timestamp;
        unsigned long long transmit_timestamp;
-};
+} __attribute__((packed));
 
 void sntp_start(void); /* Begin SNTP */
 
index ced45ec..61e1671 100644 (file)
@@ -742,8 +742,8 @@ void tftp_start(enum proto_t protocol)
                        (net_ip.s_addr >> 16) & 0xFF,
                        (net_ip.s_addr >> 24) & 0xFF);
 
-               strncpy(tftp_filename, default_filename, MAX_LEN);
-               tftp_filename[MAX_LEN - 1] = 0;
+               strncpy(tftp_filename, default_filename, DEFAULT_NAME_LEN);
+               tftp_filename[DEFAULT_NAME_LEN - 1] = 0;
 
                printf("*** Warning: no boot file name; using '%s'\n",
                       tftp_filename);
index 3b5c17a..2dacf79 100644 (file)
@@ -157,9 +157,6 @@ CONFIG_BCH_CONST_PARAMS
 CONFIG_BCH_CONST_T
 CONFIG_BCM2835_GPIO
 CONFIG_BCM283X_MU_SERIAL
-CONFIG_BCM_SF2_ETH
-CONFIG_BCM_SF2_ETH_DEFAULT_PORT
-CONFIG_BCM_SF2_ETH_GMAC
 CONFIG_BIOSEMU
 CONFIG_BITBANGMII_MULTI
 CONFIG_BL1_OFFSET
@@ -5204,7 +5201,6 @@ CONFIG_VIDEO_MXS
 CONFIG_VIDEO_MXS_MODE_SYSTEM
 CONFIG_VIDEO_OMAP3
 CONFIG_VIDEO_ONBOARD
-CONFIG_VIDEO_SM501_PCI
 CONFIG_VIDEO_STD_TIMINGS
 CONFIG_VIDEO_SUNXI
 CONFIG_VIDEO_VCXK