Merge with git://www.denx.de/git/u-boot.git

diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 45bcd4b..5fe3af9 100644 (file)
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -126,6 +126,9 @@ tlbtab:
        /* TLB-entry for peripherals */
        tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
+       /* TLB-entry PCI IO Space - from sr@denx.de */
+       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
        tlbtab_end
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index 2378553..acfda83 100644 (file)
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -28,6 +28,11 @@
 
 #define        PCIAUTO_IDE_MODE_MASK           0x05
 
+/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CFG_PCI_CACHE_LINE_SIZE
+#define CFG_PCI_CACHE_LINE_SIZE        8
+#endif
+
 /*
  *
  */
@@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose,
        }
 
        pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
-       pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+       pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
+               CFG_PCI_CACHE_LINE_SIZE);
        pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 }
 

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 824a812..c2e1386 100644 (file)
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -400,7 +400,8 @@
  *----------------------------------------------------------------------*/
 /* General PCI */
 #define CONFIG_PCI                     /* include pci support          */
-#undef CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play   */
+#define CFG_PCI_CACHE_LINE_SIZE        0 /* to avoid problems with PNP */
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup  */
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/