/u-boot.sha1
/u-boot.dis
/u-boot.lds
+/u-boot.ubl
#
# Generated files
E: ThomasF@hyperion-entertainment.com
D: Support for AmigaOne
-N: Niklaus Giger
-E: niklaus.giger@netstal.com
-D: Support for HCU(x) boards
-W: www.netstal.com
-
N: Paul Gortmaker
E: paul.gortmaker@windriver.com
D: Support for WRS SBC8347/8349 boards
WUH405 PPC405EP
CMS700 PPC405EP
-Niklaus Giger <niklaus.giger@netstal.com>
-
- HCU4 PPC405GPr
- MCU25 PPC405GPr
- HCU5 PPC440EPx
-
Siddarth Gore <gores@marvell.com>
guruplug ARM926EJS (Kirkwood SoC)
EVB64260 MPC7xx_74xx
+ integratorcp various
+ versatile ARM926EJ-S
+ versatile ARM926EJ-S
+
#########################################################################
# ARM Systems: #
edb9315 ARM920T (EP9315)
edb9315a ARM920T (EP9315)
-Konstantin Kletschke <kletschke@synertronixx.de>
- scb9328 ARM920T
-
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
SMDKV310 ARM ARMV7 (S5PC210 SoC)
+Torsten Koschorrek <koschorrek@synertronixx.de>
+ scb9328 ARM920T (i.MXL)
+
Frederik Kriewitz <frederik@kriewitz.eu>
devkit8000 ARM ARMV7 (OMAP3530 SoC)
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
-Peter Pearse <peter.pearse@arm.com>
- integratorcp All current ARM supplied & supported core modules
- -see http://www.arm.com/products/DevTools/Hardware_Platforms.html
- versatile ARM926EJ-S
- versatile ARM926EJ-S
+Linus Walleij <linus.walleij@linaro.org>
+ integratorap ARM920T
Dave Peverley <dpeverley@mpc-data.co.uk>
Matthias Weisser <weisserm@arcor.de>
jadecpu ARM926EJS (MB86R01 SoC)
+ zmx25 ARM926EJS (imx25 SoC)
Richard Woodruff <r-woodruff2@ti.com>
#!/bin/bash
-
# Tool mainly for U-Boot Quality Assurance: build one or more board
# configurations with minimal verbosity, showing only warnings and
# errors.
-#
-# There are several ways to select which boards to build.
-#
-# Traditionally, architecture names (like "powerpc"), CPU family names
-# (like "mpc83xx") or board names can be specified on the command
-# line; without any arguments, MAKEALL defaults to building all Power
-# Architecture systems (i. e. same as for "MAKEALL powerpc").
-#
-# With the introduction of the board.cfg file, it has become possible
-# to provide additional selections. We use standard command line
-# options for this:
-#
-# -a or --arch : Select architecture
-# -c or --cpu : Select CPU family
-# -s or --soc : Select SoC type
-# -v or --vendor: Select board vendor
-#
-# Selections by these options are logically ANDed; if the same option
-# is used repeatedly, such selections are ORed. So "-v FOO -v BAR"
-# will select all configurations where the vendor is either FOO or
-# BAR. Any additional arguments specified on the command line are
-# always build additionally.
-#
-# Examples:
-#
-# - build all Power Architecture boards:
-#
-# MAKEALL -a powerpc
-# or
-# MAKEALL --arch powerpc
-# or
-# MAKEALL powerpc
-#
-# - build all PowerPC boards manufactured by vendor "esd":
-#
-# MAKEALL -a powerpc -v esd
-#
-# - build all PowerPC boards manufactured either by "keymile" or
-# "siemens":
-#
-# MAKEALL -a powerpc -v keymile -v siemens
-#
-# - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards:
-#
-# MAKEALL -c mpc83xx -v freescale 4xx
-#
-#########################################################################
-
-SHORT_OPTS="a:c:v:s:"
-LONG_OPTS="arch:,cpu:,vendor:,soc:"
+
+usage()
+{
+ # if exiting with 0, write to stdout, else write to stderr
+ local ret=${1:-0}
+ [ "${ret}" -eq 1 ] && exec 1>&2
+ cat <<-EOF
+ Usage: MAKEALL [options] [--] [boards-to-build]
+
+ Options:
+ -a ARCH, --arch ARCH Build all boards with arch ARCH
+ -c CPU, --cpu CPU Build all boards with cpu CPU
+ -v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR
+ -s SOC, --soc SOC Build all boards with soc SOC
+ -h, --help This help output
+
+ Selections by these options are logically ANDed; if the same option
+ is used repeatedly, such selections are ORed. So "-v FOO -v BAR"
+ will select all configurations where the vendor is either FOO or
+ BAR. Any additional arguments specified on the command line are
+ always build additionally. See the boards.cfg file for more info.
+
+ If no boards are specified, then the default is "powerpc".
+
+ Environment variables:
+ BUILD_NCPUS number of parallel make jobs (default: auto)
+ CROSS_COMPILE cross-compiler toolchain prefix (default: "")
+ MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
+ BUILD_DIR output build directory (default: ./)
+
+ Examples:
+ - build all Power Architecture boards:
+ MAKEALL -a powerpc
+ MAKEALL --arch powerpc
+ MAKEALL powerpc
+ - build all PowerPC boards manufactured by vendor "esd":
+ MAKEALL -a powerpc -v esd
+ - build all PowerPC boards manufactured either by "keymile" or "siemens":
+ MAKEALL -a powerpc -v keymile -v siemens
+ - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards:
+ MAKEALL -c mpc83xx -v freescale 4xx
+ EOF
+ exit ${ret}
+}
+
+SHORT_OPTS="ha:c:v:s:"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:"
# Option processing based on util-linux-2.13/getopt-parse.bash
TEMP=`getopt -o ${SHORT_OPTS} --long ${LONG_OPTS} \
-n 'MAKEALL' -- "$@"`
-if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi
+[ $? != 0 ] && usage 1
# Note the quotes around `$TEMP': they are essential!
eval set -- "$TEMP"
fi
SELECTED='y'
shift 2 ;;
+ -h|--help)
+ usage ;;
--)
shift ; break ;;
*)
endif # ifneq ($(BUILD_DIR),)
OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
+SPLTREE := $(OBJTREE)/spl
SRCTREE := $(CURDIR)
TOPDIR := $(SRCTREE)
LNDIR := $(OBJTREE)
-export TOPDIR SRCTREE OBJTREE
+export TOPDIR SRCTREE OBJTREE SPLTREE
MKCONFIG := $(SRCTREE)/mkconfig
export MKCONFIG
endif
# Always append ALL so that arch config.mk's can add custom ones
-ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
+ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
-ifeq ($(CONFIG_NAND_U_BOOT),y)
-ALL += $(obj)u-boot-nand.bin
-endif
-
-ifeq ($(CONFIG_ONENAND_U_BOOT),y)
-ALL += $(obj)u-boot-onenand.bin
+ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
+ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
-endif
+ALL-$(CONFIG_MMC_U_BOOT) += $(obj)mmc_spl/u-boot-mmc-spl.bin
+ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
-ifeq ($(CONFIG_MMC_U_BOOT),y)
-ALL += $(obj)mmc_spl/u-boot-mmc-spl.bin
-endif
-
-all: $(ALL)
+all: $(ALL-y)
$(obj)u-boot.hex: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
$(obj)u-boot.img: $(obj)u-boot.bin
$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
- -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
+ -O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
+$(obj)u-boot.ubl: $(obj)u-boot-nand.bin
+ $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
+ -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+
GEN_UBOOT = \
UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
$(obj)mmc_spl/u-boot-mmc-spl.bin: mmc_spl
+$(obj)spl/u-boot-spl.bin: depend
+ $(MAKE) -C spl all
+
$(TIMESTAMP_FILE):
@LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
@LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@
TAG_SUBDIRS += $(dir $(__LIBS))
TAG_SUBDIRS += include
+FIND := find
+FINDFLAGS := -L
+
tags ctags:
- ctags -w -o $(obj)ctags `find $(TAG_SUBDIRS) \
+ ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
etags:
- etags -a -o $(obj)etags `find $(TAG_SUBDIRS) \
+ etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
cscope:
- find $(TAG_SUBDIRS) -name '*.[chS]' -print > cscope.files
+ $(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \
+ cscope.files
cscope -b -q -k
SYSTEM_MAP = \
endif # config.mk
$(VERSION_FILE):
+ @mkdir -p $(dir $(VERSION_FILE))
@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
printf '#define PLAIN_VERSION "%s%s"\n' \
"$(U_BOOT_VERSION)" "$${localvers}" ; \
@rm -f $(obj)mmc_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
+ @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
| xargs -0 rm -f
@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
$(obj)cscope.* $(obj)*.*~
- @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
+ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.imx
+ @rm -f $(obj)u-boot.ubl
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)mmc_spl ] || find $(obj)mmc_spl -name "*" -type l -print | xargs rm -f
-ifeq ($(OBJTREE),$(SRCTREE))
-mrproper \
-distclean: clobber unconfig
-else
mrproper \
distclean: clobber unconfig
+ifneq ($(OBJTREE),$(SRCTREE))
rm -rf $(obj)*
endif
/lib Architecture specific library files
/mips Files generic to MIPS architecture
/cpu CPU specific files
+ /mips32 Files specific to MIPS32 CPUs
/lib Architecture specific library files
/nios2 Files generic to Altera NIOS2 architecture
/cpu CPU specific files
2. The core frequency as calculated above is multiplied
by this value.
+- MIPS CPU options:
+ CONFIG_SYS_INIT_SP_OFFSET
+
+ Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
+ pointer. This is needed for the temporary stack before
+ relocation.
+
+ CONFIG_SYS_MIPS_CACHE_MODE
+
+ Cache operation mode for the MIPS CPU.
+ See also arch/mips/include/asm/mipsregs.h.
+ Possible values are:
+ CONF_CM_CACHABLE_NO_WA
+ CONF_CM_CACHABLE_WA
+ CONF_CM_UNCACHED
+ CONF_CM_CACHABLE_NONCOHERENT
+ CONF_CM_CACHABLE_CE
+ CONF_CM_CACHABLE_COW
+ CONF_CM_CACHABLE_CUW
+ CONF_CM_CACHABLE_ACCELERATED
+
+ CONFIG_SYS_XWAY_EBU_BOOTCFG
+
+ Special option for Lantiq XWAY SoCs for booting from NOR flash.
+ See also arch/mips/cpu/mips32/start.S.
+
+ CONFIG_XWAY_SWAP_BYTES
+
+ Enable compilation of tools/xway-swap-bytes needed for Lantiq
+ XWAY SoCs for booting from NOR flash. The U-Boot image needs to
+ be swapped if a flash programmer is used.
+
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
+ CONFIG_MACH_TYPE [relevant for ARM only][mandatory]
+
+ This setting is mandatory for all boards that have only one
+ machine type and must be used to specify the machine type
+ number as it appears in the ARM machine registry
+ (see http://www.arm.linux.org.uk/developer/machines/).
+ Only boards that have multiple machine types supported
+ in a single configuration file and the machine type is
+ runtime discoverable, do not have to use this setting.
+
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
enabled with CONFIG_CMD_MMC. The MMC driver also works with
the FAT fs. This is enabled with CONFIG_CMD_FAT.
+ CONFIG_SH_MMCIF
+ Support for Renesas on-chip MMCIF controller
+
+ CONFIG_SH_MMCIF_ADDR
+ Define the base address of MMCIF registers
+
+ CONFIG_SH_MMCIF_CLK
+ Define the clock frequency for MMCIF
+
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
CONFIG_JFFS2_NAND_DEV
=>
If you now switch to the new I2C Bus 3 with "i2c dev 3"
- u-boot sends First the Commando to the mux@70 to enable
- channel 6, and then the Commando to the mux@71 to enable
+ u-boot first sends the command to the mux@70 to enable
+ channel 6, and then the command to the mux@71 to enable
the channel 4.
After that, you can use the "normal" i2c commands as
- usual, to communicate with your I2C devices behind
+ usual to communicate with your I2C devices behind
the 2 muxes.
This option is actually implemented for the bitbanging
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
+- SPL framework
+ CONFIG_SPL
+ Enable building of SPL globally.
+
+ CONFIG_SPL_TEXT_BASE
+ TEXT_BASE for linking the SPL binary.
+
+ CONFIG_SPL_LDSCRIPT
+ LDSCRIPT for linking the SPL binary.
+
+ CONFIG_SPL_LIBCOMMON_SUPPORT
+ Support for common/libcommon.o in SPL binary
+
+ CONFIG_SPL_LIBDISK_SUPPORT
+ Support for disk/libdisk.o in SPL binary
+
+ CONFIG_SPL_I2C_SUPPORT
+ Support for drivers/i2c/libi2c.o in SPL binary
+
+ CONFIG_SPL_GPIO_SUPPORT
+ Support for drivers/gpio/libgpio.o in SPL binary
+
+ CONFIG_SPL_MMC_SUPPORT
+ Support for drivers/mmc/libmmc.o in SPL binary
+
+ CONFIG_SPL_SERIAL_SUPPORT
+ Support for drivers/serial/libserial.o in SPL binary
+
+ CONFIG_SPL_SPI_FLASH_SUPPORT
+ Support for drivers/mtd/spi/libspi_flash.o in SPL binary
+
+ CONFIG_SPL_SPI_SUPPORT
+ Support for drivers/spi/libspi.o in SPL binary
+
+ CONFIG_SPL_FAT_SUPPORT
+ Support for fs/fat/libfat.o in SPL binary
+
+ CONFIG_SPL_LIBGENERIC_SUPPORT
+ Support for lib/libgeneric.o in SPL binary
Modem Support:
--------------
of environment data (variable area); in general, we support the
following configurations:
+- CONFIG_BUILD_ENVCRC:
+
+ Builds up envcrc with the target environment so that external utils
+ may easily extract it and embed it in final U-Boot images.
+
- CONFIG_ENV_IS_IN_FLASH:
Define this if the environment is in flash memory.
globally (CONFIG_CMD_MEM).
- CONFIG_SKIP_LOWLEVEL_INIT
- [ARM only] If this variable is defined, then certain
+ [ARM, MIPS only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
other boot loader or by a debugger which performs
these initializations itself.
-- CONFIG_PRELOADER
+- CONFIG_SPL_BUILD
Modifies the behaviour of start.S when compiling a loader
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
This can be used to load and uncompress arbitrary
data.
+ fdt_high - if set this restricts the maximum address that the
+ flattened device tree will be copied into upon boot.
+ If this is set to the special value 0xFFFFFFFF then
+ the fdt will not be copied at all on boot. For this
+ to work it must reside in writable memory, have
+ sufficient padding on the end of it for u-boot to
+ add the information it needs into it, and the memory
+ must be accessible by the kernel.
+
i2cfast - (PPC405GP|PPC405EP only)
if set to 'y' configures Linux I2C driver for fast
mode (400kHZ). This environment variable is used in
All contributions to U-Boot should conform to the Linux kernel
coding style; see the file "Documentation/CodingStyle" and the script
-"scripts/Lindent" in your Linux kernel source directory. In sources
-originating from U-Boot a style corresponding to "Lindent -pcs" (adding
-spaces before parameters to function calls) is actually used.
+"scripts/Lindent" in your Linux kernel source directory.
Source files originating from a different project (for example the
MTD subsystem) are generally exempt from these guidelines and are not
Please also stick to the following formatting rules:
- remove any trailing white space
-- use TAB characters for indentation, not spaces
+- use TAB characters for indentation and vertical alignment, not spaces
- make sure NOT to use DOS '\r\n' line feeds
-- do not add more than 2 empty lines to source files
+- do not add more than 2 consecutive empty lines to source files
- do not add trailing empty lines to source files
Submissions which do not conform to the standards may be returned
* For major contributions, your entry to the CREDITS file
* When you add support for a new board, don't forget to add this
- board to the MAKEALL script, too.
+ board to the MAINTAINERS file, too.
* If your patch adds new configuration options, don't forget to
document these in the README file.
* The patch itself. If you are using git (which is *strongly*
recommended) you can easily generate the patch using the
- "git-format-patch". If you then use "git-send-email" to send it to
+ "git format-patch". If you then use "git send-email" to send it to
the U-Boot mailing list, you will avoid most of the common problems
with some other mail clients.
# For EABI, make sure to provide raise()
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
-# This file is parsed several times; make sure to add only once.
-ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS)))
-PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
+# This file is parsed many times, so the string may get added multiple
+# times. Also, the prefix needs to be different based on whether
+# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
+# before adding the correct one.
+ifdef CONFIG_SPL_BUILD
+PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \
+ $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
+else
+PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \
+ $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
endif
endif
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
#include <asm/io.h>
static u32 mx31_decode_pll(u32 reg, u32 infreq)
return mx31_get_mpl_dpdgck_clk();
}
-u32 mx31_get_ipg_clk(void)
+static u32 mx31_get_ipg_clk(void)
{
u32 freq = mx31_get_mcu_main_clk();
u32 pdr0 = __REG(CCM_PDR0);
printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
}
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return mx31_get_mcu_main_clk();
+ case MXC_IPG_CLK:
+ case MXC_CSPI_CLK:
+ case MXC_UART_CLK:
+ return mx31_get_ipg_clk();
+ }
+ return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return mxc_get_clock(MXC_UART_CLK);
+}
+
void mx31_gpio_mux(unsigned long mode)
{
unsigned long reg, shift, tmp;
return 0;
}
-void reset_timer_masked (void)
-{
- /* reset time */
- gd->lastinc = GPTCNT; /* capture current incrementer value time */
- gd->tbl = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
unsigned long long get_ticks (void)
{
ulong now = GPTCNT; /* current tick value */
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- gd->tbl = time_to_tick(t);
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay (unsigned long usec)
{
sinclude $(obj).depend
#########################################################################
-
-$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
- ./asm-offsets.s
- @echo Generating $@
- $(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@
-
-asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
- ./asm-offsets.c
- $(CC) -DDO_DEPS_ONLY \
- $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ ./asm-offsets.c -c -S
return val;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
ulong tmp;
return (tmp / 1000) - base;
}
-void set_timer(ulong t)
-{
-}
-
/*
* delay x useconds AND preserve advance timstamp value
* GPTCNT is now supposed to tick 1 by 1 us.
DECLARE_GLOBAL_DATA_PTR;
+static void reset_timer_masked (void)
+{
+ /* reset time */
+ gd->lastinc = READ_TIMER; /* capture current incrementer value time */
+ gd->tbl = 0; /* start "advancing" time stamp from 0 */
+}
+
int timer_init (void)
{
int32_t val;
/*
* timer without interrupts
*/
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- gd->tbl = t;
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay (unsigned long usec)
{
/*NOP*/;
}
-void reset_timer_masked (void)
-{
- /* reset time */
- gd->lastinc = READ_TIMER; /* capture current incrementer value time */
- gd->tbl = 0; /* start "advancing" time stamp from 0 */
-}
-
ulong get_timer_masked (void)
{
ulong now = READ_TIMER; /* current tick value */
#include <version.h>
.globl _start
_start: b reset
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
.global _end_vect
_end_vect:
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
add r0, r0, #4
cmp r0, r1
bne clbss_l
-#endif /* #ifndef CONFIG_PRELOADER */
+#endif /* #ifndef CONFIG_SPL_BUILD */
/*
* We are done. Do not return, instead branch to second part of board
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
/*
* exception handlers
*/
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
-#else /* !CONFIG_PRELOADER */
+#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
#endif
mov pc, lr @ back to caller
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
return (ulong)(timer_load_val / 100);
}
-void reset_timer_masked(void)
-{
- /* reset time */
- lastdec = read_timer();
- timestamp = 0;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer_masked(void)
{
unsigned long long res = get_ticks();
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
-}
-
void __udelay(unsigned long usec)
{
unsigned long long tmp;
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
return 0;
}
-void reset_timer(void)
-{
- lastinc = timestamp = 0;
-
- __raw_writel(0, ®s->tcr);
- __raw_writel(0, ®s->tim34);
- __raw_writel(2 << 22, ®s->tcr);
-}
-
static ulong get_timer_raw(void)
{
ulong now = __raw_readl(®s->tim34);
return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
unsigned long long get_ticks(void)
{
return get_timer(0);
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
void __udelay (unsigned long usec)
{
ulong tmo;
#endif
}
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER;
- timestamp = 0;
-}
-
ulong get_timer_masked (void)
{
ulong now = READ_TIMER;
/* Command 16 to read aBlocks from the MMC/SD - caed */
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
/* Command 24 to write a block to the MMC/SD - card */
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-/* Interupt-Controller base addresses */
+/* Interrupt-Controller base addresses */
INTMR1: .word 0x80000280 @ 32 bit size
INTMR2: .word 0x80001280 @ 16 bit size
INTMR3: .word 0x80002280 @ 8 bit size
debug("%s(): lastdec = %lx\n", __func__, lastdec);
}
-void reset_timer(void)
-{
- debug("%s()\n", __func__);
- reset_timer_masked();
-}
-
/*
* return timer ticks
*/
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- debug("%s(%lx)\n", __func__, t);
- timestamp = t;
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay(unsigned long usec)
{
when the value in TC_RC is reached */
writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
- writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
+ writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
/*
* timer without interrupts
*/
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- gd->tbl = t;
-}
-
void __udelay(unsigned long usec)
{
udelay_masked(usec);
}
-void reset_timer_masked(void)
-{
- /* reset time */
- at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
- gd->lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
- gd->tbl = 0;
-}
-
ulong get_timer_raw(void)
{
at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
{
unsigned int timeout;
+ unsigned long start;
pDesc->state = BUSY;
}
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
timeout = 0;
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
- ((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT));
+ ((timeout = get_timer(start) ) < CONFIG_SYS_SPI_WRITE_TOUT));
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
pDesc->state = IDLE;
/*
* timer without interrupts
*/
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
void __udelay (unsigned long usec)
{
udelay_masked(usec);
}
-void reset_timer_masked (void)
-{
- /* reset time */
- lastinc = READ_TIMER;
- timestamp = 0;
-}
-
ulong get_timer_raw (void)
{
ulong now = READ_TIMER;
return get_timer_masked() - base;
}
-void reset_timer_masked(void)
-{
- read_timer();
- timer.ticks = 0;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
void __udelay(unsigned long usec)
{
unsigned long long target;
writel(TIMER_ENABLE | TIMER_CLKSEL,
&timer_regs->timer3.control);
- reset_timer_masked();
+ /* Reset the timer */
+ read_timer();
+ timer.ticks = 0;
return 0;
}
TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
- reset_timer_masked();
+ /* Reset the timer */
+ TCTL1 &= ~TCTL_TEN;
+ TCTL1 |= TCTL_TEN; /* Enable timer */
return (0);
}
/*
* timer without interrupts
*/
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked() - base;
}
-void set_timer (ulong t)
-{
- /* nop */
-}
-
-void reset_timer_masked (void)
-{
- TCTL1 &= ~TCTL_TEN;
- TCTL1 |= TCTL_TEN; /* Enable timer */
-}
-
ulong get_timer_masked (void)
{
return TCN1;
int timer_init (void)
{
- reset_timer();
+ /* Set the hadware timer for 1ms */
+ ks8695_write(KS8695_TIMER1, TIMER_COUNT);
+ ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
+ ks8695_write(KS8695_TIMER_CTRL, 0x2);
+ timer_ticks = 0;
return 0;
}
#define TIMER_COUNT (TIMER_INTERVAL / 2)
#define TIMER_PULSE TIMER_COUNT
-void reset_timer_masked(void)
-{
- /* Set the hadware timer for 1ms */
- ks8695_write(KS8695_TIMER1, TIMER_COUNT);
- ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
- ks8695_write(KS8695_TIMER_CTRL, 0x2);
- timer_ticks = 0;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer_masked(void)
{
/* Check for timer wrap */
return (get_timer_masked() - base);
}
-void set_timer(ulong t)
-{
- timer_ticks = t;
-}
-
void __udelay(ulong usec)
{
ulong start = get_timer_masked();
/*
* timer without interrupts
*/
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
void __udelay (unsigned long usec)
{
ulong tmo;
/*NOP*/;
}
-void reset_timer_masked(void)
-{
- /* reset time */
- lastdec = READ_TIMER();
- timestamp = 0;
-}
-
ulong get_timer_masked(void)
{
ulong tmr = get_ticks();
# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
CONFIG_SYS_TIMERBASE + CNTL_TIMER);
/* init the timestamp and lastdec value */
- reset_timer_masked();
+ lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
+ (TIMER_CLOCK / CONFIG_SYS_HZ);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
return 0;
}
/*
* timer without interrupts
*/
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay (unsigned long usec)
{
}
}
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
- (TIMER_CLOCK / CONFIG_SYS_HZ);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
ulong get_timer_masked (void)
{
uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
return(readl(&armd1timers->cvwr));
}
-void reset_timer_masked(void)
-{
- /* reset time */
- gd->tbl = read_timer();
- gd->tbu = 0;
-}
-
ulong get_timer_masked(void)
{
ulong now = read_timer();
return gd->tbu;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
base);
}
-void set_timer(ulong t)
-{
- gd->tbu = t;
-}
-
void __udelay(unsigned long usec)
{
ulong delayticks;
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
/* init the gd->tbu and gd->tbl value */
- reset_timer_masked();
+ gd->tbl = read_timer();
+ gd->tbu = 0;
return 0;
}
return(0);
}
-void reset_timer(void)
-{
- gd->timer_reset_value = get_ticks();
-}
-
/*
* Get the current 64 bit timer tick count
*/
#define timestamp gd->tbl
#define lastdec gd->lastinc
-void reset_timer_masked(void)
-{
- /* reset time */
- lastdec = READ_TIMER;
- timestamp = 0;
-}
-
ulong get_timer_masked(void)
{
ulong now = READ_TIMER;
return timestamp;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
void __udelay(unsigned long usec)
{
uint current;
writel(cntmrctrl, CNTMR_CTRL_REG);
/* init the timestamp and lastdec value */
- reset_timer_masked();
+ lastdec = READ_TIMER;
+ timestamp = 0;
return 0;
}
writel(ctrl, &timer->control);
- reset_timer_masked();
+ /* capture current value time */
+ lastdec = readl(&timer->value);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
return 0;
}
return timestamp;
}
-void reset_timer_masked(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
-
- /* capture current value time */
- lastdec = readl(&timer->value);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
ulong get_timer_masked(void)
{
return tick_to_time(get_ticks());
/*NOP*/;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
LIB = $(obj)lib$(SOC).o
-COBJS = generic.o timer.o
-MX27OBJS = reset.o
+COBJS = generic.o timer.o reset.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ /* Clock Control Module */
+ DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+ DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+ DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+ DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+ DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+ DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+ /* Enhanced SDRAM Controller */
+ DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+ DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+ DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+ /* Multi-Layer AHB Crossbar Switch */
+ DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+ DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+ DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+ DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+ DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+ DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+ DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+ DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+ DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+ DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+ DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+ DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+ DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+ DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+ DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+ /* AHB <-> IP-Bus Interface */
+ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+ DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+
+ return 0;
+}
return 0;
}
-void reset_timer_masked(void)
-{
- struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
- /* reset time */
- /* capture current incrementer value time */
- lastinc = readl(&gpt->counter);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
unsigned long long get_ticks (void)
{
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = time_to_tick(t);
-}
-
/* delay x useconds AND preserve advance timstamp value */
void __udelay (unsigned long usec)
{
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ ulong tbclk;
+
+ tbclk = CONFIG_MX25_CLK32;
+ return tbclk;
+}
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
+ DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
+ DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
+ DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
+
+ DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
+ DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
+ DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
+ DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
+ DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+ DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+ DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+
+ DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+ DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+ DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
+ DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
+ return 0;
+}
}
#ifdef CONFIG_MXC_UART
-void mx27_uart_init_pins(void)
+void mx27_uart1_init_pins(void)
{
int i;
unsigned int mode[] = {
return 0;
}
-void reset_timer_masked(void)
-{
- struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
- /* reset time */
- /* capture current incrementer value time */
- lastinc = readl(®s->gpt_tcn);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
unsigned long long get_ticks (void)
{
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = time_to_tick(t);
-}
-
/* delay x useconds AND preserve advance timstamp value */
void __udelay (unsigned long usec)
{
/* Configure a free-running, auto-wrap counter with no prescaler */
int timer_init(void)
{
+ ulong val;
+
writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
CONFIG_SYS_TIMERBASE + MTU_CR(0));
- reset_timer();
- return 0;
-}
-/* Restart counting from 0 */
-void reset_timer(void)
-{
- ulong val;
+ /* Reset the timer */
writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
/*
* The load-register isn't really immediate: it changes on clock
val = READ_TIMER();
while (READ_TIMER() == val)
;
+
+ return 0;
}
/* Return how many HZ passed since "base" */
/*
* timer without interrupts
*/
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay (unsigned long usec)
{
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (volatile long *) orion5x_sdram_bar(0),
+ (long *) orion5x_sdram_bar(0),
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
gd->bd->bi_dram[i].size = get_ram_size(
- (volatile long *) (gd->bd->bi_dram[i].start),
+ (long *) (gd->bd->bi_dram[i].start),
CONFIG_MAX_RAM_BANK_SIZE);
}
}
#define timestamp gd->tbl
#define lastdec gd->lastinc
-void reset_timer_masked(void)
-{
- /* reset time */
- lastdec = read_timer();
- timestamp = 0;
-}
-
ulong get_timer_masked(void)
{
ulong now = read_timer();
return timestamp;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
static inline ulong uboot_cntr_val(void)
{
return readl(CNTMR_VAL_REG(UBOOT_CNTR));
void timer_init_r(void)
{
/* init the timestamp and lastdec value */
- reset_timer_masked();
+ lastdec = read_timer();
+ timestamp = 0;
}
return val;
}
-void reset_timer_masked(void)
-{
- /* reset time */
- gd->tbl = read_timer();
- gd->tbu = 0;
-}
-
ulong get_timer_masked(void)
{
ulong now = read_timer();
return gd->tbu;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
base);
}
-void set_timer(ulong t)
-{
- gd->tbu = t;
-}
-
void __udelay(unsigned long usec)
{
ulong delayticks;
/* Enable timer 0 */
writel(0x1, &panthtimers->cer);
/* init the gd->tbu and gd->tbl value */
- reset_timer_masked();
+ gd->tbl = read_timer();
+ gd->tbu = 0;
return 0;
}
/* auto reload, start timer */
writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
- reset_timer_masked();
+ /* Reset the timer */
+ lastdec = READ_TIMER();
+ timestamp = 0;
return 0;
}
/*
* timer without interrupts
*/
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return (get_timer_masked() / GPT_RESOLUTION) - base;
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
void __udelay(unsigned long usec)
{
ulong tmo;
;
}
-void reset_timer_masked(void)
-{
- /* reset time */
- lastdec = READ_TIMER();
- timestamp = 0;
-}
-
ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
.globl _start
_start:
b reset
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
/* No exception handlers in preloader */
ldr pc, _hang
ldr pc, _hang
_fiq:
.word fiq
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
.balignl 16,0xdeadbeef
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
/*
* exception handlers
*/
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
ldr sp, _TEXT_BASE /* switch to abort stack */
1:
bl 1b /* hang and never return */
-#else /* !CONFIG_PRELOADER */
+#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
bl do_fiq
#endif
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
/*
* timer without interrupts
*/
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay (unsigned long usec)
{
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
sinclude $(obj).depend
+lowlevel_init.o : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
--- /dev/null
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
+ DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
+ DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+ DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+ DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+ DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
+ DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
+ DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+ DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+ DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+ DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
+ DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
+ DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
+ DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
+ DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+ DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+ DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+ DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
+ DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
+ DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
+ DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+ DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+ DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+ DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+ DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+ DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+ DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+ DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+ DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+ DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+ DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+ DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+ DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+ DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
+#if defined(CONFIG_MX53)
+ DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+#endif
+
+ /* DPLL */
+ DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
+ DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
+ DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
+ DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
+ DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
+ DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
+ DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
+ DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
+
+ return 0;
+}
orr r0, r0, #(1 << 23) /* disable write allocate combine */
orr r0, r0, #(1 << 22) /* disable write allocate */
- cmp r3, #0x10 /* r3 contains the silicon rev */
+#if defined(CONFIG_MX51)
+ ldr r1, =0x0
+ ldr r3, [r1, #ROM_SI_REV]
+ cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
orrls r0, r0, #(1 << 25)
+#endif
mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */
int timer_init(void)
{
int i;
+ ulong val;
/* setup GP Timer 1 */
__raw_writel(GPTCR_SWR, &cur_gpt->control);
/* Freerun Mode, PERCLK1 input */
i = __raw_readl(&cur_gpt->control);
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
- reset_timer_masked();
- return 0;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-void reset_timer_masked(void)
-{
- ulong val = __raw_readl(&cur_gpt->counter);
+ val = __raw_readl(&cur_gpt->counter);
lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
+
+ return 0;
}
ulong get_timer_masked(void)
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay(unsigned long usec)
{
writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
&timer_base->tclr);
- reset_timer_masked(); /* init the timestamp and lastinc value */
+ /* reset time, capture current incrementer value time */
+ gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+ gd->tbl = 0; /* start "advancing" time stamp from 0 */
return 0;
}
/*
* timer without interrupts
*/
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- gd->tbl = t;
-}
-
/* delay x useconds */
void __udelay(unsigned long usec)
{
}
}
-void reset_timer_masked(void)
-{
- /* reset time, capture current incrementer value time */
- gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
- gd->tbl = 0; /* start "advancing" time stamp from 0 */
-}
-
ulong get_timer_masked(void)
{
/* current tick value */
/*
* timer without interrupts
*/
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
unsigned long get_timer(unsigned long base)
{
return get_timer_masked() - base;
}
-void set_timer(unsigned long t)
-{
- gd->tbl = t;
-}
-
/* delay x useconds */
void __udelay(unsigned long usec)
{
mov sp, r4
adr r0, _start
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
cmp r0, r6
beq clear_bss /* skip relocation */
#endif
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
add r0, r0, #4
cmp r0, r1
bne clbss_l
-#endif /* #ifndef CONFIG_PRELOADER */
+#endif /* #ifndef CONFIG_SPL_BUILD */
/*
* We are done. Do not return, instead branch to second part of board
_dynsym_start_ofs:
.word __dynsym_start - _start
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
*
* CPU_init_critical registers
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
+#endif
/*
*************************************************************************
*
#define TIMER_LOAD_VAL 0xffffffff
/* timer without interrupts */
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- gd->tbl = t;
-}
-
/* delay x useconds */
void __udelay(unsigned long usec)
{
}
}
-void reset_timer_masked(void)
-{
- /* reset time, capture current incrementer value time */
- gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ);
- gd->tbl = 0; /* start "advancing" time stamp from 0 */
-}
-
ulong get_timer_masked(void)
{
ulong now;
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- gd->tbl = t;
-}
-
/*
* Emulation of Power architecture long long timebase.
*
&dispatchQInfo[qId].statusMask);
- /* Set the interupt source is this queue is in the range 0-31 */
+ /* Set the interrupt source is this queue is in the range 0-31 */
if (qId < IX_QMGR_MIN_QUEUPP_QID)
{
ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
BOOL portInitialized;
UINT32 npeId; /**< NpeId for this port */
IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
- IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
+ IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
} IxEthAccPortDataInfo;
extern IxEthAccPortDataInfo ixEthAccPortData[];
*/
typedef struct
{
- UINT32 rxBitField; /**< Recieved bit field */
+ UINT32 rxBitField; /**< Received bit field */
UINT32 atmCellHeader; /**< ATM Cell Header */
UINT32 rsvdWord0; /**< Reserved field */
UINT16 currMbufLen; /**< Mbuf Length */
* @brief Queue interrupt source select.
*
* This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
+ * an interrupt being fired by the AQM. Interrupt source is configurable for
* queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
* NE(Nearly Empty) status flag.
*
*
* @def IX_ETH_ACC_RX_FRAME_ETH_Q
*
-* @brief Eth0/Eth1 NPE Frame Recieve Q.
+* @brief Eth0/Eth1 NPE Frame Receive Q.
*
* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
*
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
gd->timestamp = 0;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer_masked(void)
{
return tick_to_time(get_ticks());
return get_timer_masked() - base;
}
-void set_timer(ulong t)
-{
- gd->timestamp = time_to_tick(t);
-}
-
/* delay x useconds AND preserve advance timestamp value */
void __udelay(unsigned long usec)
{
msr cpsr,r0
#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
-#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
+#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
#define pCLKSET 0x80000420 /* clock divisor register */
/* disable watchdog, set watchdog control register to
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
/*
* timer without interrupts
*/
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return (get_timer_masked() - base);
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
void __udelay (unsigned long usec)
{
ulong tmo,tmp;
.globl _start
_start: b reset
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
.balignl 16,0xdeadbeef
.word 0x0badc0de
#endif /* CONFIG_USE_IRQ */
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
blo copy_loop
ldmfd sp!, {r0-r12}
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
-#endif /* #ifndef CONFIG_PRELOADER */
+#endif /* #ifndef CONFIG_SPL_BUILD */
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
add r0, r0, #4
cmp r0, r1
bne clbss_l
-#endif /* #ifndef CONFIG_PRELOADER */
+#endif /* #ifndef CONFIG_SPL_BUILD */
/*
* We are done. Do not return, instead branch to second part of board
_dynsym_start_ofs:
.word __dynsym_start - _start
-#else /* CONFIG_PRELOADER */
+#else /* CONFIG_SPL_BUILD */
/****************************************************************************/
/* */
/* Start OneNAND IPL */
ldr pc, =start_oneboot
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/****************************************************************************/
/* */
/* Interrupt handling */
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
-#endif /* CONFIG_PRELOADER
+#endif /* CONFIG_SPL_BUILD
/****************************************************************************/
/* */
/****************************************************************************/
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
ldr sp, _TEXT_BASE /* use 32 words abort stack */
get_bad_stack
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
b reset_endless
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
.section .mmudata, "a"
.align 14
.globl mmu_table
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
int timer_init (void)
{
- reset_timer();
+ writel(0, OSCR);
return 0;
}
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- /* nop */
-}
-
void __udelay (unsigned long usec)
{
udelay_masked (usec);
}
-
-void reset_timer_masked (void)
-{
- writel(0, OSCR);
-}
-
ulong get_timer_masked (void)
{
return tick_to_time(get_ticks());
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
/*
* timer without interrupts
*/
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
void __udelay (unsigned long usec)
{
ulong tmo;
/*NOP*/;
}
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER;
- timestamp = 0;
-}
-
ulong get_timer_masked (void)
{
ulong now = READ_TIMER;
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
*/
-/* Interupt-Controller base address */
+/* Interrupt-Controller base address */
IC_BASE: .word 0x90050000
#define ICMR 0x04
return 0;
}
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked ();
}
-void set_timer (ulong t)
-{
- /* nop */
-}
-
void __udelay (unsigned long usec)
{
udelay_masked (usec);
}
-
-void reset_timer_masked (void)
-{
- OSCR = 0;
-}
-
ulong get_timer_masked (void)
{
return OSCR;
/* GPIO registers */
struct gpio_regs {
- u32 dr; /* data */
- u32 dir; /* direction */
+ u32 gpio_dr; /* data */
+ u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 mac_addr[6];
};
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+ u32 mpr0;
+ u32 pad00[3];
+ u32 sgpcr0;
+ u32 pad01[59];
+ u32 mpr1;
+ u32 pad02[3];
+ u32 sgpcr1;
+ u32 pad03[59];
+ u32 mpr2;
+ u32 pad04[3];
+ u32 sgpcr2;
+ u32 pad05[59];
+ u32 mpr3;
+ u32 pad06[3];
+ u32 sgpcr3;
+ u32 pad07[59];
+ u32 mpr4;
+ u32 pad08[3];
+ u32 sgpcr4;
+ u32 pad09[251];
+ u32 mgpcr0;
+ u32 pad10[63];
+ u32 mgpcr1;
+ u32 pad11[63];
+ u32 mgpcr2;
+ u32 pad12[63];
+ u32 mgpcr3;
+ u32 pad13[63];
+ u32 mgpcr4;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+ u32 mpr_0_7;
+ u32 mpr_8_15;
+};
+
#endif
/* AIPS 1 */
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
+/* Names used in GPIO driver */
+#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
+#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
+#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
+#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
+
#endif /* _IMX_REGS_H */
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Common asm macros for imx25
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_MACRO_H__
+#define __ASM_ARM_ARCH_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+.macro init_aips
+ write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
+ write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
+ write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
+ write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
+.endm
+
+.macro init_max
+ write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
+
+ write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
+
+ write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_ARCH_MACRO_H__ */
+++ /dev/null
-#define AIPI1_PSR0 0x10000000
-#define AIPI1_PSR1 0x10000004
-#define AIPI2_PSR0 0x10020000
-#define AIPI2_PSR1 0x10020004
-#define CSCR 0x10027000
-#define MPCTL0 0x10027004
-#define SPCTL0 0x1002700c
-#define PCDR0 0x10027018
-#define PCDR1 0x1002701c
-#define PCCR0 0x10027020
-#define PCCR1 0x10027024
-#define ESDCTL0_ROF 0x00
-#define ESDCFG0_ROF 0x04
-#define ESDCTL1_ROF 0x08
-#define ESDCFG1_ROF 0x0C
-#define ESDMISC_ROF 0x10
extern void imx_gpio_mode (int gpio_mode);
#ifdef CONFIG_MXC_UART
-extern void mx27_uart_init_pins(void);
+extern void mx27_uart1_init_pins(void);
#endif /* CONFIG_MXC_UART */
#ifdef CONFIG_FEC_MXC
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
-extern u32 mx31_get_ipg_clk(void);
-#define imx_get_uartclk mx31_get_ipg_clk
+enum mxc_clock {
+ MXC_ARM_CLK,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
+ MXC_UART_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+extern u32 imx_get_uartclk();
extern void mx31_gpio_mux(unsigned long mode);
extern void mx31_set_pad(enum iomux_pins pin, u32 config);
#define IRAM_SIZE (16 * 1024)
#define MX31_AIPS1_BASE_ADDR 0x43f00000
-#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
/* USB portsc */
/* values for portsc field */
+++ /dev/null
-/*
- * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
- *
- * These should be auto-generated
- */
-/* CCM */
-#define CLKCTL_CCR 0x00
-#define CLKCTL_CCDR 0x04
-#define CLKCTL_CSR 0x08
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR 0x14
-#define CLKCTL_CBCMR 0x18
-#define CLKCTL_CSCMR1 0x1C
-#define CLKCTL_CSCMR2 0x20
-#define CLKCTL_CSCDR1 0x24
-#define CLKCTL_CS1CDR 0x28
-#define CLKCTL_CS2CDR 0x2C
-#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCCDR 0x34
-#define CLKCTL_CSCDR2 0x38
-#define CLKCTL_CSCDR3 0x3C
-#define CLKCTL_CSCDR4 0x40
-#define CLKCTL_CWDR 0x44
-#define CLKCTL_CDHIPR 0x48
-#define CLKCTL_CDCR 0x4C
-#define CLKCTL_CTOR 0x50
-#define CLKCTL_CLPCR 0x54
-#define CLKCTL_CISR 0x58
-#define CLKCTL_CIMR 0x5C
-#define CLKCTL_CCOSR 0x60
-#define CLKCTL_CGPR 0x64
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6C
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7C
-#define CLKCTL_CCGR6 0x80
-#if defined(CONFIG_MX53)
-#define CLKCTL_CCGR7 0x84
-#define CLKCTL_CMEOR 0x88
-#elif defined(CONFIG_MX51)
-#define CLKCTL_CMEOR 0x84
-#endif
-
-/* DPLL */
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
u32 ccgr4;
u32 ccgr5;
u32 ccgr6;
+#if defined(CONFIG_MX53)
+ u32 ccgr7;
+#endif
u32 cmeor;
};
+/* DPLL registers */
+struct dpll {
+ u32 dp_ctl;
+ u32 dp_config;
+ u32 dp_op;
+ u32 dp_mfd;
+ u32 dp_mfn;
+ u32 dp_mfn_minus;
+ u32 dp_mfn_plus;
+ u32 dp_hfs_op;
+ u32 dp_hfs_mfd;
+ u32 dp_hfs_mfn;
+ u32 dp_mfn_togc;
+ u32 dp_destat;
+};
/* WEIM registers */
struct weim {
u32 cs0gcr1;
#define CPCON (1 << 8)
+#define SWR_SDMMC4_RST (1 << 15)
+#define CLK_ENB_SDMMC4 (1 << 15)
+#define SWR_SDMMC3_RST (1 << 5)
+#define CLK_ENB_SDMMC3 (1 << 5)
+
#endif /* CLK_RST_H */
#define Z_GMC (1 << 29)
#define Z_IRRX (1 << 20)
#define Z_IRTX (1 << 19)
+#define Z_GMA (1 << 28)
+#define Z_GME (1 << 0)
+#define Z_ATB (1 << 1)
+#define Z_SDB (1 << 15)
+#define Z_SDC (1 << 1)
+#define Z_SDD (1 << 2)
#endif /* PINMUX_H */
return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
}
+static inline int __ilog2(unsigned int x)
+{
+ return generic_fls(x) - 1;
+}
+
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
/*
- * The following data structure is placed in some memory wich is
+ * The following data structure is placed in some memory which is
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
* some locked parts of the data cache) to allow for a minimum set of
* global variables during system initialization (until we have set
void setup_serial_tag (struct tag **params);
void setup_revision_tag (struct tag **params);
-/* ------------------------------------------------------------ */
-/* Here is a list of some prototypes which are incompatible to */
-/* the U-Boot implementation */
-/* To be fixed! */
-/* ------------------------------------------------------------ */
-/* common/cmd_nvedit.c */
-int setenv (char *, char *);
-
/* cpu/.../interrupt.c */
int arch_interrupt_init (void);
void reset_timer_masked (void);
ulong get_timer_masked (void);
void udelay_masked (unsigned long usec);
-/* cpu/.../timer.c */
-int timer_init (void);
-
#endif /* _U_BOOT_ARM_H_ */
LIB = $(obj)lib$(ARCH).o
LIBGCC = $(obj)libgcc.o
+ifndef CONFIG_SPL_BUILD
GLSOBJS += _ashldi3.o
GLSOBJS += _ashrdi3.o
GLSOBJS += _divsi3.o
COBJS-y += reset.o
SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
+endif
SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
$(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <net.h>
#include <serial.h>
extern void dataflash_print_info(void);
#endif
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
-const char version_string[] =
- U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
-
#ifdef CONFIG_DRIVER_RTL8019
extern void rtl8019_get_enetaddr (uchar * addr);
#endif
gd->mon_len = _bss_end_ofs;
+#ifdef CONFIG_MACH_TYPE
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
debug ("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* reserve memory for malloc() arena
*/
return ((unsigned long long)hi_now << 32) | lo;
}
-void reset_timer(void)
-{
- sysreg_write(COUNT, 0);
- cpu_sync_pipeline(); /* process any pending interrupts */
- timer_overflow = 0;
-}
-
unsigned long get_timer(unsigned long base)
{
u64 now = get_ticks();
return (unsigned long)(now >> 32) - base;
}
-void set_timer(unsigned long t)
-{
- unsigned long long ticks = t;
- unsigned long lo, hi, hi_new;
-
- ticks = (ticks * get_tbclk()) / CONFIG_SYS_HZ;
- hi = ticks >> 32;
- lo = ticks & 0xffffffffUL;
-
- do {
- timer_overflow = hi;
- sysreg_write(COUNT, lo);
- hi_new = timer_overflow;
- } while (hi_new != hi);
-}
-
/*
* For short delays only. It will overflow after a few seconds.
*/
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <net.h>
#include <miiphy.h>
#endif
-#include <asm/initcalls.h>
#include <asm/sections.h>
#include <asm/arch/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
-const char version_string[] =
- U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME") " CONFIG_IDENT_STRING;
-
unsigned long monitor_flash_len;
/* Weak aliases for optional board functions */
PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-ALL += $(obj)u-boot.ldr
+ALL-y += $(obj)u-boot.ldr
endif
ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o
return (milisec - base);
}
-
-void reset_timer(void)
-{
- timer_init();
-}
#include <malloc.h>
#include <mmc.h>
#include <net.h>
-#include <timestamp.h>
#include <status_led.h>
#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
-const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")";
-
__attribute__((always_inline))
static inline void serial_early_puts(const char *s)
{
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
/*------------------------------------------------------------------------------*/
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
}
-void reset_timer(void)
-{
- timestamp = 0;
-}
-
ulong get_timer(ulong base)
{
return (timestamp - base);
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
#endif /* CONFIG_SLTTMR */
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
udelay (20);
- set_timer (0);
-
/* Insert function pointers now that we have relocated the code */
/* Initialize from environment */
DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
}
-void reset_timer(void)
-{
- timestamp = 0;
-}
-
ulong get_timer(ulong base)
{
return (timestamp - base);
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
#endif /* CONFIG_MCFTMR */
#if defined(CONFIG_MCFPIT)
timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
}
-void set_timer(ulong t)
-{
- volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
-
- timestamp = 0;
- timerp->pmr = lastinc = 0;
-}
-
ulong get_timer(ulong base)
{
unsigned short now, diff;
void wait_ticks(unsigned long ticks)
{
- set_timer(0);
- while (get_timer(0) < ticks) ;
+ u32 start = get_timer(0);
+ while (get_timer(start) < ticks) ;
}
#endif /* CONFIG_MCFPIT */
volatile int timestamp = 0;
-void reset_timer (void)
-{
- timestamp = 0;
-}
-
#ifdef CONFIG_SYS_TIMER_0
ulong get_timer (ulong base)
{
}
#endif
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
#ifdef CONFIG_SYS_INTC_0
#ifdef CONFIG_SYS_TIMER_0
microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
tmr->control = TIMER_INTERRUPT | TIMER_RESET;
tmr->control =
TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
- reset_timer ();
+ timestamp = 0;
install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
return 0;
}
#include <common.h>
#include <command.h>
#include <malloc.h>
-#include <timestamp.h>
#include <version.h>
#include <watchdog.h>
#include <stdio_dev.h>
DECLARE_GLOBAL_DATA_PTR;
-const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")";
-
#ifdef CONFIG_SYS_GPIO_0
extern int gpio_init (void);
#endif
#include <asm/regdef.h>
#include <asm/mipsregs.h>
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
_start:
RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) # software reboot
-#ifdef CONFIG_INCA_IP
- .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
- .word 0x00000000 # booting phase of the flash
+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+ /*
+ * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
+ * access external NOR flashes. If the board boots from NOR flash the
+ * internal BootROM does a blind read at address 0xB0000010 to read the
+ * initial configuration for that EBU in order to access the flash
+ * device with correct parameters. This config option is board-specific.
+ */
+ .word CONFIG_SYS_XWAY_EBU_BOOTCFG
+ .word 0x00000000
#else
RVECENT(romReserved,2)
#endif
nop
/* ... and enable them */
- li t0, CONF_CM_CACHABLE_NONCOHERENT
+ li t0, CONFIG_SYS_MIPS_CACHE_MODE
mtc0 t0, CP0_CONFIG
#endif
return 0;
}
-void reset_timer(void)
-{
- timestamp = 0;
- write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-}
-
ulong get_timer(ulong base)
{
unsigned int count;
return (timestamp - base);
}
-void set_timer(ulong t)
-{
- timestamp = t;
- write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-}
-
void __udelay(unsigned long usec)
{
unsigned int tmo;
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <net.h>
#include <environment.h>
ulong monitor_flash_len;
-const char version_string[] =
- U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
-
static char *failed = "*** failed ***\n";
/*
return (timestamp - base);
}
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
-
/* The board must handle this interrupt if a timer is not
* provided.
*/
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include <version.h>
/*************************************************************************
bge r4, r0, dly_clks
ret
-
-#if !defined(CONFIG_IDENT_STRING)
-#define CONFIG_IDENT_STRING ""
-#endif
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
#include <asm-offsets.h>
#include <config.h>
#include <74xx_7xx.h>
-#include <timestamp.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <galileo/gt64260R.h>
#endif
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
*/
#include <common.h>
+#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <serial.h>
serial_puts_dev(port, s); \
}
-#define INIT_PSC_SERIAL_STRUCTURE(port, name, bus) { \
+#define INIT_PSC_SERIAL_STRUCTURE(port, name) { \
name, \
- bus, \
serial##port##_init, \
serial##port##_uninit, \
serial##port##_setbrg, \
#if defined(CONFIG_SYS_PSC1)
DECLARE_PSC_SERIAL_FUNCTIONS(1);
struct serial_device serial1_device =
-INIT_PSC_SERIAL_STRUCTURE(1, "psc1", "UART1");
+INIT_PSC_SERIAL_STRUCTURE(1, "psc1");
#endif
#if defined(CONFIG_SYS_PSC3)
DECLARE_PSC_SERIAL_FUNCTIONS(3);
struct serial_device serial3_device =
-INIT_PSC_SERIAL_STRUCTURE(3, "psc3", "UART3");
+INIT_PSC_SERIAL_STRUCTURE(3, "psc3");
#endif
#if defined(CONFIG_SYS_PSC4)
DECLARE_PSC_SERIAL_FUNCTIONS(4);
struct serial_device serial4_device =
-INIT_PSC_SERIAL_STRUCTURE(4, "psc4", "UART4");
+INIT_PSC_SERIAL_STRUCTURE(4, "psc4");
#endif
#if defined(CONFIG_SYS_PSC6)
DECLARE_PSC_SERIAL_FUNCTIONS(6);
struct serial_device serial6_device =
-INIT_PSC_SERIAL_STRUCTURE(6, "psc6", "UART6");
+INIT_PSC_SERIAL_STRUCTURE(6, "psc6");
#endif
+__weak struct serial_device *default_serial_console(void)
+{
+#if (CONFIG_PSC_CONSOLE == 3)
+ return &serial3_device;
+#elif (CONFIG_PSC_CONSOLE == 6)
+ return &serial6_device;
+#else
+#error "invalid CONFIG_PSC_CONSOLE"
+#endif
+}
+
#else
void serial_setbrg(void)
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING "MPC512X"
+#endif
#include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING "MPC512X"
-#endif
-
/*
* Floating Point enable, Machine Check and Recoverable Interr.
*/
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii " ", CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Vector Table
#include <asm-offsets.h>
#include <config.h>
#include <mpc5xx.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_5xx 1 /* needed for Linux kernel header files */
#include <asm/processor.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't have a MMU.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
*/
#include <common.h>
+#include <linux/compiler.h>
#include <mpc5xxx.h>
#if defined (CONFIG_SERIAL_MULTI)
struct serial_device serial0_device =
{
"serial0",
- "UART0",
serial0_init,
NULL,
serial0_setbrg,
serial0_puts,
};
+__weak struct serial_device *default_serial_console(void)
+{
+ return &serial0_device;
+}
+
struct serial_device serial1_device =
{
"serial1",
- "UART1",
serial1_init,
NULL,
serial1_setbrg,
#include <asm-offsets.h>
#include <config.h>
#include <mpc5xxx.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Exception vectors
#include <asm-offsets.h>
#include <config.h>
#include <mpc8220.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Exception vectors
#include <asm-offsets.h>
#include <config.h>
#include <mpc824x.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <asm-offsets.h>
#include <config.h>
#include <mpc8260.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_8260 1 /* needed for Linux kernel header files */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Hard Reset Configuration Word (HRCW) table
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
-#include <timestamp.h>
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING "MPC83XX"
+#endif
#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING "MPC83XX"
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii " ", CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 2
COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o
-COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
+COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
COBJS-$(CONFIG_P1025) += p1021_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
{
sys_info_t sysinfo;
uint pvr, svr;
- uint fam;
uint ver;
uint major, minor;
struct cpu_type *cpu;
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
- fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
- if (PVR_FAM(PVR_85xx)) {
- switch(PVR_MEM(pvr)) {
- case 0x1:
- case 0x2:
- puts("E500");
- break;
- case 0x3:
- puts("E500MC");
- break;
- case 0x4:
- puts("E5500");
- break;
- default:
- puts("Unknown");
- break;
- }
- } else {
+ switch(ver) {
+ case PVR_VER_E500_V1:
+ case PVR_VER_E500_V2:
+ puts("E500");
+ break;
+ case PVR_VER_E500MC:
+ puts("E500MC");
+ break;
+ case PVR_VER_E5500:
+ puts("E5500");
+ break;
+ default:
puts("Unknown");
+ break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
lbc_sdram_init();
#endif
- puts("DDR: ");
+ debug("DDR: ");
return dram_size;
}
#endif /* CONFIG_SYS_RAMBOOT */
unsigned int
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
+void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
+
static void dump_spd_ddr_reg(void)
{
int i, j, k, m;
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
- phys_addr_t rpn = 0;
int ddr_esel;
- ptr = vstart;
-
- while (ptr < (vstart + size)) {
- ddr_esel = find_tlb_idx((void *)ptr, 1);
- if (ddr_esel != -1) {
- read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
- disable_tlb(ddr_esel);
- }
- ptr += TSIZE_TO_BYTES(tsize);
- }
+ clear_ddr_tlbs_phys(p_addr, size>>20);
/* Setup new tlb to cover the physical address */
setup_ddr_tlbs_phys(p_addr, size>>20);
void cpu_init_f (void)
{
extern void m8560_cpm_reset (void);
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
/* Invalidate the CPC before DDR gets enabled */
invalidate_cpc();
+
+ #ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* set DCSRCR so that DCSR space is 1G */
+ setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
+ in_be32(&gur->dcsrcr);
+#endif
+
}
/* Implement a dummy function for those platforms w/o SERDES */
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+ if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+ (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+ puts("N/A\n");
+ goto skip_l2;
+ }
+
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */
;
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
}
+
+skip_l2:
#else
puts("disabled\n");
#endif
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
+#include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */
DECLARE_GLOBAL_DATA_PTR;
u32 *ph;
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
u32 size, line_size, num_ways, num_sets;
+ int has_l2 = 1;
+
+ /* P2040/P2040E has no L2, so dont set any L2 props */
+ if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+ (SVR_SOC_VER(get_svr()) == SVR_P2040_E))
+ has_l2 = 0;
size = (l2cfg0 & 0x3fff) * 64 * 1024;
num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
goto next;
}
+ if (has_l2) {
#ifdef CONFIG_SYS_CACHE_STASHING
- {
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
if (reg)
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
- }
#endif
- fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
- fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
- fdt_setprop_cell(blob, l2_off, "cache-size", size);
- fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
- fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
+ fdt_setprop_cell(blob, l2_off, "cache-block-size",
+ line_size);
+ fdt_setprop_cell(blob, l2_off, "cache-size", size);
+ fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
+ fdt_setprop_cell(blob, l2_off, "cache-level", 2);
+ fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ }
if (l3_off < 0) {
ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
}
#endif
+/**
+ * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
+ *
+ * The binding for an Fman firmware node is documented in
+ * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains
+ * the actual Fman firmware binary data. The operating system is expected to
+ * be able to parse the binary data to determine any attributes it needs.
+ */
+#ifdef CONFIG_SYS_DPAA_FMAN
+void fdt_fixup_fman_firmware(void *blob)
+{
+ int rc, fmnode, fwnode = -1;
+ uint32_t phandle;
+ struct qe_firmware *fmanfw;
+ const struct qe_header *hdr;
+ unsigned int length;
+ uint32_t crc;
+ const char *p;
+
+ /* The first Fman we find will contain the actual firmware. */
+ fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
+ if (fmnode < 0)
+ /* Exit silently if there are no Fman devices */
+ return;
+
+ /* If we already have a firmware node, then also exit silently. */
+ if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
+ return;
+
+ /* If the environment variable is not set, then exit silently */
+ p = getenv("fman_ucode");
+ if (!p)
+ return;
+
+ fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0);
+ if (!fmanfw)
+ return;
+
+ hdr = &fmanfw->header;
+ length = be32_to_cpu(hdr->length);
+
+ /* Verify the firmware. */
+ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+ (hdr->magic[2] != 'F')) {
+ printf("Data at %p is not an Fman firmware\n", fmanfw);
+ return;
+ }
+
+ if (length > CONFIG_SYS_FMAN_FW_LENGTH) {
+ printf("Fman firmware at %p is too large (size=%u)\n",
+ fmanfw, length);
+ return;
+ }
+
+ length -= sizeof(u32); /* Subtract the size of the CRC */
+ crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length));
+ if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
+ printf("Fman firmware at %p has invalid CRC\n", fmanfw);
+ return;
+ }
+
+ /* Increase the size of the fdt to make room for the node. */
+ rc = fdt_increase_size(blob, fmanfw->header.length);
+ if (rc < 0) {
+ printf("Unable to make room for Fman firmware: %s\n",
+ fdt_strerror(rc));
+ return;
+ }
+
+ /* Create the firmware node. */
+ fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
+ if (fwnode < 0) {
+ char s[64];
+ fdt_get_path(blob, fmnode, s, sizeof(s));
+ printf("Could not add firmware node to %s: %s\n", s,
+ fdt_strerror(fwnode));
+ return;
+ }
+ rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware");
+ if (rc < 0) {
+ char s[64];
+ fdt_get_path(blob, fwnode, s, sizeof(s));
+ printf("Could not add compatible property to node %s: %s\n", s,
+ fdt_strerror(rc));
+ return;
+ }
+ phandle = fdt_alloc_phandle(blob);
+ rc = fdt_setprop_cell(blob, fwnode, "linux,phandle", phandle);
+ if (rc < 0) {
+ char s[64];
+ fdt_get_path(blob, fwnode, s, sizeof(s));
+ printf("Could not add phandle property to node %s: %s\n", s,
+ fdt_strerror(rc));
+ return;
+ }
+ rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length);
+ if (rc < 0) {
+ char s[64];
+ fdt_get_path(blob, fwnode, s, sizeof(s));
+ printf("Could not add firmware property to node %s: %s\n", s,
+ fdt_strerror(rc));
+ return;
+ }
+
+ /* Find all other Fman nodes and point them to the firmware node. */
+ while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) {
+ rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle);
+ if (rc < 0) {
+ char s[64];
+ fdt_get_path(blob, fmnode, s, sizeof(s));
+ printf("Could not add pointer property to node %s: %s\n",
+ s, fdt_strerror(rc));
+ return;
+ }
+ }
+}
+#else
+#define fdt_fixup_fman_firmware(x)
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
ft_fixup_qe_snum(blob);
#endif
+ fdt_fixup_fman_firmware(blob);
+
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
*/
do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
"timer-frequency", gd->bus_clk/2, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
+ "clock_freq", gd->bus_clk, 1);
+}
+
+/*
+ * For some CCSR devices, we only have the virtual address, not the physical
+ * address. This is because we map CCSR as a whole, so we typically don't need
+ * a macro for the physical address of any device within CCSR. In this case,
+ * we calculate the physical address of that device using it's the difference
+ * between the virtual address of the device and the virtual address of the
+ * beginning of CCSR.
+ */
+#define CCSR_VIRT_TO_PHYS(x) \
+ (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+
+/*
+ * Verify the device tree
+ *
+ * This function compares several CONFIG_xxx macros that contain physical
+ * addresses with the corresponding nodes in the device tree, to see if
+ * the physical addresses are all correct. For example, if
+ * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
+ * of the first UART. We convert this to a physical address and compare
+ * that with the physical address of the first ns16550-compatible node
+ * in the device tree. If they don't match, then we display a warning.
+ *
+ * Returns 1 on success, 0 on failure
+ */
+int ft_verify_fdt(void *fdt)
+{
+ uint64_t ccsr = 0;
+ int aliases;
+ int off;
+
+ /* First check the CCSR base address */
+ off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
+ if (off > 0)
+ ccsr = fdt_get_base_address(fdt, off);
+
+ if (!ccsr) {
+ printf("Warning: could not determine base CCSR address in "
+ "device tree\n");
+ /* No point in checking anything else */
+ return 0;
+ }
+
+ if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) {
+ printf("Warning: U-Boot configured CCSR at address %llx,\n"
+ "but the device tree has it at %llx\n",
+ (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr);
+ /* No point in checking anything else */
+ return 0;
+ }
+
+ /*
+ * Get the 'aliases' node. If there isn't one, then there's nothing
+ * left to do.
+ */
+ aliases = fdt_path_offset(fdt, "/aliases");
+ if (aliases > 0) {
+#ifdef CONFIG_SYS_NS16550_COM1
+ if (!fdt_verify_alias_address(fdt, aliases, "serial0",
+ CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
+ return 0;
+#endif
+
+#ifdef CONFIG_SYS_NS16550_COM2
+ if (!fdt_verify_alias_address(fdt, aliases, "serial1",
+ CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
+ return 0;
+#endif
+ }
+
+ return 1;
}
PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
SATA2, NONE, NONE, NONE, NONE, },
[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
- PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
- NONE, NONE, NONE, NONE, NONE, NONE, },
+ PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
PCIE3, NONE, NONE, NONE, NONE, },
SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
NONE, NONE, NONE, },
[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
- NONE, NONE, NONE, NONE, NONE, },
+ SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, NONE, NONE, NONE, NONE, },
[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
{
+ enum srds_prtcl prtcl;
+ u32 svr = get_svr();
+ u32 ver = SVR_SOC_VER(svr);
+
if (!serdes_lane_enabled(lane))
return NONE;
- return serdes_cfg_tbl[cfg][lane];
+ prtcl = serdes_cfg_tbl[cfg][lane];
+
+ /* P2040[e] does not support XAUI */
+ if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+ prtcl = NONE;
+
+ return prtcl;
}
int is_serdes_prtcl_valid(u32 prtcl)
{
int i;
+ u32 svr = get_svr();
+ u32 ver = SVR_SOC_VER(svr);
if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
return 0;
+ /* P2040[e] does not support XAUI */
+ if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+ return 0;
+
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
dev_handle = fdt_get_phandle(blob, dev_off);
if (dev_handle <= 0) {
dev_handle = fdt_alloc_phandle(blob);
- fdt_setprop_cell(blob, dev_off,
- "linux,phandle", dev_handle);
+ ret = fdt_create_phandle(blob, dev_off,
+ dev_handle);
+ if (ret < 0)
+ return ret;
}
ret = fdt_setprop(blob, childoff, "dev-handle",
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
+ /* skip L2 setup on P2040/P2040E as they have no L2 */
+ mfspr r2,SPRN_SVR
+ lis r3,SVR_P2040@h
+ ori r3,r3,SVR_P2040@l
+ cmpw r2,r3
+ beq 3f
+
+ lis r3,SVR_P2040_E@h
+ ori r3,r3,SVR_P2040_E@l
+ cmpw r2,r3
+ beq 3f
+
/* Enable/invalidate the L2 cache */
msync
lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
andis. r1,r3,L2CSR0_L2E@h
beq 2b
#endif
+3:
#define EPAPR_MAGIC (0x45504150)
#define ENTRY_ADDR_UPPER 0
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/cache.h>
#include <asm/mmu.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
.long 0x27051956 /* U-BOOT Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
.globl _start_cont
/* Cache functions.
*/
+.globl flush_icache
+flush_icache:
.globl invalidate_icache
invalidate_icache:
mfspr r0,L1CSR1
return
setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
+
+/* Invalidate the DDR TLBs for the requested size */
+void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
+{
+ u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned long epn;
+ u32 tsize, valid, ptr;
+ phys_addr_t rpn = 0;
+ int ddr_esel;
+ u64 memsize = (u64)memsize_in_meg << 20;
+
+ ptr = vstart;
+
+ while (ptr < (vstart + memsize)) {
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+ disable_tlb(ddr_esel);
+ }
+ ptr += TSIZE_TO_BYTES(tsize);
+ }
+}
+
+void clear_ddr_tlbs(unsigned int memsize_in_meg)
+{
+ clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+}
+
+
#endif /* !CONFIG_NAND_SPL */
#include <asm-offsets.h>
#include <config.h>
#include <mpc86xx.h>
-#include <timestamp.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/*
* Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
*/
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <command.h>
#include <serial.h>
#include <watchdog.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
struct serial_device serial_smc_device =
{
"serial_smc",
- "SMC",
smc_init,
NULL,
smc_setbrg,
struct serial_device serial_scc_device =
{
"serial_scc",
- "SCC",
scc_init,
NULL,
scc_setbrg,
#endif /* CONFIG_8xx_CONS_SCCx */
+__weak struct serial_device *default_serial_console(void)
+{
+#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
+ return &serial_smc_device;
+#else
+ return &serial_scc_device;
+#endif
+}
+
#ifdef CONFIG_MODEM_SUPPORT
void disable_putc(void)
{
{
int i = -1;
- if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
+ if (strcmp(default_serial_console()->name, "serial_smc") == 0)
{
#if defined(CONFIG_8xx_CONS_SMC1)
i = 1;
i = 2;
#endif
}
- else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
+ else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
{
#if defined(CONFIG_8xx_CONS_SCC1)
i = 1;
if (i >= 0)
{
- serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
+ serial_printf("[on %s%d] ", default_serial_console()->name, i);
}
}
#include <asm-offsets.h>
#include <config.h>
#include <mpc8xx.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_8xx 1 /* needed for Linux kernel header files */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <common.h>
#include <config.h>
#include <version.h>
-#include <timestamp.h>
#include <i2c.h>
#include <linux/types.h>
#include <stdio_dev.h>
CPU_TYPE_ENTRY(P1016, P1016_E, 1),
CPU_TYPE_ENTRY(P1016, P1016, 1),
CPU_TYPE_ENTRY(P1017, P1017, 1),
- CPU_TYPE_ENTRY(P1017, P1017, 1),
+ CPU_TYPE_ENTRY(P1017, P1017_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
#include <asm/fsl_serdes.h>
#include <phy.h>
#include <hwconfig.h>
-#ifdef CONFIG_HAS_FSL_DR_USB
-#include <usb.h>
-#endif
+
+#define FSL_MAX_NUM_USB_CTRLS 2
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
char str[5];
int i, j;
- for (i = 1; i <= USB_MAX_DEVICE; i++) {
+ for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) {
int mode_idx = -1, phy_idx = -1;
sprintf(str, "%s%d", "usb", i);
if (hwconfig(str)) {
usb1_defined = 1;
if (mode_idx < 0 && phy_idx < 0)
printf("WARNING: invalid phy or mode\n");
- } else {
- break;
}
}
if (!usb1_defined) {
#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/mmu.h>
#include <asm/ppc4xx-isram.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#ifdef CONFIG_SYS_INIT_DCACHE_CS
# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
# define PBxAP PB1AP
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
u32 cgencrl; /* Core general control */
u8 res31[184];
u32 sriopstecr; /* SRIO prescaler timer enable control */
- u8 res32[1788];
+ u32 dcsrcr; /* DCSR Control register */
+ u8 res32[1784];
u32 pmuxcr; /* Pin multiplexing control */
u8 res33[60];
u32 iovselsr; /* I/O voltage selection status */
u8 res37[380];
} ccsr_gur_t;
+#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
+#define FSL_CORENET_DCSR_SZ_4M 0x0
+#define FSL_CORENET_DCSR_SZ_1G 0x3
+
/*
* On p4080 we have an LIODN for msg unit (rmu) but not maintenance
* everything after has RMan thus msg unit LIODN is used for maintenance
extern void print_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
+extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PVR_85xx 0x80200000
#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
+#define PVR_VER_E500_V1 0x8020
+#define PVR_VER_E500_V2 0x8021
+#define PVR_VER_E500MC 0x8023
+#define PVR_VER_E5500 0x8024
#define PVR_86xx 0x80040000
udelay (20);
- set_timer (0);
-
/* Initialize from environment */
if ((s = getenv ("loadaddr")) != NULL) {
load_addr = simple_strtoul (s, NULL, 16);
* r8: 0
* r9: 0
*/
-#if defined(CONFIG_85xx) || defined(CONFIG_440)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
#define EPAPR_MAGIC (0x45504150)
#else
#define EPAPR_MAGIC (0x65504150)
return ret;
}
+/*
+ * Verify the device tree.
+ *
+ * This function is called after all device tree fix-ups have been enacted,
+ * so that the final device tree can be verified. The definition of "verified"
+ * is up to the specific implementation. However, it generally means that the
+ * addresses of some of the devices in the device tree are compared with the
+ * actual addresses at which U-Boot has placed them.
+ *
+ * Returns 1 on success, 0 on failure. If 0 is returned, U-boot will halt the
+ * boot process.
+ */
+static int __ft_verify_fdt(void *fdt)
+{
+ return 1;
+}
+__attribute__((weak, alias("__ft_verify_fdt"))) int ft_verify_fdt(void *fdt);
+
static int boot_body_linux(bootm_headers_t *images)
{
ulong rd_len;
return ret;
of_size = ret;
- if (*initrd_start && *initrd_end)
+ if (*initrd_start && *initrd_end) {
of_size += FDT_RAMDISK_OVERHEAD;
+ fdt_set_totalsize(*of_flat_tree, of_size);
+ }
/* Create a new LMB reservation */
lmb_reserve(lmb, (ulong)*of_flat_tree, of_size);
/* fixup the initrd now that we know where it should be */
if (*initrd_start && *initrd_end)
fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+ if (!ft_verify_fdt(*of_flat_tree))
+ return -1;
}
#endif /* CONFIG_OF_LIBFDT */
return 0;
#endif /* CONFIG_SHOW_ACTIVITY */
}
-void reset_timer (void)
-{
- timestamp = 0;
-}
-
ulong get_timer (ulong base)
{
return (timestamp - base);
}
-
-void set_timer (ulong t)
-{
- timestamp = t;
-}
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <watchdog.h>
#include <net.h>
extern int dram_init(void);
extern int timer_init(void);
-const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")";
-
unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
#ifndef CONFIG_SYS_NO_FLASH
return tick_to_time(get_ticks()) - base;
}
-void set_timer (unsigned long t)
-{
- writel((0 - t), TCNT0);
-}
-
-void reset_timer (void)
-{
- tmu_timer_stop(0);
- set_timer (0);
- tmu_timer_start(0);
-}
-
unsigned long get_tbclk (void)
{
return timer_freq;
/* User Device 0 only */
cmt_timer_stop(0);
- set_timer(CMT_TIMER_RESET);
+ writew(CMT_TIMER_RESET, CMCOR_0);
cmt_timer_start(0);
return 0;
return (get_usec() / 1000) - base;
}
-void set_timer(ulong t)
-{
- writew((u16) t, CMCOR_0);
-}
-
-void reset_timer(void)
-{
- cmt_timer_stop(0);
- set_timer(CMT_TIMER_RESET);
- cmt0_timer = 0;
- cmt_timer_start(0);
-}
-
void __udelay(unsigned long usec)
{
unsigned long end = get_usec() + usec;
#include <asm/psr.h>
#include <asm/stack.h>
#include <asm/leon.h>
-#include <timestamp.h>
#include <version.h>
/* Entry for traps which jump to a programmer-specified trap handler. */
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.section ".text"
.align 4
#include <asm/psr.h>
#include <asm/stack.h>
#include <asm/leon.h>
-#include <timestamp.h>
#include <version.h>
/* Entry for traps which jump to a programmer-specified trap handler. */
.extern leon3_snooping_avail
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.section ".text"
.align 4
*
* Interrupt Transfers.
* --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
* of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
udelay(20);
- set_timer(0);
-
/* Initialize from environment */
if ((s = getenv("loadaddr")) != NULL) {
load_addr = simple_strtoul(s, NULL, 16);
timestamp++;
}
-void reset_timer(void)
-{
- timestamp = 0;
-}
-
ulong get_timer(ulong base)
{
return (timestamp - base);
}
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
void timer_interrupt_init(void)
{
int irq;
- reset_timer();
+ timestamp = 0;
irq = timer_interrupt_init_cpu();
movw %ax, %es
movw %ax, %ss
- /* Clear the interupt vectors */
+ /* Clear the interrupt vectors */
lidt blank_idt_ptr
/* Early platform init (setup gpio, etc ) */
/* arch/x86/cpu/interrupts.c */
void set_vector(u8 intnum, void *routine);
-/* arch/x86/lib/interupts.c */
+/* arch/x86/lib/interrupts.c */
void disable_irq(int irq);
void enable_irq(int irq);
int register_timer_isr (timer_fnc_t *isr_func);
/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */
-int timer_init(void);
int dram_init_f(void);
/* cpu/.../interrupts.c */
#include <watchdog.h>
#include <command.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <malloc.h>
#include <net.h>
extern ulong __bss_start;
extern ulong __bss_end;
-const char version_string[] =
- U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
-
/************************************************************************
* Init Utilities *
************************************************************************
udelay(20);
- set_timer (0);
-
/* Initialize from environment */
if ((s = getenv ("loadaddr")) != NULL) {
load_addr = simple_strtoul (s, NULL, 16);
}
}
-void reset_timer (void)
-{
- system_ticks = 0;
-}
-
ulong get_timer (ulong base)
{
return (system_ticks - base);
}
-
-void set_timer (ulong t)
-{
- system_ticks = t;
-}
{
int state;
ulong result;
+ ulong start;
volatile u16 *addr =
(volatile u16 *) (info->start[sector]);
/* wait until flash is ready */
state = 0;
- set_timer (0);
+ start = get_timer(0);
do {
result = *addr;
/* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
state = ERR_TIMOUT;
}
ulong result;
int cflag, iflag;
int state;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
*addr = data;
/* arm simple, non interrupt dependent timer */
- set_timer (0);
+ start = get_timer(0);
/* wait until flash is ready */
state = 0;
result = *addr;
/* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
state = ERR_TIMOUT;
}
if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
int dram_init(void)
{
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
remap gt regs?
map PCI mem/io
map device space
- clear out interupts
+ clear out interrupts
init_timebase
env_init
serial_init
status = i2c_get_data (data, len);
if (status) {
#ifdef DEBUG_I2C
- printf ("Data not recieved: 0x%02x\n", status);
+ printf ("Data not received: 0x%02x\n", status);
#endif
return status;
}
#define dlm ier
#define FCR_FIFO_EN 0x01 /*fifo enable*/
-#define FCR_RXSR 0x02 /*reciever soft reset*/
+#define FCR_RXSR 0x02 /*receiver soft reset*/
#define FCR_TXSR 0x04 /*transmitter soft reset*/
#define CHANNEL2_REGISTER10 0x9070
#define CHANNEL2_REGISTER11 0x9074
-/* MPSCs Interupts */
+/* MPSCs Interrupts */
#define MPSC0_CAUSE 0xb824
#define MPSC0_MASK 0xb8a4
int rc = ERR_OK;
unsigned long base;
unsigned long addr;
+ ulong start;
if ((info->flash_id & FLASH_VENDMASK) !=
(FUJ_MANUFACT & FLASH_VENDMASK)) {
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
/* ARM simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
{
int flag;
unsigned long base;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
flag = disable_interrupts ();
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
base = dest & 0xF0000000;
FL_WORD (base + (0x555 << 1)) = 0xAA;
/* init the timestamp */
total_count = 0ULL;
- reset_timer_masked();
+ /* capure current decrementer value */
+ lastdec = READ_TIMER;
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0L;
div_timer = CONFIG_SYS_HZ_CLOCK;
do_div(div_timer, CONFIG_SYS_HZ);
/*
* timer without interrupts
*/
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
ulong get_timer (ulong base_ticks)
{
return get_timer_masked () - base_ticks;
}
-void set_timer (ulong ticks)
-{
- timestamp = ticks;
- total_count = ticks * div_timer;
-}
-
/* delay usec useconds */
void __udelay (unsigned long usec)
{
}
}
-void reset_timer_masked (void)
-{
- /* capure current decrementer value */
- lastdec = READ_TIMER;
- /* start "advancing" time stamp from 0 */
- timestamp = 0L;
-}
-
/* converts the timer reading to U-Boot ticks */
/* the timestamp is the number of ticks since reset */
ulong get_timer_masked (void)
timestamp = 0;
}
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
ulong get_timer_masked(void)
{
ulong now = readl(&systimer_base->timer0value) / 1000;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1;
+ ulong start;
/* first look for protection bits */
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
volatile u16 *addr = (volatile u16 *) (info->start[sect]);
result = *addr;
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
int rc = ERR_OK;
int cflag, iflag;
int chip1;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait until flash is ready */
chip1 = 0;
result = *addr;
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip1 = ERR | TMO;
break;
}
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#define afr iirfcrafr
#define FCR_FIFO_EN 0x01 /*fifo enable */
-#define FCR_RXSR 0x02 /*reciever soft reset */
+#define FCR_RXSR 0x02 /*receiver soft reset */
#define FCR_TXSR 0x04 /*transmitter soft reset */
#define FCR_DMS 0x08 /* DMA Mode Select */
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
int flag, prot, sect;
ulong type;
int rcode = 0;
+ ulong start;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
addr = (volatile unsigned char *) (info->start[sect]);
*addr = 0x50; /* clear status register */
*addr = 0xD0; /* erase confirm */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xB0; /* suspend erase */
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = 0xFF; /* restore read mode */
return (1);
}
int flag, prot, sect;
ulong type;
int rcode = 0;
+ ulong start;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
addr = (volatile unsigned char *) (info->start[sect]);
*addr = 0x50; /* clear status register */
*addr = 0xD0; /* erase confirm */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xB0; /* suspend erase */
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = 0xFF; /* restore read mode */
return (1);
}
{
vu_short *addr = (vu_short *)(info->start[0]);
int flag, prot, sect, ssect, l_sect;
- ulong now, last;
+ ulong now, last, start;
debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
if (l_sect < 0)
goto DONE;
- reset_timer_masked ();
+ start = get_timer(0);
last = 0;
addr = (vu_short *)(info->start[l_sect]);
while ((addr[0] & 0x0080) != 0x0080) {
- if ((now = get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
{
int flag;
vu_short *base; /* first address in flash bank */
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
if (flag)
enable_interrupts();
- reset_timer_masked ();
+ start = get_timer(0);
/* data polling for D7 */
while ((*dest & 0x0080) != (data & 0x0080)) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = 0x00F0; /* reset bank */
return (1);
}
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1;
+ ulong start;
/* first look for protection bits */
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- set_timer (0);
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
volatile u16 *addr =
result = *addr;
/* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
int rc = ERR_OK;
int cflag, iflag;
int chip1;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
*addr = data;
/* arm simple, non interrupt dependent timer */
- set_timer (0);
+ start = get_timer(0);
/* wait until flash is ready */
chip1 = 0;
result = *addr;
/* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip1 = ERR | TMO;
break;
}
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
*addr = 0xD0; /* erase confirm */
while ((*addr & 0x80) != 0x80) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0xB0; /* suspend erase */
*addr = 0xFF; /* reset to read mode */
vu_short *addr = (vu_short *) dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((val = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0xB0;
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
u32 * volatile addr = (u32 * volatile)(info->start[sect]);
*addr = 0x00D000D0; /* erase confirm */
while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B000B0; /* suspend erase*/
*addr = 0x00FF00FF; /* read mode */
rc = ERR_TIMOUT;
u32 * volatile addr = (u32 * volatile)dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* read array command - just for the case... */
*addr = 0x00FF00FF;
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while(((val = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0x00B000B0;
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (volatile void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
*addr = (FPW)0x00500050; /* clear status register */
*addr = (FPW)0x00200020; /* erase setup */
*addr = (FPW)0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW)0x00B000B0; /* suspend erase */
*addr = (FPW)0x00FF00FF; /* reset to read mode */
FPWV *addr = (FPWV *)dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (start = get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW)0x00FF00FF; /* restore read mode */
return (1);
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
*addr = 0xD0; /* erase confirm */
while ((*addr & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0xB0; /* suspend erase */
*addr = 0xFF; /* reset to read mode */
rc = ERR_TIMOUT;
vu_short *addr = (vu_short *) dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((val = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0xB0;
int dram_init(void)
{
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
remap gt regs?
map PCI mem/io
map device space
- clear out interupts
+ clear out interrupts
init_timebase
env_init
serial_init
status = i2c_get_data(data, len);
if (status) {
#ifdef DEBUG_I2C
- printf("Data not recieved: 0x%02x\n", status);
+ printf("Data not received: 0x%02x\n", status);
#endif
return status;
}
#endif
fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
}
int board_eth_init(bd_t *bis)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
#endif
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
The 11th column addre will still be mucxed correctly onto the bus.
Also be aware that the MPC8266ADS board Rev B has not connected
- Row addres 13 to anything.
+ Row address 13 to anything.
The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
*/
setup_ddr_bat(dram_size);
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
setup_ddr_bat(dram_size);
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
{
u32 size1, size2;
- size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
{
u32 size1, size2;
- size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
{
u32 size1, size2;
- size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
#
-# (C) Copyright 2007-2008 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
+# Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o \
- ../common/fixed_sdram.o \
- ../common/nm_bsp.o
+COBJS-y += $(BOARD).o
+COBJS-y += cpld.o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+COBJS-$(CONFIG_PCI) += pci.o
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(OBJS)
+ rm -f $(OBJS) $(SOBJS)
distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
+ rm -f $(LIB) core *.bak .depend
#########################################################################
--- /dev/null
+/**
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CPLD_BASE - The virtual address of the base of the CPLD register map
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+static u8 __cpld_read(unsigned int reg)
+{
+ void *p = (void *)CPLD_BASE;
+
+ return in_8(p + reg);
+}
+u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
+
+static void __cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+void cpld_write(unsigned int reg, u8 value)
+ __attribute__((weak, alias("__cpld_write")));
+
+/*
+ * Reset the board. This honors the por_cfg registers.
+ */
+void __cpld_reset(void)
+{
+ CPLD_WRITE(system_rst, 1);
+}
+void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void __cpld_set_altbank(void)
+{
+ CPLD_WRITE(fbank_sel, 1);
+}
+void cpld_set_altbank(void)
+ __attribute__((weak, alias("__cpld_set_altbank")));
+
+/**
+ * Set the boot bank to the default bank
+ */
+void __cpld_clear_altbank(void)
+{
+ CPLD_WRITE(fbank_sel, 0);
+}
+void cpld_clear_altbank(void)
+ __attribute__((weak, alias("__cpld_clear_altbank")));
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+ printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
+ printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
+ printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg));
+ printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
+ printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
+ printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
+ printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
+ printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
+ printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
+ printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
+ printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
+ printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
+ putc('\n');
+}
+#endif
+
+int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+ unsigned int i;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_clear_altbank();
+
+ cpld_reset();
+ } else if (strcmp(argv[1], "watchdog") == 0) {
+ static char *period[8] = {"1ms", "10ms", "30ms", "disable",
+ "100ms", "1s", "10s", "60s"};
+ for (i = 0; i < ARRAY_SIZE(period); i++) {
+ if (strcmp(argv[2], period[i]) == 0)
+ CPLD_WRITE(wd_cfg, i);
+ }
+ } else if (strcmp(argv[1], "lane_mux") == 0) {
+ u32 lane = simple_strtoul(argv[2], NULL, 16);
+ u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
+ u8 reg = CPLD_READ(serdes_mux);
+
+ switch (lane) {
+ case 0x6:
+ reg &= ~SERDES_MUX_LANE_6_MASK;
+ reg |= val << SERDES_MUX_LANE_6_SHIFT;
+ break;
+ case 0xa:
+ reg &= ~SERDES_MUX_LANE_A_MASK;
+ reg |= val << SERDES_MUX_LANE_A_SHIFT;
+ break;
+ case 0xc:
+ reg &= ~SERDES_MUX_LANE_C_MASK;
+ reg |= val << SERDES_MUX_LANE_C_SHIFT;
+ break;
+ case 0xd:
+ reg &= ~SERDES_MUX_LANE_D_MASK;
+ reg |= val << SERDES_MUX_LANE_D_SHIFT;
+ break;
+ default:
+ printf("Invalid value\n");
+ break;
+ }
+
+ CPLD_WRITE(serdes_mux, reg);
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
+ "Reset the board or pin mulexing selection using the CPLD sequencer",
+ "reset - hard reset to default bank\n"
+ "cpld_cmd reset altbank - reset to alternate bank\n"
+ "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
+ " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
+ "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
+ " lane 6: 0 -> slot1 (Default)\n"
+ " 1 -> SGMII\n"
+ " lane a: 0 -> slot2 (Default)\n"
+ " 1 -> AURORA\n"
+ " lane c: 0 -> slot2 (Default)\n"
+ " 1 -> SATA0\n"
+ " lane d: 0 -> slot2 (Default)\n"
+ " 1 -> SATA1\n"
+#ifdef DEBUG
+ "cpld_cmd dump - display the CPLD registers\n"
+#endif
+ );
--- /dev/null
+/**
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct cpld_data {
+ u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
+ u8 pcba_ver; /* 0x2 - PCBA Revision Register */
+ u8 system_rst; /* 0x3 - system reset register */
+ u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */
+ u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
+ u8 por_cfg; /* 0x6 - POR Control Register */
+ u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
+ u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
+ u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
+ u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
+ u8 fbank_sel; /* 0xb - Flash bank selection */
+ u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
+ u8 sw[1]; /* 0xd - SW2 Status */
+} __attribute__ ((packed)) cpld_data_t;
+
+#define SERDES_MUX_LANE_6_MASK 0x2
+#define SERDES_MUX_LANE_6_SHIFT 1
+#define SERDES_MUX_LANE_A_MASK 0x1
+#define SERDES_MUX_LANE_A_SHIFT 0
+#define SERDES_MUX_LANE_C_MASK 0x4
+#define SERDES_MUX_LANE_C_SHIFT 2
+#define SERDES_MUX_LANE_D_MASK 0x8
+#define SERDES_MUX_LANE_D_SHIFT 3
+
+/* Pointer to the CPLD register set */
+#define cpld ((cpld_data_t *)CPLD_BASE)
+
+/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
+#define CPLD_SW(x) (cpld->sw[(x) - 2])
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
+#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+typedef struct {
+ u32 datarate_mhz_low;
+ u32 datarate_mhz_high;
+ u32 n_ranks;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+} board_specific_parameters_t;
+
+/*
+ * ranges for parameters:
+ * wr_data_delay = 0-6
+ * clk adjust = 0-8
+ * cpo 2-0x1E (30)
+ */
+const board_specific_parameters_t board_specific_parameters[] = {
+ /*
+ * memory controller 0
+ * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
+ * mhz| mhz|ranks|adjst| start | delay|
+ */
+ { 1017, 1116, 2, 4, 6, 0xff, 2, 0},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const board_specific_parameters_t *pbsp =
+ &board_specific_parameters[0];
+ u32 num_params = ARRAY_SIZE(board_specific_parameters);
+ u32 i;
+ ulong ddr_freq;
+
+ /*
+ * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high &&
+ pdimm[0].n_ranks == pbsp->n_ranks) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->twoT_en = pbsp->force_2T;
+ break;
+ }
+ pbsp++;
+ }
+
+ if (i == num_params) {
+ printf("Warning: board specific timing not found "
+ "for data rate %lu MT/s!\n", ddr_freq);
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /* Write leveling override */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /* Rtt and Rtt_WR override */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 60 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts("Initializing....");
+
+ if (fsl_use_spd()) {
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+ } else {
+ puts("no SPD and fixed parameters\n");
+ return dram_size;
+ }
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ debug(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+ SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+extern void pci_of_setup(void *blob, bd_t *bd);
+
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ u8 sw;
+ struct cpu_type *cpu = gd->cpu;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ unsigned int i;
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
+ CPLD_READ(cpld_ver_sub));
+
+ sw = CPLD_READ(fbank_sel);
+ printf("vBank: %d\n", sw & 0x1);
+
+#ifdef CONFIG_PHYS_64BIT
+ puts("36-bit Addressing\n");
+#endif
+
+ /*
+ * Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+ sw = in_8(&CPLD_SW(2)) >> 2;
+ for (i = 0; i < 2; i++) {
+ static const char * const freq[] = {"0", "100", "125"};
+ unsigned int clock = (sw >> (2 * i)) & 3;
+
+ printf("Bank%u=%sMhz ", i+1, freq[clock]);
+ }
+ puts("\n");
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
+ setbits_be32(&gur->ddrclkdr, 0x000f000f);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+ setup_portals();
+
+ return 0;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ default:
+ return "150";
+ }
+}
+
+#define NUM_SRDS_BANKS 2
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[NUM_SRDS_BANKS];
+ unsigned int i;
+ u8 sw;
+
+ sw = in_8(&CPLD_SW(2)) >> 2;
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ unsigned int clock = (sw >> (2 * i)) & 3;
+ switch (clock) {
+ case 1:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 2:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ default:
+ printf("Warning: SDREFCLK%u switch setting of '11' is "
+ "unsupported\n", i + 1);
+ break;
+ }
+ }
+
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 expected = in_be32(®s->bank[i].pllcr0);
+ expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES bank %u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+}
/*
- * Copyright (C) 2005, 2006 Atmel Corporation
+ * Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __ASM_AVR32_INITCALLS_H__
-#define __ASM_AVR32_INITCALLS_H__
-#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
-extern int cpu_init(void);
-extern int timer_init(void);
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
-#endif /* __ASM_AVR32_INITCALLS_H__ */
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_1M, 1),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
flash_erase(flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf("\n");
}
- start = get_timer(0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
*/
int
-fpga_load (int mezz, uchar *addr, ulong size)
+fpga_load(int mezz, const uchar *addr, ulong size)
{
hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
xlx_info_t *fp;
xlx_iopins_t *fpgaio;
volatile uchar *fpgabase;
volatile uint cnt;
- uchar *eaddr = addr + size;
+ const uchar *eaddr = addr + size;
int result;
if (mezz)
int iflag, prot, sect;
int rc = ERR_OK;
int chip1;
+ ulong start;
/* first look for protection bits */
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- set_timer (0);
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
volatile u16 *addr =
result = *addr;
/* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
int rc = ERR_OK;
int iflag;
int chip1;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
*addr = data;
/* arm simple, non interrupt dependent timer */
- set_timer (0);
+ start = get_timer(0);
/* wait until flash is ready */
chip1 = 0;
result = *addr;
/* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
chip1 = ERR | TMO;
break;
}
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *) (info->start[sect]);
*addr = 0x00D000D0; /* erase confirm */
while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B000B0; /* suspend erase */
*addr = 0x00FF00FF; /* reset to read mode */
ulong barf;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* read status register command */
*addr = 0x00700070;
/* wait while polling the status register */
while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0x00B000B0;
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
PRINTK("\n");
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
u16 * volatile addr = (u16 * volatile)(info->start[sect]);
while ((*addr & 0x0080) != 0x0080) {
PRINTK(".");
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B0; /* suspend erase*/
*addr = 0x00FF; /* read mode */
rc = ERR_TIMOUT;
volatile u16 *addr = (u16 *)dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) return ERR_NOT_ERASED;
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while(((val = *addr) & 0x80) != 0x80) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
*addr = 0xB0; /* suspend program command */
goto outahere;
LIB = $(obj)lib$(BOARD).o
-COBJS := $(BOARD).o cmd_mtc.o
+COBJS-y := $(BOARD).o cmd_mtc.o
+COBJS-$(CONFIG_VIDEO) += cmd_disp.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
--- /dev/null
+/*
+ * (C) Copyright 2011 DENX Software Engineering,
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include <asm/io.h>
+
+#define GPIO_USB1_0 0x00010000
+
+static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (argc < 2) {
+ printf("%s\n",
+ in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off");
+ return 0;
+ }
+
+ if (!strncmp(argv[1], "on", 2)) {
+ setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+ } else if (!strncmp(argv[1], "off", 3)) {
+ clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+ } else {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+ return 0;
+}
+
+U_BOOT_CMD(disp, 2, 1, cmd_disp,
+ "disp [on/off] - switch display on/off",
+ "\n - print display on/off status\n"
+ "on\n - turn on\n"
+ "off\n - turn off\n"
+);
DECLARE_GLOBAL_DATA_PTR;
+static uchar user_out;
+
static const char *led_names[] = {
"diag",
"can1",
else
pcmd.cmd_val2 = 0;
+ pcmd.user_out = user_out;
+
mtc_calculate_checksum(&pcmd);
err = msp430_xfer(&pcmd, &prx);
memset(&prx, 0, sizeof(prx));
pcmd.cmd = CMD_GET_VIM;
+ pcmd.user_out = user_out;
mtc_calculate_checksum(&pcmd);
err = msp430_xfer(&pcmd, &prx);
pcmd.cmd = CMD_GET_VIM;
pcmd.user_out = channel_mask;
+ user_out = channel_mask;
mtc_calculate_checksum(&pcmd);
err = msp430_xfer(&pcmd, &prx);
memset(&prx, 0, sizeof(prx));
pcmd.cmd = CMD_GET_VIM;
+ pcmd.user_out = user_out;
mtc_calculate_checksum(&pcmd);
err = msp430_xfer(&pcmd, &prx);
rx_msp_cmd prx;
int err;
char buf[5];
+ uchar appreg;
/* read appreg */
memset(&pcmd, 0, sizeof(pcmd));
pcmd.cmd_val0 = 5; /* max. Count */
pcmd.cmd_val1 = 5; /* max. Time */
pcmd.cmd_val2 = 0; /* =0 means read appreg */
+ pcmd.user_out = user_out;
mtc_calculate_checksum(&pcmd);
err = msp430_xfer(&pcmd, &prx);
+ /* on success decide between read or write */
if (!err) {
- sprintf(buf, "%d", prx.ack2);
- setenv("appreg", buf);
+ if (argc == 2) {
+ appreg = simple_strtol(argv[1], NULL, 10);
+ if (appreg == 0) {
+ printf("mtc appreg: invalid parameter - "
+ "must be between 1 and 255\n");
+ return -1;
+ }
+ memset(&pcmd, 0, sizeof(pcmd));
+ pcmd.cmd = CMD_WD_PARA;
+ pcmd.cmd_val0 = prx.ack3; /* max. Count */
+ pcmd.cmd_val1 = prx.ack0; /* max. Time */
+ pcmd.cmd_val2 = appreg; /* !=0 means write appreg */
+ pcmd.user_out = user_out;
+ memset(&prx, 0, sizeof(prx));
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+ } else {
+ sprintf(buf, "%d", prx.ack2);
+ setenv("appreg", buf);
+ }
}
return err;
memset(&prx, 0, sizeof(prx));
pcmd.cmd = CMD_FW_VERSION;
+ pcmd.user_out = user_out;
mtc_calculate_checksum(&pcmd);
err = msp430_xfer(&pcmd, &prx);
pcmd.cmd = CMD_WD_WDSTATE;
pcmd.cmd_val2 = 1;
+ pcmd.user_out = user_out;
mtc_calculate_checksum(&pcmd);
err = msp430_xfer(&pcmd, &prx);
"returns state of user key", ""),
U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
"returns firmware version of supervisor uC", ""),
- U_BOOT_CMD_MKENT(appreg, 0, 1, do_mtc_appreg,
- "reads appreg value and stores in environment variable 'appreg'", ""),
+ U_BOOT_CMD_MKENT(appreg, 1, 1, do_mtc_appreg,
+ "reads or writes appreg value and stores in environment "
+ "variable 'appreg'",
+ "[value] - value (1 - 255) to write to appreg"),
U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
"returns state of digital input",
"<channel_num> - get state of digital input (1 or 2)\n"),
" [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n"
"key - returns state of user key\n"
"version - returns firmware version of supervisor uC\n"
- "appreg - reads appreg value and stores in environment variable"
- " 'appreg'\n"
+ "appreg [value] - reads (in environment variable 'appreg') or writes"
+ " appreg value\n"
+ " [value]: value (1 - 255) to write to appreg\n"
"digin [channel] - returns state of digital input (1 or 2)\n"
"digout <on|off> <on|off> - sets state of two digital outputs\n"
"state - displays state\n"
#endif
#include <libfdt.h>
#include <fdt_support.h>
+#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#if defined(CONFIG_VIDEO)
+
+#define GPIO_USB1_0 0x00010000 /* Power-On pin */
+#define GPIO_USB1_9 0x08 /* PX_~EN pin */
+
+#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
+#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
+#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
+#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
+
+#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
+
+/* ExBo I2C Addresses */
+#define EXBO_EE_I2C_ADDRESS 0x56
+
+static void exbo_hw_init(void)
+{
+ struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+ unsigned char val;
+
+ /* 1st, check if extension board is present */
+ if (i2c_read(EXBO_EE_I2C_ADDRESS, 0, 1, &val, 1))
+ return;
+
+ /* configure IrDA pins (PSC6 port) as gpios */
+ gpio->port_config &= 0xFF8FFFFF;
+
+ /* Init for USB1_0, EE_CLK and EE_DI - Low */
+ setbits_be32(&gpio->simple_ddr,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+ clrbits_be32(&gpio->simple_ode,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+ clrbits_be32(&gpio->simple_dvo,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+ setbits_be32(&gpio->simple_gpioe,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+
+ /* Init for EE_DO, EE_CTS - Input */
+ clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
+ setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
+
+ /* Init for PX_~EN (USB1_9) - High */
+ clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
+ setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
+ clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
+ setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
+ setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
+
+ /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
+ out_be32(&gpt[0].emsr, GPT_GPIO_ON);
+ /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
+ out_be32(&gpt[1].emsr, GPT_GPIO_ON);
+
+ /* Power-On camera supply */
+ setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+}
+#else
+static inline void exbo_hw_init(void) {}
+#endif /* CONFIG_VIDEO */
+
int board_early_init_r(void)
{
#ifdef CONFIG_MPC52XX_SPI
/* enable CS0 */
setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
+ exbo_hw_init();
+
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
/* Low level USB init, required for proper kernel operation */
usb_cpu_init();
#define EEPROM_ADDR_IDENT 0 /* identification word offset */
#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */
#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */
-#define EEPROM_ADDR_ETHADDR 23 /* ethernet addres offset */
+#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */
#endif
writel(0x0, &padctl->pad_d11);
/* drop PHY power and assert reset (low) */
- val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9));
- writel(val, &gpio4->dr);
- val = readl(&gpio4->dir) | (1 << 7) | (1 << 9);
- writel(val, &gpio4->dir);
+ val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9));
+ writel(val, &gpio4->gpio_dr);
+ val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9);
+ writel(val, &gpio4->gpio_dir);
mdelay(5);
debug("resetting phy\n");
/* turn on PHY power leaving reset asserted */
- val = readl(&gpio4->dr) | 1 << 9;
- writel(val, &gpio4->dr);
+ val = readl(&gpio4->gpio_dr) | 1 << 9;
+ writel(val, &gpio4->gpio_dr);
mdelay(10);
/*
* set each to 1 and make each an output
*/
- val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12);
- writel(val, &gpio3->dr);
- val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12);
- writel(val, &gpio3->dir);
+ val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12);
+ writel(val, &gpio3->gpio_dr);
+ val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12);
+ writel(val, &gpio3->gpio_dir);
mdelay(22); /* this value came from RedBoot */
/*
* deassert PHY reset
*/
- val = readl(&gpio4->dr) | 1 << 7;
- writel(val, &gpio4->dr);
- writel(val, &gpio4->dr);
+ val = readl(&gpio4->gpio_dr) | 1 << 7;
+ writel(val, &gpio4->gpio_dr);
+ writel(val, &gpio4->gpio_dr);
mdelay(5);
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
#else
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*/
#include <common.h>
-#if defined(CONFIG_KM82XX)
-#include <mpc8260.h>
-#endif
#include <ioports.h>
#include <command.h>
#include <malloc.h>
#include <libfdt.h>
#endif
-#include "../common/common.h"
+#include "common.h"
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
+#endif
static void i2c_write_start_seq(void);
-static int i2c_make_abort(void);
DECLARE_GLOBAL_DATA_PTR;
-int ivm_calc_crc(unsigned char *buf, int len)
-{
- const unsigned short crc_tab[16] = {
- 0x0000, 0xCC01, 0xD801, 0x1400,
- 0xF001, 0x3C00, 0x2800, 0xE401,
- 0xA001, 0x6C00, 0x7800, 0xB401,
- 0x5000, 0x9C01, 0x8801, 0x4400};
-
- unsigned short crc = 0; /* final result */
- unsigned short r1 = 0; /* temp */
- unsigned char byte = 0; /* input buffer */
- int i;
-
- /* calculate CRC from array data */
- for (i = 0; i < len; i++) {
- byte = buf[i];
-
- /* lower 4 bits */
- r1 = crc_tab[crc & 0xF];
- crc = ((crc) >> 4) & 0x0FFF;
- crc = crc ^ r1 ^ crc_tab[byte & 0xF];
-
- /* upper 4 bits */
- r1 = crc_tab[crc & 0xF];
- crc = (crc >> 4) & 0x0FFF;
- crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF];
- }
- return crc;
-}
-
/*
* Set Keymile specific environment variables
* Currently only some memory layout variables are calculated here
return 0;
}
-static int ivm_set_value(char *name, char *value)
-{
- char tempbuf[256];
-
- if (value != NULL) {
- sprintf(tempbuf, "%s=%s", name, value);
- return set_local_var(tempbuf, 0);
- } else {
- unset_local_var(name);
- }
- return 0;
-}
-
-static int ivm_get_value(unsigned char *buf, int len, char *name, int off,
- int check)
-{
- unsigned short val;
- unsigned char valbuf[30];
-
- if ((buf[off + 0] != buf[off + 2]) &&
- (buf[off + 2] != buf[off + 4])) {
- printf("%s Error corrupted %s\n", __func__, name);
- val = -1;
- } else {
- val = buf[off + 0] + (buf[off + 1] << 8);
- if ((val == 0) && (check == 1))
- val = -1;
- }
- sprintf((char *)valbuf, "%x", val);
- ivm_set_value(name, (char *)valbuf);
- return val;
-}
-
-#define INV_BLOCKSIZE 0x100
-#define INV_DATAADDRESS 0x21
-#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3)
-
-#define IVM_POS_SHORT_TEXT 0
-#define IVM_POS_MANU_ID 1
-#define IVM_POS_MANU_SERIAL 2
-#define IVM_POS_PART_NUMBER 3
-#define IVM_POS_BUILD_STATE 4
-#define IVM_POS_SUPPLIER_PART_NUMBER 5
-#define IVM_POS_DELIVERY_DATE 6
-#define IVM_POS_SUPPLIER_BUILD_STATE 7
-#define IVM_POS_CUSTOMER_ID 8
-#define IVM_POS_CUSTOMER_PROD_ID 9
-#define IVM_POS_HISTORY 10
-#define IVM_POS_SYMBOL_ONLY 11
-
-static char convert_char(char c)
-{
- return (c < ' ' || c > '~') ? '.' : c;
-}
-
-static int ivm_findinventorystring(int type,
- unsigned char* const string,
- unsigned long maxlen,
- unsigned char *buf)
-{
- int xcode = 0;
- unsigned long cr = 0;
- unsigned long addr = INV_DATAADDRESS;
- unsigned long size = 0;
- unsigned long nr = type;
- int stop = 0; /* stop on semicolon */
-
- memset(string, '\0', maxlen);
- switch (type) {
- case IVM_POS_SYMBOL_ONLY:
- nr = 0;
- stop= 1;
- break;
- default:
- nr = type;
- stop = 0;
- }
-
- /* Look for the requested number of CR. */
- while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
- if ((buf[addr] == '\r')) {
- cr++;
- }
- addr++;
- }
-
- /*
- * the expected number of CR was found until the end of the IVM
- * content --> fill string
- */
- if (addr < INVENTORYDATASIZE) {
- /* Copy the IVM string in the corresponding string */
- for (; (buf[addr] != '\r') &&
- ((buf[addr] != ';') || (!stop)) &&
- (size < (maxlen - 1) &&
- (addr < INVENTORYDATASIZE)); addr++)
- {
- size += sprintf((char *)string + size, "%c",
- convert_char (buf[addr]));
- }
-
- /*
- * copy phase is done: check if everything is ok. If not,
- * the inventory data is most probably corrupted: tell
- * the world there is a problem!
- */
- if (addr == INVENTORYDATASIZE) {
- xcode = -1;
- printf("Error end of string not found\n");
- } else if ((size >= (maxlen - 1)) &&
- (buf[addr] != '\r')) {
- xcode = -1;
- printf("string too long till next CR\n");
- }
- } else {
- /*
- * some CR are missing...
- * the inventory data is most probably corrupted
- */
- xcode = -1;
- printf("not enough cr found\n");
- }
- return xcode;
-}
-
-#define GET_STRING(name, which, len) \
- if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \
- ivm_set_value(name, (char *)valbuf); \
- }
-
-static int ivm_check_crc(unsigned char *buf, int block)
-{
- unsigned long crc;
- unsigned long crceeprom;
-
- crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
- crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
- buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
- if (crc != crceeprom) {
- if (block == 0)
- printf("Error CRC Block: %d EEprom: calculated: \
- %lx EEprom: %lx\n", block, crc, crceeprom);
- return -1;
- }
- return 0;
-}
-
-static int ivm_analyze_block2(unsigned char *buf, int len)
-{
- unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
- unsigned long count;
-
- /* IVM_MacAddress */
- sprintf((char *)valbuf, "%pM", buf);
- ivm_set_value("IVM_MacAddress", (char *)valbuf);
- /* if an offset is defined, add it */
-#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
- if (CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) {
- unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
-
- val += CONFIG_PIGGY_MAC_ADRESS_OFFSET;
- buf[4] = (val >> 16) & 0xff;
- buf[5] = (val >> 8) & 0xff;
- buf[6] = val & 0xff;
- sprintf((char *)valbuf, "%pM", buf);
- }
-#endif
- if (getenv("ethaddr") == NULL)
- setenv((char *)"ethaddr", (char *)valbuf);
-
- /* IVM_MacCount */
- count = (buf[10] << 24) +
- (buf[11] << 16) +
- (buf[12] << 8) +
- buf[13];
- if (count == 0xffffffff)
- count = 1;
- sprintf((char *)valbuf, "%lx", count);
- ivm_set_value("IVM_MacCount", (char *)valbuf);
- return 0;
-}
-
-int ivm_analyze_eeprom(unsigned char *buf, int len)
-{
- unsigned short val;
- unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
- unsigned char *tmp;
-
- if (ivm_check_crc(buf, 0) != 0)
- return -1;
-
- ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
- "IVM_BoardId", 0, 1);
- val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
- "IVM_HWKey", 6, 1);
- if (val != 0xffff) {
- sprintf((char *)valbuf, "%x", ((val / 100) % 10));
- ivm_set_value("IVM_HWVariant", (char *)valbuf);
- sprintf((char *)valbuf, "%x", (val % 100));
- ivm_set_value("IVM_HWVersion", (char *)valbuf);
- }
- ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
- "IVM_Functions", 12, 0);
-
- GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
- GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
- tmp = (unsigned char *) getenv("IVM_DeviceName");
- if (tmp) {
- int len = strlen((char *)tmp);
- int i = 0;
-
- while (i < len) {
- if (tmp[i] == ';') {
- ivm_set_value("IVM_ShortText",
- (char *)&tmp[i + 1]);
- break;
- }
- i++;
- }
- if (i >= len)
- ivm_set_value("IVM_ShortText", NULL);
- } else {
- ivm_set_value("IVM_ShortText", NULL);
- }
- GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
- GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
- GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32)
- GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32)
- GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32)
- GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32)
- GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32)
- GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
- GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
-
- if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
- return 0;
- ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2],
- CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
-
- return 0;
-}
-
-int ivm_read_eeprom(void)
-{
-#if defined(CONFIG_I2C_MUX)
- I2C_MUX_DEVICE *dev = NULL;
-#endif
- uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
- uchar *buf;
- unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
- int ret;
-
-#if defined(CONFIG_I2C_MUX)
- /* First init the Bus, select the Bus */
-#if defined(CONFIG_SYS_I2C_IVM_BUS)
- dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS);
-#else
- buf = (unsigned char *) getenv("EEprom_ivm");
- if (buf != NULL)
- dev = i2c_mux_ident_muxstring(buf);
-#endif
- if (dev == NULL) {
- printf("Error couldnt add Bus for IVM\n");
- return -1;
- }
- i2c_set_bus_num(dev->busid);
-#endif
-
- buf = (unsigned char *) getenv("EEprom_ivm_addr");
- if (buf != NULL)
- dev_addr = simple_strtoul((char *)buf, NULL, 16);
-
- /* add deblocking here */
- i2c_make_abort();
-
- ret = i2c_read(dev_addr, 0, 1, i2c_buffer,
- CONFIG_SYS_IVM_EEPROM_MAX_LEN);
- if (ret != 0) {
- printf ("Error reading EEprom\n");
- return -2;
- }
-
- return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
-}
-
-#if defined(CONFIG_SYS_I2C_INIT_BOARD)
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
-#if defined(CONFIG_KM_82XX)
-#define SDA_MASK 0x00010000
-#define SCL_MASK 0x00020000
-void set_pin(int state, unsigned long mask)
-{
- ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
-
- if (state)
- setbits_be32(&iop->pdat, mask);
- else
- clrbits_be32(&iop->pdat, mask);
-
- setbits_be32(&iop->pdir, mask);
-}
-
-static int get_pin(unsigned long mask)
-{
- ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
-
- clrbits_be32(&iop->pdir, mask);
- return 0 != (in_be32(&iop->pdat) & mask);
-}
-
-static void set_sda(int state)
-{
- set_pin(state, SDA_MASK);
-}
-
-static void set_scl(int state)
-{
- set_pin(state, SCL_MASK);
-}
-
-static int get_sda(void)
-{
- return get_pin(SDA_MASK);
-}
-
-static int get_scl(void)
-{
- return get_pin(SCL_MASK);
-}
-
-#if defined(CONFIG_HARD_I2C)
-static void setports(int gpio)
-{
- ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
-
- if (gpio) {
- clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
- clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
- } else {
- setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
- clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
- setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
- }
-}
-#endif
-#endif
-
#if !defined(CONFIG_MPC83xx)
static void i2c_write_start_seq(void)
{
* This I2C Deblocking mechanism was developed by Keymile in association
* with Anatech and Atmel in 1998.
*/
-static int i2c_make_abort(void)
+int i2c_make_abort(void)
{
#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
sda_state = get_sda();
if (scl_state && sda_state) {
ret = 0;
+ printf("[INFO] i2c abort after %d clocks\n", i);
break;
}
}
if (ret == 0)
for (i = 0; i < 5; i++)
i2c_write_start_seq();
+ else
+ printf("[ERROR] i2c abort failed\n");
/* respect stop setup time */
udelay(DELAY_ABORT_SEQ);
#endif
return ret;
}
-#endif
+#endif /* !MPC83xx */
#if defined(CONFIG_MPC83xx)
static void i2c_write_start_seq(void)
out_8(&dev->cr, (I2C_CR_MEN));
}
-static int i2c_make_abort(void)
+int i2c_make_abort(void)
{
struct fsl_i2c *dev;
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
/* Now run the AbortSequence() */
i2c_make_abort();
}
-#endif
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-int fdt_set_node_and_value(void *blob,
- char *nodename,
- char *regname,
- void *var,
- int size)
-{
- int ret = 0;
- int nodeoffset = 0;
-
- nodeoffset = fdt_path_offset(blob, nodename);
- if (nodeoffset >= 0) {
- ret = fdt_setprop(blob, nodeoffset, regname, var,
- size);
- if (ret < 0)
- printf("ft_blob_update(): cannot set %s/%s "
- "property err:%s\n", nodename, regname,
- fdt_strerror(ret));
- } else {
- printf("ft_blob_update(): cannot find %s node "
- "err:%s\n", nodename, fdt_strerror(nodeoffset));
- }
- return ret;
-}
-
-int fdt_get_node_and_value(void *blob,
- char *nodename,
- char *propname,
- void **var)
-{
- int len;
- int nodeoffset = 0;
-
- nodeoffset = fdt_path_offset(blob, nodename);
- if (nodeoffset >= 0) {
- *var = (void *)fdt_getprop(blob, nodeoffset, propname, &len);
- if (len == 0) {
- /* no value */
- printf("%s no value\n", __func__);
- return -1;
- } else if (len > 0) {
- return len;
- } else {
- printf("libfdt fdt_getprop(): %s\n",
- fdt_strerror(len));
- return -2;
- }
- } else {
- printf("%s: cannot find %s node err:%s\n", __func__,
- nodename, fdt_strerror(nodeoffset));
- return -3;
- }
-}
-#endif
#if !defined(MACH_TYPE_KM_KIRKWOOD)
int ethernet_present(void)
}
sprintf((char *)buf, "%s", p);
setenv("boardid", (char *)buf);
+ printf("set boardid=%s\n", buf);
p = get_local_var("IVM_HWKey");
if (p == NULL) {
}
sprintf((char *)buf, "%s", p);
setenv("hwkey", (char *)buf);
+ printf("set hwkey=%s\n", buf);
+ printf("Execute manually saveenv for persistent storage.\n");
return 0;
}
* Compare the values of the found entry in the
* list with the valid values which are stored
* in the inventory eeprom. If they are equal
- * store the values in environment variables
- * and save the environment.
- * This can only happen once for the lifetime
- * of a board, because once saved the function
- * will never reach the while loop.
+ * set the values in environment variables.
*/
if ((bid == ivmbid) && (hwkey == ivmhwkey)) {
char buf[10];
setenv("boardid", buf);
sprintf(buf, "%lx", hwkey);
setenv("hwkey", buf);
- saveenv();
}
} /* end while( ! found ) */
}
printf("boardid=0x%3lX, hwkey=%ld\n", envbid, envhwkey);
rc = 0; /* match */
} else {
- printf("Error: env bId=0x%3lX, hwKey=%ld\n", envbid, envhwkey);
+ printf("Error: env boardid=0x%3lX, hwkey=%ld\n", envbid,
+ envhwkey);
printf(" IVM bId=0x%3lX, hwKey=%ld\n", ivmbid, ivmhwkey);
rc = 1; /* don't match */
}
int ethernet_present(void);
int ivm_read_eeprom(void);
-void set_pin(int state, unsigned long mask);
int set_km_env(void);
int fdt_set_node_and_value(void *blob,
void **var);
int i2c_soft_read_pin(void);
+int i2c_make_abort(void);
#endif /* __KEYMILE_COMMON_H */
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hush.h>
+#include <i2c.h>
+#include "common.h"
+
+int ivm_calc_crc(unsigned char *buf, int len)
+{
+ const unsigned short crc_tab[16] = {
+ 0x0000, 0xCC01, 0xD801, 0x1400,
+ 0xF001, 0x3C00, 0x2800, 0xE401,
+ 0xA001, 0x6C00, 0x7800, 0xB401,
+ 0x5000, 0x9C01, 0x8801, 0x4400};
+
+ unsigned short crc = 0; /* final result */
+ unsigned short r1 = 0; /* temp */
+ unsigned char byte = 0; /* input buffer */
+ int i;
+
+ /* calculate CRC from array data */
+ for (i = 0; i < len; i++) {
+ byte = buf[i];
+
+ /* lower 4 bits */
+ r1 = crc_tab[crc & 0xF];
+ crc = ((crc) >> 4) & 0x0FFF;
+ crc = crc ^ r1 ^ crc_tab[byte & 0xF];
+
+ /* upper 4 bits */
+ r1 = crc_tab[crc & 0xF];
+ crc = (crc >> 4) & 0x0FFF;
+ crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF];
+ }
+ return crc;
+}
+
+static int ivm_set_value(char *name, char *value)
+{
+ char tempbuf[256];
+
+ if (value != NULL) {
+ sprintf(tempbuf, "%s=%s", name, value);
+ return set_local_var(tempbuf, 0);
+ } else {
+ unset_local_var(name);
+ }
+ return 0;
+}
+
+static int ivm_get_value(unsigned char *buf, int len, char *name, int off,
+ int check)
+{
+ unsigned short val;
+ unsigned char valbuf[30];
+
+ if ((buf[off + 0] != buf[off + 2]) &&
+ (buf[off + 2] != buf[off + 4])) {
+ printf("%s Error corrupted %s\n", __func__, name);
+ val = -1;
+ } else {
+ val = buf[off + 0] + (buf[off + 1] << 8);
+ if ((val == 0) && (check == 1))
+ val = -1;
+ }
+ sprintf((char *)valbuf, "%x", val);
+ ivm_set_value(name, (char *)valbuf);
+ return val;
+}
+
+#define INV_BLOCKSIZE 0x100
+#define INV_DATAADDRESS 0x21
+#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3)
+
+#define IVM_POS_SHORT_TEXT 0
+#define IVM_POS_MANU_ID 1
+#define IVM_POS_MANU_SERIAL 2
+#define IVM_POS_PART_NUMBER 3
+#define IVM_POS_BUILD_STATE 4
+#define IVM_POS_SUPPLIER_PART_NUMBER 5
+#define IVM_POS_DELIVERY_DATE 6
+#define IVM_POS_SUPPLIER_BUILD_STATE 7
+#define IVM_POS_CUSTOMER_ID 8
+#define IVM_POS_CUSTOMER_PROD_ID 9
+#define IVM_POS_HISTORY 10
+#define IVM_POS_SYMBOL_ONLY 11
+
+static char convert_char(char c)
+{
+ return (c < ' ' || c > '~') ? '.' : c;
+}
+
+static int ivm_findinventorystring(int type,
+ unsigned char *const string,
+ unsigned long maxlen,
+ unsigned char *buf)
+{
+ int xcode = 0;
+ unsigned long cr = 0;
+ unsigned long addr = INV_DATAADDRESS;
+ unsigned long size = 0;
+ unsigned long nr = type;
+ int stop = 0; /* stop on semicolon */
+
+ memset(string, '\0', maxlen);
+ switch (type) {
+ case IVM_POS_SYMBOL_ONLY:
+ nr = 0;
+ stop = 1;
+ break;
+ default:
+ nr = type;
+ stop = 0;
+ }
+
+ /* Look for the requested number of CR. */
+ while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
+ if ((buf[addr] == '\r'))
+ cr++;
+ addr++;
+ }
+
+ /*
+ * the expected number of CR was found until the end of the IVM
+ * content --> fill string
+ */
+ if (addr < INVENTORYDATASIZE) {
+ /* Copy the IVM string in the corresponding string */
+ for (; (buf[addr] != '\r') &&
+ ((buf[addr] != ';') || (!stop)) &&
+ (size < (maxlen - 1) &&
+ (addr < INVENTORYDATASIZE)); addr++) {
+ size += sprintf((char *)string + size, "%c",
+ convert_char (buf[addr]));
+ }
+
+ /*
+ * copy phase is done: check if everything is ok. If not,
+ * the inventory data is most probably corrupted: tell
+ * the world there is a problem!
+ */
+ if (addr == INVENTORYDATASIZE) {
+ xcode = -1;
+ printf("Error end of string not found\n");
+ } else if ((size >= (maxlen - 1)) &&
+ (buf[addr] != '\r')) {
+ xcode = -1;
+ printf("string too long till next CR\n");
+ }
+ } else {
+ /*
+ * some CR are missing...
+ * the inventory data is most probably corrupted
+ */
+ xcode = -1;
+ printf("not enough cr found\n");
+ }
+ return xcode;
+}
+
+#define GET_STRING(name, which, len) \
+ if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \
+ ivm_set_value(name, (char *)valbuf); \
+ }
+
+static int ivm_check_crc(unsigned char *buf, int block)
+{
+ unsigned long crc;
+ unsigned long crceeprom;
+
+ crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
+ crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
+ buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
+ if (crc != crceeprom) {
+ if (block == 0)
+ printf("Error CRC Block: %d EEprom: calculated: \
+ %lx EEprom: %lx\n", block, crc, crceeprom);
+ return -1;
+ }
+ return 0;
+}
+
+static int ivm_analyze_block2(unsigned char *buf, int len)
+{
+ unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+ unsigned long count;
+
+ /* IVM_MacAddress */
+ sprintf((char *)valbuf, "%pM", buf);
+ ivm_set_value("IVM_MacAddress", (char *)valbuf);
+ /* if an offset is defined, add it */
+#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
+ if (CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) {
+ unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
+
+ val += CONFIG_PIGGY_MAC_ADRESS_OFFSET;
+ buf[4] = (val >> 16) & 0xff;
+ buf[5] = (val >> 8) & 0xff;
+ buf[6] = val & 0xff;
+ sprintf((char *)valbuf, "%pM", buf);
+ }
+#endif
+ setenv((char *)"ethaddr", (char *)valbuf);
+
+ /* IVM_MacCount */
+ count = (buf[10] << 24) +
+ (buf[11] << 16) +
+ (buf[12] << 8) +
+ buf[13];
+ if (count == 0xffffffff)
+ count = 1;
+ sprintf((char *)valbuf, "%lx", count);
+ ivm_set_value("IVM_MacCount", (char *)valbuf);
+ return 0;
+}
+
+int ivm_analyze_eeprom(unsigned char *buf, int len)
+{
+ unsigned short val;
+ unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+ unsigned char *tmp;
+
+ if (ivm_check_crc(buf, 0) != 0)
+ return -1;
+
+ ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+ "IVM_BoardId", 0, 1);
+ val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+ "IVM_HWKey", 6, 1);
+ if (val != 0xffff) {
+ sprintf((char *)valbuf, "%x", ((val / 100) % 10));
+ ivm_set_value("IVM_HWVariant", (char *)valbuf);
+ sprintf((char *)valbuf, "%x", (val % 100));
+ ivm_set_value("IVM_HWVersion", (char *)valbuf);
+ }
+ ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+ "IVM_Functions", 12, 0);
+
+ GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
+ GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
+ tmp = (unsigned char *) getenv("IVM_DeviceName");
+ if (tmp) {
+ int len = strlen((char *)tmp);
+ int i = 0;
+
+ while (i < len) {
+ if (tmp[i] == ';') {
+ ivm_set_value("IVM_ShortText",
+ (char *)&tmp[i + 1]);
+ break;
+ }
+ i++;
+ }
+ if (i >= len)
+ ivm_set_value("IVM_ShortText", NULL);
+ } else {
+ ivm_set_value("IVM_ShortText", NULL);
+ }
+ GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
+ GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
+ GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32)
+ GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32)
+ GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32)
+ GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32)
+ GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32)
+ GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
+ GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
+
+ if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
+ return 0;
+ ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2],
+ CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
+
+ return 0;
+}
+
+int ivm_read_eeprom(void)
+{
+#if defined(CONFIG_I2C_MUX)
+ I2C_MUX_DEVICE *dev = NULL;
+#endif
+ uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+ uchar *buf;
+ unsigned long dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
+ int ret;
+
+#if defined(CONFIG_I2C_MUX)
+ /* First init the Bus, select the Bus */
+#if defined(CONFIG_SYS_I2C_IVM_BUS)
+ dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS);
+#else
+ buf = (unsigned char *) getenv("EEprom_ivm");
+ if (buf != NULL)
+ dev = i2c_mux_ident_muxstring(buf);
+#endif
+ if (dev == NULL) {
+ printf("Error couldnt add Bus for IVM\n");
+ return -1;
+ }
+ i2c_set_bus_num(dev->busid);
+#endif
+
+ buf = (unsigned char *) getenv("EEprom_ivm_addr");
+ if (buf != NULL) {
+ ret = strict_strtoul((char *)buf, 16, &dev_addr);
+ if (ret != 0)
+ return -3;
+ }
+
+ /* add deblocking here */
+ i2c_make_abort();
+
+ ret = i2c_read(dev_addr, 0, 1, i2c_buffer,
+ CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ if (ret != 0) {
+ printf("Error reading EEprom\n");
+ return -2;
+ }
+
+ return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _KEYMILE_HDLC_ENET_H_
-#define _KEYMILE_HDLC_ENET_H_
-
-/* Unfortuantely, we have do this to get the flag defines in the cbd_t */
-#ifdef CONFIG_KM8XX
-#include <commproc.h>
-#endif
-#ifdef CONFIG_MGCOGE
-#include <mpc8260.h>
-#include <asm/cpm_8260.h>
-#endif
-
-/*
- * Defines for the ICN protocol used for communication over HDLC
- * on the backplane between MGSUVDs and MGCOGEs.
- */
-
-/*
- * MAC which is reserved for communication (0x00 - 0xff in the last byte,
- * which is the slot number)
- */
-
-/*
- * A DLL frame looks like this:
- * 8 bit | 8 bit | 8 bit | 8 bit | n * 8 bit| 16 bit| 8 bit
- * opening| destination| source | application| data | FCS | closing
- * flag | address | address| | | | flag
- * (HW) (APP) (APP) (APP) (APP) (HW) (HW)
- */
-
-/*
- * The opening flag, the FCS and the closing flag are set by the hardware so
- * they are not reflected in this struct.
- */
-struct icn_hdr {
- unsigned char dest_addr;
- unsigned char src_addr;
- unsigned char application;
-} __attribute__((packed));
-
-#define ICNHDR_LEN (sizeof(struct icn_hdr))
-#define CRC_LEN (sizeof(short))
-/* bytes to remove from packet before sending it upstream */
-#define REMOVE (ICNHDR_LEN + CRC_LEN)
-
-struct icn_frame {
- struct icn_hdr hdr;
- unsigned char data[0]; /* a place holder */
-} __attribute__((packed));
-
-/* Address field */
-#define HDLC_UUA 0x00 /* Unicast Unit Address */
-#define HDLC_UUA_MASK 0x3f /* the last 6 bits contain the slot number */
-#define SET_HDLC_UUA(x) ((HDLC_UUA | ((x) & HDLC_UUA_MASK)))
-#define HDLC_UACUA 0x7f /* Unicast Active Control Unit Address */
-#define HDLC_BCAST 0xff /* broadcast */
-
-/* Application field */
-#define MGS_UUSP 0x00
-#define MGS_UREP 0x01
-#define MGS_IUP 0x02
-#define MGS_UTA 0x03
-#define MGS_MDS 0x04
-#define MGS_ITIME 0x05
-/* added by DENX */
-#define MGS_NETCONS 0x06 /* netconsole */
-#define MGS_TFTP 0x07
-
-/* Useful defines for buffer sizes, etc. */
-#define HDLC_PKTBUFSRX 32
-#define MAX_FRAME_LENGTH 1500 /* ethernet frame size */
- /* 14 + 28 */
-#define INET_HDR_SIZE (ETHER_HDR_SIZE + IP_HDR_SIZE)
-#define INET_HDR_ALIGN (((INET_HDR_SIZE + PKTALIGN - 1) / PKTALIGN) * PKTALIGN)
-/* INET_HDR_SIZE is stripped off */
-#define PKT_MAXBLR_SIZE (MAX_FRAME_LENGTH + INET_HDR_ALIGN)
-
-/*
- * It is too slow to read always the port numbers and IP addresses from the
- * string variables.
- * cachedNumbers is meant to cache it.
- * THIS IS ONLY A SPEED IMPROVEMENT!
- */
-enum {
- IP_ADDR = 0, /* getenv_IPaddr("serverip"); */
- IP_SERVER, /* getenv_IPaddr("ipaddr"); */
- TFTP_SRC_PORT, /* simple_strtol(getenv("tftpsrcp"), NULL, 10); */
- TFTP_DST_PORT, /* simple_strtol(getenv("tftpdstp"), NULL, 10); */
- NETCONS_PORT, /* simple_strtol(getenv("ncip"), NULL, 10); */
- CACHEDNUMBERS
-};
-
-#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
-
-/* define this to create a test commend (htest) */
-#undef TEST_IT
-#ifdef TEST_IT
-/* have to save a copy of the eth_device for the test command's use */
-struct eth_device *seth;
-#endif
-/* define this for outputting of received packets */
-#undef TEST_RX
-/* define this for outputting of packets being sent */
-#undef TEST_TX
-
-#endif /* _KEYMILE_HDLC_ENET_H_ */
LIB = $(obj)lib$(BOARD).o
-COBJS := $(BOARD).o ../common/common.o
+COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
}
#ifdef CONFIG_MGCOGE3NE
+static void set_pin(int state, unsigned long mask);
+
/*
* For mgcoge3ne boards, the mgcoge3un control is controlled from
* a GPIO line on the PPC CPU. If bobcatreset is set the line
return 0;
}
+#define SDA_MASK 0x00010000
+#define SCL_MASK 0x00020000
+
+static void set_pin(int state, unsigned long mask)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ if (state)
+ setbits_be32(&iop->pdat, mask);
+ else
+ clrbits_be32(&iop->pdat, mask);
+
+ setbits_be32(&iop->pdir, mask);
+}
+
+static int get_pin(unsigned long mask)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ clrbits_be32(&iop->pdir, mask);
+ return 0 != (in_be32(&iop->pdat) & mask);
+}
+
+void set_sda(int state)
+{
+ set_pin(state, SDA_MASK);
+}
+
+void set_scl(int state)
+{
+ set_pin(state, SCL_MASK);
+}
+
+int get_sda(void)
+{
+ return get_pin(SDA_MASK);
+}
+
+int get_scl(void)
+{
+ return get_pin(SCL_MASK);
+}
+
+#if defined(CONFIG_HARD_I2C)
+static void setports(int gpio)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ if (gpio) {
+ clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+ clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
+ } else {
+ setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+ clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
+ setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
+ }
+}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void ft_board_setup(void *blob, bd_t *bd)
{
LIB = $(obj)lib$(BOARD).o
-COBJS += $(BOARD).o ../common/common.o
+COBJS += $(BOARD).o ../common/common.o ../common/ivm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
LIB = $(obj)lib$(BOARD).o
-COBJS := $(BOARD).o ../common/common.o
+COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
{
/* dram_init must store complete ramsize in gd->ram_size */
/* Fix this */
- gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
+ gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
kw_sdram_bs(0));
return 0;
}
-debug-common-env.txt
+These scripts are needed for our development usecases. Copy this directory
+into your tftp root directory to be able to use this scripts.
+cp -r <u-boot-repo>/board/keymile/scripts <your_tftp_root>/
+
+To load and configure these usecase, two environment variables in the u-boot
+default environment must be parsed:
+run develop : setup environment to configure for rootfs via nfs
+run ramfs : setup environment to configure for rootfs in ram
+
+Last change: 20.05.2011
+
+develop-common.txt
+============================
+This file defines variables for working with rootfs via nfs for powerpc and
+arm.
+
+develop-<arch>.txt
============================
-This file defines environment variables which are valid for powerpc boards
-and for arm boards.
+This file defines architecture specific variables for working with rootfs via
+nfs arm.
-addramfs: add phram device for the rootfilesysten in ram
-develop: for development, laod kernel via tftp and mount rootfs via NFS
-nfsargs: default arguments for nfs boot
-ramfs: load rootfilesystem in RAM kernel
-rootfsfile: loacation of the rootfs file for ramfs
-setramfspram: compute PRAM size for ramfs target
-setrootfsaddr: compute rootfilesystem address for phram
-tftpkernel: load a kernel with tftp into ram
-tftpramfs: load rootfs with tftp into ram
-debug-ppc-env.txt
+ramfs-common.txt
============================
-fdt_file: location of the dtb file on the tftp server
-tftpfdt: load dtb file and set fdt address
+This file defines variables for working with rootfs inside the ram for powerpc
+and arm.
-debug-arm-env.txt
+ramfs-<arch>.txt
============================
-tftpfdt: for arm only a dummy variable, because we have no fdt on arm
+This file defines architecture specific variables for working with rootfs inside
+ram.
+++ /dev/null
-debug_env_common=tftpboot 0x200000 scripts/debug-common-env.txt && env import -t 0x200000 ${filesize}
-tftpfdt=true
+++ /dev/null
-addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}"
-develop=setenv subbootcmds "tftpfdt tftpkernel nfsargs ${commonargs} boot " && setenv bootcmd 'run bootrunner' && setenv altbootcmd 'run bootcmd' && km_setboardid && saveenv && reset
-nfsargs=setenv bootargs ubi.mtd=ubi0 root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
-ramfs=setenv actual_bank -1 && setenv subbootcmds "tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs ${commonargs} addpanic addramfs boot " && setenv bootcmd 'run bootrunner' && setenv altbootcmd 'run bootcmd' && run setboardid && run setramfspram && run setpnvramaddr && saveenv && reset
-rootfsfile=${hostname}/rootfsImage
-setramfspram=setexpr value 0 + ${reservedpram} && setexpr value 0x${value} + ${rootfssize} && setexpr value 0x${value} + ${varsize} && setexpr value 0x${value} + ${pnvramsize} && setexpr value 0x${value} / 0x400 && setenv pram 0x${value}
-tftpkernel=tftpboot ${kernel_addr_r} ${hostname}/uImage && setenv actual_kernel_addr ${kernel_addr_r}
-tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage && setenv loadaddr
-setrootfsaddr=setexpr value ${pnvramsize} - ${rootfssize} && setenv rootfsaddr 0x${value}
+++ /dev/null
-debug_env_common=tftpboot 0x200000 scripts/debug-common-env.txt && env import -t 0x200000 ${filesize}
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb && setenv actual_fdt_addr ${fdt_addr_r}
--- /dev/null
+setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
+tftpfdt=true
--- /dev/null
+altbootcmd=run ${subbootcmds}
+bootcmd=run ${subbootcmds}
+configure=km_setboardid && saveenv && reset
+subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:/opt/eldk/${arch}
+tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage
--- /dev/null
+setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
+tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
--- /dev/null
+setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
+tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
--- /dev/null
+setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
+tftpfdt=true
--- /dev/null
+addramfs=setenv bootargs "${bootargs} mem=${rootfsaddr} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}"
+actual_bank=-1
+altbootcmd=run ${subbootcmds}
+bootcmd=run ${subbootcmds}
+subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
+configure=km_setboardid && run setramfspram && saveenv && reset
+setramfspram=setexpr value 0 + ${rootfssize} && setexpr value 0x${value} / 0x400 && setexpr value 0x${value} + ${pram} && setenv pram 0x${value}
+rootfsfile=${hostname}/rootfsImage
+setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
+tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage
+tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
--- /dev/null
+setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
+tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
--- /dev/null
+setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
+tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
ulong result;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
+ ulong start;
/* first look for protection bits */
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0)
{ /* not protected */
do
{
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
*addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
result = BIT_TIMEOUT;
ulong result;
int rc = ERR_OK;
int cflag, iflag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait until flash is ready */
do
{
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
*addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
result = BIT_TIMEOUT;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
#ifdef CONFIG_MXC_UART
- mx27_uart_init_pins();
+ mx27_uart1_init_pins();
#endif
#ifdef CONFIG_FEC_MXC
mx27_fec_init_pins();
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
#endif
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
QUAD_INIT (1)
QUAD_INIT (2)
QUAD_INIT (3)
+
+struct serial_device *default_serial_console(void)
+{
+ return ZOOM2_DEFAULT_SERIAL_DEVICE;
+}
#define S(a) #a
#define N(a) S(quad##a)
-#define U(a) S(UART##a)
#define QUAD_INIT(n) \
int quad_init_##n(void) \
struct serial_device zoom2_serial_device##n = \
{ \
N(n), \
- U(n), \
quad_init_##n, \
NULL, \
quad_setbrg_##n, \
ulong result, result1;
int iflag, prot, sect;
int rc = ERR_OK;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
sect, info->start[sect]);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *) (info->start[sect]);
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_STATUS_RESET;
result = BIT_TIMEOUT;
break;
ulong result;
int rc = ERR_OK;
int iflag;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_SUSPEND;
result = BIT_TIMEOUT;
break;
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
#define MV_MAX_ENV_ENTRY_LENGTH 64
#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
+#ifndef CONFIG_ENV_IS_NOWHERE
void mv_reset_environment(void)
{
int i;
saveenv();
}
+#endif
int mv_load_fpga(void)
{
return 0;
}
-int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);
return 0;
}
-int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);
return 0;
}
-int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);
{
int flag, sect, setup_offset = 0;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
(__u16) SECERASE_CMD;
/* wait some time */
- reset_timer_masked ();
- while (get_timer_masked () < 1000) {
+ start = get_timer(0);
+ while (get_timer(start) < 1000) {
}
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
while (flash_check_erase_amd (info->start[sect])) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("timeout!\n");
/* OOPS: reach timeout,
* try to reset chip
{
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*(__u16 *) (dest) & data) != data)
}
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
while (flash_check_write_amd (dest)) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
printf ("timeout! @ %08lX\n", dest);
/* OOPS: reach timeout,
* try to reset chip */
*
* Interrupt Transfers.
* --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
* of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ get_timer(0);
SF_NvmodeErase();
SF_NvmodeWrite();
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include "nm.h"
-
-#if defined(DEBUG)
-void show_sdram_registers(void)
-{
- u32 value;
-
- printf("SDRAM Controller Registers --\n");
- mfsdram(SDRAM0_CFG, value);
- printf(" SDRAM0_CFG : 0x%08x\n", value);
- mfsdram(SDRAM0_STATUS, value);
- printf(" SDRAM0_STATUS: 0x%08x\n", value);
- mfsdram(SDRAM0_B0CR, value);
- printf(" SDRAM0_B0CR : 0x%08x\n", value);
- mfsdram(SDRAM0_B1CR, value);
- printf(" SDRAM0_B1CR : 0x%08x\n", value);
- mfsdram(SDRAM0_TR, value);
- printf(" SDRAM0_TR : 0x%08x\n", value);
- mfsdram(SDRAM0_RTR, value);
- printf(" SDRAM0_RTR : 0x%08x\n", value);
-}
-#endif
-
-long int init_ppc405_sdram(unsigned int dram_size)
-{
-#ifdef DEBUG
- printf(__FUNCTION__);
-#endif
- /* disable memory controller */
- mtsdram(SDRAM0_CFG, 0x00000000);
-
- udelay (500);
-
- /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtsdram(SDRAM0_BESR0, 0xffffffff);
-
- /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtsdram(SDRAM0_BESR1, 0xffffffff);
-
- /* Clear SDRAM0_ECCCFG (disable ECC) */
- mtsdram(SDRAM0_ECCCFG, 0x00000000);
-
- /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtsdram(SDRAM0_ECCESR, 0xffffffff);
-
- /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
- */
- mtsdram(SDRAM0_TR, 0x008a4015);
-
- /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
- * and refresh timer
- */
- switch (dram_size >> 20) {
- case 32:
- mtsdram(SDRAM0_B0CR, 0x00062001);
- mtsdram(SDRAM0_RTR, 0x07F00000);
- break;
- case 64:
- mtsdram(SDRAM0_B0CR, 0x00084001);
- mtsdram(SDRAM0_RTR, 0x04100000);
- break;
- case 128:
- mtsdram(SDRAM0_B0CR, 0x000A4001);
- mtsdram(SDRAM0_RTR, 0x04100000);
- break;
- default:
- printf("Invalid memory size of %d MB given\n", dram_size >> 20);
- }
-
- /* Power management idle timer set to the default. */
- mtsdram(SDRAM0_PMIT, 0x07c00000);
-
- udelay (500);
-
- /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
- mtsdram(SDRAM0_CFG, 0x90800000);
-
-#ifdef DEBUG
- printf("%s: done\n", __FUNCTION__);
-#endif
- return dram_size;
-}
+++ /dev/null
-/*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-extern void hcu_led_set(u32 value);
-extern u32 get_serial_number(void);
-extern u32 hcu_get_slot(void);
-extern int board_with_pci(void);
-extern void nm_show_print(int generation, int index, int hw_capabilities);
-extern void set_params_for_sw_install(int install_requested, char *board_name );
-extern void common_misc_init_r(void);
-
-enum {
- /* HW_GENERATION_HCU1/2 is no longer supported */
- HW_GENERATION_HCU3 = 0x10,
- HW_GENERATION_HCU4 = 0x20,
- HW_GENERATION_HCU5 = 0x30,
- HW_GENERATION_MCU = 0x08,
- HW_GENERATION_MCU20 = 0x0a,
- HW_GENERATION_MCU25 = 0x09,
-};
-
-#ifdef CONFIG_405GP
-#if defined(DEBUG)
-void show_sdram_registers(void);
-#endif
-long int init_ppc405_sdram(unsigned int dram_size);
-#endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include "nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DEFAULT_ETH_ADDR "ethaddr"
-
-typedef struct {u8 id; char *name;} generation_info;
-
-generation_info generations[6] = {
- {HW_GENERATION_HCU3, "HCU3"},
- {HW_GENERATION_HCU4, "HCU4"},
- {HW_GENERATION_HCU5, "HCU5"},
- {HW_GENERATION_MCU, "MCU"},
- {HW_GENERATION_MCU20, "MCU20"},
- {HW_GENERATION_MCU25, "MCU25"},
-};
-
-void nm_show_print(int generation, int index, int hw_capabilities)
-{
- int j;
- char *generationName=0;
-
- /* reset ANSI terminal color mode */
- printf("\x1B""[0m""Netstal Maschinen AG: ");
- for (j=0; j < (sizeof(generations)/sizeof(generations[0])); j++) {
- if (generations[j].id == generation) {
- generationName = generations[j].name;
- break;
- }
- }
- printf("%s: index %d HW 0x%x\n", generationName, index, hw_capabilities);
- for (j = 0;j < 6; j++) {
- hcu_led_set(1 << j);
- udelay(200 * 1000);
- }
-}
-
-void set_params_for_sw_install(int install_requested, char *board_name )
-{
- if (install_requested) {
- char string[128];
-
- printf("\n\n%s SW-Installation: %d patching boot parameters\n",
- board_name, install_requested);
- setenv("bootdelay", "0");
- setenv("loadaddr", "0x01000000");
- setenv("serverip", "172.25.1.1");
- setenv("bootcmd", "run install");
- sprintf(string, "tftp ${loadaddr} admin/sw_on_hd; "
- "tftp ${loadaddr} installer/%s_sw_inst; "
- "run boot_sw_inst", board_name);
- setenv("install", string);
- sprintf(string, "setenv bootargs emac(0,0)c:%s/%s_sw_inst "
- "e=${ipaddr} h=${serverip} f=0x1000; "
- "bootvx ${loadaddr}%c",
- board_name, board_name, 0);
- setenv("boot_sw_inst", string);
- }
-}
-
-void common_misc_init_r(void)
-{
- IPaddr_t ipaddr;
- char *ipstring;
- uchar ethaddr[6];
-
- if (!eth_getenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr)) {
- /* Must be in sync with CONFIG_ETHADDR */
- u32 serial = get_serial_number();
- ethaddr[0] = 0x00;
- ethaddr[1] = 0x60;
- ethaddr[2] = 0x13;
- ethaddr[3] = (serial >> 16) & 0xff;
- ethaddr[4] = (serial >> 8) & 0xff;
- ethaddr[5] = hcu_get_slot();
- eth_setenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr);
- }
-
- /* IP-Adress update */
- ipstring = getenv("ipaddr");
- if (ipstring == 0)
- ipaddr = string_to_ip("172.25.1.99");
- else
- ipaddr = string_to_ip(ipstring);
- if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
- char tmp[22];
-
- ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
- ip_to_string (ipaddr, tmp);
- printf("%s: enforce %s\n", __FUNCTION__, tmp);
- setenv("ipaddr", tmp);
- saveenv();
- }
-}
+++ /dev/null
-#
-# (C) Copyright 2007-2008 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o \
- ../common/fixed_sdram.o \
- ../common/nm_bsp.o
-
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
-
-clean:
- rm -f $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-HCU4 Configuration Details
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xf4000000 - 0xf4000fff
-
-The 405GPr includes a 4K on-chip memory that can be placed however
-software chooses. I choose to place the memory at this address, to
-keep it out of the cachable areas.
-
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC405GPr
-chip.
-
-Chip-Select 2: Flash Memory
----------------------------
-
-0x70000000
-
-Chip-Select 3: CAN Interface
-----------------------------
-0x7800000
-
-
-Chip-Select 4: IMC-bus standard
--------------------------------
-
-Our IO-Bus (slow version)
-
-
-Chip-Select 5: IMC-bus fast (inactive)
---------------------------------------
-
-Our IO-Bus (fast, but not yet use)
-
-
-Memory Bank 1 -- SDRAM
--------------------------------------
-
-0x00000000 - 0x1ffffff # Default 32 MB
+++ /dev/null
-#
-# (C) Copyright 2005 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Netstal Maschinen AG: HCU4 boards
-#
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG -g
-endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/u-boot.h>
-#include "../common/nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
-#define HCU_SLOT_ADDRESS (0x7C000000 + 0x400000)
-#define HCU_DIGITAL_IO_REGISTER (0x7C000000 + 0x500000)
-#define HCU_SW_INSTALL_REQUESTED 0x10
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-
-/* Attention: If you want 1 microsecs times from the external oscillator
- * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
- * 0x00804051 causes problems with u-boot and linux!
- */
-#define CPC0_CR0_VALUE 0x0030103c
-#define CPC0_CR1_VALUE 0x00004051
-
-int board_early_init_f (void)
-{
- /*
- * Interrupt controller setup for the HCU4 board.
- * Note: IRQ 0-15 405GP internally generated; high; level sensitive
- * IRQ 16 405GP internally generated; low; level sensitive
- * IRQ 17-24 RESERVED/UNUSED
- * IRQ 31 (EXT IRQ 6) (unused)
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
- mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
- mtdcr(CPC0_ECR, 0x60606000);
- mtdcr(CPC0_EIRR, 0x7C000000);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init (void)
-{
- return board_early_init_f ();
-}
-#endif
-
-int sys_install_requested(void)
-{
- u16 ioValue = in_be16((u16 *)HCU_DIGITAL_IO_REGISTER);
- return (ioValue & HCU_SW_INSTALL_REQUESTED) != 0;
-}
-
-int checkboard (void)
-{
- u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
- u16 generation = boardVersReg & 0xf0;
- u16 index = boardVersReg & 0x0f;
-
- /* Cannot be done in board_early_init */
- mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
-
- /* Force /RTS to active. The board it not wired quite
- * correctly to use cts/rtc flow control, so just force the
- * /RST active and forget about it.
- */
- writeb (readb (0xef600404) | 0x03, 0xef600404);
- nm_show_print(generation, index, 0);
-
- return 0;
-}
-
-u32 hcu_led_get(void)
-{
- return (~(in_be32((u32 *)GPIO0_OR)) >> 23) & 0xff;
-}
-
-/*
- * hcu_led_set value to be placed into the LEDs (max 6 bit)
- */
-void hcu_led_set(u32 value)
-{
- u32 tmp = ~value;
-
- tmp = (tmp << 23) | 0x7FFFFF;
- out_be32((u32 *)GPIO0_OR, tmp);
-}
-
-/*
- * hcu_get_slot
- */
-u32 hcu_get_slot(void)
-{
- u16 slot = in_be16((u16 *)HCU_SLOT_ADDRESS);
- return slot & 0x7f;
-}
-
-/*
- * get_serial_number
- */
-u32 get_serial_number(void)
-{
- u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
-
- if (serial == 0xffffffff)
- return 0;
-
- return serial;
-}
-
-
-/*
- * misc_init_r.
- */
-
-int misc_init_r(void)
-{
- common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "hcu4" );
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- long dram_size = 0;
- u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
- u16 generation = boardVersReg & 0xf0;
- u16 index = boardVersReg & 0x0f;
-
- if (generation == HW_GENERATION_HCU3 && index < 0xf)
- dram_size = 32 << 20; /* 32 MB - RAM */
- else
- dram_size = 64 << 20; /* 64 MB - RAM */
- init_ppc405_sdram(dram_size);
-
-#ifdef DEBUG
- show_sdram_registers();
-#endif
-
- return dram_size;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
+++ /dev/null
-HCU5 configuration details and startup sequence
-
-(C) Copyright 2007 Netstal Maschinen AG
- Niklaus Giger (Niklaus.Giger@netstal.com)
-
-TODO:
------
-- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
- - Does not occur if both EMAC are connected
-- Fix RTS/CTS problem (HW?)
- CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
- Switching to interrupt driven serial input mode
-
-Caveats:
---------
-Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
-see hcu5.c.
-
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xe0010000- 0xe0013fff CONFIG_SYS_OCM_BASE
-The 440EPx includes a 16K on-chip memory that can be placed however
-software chooses.
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC440EPX
-chip.
-
-Chip-Select 2: Flash Memory
----------------------------
-
-Not used
-
-Chip-Select 3: CAN Interface
-----------------------------
-0xc800000: 2 Intel 82527 CAN-Controller
-
-
-Chip-Select 4: IMC-bus standard
--------------------------------
-
-0xcc00000: Netstal specific IO-Bus
-
-
-Chip-Select 5: IMC-bus fast (inactive)
---------------------------------------
-
-0xce00000: Netstal specific IO-Bus (fast, but not yet used)
-
-
-Memory Bank 1 -- DDR2
--------------------------------------
-
-0x00000000 - 0xfffffff # Default 256 MB
-
-PCI ??
-
-USB ??
-Only USB_STORAGE is enabled to load vxWorks
-from a memory stick.
-
-System-LEDs ??? (Analog zu HCU4 ???)
-
-Startup sequence
-----------------
-
-(arch/powerpc/cpu/ppc4xx/resetvec.S)
-depending on configs option
-call _start_440 _start_pci oder _start
-
-(arch/powerpc/cpu/ppc4xx/start.S)
-
-_start_440:
- initialize register like
- CCR0
- debug
- setup interrupt vectors
- configure cache regions
- clear and setup TLB
- enable internal RAM
- jump start_ram
- which in turn will jump to start
-_start:
- Clear and set up some registers.
- Debug setup
- Setup the internal SRAM
- Setup the stack in internal SRAM
- setup stack pointer (r1)
- setup GOT
- call cpu_init_f /* run low-level CPU init code (from Flash) */
-
- call cpu_init_f
- board_init_f: (arch/powerpc/lib\board.c)
- init_sequence defines a list of function to be called
- board_early_init_f: (board/netstal/hcu5/hcu5.c)
- We are using Bootstrap-Option A
- if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
- Setup the GPIO pins
- Setup the interrupt controller polarities, triggers, etc.
- Ethernet, PCI, USB enable
- setup BOOT FLASH (Chip timing)
- init_baudrate,
- serial_init
- checkcpu
- misc_init_f #ifdef
- init_func_i2c #ifdef
- post_init_f #ifdef
- init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
- (EYE function removed!!)
- test_dram call
-
- * Reserve memory at end of RAM for (top down in that order):
- * - kernel log buffer
- * - protected RAM
- * - LCD framebuffer
- * - monitor code
- * - board info struct
- Save local variables to board info struct
- call relocate_code() does not return
- relocate_code: (arch/powerpc/cpu/ppc4xx/start.S)
--------------------------------------------------------
-From now on our copy is in RAM and we will run from there,
- starting with board_init_r
--------------------------------------------------------
- board_init_r: (arch/powerpc/lib\board.c)
- setup bd function pointers
- trap_init
- flash_init: (board/netstal/hcu5/flash.c)
- /* setup for u-boot erase, update */
- setup bd flash info
- cpu_init_r: (arch/powerpc/cpu/ppc4xx/cpu_init.c)
- peripheral chip select in using defines like
- CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
- mem_malloc_init
- malloc_bin_reloc
- spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
- env_relocated
- misc_init_r(bd): (board/netstal/hcu5.c)
- ethaddr mit serial number ergänzen
- Then we will somehow go into the command loop
-
-Most of the HW specific code for the HCU5 may be found in
-include/configs/hcu5.h
-board/netstal/hcu5/*
-arch/powerpc/cpu/ppc4xx/*
-arch/powerpc/lib/*
-include/ppc440.h
-
-Drivers for serial etc are found under drivers/
-
-Don't ask question if you did not look at the README !!
-Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there.
+++ /dev/null
-#
-# (C) Copyright 2005 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Netstal Maschinen AG: HCU5 boards
-#
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG -g
-endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include <asm/io.h>
-#include <asm/4xx_pci.h>
-
-#include "../common/nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#undef BOOTSTRAP_OPTION_A_ACTIVE
-
-#define SDR0_CP440 0x0180
-
-#define SYSTEM_RESET 0x30000000
-#define CHIP_RESET 0x20000000
-
-#define SDR0_ECID0 0x0080
-#define SDR0_ECID1 0x0081
-#define SDR0_ECID2 0x0082
-#define SDR0_ECID3 0x0083
-
-#define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000)
-#define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000)
-#define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000)
-#define HCU_SW_INSTALL_REQUESTED 0x10
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-
-int board_early_init_f(void)
-{
-
-#ifdef BOOTSTRAP_OPTION_A_ACTIVE
- /* Booting with Bootstrap Option A
- * First boot, with CPR0_ICFG_RLI_MASK == 0
- * no we setup varios boot strapping register,
- * then we do reset the PPC440 using a chip reset
- * Unfortunately, we cannot use this option, as Nto1 is not set
- * with Bootstrap Option A and cannot be changed later on by SW
- * There are no other possible boostrap options with a 8 bit ROM
- * See Errata (Version 1.04) CHIP_9
- */
-
- u32 cpr0icfg;
- u32 dbcr;
-
- mfcpr(CPR0_ICFG, cpr0icfg);
- if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
- mtcpr(CPR0_MALD, 0x02000000);
- mtcpr(CPR0_OPBD, 0x02000000);
- mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
- mtcpr(CPR0_PLLC, 0x40000238);
- mtcpr(CPR0_PLLD, 0x01010414);
- mtcpr(CPR0_PRIMAD, 0x01000000);
- mtcpr(CPR0_PRIMBD, 0x01000000);
- mtcpr(CPR0_SPCID, 0x03000000);
- mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
- mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
- mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
-
- /*
- * Initiate system reset in debug control register DBCR
- */
- dbcr = mfspr(SPRN_DBCR0);
- mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
- }
- mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
-#endif
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xb8400000);
-
- /*
- * Setup the GPIO pins
- */
- out32(GPIO0_OR, 0x00000000);
- out32(GPIO0_TCR, 0x7C2FF1CF);
- out32(GPIO0_OSRL, 0x40055000);
- out32(GPIO0_OSRH, 0x00000000);
- out32(GPIO0_TSRL, 0x40055000);
- out32(GPIO0_TSRH, 0x00000400);
- out32(GPIO0_ISR1L, 0x40000000);
- out32(GPIO0_ISR1H, 0x00000000);
- out32(GPIO0_ISR2L, 0x00000000);
- out32(GPIO0_ISR2H, 0x00000000);
- out32(GPIO0_ISR3L, 0x00000000);
- out32(GPIO0_ISR3H, 0x00000000);
-
- out32(GPIO1_OR, 0x00000000);
- out32(GPIO1_TCR, 0xC6007FFF);
- out32(GPIO1_OSRL, 0x00140000);
- out32(GPIO1_OSRH, 0x00000000);
- out32(GPIO1_TSRL, 0x00000000);
- out32(GPIO1_TSRH, 0x00000000);
- out32(GPIO1_ISR1L, 0x05415555);
- out32(GPIO1_ISR1H, 0x40000000);
- out32(GPIO1_ISR2L, 0x00000000);
- out32(GPIO1_ISR2H, 0x00000000);
- out32(GPIO1_ISR3L, 0x00000000);
- out32(GPIO1_ISR3H, 0x00000000);
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
- mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
-
- /* setup BOOT FLASH */
- mtsdr(SDR0_CUST0, 0xC0082350);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init(void)
-{
- return board_early_init_f();
-}
-
-#endif
-
-int sys_install_requested(void)
-{
- u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
- return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
-}
-
-int checkboard(void)
-{
- u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
- u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
- u16 generation = in_be16(boardVersReg) & 0xf0;
- u16 index = in_be16(boardVersReg) & 0x0f;
- u32 ecid0, ecid1, ecid2, ecid3;
-
- nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
- mfsdr(SDR0_ECID0, ecid0);
- mfsdr(SDR0_ECID1, ecid1);
- mfsdr(SDR0_ECID2, ecid2);
- mfsdr(SDR0_ECID3, ecid3);
-
- printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
-
- return 0;
-}
-
-u32 hcu_led_get(void)
-{
- return in16(SYS_IO_ADDRESS) & 0x3f;
-}
-
-/*
- * hcu_led_set value to be placed into the LEDs (max 6 bit)
- */
-void hcu_led_set(u32 value)
-{
- out16(SYS_IO_ADDRESS, value);
-}
-
-/*
- * get_serial_number
- */
-u32 get_serial_number(void)
-{
- u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
-
- if (in_be32(serial) == 0xffffffff)
- return 0;
-
- return in_be32(serial);
-}
-
-
-/*
- * hcu_get_slot
- */
-u32 hcu_get_slot(void)
-{
- u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
- return in_be16(slot) & 0x7f;
-}
-
-
-/*
- * misc_init_r.
- */
-int misc_init_r(void)
-{
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-#endif
-
- /*
- * USB stuff...
- */
-
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
-
- /* An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
-
- /* To enable the USB 2.0 Device function through the UTMI interface */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /*clear resets*/
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "hcu5" );
- /* We cannot easily enable trace before, as there are other
- * routines messing around with sdr0_pfc1. And I do not need it.
- */
- if (mfspr(SPRN_DBCR0) & 0x80000000) {
- /* External debugger alive
- * enable trace facilty for Lauterbach
- * CCR0[DTB]=0 Enable broadcast of trace information
- * SDR0_PFC0[TRE] Trace signals are enabled instead of
- * GPIO49-63
- */
- mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
- mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
- }
- return 0;
-}
-#ifdef CONFIG_PCI
-int board_with_pci(void)
-{
- u32 reg;
-
- mfsdr(SDR0_PCI0, reg);
- return (reg & SDR0_PCI0_PAE_MASK);
-}
-
-/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- */
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- if (!board_with_pci()) { return 0; }
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SDR0_AMP1, addr);
- mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3A0_ACR);
- mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SDR0_AMP0, addr);
- mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4A0_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4A0_ACR, addr); /* Sequoia */
-
- /*
- * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
- * Workaround: Disable write pipelining to DDR SDRAM by setting
- * PLB4A0_ACR[WRP] = 0.
- */
- mtdcr(PLB4A0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
-
- /* Segment1 */
- mtdcr(PLB4A1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
-
- return board_with_pci();
-}
-
-/*
- * Override weak default pci_master_init()
- */
-void pci_master_init(struct pci_controller *hose)
-{
- if (!board_with_pci())
- return;
-
- __pci_master_init(hose);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
+++ /dev/null
-/*
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
- tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
- /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
- AC_RWX | SA_IG )
-
- /* TLB#2: TLB-entry for EBC */
- tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
-
- /*
- * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
- * off to use the speed up boot process. It is patched after relocation
- * to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
- AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- /* TLB#4: */
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
- AC_RW | SA_IG )
- /* TLB#5: */
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
- AC_RW | SA_IG )
- /* TLB#6: */
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
- AC_RW | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- /* TLB#7: */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
- AC_RWX | SA_IG )
-
- /*TLB-entry PCI registers*/
- /* TLB#8: */
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for peripherals */
- /* TLB#9: */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- /* CAN */
- /* TLB#10: */
- tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
-
- /* TLB#11: CPLD and IMC-Standard 32 MB */
- tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
-
- /* TLB#12: */
- tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
- AC_RWX | SA_IG )
-
- /* IMC-Fast 32 MB */
- /* TLB#13: */
- tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
- /* TLB#14: */
- tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
- AC_RWX | SA_IG )
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-
-void hcu_led_set(u32 value);
-void dcbz_area(u32 start_address, u32 num_bytes);
-
-#define ECC_RAM 0x03267F0B
-#define NO_ECC_RAM 0x00267F0B
-
-#define HCU_HW_SDRAM_CONFIG_MASK 0x7
-
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
- /* disable caching on DDR2 */
-
-void board_add_ram_info(int use_default)
-{
- PPC4xx_SYS_INFO board_cfg;
- u32 val;
-
- mfsdram(DDR0_22, val);
- val &= DDR0_22_CTRL_RAW_MASK;
- switch (val) {
- case DDR0_22_CTRL_RAW_ECC_DISABLE:
- puts(" (ECC disabled");
- break;
- case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
- puts(" (ECC check only");
- break;
- case DDR0_22_CTRL_RAW_NO_ECC_RAM:
- puts(" (no ECC ram");
- break;
- case DDR0_22_CTRL_RAW_ECC_ENABLE:
- puts(" (ECC enabled");
- break;
- }
-
- get_sys_info(&board_cfg);
- printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
-
- mfsdram(DDR0_03, val);
- val = DDR0_03_CASLAT_DECODE(val);
- printf(", CL%d)", val);
-}
-
-/*--------------------------------------------------------------------
- * wait_for_dlllock.
- *--------------------------------------------------------------------*/
-static int wait_for_dlllock(void)
-{
- unsigned long val;
- int wait = 0;
-
- /* -----------------------------------------------------------+
- * Wait for the DCC master delay line to finish calibration
- * ----------------------------------------------------------*/
- mtdcr(SDRAM0_CFGADDR, DDR0_17);
- val = DDR0_17_DLLLOCKREG_UNLOCKED;
-
- while (wait != 0xffff) {
- val = mfdcr(SDRAM0_CFGDATA);
- if ((val & DDR0_17_DLLLOCKREG_MASK) ==
- DDR0_17_DLLLOCKREG_LOCKED)
- /* dlllockreg bit on */
- return 0;
- else
- wait++;
- }
- debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
- debug("Waiting for dlllockreg bit to raise\n");
-
- return -1;
-}
-
-/***********************************************************************
- *
- * sdram_panic -- Panic if we cannot configure the sdram correctly
- *
- ************************************************************************/
-void sdram_panic(const char *reason)
-{
- printf("\n%s: reason %s", __FUNCTION__, reason);
- hcu_led_set(0xff);
- while (1) {
- }
- /* Never return */
-}
-
-#ifdef CONFIG_DDR_ECC
-void blank_string(int size)
-{
- int i;
-
- for (i=0; i<size; i++)
- putc('\b');
- for (i=0; i<size; i++)
- putc(' ');
- for (i=0; i<size; i++)
- putc('\b');
-}
-/*---------------------------------------------------------------------------+
- * program_ecc.
- *---------------------------------------------------------------------------*/
-static void program_ecc(unsigned long start_address, unsigned long num_bytes)
-{
- u32 val;
- char str[] = "ECC generation -";
-#if defined(CONFIG_PRAM)
- u32 *magicPtr;
- u32 magic;
-
- if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
- /* only if no external debugger is alive!
- * Check whether vxWorks is using EDR logging, if yes zero
- * also PostMortem and user reserved memory
- */
- magicPtr = (u32 *)(start_address + num_bytes -
- (CONFIG_PRAM*1024) + sizeof(u32));
- magic = in_be32(magicPtr);
- debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
- __FUNCTION__, CONFIG_PRAM,
- magicPtr, magic);
- if (magic == 0xbeefbabe) {
- printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
- num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
- }
- }
-#endif
-
- sync();
-
- puts(str);
-
- /* ECC bit set method for cached memory */
- /* Fast method, no noticeable delay */
- dcbz_area(start_address, num_bytes);
- /* Write modified dcache lines back to memory */
- clean_dcache_range(start_address, start_address + num_bytes);
- blank_string(strlen(str));
-
- /* Clear error status */
- mfsdram(DDR0_00, val);
- mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
- /*
- * Clear possible ECC errors
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
-
- /* Set 'int_mask' parameter to functionnal value */
- mfsdram(DDR0_01, val);
- mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
- DDR0_01_INT_MASK_ALL_OFF));
-
- return;
-}
-#endif
-
-
-/***********************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
- unsigned int dram_size = 0;
-
- mtsdram(DDR0_02, 0x00000000);
-
- /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02030602);
- mtsdram(DDR0_04, 0x0A020200);
- mtsdram(DDR0_05, 0x02020307);
- switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
- case 1:
- dram_size = 256 * 1024 * 1024 ;
- mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
- mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
- mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
- break;
- case 0:
- default:
- dram_size = 128 * 1024 * 1024 ;
- mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
- mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
- mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
- break;
- }
- mtsdram(DDR0_07, 0x00090100);
-
- /*
- * TCPD=200 cycles of clock input is required to lock the DLL.
- * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
- */
- mtsdram(DDR0_08, 0x02C80001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x1D000000);
- mtsdram(DDR0_18, 0x1D1D1D1D);
- mtsdram(DDR0_19, 0x1D1D1D1D);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
- mtsdram(DDR0_22, ECC_RAM);
-#else
- mtsdram(DDR0_22, NO_ECC_RAM);
-#endif
-
- mtsdram(DDR0_23, 0x00000000);
- mtsdram(DDR0_24, 0x01020001);
- mtsdram(DDR0_26, 0x2D930517);
- mtsdram(DDR0_27, 0x00008236);
- mtsdram(DDR0_28, 0x00000000);
- mtsdram(DDR0_31, 0x00000000);
- mtsdram(DDR0_42, 0x01000006);
- mtsdram(DDR0_44, 0x00000003);
- mtsdram(DDR0_02, 0x00000001);
- wait_for_dlllock();
- mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
-
- /*
- * Program tlb entries for this size (dynamic)
- */
- remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
- program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
-
- /*
- * Setup 2nd TLB with same physical address but different virtual
- * address with cache enabled. This is done for fast ECC generation.
- */
- program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
-
-#ifdef CONFIG_DDR_ECC
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
-#endif
-
- return (dram_size);
-}
+++ /dev/null
-MCU25 Configuration Details
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xf4000000 - 0xf4000fff
-
-The 405GPr includes a 4K on-chip memory that can be placed however
-software chooses. I choose to place the memory at this address, to
-keep it out of the cachable areas.
-
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC405GPr
-chip.
-
-Chip-Select 2: Flash Memory
----------------------------
-
-0x70000000
-
-Chip-Select 3: CAN Interface
-----------------------------
-0x7800000
-
-
-Chip-Select 4: IMC-bus standard
--------------------------------
-
-Our IO-Bus (slow version)
-
-
-Chip-Select 5: IMC-bus fast (inactive)
---------------------------------------
-
-Our IO-Bus (fast, but not yet use)
-
-
-Memory Bank 1 -- SDRAM
--------------------------------------
-
-0x00000000 - 0x2ffffff # Default 64 MB
+++ /dev/null
-#
-# (C) Copyright 2005 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Netstal Maschinen AG: MCU25 board
-#
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG -g
-endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/u-boot.h>
-#include "../common/nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MCU25_SLOT_ADDRESS (0x7A000000 + 0x0A)
-#define MCU25_DIGITAL_IO_REGISTER (0x7A000000 + 0xc0)
-
-#define MCU25_LED_REGISTER_ADDRESS (0x7C000000 + 0x10)
-#define MCU25_VERSIONS_REGISTER (0x7C000000 + 0x0C)
-#define MCU25_IO_CONFIGURATION (0x7C000000 + 0x0e)
-#define MCU_SW_INSTALL_REQUESTED 0x08
-
-#define SDRAM_LEN (32 << 20) /* 32 MB - RAM */
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-
-/* Attention: If you want 1 microsecs times from the external oscillator
- * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
- * 0x00804051 causes problems with u-boot and linux!
- */
-#define CPC0_CR0_VALUE 0x0007F03C
-#define CPC0_CR1_VALUE 0x00004051
-
-int board_early_init_f (void)
-{
- /* Documented in A-1171
- *
- * Interrupt controller setup for the MCU25 board.
- * Note: IRQ 0-15 405GP internally generated; high; level sensitive
- * IRQ 16 405GP internally generated; low; level sensitive
- * IRQ 17-24 RESERVED/UNUSED
- * IRQ 31 (EXT IRQ 6) (unused)
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
- mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
- mtdcr(CPC0_ECR, 0x60606000);
- mtdcr(CPC0_EIRR, 0x7C000000);
- out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR );
- out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);
- out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);
- mtspr(SPRN_CCR0, 0x00700000);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init (void)
-{
- return board_early_init_f ();
-}
-#endif
-
-int sys_install_requested(void)
-{
- u16 ioValue = in_be16((u16 *)MCU25_DIGITAL_IO_REGISTER);
- return (ioValue & MCU_SW_INSTALL_REQUESTED) != 0;
-}
-
-int checkboard (void)
-{
- u16 boardVersReg = in_be16((u16 *)MCU25_VERSIONS_REGISTER);
- u16 hwConfig = in_be16((u16 *)MCU25_IO_CONFIGURATION);
- u16 generation = boardVersReg & 0x0f;
- u16 index = boardVersReg & 0xf0;
-
- /* Cannot be done in board_early_init */
- mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
-
- /* Force /RTS to active. The board it not wired quite
- * correctly to use cts/rtc flow control, so just force the
- * /RST active and forget about it.
- */
- writeb (readb (0xef600404) | 0x03, 0xef600404);
- nm_show_print(generation, index, hwConfig);
- return 0;
-}
-
-u32 hcu_led_get(void)
-{
- return in_be16((u16 *)MCU25_LED_REGISTER_ADDRESS) & 0x3ff;
-}
-
-/*
- * hcu_led_set value to be placed into the LEDs (max 6 bit)
- */
-void hcu_led_set(u32 value)
-{
- out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value);
-}
-
-/*
- * hcu_get_slot
- */
-u32 hcu_get_slot(void)
-{
- u16 slot = in_be16((u16 *)MCU25_SLOT_ADDRESS);
- return slot & 0x7f;
-}
-
-/*
- * get_serial_number
- */
-u32 get_serial_number(void)
-{
- u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
-
- if (serial == 0xffffffff)
- return 0;
-
- return serial;
-}
-
-
-/*
- * misc_init_r.
- */
-
-int misc_init_r(void)
-{
- common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "mcu25" );
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- unsigned int dram_size = 64*1024*1024;
- init_ppc405_sdram(dram_size);
-
-#ifdef DEBUG
- show_sdram_registers();
-#endif
-
- return dram_size;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
-
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
flash_unprotect_sectors (addr);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
#include <asm/arch/uart.h>
#include "board.h"
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
const struct tegra2_sysinfo sysinfo = {
*/
int timer_init(void)
{
- reset_timer();
return 0;
}
}
/*
+ * Routine: clock_init_mmc
+ * Description: init the PLL and clocks for the SDMMC controllers
+ */
+static void clock_init_mmc(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* Do the SDMMC resets/clock enables */
+
+ /* Assert Reset to SDMMC4 */
+ reg = readl(&clkrst->crc_rst_dev_l);
+ reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */
+ writel(reg, &clkrst->crc_rst_dev_l);
+
+ /* Enable clk to SDMMC4 */
+ reg = readl(&clkrst->crc_clk_out_enb_l);
+ reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */
+ writel(reg, &clkrst->crc_clk_out_enb_l);
+
+ /* Enable pllp_out0 to SDMMC4 */
+ reg = readl(&clkrst->crc_clk_src_sdmmc4);
+ reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
+ reg |= (10 << 1); /* n-1, 11-1 shl 1 */
+ writel(reg, &clkrst->crc_clk_src_sdmmc4);
+
+ /*
+ * As per the Tegra2 TRM, section 5.3.4:
+ * 'Wait 2 us for the clock to flush through the pipe/logic'
+ */
+ udelay(2);
+
+ /* De-assert reset to SDMMC4 */
+ reg = readl(&clkrst->crc_rst_dev_l);
+ reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */
+ writel(reg, &clkrst->crc_rst_dev_l);
+
+ /* Assert Reset to SDMMC3 */
+ reg = readl(&clkrst->crc_rst_dev_u);
+ reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */
+ writel(reg, &clkrst->crc_rst_dev_u);
+
+ /* Enable clk to SDMMC3 */
+ reg = readl(&clkrst->crc_clk_out_enb_u);
+ reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */
+ writel(reg, &clkrst->crc_clk_out_enb_u);
+
+ /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
+ reg = readl(&clkrst->crc_clk_src_sdmmc3);
+ reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
+ reg |= (10 << 1); /* n-1, 11-1 shl 1 */
+ writel(reg, &clkrst->crc_clk_src_sdmmc3);
+
+ /* wait for 2us */
+ udelay(2);
+
+ /* De-assert reset to SDMMC3 */
+ reg = readl(&clkrst->crc_rst_dev_u);
+ reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */
+ writel(reg, &clkrst->crc_rst_dev_u);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+ struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 reg;
+
+ /* SDMMC4 */
+ /* config 2, x8 on 2nd set of pins */
+ reg = readl(&pmt->pmt_ctl_a);
+ reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */
+ writel(reg, &pmt->pmt_ctl_a);
+ reg = readl(&pmt->pmt_ctl_b);
+ reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */
+ writel(reg, &pmt->pmt_ctl_b);
+ reg = readl(&pmt->pmt_ctl_d);
+ reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
+ writel(reg, &pmt->pmt_ctl_d);
+
+ reg = readl(&pmt->pmt_tri_a);
+ reg &= ~Z_ATB; /* Z_ATB = normal (0) */
+ reg &= ~Z_GMA; /* Z_GMA = normal (0) */
+ writel(reg, &pmt->pmt_tri_a);
+ reg = readl(&pmt->pmt_tri_b);
+ reg &= ~Z_GME; /* Z_GME = normal (0) */
+ writel(reg, &pmt->pmt_tri_b);
+
+ /* SDMMC3 */
+ /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
+ reg = readl(&pmt->pmt_ctl_d);
+ reg &= 0xFFFF03FF;
+ reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */
+ reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */
+ reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
+ writel(reg, &pmt->pmt_ctl_d);
+
+ reg = readl(&pmt->pmt_tri_b);
+ reg &= ~Z_SDC; /* Z_SDC = normal (0) */
+ reg &= ~Z_SDD; /* Z_SDD = normal (0) */
+ writel(reg, &pmt->pmt_tri_b);
+ reg = readl(&pmt->pmt_tri_d);
+ reg &= ~Z_SDB; /* Z_SDB = normal (0) */
+ writel(reg, &pmt->pmt_tri_d);
+}
+
+/*
* Routine: clock_init
* Description: Do individual peripheral clock reset/enables
*/
return 0;
}
+
+#ifdef CONFIG_TEGRA2_MMC
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ debug("board_mmc_init called\n");
+ /* Enable clocks, muxes, etc. for SDMMC controllers */
+ clock_init_mmc();
+ pin_mux_mmc();
+
+ debug("board_mmc_init: init eMMC\n");
+ /* init dev 0, eMMC chip, with 4-bit bus */
+ tegra2_mmc_init(0, 4);
+
+ debug("board_mmc_init: init SD slot\n");
+ /* init dev 1, SD slot, with 4-bit bus */
+ tegra2_mmc_init(1, 4);
+
+ return 0;
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ debug("board_mmc_getcd called\n");
+ /*
+ * Hard-code CD presence for now. Need to add GPIO inputs
+ * for Seaboard & Harmony (& Kaen/Aebl/Wario?)
+ */
+ *cd = 1;
+ return 0;
+}
+#endif
void pinmux_init(void);
void gpio_init(void);
void gpio_config_uart(void);
+int tegra2_mmc_init(int dev_index, int bus_width);
#endif /* BOARD_H */
#
# Check the U-Boot Image with a SHA1 checksum
-ALL += $(obj)u-boot.sha1
+ALL-y += $(obj)u-boot.sha1
PLATFORM_CPPFLAGS += -DCONFIG_440=1
FPWV *addr;
int flag, prot, sect;
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong now, last;
+ ulong start, now, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- reset_timer_masked ();
-
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
- reset_timer_masked ();
+ start = get_timer(0);
last = 0;
addr = (FPWV *) (info->start[sect]);
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
if ((now =
- get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
int flag;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
if (flag)
enable_interrupts ();
- reset_timer_masked ();
+ start = get_timer(0);
/* data polling for D7 */
while (res == 0
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00F000F0; /* reset bank */
res = 1;
}
{
int flag;
int res = 0; /* result, assume success */
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
if (flag)
enable_interrupts ();
- reset_timer_masked ();
+ start = get_timer(0);
while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00B000B0; /* Suspend program */
res = 1;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
ulong result, result1;
int iflag, prot, sect;
int rc = ERR_OK;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
sect, info->start[sect]);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *) (info->start[sect]);
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_STATUS_RESET;
result = BIT_TIMEOUT;
break;
ulong result;
int rc = ERR_OK;
int iflag;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_SUSPEND;
result = BIT_TIMEOUT;
break;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip;
+ ulong start;
/* first look for protection bits */
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
result = *addr;
/* check timeout */
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip = TMO;
int rc = ERR_OK;
int cflag, iflag;
int chip;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ get_timer(start);
/* wait until flash is ready */
chip = 0;
result = *addr;
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip = ERR | TMO;
break;
}
dram_size = fixed_sdram ();
#endif
- puts (" DDR: ");
+ debug (" DDR: ");
return dram_size;
}
+++ /dev/null
-#
-# This config file is used for compilation of scb93328 sources
-#
-# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-CONFIG_SYS_TEXT_BASE = 0x08f00000
static int flash_ready (ulong timeout)
{
int ok = 1;
+ ulong start;
- reset_timer_masked ();
+ start = get_timer(0);
while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
FLASH_CMD (CFI_INTEL_SR_READY)) {
- if (get_timer_masked () > timeout && timeout != 0) {
+ if (get_timer(start) > timeout && timeout != 0) {
ok = 0;
break;
}
int dram_init (void)
{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)SCB9328_SDRAM_1,
+ SCB9328_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
- gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
- gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
- gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
- gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
- gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
- gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE;
-#endif
- return 0;
}
/**
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1, chip2;
+ ulong start;
/* first look for protection bits */
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0)
{ /* not protected */
result = *addr;
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
int rc = ERR_OK;
int cflag, iflag;
int chip1, chip2;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait until flash is ready */
chip1 = chip2 = 0;
result = *addr;
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
chip1 = ERR | TMO;
break;
CONFIG_SYS_TEXT_BASE = 0x00700000
-ALL += $(obj)u-boot.img
+ALL-y += $(obj)u-boot.img
# Environment variables in NAND
ifeq ($(ENV),NAND)
CONFIG_SYS_TEXT_BASE = 0x00700000
-ALL += $(obj)u-boot.img
+ALL-y += $(obj)u-boot.img
# Environment variables in NAND
ifeq ($(ENV),NAND)
CONFIG_SYS_TEXT_BASE = 0x00700000
-ALL += $(obj)u-boot.img
+ALL-y += $(obj)u-boot.img
# Environment variables in NAND
ifeq ($(ENV),NAND)
CONFIG_SYS_TEXT_BASE = 0x00700000
-ALL += $(obj)u-boot.img
+ALL-y += $(obj)u-boot.img
# Environment variables in NAND
ifeq ($(ENV),NAND)
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#endif
}
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup (blob, bd);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
int
board_early_init_f(void)
{
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
#
-# (C) Copyright 2007-2008 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
+# (c) 2010 Graf-Syteco, Matthias Weisser
+# <weisserm@arcor.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o \
- sdram.o \
- ../common/nm_bsp.o
-SOBJS = init.o
+COBJS-y += zmx25.o
+SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
-all: $(LIB) $(SOBJS)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/macro.h>
+#include <asm/arch/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+/*
+ * clocks
+ */
+.macro init_clocks
+
+ /* disable clock output */
+ write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
+ write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
+
+ /*
+ * enable all implemented clocks in all three
+ * clock control registers
+ */
+ write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
+ write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
+ write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
+
+ /* Devide NAND clock by 32 */
+ write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
+.endm
+
+/*
+ * sdram controller init
+ */
+.macro init_lpddr
+ ldr r0, =IMX_ESDRAMC_BASE
+ ldr r2, =IMX_SDRAM_BANK0_BASE
+
+ /*
+ * reset SDRAM controller
+ * then wait for initialization to complete
+ */
+ ldr r1, =(1 << 1) | (1 << 2)
+ str r1, [r0, #ESDRAMC_ESDMISC]
+1: ldr r3, [r0, #ESDRAMC_ESDMISC]
+ tst r3, #(1 << 31)
+ beq 1b
+ ldr r1, =(1 << 2)
+ str r1, [r0, #ESDRAMC_ESDMISC]
+
+ ldr r1, =0x002a7420
+ str r1, [r0, #ESDRAMC_ESDCFG0]
+
+ /* control | precharge */
+ ldr r1, =0x92216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+ /* dram command encoded in address */
+ str r1, [r2, #0x400]
+
+ /* auto refresh */
+ ldr r1, =0xa2216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+ /* read dram twice to auto refresh */
+ ldr r3, [r2]
+ ldr r3, [r2]
+
+ /* control | load mode */
+ ldr r1, =0xb2216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+
+ /* mode register of lpddram */
+ strb r1, [r2, #0x33]
+
+ /* extended mode register of lpddrram */
+ ldr r2, =0x81000000
+ strb r1, [r2]
+
+ /* control | normal */
+ ldr r1, =0x82216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ init_aips
+ init_max
+ init_clocks
+ init_lpddr
+ mov pc, lr
--- /dev/null
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Based on tx25.c:
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on imx27lite.c:
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ * And:
+ * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mxc_gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx25-pinmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init()
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ struct iomuxc_pad_input_select *inputselect;
+ u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+ u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
+ u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
+ u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
+ u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
+ u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
+
+ icache_enable();
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+ inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
+
+ /* Setup of core volatage selection pin to run at 1.4V */
+ writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1);
+
+ /* Setup of input daisy chains for SD card pins*/
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
+
+ /* Setup of digital output for USB power and OC */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1);
+
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN);
+
+ /* Setup of digital output control pins */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
+
+ writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
+ writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
+
+ /* Switch both output drivers off */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT);
+
+ /* Setup of key input pin GPIO2[29]*/
+ writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
+ writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN);
+
+ /* Setup of status LED outputs */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
+
+ /* Switch both LEDs off */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT);
+
+ /* Setup of CAN1 and CAN2 signals */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
+
+ /* Setup of input daisy chains for CAN signals*/
+ writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
+ writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
+
+ /* Setup of I2C3 signals */
+ writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
+ writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
+
+ /* Setup of input daisy chains for I2C3 signals*/
+ writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
+ writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
+
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_ZMX25;
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ const char *e;
+
+#ifdef CONFIG_FEC_MXC
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
+ u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
+
+ /*
+ * fec pin init is generic
+ */
+ mx25_fec_init_pins();
+
+ /*
+ * Set up LAN-RESET and FEC_RX_ERR
+ *
+ * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
+ * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
+ */
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+
+ writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
+ writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
+
+ /* assert PHY reset (low) */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT);
+
+ udelay(5000);
+
+ /* deassert PHY reset */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1);
+
+ udelay(5000);
+#endif
+
+ e = getenv("gs_base_board");
+ if (e != NULL) {
+ if (strcmp(e, "G283") == 0) {
+ int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29));
+
+ if (key) {
+ /* Switch on both LEDs to inidcate boot mode */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
+
+ setenv("preboot", "run gs_slow_boot");
+ } else
+ setenv("preboot", "run gs_fast_boot");
+ }
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
-
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
flash_unprotect_sectors (addr);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
-
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
flash_unprotect_sectors (addr);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
/* Local functions */
static int detect_num_flash_banks(void);
-static long int get_ddr_bank_size(short cs, volatile long *base);
+static long int get_ddr_bank_size(short cs, long *base);
static void set_cs_bounds(short cs, long base, long size);
static void set_cs_config(short cs, long config);
static void set_ddr_config(void);
debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs,
- (volatile long*)(CONFIG_SYS_DDR_BASE + size));
+ (long *)(CONFIG_SYS_DDR_BASE + size));
size += bank_size;
debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
/*************************************************************************
* Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
*/
-static long int get_ddr_bank_size(short cs, volatile long *base)
+static long int get_ddr_bank_size(short cs, long *base)
{
/* This array lists all valid DDR SDRAM configurations, with
* Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
udelay (1000);
#endif /* CONFIG_TQM8548 */
+ /*
+ * get_ram_size() depends on having tlbs for the DDR, but they are
+ * not yet setup because we don't know the size. Set up a temp
+ * mapping and delete it when done.
+ */
+ setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
for (i = 0; i < N_DDR_CS_CONF; i++) {
ddr->cs0_config = ddr_cs_conf[i].reg;
break;
}
}
+ clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
#ifdef CONFIG_TQM8548
if (i < N_DDR_CS_CONF) {
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
int rc = 0;
vu_long *addr = (vu_long *)(info->start[sector]);
int flag = disable_interrupts();
+ ulong start;
*addr = INTEL_CLEAR; /* Clear status register */
if (prot) { /* Set sector lock bit */
*addr = INTEL_CONFIRM; /* clear */
}
- reset_timer_masked ();
+ start = get_timer(0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
printf("Flash lock bit operation timed out\n");
rc = 1;
break;
{
if (info->protect[i])
{
- reset_timer_masked ();
+ start = get_timer(0);
addr = (vu_long *)(info->start[i]);
*addr = INTEL_LOCKBIT; /* Sector lock bit */
*addr = INTEL_PROTECT; /* set */
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
{
- if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
{
printf("Flash lock bit operation timed out\n");
rc = 1;
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
sheevaplug arm arm926ejs - Marvell kirkwood
dockstar arm arm926ejs - Seagate kirkwood
jadecpu arm arm926ejs jadecpu syteco mb86r0x
+zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
nhk8815 arm arm926ejs nhk8815 st nomadik
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
ca9x4_ct_vxp arm armv7 vexpress armltd
-efikamx arm armv7 efikamx - mx5 mx51evk:IMX_CONFIG=board/efikamx/imximage.cfg
+efikamx arm armv7 efikamx - mx5 efikamx:IMX_CONFIG=board/efikamx/imximage.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg
mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
BC3450 powerpc mpc5xxx bc3450
canmb powerpc mpc5xxx
cm5200 powerpc mpc5xxx
-digsy_mtc powerpc mpc5xxx digsy_mtc
-digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000
-digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc - - digsy_mtc:DIGSY_REV5
-digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5
+digsy_mtc powerpc mpc5xxx digsy_mtc intercontrol
+digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000
+digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:DIGSY_REV5
+digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5
galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200
galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT
icecube_5200 powerpc mpc5xxx icecube - - IceCube
P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND
P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD
P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH
+P2041RDB powerpc mpc85xx p2041rdb freescale
+P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P3041DS powerpc mpc85xx corenet_ds freescale
P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
MIP405 powerpc ppc4xx mip405 mpl
MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
PIP405 powerpc ppc4xx pip405 mpl
-hcu4 powerpc ppc4xx hcu4 netstal
-hcu5 powerpc ppc4xx hcu5 netstal
-mcu25 powerpc ppc4xx mcu25 netstal
alpr powerpc ppc4xx - prodrive
p3p440 powerpc ppc4xx - prodrive
KAREF powerpc ppc4xx karef sandburst
LIB = $(obj)libcommon.o
# core
+ifndef CONFIG_SPL_BUILD
COBJS-y += main.o
-COBJS-y += console.o
COBJS-y += command.o
COBJS-y += dlmalloc.o
COBJS-y += exports.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
COBJS-y += image.o
-COBJS-y += memsize.o
COBJS-y += s_record.o
COBJS-$(CONFIG_SERIAL_MULTI) += serial.o
-COBJS-y += stdio.o
COBJS-y += xyzModem.o
# core command
COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
+COBJS-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
ifdef CONFIG_FPGA
COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
COBJS-$(CONFIG_UPDATE_TFTP) += update.o
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
+endif
+
+COBJS-y += console.o
+COBJS-y += memsize.o
+COBJS-y += stdio.o
COBJS := $(sort $(COBJS-y))
return 1;
}
+int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
+{
+ const char *ep = getenv("autostart");
+
+ if (ep && !strcmp(ep, "yes")) {
+ char *local_args[2];
+ local_args[0] = (char *)cmd;
+ local_args[1] = NULL;
+ printf("Automatic boot of image at addr 0x%08lX ...\n", load_addr);
+ return do_bootm(cmdtp, 0, 1, local_args);
+ }
+
+ return 0;
+}
+
/**
* image_get_kernel - verify legacy format kernel image
* @img_addr: in RAM address of the legacy format image to be verified
*/
#include <common.h>
#include <command.h>
+#include <linux/compiler.h>
-static int on_off (const char *);
+static int parse_argv(const char *);
+
+void __weak flush_icache(void)
+{
+ /* please define arch specific flush_icache */
+ puts("No arch specific flush_icache available!\n");
+}
int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
case 2: /* on / off */
- switch (on_off(argv[1])) {
+ switch (parse_argv(argv[1])) {
case 0: icache_disable();
break;
case 1: icache_enable ();
break;
+ case 2: flush_icache();
+ break;
}
/* FALL TROUGH */
case 1: /* get status */
return 0;
}
+void __weak flush_dcache(void)
+{
+ puts("No arch specific flush_dcache available!\n");
+ /* please define arch specific flush_dcache */
+}
+
int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
case 2: /* on / off */
- switch (on_off(argv[1])) {
+ switch (parse_argv(argv[1])) {
case 0: dcache_disable();
break;
case 1: dcache_enable ();
break;
+ case 2: flush_dcache();
+ break;
}
/* FALL TROUGH */
case 1: /* get status */
}
-static int on_off (const char *s)
+static int parse_argv(const char *s)
{
- if (strcmp(s, "on") == 0) {
+ if (strcmp(s, "flush") == 0) {
+ return (2);
+ } else if (strcmp(s, "on") == 0) {
return (1);
} else if (strcmp(s, "off") == 0) {
return (0);
U_BOOT_CMD(
icache, 2, 1, do_icache,
"enable or disable instruction cache",
- "[on, off]\n"
- " - enable or disable instruction cache"
+ "[on, off, flush]\n"
+ " - enable, disable, or flush instruction cache"
);
U_BOOT_CMD(
dcache, 2, 1, do_dcache,
"enable or disable data cache",
- "[on, off]\n"
- " - enable or disable data (writethrough) cache"
+ "[on, off, flush]\n"
+ " - enable, disable, or flush data (writethrough) cache"
);
/*
* For a FRAM device there is no limit on the number of the
- * bytes that can be ccessed with the single read or write
+ * bytes that can be accessed with the single read or write
* operation.
*/
#if !defined(CONFIG_SYS_I2C_FRAM)
image_header_t *hdr; /* used for fdc boot */
unsigned char boot_drive;
int i,nrofblk;
- char *ep;
- int rcode = 0;
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
#endif
/* Loading ok, update default load address */
load_addr = addr;
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
- char *local_args[2];
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
-
- do_bootm (cmdtp, 0, 1, local_args);
- rcode ++;
- }
- return rcode;
+ return bootm_maybe_autostart(cmdtp, argv[0]);
}
U_BOOT_CMD(
char *name;
char *ep;
int size;
- int rcode = 0;
char buf [12];
int drive = CONFIG_SYS_FDC_DRIVE_NUMBER;
printf("Floppy DOS load complete: %d bytes loaded to 0x%lx\n",
size, load_addr);
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
- char *local_args[2];
- local_args[0] = argv[0];
- local_args[1] = NULL;
- printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr);
- rcode = do_bootm (cmdtp, 0, 1, local_args);
- }
- return rcode;
+ return bootm_maybe_autostart(cmdtp, argv[0]);
}
/*-----------------------------------------------------------------------------
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Andreas Pretzsch, carpe noctem engineering, apr@cn-eng.de
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if !defined(CONFIG_UPDATE_TFTP)
+#error "CONFIG_UPDATE_TFTP required"
+#endif
+
+extern int update_tftp(ulong addr);
+
+static int do_fitupd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr = 0UL;
+
+ if (argc > 2)
+ return cmd_usage(cmdtp);
+
+ if (argc == 2)
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ return update_tftp(addr);
+}
+
+U_BOOT_CMD(fitupd, 2, 0, do_fitupd,
+ "update from FIT image",
+ "[addr]\n"
+ "\t- run update from FIT image at addr\n"
+ "\t or from tftp 'updatefile'"
+);
} /* bank */
}
if (!found) {
- /* error, addres not in flash */
+ /* error, address not in flash */
printf("Error: end address (0x%08lx) not in flash!\n", *addr);
return 1;
}
{
const void *fit_hdr = (const void *)fpga_data;
int noffset;
- void *fit_data;
+ const void *fit_data;
if (fit_uname == NULL) {
puts ("No FIT subimage unit name\n");
return tmp;
}
-/* Analyses a Muxstring and sends immediately the
- Commands to the Muxes. Runs from Flash.
+/* Analyses a Muxstring and immediately sends the
+ commands to the muxes. Runs from flash.
*/
int i2c_mux_ident_muxstring_f (uchar *buf)
{
ulong addr, cnt;
disk_partition_t info;
image_header_t *hdr;
- int rcode = 0;
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
#endif
load_addr = addr;
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
- char *local_args[2];
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
-
- do_bootm (cmdtp, 0, 1, local_args);
- rcode = 1;
- }
- return rcode;
+ return bootm_maybe_autostart(cmdtp, argv[0]);
}
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t * ide_get_dev(int dev)
{
return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
}
+#endif
#ifdef CONFIG_IDE_8xx_DIRECT
mac, 3, 1, do_mac,
"display and program the system ID and MAC addresses in EEPROM",
"[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n"
- "read\n"
- " - show content of EEPROM\n"
+ "mac read\n"
+ " - read EEPROM content into memory\n"
"mac save\n"
" - save to the EEPROM\n"
"mac id\n"
addr = simple_strtoul(argv[1], NULL, 16);
len = simple_strtoul(argv[2], NULL, 16);
- md5((unsigned char *) addr, len, output);
+ md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5);
printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1);
for (i = 0; i < 16; i++)
printf("%02x", output[i]);
length = simple_strtoul (argv[2], NULL, 16);
- crc = crc32 (0, (const uchar *) addr, length);
+ crc = crc32_wd (0, (const uchar *) addr, length, CHUNKSZ_CRC32);
printf ("CRC32 for %08lx ... %08lx ==> %08lx\n",
addr, addr + length - 1, crc);
addr += base_address;
length = simple_strtoul(*av++, NULL, 16);
- crc = crc32(0, (const uchar *) addr, length);
+ crc = crc32_wd (0, (const uchar *) addr, length, CHUNKSZ_CRC32);
if (!verify) {
printf ("CRC32 for %08lx ... %08lx ==> %08lx\n",
);
#else /* !CONFIG_GENERIC_MMC */
+enum mmc_state {
+ MMC_INVALID,
+ MMC_READ,
+ MMC_WRITE,
+ MMC_ERASE,
+};
static void print_mmcinfo(struct mmc *mmc)
{
printf("Device: %s\n", mmc->name);
int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ enum mmc_state state;
+
if (argc < 2)
return cmd_usage(cmdtp);
}
mmc->has_init = 0;
- mmc_init(mmc);
- return 0;
+ if (mmc_init(mmc))
+ return 1;
+ else
+ return 0;
} else if (strncmp(argv[1], "part", 4) == 0) {
block_dev_desc_t *mmc_dev;
struct mmc *mmc = find_mmc_device(curr_device);
curr_device, mmc->part_num);
return 0;
- } else if (strcmp(argv[1], "read") == 0) {
- void *addr = (void *)simple_strtoul(argv[2], NULL, 16);
- u32 cnt = simple_strtoul(argv[4], NULL, 16);
- u32 n;
- u32 blk = simple_strtoul(argv[3], NULL, 16);
- struct mmc *mmc = find_mmc_device(curr_device);
-
- if (!mmc) {
- printf("no mmc device at slot %x\n", curr_device);
- return 1;
- }
-
- printf("\nMMC read: dev # %d, block # %d, count %d ... ",
- curr_device, blk, cnt);
-
- mmc_init(mmc);
-
- n = mmc->block_dev.block_read(curr_device, blk, cnt, addr);
+ }
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512); /* FIXME */
+ if (strcmp(argv[1], "read") == 0)
+ state = MMC_READ;
+ else if (strcmp(argv[1], "write") == 0)
+ state = MMC_WRITE;
+ else if (strcmp(argv[1], "erase") == 0)
+ state = MMC_ERASE;
+ else
+ state = MMC_INVALID;
- printf("%d blocks read: %s\n",
- n, (n==cnt) ? "OK" : "ERROR");
- return (n == cnt) ? 0 : 1;
- } else if (strcmp(argv[1], "write") == 0) {
- void *addr = (void *)simple_strtoul(argv[2], NULL, 16);
- u32 cnt = simple_strtoul(argv[4], NULL, 16);
- u32 n;
+ if (state != MMC_INVALID) {
struct mmc *mmc = find_mmc_device(curr_device);
+ int idx = 2;
+ u32 blk, cnt, n;
+ void *addr;
- int blk = simple_strtoul(argv[3], NULL, 16);
+ if (state != MMC_ERASE) {
+ addr = (void *)simple_strtoul(argv[idx], NULL, 16);
+ ++idx;
+ } else
+ addr = 0;
+ blk = simple_strtoul(argv[idx], NULL, 16);
+ cnt = simple_strtoul(argv[idx + 1], NULL, 16);
if (!mmc) {
printf("no mmc device at slot %x\n", curr_device);
return 1;
}
- printf("\nMMC write: dev # %d, block # %d, count %d ... ",
- curr_device, blk, cnt);
+ printf("\nMMC %s: dev # %d, block # %d, count %d ... ",
+ argv[1], curr_device, blk, cnt);
mmc_init(mmc);
- n = mmc->block_dev.block_write(curr_device, blk, cnt, addr);
+ switch (state) {
+ case MMC_READ:
+ n = mmc->block_dev.block_read(curr_device, blk,
+ cnt, addr);
+ /* flush cache after read */
+ flush_cache((ulong)addr, cnt * 512); /* FIXME */
+ break;
+ case MMC_WRITE:
+ n = mmc->block_dev.block_write(curr_device, blk,
+ cnt, addr);
+ break;
+ case MMC_ERASE:
+ n = mmc->block_dev.block_erase(curr_device, blk, cnt);
+ break;
+ default:
+ BUG();
+ }
- printf("%d blocks written: %s\n",
- n, (n == cnt) ? "OK" : "ERROR");
+ printf("%d blocks %s: %s\n",
+ n, argv[1], (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? 0 : 1;
}
"MMC sub system",
"read addr blk# cnt\n"
"mmc write addr blk# cnt\n"
+ "mmc erase blk# cnt\n"
"mmc rescan\n"
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
ulong offset, ulong addr, char *cmd)
{
int r;
- char *ep, *s;
+ char *s;
size_t cnt;
image_header_t *hdr;
#if defined(CONFIG_FIT)
load_addr = addr;
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
- char *local_args[2];
-
- local_args[0] = cmd;
- local_args[1] = NULL;
-
- printf("Automatic boot of image at addr 0x%08lx ...\n", addr);
-
- do_bootm(cmdtp, 0, 1, local_args);
- return 1;
- }
- return 0;
+ return bootm_maybe_autostart(cmdtp, cmd);
}
int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
/* flush cache */
flush_cache(load_addr, size);
- /* Loading ok, check if we should attempt an auto-start */
- if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
- char *local_args[2];
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lX ...\n",
- load_addr);
- show_boot_progress (82);
- rcode = do_bootm (cmdtp, 0, 1, local_args);
- }
+ show_boot_progress(82);
+ rcode = bootm_maybe_autostart(cmdtp, argv[0]);
if (rcode < 0)
show_boot_progress (-83);
return 0;
}
-int setenv(char *varname, char *varvalue)
+int setenv(const char *varname, const char *varvalue)
{
- char * const argv[4] = { "setenv", varname, varvalue, NULL };
+ const char * const argv[4] = { "setenv", varname, varvalue, NULL };
+
if ((varvalue == NULL) || (varvalue[0] == '\0'))
- return _do_env_set(0, 2, argv);
+ return _do_env_set(0, 2, (char * const *)argv);
else
- return _do_env_set(0, 3, argv);
+ return _do_env_set(0, 3, (char * const *)argv);
}
int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
* return address of storage for that variable,
* or NULL if not found
*/
-char *getenv(char *name)
+char *getenv(const char *name)
{
if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
ENTRY e, *ep;
/*
* Look up variable from environment for restricted C runtime env.
*/
-int getenv_f(char *name, char *buf, unsigned len)
+int getenv_f(const char *name, char *buf, unsigned len)
{
int i, nxt;
}
int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t *sata_get_dev(int dev)
{
return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
}
+#endif
int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#define SCSI_VEND_ID 0x10b9
#define SCSI_DEV_ID 0x5288
-#else
+#elif !defined(CONFIG_SCSI_AHCI_PLAT)
#error no scsi device defined
#endif
scsi_curr_dev = -1;
}
-
+#ifdef CONFIG_PCI
void scsi_init(void)
{
int busdevfunc;
scsi_low_level_init(busdevfunc);
scsi_scan(1);
}
+#endif
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t * scsi_get_dev(int dev)
{
return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
}
-
+#endif
/******************************************************************************
* scsi boot command intepreter. Derived from diskboot
ulong addr, cnt;
disk_partition_t info;
image_header_t *hdr;
- int rcode = 0;
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
#endif
flush_cache (addr, (cnt+1)*info.blksz);
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
- char *local_args[2];
- local_args[0] = argv[0];
- local_args[1] = NULL;
- printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
- rcode = do_bootm (cmdtp, 0, 1, local_args);
- }
- return rcode;
+ return bootm_maybe_autostart(cmdtp, argv[0]);
}
/*********************************************************************************
addr = simple_strtoul(argv[1], NULL, 16);
len = simple_strtoul(argv[2], NULL, 16);
- sha1_csum((unsigned char *) addr, len, output);
+ sha1_csum_wd((unsigned char *) addr, len, output, CHUNKSZ_SHA1);
printf("SHA1 for %08lx ... %08lx ==> ", addr, addr + len - 1);
for (i = 0; i < 20; i++)
printf("%02x", output[i]);
{
char *boot_device = NULL;
char *ep;
- int dev, part = 1, rcode;
+ int dev, part = 1;
ulong addr, cnt;
disk_partition_t info;
image_header_t *hdr;
flush_cache(addr, (cnt+1)*info.blksz);
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
- char *local_args[2];
- local_args[0] = argv[0];
- local_args[1] = NULL;
- printf("Automatic boot of image at addr 0x%08lX ...\n", addr);
- rcode = do_bootm(cmdtp, 0, 1, local_args);
- return rcode;
- }
- return 0;
+ return bootm_maybe_autostart(cmdtp, argv[0]);
}
#endif /* CONFIG_USB_STORAGE */
#include <common.h>
#include <command.h>
#include <version.h>
+#include <linux/compiler.h>
-extern char version_string[];
+const char __weak version_string[] = U_BOOT_VERSION_STRING;
int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
memmove ((char *) dest, (char *)data, len);
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
break;
+#ifdef CONFIG_GZIP
case IH_COMP_GZIP:
printf (" Uncompressing part %d ... ", part);
if (gunzip ((void *) dest, unc_len,
return 1;
}
break;
+#endif
#if defined(CONFIG_BZIP2)
case IH_COMP_BZIP2:
{
return find_cmd_tbl(cmd, &__u_boot_cmd_start, len);
}
-int cmd_usage(cmd_tbl_t *cmdtp)
+int cmd_usage(const cmd_tbl_t *cmdtp)
{
printf("%s - %s\n\n", cmdtp->name, cmdtp->usage);
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
-uchar default_environment[] = {
+const uchar default_environment[] = {
#ifdef CONFIG_BOOTARGS
"bootargs=" CONFIG_BOOTARGS "\0"
#endif
return (c);
}
-uchar *env_get_addr (int index)
+const uchar *env_get_addr (int index)
{
if (gd->env_valid)
return (uchar *)(gd->env_addr + index);
* Generate embedded environment table
* inside U-Boot image, if needed.
*/
-#if defined(ENV_IS_EMBEDDED)
+#if defined(ENV_IS_EMBEDDED) || defined(CONFIG_BUILD_ENVCRC)
/*
* Only put the environment in it's own section when we are building
* U-Boot proper. The host based program "tools/envcrc" does not need
static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1;
#endif /* CONFIG_ENV_ADDR_REDUND */
-extern uchar default_environment[];
+extern const uchar default_environment[];
uchar env_get_char_spec(int index)
return phandle + 1;
}
+/*
+ * fdt_create_phandle: Create a phandle property for the given node
+ *
+ * @fdt: ptr to device tree
+ * @nodeoffset: node to update
+ * @phandle: phandle value to set (must be unique)
+*/
+int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle)
+{
+ int ret;
+
+#ifdef DEBUG
+ int off = fdt_node_offset_by_phandle(fdt, phandle);
+
+ if ((off >= 0) && (off != nodeoffset)) {
+ char buf[64];
+
+ fdt_get_path(fdt, nodeoffset, buf, sizeof(buf));
+ printf("Trying to update node %s with phandle %u ",
+ buf, phandle);
+
+ fdt_get_path(fdt, off, buf, sizeof(buf));
+ printf("that already exists in node %s.\n", buf);
+ return -FDT_ERR_BADPHANDLE;
+ }
+#endif
+
+ ret = fdt_setprop_cell(fdt, nodeoffset, "phandle", phandle);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * For now, also set the deprecated "linux,phandle" property, so that we
+ * don't break older kernels.
+ */
+ ret = fdt_setprop_cell(fdt, nodeoffset, "linux,phandle", phandle);
+
+ return ret;
+}
+
#if defined(CONFIG_VIDEO)
int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf)
{
return ret;
}
#endif
+
+/*
+ * Verify the physical address of device tree node for a given alias
+ *
+ * This function locates the device tree node of a given alias, and then
+ * verifies that the physical address of that device matches the given
+ * parameter. It displays a message if there is a mismatch.
+ *
+ * Returns 1 on success, 0 on failure
+ */
+int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr)
+{
+ const char *path;
+ const u32 *reg;
+ int node, len;
+ u64 dt_addr;
+
+ path = fdt_getprop(fdt, anode, alias, NULL);
+ if (!path) {
+ /* If there's no such alias, then it's not a failure */
+ return 1;
+ }
+
+ node = fdt_path_offset(fdt, path);
+ if (node < 0) {
+ printf("Warning: device tree alias '%s' points to invalid "
+ "node %s.\n", alias, path);
+ return 0;
+ }
+
+ reg = fdt_getprop(fdt, node, "reg", &len);
+ if (!reg) {
+ printf("Warning: device tree node '%s' has no address.\n",
+ path);
+ return 0;
+ }
+
+ dt_addr = fdt_translate_address(fdt, node, reg);
+ if (addr != dt_addr) {
+ printf("Warning: U-Boot configured device %s at address %llx,\n"
+ " but the device tree has it address %llx.\n",
+ alias, addr, dt_addr);
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Returns the base address of an SOC or PCI node
+ */
+u64 fdt_get_base_address(void *fdt, int node)
+{
+ int size;
+ u32 naddr;
+ const u32 *prop;
+
+ prop = fdt_getprop(fdt, node, "#address-cells", &size);
+ if (prop && size == 4)
+ naddr = *prop;
+ else
+ naddr = 2;
+
+ prop = fdt_getprop(fdt, node, "ranges", &size);
+
+ return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0;
+}
{ IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", },
{ IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",},
{ IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",},
+ { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",},
{ -1, "", "", },
};
{
void *fdt_blob = *of_flat_tree;
void *of_start = 0;
+ char *fdt_high;
ulong of_len = 0;
int err;
+ int disable_relocation = 0;
/* nothing to do */
if (*of_size == 0)
/* position on a 4K boundary before the alloc_current */
/* Pad the FDT by a specified amount */
of_len = *of_size + CONFIG_SYS_FDT_PAD;
- of_start = (void *)(unsigned long)lmb_alloc_base(lmb, of_len, 0x1000,
- getenv_bootm_mapsize() + getenv_bootm_low());
+
+ /* If fdt_high is set use it to select the relocation address */
+ fdt_high = getenv("fdt_high");
+ if (fdt_high) {
+ void *desired_addr = (void *)simple_strtoul(fdt_high, NULL, 16);
+
+ if (((ulong) desired_addr) == ~0UL) {
+ /* All ones means use fdt in place */
+ desired_addr = fdt_blob;
+ disable_relocation = 1;
+ }
+ if (desired_addr) {
+ of_start =
+ (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+ ((ulong)
+ desired_addr)
+ + of_len);
+ if (desired_addr && of_start != desired_addr) {
+ puts("Failed using fdt_high value for Device Tree");
+ goto error;
+ }
+ } else {
+ of_start =
+ (void *)(ulong) lmb_alloc(lmb, of_len, 0x1000);
+ }
+ } else {
+ of_start =
+ (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+ getenv_bootm_mapsize()
+ + getenv_bootm_low());
+ }
if (of_start == 0) {
puts("device tree - allocation error\n");
goto error;
}
- debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n",
- fdt_blob, fdt_blob + *of_size - 1, of_len, of_len);
+ if (disable_relocation) {
+ /* We assume there is space after the existing fdt to use for padding */
+ fdt_set_totalsize(of_start, of_len);
+ printf(" Using Device Tree in place at %p, end %p\n",
+ of_start, of_start + of_len - 1);
+ } else {
+ debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n",
+ fdt_blob, fdt_blob + *of_size - 1, of_len, of_len);
- printf (" Loading Device Tree to %p, end %p ... ",
- of_start, of_start + of_len - 1);
+ printf (" Loading Device Tree to %p, end %p ... ",
+ of_start, of_start + of_len - 1);
- err = fdt_open_into (fdt_blob, of_start, of_len);
- if (err != 0) {
- fdt_error ("fdt move failed");
- goto error;
+ err = fdt_open_into (fdt_blob, of_start, of_len);
+ if (err != 0) {
+ fdt_error ("fdt move failed");
+ goto error;
+ }
+ puts ("OK\n");
}
- puts ("OK\n");
*of_flat_tree = of_start;
*of_size = of_len;
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <version.h>
#ifdef CONFIG_MODEM_SUPPORT
#include <malloc.h> /* for free() prototype */
#endif
void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
#if defined(CONFIG_UPDATE_TFTP)
-void update_tftp (void);
+int update_tftp (ulong addr);
#endif /* CONFIG_UPDATE_TFTP */
#define MAX_DELAY_STOP_STR 32
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
-static int abortboot(int);
-#endif
-
#undef DEBUG_PARSER
char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */
*/
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
# if defined(CONFIG_AUTOBOOT_KEYED)
-static __inline__ int abortboot(int bootdelay)
+static inline int abortboot(int bootdelay)
{
int abort = 0;
uint64_t etime = endtick(bootdelay);
static int menukey = 0;
#endif
-static __inline__ int abortboot(int bootdelay)
+static inline int abortboot(int bootdelay)
{
int abort = 0;
#ifdef CONFIG_VERSION_VARIABLE
{
- extern char version_string[];
-
setenv ("ver", version_string); /* set version variable */
}
#endif /* CONFIG_VERSION_VARIABLE */
#endif /* CONFIG_PREBOOT */
#if defined(CONFIG_UPDATE_TFTP)
- update_tftp ();
+ update_tftp (0UL);
#endif /* CONFIG_UPDATE_TFTP */
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
# ifdef CONFIG_MENUKEY
if (menukey == CONFIG_MENUKEY) {
- s = getenv("menucmd");
- if (s) {
+ s = getenv("menucmd");
+ if (s) {
# ifndef CONFIG_SYS_HUSH_PARSER
- run_command (s, 0);
+ run_command(s, 0);
# else
- parse_string_outer(s, FLAG_PARSE_SEMICOLON |
- FLAG_EXIT_FROM_LOOP);
+ parse_string_outer(s, FLAG_PARSE_SEMICOLON |
+ FLAG_EXIT_FROM_LOOP);
# endif
- }
+ }
}
#endif /* CONFIG_MENUKEY */
#endif /* CONFIG_BOOTDELAY */
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*/
-long get_ram_size(volatile long *base, long maxsize)
+long get_ram_size(long *base, long maxsize)
{
volatile long *addr;
long save[32];
{
struct mii_dev *new_dev;
struct legacy_mii_dev *ldev;
- unsigned int name_len;
+
+ BUG_ON(strlen(name) >= MDIO_NAME_LEN);
/* check if we have unique name */
new_dev = miiphy_get_dev_by_name(name);
}
/* allocate memory */
- name_len = strlen(name);
- if (name_len > MDIO_NAME_LEN - 1) {
- /* Hopefully this won't happen, but if it does, we'll know */
- printf("miiphy_register: MDIO name was longer than %d\n",
- MDIO_NAME_LEN);
- return;
- }
-
new_dev = mdio_alloc();
ldev = malloc(sizeof(*ldev));
/* initalize mii_dev struct fields */
new_dev->read = legacy_miiphy_read;
new_dev->write = legacy_miiphy_write;
- sprintf(new_dev->name, name);
+ strncpy(new_dev->name, name, MDIO_NAME_LEN);
+ new_dev->name[MDIO_NAME_LEN - 1] = 0;
ldev->read = read;
ldev->write = write;
new_dev->priv = ldev;
#include <common.h>
#include <serial.h>
#include <stdio_dev.h>
+#include <post.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
-#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA250) && !defined(CONFIG_PXA27X)
-struct serial_device *__default_serial_console (void)
-{
-#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
- return &serial_smc_device;
-#elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
- || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
- return &serial_scc_device;
-#elif defined(CONFIG_4xx) \
- || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \
- || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \
- || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \
- || defined(CONFIG_TEGRA2)
-#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
-#if (CONFIG_CONS_INDEX==1)
- return &eserial1_device;
-#elif (CONFIG_CONS_INDEX==2)
- return &eserial2_device;
-#elif (CONFIG_CONS_INDEX==3)
- return &eserial3_device;
-#elif (CONFIG_CONS_INDEX==4)
- return &eserial4_device;
-#else
-#error "Bad CONFIG_CONS_INDEX."
-#endif
-#else
- return &serial0_device;
-#endif
-#elif defined(CONFIG_MPC512X)
-#if (CONFIG_PSC_CONSOLE == 3)
- return &serial3_device;
-#elif (CONFIG_PSC_CONSOLE == 6)
- return &serial6_device;
-#else
-#error "Bad CONFIG_PSC_CONSOLE."
-#endif
-#elif defined(CONFIG_S3C2410)
-#if defined(CONFIG_SERIAL1)
- return &s3c24xx_serial0_device;
-#elif defined(CONFIG_SERIAL2)
- return &s3c24xx_serial1_device;
-#elif defined(CONFIG_SERIAL3)
- return &s3c24xx_serial2_device;
-#else
-#error "CONFIG_SERIAL? missing."
-#endif
-#elif defined(CONFIG_S5P)
-#if defined(CONFIG_SERIAL0)
- return &s5p_serial0_device;
-#elif defined(CONFIG_SERIAL1)
- return &s5p_serial1_device;
-#elif defined(CONFIG_SERIAL2)
- return &s5p_serial2_device;
-#elif defined(CONFIG_SERIAL3)
- return &s5p_serial3_device;
-#else
-#error "CONFIG_SERIAL? missing."
-#endif
-#elif defined(CONFIG_OMAP3_ZOOM2)
- return ZOOM2_DEFAULT_SERIAL_DEVICE;
-#else
-#error No default console
-#endif
-}
-
-struct serial_device *default_serial_console(void) __attribute__((weak, alias("__default_serial_console")));
-#endif
-
-int serial_register (struct serial_device *dev)
+void serial_register(struct serial_device *dev)
{
#ifdef CONFIG_NEEDS_MANUAL_RELOC
dev->init += gd->reloc_off;
dev->next = serial_devices;
serial_devices = dev;
-
- return 0;
}
void serial_initialize (void)
serial_current->puts (s);
}
+
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
+
+/* Mark weak until post/cpu/.../uart.c migrate over */
+__weak
+int uart_post_test(int flags)
+{
+ unsigned char c;
+ int ret, saved_baud, b;
+ struct serial_device *saved_dev, *s;
+ bd_t *bd = gd->bd;
+
+ /* Save current serial state */
+ ret = 0;
+ saved_dev = serial_current;
+ saved_baud = bd->bi_baudrate;
+
+ for (s = serial_devices; s; s = s->next) {
+ /* If this driver doesn't support loop back, skip it */
+ if (!s->loop)
+ continue;
+
+ /* Test the next device */
+ serial_current = s;
+
+ ret = serial_init();
+ if (ret)
+ goto done;
+
+ /* Consume anything that happens to be queued */
+ while (serial_tstc())
+ serial_getc();
+
+ /* Enable loop back */
+ s->loop(1);
+
+ /* Test every available baud rate */
+ for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
+ bd->bi_baudrate = bauds[b];
+ serial_setbrg();
+
+ /*
+ * Stick to printable chars to avoid issues:
+ * - terminal corruption
+ * - serial program reacting to sequences and sending
+ * back random extra data
+ * - most serial drivers add in extra chars (like \r\n)
+ */
+ for (c = 0x20; c < 0x7f; ++c) {
+ /* Send it out */
+ serial_putc(c);
+
+ /* Make sure it's the same one */
+ ret = (c != serial_getc());
+ if (ret) {
+ s->loop(0);
+ goto done;
+ }
+
+ /* Clean up the output in case it was sent */
+ serial_putc('\b');
+ ret = ('\b' != serial_getc());
+ if (ret) {
+ s->loop(0);
+ goto done;
+ }
+ }
+ }
+
+ /* Disable loop back */
+ s->loop(0);
+
+ /* XXX: There is no serial_uninit() !? */
+ if (s->uninit)
+ s->uninit();
+ }
+
+ done:
+ /* Restore previous serial state */
+ serial_current = saved_dev;
+ bd->bi_baudrate = saved_baud;
+ serial_reinit_all();
+ serial_setbrg();
+
+ return ret;
+}
+#endif
return 0;
}
-void update_tftp(void)
+int update_tftp(ulong addr)
{
char *filename, *env_addr;
int images_noffset, ndepth, noffset;
ulong update_addr, update_fladdr, update_size;
- ulong addr;
void *fit;
+ int ret = 0;
+
+ /* use already present image */
+ if (addr)
+ goto got_update_file;
printf("Auto-update from TFTP: ");
if (filename == NULL) {
printf("failed, env. variable '%s' not found\n",
UPDATE_FILE_ENV);
- return;
+ return 1;
}
printf("trying update file '%s'\n", filename);
if (update_load(filename, CONFIG_UPDATE_TFTP_MSEC_MAX,
CONFIG_UPDATE_TFTP_CNT_MAX, addr)) {
printf("Can't load update file, aborting auto-update\n");
- return;
+ return 1;
}
+got_update_file:
fit = (void *)addr;
if (!fit_check_format((void *)fit)) {
printf("Bad FIT format of the update file, aborting "
"auto-update\n");
- return;
+ return 1;
}
/* process updates */
if (!fit_image_check_hashes(fit, noffset)) {
printf("Error: invalid update hash, aborting\n");
+ ret = 1;
goto next_node;
}
&update_fladdr, &update_size)) {
printf("Error: can't get update parameteres, "
"aborting\n");
+ ret = 1;
goto next_node;
}
if (update_flash(update_addr, update_fladdr, update_size)) {
printf("Error: can't flash update, aborting\n");
+ ret = 1;
goto next_node;
}
next_node:
noffset = fdt_next_node(fit, noffset, &ndepth);
}
- return;
+ return ret;
}
struct usb_device * usb_get_dev_index(int index);
void uhci_show_temp_int_td(void);
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t *usb_stor_get_dev(int index)
{
return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL;
}
-
+#endif
void usb_show_progress(void)
{
ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
/*
* Consume any trailing crap left in the inbuffer from
- * previous recieved blocks. Since very few files are an exact multiple
+ * previous received blocks. Since very few files are an exact multiple
* of the transfer block size, there will almost always be some gunk here.
* If we don't eat it now, RedBoot will think the user typed it.
*/
#########################################################################
-ifneq ($(OBJTREE),$(SRCTREE))
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
dir := $(subst $(SRCTREE)/,,$(CURDIR))
endif
+ifneq ($(OBJTREE),$(SRCTREE))
+# Create object files for SPL in a separate directory
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
+else
obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/)
+endif
src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/)
$(shell mkdir -p $(obj))
else
+# Create object files for SPL in a separate directory
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
+
+$(shell mkdir -p $(obj))
+else
obj :=
+endif
src :=
endif
CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
-D__KERNEL__
+
+# Enable garbage collection of un-used sections for SPL
+ifeq ($(CONFIG_SPL_BUILD),y)
+CPPFLAGS += -ffunction-sections -fdata-sections
+LDFLAGS_FINAL += --gc-sections
+endif
+
ifneq ($(CONFIG_SYS_TEXT_BASE),)
CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
endif
+ifneq ($(CONFIG_SPL_TEXT_BASE),)
+CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE)
+endif
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+CPPFLAGS += -DCONFIG_SPL_BUILD
+endif
+
ifneq ($(RESET_VECTOR_ADDRESS),)
CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS)
endif
endif
CFLAGS += $(call cc-option,-fno-stack-protector)
+# Some toolchains enable security related warning flags by default,
+# but they don't make much sense in the u-boot world, so disable them.
+CFLAGS += $(call cc-option,-Wno-format-nonliteral)
+CFLAGS += $(call cc-option,-Wno-format-security)
# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
endif
+LDFLAGS_u-boot-spl += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL)
+ifneq ($(CONFIG_SPL_TEXT_BASE),)
+LDFLAGS_u-boot-spl += -Ttext $(CONFIG_SPL_TEXT_BASE)
+endif
+
# Location of a usable BFD library, where we define "usable" as
# "built for ${HOST}, supports ${TARGET}". Sensible values are
# - When cross-compiling: the root of the cross-environment
LIB = $(obj)libdisk.o
-COBJS-y += part.o
+COBJS-$(CONFIG_PARTITIONS) += part.o
COBJS-$(CONFIG_MAC_PARTITION) += part_mac.o
COBJS-$(CONFIG_DOS_PARTITION) += part_dos.o
COBJS-$(CONFIG_ISO_PARTITION) += part_iso.o
int test_part_dos (block_dev_desc_t *dev_desc)
{
- unsigned char buffer[DEFAULT_SECTOR_SIZE];
+ unsigned char buffer[dev_desc->blksz];
if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) ||
(buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) ||
static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative,
int part_num)
{
- unsigned char buffer[DEFAULT_SECTOR_SIZE];
+ unsigned char buffer[dev_desc->blksz];
dos_partition_t *pt;
int i;
int relative, int part_num,
int which_part, disk_partition_t *info)
{
- unsigned char buffer[DEFAULT_SECTOR_SIZE];
+ unsigned char buffer[dev_desc->blksz];
dos_partition_t *pt;
int i;
#define _DISK_PART_DOS_H
-#ifdef CONFIG_ISO_PARTITION
-/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS
- have 2048 byte blocks */
-#define DEFAULT_SECTOR_SIZE 2048
-#else
-#define DEFAULT_SECTOR_SIZE 512
-#endif
#define DOS_PART_TBL_OFFSET 0x1be
#define DOS_PART_MAGIC_OFFSET 0x1fe
#define DOS_PBR_FSTYPE_OFFSET 0x36
--- /dev/null
+Generic SPL framework
+=====================
+
+Overview
+--------
+
+To unify all existing implementations for a secondary program loader (SPL)
+and to allow simply adding of new implementations this generic SPL framework
+has been created. With this framework almost all source files for a board
+can be reused. No code duplication or symlinking is necessary anymore.
+
+
+How it works
+------------
+
+There is a new directory TOPDIR/spl which contains only a Makefile.
+The object files are built separately for SPL and placed in this directory.
+The final binaries which are generated are u-boot-spl, u-boot-spl.bin and
+u-boot-spl.map.
+
+During the SPL build a variable named CONFIG_SPL_BUILD is exported
+in the make environment and also appended to CPPFLAGS with -DCONFIG_SPL_BUILD.
+Source files can therefore be compiled for SPL with different settings.
+ARM-based boards have previously used the option CONFIG_PRELOADER for it.
+
+For example:
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+COBJS-y += board_spl.o
+else
+COBJS-y += board.o
+endif
+
+COBJS-$(CONFIG_SPL_BUILD) += foo.o
+
+#ifdef CONFIG_SPL_BUILD
+ foo();
+#endif
+
+
+The building of SPL images can be with:
+
+#define CONFIG_SPL
+
+Because SPL images normally have a different text base, one have to be
+configured by defining CONFIG_SPL_TEXT_BASE. The linker script have to be
+defined with CONFIG_SPL_LDSCRIPT.
+
+To support generic U-Boot libraries and drivers in the SPL binary one can
+optionally define CONFIG_SPL_XXX_SUPPORT. Currently following options
+are supported:
+
+CONFIG_SPL_LIBCOMMON_SUPPORT (common/libcommon.o)
+CONFIG_SPL_LIBDISK_SUPPORT (disk/libdisk.o)
+CONFIG_SPL_I2C_SUPPORT (drivers/i2c/libi2c.o)
+CONFIG_SPL_GPIO_SUPPORT (drivers/gpio/libgpio.o)
+CONFIG_SPL_MMC_SUPPORT (drivers/mmc/libmmc.o)
+CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o)
+CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
+CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
+CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
+CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SYS_INIT_RAM_ADDR
-- defines the base address of the MCF5272 internal SRAM
CONFIG_SYS_ENET_BD_BASE
- -- defines the base addres of the FEC buffer descriptors
+ -- defines the base address of the FEC buffer descriptors
CONFIG_SYS_SCR -- defines the contents of the System Configuration Register
CONFIG_SYS_SPR -- defines the contents of the System Protection Register
CONFIG_SYS_INT_FLASH_BASE
-- defines the base address of the MCF5282 internal Flash memory
CONFIG_SYS_ENET_BD_BASE
- -- defines the base addres of the FEC buffer descriptors
+ -- defines the base address of the FEC buffer descriptors
CONFIG_SYS_MFD
-- defines the PLL Multiplication Factor Devider
--- /dev/null
+Overview
+=========
+The P2041 Processor combines four Power Architecture processor cores
+with high-performance datapath acceleration architecture(DPAA), CoreNet
+fabric infrastructure, as well as network and peripheral bus interfaces
+required for networking, telecom/datacom, wireless infrastructure, and
+military/aerospace applications.
+
+P2041RDB board is a quad core platform supporting the P2041 processor
+of QorIQ DPAA series.
+
+Boot from NOR flash
+===================
+1. Build image
+ make P2041RDB_config
+ make all
+
+2. Program image
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff80000 efffffff
+ => cp.b 1000000 eff80000 80000
+
+3. Program RCW
+ => tftp 1000000 rcw.bin
+ => protect off all
+ => erase e8000000 e801ffff
+ => cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => protect off all
+ => erase ef000000 ef0fffff
+ => cp.b 1000000 ef000000 2000
+
+5. Change DIP-switch
+ SW1[1-5] = 10110
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SDCard
+===================
+1. Build image
+ make P2041RDB_SDCARD_config
+ make all
+
+2. Generate PBL imge
+ Use PE tool to produce a image used to be programed to
+ SDCard which contains RCW and U-Boot image.
+
+3. Program the PBL image to SDCard
+ => tftp 1000000 pbl_sd.bin
+ => mmcinfo
+ => mmc write 1000000 8 441
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => mmc write 1000000 46a 10
+
+5. Change DIP-switch
+ SW1[1-5] = 01100
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SPI flash
+===================
+1. Build image
+ make P2041RDB_SPIFLASH_config
+ make all
+
+2. Generate PBL imge
+ Use PE tool to produce a image used to be programed to
+ SPI flash which contains RCW and U-Boot image.
+
+3. Program the PBL image to SPI flash
+ => tftp 1000000 pbl_spi.bin
+ => spi probe 0
+ => sf erase 0 100000
+ => sf write 1000000 0 $filesize
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => sf erase 110000 10000
+ => sf write 1000000 110000 $filesize
+
+5. Change DIP-switch
+ SW1[1-5] = 10100
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+CPLD command
+============
+The CPLD is used to control the power sequence and some serdes lane
+mux function.
+
+cpld reset - hard reset to default bank
+cpld reset altbank - reset to alternate bank
+cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
+ lane 6: 0 -> slot1 (Default)
+ 1 -> SGMII
+ lane a: 0 -> slot2 (Default)
+ 1 -> AURORA
+ lane c: 0 -> slot2 (Default)
+ 1 -> SATA0
+ lane d: 0 -> slot2 (Default)
+ 1 -> SATA1
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this:
+ dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
+
+Or use the following command:
+ {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory:
+ {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
+
+Booting Linux
+=============
+Place a linux uImage in the TFTP disk area.
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp 3000000 p2041rdb.dtb
+ bootm 1000000 2000000 3000000
#config to build the kernel
qemu_mips_defconfig
-#patch to fix mips interupt init on 2.6.24.y kernel
+#patch to fix mips interrupt init on 2.6.24.y kernel
qemu_mips_kernel.patch
initrd.gz
vmlinux
--- /dev/null
+---------------------------------------------
+UBL image Boot Image generation using mkimage
+---------------------------------------------
+
+This document describes how to set up an U-Boot image that can be directly
+booted by a DaVinci processor via NAND boot mode, using an UBL header,
+but without need for UBL.
+
+For more details see section 11.2 "ARM ROM Boot Modes" of
+http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf
+
+Command syntax:
+--------------
+./tools/mkimage -l <u-boot_file>
+ to list the UBL image file details
+
+./tools/mkimage -T ublimage \
+ -n <board specific configuration file> \
+ -d <u-boot binary> <output image file>
+
+For example, for the davinci dm365evm board:
+./tools/mkimage -n ./board/davinci/dm365evm/ublimage.cfg \
+ -T ublimage \
+ -d u-boot-nand.bin u-boot.ubl
+
+You can generate the image directly when you compile u-boot with:
+
+$ make u-boot.ubl
+
+The output image can be flashed into the NAND.
+
+Please check the DaVinci documentation for further details.
+
+Board specific configuration file specifications:
+-------------------------------------------------
+1. This file must present in the $(BOARDDIR) and the name should be
+ ublimage.cfg (since this is used in Makefile).
+2. This file can have empty lines and lines starting with "#" as first
+ character to put comments.
+3. This file can have configuration command lines as mentioned below,
+ any other information in this file is treated as invalid.
+
+Configuration command line syntax:
+---------------------------------
+1. Each command line must have two strings, first one command or address
+ and second one data string
+2. Following are the valid command strings and associated data strings:-
+ Command string data string
+ -------------- -----------
+ MODE UBL special mode, on of:
+ safe
+ Example:
+ MODE safe
+
+ ENTRY Entry point address for the user
+ bootloader (absolute address) = TEXT_BASE
+ nand_spl loader.
+ Example:
+ ENTRY 0x00000020
+
+ PAGES Number of pages (size of user bootloader
+ in number of pages)
+ Example:
+ PAGES 27
+
+ START_BLOCK Block number where user bootloader is present
+ Example:
+ START_BLOCK 5
+
+ START_PAGE Page number where user bootloader is present
+ (for RBL always 0)
+ Example:
+ START_PAGE 0
+
+------------------------------------------------
+
+Structure of the u-boot.ubl binary:
+
+compile steps:
+
+1) nand_spl code compile, with pad_to = (TEXT_BASE +
+ (CONFIG_SYS_NROF_PAGES_NAND_SPL * pagesize))
+ Example: cam_enc_4xx pad_to = 0x20 + (6 * 0x800) = 0x3020 = 12320
+ -> u-boot-spl-16k.bin
+
+ !! TEXT_BASE = 0x20, as the RBL starts at 0x20
+
+2) compile u-boot.bin ("normal" u-boot)
+ -> u-boot.bin
+
+3) create u-boot-nand.bin = u-boot-spl-16k.bin + u-boot.bin
+
+4) create u-boot.ubl, size = 1 page size NAND
+ create UBL header and paste it before u-boot.bin
+
+This steps are done automagically if you do a "make all"
+
+-> You get an u-boot.ubl binary, which you can flash
+ into your NAND.
+
+Structure of this binary (Example for the cam_enc_4xx board with a NAND
+page size = 0x800):
+
+offset : 0x00000 | 0x800 | 0x3800
+content: UBL | nand_spl | u-boot code
+ Header | code |
+
+The NAND layout looks for example like this:
+
+(Example for the cam_enc_4xx board with a NAND page size = 0x800, block
+size = 0x20000 and CONFIG_SYS_NROF_UBL_HEADER 5):
+
+offset : 0x80000 | 0xa0000 | 0xa3000
+content: UBL | nand_spl | u-boot code
+ Header | code |
+ ^ ^
+ ^ 0xa0000 = CONFIG_SYS_NROF_UBL_HEADER * 0x20000
+ ^
+ 0x80000 = Block 4 * 0x20000
+
+If the cpu starts in NAND boot mode, it checks the UBL descriptor
+starting with block 1 (page 0). When a valid UBL signature is found,
+the corresponding block number (from 1 to 24) is written to the last 32
+bits of ARM internal memory (0x7ffc-0x8000). This feature is provided
+as a basic debug mechanism. If not found, it continues with block 2
+... last possible block is 24
+
+If a valid UBL descriptor is found, the UBL descriptor is read and
+processed. The descriptor gives the information required for loading
+and control transfer to the nand_spl code. The nand_spl code is then
+read and processed.
+
+Once the user-specified start-up conditions are set, the RBL copies the
+nand_spl into ARM internal RAM, starting at address 0x0000: 0020.
+ ^^^^
+
+The nand_spl code itself now does necessary intializations, and at least,
+copies the u-boot code from NAND into RAM, and jumps to it ...
+
+------------------------------------------------
+Author: Heiko Schocher <hs@denx.de>
to be prepared. Refer to the doc/uImage.FIT/ directory for more details on FIT
images.
+This mechanism can be also triggered by the commmand "fitupd".
+If an optional, non-zero address is provided as argument, the TFTP transfer
+is skipped and the image at this address is used.
+The fitupd command is enabled by CONFIG_CMD_FITUPD.
+
Example .its files
------------------
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_dev_t pdev = probe_ent->dev;
+ u16 tmp16;
+ unsigned short vendor;
+#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
u32 tmp, cap_save;
- u16 tmp16;
int i, j;
volatile u8 *port_mmio;
- unsigned short vendor;
cap_save = readl(mmio + HOST_CAP);
cap_save &= ((1 << 28) | (1 << 17));
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (vendor == PCI_VENDOR_ID_INTEL) {
tmp16 |= 0xf;
pci_write_config_word(pdev, 0x92, tmp16);
}
-
+#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
-
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
-
+#endif
return 0;
}
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_dev_t pdev = probe_ent->dev;
+ u16 cc;
+#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
u32 vers, cap, impl, speed;
const char *speed_s;
- u16 cc;
const char *scc_s;
vers = readl(mmio + HOST_VERSION);
else
speed_s = "?";
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ scc_s = "SATA";
+#else
pci_read_config_word(pdev, 0x0a, &cc);
if (cc == 0x0101)
scc_s = "IDE";
scc_s = "RAID";
else
scc_s = "unknown";
-
+#endif
printf("AHCI %02x%02x.%02x%02x "
"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
(vers >> 24) & 0xff,
cap & (1 << 13) ? "part " : "");
}
+#ifndef CONFIG_SCSI_AHCI_PLAT
static int ahci_init_one(pci_dev_t pdev)
{
u16 vendor;
err_out:
return rc;
}
-
+#endif
#define MAX_DATA_BYTE_COUNT (4*1024*1024)
{
int i;
for (i = 0; i < len / 2; i++)
- target[i] = le16_to_cpu(src[i]);
+ target[i] = swab16(src[i]);
return (char *)target;
}
int i;
u32 linkmap;
+#ifndef CONFIG_SCSI_AHCI_PLAT
ahci_init_one(busdevfunc);
+#endif
linkmap = probe_ent->link_port_map;
}
}
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int ahci_init(u32 base)
+{
+ int i, rc = 0;
+ u32 linkmap;
+
+ memset(ataid, 0, sizeof(ataid));
+
+ probe_ent = malloc(sizeof(struct ahci_probe_ent));
+ memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
+
+ probe_ent->host_flags = ATA_FLAG_SATA
+ | ATA_FLAG_NO_LEGACY
+ | ATA_FLAG_MMIO
+ | ATA_FLAG_PIO_DMA
+ | ATA_FLAG_NO_ATAPI;
+ probe_ent->pio_mask = 0x1f;
+ probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
+
+ probe_ent->mmio_base = base;
+
+ /* initialize adapter */
+ rc = ahci_host_init(probe_ent);
+ if (rc)
+ goto err_out;
+
+ ahci_print_info(probe_ent);
+
+ linkmap = probe_ent->link_port_map;
+
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+ if (((linkmap >> i) & 0x01)) {
+ if (ahci_port_start((u8) i)) {
+ printf("Can not start port %d\n", i);
+ continue;
+ }
+ ahci_set_feature((u8) i);
+ }
+ }
+err_out:
+ return rc;
+}
+#endif
void scsi_bus_reset(void)
{
u32 from, cur, err;
err = MG_ERR_NONE;
+#ifdef CONFIG_SYS_LOW_RES_TIMER
reset_timer();
+#endif
from = get_timer(0);
status = readb(mg_base() + MG_REG_STATUS);
return err;
}
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t *mg_disk_get_dev(int dev)
{
return ((block_dev_desc_t *) & mg_disk_dev);
}
+#endif
/* must override this function */
struct mg_drv_data * __attribute__((weak)) mg_get_drv_data (void)
ace_writew((val & 0xffff), 0x18);
}
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t *systemace_get_dev(int dev)
{
/* The first time through this, the systemace_dev object is
return &systemace_dev;
}
+#endif
/*
* This function is called (by dereferencing the block_read pointer in
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
-static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
-static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
-/* static int ACEX1K_ps_info( Altera_desc *desc ); */
+static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
+static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
+/* static int ACEX1K_ps_info(Altera_desc *desc); */
/* ------------------------------------------------------------------------- */
/* ACEX1K Generic Implementation */
-int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
+int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
+int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* ACEX1K Passive Serial Generic Implementation */
-static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
static int altera_validate (Altera_desc * desc, const char *fn);
/* ------------------------------------------------------------------------- */
-int altera_load( Altera_desc *desc, void *buf, size_t bsize )
+int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
__FUNCTION__);
ret_val = ACEX1K_load (desc, buf, bsize);
#elif defined(CONFIG_FPGA_CYCLON2)
- PRINTF ("%s: Launching the CYCLON II Loader...\n",
+ PRINTF ("%s: Launching the CYCLONE II Loader...\n",
__FUNCTION__);
ret_val = CYC2_load (desc, buf, bsize);
#else
return ret_val;
}
-int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
+int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
-static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize );
-static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
+static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
+static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
/* static int CYC2_ps_info( Altera_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* CYCLON2 Generic Implementation */
-int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
+int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
ret_val = CYC2_ps_load (desc, buf, bsize);
break;
+ case fast_passive_parallel:
+ /* Fast Passive Parallel (FPP) and PS only differ in what is
+ * done in the write() callback. Use the existing PS load
+ * function for FPP, too.
+ */
+ PRINTF ("%s: Launching Fast Passive Parallel Loader\n",
+ __FUNCTION__);
+ ret_val = CYC2_ps_load(desc, buf, bsize);
+ break;
+
/* Add new interface types here */
default:
return ret_val;
}
-int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize)
+int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* CYCLON2 Passive Serial Generic Implementation */
-static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
/* Local static functions */
static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum );
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn );
static int fpga_dev_info( int devnum );
/* fpga_validate
* generic parameter checking code
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn )
{
fpga_desc * desc = fpga_get_desc( devnum );
/*
* Generic multiplexing code
*/
-int fpga_load( int devnum, void *buf, size_t bsize )
+int fpga_load(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
/* fpga_dump
* generic multiplexing code
*/
-int fpga_dump( int devnum, void *buf, size_t bsize )
+int fpga_dump(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan2_sp_info( Xilinx_desc *desc ); */
+static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
-static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan2_ss_info( Xilinx_desc *desc ); */
+static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
/* ------------------------------------------------------------------------- */
-static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan3_sp_info( Xilinx_desc *desc ); */
+static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan3_sp_info(Xilinx_desc *desc ); */
-static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan3_ss_info( Xilinx_desc *desc ); */
+static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan3_ss_info(Xilinx_desc *desc); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
/* ------------------------------------------------------------------------- */
-static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize);
+static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize);
+static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
/* ------------------------------------------------------------------------- */
-int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
return ret_val;
}
-int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
int timeout = I2C_TIMEOUT;
u16 stat;
- writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
+ writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
writew (stat, &i2c_base->stat);
udelay(1000);
COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
+COBJS-$(CONFIG_SDHCI) += sdhci.o
+COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
u32 sdcr; /* 0x0c */
u32 argr; /* 0x10 */
u32 cmdr; /* 0x14 */
- u32 _18; /* 0x18 */
+ u32 blkr; /* 0x18 */
u32 _1c; /* 0x1c */
u32 rspr; /* 0x20 */
u32 rspr1; /* 0x24 */
#define MMCI_SDCR 0x000c
#define MMCI_ARGR 0x0010
#define MMCI_CMDR 0x0014
+#define MMCI_BLKR 0x0018
#define MMCI_RSPR 0x0020
#define MMCI_RSPR1 0x0024
#define MMCI_RSPR2 0x0028
#define MMCI_TRTYP_OFFSET 19
#define MMCI_TRTYP_SIZE 2
+/* Bitfields in BLKR */
+#define MMCI_BCNT_OFFSET 0
+#define MMCI_BCNT_SIZE 16
+#define MMCI_BLKLEN_OFFSET 16
+#define MMCI_BLKLEN_SIZE 16
+
/* Bitfields in RSPRx */
#define MMCI_RSP_OFFSET 0
#define MMCI_RSP_SIZE 32
/* Figure out the transfer arguments */
cmdr = mci_encode_cmd(cmd, data, &error_flags);
+ if (data)
+ writel(MMCI_BF(BCNT, data->blocks) |
+ MMCI_BF(BLKLEN, mmc->read_bl_len), &mci->blkr);
+
/* Send the command */
writel(cmd->cmdarg, &mci->argr);
writel(cmdr, &mci->cmdr);
return NULL;
}
+static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
+{
+ struct mmc_cmd cmd;
+ ulong end;
+ int err, start_cmd, end_cmd;
+
+ if (mmc->high_capacity)
+ end = start + blkcnt - 1;
+ else {
+ end = (start + blkcnt - 1) * mmc->write_bl_len;
+ start *= mmc->write_bl_len;
+ }
+
+ if (IS_SD(mmc)) {
+ start_cmd = SD_CMD_ERASE_WR_BLK_START;
+ end_cmd = SD_CMD_ERASE_WR_BLK_END;
+ } else {
+ start_cmd = MMC_CMD_ERASE_GROUP_START;
+ end_cmd = MMC_CMD_ERASE_GROUP_END;
+ }
+
+ cmd.cmdidx = start_cmd;
+ cmd.cmdarg = start;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ goto err_out;
+
+ cmd.cmdidx = end_cmd;
+ cmd.cmdarg = end;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ goto err_out;
+
+ cmd.cmdidx = MMC_CMD_ERASE;
+ cmd.cmdarg = SECURE_ERASE;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ goto err_out;
+
+ return 0;
+
+err_out:
+ puts("mmc erase failed\n");
+ return err;
+}
+
+static unsigned long
+mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
+{
+ int err = 0;
+ struct mmc *mmc = find_mmc_device(dev_num);
+ lbaint_t blk = 0, blk_r = 0;
+
+ if (!mmc)
+ return -1;
+
+ if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size))
+ printf("\n\nCaution! Your devices Erase group is 0x%x\n"
+ "The erase range would be change to 0x%lx~0x%lx\n\n",
+ mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
+ ((start + blkcnt + mmc->erase_grp_size)
+ & ~(mmc->erase_grp_size - 1)) - 1);
+
+ while (blk < blkcnt) {
+ blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
+ mmc->erase_grp_size : (blkcnt - blk);
+ err = mmc_erase_t(mmc, start + blk, blk_r);
+ if (err)
+ break;
+
+ blk += blk_r;
+ }
+
+ return blk;
+}
+
static ulong
mmc_write_blocks(struct mmc *mmc, ulong start, lbaint_t blkcnt, const void*src)
{
(mmc->voltages &
(cmd.response[0] & OCR_VOLTAGE_MASK)) |
(cmd.response[0] & OCR_ACCESS_MODE));
+
+ if (mmc->host_caps & MMC_MODE_HC)
+ cmd.cmdarg |= OCR_HCS;
+
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
{
int err;
uint mult, freq;
- u64 cmult, csize;
+ u64 cmult, csize, capacity;
struct mmc_cmd cmd;
char ext_csd[512];
int timeout = 1000;
return err;
}
+ /*
+ * For SD, its erase group is always one sector
+ */
+ mmc->erase_grp_size = 1;
mmc->part_config = MMCPART_NOAVAILABLE;
if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
/* check ext_csd version and capacity */
err = mmc_send_ext_csd(mmc, ext_csd);
if (!err & (ext_csd[192] >= 2)) {
- mmc->capacity = ext_csd[212] << 0 | ext_csd[213] << 8 |
- ext_csd[214] << 16 | ext_csd[215] << 24;
- mmc->capacity *= 512;
+ /*
+ * According to the JEDEC Standard, the value of
+ * ext_csd's capacity is valid if the value is more
+ * than 2GB
+ */
+ capacity = ext_csd[212] << 0 | ext_csd[213] << 8 |
+ ext_csd[214] << 16 | ext_csd[215] << 24;
+ capacity *= 512;
+ if ((capacity >> 20) > 2 * 1024)
+ mmc->capacity = capacity;
+ }
+
+ /*
+ * Check whether GROUP_DEF is set, if yes, read out
+ * group size from ext_csd directly, or calculate
+ * the group size from the csd value.
+ */
+ if (ext_csd[175])
+ mmc->erase_grp_size = ext_csd[224] * 512 * 1024;
+ else {
+ int erase_gsz, erase_gmul;
+ erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
+ erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
+ mmc->erase_grp_size = (erase_gsz + 1)
+ * (erase_gmul + 1);
}
/* store the partition info of emmc */
mmc->block_dev.removable = 1;
mmc->block_dev.block_read = mmc_bread;
mmc->block_dev.block_write = mmc_bwrite;
+ mmc->block_dev.block_erase = mmc_berase;
if (!mmc->b_max)
mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
return 0;
}
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t *mmc_get_dev(int dev)
{
struct mmc *mmc = find_mmc_device(dev);
return mmc ? &mmc->block_dev : NULL;
}
+#endif
int mmc_init(struct mmc *mmc)
{
--- /dev/null
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+static char *MVSDH_NAME = "mv_sdh";
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+{
+ struct sdhci_host *host = NULL;
+ host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf("sdh_host malloc fail!\n");
+ return 1;
+ }
+
+ host->name = MVSDH_NAME;
+ host->ioaddr = (void *)regbase;
+ host->quirks = quirks;
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ add_sdhci(host, max_clk, min_clk);
+ return 0;
+}
mmc->host_caps = MMC_MODE_8BIT;
else
mmc->host_caps = MMC_MODE_4BIT;
- mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
mmc->f_min = 400000;
mmc->f_max = 52000000;
--- /dev/null
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <sdhci.h>
+
+void *aligned_buffer;
+
+static void sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+ unsigned long timeout;
+
+ /* Wait max 100 ms */
+ timeout = 100;
+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
+ if (timeout == 0) {
+ printf("Reset 0x%x never completed.\n", (int)mask);
+ return;
+ }
+ timeout--;
+ udelay(1000);
+ }
+}
+
+static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
+{
+ int i;
+ if (cmd->resp_type & MMC_RSP_136) {
+ /* CRC is stripped so we need to do some shifting. */
+ for (i = 0; i < 4; i++) {
+ cmd->response[i] = sdhci_readl(host,
+ SDHCI_RESPONSE + (3-i)*4) << 8;
+ if (i != 3)
+ cmd->response[i] |= sdhci_readb(host,
+ SDHCI_RESPONSE + (3-i)*4-1);
+ }
+ } else {
+ cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
+ }
+}
+
+static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
+{
+ int i;
+ char *offs;
+ for (i = 0; i < data->blocksize; i += 4) {
+ offs = data->dest + i;
+ if (data->flags == MMC_DATA_READ)
+ *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
+ else
+ sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
+ }
+}
+
+static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
+ unsigned int start_addr)
+{
+ unsigned int stat, rdy, mask, block = 0;
+
+ rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
+ mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
+ do {
+ stat = sdhci_readl(host, SDHCI_INT_STATUS);
+ if (stat & SDHCI_INT_ERROR) {
+ printf("Error detected in status(0x%X)!\n", stat);
+ return -1;
+ }
+ if (stat & rdy) {
+ if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
+ continue;
+ sdhci_writel(host, rdy, SDHCI_INT_STATUS);
+ sdhci_transfer_pio(host, data);
+ data->dest += data->blocksize;
+ if (++block >= data->blocks)
+ break;
+ }
+#ifdef CONFIG_MMC_SDMA
+ if (stat & SDHCI_INT_DMA_END) {
+ sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
+ start_addr &= SDHCI_DEFAULT_BOUNDARY_SIZE - 1;
+ start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
+ sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
+ }
+#endif
+ } while (!(stat & SDHCI_INT_DATA_END));
+ return 0;
+}
+
+int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+ unsigned int stat = 0;
+ int ret = 0;
+ int trans_bytes = 0, is_aligned = 1;
+ u32 mask, flags, mode;
+ unsigned int timeout, start_addr = 0;
+
+ /* Wait max 10 ms */
+ timeout = 10;
+
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
+ mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
+
+ /* We shouldn't wait for data inihibit for stop commands, even
+ though they might use busy signaling */
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ mask &= ~SDHCI_DATA_INHIBIT;
+
+ while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
+ if (timeout == 0) {
+ printf("Controller never released inhibit bit(s).\n");
+ return COMM_ERR;
+ }
+ timeout--;
+ udelay(1000);
+ }
+
+ mask = SDHCI_INT_RESPONSE;
+ if (!(cmd->resp_type & MMC_RSP_PRESENT))
+ flags = SDHCI_CMD_RESP_NONE;
+ else if (cmd->resp_type & MMC_RSP_136)
+ flags = SDHCI_CMD_RESP_LONG;
+ else if (cmd->resp_type & MMC_RSP_BUSY) {
+ flags = SDHCI_CMD_RESP_SHORT_BUSY;
+ mask |= SDHCI_INT_DATA_END;
+ } else
+ flags = SDHCI_CMD_RESP_SHORT;
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ flags |= SDHCI_CMD_CRC;
+ if (cmd->resp_type & MMC_RSP_OPCODE)
+ flags |= SDHCI_CMD_INDEX;
+ if (data)
+ flags |= SDHCI_CMD_DATA;
+
+ /*Set Transfer mode regarding to data flag*/
+ if (data != 0) {
+ sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
+ mode = SDHCI_TRNS_BLK_CNT_EN;
+ trans_bytes = data->blocks * data->blocksize;
+ if (data->blocks > 1)
+ mode |= SDHCI_TRNS_MULTI;
+
+ if (data->flags == MMC_DATA_READ)
+ mode |= SDHCI_TRNS_READ;
+
+#ifdef CONFIG_MMC_SDMA
+ if (data->flags == MMC_DATA_READ)
+ start_addr = (unsigned int)data->dest;
+ else
+ start_addr = (unsigned int)data->src;
+ if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
+ (start_addr & 0x7) != 0x0) {
+ is_aligned = 0;
+ start_addr = (unsigned int)aligned_buffer;
+ if (data->flags != MMC_DATA_READ)
+ memcpy(aligned_buffer, data->src, trans_bytes);
+ }
+
+ sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
+ mode |= SDHCI_TRNS_DMA;
+#endif
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
+ data->blocksize),
+ SDHCI_BLOCK_SIZE);
+ sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
+ }
+
+ sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
+#ifdef CONFIG_MMC_SDMA
+ flush_cache(0, ~0);
+#endif
+ sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
+ do {
+ stat = sdhci_readl(host, SDHCI_INT_STATUS);
+ if (stat & SDHCI_INT_ERROR)
+ break;
+ } while ((stat & mask) != mask);
+
+ if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
+ sdhci_cmd_done(host, cmd);
+ sdhci_writel(host, mask, SDHCI_INT_STATUS);
+ } else
+ ret = -1;
+
+ if (!ret && data)
+ ret = sdhci_transfer_data(host, data, start_addr);
+
+ stat = sdhci_readl(host, SDHCI_INT_STATUS);
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
+ if (!ret) {
+ if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
+ !is_aligned && (data->flags == MMC_DATA_READ))
+ memcpy(data->dest, aligned_buffer, trans_bytes);
+ return 0;
+ }
+
+ sdhci_reset(host, SDHCI_RESET_CMD);
+ sdhci_reset(host, SDHCI_RESET_DATA);
+ if (stat & SDHCI_INT_TIMEOUT)
+ return TIMEOUT;
+ else
+ return COMM_ERR;
+}
+
+static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
+{
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+ unsigned int div, clk, timeout;
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return 0;
+
+ if (host->version >= SDHCI_SPEC_300) {
+ /* Version 3.00 divisors must be a multiple of 2. */
+ if (mmc->f_max <= clock)
+ div = 1;
+ else {
+ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
+ if ((mmc->f_max / div) <= clock)
+ break;
+ }
+ }
+ } else {
+ /* Version 2.00 divisors must be a power of 2. */
+ for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
+ if ((mmc->f_max / div) <= clock)
+ break;
+ }
+ }
+ div >>= 1;
+
+ clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
+ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
+ << SDHCI_DIVIDER_HI_SHIFT;
+ clk |= SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Wait max 20 ms */
+ timeout = 20;
+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ printf("Internal clock never stabilised.\n");
+ return -1;
+ }
+ timeout--;
+ udelay(1000);
+ }
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+ return 0;
+}
+
+static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
+{
+ u8 pwr = 0;
+
+ if (power != (unsigned short)-1) {
+ switch (1 << power) {
+ case MMC_VDD_165_195:
+ pwr = SDHCI_POWER_180;
+ break;
+ case MMC_VDD_29_30:
+ case MMC_VDD_30_31:
+ pwr = SDHCI_POWER_300;
+ break;
+ case MMC_VDD_32_33:
+ case MMC_VDD_33_34:
+ pwr = SDHCI_POWER_330;
+ break;
+ }
+ }
+
+ if (pwr == 0) {
+ sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
+ return;
+ }
+
+ pwr |= SDHCI_POWER_ON;
+
+ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+}
+
+void sdhci_set_ios(struct mmc *mmc)
+{
+ u32 ctrl;
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+
+ if (mmc->clock != host->clock)
+ sdhci_set_clock(mmc, mmc->clock);
+
+ /* Set bus width */
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ if (mmc->bus_width == 8) {
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ if (host->version >= SDHCI_SPEC_300)
+ ctrl |= SDHCI_CTRL_8BITBUS;
+ } else {
+ if (host->version >= SDHCI_SPEC_300)
+ ctrl &= ~SDHCI_CTRL_8BITBUS;
+ if (mmc->bus_width == 4)
+ ctrl |= SDHCI_CTRL_4BITBUS;
+ else
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ }
+
+ if (mmc->clock > 26000000)
+ ctrl |= SDHCI_CTRL_HISPD;
+ else
+ ctrl &= ~SDHCI_CTRL_HISPD;
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
+int sdhci_init(struct mmc *mmc)
+{
+ struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+
+ if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
+ aligned_buffer = memalign(8, 512*1024);
+ if (!aligned_buffer) {
+ printf("Aligned buffer alloc failed!!!");
+ return -1;
+ }
+ }
+
+ /* Eable all state */
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
+
+ sdhci_set_power(host, fls(mmc->voltages) - 1);
+
+ return 0;
+}
+
+int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
+{
+ struct mmc *mmc;
+ unsigned int caps;
+
+ mmc = malloc(sizeof(struct mmc));
+ if (!mmc) {
+ printf("mmc malloc fail!\n");
+ return -1;
+ }
+
+ mmc->priv = host;
+
+ sprintf(mmc->name, "%s", host->name);
+ mmc->send_cmd = sdhci_send_command;
+ mmc->set_ios = sdhci_set_ios;
+ mmc->init = sdhci_init;
+
+ caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+#ifdef CONFIG_MMC_SDMA
+ if (!(caps & SDHCI_CAN_DO_SDMA)) {
+ printf("Your controller don't support sdma!!\n");
+ return -1;
+ }
+#endif
+
+ if (max_clk)
+ mmc->f_max = max_clk;
+ else {
+ if (host->version >= SDHCI_SPEC_300)
+ mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
+ >> SDHCI_CLOCK_BASE_SHIFT;
+ else
+ mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
+ >> SDHCI_CLOCK_BASE_SHIFT;
+ mmc->f_max *= 1000000;
+ }
+ if (mmc->f_max == 0) {
+ printf("Hardware doesn't specify base clock frequency\n");
+ return -1;
+ }
+ if (min_clk)
+ mmc->f_min = min_clk;
+ else {
+ if (host->version >= SDHCI_SPEC_300)
+ mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
+ else
+ mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
+ }
+
+ mmc->voltages = 0;
+ if (caps & SDHCI_CAN_VDD_330)
+ mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
+ if (caps & SDHCI_CAN_VDD_300)
+ mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+ if (caps & SDHCI_CAN_VDD_180)
+ mmc->voltages |= MMC_VDD_165_195;
+ mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ if (caps & SDHCI_CAN_DO_8BIT)
+ mmc->host_caps |= MMC_MODE_8BIT;
+
+ sdhci_reset(host, SDHCI_RESET_ALL);
+ mmc_register(mmc);
+
+ return 0;
+}
--- /dev/null
+/*
+ * MMCIF driver.
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include "sh_mmcif.h"
+
+#define DRIVER_NAME "sh_mmcif"
+
+static void *mmc_priv(struct mmc *mmc)
+{
+ return (void *)mmc->priv;
+}
+
+static int sh_mmcif_intr(void *dev_id)
+{
+ struct sh_mmcif_host *host = dev_id;
+ u32 state = 0;
+
+ state = sh_mmcif_read(&host->regs->ce_int);
+ state &= sh_mmcif_read(&host->regs->ce_int_mask);
+
+ if (state & INT_RBSYE) {
+ sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
+ goto end;
+ } else if (state & INT_CRSPE) {
+ sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
+ /* one more interrupt (INT_RBSYE) */
+ if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
+ return -EAGAIN;
+ goto end;
+ } else if (state & INT_BUFREN) {
+ sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
+ goto end;
+ } else if (state & INT_BUFWEN) {
+ sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
+ goto end;
+ } else if (state & INT_CMD12DRE) {
+ sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
+ INT_BUFRE), &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
+ goto end;
+ } else if (state & INT_BUFRE) {
+ sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
+ goto end;
+ } else if (state & INT_DTRANE) {
+ sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
+ goto end;
+ } else if (state & INT_CMD12RBE) {
+ sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
+ &host->regs->ce_int);
+ sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
+ goto end;
+ } else if (state & INT_ERR_STS) {
+ /* err interrupts */
+ sh_mmcif_write(~state, &host->regs->ce_int);
+ sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
+ goto err;
+ } else
+ return -EAGAIN;
+
+err:
+ host->sd_error = 1;
+ debug("%s: int err state = %08x\n", DRIVER_NAME, state);
+end:
+ host->wait_int = 1;
+ return 0;
+}
+
+static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
+{
+ int timeout = 10000000;
+
+ while (1) {
+ timeout--;
+ if (timeout < 0) {
+ printf("timeout\n");
+ return 0;
+ }
+
+ if (!sh_mmcif_intr(host))
+ break;
+
+ udelay(1); /* 1 usec */
+ }
+
+ return 1; /* Return value: NOT 0 = complete waiting */
+}
+
+static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
+{
+ int i;
+
+ sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
+ sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
+
+ if (!clk)
+ return;
+ if (clk == CLKDEV_EMMC_DATA) {
+ sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
+ } else {
+ for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++)
+ ;
+ sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl);
+ }
+ sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
+}
+
+static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
+{
+ u32 tmp;
+
+ tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
+ CLK_CLEAR);
+
+ sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
+ sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
+ sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
+ &host->regs->ce_clk_ctrl);
+ /* byte swap on */
+ sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
+}
+
+static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
+{
+ u32 state1, state2;
+ int ret, timeout = 10000000;
+
+ host->sd_error = 0;
+ host->wait_int = 0;
+
+ state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
+ state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
+ debug("%s: ERR HOST_STS1 = %08x\n", \
+ DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
+ debug("%s: ERR HOST_STS2 = %08x\n", \
+ DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
+
+ if (state1 & STS1_CMDSEQ) {
+ debug("%s: Forced end of command sequence\n", DRIVER_NAME);
+ sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
+ sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
+ while (1) {
+ timeout--;
+ if (timeout < 0) {
+ printf(DRIVER_NAME": Forceed end of " \
+ "command sequence timeout err\n");
+ return -EILSEQ;
+ }
+ if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
+ & STS1_CMDSEQ))
+ break;
+ }
+ sh_mmcif_sync_reset(host);
+ return -EILSEQ;
+ }
+
+ if (state2 & STS2_CRC_ERR)
+ ret = -EILSEQ;
+ else if (state2 & STS2_TIMEOUT_ERR)
+ ret = TIMEOUT;
+ else
+ ret = -EILSEQ;
+ return ret;
+}
+
+static int sh_mmcif_single_read(struct sh_mmcif_host *host,
+ struct mmc_data *data)
+{
+ long time;
+ u32 blocksize, i;
+ unsigned long *p = (unsigned long *)data->dest;
+
+ if ((unsigned long)p & 0x00000001) {
+ printf("%s: The data pointer is unaligned.", __func__);
+ return -EIO;
+ }
+
+ host->wait_int = 0;
+
+ /* buf read enable */
+ sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
+ time = mmcif_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_mmcif_error_manage(host);
+
+ host->wait_int = 0;
+ blocksize = (BLOCK_SIZE_MASK &
+ sh_mmcif_read(&host->regs->ce_block_set)) + 3;
+ for (i = 0; i < blocksize / 4; i++)
+ *p++ = sh_mmcif_read(&host->regs->ce_data);
+
+ /* buffer read end */
+ sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
+ time = mmcif_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_mmcif_error_manage(host);
+
+ host->wait_int = 0;
+ return 0;
+}
+
+static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
+ struct mmc_data *data)
+{
+ long time;
+ u32 blocksize, i, j;
+ unsigned long *p = (unsigned long *)data->dest;
+
+ if ((unsigned long)p & 0x00000001) {
+ printf("%s: The data pointer is unaligned.", __func__);
+ return -EIO;
+ }
+
+ host->wait_int = 0;
+ blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
+ for (j = 0; j < data->blocks; j++) {
+ sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
+ time = mmcif_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_mmcif_error_manage(host);
+
+ host->wait_int = 0;
+ for (i = 0; i < blocksize / 4; i++)
+ *p++ = sh_mmcif_read(&host->regs->ce_data);
+
+ WATCHDOG_RESET();
+ }
+ return 0;
+}
+
+static int sh_mmcif_single_write(struct sh_mmcif_host *host,
+ struct mmc_data *data)
+{
+ long time;
+ u32 blocksize, i;
+ const unsigned long *p = (unsigned long *)data->dest;
+
+ if ((unsigned long)p & 0x00000001) {
+ printf("%s: The data pointer is unaligned.", __func__);
+ return -EIO;
+ }
+
+ host->wait_int = 0;
+ sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
+
+ time = mmcif_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_mmcif_error_manage(host);
+
+ host->wait_int = 0;
+ blocksize = (BLOCK_SIZE_MASK &
+ sh_mmcif_read(&host->regs->ce_block_set)) + 3;
+ for (i = 0; i < blocksize / 4; i++)
+ sh_mmcif_write(*p++, &host->regs->ce_data);
+
+ /* buffer write end */
+ sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
+
+ time = mmcif_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_mmcif_error_manage(host);
+
+ host->wait_int = 0;
+ return 0;
+}
+
+static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
+ struct mmc_data *data)
+{
+ long time;
+ u32 i, j, blocksize;
+ const unsigned long *p = (unsigned long *)data->dest;
+
+ if ((unsigned long)p & 0x00000001) {
+ printf("%s: The data pointer is unaligned.", __func__);
+ return -EIO;
+ }
+
+ host->wait_int = 0;
+ blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
+ for (j = 0; j < data->blocks; j++) {
+ sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
+
+ time = mmcif_wait_interrupt_flag(host);
+
+ if (time == 0 || host->sd_error != 0)
+ return sh_mmcif_error_manage(host);
+
+ host->wait_int = 0;
+ for (i = 0; i < blocksize / 4; i++)
+ sh_mmcif_write(*p++, &host->regs->ce_data);
+
+ WATCHDOG_RESET();
+ }
+ return 0;
+}
+
+static void sh_mmcif_get_response(struct sh_mmcif_host *host,
+ struct mmc_cmd *cmd)
+{
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
+ cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
+ cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
+ cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
+ debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
+ cmd->response[1], cmd->response[2], cmd->response[3]);
+ } else {
+ cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
+ }
+}
+
+static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
+ struct mmc_cmd *cmd)
+{
+ cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
+}
+
+static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
+ struct mmc_data *data, struct mmc_cmd *cmd)
+{
+ u32 tmp = 0;
+ u32 opc = cmd->cmdidx;
+
+ /* Response Type check */
+ switch (cmd->resp_type) {
+ case MMC_RSP_NONE:
+ tmp |= CMD_SET_RTYP_NO;
+ break;
+ case MMC_RSP_R1:
+ case MMC_RSP_R1b:
+ case MMC_RSP_R3:
+ tmp |= CMD_SET_RTYP_6B;
+ break;
+ case MMC_RSP_R2:
+ tmp |= CMD_SET_RTYP_17B;
+ break;
+ default:
+ printf(DRIVER_NAME": Not support type response.\n");
+ break;
+ }
+
+ /* RBSY */
+ if (opc == MMC_CMD_SWITCH)
+ tmp |= CMD_SET_RBSY;
+
+ /* WDAT / DATW */
+ if (host->data) {
+ tmp |= CMD_SET_WDAT;
+ switch (host->bus_width) {
+ case MMC_BUS_WIDTH_1:
+ tmp |= CMD_SET_DATW_1;
+ break;
+ case MMC_BUS_WIDTH_4:
+ tmp |= CMD_SET_DATW_4;
+ break;
+ case MMC_BUS_WIDTH_8:
+ tmp |= CMD_SET_DATW_8;
+ break;
+ default:
+ printf(DRIVER_NAME": Not support bus width.\n");
+ break;
+ }
+ }
+ /* DWEN */
+ if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
+ opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
+ tmp |= CMD_SET_DWEN;
+ /* CMLTE/CMD12EN */
+ if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
+ opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
+ tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
+ sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
+ }
+ /* RIDXC[1:0] check bits */
+ if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
+ opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
+ tmp |= CMD_SET_RIDXC_BITS;
+ /* RCRC7C[1:0] check bits */
+ if (opc == MMC_CMD_SEND_OP_COND)
+ tmp |= CMD_SET_CRC7C_BITS;
+ /* RCRC7C[1:0] internal CRC7 */
+ if (opc == MMC_CMD_ALL_SEND_CID ||
+ opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
+ tmp |= CMD_SET_CRC7C_INTERNAL;
+
+ return opc = ((opc << 24) | tmp);
+}
+
+static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
+ struct mmc_data *data, u16 opc)
+{
+ u32 ret;
+
+ switch (opc) {
+ case MMC_CMD_READ_MULTIPLE_BLOCK:
+ ret = sh_mmcif_multi_read(host, data);
+ break;
+ case MMC_CMD_WRITE_MULTIPLE_BLOCK:
+ ret = sh_mmcif_multi_write(host, data);
+ break;
+ case MMC_CMD_WRITE_SINGLE_BLOCK:
+ ret = sh_mmcif_single_write(host, data);
+ break;
+ case MMC_CMD_READ_SINGLE_BLOCK:
+ case MMC_CMD_SEND_EXT_CSD:
+ ret = sh_mmcif_single_read(host, data);
+ break;
+ default:
+ printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
+ struct mmc_data *data, struct mmc_cmd *cmd)
+{
+ long time;
+ int ret = 0, mask = 0;
+ u32 opc = cmd->cmdidx;
+
+ if (opc == MMC_CMD_STOP_TRANSMISSION) {
+ /* MMCIF sends the STOP command automatically */
+ if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
+ sh_mmcif_bitset(MASK_MCMD12DRE,
+ &host->regs->ce_int_mask);
+ else
+ sh_mmcif_bitset(MASK_MCMD12RBE,
+ &host->regs->ce_int_mask);
+
+ time = mmcif_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_mmcif_error_manage(host);
+
+ sh_mmcif_get_cmd12response(host, cmd);
+ return 0;
+ }
+ if (opc == MMC_CMD_SWITCH)
+ mask = MASK_MRBSYE;
+ else
+ mask = MASK_MCRSPE;
+
+ mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
+ MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
+ MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
+ MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
+
+ if (host->data) {
+ sh_mmcif_write(0, &host->regs->ce_block_set);
+ sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
+ }
+ opc = sh_mmcif_set_cmd(host, data, cmd);
+
+ sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
+ sh_mmcif_write(mask, &host->regs->ce_int_mask);
+
+ debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
+ /* set arg */
+ sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
+ host->wait_int = 0;
+ /* set cmd */
+ sh_mmcif_write(opc, &host->regs->ce_cmd_set);
+
+ time = mmcif_wait_interrupt_flag(host);
+ if (time == 0)
+ return sh_mmcif_error_manage(host);
+
+ if (host->sd_error) {
+ switch (cmd->cmdidx) {
+ case MMC_CMD_ALL_SEND_CID:
+ case MMC_CMD_SELECT_CARD:
+ case MMC_CMD_APP_CMD:
+ ret = TIMEOUT;
+ break;
+ default:
+ printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
+ ret = sh_mmcif_error_manage(host);
+ break;
+ }
+ host->sd_error = 0;
+ host->wait_int = 0;
+ return ret;
+ }
+
+ /* if no response */
+ if (!(opc & 0x00C00000))
+ return 0;
+
+ if (host->wait_int == 1) {
+ sh_mmcif_get_response(host, cmd);
+ host->wait_int = 0;
+ }
+ if (host->data)
+ ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
+ host->last_cmd = cmd->cmdidx;
+
+ return ret;
+}
+
+static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct sh_mmcif_host *host = mmc_priv(mmc);
+ int ret;
+
+ WATCHDOG_RESET();
+
+ switch (cmd->cmdidx) {
+ case MMC_CMD_APP_CMD:
+ return TIMEOUT;
+ case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
+ if (data)
+ /* ext_csd */
+ break;
+ else
+ /* send_if_cond cmd (not support) */
+ return TIMEOUT;
+ default:
+ break;
+ }
+ host->sd_error = 0;
+ host->data = data;
+ ret = sh_mmcif_start_cmd(host, data, cmd);
+ host->data = NULL;
+
+ return ret;
+}
+
+static void sh_mmcif_set_ios(struct mmc *mmc)
+{
+ struct sh_mmcif_host *host = mmc_priv(mmc);
+
+ if (mmc->clock)
+ sh_mmcif_clock_control(host, mmc->clock);
+
+ if (mmc->bus_width == 8)
+ host->bus_width = MMC_BUS_WIDTH_8;
+ else if (mmc->bus_width == 4)
+ host->bus_width = MMC_BUS_WIDTH_4;
+ else
+ host->bus_width = MMC_BUS_WIDTH_1;
+
+ debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
+}
+
+static int sh_mmcif_init(struct mmc *mmc)
+{
+ struct sh_mmcif_host *host = mmc_priv(mmc);
+
+ sh_mmcif_sync_reset(host);
+ sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
+ return 0;
+}
+
+int mmcif_mmc_init(void)
+{
+ int ret = 0;
+ struct mmc *mmc;
+ struct sh_mmcif_host *host = NULL;
+
+ mmc = malloc(sizeof(struct mmc));
+ if (!mmc)
+ ret = -ENOMEM;
+ memset(mmc, 0, sizeof(*mmc));
+ host = malloc(sizeof(struct sh_mmcif_host));
+ if (!host)
+ ret = -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ mmc->f_min = CLKDEV_MMC_INIT;
+ mmc->f_max = CLKDEV_EMMC_DATA;
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
+ MMC_MODE_8BIT;
+ memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
+ mmc->send_cmd = sh_mmcif_request;
+ mmc->set_ios = sh_mmcif_set_ios;
+ mmc->init = sh_mmcif_init;
+ host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
+ host->clk = CONFIG_SH_MMCIF_CLK;
+ mmc->priv = host;
+
+ mmc_register(mmc);
+
+ return ret;
+}
--- /dev/null
+/*
+ * MMCIF driver.
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ */
+
+#ifndef _SH_MMCIF_H_
+#define _SH_MMCIF_H_
+
+struct sh_mmcif_regs {
+ unsigned long ce_cmd_set;
+ unsigned long reserved;
+ unsigned long ce_arg;
+ unsigned long ce_arg_cmd12;
+ unsigned long ce_cmd_ctrl;
+ unsigned long ce_block_set;
+ unsigned long ce_clk_ctrl;
+ unsigned long ce_buf_acc;
+ unsigned long ce_resp3;
+ unsigned long ce_resp2;
+ unsigned long ce_resp1;
+ unsigned long ce_resp0;
+ unsigned long ce_resp_cmd12;
+ unsigned long ce_data;
+ unsigned long reserved2[2];
+ unsigned long ce_int;
+ unsigned long ce_int_mask;
+ unsigned long ce_host_sts1;
+ unsigned long ce_host_sts2;
+ unsigned long reserved3[11];
+ unsigned long ce_version;
+};
+
+/* CE_CMD_SET */
+#define CMD_MASK 0x3f000000
+#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
+/* R1/R1b/R3/R4/R5 */
+#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22))
+/* R2 */
+#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22))
+/* R1b */
+#define CMD_SET_RBSY (1 << 21)
+#define CMD_SET_CCSEN (1 << 20)
+/* 1: on data, 0: no data */
+#define CMD_SET_WDAT (1 << 19)
+/* 1: write to card, 0: read from card */
+#define CMD_SET_DWEN (1 << 18)
+/* 1: multi block trans, 0: single */
+#define CMD_SET_CMLTE (1 << 17)
+/* 1: CMD12 auto issue */
+#define CMD_SET_CMD12EN (1 << 16)
+/* index check */
+#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14))
+/* check bits check */
+#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14))
+/* no check */
+#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14))
+/* 1: CRC7 check*/
+#define CMD_SET_CRC7C ((0 << 13) | (0 << 12))
+/* 1: check bits check*/
+#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12))
+/* 1: internal CRC7 check*/
+#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12))
+/* 1: CRC16 check*/
+#define CMD_SET_CRC16C (1 << 10)
+/* 1: not receive CRC status */
+#define CMD_SET_CRCSTE (1 << 8)
+/* 1: tran mission bit "Low" */
+#define CMD_SET_TBIT (1 << 7)
+/* 1: open/drain */
+#define CMD_SET_OPDM (1 << 6)
+#define CMD_SET_CCSH (1 << 5)
+/* 1bit */
+#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0))
+/* 4bit */
+#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0))
+/* 8bit */
+#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0))
+
+/* CE_CMD_CTRL */
+#define CMD_CTRL_BREAK (1 << 0)
+
+/* CE_BLOCK_SET */
+#define BLOCK_SIZE_MASK 0x0000ffff
+
+/* CE_CLK_CTRL */
+#define CLK_ENABLE (1 << 24)
+#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
+#define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
+/* respons timeout */
+#define SRSPTO_256 ((1 << 13) | (0 << 12))
+/* respons busy timeout */
+#define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
+/* read/write timeout */
+#define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
+/* ccs timeout */
+#define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
+
+/* CE_BUF_ACC */
+#define BUF_ACC_DMAWEN (1 << 25)
+#define BUF_ACC_DMAREN (1 << 24)
+#define BUF_ACC_BUSW_32 (0 << 17)
+#define BUF_ACC_BUSW_16 (1 << 17)
+#define BUF_ACC_ATYP (1 << 16)
+
+/* CE_INT */
+#define INT_CCSDE (1 << 29)
+#define INT_CMD12DRE (1 << 26)
+#define INT_CMD12RBE (1 << 25)
+#define INT_CMD12CRE (1 << 24)
+#define INT_DTRANE (1 << 23)
+#define INT_BUFRE (1 << 22)
+#define INT_BUFWEN (1 << 21)
+#define INT_BUFREN (1 << 20)
+#define INT_CCSRCV (1 << 19)
+#define INT_RBSYE (1 << 17)
+#define INT_CRSPE (1 << 16)
+#define INT_CMDVIO (1 << 15)
+#define INT_BUFVIO (1 << 14)
+#define INT_WDATERR (1 << 11)
+#define INT_RDATERR (1 << 10)
+#define INT_RIDXERR (1 << 9)
+#define INT_RSPERR (1 << 8)
+#define INT_CCSTO (1 << 5)
+#define INT_CRCSTO (1 << 4)
+#define INT_WDATTO (1 << 3)
+#define INT_RDATTO (1 << 2)
+#define INT_RBSYTO (1 << 1)
+#define INT_RSPTO (1 << 0)
+#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
+ INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
+ INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
+ INT_RDATTO | INT_RBSYTO | INT_RSPTO)
+#define INT_START_MAGIC 0xD80430C0
+
+/* CE_INT_MASK */
+#define MASK_ALL 0x00000000
+#define MASK_MCCSDE (1 << 29)
+#define MASK_MCMD12DRE (1 << 26)
+#define MASK_MCMD12RBE (1 << 25)
+#define MASK_MCMD12CRE (1 << 24)
+#define MASK_MDTRANE (1 << 23)
+#define MASK_MBUFRE (1 << 22)
+#define MASK_MBUFWEN (1 << 21)
+#define MASK_MBUFREN (1 << 20)
+#define MASK_MCCSRCV (1 << 19)
+#define MASK_MRBSYE (1 << 17)
+#define MASK_MCRSPE (1 << 16)
+#define MASK_MCMDVIO (1 << 15)
+#define MASK_MBUFVIO (1 << 14)
+#define MASK_MWDATERR (1 << 11)
+#define MASK_MRDATERR (1 << 10)
+#define MASK_MRIDXERR (1 << 9)
+#define MASK_MRSPERR (1 << 8)
+#define MASK_MCCSTO (1 << 5)
+#define MASK_MCRCSTO (1 << 4)
+#define MASK_MWDATTO (1 << 3)
+#define MASK_MRDATTO (1 << 2)
+#define MASK_MRBSYTO (1 << 1)
+#define MASK_MRSPTO (1 << 0)
+
+/* CE_HOST_STS1 */
+#define STS1_CMDSEQ (1 << 31)
+
+/* CE_HOST_STS2 */
+#define STS2_CRCSTE (1 << 31)
+#define STS2_CRC16E (1 << 30)
+#define STS2_AC12CRCE (1 << 29)
+#define STS2_RSPCRC7E (1 << 28)
+#define STS2_CRCSTEBE (1 << 27)
+#define STS2_RDATEBE (1 << 26)
+#define STS2_AC12REBE (1 << 25)
+#define STS2_RSPEBE (1 << 24)
+#define STS2_AC12IDXE (1 << 23)
+#define STS2_RSPIDXE (1 << 22)
+#define STS2_CCSTO (1 << 15)
+#define STS2_RDATTO (1 << 14)
+#define STS2_DATBSYTO (1 << 13)
+#define STS2_CRCSTTO (1 << 12)
+#define STS2_AC12BSYTO (1 << 11)
+#define STS2_RSPBSYTO (1 << 10)
+#define STS2_AC12RSPTO (1 << 9)
+#define STS2_RSPTO (1 << 8)
+
+#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
+ STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
+#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
+ STS2_DATBSYTO | STS2_CRCSTTO | \
+ STS2_AC12BSYTO | STS2_RSPBSYTO | \
+ STS2_AC12RSPTO | STS2_RSPTO)
+
+/* CE_VERSION */
+#define SOFT_RST_ON (1 << 31)
+#define SOFT_RST_OFF (0 << 31)
+
+#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
+#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */
+
+#define MMC_BUS_WIDTH_1 0
+#define MMC_BUS_WIDTH_4 2
+#define MMC_BUS_WIDTH_8 3
+
+struct sh_mmcif_host {
+ struct mmc_data *data;
+ struct sh_mmcif_regs *regs;
+ unsigned int clk;
+ int bus_width;
+ u16 wait_int;
+ u16 sd_error;
+ u8 last_cmd;
+};
+
+static inline u32 sh_mmcif_read(unsigned long *reg)
+{
+ return readl(reg);
+}
+
+static inline void sh_mmcif_write(u32 val, unsigned long *reg)
+{
+ writel(val, reg);
+}
+
+static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
+{
+ sh_mmcif_write(val | sh_mmcif_read(reg), reg);
+}
+
+static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
+{
+ sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
+}
+
+#endif /* _SH_MMCIF_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ * Portions Copyright 2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/clk_rst.h>
+#include "tegra2_mmc.h"
+
+/* support 4 mmc hosts */
+struct mmc mmc_dev[4];
+struct mmc_host mmc_host[4];
+
+static inline struct tegra2_mmc *tegra2_get_base_mmc(int dev_index)
+{
+ unsigned long offset;
+ debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
+
+ switch (dev_index) {
+ case 0:
+ offset = TEGRA2_SDMMC4_BASE;
+ break;
+ case 1:
+ offset = TEGRA2_SDMMC3_BASE;
+ break;
+ case 2:
+ offset = TEGRA2_SDMMC2_BASE;
+ break;
+ case 3:
+ offset = TEGRA2_SDMMC1_BASE;
+ break;
+ default:
+ offset = TEGRA2_SDMMC4_BASE;
+ break;
+ }
+
+ return (struct tegra2_mmc *)(offset);
+}
+
+static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
+{
+ unsigned char ctrl;
+
+ debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
+ (u32)data->dest, data->blocks, data->blocksize);
+
+ writel((u32)data->dest, &host->reg->sysad);
+ /*
+ * DMASEL[4:3]
+ * 00 = Selects SDMA
+ * 01 = Reserved
+ * 10 = Selects 32-bit Address ADMA2
+ * 11 = Selects 64-bit Address ADMA2
+ */
+ ctrl = readb(&host->reg->hostctl);
+ ctrl &= ~(3 << 3); /* SDMA */
+ writeb(ctrl, &host->reg->hostctl);
+
+ /* We do not handle DMA boundaries, so set it to max (512 KiB) */
+ writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
+ writew(data->blocks, &host->reg->blkcnt);
+}
+
+static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
+{
+ unsigned short mode;
+ debug(" mmc_set_transfer_mode called\n");
+ /*
+ * TRNMOD
+ * MUL1SIN0[5] : Multi/Single Block Select
+ * RD1WT0[4] : Data Transfer Direction Select
+ * 1 = read
+ * 0 = write
+ * ENACMD12[2] : Auto CMD12 Enable
+ * ENBLKCNT[1] : Block Count Enable
+ * ENDMA[0] : DMA Enable
+ */
+ mode = (1 << 1) | (1 << 0);
+ if (data->blocks > 1)
+ mode |= (1 << 5);
+ if (data->flags & MMC_DATA_READ)
+ mode |= (1 << 4);
+
+ writew(mode, &host->reg->trnmod);
+}
+
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc_host *host = (struct mmc_host *)mmc->priv;
+ int flags, i;
+ unsigned int timeout;
+ unsigned int mask;
+ unsigned int retry = 0x100000;
+ debug(" mmc_send_cmd called\n");
+
+ /* Wait max 10 ms */
+ timeout = 10;
+
+ /*
+ * PRNSTS
+ * CMDINHDAT[1] : Command Inhibit (DAT)
+ * CMDINHCMD[0] : Command Inhibit (CMD)
+ */
+ mask = (1 << 0);
+ if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
+ mask |= (1 << 1);
+
+ /*
+ * We shouldn't wait for data inhibit for stop commands, even
+ * though they might use busy signaling
+ */
+ if (data)
+ mask &= ~(1 << 1);
+
+ while (readl(&host->reg->prnsts) & mask) {
+ if (timeout == 0) {
+ printf("%s: timeout error\n", __func__);
+ return -1;
+ }
+ timeout--;
+ udelay(1000);
+ }
+
+ if (data)
+ mmc_prepare_data(host, data);
+
+ debug("cmd->arg: %08x\n", cmd->cmdarg);
+ writel(cmd->cmdarg, &host->reg->argument);
+
+ if (data)
+ mmc_set_transfer_mode(host, data);
+
+ if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
+ return -1;
+
+ /*
+ * CMDREG
+ * CMDIDX[13:8] : Command index
+ * DATAPRNT[5] : Data Present Select
+ * ENCMDIDX[4] : Command Index Check Enable
+ * ENCMDCRC[3] : Command CRC Check Enable
+ * RSPTYP[1:0]
+ * 00 = No Response
+ * 01 = Length 136
+ * 10 = Length 48
+ * 11 = Length 48 Check busy after response
+ */
+ if (!(cmd->resp_type & MMC_RSP_PRESENT))
+ flags = 0;
+ else if (cmd->resp_type & MMC_RSP_136)
+ flags = (1 << 0);
+ else if (cmd->resp_type & MMC_RSP_BUSY)
+ flags = (3 << 0);
+ else
+ flags = (2 << 0);
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ flags |= (1 << 3);
+ if (cmd->resp_type & MMC_RSP_OPCODE)
+ flags |= (1 << 4);
+ if (data)
+ flags |= (1 << 5);
+
+ debug("cmd: %d\n", cmd->cmdidx);
+
+ writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
+
+ for (i = 0; i < retry; i++) {
+ mask = readl(&host->reg->norintsts);
+ /* Command Complete */
+ if (mask & (1 << 0)) {
+ if (!data)
+ writel(mask, &host->reg->norintsts);
+ break;
+ }
+ }
+
+ if (i == retry) {
+ printf("%s: waiting for status update\n", __func__);
+ return TIMEOUT;
+ }
+
+ if (mask & (1 << 16)) {
+ /* Timeout Error */
+ debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
+ return TIMEOUT;
+ } else if (mask & (1 << 15)) {
+ /* Error Interrupt */
+ debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
+ return -1;
+ }
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136) {
+ /* CRC is stripped so we need to do some shifting. */
+ for (i = 0; i < 4; i++) {
+ unsigned int offset =
+ (unsigned int)(&host->reg->rspreg3 - i);
+ cmd->response[i] = readl(offset) << 8;
+
+ if (i != 3) {
+ cmd->response[i] |=
+ readb(offset - 1);
+ }
+ debug("cmd->resp[%d]: %08x\n",
+ i, cmd->response[i]);
+ }
+ } else if (cmd->resp_type & MMC_RSP_BUSY) {
+ for (i = 0; i < retry; i++) {
+ /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
+ if (readl(&host->reg->prnsts)
+ & (1 << 20)) /* DAT[0] */
+ break;
+ }
+
+ if (i == retry) {
+ printf("%s: card is still busy\n", __func__);
+ return TIMEOUT;
+ }
+
+ cmd->response[0] = readl(&host->reg->rspreg0);
+ debug("cmd->resp[0]: %08x\n", cmd->response[0]);
+ } else {
+ cmd->response[0] = readl(&host->reg->rspreg0);
+ debug("cmd->resp[0]: %08x\n", cmd->response[0]);
+ }
+ }
+
+ if (data) {
+ while (1) {
+ mask = readl(&host->reg->norintsts);
+
+ if (mask & (1 << 15)) {
+ /* Error Interrupt */
+ writel(mask, &host->reg->norintsts);
+ printf("%s: error during transfer: 0x%08x\n",
+ __func__, mask);
+ return -1;
+ } else if (mask & (1 << 3)) {
+ /* DMA Interrupt */
+ debug("DMA end\n");
+ break;
+ } else if (mask & (1 << 1)) {
+ /* Transfer Complete */
+ debug("r/w is done\n");
+ break;
+ }
+ }
+ writel(mask, &host->reg->norintsts);
+ }
+
+ udelay(1000);
+ return 0;
+}
+
+static void mmc_change_clock(struct mmc_host *host, uint clock)
+{
+ int div, hw_div;
+ unsigned short clk;
+ unsigned long timeout;
+ unsigned int reg, hostbase;
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ debug(" mmc_change_clock called\n");
+
+ /* Change Tegra2 SDMMCx clock divisor here */
+ /* Source is 216MHz, PLLP_OUT0 */
+ if (clock == 0)
+ goto out;
+
+ div = 1;
+ if (clock <= 400000) {
+ hw_div = ((9-1)<<1); /* Best match is 375KHz */
+ div = 64;
+ } else if (clock <= 20000000)
+ hw_div = ((11-1)<<1); /* Best match is 19.6MHz */
+ else if (clock <= 26000000)
+ hw_div = ((9-1)<<1); /* Use 24MHz */
+ else
+ hw_div = ((4-1)<<1) + 1; /* 4.5 divisor for 48MHz */
+
+ debug("mmc_change_clock: hw_div = %d, card clock div = %d\n",
+ hw_div, div);
+
+ /* Change SDMMCx divisor */
+
+ hostbase = readl(&host->base);
+ debug("mmc_change_clock: hostbase = %08X\n", hostbase);
+
+ if (hostbase == TEGRA2_SDMMC1_BASE) {
+ reg = readl(&clkrst->crc_clk_src_sdmmc1);
+ reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
+ reg |= hw_div; /* n-1 */
+ writel(reg, &clkrst->crc_clk_src_sdmmc1);
+ } else if (hostbase == TEGRA2_SDMMC2_BASE) {
+ reg = readl(&clkrst->crc_clk_src_sdmmc2);
+ reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
+ reg |= hw_div; /* n-1 */
+ writel(reg, &clkrst->crc_clk_src_sdmmc2);
+ } else if (hostbase == TEGRA2_SDMMC3_BASE) {
+ reg = readl(&clkrst->crc_clk_src_sdmmc3);
+ reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
+ reg |= hw_div; /* n-1 */
+ writel(reg, &clkrst->crc_clk_src_sdmmc3);
+ } else {
+ reg = readl(&clkrst->crc_clk_src_sdmmc4);
+ reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
+ reg |= hw_div; /* n-1 */
+ writel(reg, &clkrst->crc_clk_src_sdmmc4);
+ }
+
+ writew(0, &host->reg->clkcon);
+
+ div >>= 1;
+ /*
+ * CLKCON
+ * SELFREQ[15:8] : base clock divided by value
+ * ENSDCLK[2] : SD Clock Enable
+ * STBLINTCLK[1] : Internal Clock Stable
+ * ENINTCLK[0] : Internal Clock Enable
+ */
+ clk = (div << 8) | (1 << 0);
+ writew(clk, &host->reg->clkcon);
+
+ /* Wait max 10 ms */
+ timeout = 10;
+ while (!(readw(&host->reg->clkcon) & (1 << 1))) {
+ if (timeout == 0) {
+ printf("%s: timeout error\n", __func__);
+ return;
+ }
+ timeout--;
+ udelay(1000);
+ }
+
+ clk |= (1 << 2);
+ writew(clk, &host->reg->clkcon);
+
+ debug("mmc_change_clock: clkcon = %08X\n", clk);
+ debug("mmc_change_clock: CLK_SOURCE_SDMMCx = %08X\n", reg);
+
+out:
+ host->clock = clock;
+}
+
+static void mmc_set_ios(struct mmc *mmc)
+{
+ struct mmc_host *host = mmc->priv;
+ unsigned char ctrl;
+ debug(" mmc_set_ios called\n");
+
+ debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
+
+ /* Change clock first */
+
+ mmc_change_clock(host, mmc->clock);
+
+ ctrl = readb(&host->reg->hostctl);
+
+ /*
+ * WIDE8[5]
+ * 0 = Depend on WIDE4
+ * 1 = 8-bit mode
+ * WIDE4[1]
+ * 1 = 4-bit mode
+ * 0 = 1-bit mode
+ */
+ if (mmc->bus_width == 8)
+ ctrl |= (1 << 5);
+ else if (mmc->bus_width == 4)
+ ctrl |= (1 << 1);
+ else
+ ctrl &= ~(1 << 1);
+
+ writeb(ctrl, &host->reg->hostctl);
+ debug("mmc_set_ios: hostctl = %08X\n", ctrl);
+}
+
+static void mmc_reset(struct mmc_host *host)
+{
+ unsigned int timeout;
+ debug(" mmc_reset called\n");
+
+ /*
+ * RSTALL[0] : Software reset for all
+ * 1 = reset
+ * 0 = work
+ */
+ writeb((1 << 0), &host->reg->swrst);
+
+ host->clock = 0;
+
+ /* Wait max 100 ms */
+ timeout = 100;
+
+ /* hw clears the bit when it's done */
+ while (readb(&host->reg->swrst) & (1 << 0)) {
+ if (timeout == 0) {
+ printf("%s: timeout error\n", __func__);
+ return;
+ }
+ timeout--;
+ udelay(1000);
+ }
+}
+
+static int mmc_core_init(struct mmc *mmc)
+{
+ struct mmc_host *host = (struct mmc_host *)mmc->priv;
+ unsigned int mask;
+ debug(" mmc_core_init called\n");
+
+ mmc_reset(host);
+
+ host->version = readw(&host->reg->hcver);
+ debug("host version = %x\n", host->version);
+
+ /* mask all */
+ writel(0xffffffff, &host->reg->norintstsen);
+ writel(0xffffffff, &host->reg->norintsigen);
+
+ writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
+ /*
+ * NORMAL Interrupt Status Enable Register init
+ * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
+ * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
+ * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
+ * [0] ENSTACMDCMPLT : Command Complete Status Enable
+ */
+ mask = readl(&host->reg->norintstsen);
+ mask &= ~(0xffff);
+ mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
+ writel(mask, &host->reg->norintstsen);
+
+ /*
+ * NORMAL Interrupt Signal Enable Register init
+ * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
+ */
+ mask = readl(&host->reg->norintsigen);
+ mask &= ~(0xffff);
+ mask |= (1 << 1);
+ writel(mask, &host->reg->norintsigen);
+
+ return 0;
+}
+
+static int tegra2_mmc_initialize(int dev_index, int bus_width)
+{
+ struct mmc *mmc;
+
+ debug(" mmc_initialize called\n");
+
+ mmc = &mmc_dev[dev_index];
+
+ sprintf(mmc->name, "Tegra2 SD/MMC");
+ mmc->priv = &mmc_host[dev_index];
+ mmc->send_cmd = mmc_send_cmd;
+ mmc->set_ios = mmc_set_ios;
+ mmc->init = mmc_core_init;
+
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ if (bus_width == 8)
+ mmc->host_caps = MMC_MODE_8BIT;
+ else
+ mmc->host_caps = MMC_MODE_4BIT;
+ mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ /*
+ * min freq is for card identification, and is the highest
+ * low-speed SDIO card frequency (actually 400KHz)
+ * max freq is highest HS eMMC clock as per the SD/MMC spec
+ * (actually 52MHz)
+ * Both of these are the closest equivalents w/216MHz source
+ * clock and Tegra2 SDMMC divisors.
+ */
+ mmc->f_min = 375000;
+ mmc->f_max = 48000000;
+
+ mmc_host[dev_index].clock = 0;
+ mmc_host[dev_index].reg = tegra2_get_base_mmc(dev_index);
+ mmc_host[dev_index].base = (unsigned int)mmc_host[dev_index].reg;
+ mmc_register(mmc);
+
+ return 0;
+}
+
+int tegra2_mmc_init(int dev_index, int bus_width)
+{
+ debug(" tegra2_mmc_init: index %d, bus width %d\n",
+ dev_index, bus_width);
+ return tegra2_mmc_initialize(dev_index, bus_width);
+}
--- /dev/null
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Portions Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __TEGRA2_MMC_H_
+#define __TEGRA2_MMC_H_
+
+#define TEGRA2_SDMMC1_BASE 0xC8000000
+#define TEGRA2_SDMMC2_BASE 0xC8000200
+#define TEGRA2_SDMMC3_BASE 0xC8000400
+#define TEGRA2_SDMMC4_BASE 0xC8000600
+
+#ifndef __ASSEMBLY__
+struct tegra2_mmc {
+ unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
+ unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
+ unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
+ unsigned int argument; /* _ARGUMENT_0 */
+ unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
+ unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
+ unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
+ unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
+ unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
+ unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
+ unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
+ unsigned int prnsts; /* _PRESENT_STATE_0 */
+ unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
+ unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
+ unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
+ unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
+ unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
+ unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
+ unsigned char swrst; /* _SW_RESET_ 31:24 */
+ unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
+ unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
+ unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
+ unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
+ unsigned char res1[2]; /* _RESERVED 31:16 */
+ unsigned int capareg; /* _CAPABILITIES_0 */
+ unsigned char res2[4]; /* RESERVED, offset 44h-47h */
+ unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
+ unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
+ unsigned short setacmd12err; /* offset 50h */
+ unsigned short setinterr; /* offset 52h */
+ unsigned char admaerr; /* offset 54h */
+ unsigned char res4[3]; /* RESERVED, offset 55h-57h */
+ unsigned long admaaddr; /* offset 58h-5Fh */
+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
+ unsigned short slotintstatus; /* offset FCh */
+ unsigned short hcver; /* HOST Version */
+ unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
+};
+
+struct mmc_host {
+ struct tegra2_mmc *reg;
+ unsigned int version; /* SDHCI spec. version */
+ unsigned int clock; /* Current clock (MHz) */
+ unsigned int base; /* Base address, SDMMC1/2/3/4 */
+};
+
+int tegra2_mmc_init(int dev_index, int bus_width);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __TEGRA2_MMC_H_ */
#endif
/* Wait for command completion */
+#ifdef CONFIG_SYS_LOW_RES_TIMER
reset_timer();
+#endif
start = get_timer (0);
while (flash_is_busy (info, sector)) {
if (get_timer (start) > tout) {
#endif
/* Wait for command completion */
+#ifdef CONFIG_SYS_LOW_RES_TIMER
reset_timer();
+#endif
start = get_timer(0);
while (1) {
switch (info->portwidth) {
{
struct spi_slave *slave;
char buf[3];
+ ulong start;
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if(spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END))
return -1;
- reset_timer_masked();
+ start = get_timer(0);
do {
buf[0] = SPI_EEPROM_RDSR;
buf[1] = 0;
if (!(buf[1] & 1))
break;
- } while (get_timer_masked() < CONFIG_SYS_SPI_WRITE_TOUT);
+ } while (get_timer(start) < CONFIG_SYS_SPI_WRITE_TOUT);
if (buf[1] & 1)
printf ("*** spi_write: Time out while writing!\n");
#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
-#define EON_ID_EN25Q128 0x18
-
struct eon_spi_flash_params {
u8 idcode1;
u16 page_size;
const char *name;
};
-/* spi_flash needs to be first so upper layers can free() it */
-struct eon_spi_flash {
- struct spi_flash flash;
- const struct eon_spi_flash_params *params;
-};
-
-static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash)
-{
- return container_of(flash, struct eon_spi_flash, flash);
-}
-
static const struct eon_spi_flash_params eon_spi_flash_table[] = {
{
- .idcode1 = EON_ID_EN25Q128,
+ .idcode1 = 0x18,
.page_size = 256,
.pages_per_sector = 16,
.sectors_per_block = 16,
},
};
-static int eon_write(struct spi_flash *flash,
- u32 offset, size_t len, const void *buf)
-{
- struct eon_spi_flash *eon = to_eon_spi_flash(flash);
- unsigned long page_addr;
- unsigned long byte_addr;
- unsigned long page_size;
- size_t chunk_len;
- size_t actual;
- int ret;
- u8 cmd[4];
-
- page_size = eon->params->page_size;
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- ret = 0;
- for (actual = 0; actual < len; actual += chunk_len) {
- chunk_len = min(len - actual, page_size - byte_addr);
-
- cmd[0] = CMD_EN25Q128_PP;
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
-
- debug
- ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- break;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: EON Page Program failed\n");
- break;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- break;
-
- page_addr++;
- byte_addr = 0;
- }
-
- debug("SF: EON: Successfully programmed %u bytes @ 0x%x\n",
- len, offset);
-
- spi_release_bus(flash->spi);
- return ret;
-}
-
static int eon_erase(struct spi_flash *flash, u32 offset, size_t len)
{
return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len);
struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
{
const struct eon_spi_flash_params *params;
- struct eon_spi_flash *eon;
+ struct spi_flash *flash;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
return NULL;
}
- eon = malloc(sizeof(*eon));
- if (!eon) {
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
debug("SF: Failed to allocate memory\n");
return NULL;
}
- eon->params = params;
- eon->flash.spi = spi;
- eon->flash.name = params->name;
+ flash->spi = spi;
+ flash->name = params->name;
- eon->flash.write = eon_write;
- eon->flash.erase = eon_erase;
- eon->flash.read = spi_flash_cmd_read_fast;
- eon->flash.sector_size = params->page_size * params->pages_per_sector
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = eon_erase;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->page_size = params->page_size;
+ flash->sector_size = params->page_size * params->pages_per_sector
* params->sectors_per_block;
- eon->flash.size = params->page_size * params->pages_per_sector
+ flash->size = params->page_size * params->pages_per_sector
* params->nr_sectors;
- return &eon->flash;
+ return flash;
}
const char *name;
};
-struct macronix_spi_flash {
- struct spi_flash flash;
- const struct macronix_spi_flash_params *params;
-};
-
-static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash
- *flash)
-{
- return container_of(flash, struct macronix_spi_flash, flash);
-}
-
static const struct macronix_spi_flash_params macronix_spi_flash_table[] = {
{
.idcode = 0x2015,
},
};
-static int macronix_write(struct spi_flash *flash,
- u32 offset, size_t len, const void *buf)
-{
- struct macronix_spi_flash *mcx = to_macronix_spi_flash(flash);
- unsigned long page_addr;
- unsigned long byte_addr;
- unsigned long page_size;
- size_t chunk_len;
- size_t actual;
- int ret;
- u8 cmd[4];
-
- page_size = mcx->params->page_size;
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- ret = 0;
- for (actual = 0; actual < len; actual += chunk_len) {
- chunk_len = min(len - actual, page_size - byte_addr);
-
- cmd[0] = CMD_MX25XX_PP;
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
-
- debug
- ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- break;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: Macronix Page Program failed\n");
- break;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- break;
-
- page_addr++;
- byte_addr = 0;
- }
-
- debug("SF: Macronix: Successfully programmed %u bytes @ 0x%x\n",
- len, offset);
-
- spi_release_bus(flash->spi);
- return ret;
-}
-
static int macronix_erase(struct spi_flash *flash, u32 offset, size_t len)
{
return spi_flash_cmd_erase(flash, CMD_MX25XX_BE, offset, len);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
{
const struct macronix_spi_flash_params *params;
- struct macronix_spi_flash *mcx;
+ struct spi_flash *flash;
unsigned int i;
u16 id = idcode[2] | idcode[1] << 8;
return NULL;
}
- mcx = malloc(sizeof(*mcx));
- if (!mcx) {
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
debug("SF: Failed to allocate memory\n");
return NULL;
}
- mcx->params = params;
- mcx->flash.spi = spi;
- mcx->flash.name = params->name;
+ flash->spi = spi;
+ flash->name = params->name;
- mcx->flash.write = macronix_write;
- mcx->flash.erase = macronix_erase;
- mcx->flash.read = spi_flash_cmd_read_fast;
- mcx->flash.sector_size = params->page_size * params->pages_per_sector
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = macronix_erase;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->page_size = params->page_size;
+ flash->sector_size = params->page_size * params->pages_per_sector
* params->sectors_per_block;
- mcx->flash.size = mcx->flash.sector_size * params->nr_blocks;
+ flash->size = flash->sector_size * params->nr_blocks;
- return &mcx->flash;
+ return flash;
}
if (command == CMD_RAMTRON_WRITE) {
/* send WREN */
- ret = spi_flash_cmd(flash->spi, CMD_RAMTRON_WREN, NULL, 0);
+ ret = spi_flash_cmd_write_enable(flash);
if (ret < 0) {
debug("SF: Enabling Write failed\n");
goto releasebus;
const char *name;
};
-struct spansion_spi_flash {
- struct spi_flash flash;
- const struct spansion_spi_flash_params *params;
-};
-
-static inline struct spansion_spi_flash *to_spansion_spi_flash(struct spi_flash
- *flash)
-{
- return container_of(flash, struct spansion_spi_flash, flash);
-}
-
static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
{
.idcode1 = SPSN_ID_S25FL008A,
},
};
-static int spansion_write(struct spi_flash *flash,
- u32 offset, size_t len, const void *buf)
-{
- struct spansion_spi_flash *spsn = to_spansion_spi_flash(flash);
- unsigned long page_addr;
- unsigned long byte_addr;
- unsigned long page_size;
- size_t chunk_len;
- size_t actual;
- int ret;
- u8 cmd[4];
-
- page_size = spsn->params->page_size;
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- ret = 0;
- for (actual = 0; actual < len; actual += chunk_len) {
- chunk_len = min(len - actual, page_size - byte_addr);
-
- cmd[0] = CMD_S25FLXX_PP;
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
-
- debug
- ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- break;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: SPANSION Page Program failed\n");
- break;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- break;
-
- page_addr++;
- byte_addr = 0;
- }
-
- debug("SF: SPANSION: Successfully programmed %u bytes @ 0x%x\n",
- len, offset);
-
- spi_release_bus(flash->spi);
- return ret;
-}
-
static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len)
{
return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len);
struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
{
const struct spansion_spi_flash_params *params;
- struct spansion_spi_flash *spsn;
+ struct spi_flash *flash;
unsigned int i;
unsigned short jedec, ext_jedec;
return NULL;
}
- spsn = malloc(sizeof(struct spansion_spi_flash));
- if (!spsn) {
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
debug("SF: Failed to allocate memory\n");
return NULL;
}
- spsn->params = params;
- spsn->flash.spi = spi;
- spsn->flash.name = params->name;
+ flash->spi = spi;
+ flash->name = params->name;
- spsn->flash.write = spansion_write;
- spsn->flash.erase = spansion_erase;
- spsn->flash.read = spi_flash_cmd_read_fast;
- spsn->flash.sector_size = params->page_size * params->pages_per_sector;
- spsn->flash.size = spsn->flash.sector_size * params->nr_sectors;
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = spansion_erase;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->page_size = params->page_size;
+ flash->sector_size = params->page_size * params->pages_per_sector;
+ flash->size = flash->sector_size * params->nr_sectors;
- return &spsn->flash;
+ return flash;
}
return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
}
+int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = flash->page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ cmd[0] = CMD_PAGE_PROGRAM;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ debug("SF: write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ break;
+
+ page_addr++;
+ byte_addr = 0;
+ }
+
+ debug("SF: program %s %zu bytes @ %#x\n",
+ ret ? "failure" : "success", len, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len)
{
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], offset);
- ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
+ ret = spi_flash_cmd_write_enable(flash);
if (ret)
goto out;
#define CMD_READ_ARRAY_FAST 0x0b
#define CMD_READ_ARRAY_LEGACY 0xe8
+#define CMD_PAGE_PROGRAM 0x02
+#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05
#define CMD_WRITE_ENABLE 0x06
const void *data, size_t data_len);
/*
+ * Write the requested data out breaking it up into multiple write
+ * commands as needed per the write size.
+ */
+int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf);
+
+/*
+ * Enable writing on the SPI flash.
+ */
+static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
+}
+
+/*
+ * Disable writing on the SPI flash.
+ */
+static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
+}
+
+/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the ->read() operation.
*/
#define SST_SR_AAI (1 << 6) /* Addressing mode */
#define SST_SR_BPL (1 << 7) /* BP bits lock */
+#define SST_FEAT_WP (1 << 0) /* Supports AAI word program */
+#define SST_FEAT_MBP (1 << 1) /* Supports multibyte program */
+
struct sst_spi_flash_params {
u8 idcode1;
+ u8 flags;
u16 nr_sectors;
const char *name;
};
}
#define SST_SECTOR_SIZE (4 * 1024)
+#define SST_PAGE_SIZE 256
static const struct sst_spi_flash_params sst_spi_flash_table[] = {
{
.idcode1 = 0x8d,
+ .flags = SST_FEAT_WP,
.nr_sectors = 128,
.name = "SST25VF040B",
},{
.idcode1 = 0x8e,
+ .flags = SST_FEAT_WP,
.nr_sectors = 256,
.name = "SST25VF080B",
},{
.idcode1 = 0x41,
+ .flags = SST_FEAT_WP,
.nr_sectors = 512,
.name = "SST25VF016B",
},{
.idcode1 = 0x4a,
+ .flags = SST_FEAT_WP,
.nr_sectors = 1024,
.name = "SST25VF032B",
},{
.idcode1 = 0x4b,
+ .flags = SST_FEAT_MBP,
.nr_sectors = 2048,
.name = "SST25VF064C",
},{
.idcode1 = 0x01,
+ .flags = SST_FEAT_WP,
.nr_sectors = 16,
.name = "SST25WF512",
},{
.idcode1 = 0x02,
+ .flags = SST_FEAT_WP,
.nr_sectors = 32,
.name = "SST25WF010",
},{
.idcode1 = 0x03,
+ .flags = SST_FEAT_WP,
.nr_sectors = 64,
.name = "SST25WF020",
},{
.idcode1 = 0x04,
+ .flags = SST_FEAT_WP,
.nr_sectors = 128,
.name = "SST25WF040",
},
static int
sst_enable_writing(struct spi_flash *flash)
{
- int ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0);
+ int ret = spi_flash_cmd_write_enable(flash);
if (ret)
debug("SF: Enabling Write failed\n");
return ret;
static int
sst_disable_writing(struct spi_flash *flash)
{
- int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0);
+ int ret = spi_flash_cmd_write_disable(flash);
if (ret)
debug("SF: Disabling Write failed\n");
return ret;
}
static int
-sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
+sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
{
size_t actual, cmd_len;
int ret;
stm->flash.spi = spi;
stm->flash.name = params->name;
- stm->flash.write = sst_write;
+ if (stm->params->flags & SST_FEAT_WP)
+ stm->flash.write = sst_write_wp;
+ else
+ stm->flash.write = spi_flash_cmd_write_multi;
stm->flash.erase = sst_erase;
stm->flash.read = spi_flash_cmd_read_fast;
+ stm->flash.page_size = SST_PAGE_SIZE;
stm->flash.sector_size = SST_SECTOR_SIZE;
stm->flash.size = stm->flash.sector_size * params->nr_sectors;
#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */
#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */
-#define STM_ID_M25P10 0x11
-#define STM_ID_M25P16 0x15
-#define STM_ID_M25P20 0x12
-#define STM_ID_M25P32 0x16
-#define STM_ID_M25P40 0x13
-#define STM_ID_M25P64 0x17
-#define STM_ID_M25P80 0x14
-#define STM_ID_M25P128 0x18
-
struct stmicro_spi_flash_params {
u8 idcode1;
u16 page_size;
const char *name;
};
-/* spi_flash needs to be first so upper layers can free() it */
-struct stmicro_spi_flash {
- struct spi_flash flash;
- const struct stmicro_spi_flash_params *params;
-};
-
-static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash
- *flash)
-{
- return container_of(flash, struct stmicro_spi_flash, flash);
-}
-
static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = {
{
- .idcode1 = STM_ID_M25P10,
+ .idcode1 = 0x11,
.page_size = 256,
.pages_per_sector = 128,
.nr_sectors = 4,
.name = "M25P10",
},
{
- .idcode1 = STM_ID_M25P16,
+ .idcode1 = 0x15,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 32,
.name = "M25P16",
},
{
- .idcode1 = STM_ID_M25P20,
+ .idcode1 = 0x12,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 4,
.name = "M25P20",
},
{
- .idcode1 = STM_ID_M25P32,
+ .idcode1 = 0x16,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 64,
.name = "M25P32",
},
{
- .idcode1 = STM_ID_M25P40,
+ .idcode1 = 0x13,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 8,
.name = "M25P40",
},
{
- .idcode1 = STM_ID_M25P64,
+ .idcode1 = 0x17,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 128,
.name = "M25P64",
},
{
- .idcode1 = STM_ID_M25P80,
+ .idcode1 = 0x14,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 16,
.name = "M25P80",
},
{
- .idcode1 = STM_ID_M25P128,
+ .idcode1 = 0x18,
.page_size = 256,
.pages_per_sector = 1024,
.nr_sectors = 64,
},
};
-static int stmicro_write(struct spi_flash *flash,
- u32 offset, size_t len, const void *buf)
-{
- struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash);
- unsigned long page_addr;
- unsigned long byte_addr;
- unsigned long page_size;
- size_t chunk_len;
- size_t actual;
- int ret;
- u8 cmd[4];
-
- page_size = stm->params->page_size;
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- ret = 0;
- for (actual = 0; actual < len; actual += chunk_len) {
- chunk_len = min(len - actual, page_size - byte_addr);
-
- cmd[0] = CMD_M25PXX_PP;
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
-
- debug
- ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- break;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: STMicro Page Program failed\n");
- break;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- break;
-
- page_addr++;
- byte_addr = 0;
- }
-
- debug("SF: STMicro: Successfully programmed %u bytes @ 0x%x\n",
- len, offset);
-
- spi_release_bus(flash->spi);
- return ret;
-}
-
static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len)
{
return spi_flash_cmd_erase(flash, CMD_M25PXX_SE, offset, len);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
{
const struct stmicro_spi_flash_params *params;
- struct stmicro_spi_flash *stm;
+ struct spi_flash *flash;
unsigned int i;
if (idcode[0] == 0xff) {
return NULL;
}
- stm = malloc(sizeof(struct stmicro_spi_flash));
- if (!stm) {
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
debug("SF: Failed to allocate memory\n");
return NULL;
}
- stm->params = params;
- stm->flash.spi = spi;
- stm->flash.name = params->name;
+ flash->spi = spi;
+ flash->name = params->name;
- stm->flash.write = stmicro_write;
- stm->flash.erase = stmicro_erase;
- stm->flash.read = spi_flash_cmd_read_fast;
- stm->flash.sector_size = params->page_size * params->pages_per_sector;
- stm->flash.size = stm->flash.sector_size * params->nr_sectors;
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = stmicro_erase;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->page_size = params->page_size;
+ flash->sector_size = params->page_size * params->pages_per_sector;
+ flash->size = flash->sector_size * params->nr_sectors;
- return &stm->flash;
+ return flash;
}
const char *name;
};
-/* spi_flash needs to be first so upper layers can free() it */
-struct winbond_spi_flash {
- struct spi_flash flash;
- const struct winbond_spi_flash_params *params;
-};
-
-static inline struct winbond_spi_flash *
-to_winbond_spi_flash(struct spi_flash *flash)
-{
- return container_of(flash, struct winbond_spi_flash, flash);
-}
-
static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
{
.id = 0x3015,
},
};
-static int winbond_write(struct spi_flash *flash,
- u32 offset, size_t len, const void *buf)
-{
- struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
- unsigned long page_addr;
- unsigned long byte_addr;
- unsigned long page_size;
- unsigned int page_shift;
- size_t chunk_len;
- size_t actual;
- int ret;
- u8 cmd[4];
-
- page_shift = stm->params->l2_page_size;
- page_size = (1 << page_shift);
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- for (actual = 0; actual < len; actual += chunk_len) {
- chunk_len = min(len - actual, page_size - byte_addr);
-
- cmd[0] = CMD_W25_PP;
- cmd[1] = page_addr >> (16 - page_shift);
- cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8);
- cmd[3] = byte_addr;
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
- buf + actual,
- cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- goto out;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: Winbond Page Program failed\n");
- goto out;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- goto out;
-
- page_addr++;
- byte_addr = 0;
- }
-
- debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n",
- len, offset);
- ret = 0;
-
-out:
- spi_release_bus(flash->spi);
- return ret;
-}
-
static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len)
{
return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
{
const struct winbond_spi_flash_params *params;
- unsigned page_size;
- struct winbond_spi_flash *stm;
+ struct spi_flash *flash;
unsigned int i;
+ unsigned page_size;
for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) {
params = &winbond_spi_flash_table[i];
return NULL;
}
- stm = malloc(sizeof(struct winbond_spi_flash));
- if (!stm) {
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
debug("SF: Failed to allocate memory\n");
return NULL;
}
- stm->params = params;
- stm->flash.spi = spi;
- stm->flash.name = params->name;
+ flash->spi = spi;
+ flash->name = params->name;
/* Assuming power-of-two page size initially. */
page_size = 1 << params->l2_page_size;
- stm->flash.write = winbond_write;
- stm->flash.erase = winbond_erase;
- stm->flash.read = spi_flash_cmd_read_fast;
- stm->flash.sector_size = (1 << stm->params->l2_page_size) *
- stm->params->pages_per_sector;
- stm->flash.size = page_size * params->pages_per_sector
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = winbond_erase;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->page_size = page_size;
+ flash->sector_size = page_size * params->pages_per_sector;
+ flash->size = page_size * params->pages_per_sector
* params->sectors_per_block
* params->nr_blocks;
- return &stm->flash;
+ return flash;
}
rc = 0;
}
- /* handle MAL RX EOB interupt from a receive */
+ /* handle MAL RX EOB interrupt from a receive */
/* check for EOB on valid channels */
if (uic_mal & UIC_MAL_RXEOB) {
mal_eob = mfdcr(MAL0_RXEOBISR);
{
struct dw_eth_dev *priv = dev->priv;
int phy_addr;
- u16 bmcr, ctrl;
+ u16 bmcr;
#if defined(CONFIG_DW_AUTONEG)
u16 bmsr;
u32 timeout;
u16 anlpar, btsr;
+#else
+ u16 ctrl;
#endif
#if defined(CONFIG_DW_SEARCH_PHY)
priv->address = phy_addr;
else
return -1;
+#else
+ phy_addr = priv->address;
#endif
if (dw_reset_phy(dev) < 0)
return -1;
/*
* wait for the related interrupt
*/
- start = get_timer_masked();
+ start = get_timer(0);
while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Read MDIO failed...\n");
/*
* wait for the MII interrupt
*/
- start = get_timer_masked();
+ start = get_timer(0);
while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Write MDIO failed...\n");
/*
* Wait for AN completion
*/
- start = get_timer_masked();
+ start = get_timer(0);
do {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("%s: Autonegotiation timeout\n", dev->name);
GRETH_REGORIN(®s->control, GRETH_RXEN);
}
done:
- /* return positive length of packet or 0 if non recieved */
+ /* return positive length of packet or 0 if non received */
return len;
}
* ready to send and receive packets.
*
* Side effects:
- * leaves the natsemi initialized, and ready to recieve packets.
+ * leaves the natsemi initialized, and ready to receive packets.
*
* Returns: struct eth_device *: pointer to NIC data structure
*/
static int na_mii_poll_busy (void)
{
+ ulong start;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
- while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) {
+ start = get_timer(0));
+ while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) {
if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
return 1;
}
static int reset_eth (void)
{
int pt;
+ ulong start;
na_get_mac_addr ();
pt = na_mii_identify_phy ();
/* reset the phy */
na_mii_write (MII_PHY_CONTROL, 0x8000);
- reset_timer_masked ();
- while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) {
+ start = get_timer(0);
+ while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) {
if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
break;
}
}
- if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY)
+ if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY)
printf ("phy reset timeout\n");
/* set the PCS reg */
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
- * Side effects: initializes ns8382xs, ready to recieve packets.
+ * Side effects: initializes ns8382xs, ready to receive packets.
* Returns: int: number of cards found
*/
int gen10g_startup(struct phy_device *phydev)
{
int devad, reg;
- u32 mmd_mask = phydev->mmds;
+ u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK;
phydev->link = 1;
phydev->speed = SPEED_10000;
phydev->duplex = DUPLEX_FULL;
+ /*
+ * Go through all the link-reporting devices, and make sure
+ * they're all up and happy
+ */
for (devad = 0; mmd_mask; devad++, mmd_mask = mmd_mask >> 1) {
- if (!mmd_mask & 1)
+ if (!(mmd_mask & 1))
continue;
/* Read twice because link state is latched and a
#define WUCSR_MPEN 0x00000002
/* Chip ID values */
+#define CHIP_89218 0x218a
#define CHIP_9115 0x115
#define CHIP_9116 0x116
#define CHIP_9117 0x117
};
static const struct chip_id chip_ids[] = {
+ { CHIP_89218, "LAN89218" },
{ CHIP_9115, "LAN9115" },
{ CHIP_9116, "LAN9116" },
{ CHIP_9117, "LAN9117" },
hose->current_busno = hose->first_busno;
out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
- out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
+ out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
* - Master abort (pci)
* - Master PERR (pci)
* - ICCA (PCIe)
volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */
volatile ulong ctr; /* MBAR+0x810: current time register */
volatile ulong cdr; /* MBAR+0x814: current data register */
- volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interupt register */
+ volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */
volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */
volatile ulong trdr; /* MBAR+0x820: test register/divides register */
} RTC5200;
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o
+
+ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
+endif
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
*/
#include <common.h>
+#include <linux/compiler.h>
#include <ns16550.h>
#ifdef CONFIG_NS87308
serial_puts_dev(port, s);}
/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port,name,bus) {\
+#define INIT_ESERIAL_STRUCTURE(port, name) {\
name,\
- bus,\
eserial##port##_init,\
NULL,\
eserial##port##_setbrg,\
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device eserial1_device =
- INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1");
+ INIT_ESERIAL_STRUCTURE(1, "eserial0");
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device eserial2_device =
- INIT_ESERIAL_STRUCTURE(2,"eserial1","EUART2");
+ INIT_ESERIAL_STRUCTURE(2, "eserial1");
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device eserial3_device =
- INIT_ESERIAL_STRUCTURE(3,"eserial2","EUART3");
+ INIT_ESERIAL_STRUCTURE(3, "eserial2");
DECLARE_ESERIAL_FUNCTIONS(4);
struct serial_device eserial4_device =
- INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4");
+ INIT_ESERIAL_STRUCTURE(4, "eserial3");
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ return &eserial1_device;
+#elif CONFIG_CONS_INDEX == 2
+ return &eserial2_device;
+#elif CONFIG_CONS_INDEX == 3
+ return &eserial3_device;
+#elif CONFIG_CONS_INDEX == 4
+ return &eserial4_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
+#endif
+}
+
#endif /* CONFIG_SERIAL_MULTI */
struct serial_device serial_ffuart_device =
{
"serial_ffuart",
- "PXA",
ffuart_init,
NULL,
ffuart_setbrg,
struct serial_device serial_btuart_device =
{
"serial_btuart",
- "PXA",
btuart_init,
NULL,
btuart_setbrg,
struct serial_device serial_stuart_device =
{
"serial_stuart",
- "PXA",
stuart_init,
NULL,
stuart_setbrg,
*/
#include <common.h>
+#include <linux/compiler.h>
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
serial_puts_dev(port, s); \
}
-#define INIT_S3C_SERIAL_STRUCTURE(port, name, bus) { \
+#define INIT_S3C_SERIAL_STRUCTURE(port, name) { \
name, \
- bus, \
s3serial##port##_init, \
NULL,\
s3serial##port##_setbrg, \
#if defined(CONFIG_SERIAL_MULTI)
DECLARE_S3C_SERIAL_FUNCTIONS(0);
struct serial_device s3c24xx_serial0_device =
-INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1");
+INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0");
DECLARE_S3C_SERIAL_FUNCTIONS(1);
struct serial_device s3c24xx_serial1_device =
-INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2");
+INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1");
DECLARE_S3C_SERIAL_FUNCTIONS(2);
struct serial_device s3c24xx_serial2_device =
-INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3");
+INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2");
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if defined(CONFIG_SERIAL1)
+ return &s3c24xx_serial0_device;
+#elif defined(CONFIG_SERIAL2)
+ return &s3c24xx_serial1_device;
+#elif defined(CONFIG_SERIAL3)
+ return &s3c24xx_serial2_device;
+#else
+#error "CONFIG_SERIAL? missing."
+#endif
+}
#endif /* CONFIG_SERIAL_MULTI */
*/
#include <common.h>
+#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/uart.h>
#include <asm/arch/clk.h>
void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
-#define INIT_S5P_SERIAL_STRUCTURE(port, name, bus) { \
+#define INIT_S5P_SERIAL_STRUCTURE(port, name) { \
name, \
- bus, \
s5p_serial##port##_init, \
NULL, \
s5p_serial##port##_setbrg, \
DECLARE_S5P_SERIAL_FUNCTIONS(0);
struct serial_device s5p_serial0_device =
- INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0", "S5PUART0");
+ INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0");
DECLARE_S5P_SERIAL_FUNCTIONS(1);
struct serial_device s5p_serial1_device =
- INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1", "S5PUART1");
+ INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1");
DECLARE_S5P_SERIAL_FUNCTIONS(2);
struct serial_device s5p_serial2_device =
- INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2", "S5PUART2");
+ INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2");
DECLARE_S5P_SERIAL_FUNCTIONS(3);
struct serial_device s5p_serial3_device =
- INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3", "S5PUART3");
+ INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3");
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if defined(CONFIG_SERIAL0)
+ return &s5p_serial0_device;
+#elif defined(CONFIG_SERIAL1)
+ return &s5p_serial1_device;
+#elif defined(CONFIG_SERIAL2)
+ return &s5p_serial2_device;
+#elif defined(CONFIG_SERIAL3)
+ return &s5p_serial3_device;
+#else
+#error "CONFIG_SERIAL? missing."
+#endif
+}
LIB := $(obj)libspi.o
COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
+COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
--- /dev/null
+/*
+ * Driver of Andes SPI Controller
+ *
+ * (C) Copyright 2011 Andes Technology
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/io.h>
+#include "andes_spi.h"
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+static void andes_spi_spit_en(struct andes_spi_slave *ds)
+{
+ unsigned int dcr = readl(&ds->regs->dcr);
+
+ debug("%s: dcr: %x, write value: %x\n",
+ __func__, dcr, (dcr | ANDES_SPI_DCR_SPIT));
+
+ writel((dcr | ANDES_SPI_DCR_SPIT), &ds->regs->dcr);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct andes_spi_slave *ds;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ds = malloc(sizeof(*ds));
+ if (!ds)
+ return NULL;
+
+ ds->slave.bus = bus;
+ ds->slave.cs = cs;
+ ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE;
+
+ /*
+ * The hardware of andes_spi will set its frequency according
+ * to APB/AHB bus clock. Hence the hardware doesn't allow changing of
+ * requency and so the user requested speed is always ignored.
+ */
+ ds->freq = max_hz;
+
+ return &ds->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct andes_spi_slave *ds = to_andes_spi(slave);
+
+ free(ds);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct andes_spi_slave *ds = to_andes_spi(slave);
+ unsigned int apb;
+ unsigned int baud;
+
+ /* Enable the SPI hardware */
+ writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
+ udelay(1000);
+
+ /* setup format */
+ baud = ((CONFIG_SYS_CLK_FREQ / CONFIG_SYS_SPI_CLK / 2) - 1) & 0xFF;
+
+ /*
+ * SPI_CLK = AHB bus clock / ((BAUD + 1)*2)
+ * BAUD = AHB bus clock / SPI_CLK / 2) - 1
+ */
+ apb = (readl(&ds->regs->apb) & 0xffffff00) | baud;
+ writel(apb, &ds->regs->apb);
+
+ /* no interrupts */
+ writel(0, &ds->regs->ie);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct andes_spi_slave *ds = to_andes_spi(slave);
+
+ /* Disable the SPI hardware */
+ writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
+}
+
+static int andes_spi_read(struct spi_slave *slave, unsigned int len,
+ u8 *rxp, unsigned long flags)
+{
+ struct andes_spi_slave *ds = to_andes_spi(slave);
+ unsigned int i, left;
+ unsigned int data;
+
+ debug("%s: slave: %x, len: %d, rxp: %x, flags: %d\n",
+ __func__, slave, len, rxp, flags);
+
+ debug("%s: data: ", __func__);
+ while (len > 0) {
+ left = min(len, 4);
+ data = readl(&ds->regs->data);
+
+ debug(" ");
+ for (i = 0; i < left; i++) {
+ debug("%02x ", data & 0xff);
+ *rxp++ = data;
+ data >>= 8;
+ len--;
+ }
+ }
+ debug("\n");
+
+ return 0;
+}
+
+static int andes_spi_write(struct spi_slave *slave, unsigned int wlen,
+ unsigned int rlen, const u8 *txp, unsigned long flags)
+{
+ struct andes_spi_slave *ds = to_andes_spi(slave);
+ unsigned int data;
+ unsigned int i, left;
+ unsigned int spit_enabled = 0;
+
+ debug("%s: slave: %x, wlen: %d, rlen: %d, txp: %x, flags: %x\n",
+ __func__, slave, wlen, rlen, txp, flags);
+
+ /* The value of wlen and rlen wrote to register must minus 1 */
+ if (rlen == 0) /* write only */
+ writel(ANDES_SPI_DCR_MODE_WO | ANDES_SPI_DCR_WCNT(wlen-1) |
+ ANDES_SPI_DCR_RCNT(0), &ds->regs->dcr);
+ else /* write then read */
+ writel(ANDES_SPI_DCR_MODE_WR | ANDES_SPI_DCR_WCNT(wlen-1) |
+ ANDES_SPI_DCR_RCNT(rlen-1), &ds->regs->dcr);
+
+ /* wait till SPIBSY is cleared */
+ while (readl(&ds->regs->st) & ANDES_SPI_ST_SPIBSY)
+ ;
+
+ /* data write process */
+ debug("%s: txp: ", __func__);
+ while (wlen > 0) {
+ /* clear the data */
+ data = 0;
+
+ /* data are usually be read 32bits once a time */
+ left = min(wlen, 4);
+
+ for (i = 0; i < left; i++) {
+ debug("%x ", *txp);
+ data |= *txp++ << (i * 8);
+ wlen--;
+ }
+ debug("\n");
+
+ debug("data: %08x\n", data);
+ debug("streg before write: %08x\n", readl(&ds->regs->st));
+ /* wait till TXFULL is deasserted */
+ while (readl(&ds->regs->st) & ANDES_SPI_ST_TXFEL)
+ ;
+ writel(data, &ds->regs->data);
+ debug("streg after write: %08x\n", readl(&ds->regs->st));
+
+
+ if (spit_enabled == 0) {
+ /* enable SPIT bit - trigger the tx and rx progress */
+ andes_spi_spit_en(ds);
+ spit_enabled = 1;
+ }
+
+ }
+ debug("\n");
+
+ return 0;
+}
+
+/*
+ * spi_xfer:
+ * Since andes_spi doesn't support independent command transaction,
+ * that is, write and than read must be operated in continuous
+ * execution, there is no need to set dcr and trigger spit again in
+ * RX process.
+ */
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ unsigned int len;
+ static int op_nextime;
+ static u8 tmp_cmd[5];
+ static int tmp_wlen;
+ unsigned int i;
+
+ if (bitlen == 0)
+ /* Finish any previously submitted transfers */
+ goto out;
+
+ if (bitlen % 8) {
+ /* Errors always terminate an ongoing transfer */
+ flags |= SPI_XFER_END;
+ goto out;
+ }
+
+ len = bitlen / 8;
+
+ debug("%s: slave: %08x, bitlen: %d, dout: "
+ "%08x, din: %08x, flags: %d, len: %d\n",
+ __func__, slave, bitlen, dout, din, flags, len);
+
+ /*
+ * Important:
+ * andes_spi's hardware doesn't support 2 data channel. The read
+ * and write cmd/data share the same register (data register).
+ *
+ * If a command has write and read transaction, you cannot do write
+ * this time and then do read on next time.
+ *
+ * A command writes first with a read response must indicating
+ * the read length in write operation. Hence the write action must
+ * be stored temporary and wait until the next read action has been
+ * arrived. Then we flush the write and read action out together.
+ */
+ if (!dout) {
+ if (op_nextime == 1) {
+ /* flags should be SPI_XFER_END, value is 2 */
+ op_nextime = 0;
+ andes_spi_write(slave, tmp_wlen, len, tmp_cmd, flags);
+ }
+ return andes_spi_read(slave, len, din, flags);
+ } else if (!din) {
+ if (flags == SPI_XFER_BEGIN) {
+ /* store the write command and do operation next time */
+ op_nextime = 1;
+ memset(tmp_cmd, 0, sizeof(tmp_cmd));
+ memcpy(tmp_cmd, dout, len);
+
+ debug("%s: tmp_cmd: ", __func__);
+ for (i = 0; i < len; i++)
+ debug("%x ", *(tmp_cmd + i));
+ debug("\n");
+
+ tmp_wlen = len;
+ } else {
+ /*
+ * flags should be (SPI_XFER_BEGIN | SPI_XFER_END),
+ * the value is 3.
+ */
+ if (op_nextime == 1) {
+ /* flags should be SPI_XFER_END, value is 2 */
+ op_nextime = 0;
+ /* flags 3 implies write only */
+ andes_spi_write(slave, tmp_wlen, 0, tmp_cmd, 3);
+ }
+
+ debug("flags: %x\n", flags);
+ return andes_spi_write(slave, len, 0, dout, flags);
+ }
+ }
+
+out:
+ return 0;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
--- /dev/null
+/*
+ * Register definitions for the Andes SPI Controller
+ *
+ * (C) Copyright 2011 Andes Technology
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ANDES_SPI_H
+#define __ANDES_SPI_H
+
+struct andes_spi_regs {
+ unsigned int apb; /* 0x00 - APB SPI interface setting */
+ unsigned int pio; /* 0x04 - PIO reg */
+ unsigned int cr; /* 0x08 - SPI Control reg */
+ unsigned int st; /* 0x0c - SPI Status reg */
+ unsigned int ie; /* 0x10 - Interrupt Enable reg */
+ unsigned int ist; /* 0x14 - Interrupt Status reg */
+ unsigned int dcr; /* 0x18 - data control reg */
+ unsigned int data; /* 0x1c - data register */
+ unsigned int ahb; /* 0x20 - AHB SPI interface setting */
+ unsigned int ver; /* 0x3c - SPI version reg */
+};
+
+#define BIT(x) (1 << (x))
+
+/* 0x00 - APB SPI interface setting register */
+#define ANDES_SPI_APB_BAUD(x) (((x) & 0xff) < 0)
+#define ANDES_SPI_APB_CSHT(x) (((x) & 0xf) < 16)
+#define ANDES_SPI_APB_SPNTS BIT(20) /* 0: normal, 1: delay */
+#define ANDES_SPI_APB_CPHA BIT(24) /* 0: Sampling at odd edges */
+#define ANDES_SPI_APB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
+#define ANDES_SPI_APB_MSSL BIT(26) /* 0: SPI Master, 1: slave */
+
+/* 0x04 - PIO register */
+#define ANDES_SPI_PIO_MISO BIT(0) /* input value of pin MISO */
+#define ANDES_SPI_PIO_MOSI BIT(1) /* I/O value of pin MOSI */
+#define ANDES_SPI_PIO_SCK BIT(2) /* I/O value of pin SCK */
+#define ANDES_SPI_PIO_CS BIT(3) /* I/O value of pin CS */
+#define ANDES_SPI_PIO_PIOE BIT(4) /* Programming IO Enable */
+
+/* 0x08 - SPI Control register */
+#define ANDES_SPI_CR_SPIRST BIT(0) /* SPI mode reset */
+#define ANDES_SPI_CR_RXFRST BIT(1) /* RxFIFO reset */
+#define ANDES_SPI_CR_TXFRST BIT(2) /* TxFIFO reset */
+#define ANDES_SPI_CR_RXFTH(x) (((x) & 0x1f) << 10) /* RxFIFO Threshold */
+#define ANDES_SPI_CR_TXFTH(x) (((x) & 0x1f) << 18) /* TxFIFO Threshold */
+
+/* 0x0c - SPI Status register */
+#define ANDES_SPI_ST_SPIBSY BIT(0) /* SPI Transfer is active */
+#define ANDES_SPI_ST_RXFEM BIT(8) /* RxFIFO Empty Flag */
+#define ANDES_SPI_ST_RXFEL BIT(9) /* RxFIFO Full Flag */
+#define ANDES_SPI_ST_RXFVE(x) (((x) >> 10) & 0x1f)
+#define ANDES_SPI_ST_TXFEM BIT(16) /* TxFIFO Empty Flag */
+#define ANDES_SPI_ST_TXFEL BIT(7) /* TxFIFO Full Flag */
+#define ANDES_SPI_ST_TXFVE(x) (((x) >> 18) & 0x1f)
+
+/* 0x10 - Interrupt Enable register */
+#define ANDES_SPI_IE_RXFORIE BIT(0) /* RxFIFO overrun intr */
+#define ANDES_SPI_IE_TXFURIE BIT(1) /* TxFOFO underrun intr */
+#define ANDES_SPI_IE_RXFTHIE BIT(2) /* RxFIFO threshold intr */
+#define ANDES_SPI_IE_TXFTHIE BIT(3) /* TxFIFO threshold intr */
+#define ANDES_SPI_IE_SPIEIE BIT(4) /* SPI transmit END intr */
+#define ANDES_SPI_IE_SPCFIE BIT(5) /* AHB/APB TxReq conflict */
+
+/* 0x14 - Interrupt Status Register */
+#define ANDES_SPI_IST_RXFORI BIT(0) /* has RxFIFO overrun */
+#define ANDES_SPI_IST_TXFURI BIT(1) /* has TxFOFO underrun */
+#define ANDES_SPI_IST_RXFTHI BIT(2) /* has RxFIFO threshold */
+#define ANDES_SPI_IST_TXFTHI BIT(3) /* has TxFIFO threshold */
+#define ANDES_SPI_IST_SPIEI BIT(4) /* has SPI transmit END */
+#define ANDES_SPI_IST_SPCFI BIT(5) /* has AHB/APB TxReq conflict */
+
+/* 0x18 - Data Control Register */
+#define ANDES_SPI_DCR_RCNT(x) (((x) & 0x3ff) << 0)
+#define ANDES_SPI_DCR_DYCNT(x) (((x) & 0x7) << 12)
+#define ANDES_SPI_DCR_WCNT(x) (((x) & 0x3ff) << 16)
+#define ANDES_SPI_DCR_TRAMODE(x) (((x) & 0x7) << 28)
+#define ANDES_SPI_DCR_SPIT BIT(31) /* SPI bus trigger */
+
+#define ANDES_SPI_DCR_MODE_WRCON ANDES_SPI_DCR_TRAMODE(0) /* w/r at the same time */
+#define ANDES_SPI_DCR_MODE_WO ANDES_SPI_DCR_TRAMODE(1) /* write only */
+#define ANDES_SPI_DCR_MODE_RO ANDES_SPI_DCR_TRAMODE(2) /* read only */
+#define ANDES_SPI_DCR_MODE_WR ANDES_SPI_DCR_TRAMODE(3) /* write, read */
+#define ANDES_SPI_DCR_MODE_RW ANDES_SPI_DCR_TRAMODE(4) /* read, write */
+#define ANDES_SPI_DCR_MODE_WDR ANDES_SPI_DCR_TRAMODE(5) /* write, dummy, read */
+#define ANDES_SPI_DCR_MODE_RDW ANDES_SPI_DCR_TRAMODE(6) /* read, dummy, write */
+#define ANDES_SPI_DCR_MODE_RECEIVE ANDES_SPI_DCR_TRAMODE(7) /* receive */
+
+/* 0x20 - AHB SPI interface setting register */
+#define ANDES_SPI_AHB_BAUD(x) (((x) & 0xff) < 0)
+#define ANDES_SPI_AHB_CSHT(x) (((x) & 0xf) < 16)
+#define ANDES_SPI_AHB_SPNTS BIT(20) /* 0: normal, 1: delay */
+#define ANDES_SPI_AHB_CPHA BIT(24) /* 0: Sampling at odd edges */
+#define ANDES_SPI_AHB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
+#define ANDES_SPI_AHB_MSSL BIT(26) /* only Master mode */
+
+/* 0x3c - Version Register - (Year V.MAJOR.MINOR) */
+#define ANDES_SPI_VER_MINOR(x) (((x) >> 0) & 0xf)
+#define ANDES_SPI_VER_MAJOR(x) (((x) >> 8) & 0xf)
+#define ANDES_SPI_VER_YEAR(x) (((x) >> 16) & 0xf)
+
+struct andes_spi_slave {
+ struct spi_slave slave;
+ struct andes_spi_regs *regs;
+ unsigned int freq;
+};
+
+static inline struct andes_spi_slave *to_andes_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct andes_spi_slave, slave);
+}
+
+#endif /* __ANDES_SPI_H */
0x53f84000,
};
-#define mxc_get_clock(x) mx31_get_ipg_clk()
-
#elif defined(CONFIG_MX51)
#define MXC_CSPICTRL_EN (1 << 0)
#define USBCTRL_OTGBASE_OFFSET 0x600
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
+#define MX25_USB_CTRL_HSTD_BIT (1<<5)
+#define MX25_USB_CTRL_USBTE_BIT (1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
+#endif
+
+#ifdef CONFIG_MX31
#define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT (1 << 24)
#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4)
+#endif
static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
+
+#ifdef CONFIG_MX25
+ v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
+ MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
+#endif
+
#ifdef CONFIG_MX31
- v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET);
+ v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
switch (port) {
case 0: /* OTG port */
default:
return -EINVAL;
}
-
- writel(v, MX31_OTG_BASE_ADDR +
- USBCTRL_OTGBASE_OFFSET);
#endif
- return 0;
+
+ writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+ return 0;
}
int ehci_hcd_init(void)
{
- u32 tmp;
struct usb_ehci *ehci;
+#ifdef CONFIG_MX31
+ u32 tmp;
struct clock_control_regs *sc_regs =
(struct clock_control_regs *)CCM_BASE;
tmp = __raw_readl(&sc_regs->ccmr);
__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
+#endif
udelay(80);
/* Take USB2 */
- ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR +
+ ehci = (struct usb_ehci *)(IMX_USB_BASE +
(0x200 * CONFIG_MXC_USB_PORT));
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
+#ifdef CONFIG_MX31
setbits_le32(&ehci->control, USB_EN);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
-
+#endif
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
udelay(10000);
* At the moment only the 8x16 font is tested and the font fore- and
* background color is limited to black/white/gray colors. The Linux
* logo can be placed in the upper left corner and additional board
- * information strings (that normaly goes to serial port) can be drawed.
+ * information strings (that normally goes to serial port) can be drawn.
*
* The console driver can use the standard PC keyboard interface (i8042)
* for character input. Character output goes to a memory mapped video
* framebuffer with little or big-endian organisation.
* With environment setting 'console=serial' the console i/o can be
* forced to serial port.
-
- The driver uses graphic specific defines/parameters/functions:
-
- (for SMI LynxE graphic chip)
-
- CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810
- VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian
- VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill
- VIDEO_HW_BITBLT - graphic driver supports hardware bit blt
-
- Console Parameters are set by graphic drivers global struct:
-
- VIDEO_VISIBLE_COLS - x resolution
- VIDEO_VISIBLE_ROWS - y resolution
- VIDEO_PIXEL_SIZE - storage size in byte per pixel
- VIDEO_DATA_FORMAT - graphical data format GDF
- VIDEO_FB_ADRS - start of video memory
-
- CONFIG_I8042_KBD - AT Keyboard driver for i8042
- VIDEO_KBD_INIT_FCT - init function for keyboard
- VIDEO_TSTC_FCT - keyboard_tstc function
- VIDEO_GETC_FCT - keyboard_getc function
-
- CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with delay
- loop in VIDEO_TSTC_FCT (i8042)
- CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate
- CONFIG_CONSOLE_TIME - display time/date in upper right corner,
- needs CONFIG_CMD_DATE and CONFIG_CONSOLE_CURSOR
- CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
- CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
- CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings
- that normaly goes to serial port. This define
- requires a board specific function:
- video_drawstring (VIDEO_INFO_X,
- VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT,
- info);
- that fills a info buffer at i=row.
- s.a: board/eltec/bab7xx.
-CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be initialised
- as an output only device. The Keyboard driver
- will not be set-up. This may be used, if you
- have none or more than one Keyboard devices
- (USB Keyboard, AT Keyboard).
-
-CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last character. No
- blinking is provided. Uses the macros CURSOR_SET
- and CURSOR_OFF.
-CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the
- graphic chip. Uses the macro CURSOR_SET.
- ATTENTION: If booting an OS, the display driver
- must disable the hardware register of the graphic
- chip. Otherwise a blinking field is displayed
-*/
+ *
+ * The driver uses graphic specific defines/parameters/functions:
+ *
+ * (for SMI LynxE graphic chip)
+ *
+ * CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810
+ * VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian
+ * VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill
+ * VIDEO_HW_BITBLT - graphic driver supports hardware bit blt
+ *
+ * Console Parameters are set by graphic drivers global struct:
+ *
+ * VIDEO_VISIBLE_COLS - x resolution
+ * VIDEO_VISIBLE_ROWS - y resolution
+ * VIDEO_PIXEL_SIZE - storage size in byte per pixel
+ * VIDEO_DATA_FORMAT - graphical data format GDF
+ * VIDEO_FB_ADRS - start of video memory
+ *
+ * CONFIG_I8042_KBD - AT Keyboard driver for i8042
+ * VIDEO_KBD_INIT_FCT - init function for keyboard
+ * VIDEO_TSTC_FCT - keyboard_tstc function
+ * VIDEO_GETC_FCT - keyboard_getc function
+ *
+ * CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with
+ * delay loop in VIDEO_TSTC_FCT (i8042)
+ *
+ * CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate
+ * CONFIG_CONSOLE_TIME - display time/date in upper right
+ * corner, needs CONFIG_CMD_DATE and
+ * CONFIG_CONSOLE_CURSOR
+ * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
+ * CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
+ * CONFIG_CONSOLE_EXTRA_INFO - display additional board information
+ * strings that normaly goes to serial
+ * port. This define requires a board
+ * specific function:
+ * video_drawstring (VIDEO_INFO_X,
+ * VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT,
+ * info);
+ * that fills a info buffer at i=row.
+ * s.a: board/eltec/bab7xx.
+ * CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be
+ * initialized as an output only device.
+ * The Keyboard driver will not be
+ * set-up. This may be used, if you have
+ * no or more than one Keyboard devices
+ * (USB Keyboard, AT Keyboard).
+ *
+ * CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last
+ * character. No blinking is provided.
+ * Uses the macros CURSOR_SET and
+ * CURSOR_OFF.
+ *
+ * CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability
+ * of the graphic chip. Uses the macro
+ * CURSOR_SET. ATTENTION: If booting an
+ * OS, the display driver must disable
+ * the hardware register of the graphic
+ * chip. Otherwise a blinking field is
+ * displayed.
+ */
#include <common.h>
-
+#include <version.h>
#include <malloc.h>
-/*****************************************************************************/
-/* Console device defines with SMI graphic */
-/* Any other graphic must change this section */
-/*****************************************************************************/
+/*
+ * Console device defines with SMI graphic
+ * Any other graphic must change this section
+ */
#ifdef CONFIG_VIDEO_SMI_LYNXEM
#define VIDEO_HW_BITBLT
#endif
-/*****************************************************************************/
-/* Defines for the CT69000 driver */
-/*****************************************************************************/
+/*
+ * Defines for the CT69000 driver
+ */
#ifdef CONFIG_VIDEO_CT69000
#define VIDEO_FB_LITTLE_ENDIAN
#define VIDEO_HW_BITBLT
#endif
-/*****************************************************************************/
-/* Defines for the SED13806 driver */
-/*****************************************************************************/
+/*
+ * Defines for the SED13806 driver
+ */
#ifdef CONFIG_VIDEO_SED13806
#ifndef CONFIG_TOTAL5200
#define VIDEO_HW_BITBLT
#endif
-/*****************************************************************************/
-/* Defines for the SED13806 driver */
-/*****************************************************************************/
+/*
+ * Defines for the SED13806 driver
+ */
#ifdef CONFIG_VIDEO_SM501
#ifdef CONFIG_HH405
#endif
#endif
-/*****************************************************************************/
-/* Defines for the MB862xx driver */
-/*****************************************************************************/
+/*
+ * Defines for the MB862xx driver
+ */
#ifdef CONFIG_VIDEO_MB862xx
#ifdef CONFIG_VIDEO_CORALP
#endif
#endif
-/*****************************************************************************/
-/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */
-/*****************************************************************************/
+/*
+ * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
+ */
#include <video_fb.h>
-/*****************************************************************************/
-/* some Macros */
-/*****************************************************************************/
+/*
+ * some Macros
+ */
#define VIDEO_VISIBLE_COLS (pGD->winSizeX)
#define VIDEO_VISIBLE_ROWS (pGD->winSizeY)
#define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP)
#define VIDEO_DATA_FORMAT (pGD->gdfIndex)
#define VIDEO_FB_ADRS (pGD->frameAdrs)
-/*****************************************************************************/
-/* Console device defines with i8042 keyboard controller */
-/* Any other keyboard controller must change this section */
-/*****************************************************************************/
+/*
+ * Console device defines with i8042 keyboard controller
+ * Any other keyboard controller must change this section
+ */
#ifdef CONFIG_I8042_KBD
#include <i8042.h>
#define VIDEO_GETC_FCT i8042_getc
#endif
-/*****************************************************************************/
-/* Console device */
-/*****************************************************************************/
+/*
+ * Console device
+ */
#include <version.h>
#include <linux/types.h>
#endif
-/*****************************************************************************/
-/* Cursor definition: */
-/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) */
-/* to let the cursor blink. Uses the macros */
-/* CURSOR_OFF and CURSOR_ON. */
-/* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */
-/* blinking is provided. Uses the macros CURSOR_SET */
-/* and CURSOR_OFF. */
-/* CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the */
-/* graphic chip. Uses the macro CURSOR_SET. */
-/* ATTENTION: If booting an OS, the display driver */
-/* must disable the hardware register of the graphic */
-/* chip. Otherwise a blinking field is displayed */
-/*****************************************************************************/
+/*
+ * Cursor definition:
+ * CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c)
+ * to let the cursor blink. Uses the macros
+ * CURSOR_OFF and CURSOR_ON.
+ * CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No
+ * blinking is provided. Uses the macros CURSOR_SET
+ * and CURSOR_OFF.
+ * CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the
+ * graphic chip. Uses the macro CURSOR_SET.
+ * ATTENTION: If booting an OS, the display driver
+ * must disable the hardware register of the graphic
+ * chip. Otherwise a blinking field is displayed
+ */
#if !defined(CONFIG_CONSOLE_CURSOR) && \
!defined(CONFIG_VIDEO_SW_CURSOR) && \
!defined(CONFIG_VIDEO_HW_CURSOR)
#ifdef CONFIG_CONSOLE_CURSOR
#ifdef CURSOR_ON
-#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined
+#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
+ or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
-void console_cursor (int state);
+void console_cursor(int state);
+
#define CURSOR_ON console_cursor(1)
#define CURSOR_OFF console_cursor(0)
#define CURSOR_SET
#ifdef CONFIG_VIDEO_SW_CURSOR
#ifdef CURSOR_ON
-#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined
+#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
+ or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
#define CURSOR_ON
#define CURSOR_OFF video_putchar(console_col * VIDEO_FONT_WIDTH,\
#ifdef CONFIG_VIDEO_HW_CURSOR
#ifdef CURSOR_ON
-#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined
+#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
+ or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
#define CURSOR_ON
#define CURSOR_OFF
#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \
(console_row * VIDEO_FONT_HEIGHT) + video_logo_height)
-#endif /* CONFIG_VIDEO_HW_CURSOR */
+#endif /* CONFIG_VIDEO_HW_CURSOR */
#ifdef CONFIG_VIDEO_LOGO
#ifdef CONFIG_VIDEO_BMP_LOGO
#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET
#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS
-#else /* CONFIG_VIDEO_BMP_LOGO */
+#else /* CONFIG_VIDEO_BMP_LOGO */
#define LINUX_LOGO_WIDTH 80
#define LINUX_LOGO_HEIGHT 80
#define LINUX_LOGO_COLORS 214
#define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT
#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET
#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS
-#endif /* CONFIG_VIDEO_BMP_LOGO */
+#endif /* CONFIG_VIDEO_BMP_LOGO */
#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH)
#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2)
-#else /* CONFIG_VIDEO_LOGO */
+#else /* CONFIG_VIDEO_LOGO */
#define VIDEO_LOGO_WIDTH 0
#define VIDEO_LOGO_HEIGHT 0
-#endif /* CONFIG_VIDEO_LOGO */
+#endif /* CONFIG_VIDEO_LOGO */
#define VIDEO_COLS VIDEO_VISIBLE_COLS
#define VIDEO_ROWS VIDEO_VISIBLE_ROWS
/* Macros */
#ifdef VIDEO_FB_LITTLE_ENDIAN
-#define SWAP16(x) ((((x) & 0x00ff) << 8) | ( (x) >> 8))
-#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
- (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
-#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | (((x) & 0x0000ff00) >> 8)|\
- (((x) & 0x00ff0000) << 8) | (((x) & 0xff000000) >> 8) )
+#define SWAP16(x) ((((x) & 0x00ff) << 8) | \
+ ((x) >> 8) \
+ )
+#define SWAP32(x) ((((x) & 0x000000ff) << 24) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x00ff0000) >> 8) | \
+ (((x) & 0xff000000) >> 24) \
+ )
+#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \
+ (((x) & 0x0000ff00) >> 8) | \
+ (((x) & 0x00ff0000) << 8) | \
+ (((x) & 0xff000000) >> 8) \
+ )
#else
-#define SWAP16(x) (x)
-#define SWAP32(x) (x)
+#define SWAP16(x) (x)
+#define SWAP32(x) (x)
#if defined(VIDEO_FB_16BPP_WORD_SWAP)
-#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) )
+#define SHORTSWAP32(x) (((x) >> 16) | ((x) << 16))
#else
-#define SHORTSWAP32(x) (x)
-#endif
+#define SHORTSWAP32(x) (x)
#endif
-
-#if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE)
-#define PRINTD(x) printf(x)
-#else
-#define PRINTD(x)
#endif
-
#ifdef CONFIG_CONSOLE_EXTRA_INFO
-extern void video_get_info_str ( /* setup a board string: type, speed, etc. */
- int line_number, /* location to place info string beside logo */
- char *info /* buffer for info string */
- );
-
+/*
+ * setup a board string: type, speed, etc.
+ *
+ * line_number: location to place info string beside logo
+ * info: buffer for info string
+ */
+extern void video_get_info_str(int line_number, char *info);
#endif
/* Locals */
static GraphicDevice *pGD; /* Pointer to Graphic array */
-static void *video_fb_address; /* frame buffer address */
+static void *video_fb_address; /* frame buffer address */
static void *video_console_address; /* console buffer start address */
static int video_logo_height = VIDEO_LOGO_HEIGHT;
-static int console_col = 0; /* cursor col */
-static int console_row = 0; /* cursor row */
+static int console_col; /* cursor col */
+static int console_row; /* cursor row */
-static u32 eorx, fgx, bgx; /* color pats */
+static u32 eorx, fgx, bgx; /* color pats */
static const int video_font_draw_table8[] = {
- 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
- 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
- 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
- 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff };
+ 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
+ 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
+ 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
+ 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
+};
static const int video_font_draw_table15[] = {
- 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff };
+ 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff
+};
static const int video_font_draw_table16[] = {
- 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff };
+ 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff
+};
static const int video_font_draw_table24[16][3] = {
- { 0x00000000, 0x00000000, 0x00000000 },
- { 0x00000000, 0x00000000, 0x00ffffff },
- { 0x00000000, 0x0000ffff, 0xff000000 },
- { 0x00000000, 0x0000ffff, 0xffffffff },
- { 0x000000ff, 0xffff0000, 0x00000000 },
- { 0x000000ff, 0xffff0000, 0x00ffffff },
- { 0x000000ff, 0xffffffff, 0xff000000 },
- { 0x000000ff, 0xffffffff, 0xffffffff },
- { 0xffffff00, 0x00000000, 0x00000000 },
- { 0xffffff00, 0x00000000, 0x00ffffff },
- { 0xffffff00, 0x0000ffff, 0xff000000 },
- { 0xffffff00, 0x0000ffff, 0xffffffff },
- { 0xffffffff, 0xffff0000, 0x00000000 },
- { 0xffffffff, 0xffff0000, 0x00ffffff },
- { 0xffffffff, 0xffffffff, 0xff000000 },
- { 0xffffffff, 0xffffffff, 0xffffffff } };
+ {0x00000000, 0x00000000, 0x00000000},
+ {0x00000000, 0x00000000, 0x00ffffff},
+ {0x00000000, 0x0000ffff, 0xff000000},
+ {0x00000000, 0x0000ffff, 0xffffffff},
+ {0x000000ff, 0xffff0000, 0x00000000},
+ {0x000000ff, 0xffff0000, 0x00ffffff},
+ {0x000000ff, 0xffffffff, 0xff000000},
+ {0x000000ff, 0xffffffff, 0xffffffff},
+ {0xffffff00, 0x00000000, 0x00000000},
+ {0xffffff00, 0x00000000, 0x00ffffff},
+ {0xffffff00, 0x0000ffff, 0xff000000},
+ {0xffffff00, 0x0000ffff, 0xffffffff},
+ {0xffffffff, 0xffff0000, 0x00000000},
+ {0xffffffff, 0xffff0000, 0x00ffffff},
+ {0xffffffff, 0xffffffff, 0xff000000},
+ {0xffffffff, 0xffffffff, 0xffffffff}
+};
static const int video_font_draw_table32[16][4] = {
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
- { 0x00000000, 0x00000000, 0x00000000, 0x00ffffff },
- { 0x00000000, 0x00000000, 0x00ffffff, 0x00000000 },
- { 0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff },
- { 0x00000000, 0x00ffffff, 0x00000000, 0x00000000 },
- { 0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff },
- { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000 },
- { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff },
- { 0x00ffffff, 0x00000000, 0x00000000, 0x00000000 },
- { 0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff },
- { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000 },
- { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff },
- { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000 },
- { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff },
- { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000 },
- { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } };
-
-
-/******************************************************************************/
-
-static void video_drawchars (int xx, int yy, unsigned char *s, int count)
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x00000000, 0x00000000, 0x00000000, 0x00ffffff},
+ {0x00000000, 0x00000000, 0x00ffffff, 0x00000000},
+ {0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff},
+ {0x00000000, 0x00ffffff, 0x00000000, 0x00000000},
+ {0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff},
+ {0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000},
+ {0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff},
+ {0x00ffffff, 0x00000000, 0x00000000, 0x00000000},
+ {0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff},
+ {0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000},
+ {0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff},
+ {0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000},
+ {0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff},
+ {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000},
+ {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff}
+};
+
+
+static void video_drawchars(int xx, int yy, unsigned char *s, int count)
{
u8 *cdat, *dest, *dest0;
int rows, offset, c;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx;
- ((u32 *) dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx;
+ ((u32 *) dest)[0] =
+ (video_font_draw_table8[bits >> 4] &
+ eorx) ^ bgx;
+ ((u32 *) dest)[1] =
+ (video_font_draw_table8[bits & 15] &
+ eorx) ^ bgx;
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 6] & eorx) ^ bgx);
- ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 4 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 2 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table15 [bits & 3] & eorx) ^ bgx);
+ ((u32 *) dest)[0] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits >> 6] & eorx) ^
+ bgx);
+ ((u32 *) dest)[1] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits >> 4 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[2] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits >> 2 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[3] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits & 3] & eorx) ^
+ bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 6] & eorx) ^ bgx);
- ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 4 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 2 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table16 [bits & 3] & eorx) ^ bgx);
+ ((u32 *) dest)[0] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits >> 6] & eorx) ^
+ bgx);
+ ((u32 *) dest)[1] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits >> 4 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[2] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits >> 2 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[3] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits & 3] & eorx) ^
+ bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = SWAP32 ((video_font_draw_table32 [bits >> 4][0] & eorx) ^ bgx);
- ((u32 *) dest)[1] = SWAP32 ((video_font_draw_table32 [bits >> 4][1] & eorx) ^ bgx);
- ((u32 *) dest)[2] = SWAP32 ((video_font_draw_table32 [bits >> 4][2] & eorx) ^ bgx);
- ((u32 *) dest)[3] = SWAP32 ((video_font_draw_table32 [bits >> 4][3] & eorx) ^ bgx);
- ((u32 *) dest)[4] = SWAP32 ((video_font_draw_table32 [bits & 15][0] & eorx) ^ bgx);
- ((u32 *) dest)[5] = SWAP32 ((video_font_draw_table32 [bits & 15][1] & eorx) ^ bgx);
- ((u32 *) dest)[6] = SWAP32 ((video_font_draw_table32 [bits & 15][2] & eorx) ^ bgx);
- ((u32 *) dest)[7] = SWAP32 ((video_font_draw_table32 [bits & 15][3] & eorx) ^ bgx);
+ ((u32 *) dest)[0] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][0] & eorx) ^ bgx);
+ ((u32 *) dest)[1] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][1] & eorx) ^ bgx);
+ ((u32 *) dest)[2] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][2] & eorx) ^ bgx);
+ ((u32 *) dest)[3] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][3] & eorx) ^ bgx);
+ ((u32 *) dest)[4] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][0] & eorx) ^ bgx);
+ ((u32 *) dest)[5] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][1] & eorx) ^ bgx);
+ ((u32 *) dest)[6] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][2] & eorx) ^ bgx);
+ ((u32 *) dest)[7] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][3] & eorx) ^ bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = (video_font_draw_table24[bits >> 4][0] & eorx) ^ bgx;
- ((u32 *) dest)[1] = (video_font_draw_table24[bits >> 4][1] & eorx) ^ bgx;
- ((u32 *) dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx;
- ((u32 *) dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx;
- ((u32 *) dest)[4] = (video_font_draw_table24[bits & 15][1] & eorx) ^ bgx;
- ((u32 *) dest)[5] = (video_font_draw_table24[bits & 15][2] & eorx) ^ bgx;
+ ((u32 *) dest)[0] =
+ (video_font_draw_table24[bits >> 4][0]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[1] =
+ (video_font_draw_table24[bits >> 4][1]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[2] =
+ (video_font_draw_table24[bits >> 4][2]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[3] =
+ (video_font_draw_table24[bits & 15][0]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[4] =
+ (video_font_draw_table24[bits & 15][1]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[5] =
+ (video_font_draw_table24[bits & 15][2]
+ & eorx) ^ bgx;
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
}
-/*****************************************************************************/
-
-static inline void video_drawstring (int xx, int yy, unsigned char *s)
+static inline void video_drawstring(int xx, int yy, unsigned char *s)
{
- video_drawchars (xx, yy, s, strlen ((char *)s));
+ video_drawchars(xx, yy, s, strlen((char *) s));
}
-/*****************************************************************************/
-
-static void video_putchar (int xx, int yy, unsigned char c)
+static void video_putchar(int xx, int yy, unsigned char c)
{
- video_drawchars (xx, yy + video_logo_height, &c, 1);
+ video_drawchars(xx, yy + video_logo_height, &c, 1);
}
-/*****************************************************************************/
#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR)
-static void video_set_cursor (void)
+static void video_set_cursor(void)
{
/* swap drawing colors */
eorx = fgx;
bgx = eorx;
eorx = fgx ^ bgx;
/* draw cursor */
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- ' ');
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, ' ');
/* restore drawing colors */
eorx = fgx;
fgx = bgx;
eorx = fgx ^ bgx;
}
#endif
-/*****************************************************************************/
+
#ifdef CONFIG_CONSOLE_CURSOR
-void console_cursor (int state)
+void console_cursor(int state)
{
static int last_state = 0;
/* time update only if cursor is on (faster scroll) */
if (state) {
- rtc_get (&tm);
-
- sprintf (info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
- tm.tm_sec);
- video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y, (uchar *)info);
-
- sprintf (info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
- tm.tm_year);
- video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, (uchar *)info);
+ rtc_get(&tm);
+
+ sprintf(info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
+ tm.tm_sec);
+ video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y, (uchar *) info);
+
+ sprintf(info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
+ tm.tm_year);
+ video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT,
+ (uchar *) info);
}
#endif
if (state && (last_state != state)) {
- video_set_cursor ();
+ video_set_cursor();
}
if (!state && (last_state != state)) {
/* clear cursor */
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- ' ');
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, ' ');
}
last_state = state;
}
#endif
-/*****************************************************************************/
-
#ifndef VIDEO_HW_RECTFILL
-static void memsetl (int *p, int c, int v)
+static void memsetl(int *p, int c, int v)
{
while (c--)
*(p++) = v;
}
#endif
-/*****************************************************************************/
-
#ifndef VIDEO_HW_BITBLT
-static void memcpyl (int *d, int *s, int c)
+static void memcpyl(int *d, int *s, int c)
{
while (c--)
*(d++) = *(s++);
}
#endif
-/*****************************************************************************/
-
-static void console_scrollup (void)
+static void console_scrollup(void)
{
/* copy up rows ignoring the first one */
#ifdef VIDEO_HW_BITBLT
- video_hw_bitblt (VIDEO_PIXEL_SIZE, /* bytes per pixel */
- 0, /* source pos x */
- video_logo_height + VIDEO_FONT_HEIGHT, /* source pos y */
- 0, /* dest pos x */
- video_logo_height, /* dest pos y */
- VIDEO_VISIBLE_COLS, /* frame width */
- VIDEO_VISIBLE_ROWS - video_logo_height - VIDEO_FONT_HEIGHT /* frame height */
+ video_hw_bitblt(VIDEO_PIXEL_SIZE, /* bytes per pixel */
+ 0, /* source pos x */
+ video_logo_height +
+ VIDEO_FONT_HEIGHT, /* source pos y */
+ 0, /* dest pos x */
+ video_logo_height, /* dest pos y */
+ VIDEO_VISIBLE_COLS, /* frame width */
+ VIDEO_VISIBLE_ROWS
+ - video_logo_height
+ - VIDEO_FONT_HEIGHT /* frame height */
);
#else
- memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
- CONSOLE_SCROLL_SIZE >> 2);
+ memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
+ CONSOLE_SCROLL_SIZE >> 2);
#endif
/* clear the last one */
#ifdef VIDEO_HW_RECTFILL
- video_hw_rectfill (VIDEO_PIXEL_SIZE, /* bytes per pixel */
- 0, /* dest pos x */
- VIDEO_VISIBLE_ROWS - VIDEO_FONT_HEIGHT, /* dest pos y */
- VIDEO_VISIBLE_COLS, /* frame width */
- VIDEO_FONT_HEIGHT, /* frame height */
- CONSOLE_BG_COL /* fill color */
+ video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */
+ 0, /* dest pos x */
+ VIDEO_VISIBLE_ROWS
+ - VIDEO_FONT_HEIGHT, /* dest pos y */
+ VIDEO_VISIBLE_COLS, /* frame width */
+ VIDEO_FONT_HEIGHT, /* frame height */
+ CONSOLE_BG_COL /* fill color */
);
#else
- memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL);
+ memsetl(CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL);
#endif
}
-/*****************************************************************************/
-
-static void console_back (void)
+static void console_back(void)
{
CURSOR_OFF;
console_col--;
if (console_row < 0)
console_row = 0;
}
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- ' ');
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, ' ');
}
-/*****************************************************************************/
-
-static void console_newline (void)
+static void console_newline(void)
{
/* Check if last character in the line was just drawn. If so, cursor was
overwriten and need not to be cleared. Cursor clearing without this
/* Check if we need to scroll the terminal */
if (console_row >= CONSOLE_ROWS) {
/* Scroll everything up */
- console_scrollup ();
+ console_scrollup();
/* Decrement row number */
console_row--;
}
}
-static void console_cr (void)
+static void console_cr(void)
{
CURSOR_OFF;
console_col = 0;
}
-/*****************************************************************************/
-
-void video_putc (const char c)
+void video_putc(const char c)
{
static int nl = 1;
switch (c) {
case 13: /* back to first column */
- console_cr ();
+ console_cr();
break;
case '\n': /* next line */
if (console_col || (!console_col && nl))
- console_newline ();
+ console_newline();
nl = 1;
break;
console_col &= ~0x0007;
if (console_col >= CONSOLE_COLS)
- console_newline ();
+ console_newline();
break;
case 8: /* backspace */
- console_back ();
+ console_back();
break;
default: /* draw the char */
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- c);
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, c);
console_col++;
/* check for newline */
if (console_col >= CONSOLE_COLS) {
- console_newline ();
+ console_newline();
nl = 0;
}
}
CURSOR_SET;
}
-
-/*****************************************************************************/
-
-void video_puts (const char *s)
+void video_puts(const char *s)
{
- int count = strlen (s);
+ int count = strlen(s);
while (count--)
- video_putc (*s++);
+ video_putc(*s++);
}
-/*****************************************************************************/
-
/*
* Do not enforce drivers (or board code) to provide empty
* video_set_lut() if they do not support 8 bpp format.
* Implement weak default function instead.
*/
-void __video_set_lut (unsigned int index, unsigned char r,
- unsigned char g, unsigned char b)
+void __video_set_lut(unsigned int index, unsigned char r,
+ unsigned char g, unsigned char b)
{
}
-void video_set_lut (unsigned int, unsigned char, unsigned char, unsigned char)
- __attribute__((weak, alias("__video_set_lut")));
+
+void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char)
+ __attribute__ ((weak, alias("__video_set_lut")));
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
}
#define FILL_15BIT_555RGB(r,g,b) { \
- *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \
+ *(unsigned short *)fb = \
+ SWAP16((unsigned short)(((r>>3)<<10) | \
+ ((g>>3)<<5) | \
+ (b>>3))); \
fb += 2; \
}
#define FILL_16BIT_565RGB(r,g,b) { \
- *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \
+ *(unsigned short *)fb = \
+ SWAP16((unsigned short)((((r)>>3)<<11)| \
+ (((g)>>2)<<5) | \
+ ((b)>>3))); \
fb += 2; \
}
#define FILL_32BIT_X888RGB(r,g,b) { \
- *(unsigned long *)fb = SWAP32((unsigned long)(((r<<16) | (g<<8) | b))); \
+ *(unsigned long *)fb = \
+ SWAP32((unsigned long)(((r<<16) | \
+ (g<<8) | \
+ b))); \
fb += 4; \
}
#endif
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
-static void inline fill_555rgb_pswap(uchar *fb, int x,
- u8 r, u8 g, u8 b)
+static inline void fill_555rgb_pswap(uchar *fb, int x, u8 r, u8 g, u8 b)
{
- ushort *dst = (ushort *)fb;
- ushort color = (ushort)(((r >> 3) << 10) |
- ((g >> 3) << 5) |
- (b >> 3));
+ ushort *dst = (ushort *) fb;
+ ushort color = (ushort) (((r >> 3) << 10) |
+ ((g >> 3) << 5) |
+ (b >> 3));
if (x & 1)
*(--dst) = color;
else
/* Pre-calculated color table entry */
struct palette {
union {
- unsigned short w; /* word */
- unsigned int dw; /* double word */
- } ce; /* color entry */
+ unsigned short w; /* word */
+ unsigned int dw; /* double word */
+ } ce; /* color entry */
};
/*
* Helper to draw encoded/unencoded run.
*/
-static void draw_bitmap (uchar **fb, uchar *bm, struct palette *p,
- int cnt, int enc)
+static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p,
+ int cnt, int enc)
{
- ulong addr = (ulong)*fb;
+ ulong addr = (ulong) *fb;
int *off;
int enc_off = 1;
int i;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
for (i = 0; i < cnt; i++)
- *(unsigned char *)addr++ = bm[*off];
+ *(unsigned char *) addr++ = bm[*off];
break;
case GDF_15BIT_555RGB:
case GDF_16BIT_565RGB:
/* differences handled while pre-calculating palette */
for (i = 0; i < cnt; i++) {
- *(unsigned short *)addr = p[bm[*off]].ce.w;
+ *(unsigned short *) addr = p[bm[*off]].ce.w;
addr += 2;
}
break;
case GDF_32BIT_X888RGB:
for (i = 0; i < cnt; i++) {
- *(unsigned long *)addr = p[bm[*off]].ce.dw;
+ *(unsigned long *) addr = p[bm[*off]].ce.dw;
addr += 4;
}
break;
}
- *fb = (uchar *)addr; /* return modified address */
+ *fb = (uchar *) addr; /* return modified address */
}
-static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff,
- int width, int height)
+static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff,
+ int width, int height)
{
unsigned char *bm;
unsigned char *fbp;
y = __le32_to_cpu(img->header.height) - 1;
ncolors = __le32_to_cpu(img->header.colors_used);
bpp = VIDEO_PIXEL_SIZE;
- fbp = (unsigned char *)((unsigned int)video_fb_address +
- (((y + yoff) * VIDEO_COLS) + xoff) * bpp);
+ fbp = (unsigned char *) ((unsigned int) video_fb_address +
+ (((y + yoff) * VIDEO_COLS) + xoff) * bpp);
- bm = (uchar *)img + __le32_to_cpu(img->header.data_offset);
+ bm = (uchar *) img + __le32_to_cpu(img->header.data_offset);
/* pre-calculate and setup palette */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
for (i = 0; i < ncolors; i++) {
cte = img->color_table[i];
- video_set_lut (i, cte.red, cte.green, cte.blue);
+ video_set_lut(i, cte.red, cte.green, cte.blue);
}
break;
case GDF_15BIT_555RGB:
case GDF_32BIT_X888RGB:
for (i = 0; i < ncolors; i++) {
cte = img->color_table[i];
- p[i].ce.dw = SWAP32((cte.red << 16) | (cte.green << 8) |
+ p[i].ce.dw = SWAP32((cte.red << 16) |
+ (cte.green << 8) |
cte.blue);
}
break;
default:
printf("RLE Bitmap unsupported in video mode 0x%x\n",
- VIDEO_DATA_FORMAT);
+ VIDEO_DATA_FORMAT);
return -1;
}
x = 0;
y--;
fbp = (unsigned char *)
- ((unsigned int)video_fb_address +
+ ((unsigned int) video_fb_address +
(((y + yoff) * VIDEO_COLS) +
xoff) * bpp);
continue;
x += bm[2];
y -= bm[3];
fbp = (unsigned char *)
- ((unsigned int)video_fb_address +
+ ((unsigned int) video_fb_address +
(((y + yoff) * VIDEO_COLS) +
x + xoff) * bpp);
bm += 4;
}
if (x + runlen > width)
cnt = width - x;
- draw_bitmap (&fbp, bm, p, cnt, 0);
+ draw_bitmap(&fbp, bm, p, cnt, 0);
x += runlen;
}
next_run:
bm += runlen;
if (runlen & 1)
- bm++; /* 0 padding if length is odd */
+ bm++; /* 0 padding if length is odd */
}
break;
default:
if (pixels > limit)
goto error;
- if (y < height) { /* only draw into visible area */
+ if (y < height) { /* only draw into visible area */
if (x >= width) {
x += runlen;
bm += 2;
}
if (x + runlen > width)
cnt = width - x;
- draw_bitmap (&fbp, bm, p, cnt, 1);
+ draw_bitmap(&fbp, bm, p, cnt, 1);
x += runlen;
}
bm += 2;
/*
* Display the BMP file located at address bmp_image.
*/
-int video_display_bitmap (ulong bmp_image, int x, int y)
+int video_display_bitmap(ulong bmp_image, int x, int y)
{
ushort xcount, ycount;
uchar *fb;
unsigned colors;
unsigned long compression;
bmp_color_table_entry_t cte;
+
#ifdef CONFIG_VIDEO_BMP_GZIP
unsigned char *dst = NULL;
ulong len;
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
if (dst == NULL) {
printf("Error: malloc in gunzip failed!\n");
- return(1);
+ return 1;
}
- if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) {
- printf ("Error: no valid bmp or bmp.gz image at %lx\n", bmp_image);
+ if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
+ (uchar *) bmp_image,
+ &len) != 0) {
+ printf("Error: no valid bmp or bmp.gz image at %lx\n",
+ bmp_image);
free(dst);
return 1;
}
if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
- printf("Image could be truncated (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
+ printf("Image could be truncated "
+ "(increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
}
/*
* Set addr to decompressed image
*/
- bmp = (bmp_image_t *)dst;
+ bmp = (bmp_image_t *) dst;
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
- printf ("Error: no valid bmp.gz image at %lx\n", bmp_image);
+ printf("Error: no valid bmp.gz image at %lx\n",
+ bmp_image);
free(dst);
return 1;
}
#else
- printf ("Error: no valid bmp image at %lx\n", bmp_image);
+ printf("Error: no valid bmp image at %lx\n", bmp_image);
return 1;
#endif /* CONFIG_VIDEO_BMP_GZIP */
}
- width = le32_to_cpu (bmp->header.width);
- height = le32_to_cpu (bmp->header.height);
- bpp = le16_to_cpu (bmp->header.bit_count);
- colors = le32_to_cpu (bmp->header.colors_used);
- compression = le32_to_cpu (bmp->header.compression);
+ width = le32_to_cpu(bmp->header.width);
+ height = le32_to_cpu(bmp->header.height);
+ bpp = le16_to_cpu(bmp->header.bit_count);
+ colors = le32_to_cpu(bmp->header.colors_used);
+ compression = le32_to_cpu(bmp->header.compression);
- debug ("Display-bmp: %d x %d with %d colors\n",
- width, height, colors);
+ debug("Display-bmp: %d x %d with %d colors\n",
+ width, height, colors);
if (compression != BMP_BI_RGB
#ifdef CONFIG_VIDEO_BMP_RLE8
&& compression != BMP_BI_RLE8
#endif
- ) {
- printf ("Error: compression type %ld not supported\n",
- compression);
+ ) {
+ printf("Error: compression type %ld not supported\n",
+ compression);
#ifdef CONFIG_VIDEO_BMP_GZIP
if (dst)
free(dst);
if ((y + height) > VIDEO_VISIBLE_ROWS)
height = VIDEO_VISIBLE_ROWS - y;
- bmap = (uchar *) bmp + le32_to_cpu (bmp->header.data_offset);
+ bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset);
fb = (uchar *) (video_fb_address +
((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) +
x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_RLE8
if (compression == BMP_BI_RLE8) {
- return display_rle8_bitmap(bmp,
- x, y, width, height);
+ return display_rle8_bitmap(bmp, x, y, width, height);
}
#endif
/* We handle only 4, 8, or 24 bpp bitmaps */
- switch (le16_to_cpu (bmp->header.bit_count)) {
+ switch (le16_to_cpu(bmp->header.bit_count)) {
case 4:
padded_line -= width / 2;
ycount = height;
switch (VIDEO_DATA_FORMAT) {
case GDF_32BIT_X888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/*
* Don't assume that 'width' is an
* even number
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ VIDEO_PIXEL_SIZE;
}
break;
default:
/* Copy colormap */
for (xcount = 0; xcount < colors; ++xcount) {
cte = bmp->color_table[xcount];
- video_set_lut (xcount, cte.red, cte.green, cte.blue);
+ video_set_lut(xcount, cte.red, cte.green,
+ cte.blue);
}
}
ycount = height;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
*fb++ = *bmap++;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF__8BIT_332RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_8BIT_332RGB (cte.red, cte.green, cte.blue);
+ FILL_8BIT_332RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
- fill_555rgb_pswap (fb, xpos++, cte.red,
- cte.green, cte.blue);
+ fill_555rgb_pswap(fb, xpos++, cte.red,
+ cte.green,
+ cte.blue);
fb += 2;
#else
- FILL_15BIT_555RGB (cte.red, cte.green, cte.blue);
+ FILL_15BIT_555RGB(cte.red, cte.green,
+ cte.blue);
#endif
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_16BIT_565RGB (cte.red, cte.green, cte.blue);
+ FILL_16BIT_565RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_32BIT_X888RGB (cte.red, cte.green, cte.blue);
+ FILL_32BIT_X888RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_24BIT_888RGB (cte.red, cte.green, cte.blue);
+ FILL_24BIT_888RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
}
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_332RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_8BIT_332RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_8BIT_332RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
- fill_555rgb_pswap (fb, xpos++, bmap[2],
- bmap[1], bmap[0]);
+ fill_555rgb_pswap(fb, xpos++, bmap[2],
+ bmap[1], bmap[0]);
fb += 2;
#else
- FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_15BIT_555RGB(bmap[2], bmap[1],
+ bmap[0]);
#endif
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_16BIT_565RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_16BIT_565RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_32BIT_X888RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_32BIT_X888RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_24BIT_888RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_24BIT_888RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
default:
- printf ("Error: 24 bits/pixel bitmap incompatible with current video mode\n");
+ printf("Error: 24 bits/pixel bitmap incompatible "
+ "with current video mode\n");
break;
}
break;
default:
- printf ("Error: %d bit/pixel bitmaps not supported by U-Boot\n",
- le16_to_cpu (bmp->header.bit_count));
+ printf("Error: %d bit/pixel bitmaps not supported by U-Boot\n",
+ le16_to_cpu(bmp->header.bit_count));
break;
}
}
#endif
-/*****************************************************************************/
#ifdef CONFIG_VIDEO_LOGO
-void logo_plot (void *screen, int width, int x, int y)
+void logo_plot(void *screen, int width, int x, int y)
{
int xcount, i;
- int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE;
+ int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE;
int ycount = video_logo_height;
unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
unsigned char *source;
- unsigned char *dest = (unsigned char *)screen +
- ((y * width * VIDEO_PIXEL_SIZE) +
- x * VIDEO_PIXEL_SIZE);
+ unsigned char *dest = (unsigned char *) screen +
+ ((y * width * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_LOGO
source = bmp_logo_bitmap;
/* Allocate temporary space for computing colormap */
- logo_red = malloc (BMP_LOGO_COLORS);
- logo_green = malloc (BMP_LOGO_COLORS);
- logo_blue = malloc (BMP_LOGO_COLORS);
+ logo_red = malloc(BMP_LOGO_COLORS);
+ logo_green = malloc(BMP_LOGO_COLORS);
+ logo_blue = malloc(BMP_LOGO_COLORS);
/* Compute color map */
for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4;
if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) {
for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
- video_set_lut (i + VIDEO_LOGO_LUT_OFFSET,
- logo_red[i], logo_green[i], logo_blue[i]);
+ video_set_lut(i + VIDEO_LOGO_LUT_OFFSET,
+ logo_red[i], logo_green[i],
+ logo_blue[i]);
}
}
*dest = *source;
break;
case GDF__8BIT_332RGB:
- *dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
+ *dest = ((r >> 5) << 5) |
+ ((g >> 5) << 2) |
+ (b >> 6);
break;
case GDF_15BIT_555RGB:
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
- fill_555rgb_pswap (dest, xpos++, r, g, b);
+ fill_555rgb_pswap(dest, xpos++, r, g, b);
#else
*(unsigned short *) dest =
- SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)));
+ SWAP16((unsigned short) (
+ ((r >> 3) << 10) |
+ ((g >> 3) << 5) |
+ (b >> 3)));
#endif
break;
case GDF_16BIT_565RGB:
*(unsigned short *) dest =
- SWAP16 ((unsigned short) (((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3)));
+ SWAP16((unsigned short) (
+ ((r >> 3) << 11) |
+ ((g >> 2) << 5) |
+ (b >> 3)));
break;
case GDF_32BIT_X888RGB:
*(unsigned long *) dest =
- SWAP32 ((unsigned long) ((r << 16) | (g << 8) | b));
+ SWAP32((unsigned long) (
+ (r << 16) |
+ (g << 8) |
+ b));
break;
case GDF_24BIT_888RGB:
#ifdef VIDEO_FB_LITTLE_ENDIAN
dest += skip;
}
#ifdef CONFIG_VIDEO_BMP_LOGO
- free (logo_red);
- free (logo_green);
- free (logo_blue);
+ free(logo_red);
+ free(logo_green);
+ free(logo_blue);
#endif
}
-/*****************************************************************************/
-
-static void *video_logo (void)
+static void *video_logo(void)
{
char info[128];
- extern char version_string;
int space, len, y_off = 0;
#ifdef CONFIG_SPLASH_SCREEN
char *s;
ulong addr;
- if ((s = getenv ("splashimage")) != NULL) {
+ s = getenv("splashimage");
+ if (s != NULL) {
int x = 0, y = 0;
- addr = simple_strtoul (s, NULL, 16);
+ addr = simple_strtoul(s, NULL, 16);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
- if ((s = getenv ("splashpos")) != NULL) {
+ s = getenv("splashpos");
+ if (s != NULL) {
if (s[0] == 'm')
x = BMP_ALIGN_CENTER;
else
- x = simple_strtol (s, NULL, 0);
+ x = simple_strtol(s, NULL, 0);
- if ((s = strchr (s + 1, ',')) != NULL) {
+ s = strchr(s + 1, ',');
+ if (s != NULL) {
if (s[1] == 'm')
y = BMP_ALIGN_CENTER;
else
- y = simple_strtol (s + 1, NULL, 0);
+ y = simple_strtol(s + 1, NULL, 0);
}
}
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
- if (video_display_bitmap (addr, x, y) == 0) {
+ if (video_display_bitmap(addr, x, y) == 0) {
video_logo_height = 0;
return ((void *) (video_fb_address));
}
}
#endif /* CONFIG_SPLASH_SCREEN */
- logo_plot (video_fb_address, VIDEO_COLS, 0, 0);
+ logo_plot(video_fb_address, VIDEO_COLS, 0, 0);
- sprintf (info, " %s", &version_string);
+ sprintf(info, " %s", version_string);
space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH;
len = strlen(info);
if (len > space) {
- video_drawchars (VIDEO_INFO_X, VIDEO_INFO_Y,
- (uchar *)info, space);
- video_drawchars (VIDEO_INFO_X + VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
- (uchar *)info + space, len - space);
+ video_drawchars(VIDEO_INFO_X, VIDEO_INFO_Y,
+ (uchar *) info, space);
+ video_drawchars(VIDEO_INFO_X + VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
+ (uchar *) info + space, len - space);
y_off = 1;
} else
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *)info);
+ video_drawstring(VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *) info);
#ifdef CONFIG_CONSOLE_EXTRA_INFO
{
- int i, n = ((video_logo_height - VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT);
+ int i, n =
+ ((video_logo_height -
+ VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT);
for (i = 1; i < n; i++) {
- video_get_info_str (i, info);
+ video_get_info_str(i, info);
if (!*info)
continue;
len = strlen(info);
if (len > space) {
- video_drawchars (VIDEO_INFO_X,
- VIDEO_INFO_Y +
- (i + y_off) * VIDEO_FONT_HEIGHT,
- (uchar *)info, space);
+ video_drawchars(VIDEO_INFO_X,
+ VIDEO_INFO_Y +
+ (i + y_off) *
+ VIDEO_FONT_HEIGHT,
+ (uchar *) info, space);
y_off++;
- video_drawchars (VIDEO_INFO_X + VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y +
- (i + y_off) * VIDEO_FONT_HEIGHT,
- (uchar *)info + space,
- len - space);
+ video_drawchars(VIDEO_INFO_X +
+ VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y +
+ (i + y_off) *
+ VIDEO_FONT_HEIGHT,
+ (uchar *) info + space,
+ len - space);
} else {
- video_drawstring (VIDEO_INFO_X,
- VIDEO_INFO_Y +
- (i + y_off) * VIDEO_FONT_HEIGHT,
- (uchar *)info);
+ video_drawstring(VIDEO_INFO_X,
+ VIDEO_INFO_Y +
+ (i + y_off) *
+ VIDEO_FONT_HEIGHT,
+ (uchar *) info);
}
}
}
}
#endif
-
-/*****************************************************************************/
-
-static int video_init (void)
+static int video_init(void)
{
unsigned char color8;
- if ((pGD = video_hw_init ()) == NULL)
+ pGD = video_hw_init();
+ if (pGD == NULL)
return -1;
video_fb_address = (void *) VIDEO_FB_ADRS;
#ifdef CONFIG_VIDEO_HW_CURSOR
- video_init_hw_cursor (VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT);
+ video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT);
#endif
/* Init drawing pats */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
- video_set_lut (0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
- video_set_lut (0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, CONSOLE_BG_COL);
+ video_set_lut(0x01, CONSOLE_FG_COL, CONSOLE_FG_COL,
+ CONSOLE_FG_COL);
+ video_set_lut(0x00, CONSOLE_BG_COL, CONSOLE_BG_COL,
+ CONSOLE_BG_COL);
fgx = 0x01010101;
bgx = 0x00000000;
break;
case GDF__8BIT_332RGB:
color8 = ((CONSOLE_FG_COL & 0xe0) |
- ((CONSOLE_FG_COL >> 3) & 0x1c) | CONSOLE_FG_COL >> 6);
- fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8;
+ ((CONSOLE_FG_COL >> 3) & 0x1c) |
+ CONSOLE_FG_COL >> 6);
+ fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
+ color8;
color8 = ((CONSOLE_BG_COL & 0xe0) |
- ((CONSOLE_BG_COL >> 3) & 0x1c) | CONSOLE_BG_COL >> 6);
- bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8;
+ ((CONSOLE_BG_COL >> 3) & 0x1c) |
+ CONSOLE_BG_COL >> 6);
+ bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
+ color8;
break;
case GDF_15BIT_555RGB:
fgx = (((CONSOLE_FG_COL >> 3) << 26) |
- ((CONSOLE_FG_COL >> 3) << 21) | ((CONSOLE_FG_COL >> 3) << 16) |
- ((CONSOLE_FG_COL >> 3) << 10) | ((CONSOLE_FG_COL >> 3) << 5) |
- (CONSOLE_FG_COL >> 3));
+ ((CONSOLE_FG_COL >> 3) << 21) |
+ ((CONSOLE_FG_COL >> 3) << 16) |
+ ((CONSOLE_FG_COL >> 3) << 10) |
+ ((CONSOLE_FG_COL >> 3) << 5) |
+ (CONSOLE_FG_COL >> 3));
bgx = (((CONSOLE_BG_COL >> 3) << 26) |
- ((CONSOLE_BG_COL >> 3) << 21) | ((CONSOLE_BG_COL >> 3) << 16) |
- ((CONSOLE_BG_COL >> 3) << 10) | ((CONSOLE_BG_COL >> 3) << 5) |
- (CONSOLE_BG_COL >> 3));
+ ((CONSOLE_BG_COL >> 3) << 21) |
+ ((CONSOLE_BG_COL >> 3) << 16) |
+ ((CONSOLE_BG_COL >> 3) << 10) |
+ ((CONSOLE_BG_COL >> 3) << 5) |
+ (CONSOLE_BG_COL >> 3));
break;
case GDF_16BIT_565RGB:
fgx = (((CONSOLE_FG_COL >> 3) << 27) |
- ((CONSOLE_FG_COL >> 2) << 21) | ((CONSOLE_FG_COL >> 3) << 16) |
- ((CONSOLE_FG_COL >> 3) << 11) | ((CONSOLE_FG_COL >> 2) << 5) |
- (CONSOLE_FG_COL >> 3));
+ ((CONSOLE_FG_COL >> 2) << 21) |
+ ((CONSOLE_FG_COL >> 3) << 16) |
+ ((CONSOLE_FG_COL >> 3) << 11) |
+ ((CONSOLE_FG_COL >> 2) << 5) |
+ (CONSOLE_FG_COL >> 3));
bgx = (((CONSOLE_BG_COL >> 3) << 27) |
- ((CONSOLE_BG_COL >> 2) << 21) | ((CONSOLE_BG_COL >> 3) << 16) |
- ((CONSOLE_BG_COL >> 3) << 11) | ((CONSOLE_BG_COL >> 2) << 5) |
- (CONSOLE_BG_COL >> 3));
+ ((CONSOLE_BG_COL >> 2) << 21) |
+ ((CONSOLE_BG_COL >> 3) << 16) |
+ ((CONSOLE_BG_COL >> 3) << 11) |
+ ((CONSOLE_BG_COL >> 2) << 5) |
+ (CONSOLE_BG_COL >> 3));
break;
case GDF_32BIT_X888RGB:
- fgx = (CONSOLE_FG_COL << 16) | (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL;
- bgx = (CONSOLE_BG_COL << 16) | (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL;
+ fgx = (CONSOLE_FG_COL << 16) |
+ (CONSOLE_FG_COL << 8) |
+ CONSOLE_FG_COL;
+ bgx = (CONSOLE_BG_COL << 16) |
+ (CONSOLE_BG_COL << 8) |
+ CONSOLE_BG_COL;
break;
case GDF_24BIT_888RGB:
- fgx = (CONSOLE_FG_COL << 24) | (CONSOLE_FG_COL << 16) |
- (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL;
- bgx = (CONSOLE_BG_COL << 24) | (CONSOLE_BG_COL << 16) |
- (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL;
+ fgx = (CONSOLE_FG_COL << 24) |
+ (CONSOLE_FG_COL << 16) |
+ (CONSOLE_FG_COL << 8) |
+ CONSOLE_FG_COL;
+ bgx = (CONSOLE_BG_COL << 24) |
+ (CONSOLE_BG_COL << 16) |
+ (CONSOLE_BG_COL << 8) |
+ CONSOLE_BG_COL;
break;
}
eorx = fgx ^ bgx;
#ifdef CONFIG_VIDEO_LOGO
/* Plot the logo and get start point of console */
- PRINTD ("Video: Drawing the logo ...\n");
- video_console_address = video_logo ();
+ debug("Video: Drawing the logo ...\n");
+ video_console_address = video_logo();
#else
video_console_address = video_fb_address;
#endif
return 0;
}
-
-/*****************************************************************************/
-
/*
* Implement a weak default function for boards that optionally
* need to skip the video initialization.
/* As default, don't skip test */
return 0;
}
-int board_video_skip(void) __attribute__((weak, alias("__board_video_skip")));
-int drv_video_init (void)
+int board_video_skip(void)
+ __attribute__ ((weak, alias("__board_video_skip")));
+
+int drv_video_init(void)
{
int skip_dev_init;
struct stdio_dev console_dev;
return 0;
/* Init video chip - returns with framebuffer cleared */
- skip_dev_init = (video_init () == -1);
+ skip_dev_init = (video_init() == -1);
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
- PRINTD ("KBD: Keyboard init ...\n");
+ debug("KBD: Keyboard init ...\n");
skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1);
#endif
return 0;
/* Init vga device */
- memset (&console_dev, 0, sizeof (console_dev));
- strcpy (console_dev.name, "vga");
+ memset(&console_dev, 0, sizeof(console_dev));
+ strcpy(console_dev.name, "vga");
console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */
console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
console_dev.putc = video_putc; /* 'putc' function */
console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */
#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */
- if (stdio_register (&console_dev) != 0)
+ if (stdio_register(&console_dev) != 0)
return 0;
/* Return success */
static block_dev_desc_t *ext2fs_block_dev_desc;
static disk_partition_t part_info;
-int ext2fs_set_blk_dev (block_dev_desc_t * rbdd, int part)
+int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part)
{
ext2fs_block_dev_desc = rbdd;
return 0;
}
}
- return (part_info.size);
+ return part_info.size;
}
-int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) {
+int ext2fs_devread(int sector, int byte_offset, int byte_len, char *buf)
+{
char sec_buf[SECTOR_SIZE];
- unsigned block_len;
+ unsigned sectors;
-/*
- * Check partition boundaries
- */
- if ((sector < 0)
- || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >=
+ /*
+ * Check partition boundaries
+ */
+ if ((sector < 0) ||
+ ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >=
part_info.size)) {
- /* errnum = ERR_OUTSIDE_PART; */
- printf (" ** ext2fs_devread() read outside partition sector %d\n", sector);
- return (0);
+ /* errnum = ERR_OUTSIDE_PART; */
+ printf(" ** %s read outside partition sector %d\n",
+ __func__,
+ sector);
+ return 0;
}
-/*
- * Get the read to the beginning of a partition.
- */
+ /*
+ * Get the read to the beginning of a partition.
+ */
sector += byte_offset >> SECTOR_BITS;
byte_offset &= SECTOR_SIZE - 1;
- debug (" <%d, %d, %d>\n", sector, byte_offset, byte_len);
+ debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len);
if (ext2fs_block_dev_desc == NULL) {
- printf ("** Invalid Block Device Descriptor (NULL)\n");
- return (0);
+ printf(" ** %s Invalid Block Device Descriptor (NULL)\n",
+ __func__);
+ return 0;
}
if (byte_offset != 0) {
/* read first part which isn't aligned with start of sector */
if (ext2fs_block_dev_desc->
- block_read (ext2fs_block_dev_desc->dev,
- part_info.start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
- printf (" ** ext2fs_devread() read error **\n");
- return (0);
+ block_read(ext2fs_block_dev_desc->dev,
+ part_info.start + sector, 1,
+ (unsigned long *) sec_buf) != 1) {
+ printf(" ** %s read error **\n", __func__);
+ return 0;
}
- memcpy (buf, sec_buf + byte_offset,
- min (SECTOR_SIZE - byte_offset, byte_len));
- buf += min (SECTOR_SIZE - byte_offset, byte_len);
- byte_len -= min (SECTOR_SIZE - byte_offset, byte_len);
+ memcpy(buf, sec_buf + byte_offset,
+ min(SECTOR_SIZE - byte_offset, byte_len));
+ buf += min(SECTOR_SIZE - byte_offset, byte_len);
+ byte_len -= min(SECTOR_SIZE - byte_offset, byte_len);
sector++;
}
- if (byte_len == 0)
- return 1;
-
/* read sector aligned part */
- block_len = byte_len & ~(SECTOR_SIZE - 1);
-
- if (block_len == 0) {
- u8 p[SECTOR_SIZE];
-
- block_len = SECTOR_SIZE;
- ext2fs_block_dev_desc->block_read(ext2fs_block_dev_desc->dev,
- part_info.start + sector,
- 1, (unsigned long *)p);
- memcpy(buf, p, byte_len);
- return 1;
- }
+ sectors = byte_len / SECTOR_SIZE;
+
+ if (sectors > 0) {
+ if (ext2fs_block_dev_desc->block_read(
+ ext2fs_block_dev_desc->dev,
+ part_info.start + sector,
+ sectors,
+ (unsigned long *) buf) != sectors) {
+ printf(" ** %s read error - block\n", __func__);
+ return 0;
+ }
- if (ext2fs_block_dev_desc->block_read (ext2fs_block_dev_desc->dev,
- part_info.start + sector,
- block_len / SECTOR_SIZE,
- (unsigned long *) buf) !=
- block_len / SECTOR_SIZE) {
- printf (" ** ext2fs_devread() read error - block\n");
- return (0);
+ buf += sectors * SECTOR_SIZE;
+ byte_len -= sectors * SECTOR_SIZE;
+ sector += sectors;
}
- block_len = byte_len & ~(SECTOR_SIZE - 1);
- buf += block_len;
- byte_len -= block_len;
- sector += block_len / SECTOR_SIZE;
if (byte_len != 0) {
/* read rest of data which are not in whole sector */
if (ext2fs_block_dev_desc->
- block_read (ext2fs_block_dev_desc->dev,
- part_info.start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
- printf (" ** ext2fs_devread() read error - last part\n");
- return (0);
+ block_read(ext2fs_block_dev_desc->dev,
+ part_info.start + sector, 1,
+ (unsigned long *) sec_buf) != 1) {
+ printf(" ** %s read error - last part\n", __func__);
+ return 0;
}
- memcpy (buf, sec_buf, byte_len);
+ memcpy(buf, sec_buf, byte_len);
}
- return (1);
+ return 1;
}
LIB = $(obj)libfat.o
AOBJS =
-COBJS-$(CONFIG_CMD_FAT) := fat.o file.o
+COBJS-$(CONFIG_CMD_FAT) := fat.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_CMD_FAT) += file.o
+endif
SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y))
#include <altera.h>
-extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size );
-extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize );
-extern int ACEX1K_info( Altera_desc *desc );
+extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size);
+extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int ACEX1K_info(Altera_desc *desc);
-extern int CYC2_load( Altera_desc *desc, void *image, size_t size );
-extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize );
-extern int CYC2_info( Altera_desc *desc );
+extern int CYC2_load(Altera_desc *desc, const void *image, size_t size);
+extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int CYC2_info(Altera_desc *desc);
/* Slave Serial Implementation function table */
typedef struct {
#define Altera_EP2C8_SIZE 247942
#define Altera_EP2C20_SIZE 586562
#define Altera_EP2C35_SIZE 883905
+#define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */
/* Descriptor Macros
*********************************************************************/
#ifndef _AHCI_H_
#define _AHCI_H_
+#include <pci.h>
+
#define AHCI_PCI_BAR 0x24
#define AHCI_MAX_SG 56 /* hardware max is 64K */
#define AHCI_CMD_SLOT_SZ 32
u32 link_port_map; /*linkup port map*/
};
+int ahci_init(u32 base);
+
#endif
passive_parallel_asynchronous, /* parallel data */
passive_serial_asynchronous, /* serial data w/ internal clock (not used) */
altera_jtag_mode, /* jtag/tap serial (not used ) */
- fast_passive_parallel, /* fast passive parallel (FPP) */
+ fast_passive_parallel, /* fast passive parallel (FPP) */
fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */
max_altera_iface_type /* insert all new types before this */
} Altera_iface; /* end, typedef Altera_iface */
typedef enum { /* typedef Altera_Family */
- min_altera_type, /* insert all new types after this */
- Altera_ACEX1K, /* ACEX1K Family */
- Altera_CYC2, /* CYCLONII Family */
+ min_altera_type, /* insert all new types after this */
+ Altera_ACEX1K, /* ACEX1K Family */
+ Altera_CYC2, /* CYCLONII Family */
Altera_StratixII, /* StratixII Familiy */
/* Add new models here */
- max_altera_type /* insert all new types before this */
+ max_altera_type /* insert all new types before this */
} Altera_Family; /* end, typedef Altera_Family */
typedef struct { /* typedef Altera_desc */
/* Generic Altera Functions
*********************************************************************/
-extern int altera_load( Altera_desc *desc, void *image, size_t size );
-extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize );
-extern int altera_info( Altera_desc *desc );
+extern int altera_load(Altera_desc *desc, const void *image, size_t size);
+extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int altera_info(Altera_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
typedef int (*Altera_done_fn)( int cookie );
typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
-typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie);
+typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
typedef int (*Altera_abort_fn)( int cookie );
typedef int (*Altera_post_fn)( int cookie );
cmd_tbl_t *find_cmd(const char *cmd);
cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len);
-extern int cmd_usage(cmd_tbl_t *cmdtp);
+extern int cmd_usage(const cmd_tbl_t *cmdtp);
#ifdef CONFIG_AUTO_COMPLETE
extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
#ifdef CONFIG_CMD_BOOTD
extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
+#ifdef CONFIG_CMD_BOOTM
extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd);
+#else
+static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
+{
+ return 0;
+}
+#endif
extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif /* __ASSEMBLY__ */
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
#endif /* BUG */
+/* Force a compilation error if condition is true */
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
typedef void (interrupt_handler_t)(void *);
#include <asm/u-boot.h> /* boot information for Linux kernel */
void hang (void) __attribute__ ((noreturn));
+int timer_init(void);
+int cpu_init(void);
+
/* */
phys_size_t initdram (int);
int display_options (void);
int env_init (void);
void env_relocate (void);
int envmatch (uchar *, int);
-char *getenv (char *);
-int getenv_f (char *name, char *buf, unsigned len);
+char *getenv (const char *);
+int getenv_f (const char *name, char *buf, unsigned len);
int saveenv (void);
#ifdef CONFIG_PPC /* ARM version to be fixed! */
-int inline setenv (char *, char *);
+int inline setenv (const char *, const char *);
#else
-int setenv (char *, char *);
+int setenv (const char *, const char *);
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
void api_init (void);
/* common/memsize.c */
-long get_ram_size (volatile long *, long);
+long get_ram_size (long *, long);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
void irq_free_handler (int);
void reset_timer (void);
ulong get_timer (ulong base);
-void set_timer (ulong t);
void enable_interrupts (void);
int disable_interrupts (void);
unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
long simple_strtol(const char *cp,char **endp,unsigned int base);
void panic(const char *fmt, ...)
- __attribute__ ((format (__printf__, 1, 2)));
+ __attribute__ ((format (__printf__, 1, 2), noreturn));
int sprintf(char * buf, const char *fmt, ...)
__attribute__ ((format (__printf__, 2, 3)));
int vsprintf(char *buf, const char *fmt, va_list args);
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+/* Pull in stuff for the build system */
+#ifdef DO_DEPS_ONLY
+# include <environment.h>
+#endif
+
#endif /* __COMMON_H_ */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#ifdef __linux__
# include <endian.h>
# include <byteswap.h>
-#elif defined(__MACH__)
+#elif defined(__MACH__) || defined(__FreeBSD__)
# include <machine/endian.h>
typedef unsigned long ulong;
#endif
#define CONFIG_GZIP 1
#define CONFIG_ZLIB 1
+#define CONFIG_PARTITIONS 1
#endif
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
+ | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
| IRQ3 | IRQ_DSP | DSP interrupt
| IRQ4 | IRQ_DSP1 | Extra DSP interrupt
+------+----------------+------------------------------------------------------------
#define CONFIG_FMAN_ENET
#endif
+#define CONFIG_SYS_FMAN_FW
#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
-#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
#else
#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
-#define CONFIG_SYS_FMAN_FW_ADDR 0x10000000
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
#endif
+#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P2041 RDB board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_P2041RDB
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P2041
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+#define CONFIG_SRIO2 /* SRIO port 2 */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+ #define CONFIG_SYS_EXTRA_ENV_RELOC
+ #define CONFIG_ENV_IS_IN_SPI_FLASH
+ #define CONFIG_ENV_SPI_BUS 0
+ #define CONFIG_ENV_SPI_CS 0
+ #define CONFIG_ENV_SPI_MAX_HZ 10000000
+ #define CONFIG_ENV_SPI_MODE 0
+ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+ #define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+ #define CONFIG_SYS_EXTRA_ENV_RELOC
+ #define CONFIG_ENV_IS_IN_MMC
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_OFFSET (512 * 1097)
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
+ - CONFIG_ENV_SECT_SIZE)
+ #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
+ CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE (1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
+#endif
+/* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x52
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of platform clock */
+#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
+
+#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_BR0_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+ | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_FSL_CPLD
+#define CPLD_BASE 0xffdf0000 /* CPLD registers */
+#ifdef CONFIG_PHYS_64BIT
+#define CPLD_BASE_PHYS 0xfffdf0000ull
+#else
+#define CPLD_BASE_PHYS CPLD_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH 7
+#define PIXIS_LBMAP_MASK 0xf0
+#define PIXIS_LBMAP_SHIFT 4
+#define PIXIS_LBMAP_ALTBANK 0x40
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x118000
+#define CONFIG_SYS_I2C2_OFFSET 0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver */
+#define CONFIG_SYS_FMAN_FW
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
+#endif
+#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
+#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
+
+#define CONFIG_SYS_TBIPA_VALUE 8
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH /opt/nfsroot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
+ "bank_intlv=cs0_cs1\0" \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \
+ "usb_dr_mode=host\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=p2041rdb/p2041rdb.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __CONFIG_H */
* TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_HZ 1000 /* Always 1000 */
+#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
* TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_HZ 1000 /* Always 1000 */
+#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */
#define CONFIG_SYS_TEXT_BASE 0x80000000
-/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR 0xff400000
/* System clock. Primary input clock when in PCI host mode */
* DDR Setup
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+
#if defined(CONFIG_TQM_BIGFLASH) || \
(!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
+#define CONFIG_SYS_DDR_EARLY_SIZE_MB (512)
+#else
+#define CONFIG_SYS_PPC_DDR_WIMGE (0)
+#define CONFIG_SYS_DDR_EARLY_SIZE_MB (2 * 1024)
#endif
+
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_TQM8548_AG
#define CONFIG_VERY_BIG_RAM
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
+ "console=ttyO2,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
/* Default address of microcode for the Linux Fman driver */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL
+#define CONFIG_SYS_FMAN_FW
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
#endif
+#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_MMC
"fdtaddr=c00000\0" \
"fdtfile=p4080ds/p4080ds.dtb\0" \
"bdev=sda3\0" \
- "c=ffe\0" \
- "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
+ "c=ffe\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
#define CONFIG_BZIP2
/*
+ * Video
+ */
+#define CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_VIDEO_CORALP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
+
+/* Coral-PA clock frequency, geo and other both 133MHz */
+#define CONFIG_SYS_MB862xx_CCF 0x00050000
+/* Video SDRAM parameters */
+#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
+#endif
+
+/*
* Command line configuration.
*/
#include <config_cmd_default.h>
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
#define CONFIG_CMD_DFL
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_TEXT_BASE 0x97800000
+
#define CONFIG_SYS_L2CACHE_OFF
/*
#define CONFIG_CMD_SF
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA2_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_HCU4 1 /* Board is HCU4 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_405GP 1
-#define CONFIG_4xx 1
-#define CONFIG_HOSTNAME hcu4
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
-
-/*
- * Include common defines/options for all boards produced by Netstal Maschinen
- */
-#include "netstal-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
-*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-/* ... with on-chip memory here (4KBytes) */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
-/* Do not set up locked dcache as init ram. */
-#undef CONFIG_SYS_INIT_DCACHE_CS
-
-/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* Set console baudrate to 9600 */
-#define CONFIG_BAUDRATE 9600
-
-/*-----------------------------------------------------------------------
- * Flash
- *----------------------------------------------------------------------*/
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#undef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_NOWHERE
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-/* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 2048
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-/* Put the environment in Flash */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
- * the first internal I2C controller of the PPC440EPx
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-#define CONFIG_IPADDR 172.25.1.14
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_NETSTAL_DEF_ENV \
- CONFIG_NETSTAL_DEF_ENV_POWERPC \
- ""
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-/* SPD EEPROM (sdram speed config) disabled */
-#define CONFIG_SPD_EEPROM 1
-#define SPD_EEPROM_ADDRESS 0x50
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_SPR)
-
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
-#undef CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CONFIG_SYS_EBC_CFG 0x98400000
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x02005400
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
-
-#define CONFIG_SYS_EBC_PB1AP 0x03041200
-#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB2AP 0x02054500
-#define CONFIG_SYS_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB3AP 0x01840300
-#define CONFIG_SYS_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB4AP 0x01800300
-#define CONFIG_SYS_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_GPIO0_OR 0xF27FFFFF /* GPIO value */
-#define CONFIG_SYS_GPIO0_TCR 0x7FFE0000 /* GPIO value */
-#define CONFIG_SYS_GPIO0_ODR 0x00E897FC /* GPIO value */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
-
-/* Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_HCU5 1 /* Board is HCU5 */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_HOSTNAME hcu5
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
-
-/*
- * Include common defines/options for all boards produced by Netstal Maschinen
- */
-#include "netstal-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 3
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xfff00000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_BAUDRATE 115200
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#undef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_NOWHERE
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-/* Put the environment after the SDRAM and bootstrap configuration */
-#define PROM_SIZE 2048
-#define CONFIG_SYS_BOOSTRAP_OPTION_OFFSET 512
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_BOOSTRAP_OPTION_OFFSET + 0x10)
-#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-/* Put the environment in Flash */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
-#define CONFIG_SYS_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */
-#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
-#define CONFIG_DDR_ECC 1 /* enable ECC */
-
-/* Following two definitions must be kept in sync with config.h of vxWorks */
-#define USER_RESERVED_MEM ( 0) /* in kB */
-#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */
-#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM )
-
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
-
-/*-----------------------------------------------------------------------
- * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
- * the second internal I2C controller of the PPC440EPx
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_IPADDR 172.25.1.15
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_NETSTAL_DEF_ENV \
- CONFIG_NETSTAL_DEF_ENV_POWERPC \
- ""
-
-#define CONFIG_M88E1111_PHY 1
-#define CONFIG_IBM_EMAC4_V4 1
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 2
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_SPR)
-
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
-#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI 1 /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr map to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash
- *----------------------------------------------------------------------*/
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS_1 0xC8000000 /* CAN */
-#define CONFIG_SYS_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
-#define CONFIG_SYS_CPLD CONFIG_SYS_CS_2
-#define CONFIG_SYS_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */
-
-#define CONFIG_SYS_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
-#define CONFIG_SYS_EBC_PB0AP 0x02005400
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* (CONFIG_SYS_FLASH | 0xda000) */
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-
-/* Memory Bank 1 CAN-Chips initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x02054500
-#define CONFIG_SYS_EBC_PB1CR 0xC8018000
-
-/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x01840300
-#define CONFIG_SYS_EBC_PB2CR 0xCC0BA000
-
-/* Memory Bank 3 IMC-Bus fast mode initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x01800300
-#define CONFIG_SYS_EBC_PB3CR 0xCE0BA000
-
-/* Memory Bank 4 (not used) initialization */
-#undef CONFIG_SYS_EBC_PB4AP
-#undef CONFIG_SYS_EBC_PB4CR
-
-/* Memory Bank 5 (not used) initialization */
-#undef CONFIG_SYS_EBC_PB5AP
-#undef CONFIG_SYS_EBC_PB5CR
-
-#define HCU_CPLD_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x0F00000 )
-#define HCU_HW_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x1400000 )
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
- #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#endif /* __CONFIG_H */
#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
+#define CONFIG_XWAY_SWAP_BYTES
+
/*
* Clock for the MIPS core (MHz)
* allowed values: 100000000, 133000000, and 150000000 (default)
#define CONFIG_CPU_CLOCK_RATE 150000000
#endif
-#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
+#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */
-/*
- * How to get access to the slot ID. Put this here to make it easy
- * to modify in a centralized location. This is used in the HDLC
- * driver to set the MAC.
-*/
-#define CONFIG_CHECK_ETHERNET_PRESENT
-#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */
-#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */
-
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 1
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MUX
-/* EEprom support */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
/* Support the IVM EEprom */
#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_CONCAT
-/* common powerpc specific env settings */
+#define CONFIG_CMD_CRAMFS
+#define CONFIG_CRAMFS_CMDLINE
+
#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
- "bootparams=empty\0" \
- "initial_boot_bank=0\0"
+ "actual_bank=0\0"
#endif
#ifndef CONFIG_KM_DEF_NETDEV
#define str(s) #s
/*
- * bootrunner
- * - run all commands in 'subbootcmds'
- * - on error, stop running the remaing commands
- */
-#define CONFIG_KM_DEF_ENV_BOOTRUNNER \
- "bootrunner=" \
- "break=0; " \
- "for subbootcmd in ${subbootcmds}; do " \
- "if test ${break} -eq 0; then; " \
- "print ${subbootcmd}; " \
- "run ${subbootcmd} || break=1; " \
- "fi; " \
- "done\0" \
- ""
-
-/*
* boottargets
- * - set 'subbootcmds' for the bootrunner
+ * - set 'subbootcmds'
* - set 'bootcmd' and 'altbootcmd'
* available targets:
* - 'release': for a standalone system kernel/rootfs from flash
- *
- * - 'commonargs': bootargs common to all targets
*/
#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
- "commonargs=" \
- "addip " \
- "addtty " \
- "addmem " \
- "addinit " \
- "addvar " \
- "addmtdparts " \
- "addbootcount " \
- "\0" \
- "release=" \
- "setenv actual_bank ${initial_boot_bank} && " \
- "setenv subbootcmds \"" \
- "checkboardid " \
- "ubiattach ubicopy " \
- "cramfsloadfdt cramfsloadkernel " \
- "flashargs ${commonargs} " \
- "addpanic boot " \
- "\" && " \
- "setenv bootcmd \'" \
- "run actual bootrunner; reset" \
- "\' && " \
- "setenv altbootcmd \'" \
- "run backup bootrunner; reset" \
- "\' && " \
- "saveenv && saveenv && " \
- "reset\0" \
- "debug_env=" \
- "tftp 200000 " CONFIG_KM_ARCH_DBG_FILE " && " \
+ "subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \
+ "flashargs add_default addpanic boot\0" \
+ "develop=" \
+ "tftp 200000 scripts/develop-${arch}.txt && " \
"env import -t 200000 ${filesize} && " \
- "run debug_env_common\0" \
+ "run setup_debug_env\0" \
+ "ramfs=" \
+ "tftp 200000 scripts/ramfs-${arch}.txt && " \
+ "env import -t 200000 ${filesize} && " \
+ "run setup_debug_env\0" \
""
/*
* bootargs
* - modify 'bootargs'
*
- * - 'addip': add ip configuration
- * - 'addmem': limit kernel memory mem=
+ * - 'add_default': default bootargs common for all arm/ppc boards
* - 'addpanic': add kernel panic options
- * - 'addtty': add console=...
- * - 'addvar': add phram device for /var
* - 'flashargs': defaults arguments for flash base boot
*
- * processor specific settings
- * - 'addbootcount': add boot counter
- * - 'addmtdparts': add mtd partition information
*/
#define CONFIG_KM_DEF_ENV_BOOTARGS \
- "addinit=" \
- "setenv bootargs ${bootargs} init=${init}\0" \
- "addip=" \
+ "add_default=" \
"setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off\0" \
- "addmem=" \
- "setenv bootargs ${bootargs} mem=${pnvramaddr}\0" \
+ ":${hostname}:${netdev}:off3" \
+ " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \
+ " mem=${pnvramaddr} init=${init}" \
+ " phram.phram=phvar,${varaddr}," xstr(CONFIG_KM_PHRAM) \
+ " ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \
+ CONFIG_KM_DEF_BOOT_ARGS_CPU \
+ "\0" \
"addpanic=" \
"setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0" \
- "addtty=" \
- "setenv bootargs ${bootargs}" \
- " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \
- "addvar=" \
- "setenv bootargs ${bootargs} phram.phram=phvar," \
- "${varaddr}," xstr(CONFIG_KM_PHRAM) "\0" \
"flashargs=" \
"setenv bootargs " \
- "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \
"root=mtdblock:rootfs${boot_bank} " \
"rootfstype=squashfs ro\0" \
""
*/
#define CONFIG_KM_DEF_ENV_FLASH_BOOT \
"cramfsaddr=" xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \
- "cramfsloadkernel=" \
- "cramfsload ${kernel_addr_r} uImage && " \
- "setenv actual_kernel_addr ${kernel_addr_r}\0" \
+ "cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \
"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME "\0" \
"ubicopy=ubi read "xstr(CONFIG_KM_CRAMFS_ADDR) \
" bootfs${boot_bank}\0" \
* - 'default': setup default environment
*/
#define CONFIG_KM_DEF_ENV_CONSTANTS \
- "actual=setenv boot_bank ${actual_bank}\0" \
- "backup=setenv boot_bank ${backup_bank}\0" \
- "actual_bank=${initial_boot_bank}\0" \
"backup_bank=0\0" \
- "default=" \
- "setenv default 'run newenv; reset' && " \
- "run release && saveenv; reset\0" \
- "checkboardid=km_checkbidhwk\0" \
+ "release=run newenv; reset\0" \
"pnvramsize=" xstr(CONFIG_KM_PNVRAM) "\0" \
+ "testbootcmd=setenv boot_bank ${test_bank}; " \
+ "run ${subbootcmds}; reset\0" \
""
#ifndef CONFIG_KM_DEF_ENV
CONFIG_KM_DEF_ENV_BOOTPARAMS \
CONFIG_KM_DEF_NETDEV \
CONFIG_KM_DEF_ENV_CPU \
- CONFIG_KM_DEF_ENV_BOOTRUNNER \
CONFIG_KM_DEF_ENV_BOOTTARGETS \
CONFIG_KM_DEF_ENV_BOOTARGS \
CONFIG_KM_DEF_ENV_FLASH_BOOT \
CONFIG_KM_DEF_ENV_CONSTANTS \
"altbootcmd=run bootcmd\0" \
- "bootcmd=run default\0" \
+ "bootcmd=km_checkbidhwk && " \
+ " setenv bootcmd \'setenv boot_bank ${actual_bank}; " \
+ "run ${subbootcmds}; reset\' && " \
+ "setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \
+ "run ${subbootcmds}; reset\' && " \
+ "saveenv && saveenv && boot\0" \
"bootlimit=2\0" \
"init=/sbin/init-overlay.sh\0" \
- "kernel_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
- "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \
+ "load_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
+ "load=tftpboot ${load_addr_r} ${u-boot}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"stderr=serial\0" \
"stdin=serial\0" \
"stdout=serial\0" \
- "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
""
#endif /* CONFIG_KM_DEF_ENV */
#define CONFIG_CMD_DTT
#define CONFIG_JFFS2_CMDLINE
+/* EEprom support 24C08, 24C16, 24C64 */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */
#define CONFIG_KM_FDT_ADDR 0x7E0000 /* 128Kbytes */
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
+
#define CONFIG_KM_DEF_ENV_CPU \
- "addbootcount=true\0" \
- "addmtdparts=true\0" \
- "boot=bootm ${actual_kernel_addr} - ${actual_fdt_addr}\0" \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
"cramfsloadfdt=" \
"cramfsload ${fdt_addr_r} " \
- "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb && " \
- "setenv actual_fdt_addr ${fdt_addr_r}\0" \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
"fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \
+ "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"update=" \
"protect off " xstr(BOOTFLASH_START) " +${filesize} && "\
"erase " xstr(BOOTFLASH_START) " +${filesize} && " \
- "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \
+ "cp.b ${load_addr_r} " xstr(BOOTFLASH_START) \
" ${filesize} && " \
"protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \
""
-#define CONFIG_KM_ARCH_DBG_FILE "scripts/debug-ppc-env.txt"
-
#endif /* __CONFIG_KEYMILE_POWERPC_H */
"newenv=" \
"prot off 0xFE0C0000 +0x40000 && " \
"era 0xFE0C0000 +0x40000\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
+ "arch=ppc_82xx\0" \
""
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
} while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CONFIG_MPC832x /* MPC832x CPU specific */
#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
-#define CONFIG_KM_DEF_ROOTPATH \
- "rootpath=/opt/eldk/ppc_8xx\0"
+#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
/* include common defines/options for all 83xx Keymile boards */
#include "km83xx-common.h"
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif
-#ifndef CONFIG_KM_DEF_ROOTPATH
-#define CONFIG_KM_DEF_ROOTPATH \
- "rootpath=/opt/eldk/ppc_82xx\0"
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
- CONFIG_KM_DEF_ROOTPATH \
+ CONFIG_KM_DEF_ARCH \
"dtt_bus=pca9547:70:a\0" \
"EEprom_ivm=pca9547:70:9\0" \
"newenv=" \
#define CONFIG_KM_CRAMFS_ADDR 0x2400000
#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
+ "bootcountaddr=${bootcountaddr} ${mtdparts}"
+
#define CONFIG_KM_DEF_ENV_CPU \
- "addbootcount=" \
- "setenv bootargs ${bootargs} " \
- "bootcountaddr=${bootcountaddr}\0" \
- "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "boot=bootm ${actual_kernel_addr} - -\0" \
+ "boot=bootm ${load_addr_r} - -\0" \
"cramfsloadfdt=true\0" \
+ "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
CONFIG_KM_DEF_ENV_UPDATE \
""
-#define CONFIG_KM_ARCH_DBG_FILE "scripts/debug-arm-env.txt"
-
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_MISC_INIT_R
#endif
+/* EEprom support 24C128, 24C256 valid for environment eeprom */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_KM_DEF_ENV_UPDATE \
"update=" \
"spi on;sf probe 0;sf erase 0 50000;" \
- "sf write ${u-boot_addr_r} 0 ${filesize};" \
+ "sf write ${load_addr_r} 0 ${filesize};" \
"spi off\0"
/*
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
- "rootpath=/opt/eldk/arm\0" \
+ "arch=arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
+++ /dev/null
-/*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * mcu25.h - configuration for MCU25 board (similar to hcu4.h)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_MCU25 1 /* Board is MCU25 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_405GP 1
-#define CONFIG_4xx 1
-#define CONFIG_HOSTNAME mcu25
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
-
-/*
- * Include common defines/options for all boards produced by Netstal Maschinen
- */
-#include "netstal-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
-*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-/* ... with on-chip memory here (4KBytes) */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
-/* Do not set up locked dcache as init ram. */
-#undef CONFIG_SYS_INIT_DCACHE_CS
-
-/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* Set console baudrate to 9600 */
-#define CONFIG_BAUDRATE 9600
-
-/*-----------------------------------------------------------------------
- * Flash
- *----------------------------------------------------------------------*/
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#undef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_NOWHERE
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-/* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 2048
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-/* Put the environment in Flash */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
- * the first internal I2C controller of the PPC440EPx
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_IPADDR 172.25.1.25
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_NETSTAL_DEF_ENV \
- CONFIG_NETSTAL_DEF_ENV_POWERPC \
- ""
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-/* SPD EEPROM (sdram speed config) disabled */
-#define CONFIG_SPD_EEPROM 1
-#define SPD_EEPROM_ADDRESS 0x50
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_SPR)
-
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
-#undef CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CONFIG_SYS_EBC_CFG 0x98400000
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x02005400
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
-
-#define CONFIG_SYS_EBC_PB1AP 0x03041200
-#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CONFIG_SYS_EBC_PB2CR 0x7A09A000u
-
-#define CONFIG_SYS_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CONFIG_SYS_EBC_PB3CR 0x7B09A000u
-
-#define CONFIG_SYS_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CONFIG_SYS_EBC_PB4CR 0x7C09A000u
-
-#define CONFIG_SYS_EBC_PB5AP 0x00800200u
-#define CONFIG_SYS_EBC_PB5CR 0x7D81A000u
-
-#define CONFIG_SYS_EBC_PB6AP 0x01040200u
-#define CONFIG_SYS_EBC_PB6CR 0x7D91A000u
-
-#define CONFIG_SYS_GPIO0_OR 0x087FFFFF /* GPIO value */
-#define CONFIG_SYS_GPIO0_TCR 0x7FFF8000 /* GPIO value */
-#define CONFIG_SYS_GPIO0_ODR 0xFFFF0000 /* GPIO value */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
/*-----------------------------------------------------------------------
* FLASH and environment organization
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Niklaus Giger, Netstal Maschinen AG, niklaus.giger@netstal.com
- * adapted from amcc-common.h by
- * (C) Copyright 2008
- * * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Common configuration options for all Netstal boards
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __NETSTAL_COMMON_H
-#define __NETSTAL_COMMON_H
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * UART
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SERIAL_MULTI
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/* This is the 7bit address of the device, not including P. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
-/*
- * Ethernet/EMAC/PHY
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_NET_MULTI 1
-#if defined(CONFIG_440)
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* number of eth rx buffers */
-#else
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* number of eth rx buffers */
-#endif
-#define CONFIG_HAS_ETH0
-
-/*
- * Commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#if defined(CONFIG_440)
-#define CONFIG_CMD_CACHE
-#endif
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_BOOT_RETRY_TIME 30
-#define CONFIG_RESET_TO_RETRY
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_LOOPW /* enable loopw command */
-#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE /* include version env variable */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-/*
- * Booting and default environment
- */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
- "echo"
-#define CONFIG_BOOTCOMMAND "run vx"
-
-/*
- * Only very few boards have default console not on ttyS0 (like Taishan)
- */
-#if !defined(CONFIG_USE_TTY)
-#define CONFIG_USE_TTY ttyS0
-#endif
-
-/*
- * Only some 4xx PPC's are equipped with an FPU
- */
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
-/*
- * Only some boards need to extend the bootargs by some additional
- * parameters (like Makalu)
- */
-#if !defined(CONFIG_ADDMISC)
-#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0"
-#endif
-
-#define xstr(s) str(s)
-#define str(s) #s
-
-/* Setup some values for the default environment variables */
-#define CONFIG_SERVERIP 172.25.1.1
-#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_SYS_TFTP_LOADADDR 0x01000000
-#define CONFIG_SYS_VXWORKS_ADD_PARAMS "u=dpu pw=netstal8752"
-#define CONFIG_SYS_VXWORKS_SERVERNAME "c"
-/*
- * General common environment variables shared by all boards produced by Netstal Maschinen
- */
-#define CONFIG_NETSTAL_DEF_ENV \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
- CONFIG_ADDMISC \
- "initrd_high=30000000\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "uload=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " " \
- xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "vx_rom=" xstr(CONFIG_HOSTNAME) "/" \
- xstr(CONFIG_HOSTNAME) "_vx_rom\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"\
- "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} "xstr(CONFIG_SYS_MONITOR_BASE) \
- " ${filesize}; setenv filesize\0" \
- "upd=run uload update\0" \
- "vx=setenv bootfile ${vx_rom}; tftp " \
- xstr(CONFIG_SYS_TFTP_LOADADDR) "; bootvx\0" \
- CONFIG_NETSTAL_DEF_ENV_ROOTPATH
-
-/*
- * Default environment for arch/powerpc booting
- * for boards that are ported to arch/powerpc
- */
-#define CONFIG_NETSTAL_DEF_ENV_POWERPC \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
-
-#endif /* __NETSTAL_COMMON_H */
/*
* TIMER
*/
+#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_TIMER_BASE
#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_TIMER_IRQ
#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
+#define CONFIG_SYS_TEXT_BASE 0x10000000
+
+#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
+
/*
* Configuration for FLASH memory for the Synertronixx board
*/
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA2_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#endif /* __CONFIG_H */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#define CONFIG_MPC8560 1
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
/*
* I2C
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_STACKSIZE (256*1024)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
/* Serial Driver Info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
--- /dev/null
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Configuation settings for the zmx25 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_MX25
+#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "gs_fast_boot=setenv bootdelay 5\0" \
+ "gs_slow_boot=setenv bootdelay 10\0" \
+ "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
+ "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
+ "bootm 0x81000000; bootelf 0x81000000\0"
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define BOARD_LATE_INIT
+
+/*
+ * Compressions
+ */
+#define CONFIG_LZO
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * Serial
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX25_UART2
+#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR 0x00
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/*
+ * Additional command
+ */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORT 2
+#define CONFIG_MXC_USB_PORTSC 0xC0000000
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE 0xA0000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+#define CONFIG_SYS_PROMPT "zmx25> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_PREBOOT ""
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
+#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#endif /* __CONFIG_H */
/* The build system likes to know if the env is embedded */
#ifdef DO_DEPS_ONLY
# ifdef ENV_IS_EMBEDDED
-# define CONFIG_ENV_IS_EMBEDDED
+# ifndef CONFIG_ENV_IS_EMBEDDED
+# define CONFIG_ENV_IS_EMBEDDED
+# endif
# endif
#endif
unsigned char env_get_char (int);
/* Function that returns a pointer to a value from the environment */
-unsigned char *env_get_addr(int);
+const unsigned char *env_get_addr(int);
unsigned char env_get_char_memory (int index);
/* Function that updates CRC of the enironment */
int vprintf(const char *, va_list);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
-char *getenv (char *name);
-int setenv (char *varname, char *varvalue);
+char *getenv (const char *name);
+int setenv (const char *varname, const char *varvalue);
long simple_strtol(const char *cp,char **endp,unsigned int base);
int strcmp(const char * cs,const char * ct);
int ustrtoul(const char *cp, char **endp, unsigned int base);
void set_working_fdt_addr(void *addr);
int fdt_resize(void *blob);
+int fdt_increase_size(void *fdt, int add_len);
int fdt_fixup_nor_flash_size(void *blob);
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
phys_addr_t compat_off);
int fdt_alloc_phandle(void *blob);
+int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle);
int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
+int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
+ u64 addr);
+u64 fdt_get_base_address(void *fdt, int node);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
/* root function definitions */
-extern void fpga_init( void );
-extern int fpga_add( fpga_type devtype, void *desc );
-extern int fpga_count( void );
-extern int fpga_load( int devnum, void *buf, size_t bsize );
-extern int fpga_dump( int devnum, void *buf, size_t bsize );
-extern int fpga_info( int devnum );
+extern void fpga_init(void);
+extern int fpga_add(fpga_type devtype, void *desc);
+extern int fpga_count(void);
+extern int fpga_load(int devnum, const void *buf, size_t bsize);
+extern int fpga_dump(int devnum, const void *buf, size_t bsize);
+extern int fpga_info(int devnum);
#endif /* _FPGA_H_ */
#define CHANNEL2_REGISTER10 0x9070
#define CHANNEL2_REGISTER11 0x9074
-/* MPSCs Interupts */
+/* MPSCs Interrupts */
#define MPSC0_CAUSE 0xb824
#define MPSC0_MASK 0xb8a4
#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */
#define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */
#define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */
+#define IH_TYPE_UBLIMAGE 11 /* Davinci UBL Image */
/*
* Compression Types
const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
/**
+ * fdt_first_property_offset - find the offset of a node's first property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ *
+ * fdt_first_property_offset() finds the first property of the node at
+ * the given structure block offset.
+ *
+ * returns:
+ * structure block offset of the property (>=0), on success
+ * -FDT_ERR_NOTFOUND, if the requested node has no properties
+ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_first_property_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_next_property_offset - step through a node's properties
+ * @fdt: pointer to the device tree blob
+ * @offset: structure block offset of a property
+ *
+ * fdt_next_property_offset() finds the property immediately after the
+ * one at the given structure block offset. This will be a property
+ * of the same node as the given property.
+ *
+ * returns:
+ * structure block offset of the next property (>=0), on success
+ * -FDT_ERR_NOTFOUND, if the given property is the last in its node
+ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_next_property_offset(const void *fdt, int offset);
+
+/**
+ * fdt_get_property_by_offset - retrieve the property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @offset: offset of the property to retrieve
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property_by_offset() retrieves a pointer to the
+ * fdt_property structure within the device tree blob at the given
+ * offset. If lenp is non-NULL, the length of the property value is
+ * also returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ * pointer to the structure representing the property
+ * if lenp is non-NULL, *lenp contains the length of the property
+ * value (>=0)
+ * NULL, on error
+ * if lenp is non-NULL, *lenp contains an error code (<0):
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+ int offset,
+ int *lenp);
+
+/**
* fdt_get_property_namelen - find a property based on substring
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to find
}
/**
+ * fdt_getprop_by_offset - retrieve the value of a property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @ffset: offset of the property to read
+ * @namep: pointer to a string variable (will be overwritten) or NULL
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop_by_offset() retrieves a pointer to the value of the
+ * property at structure block offset 'offset' (this will be a pointer
+ * to within the device blob itself, not a copy of the value). If
+ * lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp. If namep is non-NULL,
+ * the property's namne will also be returned in the char * pointed to
+ * by namep (this will be a pointer to within the device tree's string
+ * block, not a new copy of the name).
+ *
+ * returns:
+ * pointer to the property's value
+ * if lenp is non-NULL, *lenp contains the length of the property
+ * value (>=0)
+ * if namep is non-NULL *namep contiains a pointer to the property
+ * name.
+ * NULL, on error
+ * if lenp is non-NULL, *lenp contains an error code (<0):
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+ const char **namep, int *lenp);
+
+/**
* fdt_getprop_namelen - get property value based on substring
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to find
#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
+#define MDIO_DEVS_LINK (MDIO_DEVS_PMAPMD | \
+ MDIO_DEVS_WIS | \
+ MDIO_DEVS_PCS | \
+ MDIO_DEVS_PHYXS | \
+ MDIO_DEVS_DTEXS | \
+ MDIO_DEVS_AN)
+
+
/* Control register 2. */
#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
#define MMC_MODE_4BIT 0x100
#define MMC_MODE_8BIT 0x200
#define MMC_MODE_SPI 0x400
+#define MMC_MODE_HC 0x800
#define SD_DATA_4BIT 0x00040000
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
+#define MMC_CMD_ERASE_GROUP_START 35
+#define MMC_CMD_ERASE_GROUP_END 36
+#define MMC_CMD_ERASE 38
#define MMC_CMD_APP_CMD 55
#define MMC_CMD_SPI_READ_OCR 58
#define MMC_CMD_SPI_CRC_ON_OFF 59
#define SD_CMD_SEND_IF_COND 8
#define SD_CMD_APP_SET_BUS_WIDTH 6
+#define SD_CMD_ERASE_WR_BLK_START 32
+#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_APP_SEND_OP_COND 41
#define SD_CMD_APP_SEND_SCR 51
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
+#define SECURE_ERASE 0x80000000
+
#define MMC_STATUS_MASK (~0x0206BF7F)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
#define MMC_STATUS_CURR_STATE (0xf << 9)
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
+ uint erase_grp_size;
u64 capacity;
block_dev_desc_t block_dev;
int (*send_cmd)(struct mmc *mmc,
sdma->IntPend = (1 << tasknum); \
}
-/* get interupt pending bit of a task */
+/* get interrupt pending bit of a task */
#define SDMA_GET_PENDINGBIT(tasknum) \
((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
-/* get interupt mask bit of a task */
+/* get interrupt mask bit of a task */
#define SDMA_GET_MASKBIT(tasknum) \
((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
#define PLTR 0x8000000d /* PCI Latancy Timer Register */
#define PHTR 0x8000000e /* PCI Header Type Register */
#define BISTCTRL 0x8000000f /* BIST Control */
-#define LMBAR 0x80000010 /* Local Base Addres Register */
+#define LMBAR 0x80000010 /* Local Base Address Register */
#define PCSRBAR 0x80000014 /* PCSR Base Address Register */
#define ILR 0x8000003c /* PCI Interrupt Line Register */
#define IPR 0x8000003d /* Interrupt Pin Register */
#ifndef __MXC_GPIO_H
#define __MXC_GPIO_H
+/* Converts a GPIO port number and the internal bit position
+ * to the GPIO number
+ */
+#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f))
+
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
MXC_GPIO_DIRECTION_OUT,
unsigned long start,
lbaint_t blkcnt,
const void *buffer);
+ unsigned long (*block_erase)(int dev,
+ unsigned long start,
+ lbaint_t blkcnt);
void *priv; /* driver private struct pointer */
}block_dev_desc_t;
} disk_partition_t;
/* Misc _get_dev functions */
+#ifdef CONFIG_PARTITIONS
block_dev_desc_t* get_dev(char* ifname, int dev);
block_dev_desc_t* ide_get_dev(int dev);
block_dev_desc_t* sata_get_dev(int dev);
void print_part (block_dev_desc_t *dev_desc);
void init_part (block_dev_desc_t *dev_desc);
void dev_print(block_dev_desc_t *dev_desc);
-
+#else
+static inline block_dev_desc_t* get_dev(char* ifname, int dev) { return NULL; }
+static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
+
+static inline int get_partition_info (block_dev_desc_t * dev_desc, int part,
+ disk_partition_t *info) { return -1; }
+static inline void print_part (block_dev_desc_t *dev_desc) {}
+static inline void init_part (block_dev_desc_t *dev_desc) {}
+static inline void dev_print(block_dev_desc_t *dev_desc) {}
+#endif
#ifdef CONFIG_MAC_PARTITION
/* disk/part_mac.c */
extern struct post_test post_list[];
extern unsigned int post_list_size;
extern int post_hotkeys_pressed(void);
+extern int memory_post_test(int flags);
/*
* If GCC is configured to use a version of GAS that supports
#define CONFIG_SYS_POST_BSPEC5 0x00100000
#define CONFIG_SYS_POST_CODEC 0x00200000
#define CONFIG_SYS_POST_COPROC 0x00400000
+#define CONFIG_SYS_POST_FLASH 0x00800000
#endif /* CONFIG_POST */
* functions residing inside cmd_scsi.c
*/
void scsi_init(void);
+void scsi_scan(int mode);
#define SCSI_IDENTIFY 0xC0 /* not used */
--- /dev/null
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+#ifndef __SDHCI_HW_H
+#define __SDHCI_HW_H
+
+#include <asm/io.h>
+/*
+ * Controller registers
+ */
+
+#define SDHCI_DMA_ADDRESS 0x00
+
+#define SDHCI_BLOCK_SIZE 0x04
+#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
+
+#define SDHCI_BLOCK_COUNT 0x06
+
+#define SDHCI_ARGUMENT 0x08
+
+#define SDHCI_TRANSFER_MODE 0x0C
+#define SDHCI_TRNS_DMA 0x01
+#define SDHCI_TRNS_BLK_CNT_EN 0x02
+#define SDHCI_TRNS_ACMD12 0x04
+#define SDHCI_TRNS_READ 0x10
+#define SDHCI_TRNS_MULTI 0x20
+
+#define SDHCI_COMMAND 0x0E
+#define SDHCI_CMD_RESP_MASK 0x03
+#define SDHCI_CMD_CRC 0x08
+#define SDHCI_CMD_INDEX 0x10
+#define SDHCI_CMD_DATA 0x20
+#define SDHCI_CMD_ABORTCMD 0xC0
+
+#define SDHCI_CMD_RESP_NONE 0x00
+#define SDHCI_CMD_RESP_LONG 0x01
+#define SDHCI_CMD_RESP_SHORT 0x02
+#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
+
+#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
+
+#define SDHCI_RESPONSE 0x10
+
+#define SDHCI_BUFFER 0x20
+
+#define SDHCI_PRESENT_STATE 0x24
+#define SDHCI_CMD_INHIBIT 0x00000001
+#define SDHCI_DATA_INHIBIT 0x00000002
+#define SDHCI_DOING_WRITE 0x00000100
+#define SDHCI_DOING_READ 0x00000200
+#define SDHCI_SPACE_AVAILABLE 0x00000400
+#define SDHCI_DATA_AVAILABLE 0x00000800
+#define SDHCI_CARD_PRESENT 0x00010000
+#define SDHCI_WRITE_PROTECT 0x00080000
+
+#define SDHCI_HOST_CONTROL 0x28
+#define SDHCI_CTRL_LED 0x01
+#define SDHCI_CTRL_4BITBUS 0x02
+#define SDHCI_CTRL_HISPD 0x04
+#define SDHCI_CTRL_DMA_MASK 0x18
+#define SDHCI_CTRL_SDMA 0x00
+#define SDHCI_CTRL_ADMA1 0x08
+#define SDHCI_CTRL_ADMA32 0x10
+#define SDHCI_CTRL_ADMA64 0x18
+#define SDHCI_CTRL_8BITBUS 0x20
+
+#define SDHCI_POWER_CONTROL 0x29
+#define SDHCI_POWER_ON 0x01
+#define SDHCI_POWER_180 0x0A
+#define SDHCI_POWER_300 0x0C
+#define SDHCI_POWER_330 0x0E
+
+#define SDHCI_BLOCK_GAP_CONTROL 0x2A
+
+#define SDHCI_WAKE_UP_CONTROL 0x2B
+#define SDHCI_WAKE_ON_INT 0x01
+#define SDHCI_WAKE_ON_INSERT 0x02
+#define SDHCI_WAKE_ON_REMOVE 0x04
+
+#define SDHCI_CLOCK_CONTROL 0x2C
+#define SDHCI_DIVIDER_SHIFT 8
+#define SDHCI_DIVIDER_HI_SHIFT 6
+#define SDHCI_DIV_MASK 0xFF
+#define SDHCI_DIV_MASK_LEN 8
+#define SDHCI_DIV_HI_MASK 0x300
+#define SDHCI_CLOCK_CARD_EN 0x0004
+#define SDHCI_CLOCK_INT_STABLE 0x0002
+#define SDHCI_CLOCK_INT_EN 0x0001
+
+#define SDHCI_TIMEOUT_CONTROL 0x2E
+
+#define SDHCI_SOFTWARE_RESET 0x2F
+#define SDHCI_RESET_ALL 0x01
+#define SDHCI_RESET_CMD 0x02
+#define SDHCI_RESET_DATA 0x04
+
+#define SDHCI_INT_STATUS 0x30
+#define SDHCI_INT_ENABLE 0x34
+#define SDHCI_SIGNAL_ENABLE 0x38
+#define SDHCI_INT_RESPONSE 0x00000001
+#define SDHCI_INT_DATA_END 0x00000002
+#define SDHCI_INT_DMA_END 0x00000008
+#define SDHCI_INT_SPACE_AVAIL 0x00000010
+#define SDHCI_INT_DATA_AVAIL 0x00000020
+#define SDHCI_INT_CARD_INSERT 0x00000040
+#define SDHCI_INT_CARD_REMOVE 0x00000080
+#define SDHCI_INT_CARD_INT 0x00000100
+#define SDHCI_INT_ERROR 0x00008000
+#define SDHCI_INT_TIMEOUT 0x00010000
+#define SDHCI_INT_CRC 0x00020000
+#define SDHCI_INT_END_BIT 0x00040000
+#define SDHCI_INT_INDEX 0x00080000
+#define SDHCI_INT_DATA_TIMEOUT 0x00100000
+#define SDHCI_INT_DATA_CRC 0x00200000
+#define SDHCI_INT_DATA_END_BIT 0x00400000
+#define SDHCI_INT_BUS_POWER 0x00800000
+#define SDHCI_INT_ACMD12ERR 0x01000000
+#define SDHCI_INT_ADMA_ERROR 0x02000000
+
+#define SDHCI_INT_NORMAL_MASK 0x00007FFF
+#define SDHCI_INT_ERROR_MASK 0xFFFF8000
+
+#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
+ SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
+#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
+ SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
+ SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
+ SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
+#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
+
+#define SDHCI_ACMD12_ERR 0x3C
+
+/* 3E-3F reserved */
+
+#define SDHCI_CAPABILITIES 0x40
+#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
+#define SDHCI_TIMEOUT_CLK_SHIFT 0
+#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
+#define SDHCI_CLOCK_BASE_MASK 0x00003F00
+#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
+#define SDHCI_CLOCK_BASE_SHIFT 8
+#define SDHCI_MAX_BLOCK_MASK 0x00030000
+#define SDHCI_MAX_BLOCK_SHIFT 16
+#define SDHCI_CAN_DO_8BIT 0x00040000
+#define SDHCI_CAN_DO_ADMA2 0x00080000
+#define SDHCI_CAN_DO_ADMA1 0x00100000
+#define SDHCI_CAN_DO_HISPD 0x00200000
+#define SDHCI_CAN_DO_SDMA 0x00400000
+#define SDHCI_CAN_VDD_330 0x01000000
+#define SDHCI_CAN_VDD_300 0x02000000
+#define SDHCI_CAN_VDD_180 0x04000000
+#define SDHCI_CAN_64BIT 0x10000000
+
+#define SDHCI_CAPABILITIES_1 0x44
+
+#define SDHCI_MAX_CURRENT 0x48
+
+/* 4C-4F reserved for more max current */
+
+#define SDHCI_SET_ACMD12_ERROR 0x50
+#define SDHCI_SET_INT_ERROR 0x52
+
+#define SDHCI_ADMA_ERROR 0x54
+
+/* 55-57 reserved */
+
+#define SDHCI_ADMA_ADDRESS 0x58
+
+/* 60-FB reserved */
+
+#define SDHCI_SLOT_INT_STATUS 0xFC
+
+#define SDHCI_HOST_VERSION 0xFE
+#define SDHCI_VENDOR_VER_MASK 0xFF00
+#define SDHCI_VENDOR_VER_SHIFT 8
+#define SDHCI_SPEC_VER_MASK 0x00FF
+#define SDHCI_SPEC_VER_SHIFT 0
+#define SDHCI_SPEC_100 0
+#define SDHCI_SPEC_200 1
+#define SDHCI_SPEC_300 2
+
+/*
+ * End of controller registers.
+ */
+
+#define SDHCI_MAX_DIV_SPEC_200 256
+#define SDHCI_MAX_DIV_SPEC_300 2046
+
+/*
+ * quirks
+ */
+#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
+
+/*
+ * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
+ */
+#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
+#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
+struct sdhci_ops {
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+ u32 (*read_l)(struct sdhci_host *host, int reg);
+ u16 (*read_w)(struct sdhci_host *host, int reg);
+ u8 (*read_b)(struct sdhci_host *host, int reg);
+ void (*write_l)(struct sdhci_host *host, u32 val, int reg);
+ void (*write_w)(struct sdhci_host *host, u16 val, int reg);
+ void (*write_b)(struct sdhci_host *host, u8 val, int reg);
+#endif
+};
+
+struct sdhci_host {
+ char *name;
+ void *ioaddr;
+ unsigned int quirks;
+ unsigned int version;
+ unsigned int clock;
+ const struct sdhci_ops *ops;
+};
+
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+
+static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+ if (unlikely(host->ops->write_l))
+ host->ops->write_l(host, val, reg);
+ else
+ writel(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
+{
+ if (unlikely(host->ops->write_w))
+ host->ops->write_w(host, val, reg);
+ else
+ writew(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+ if (unlikely(host->ops->write_b))
+ host->ops->write_b(host, val, reg);
+ else
+ writeb(val, host->ioaddr + reg);
+}
+
+static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
+{
+ if (unlikely(host->ops->read_l))
+ return host->ops->read_l(host, reg);
+ else
+ return readl(host->ioaddr + reg);
+}
+
+static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
+{
+ if (unlikely(host->ops->read_w))
+ return host->ops->read_w(host, reg);
+ else
+ return readw(host->ioaddr + reg);
+}
+
+static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
+{
+ if (unlikely(host->ops->read_b))
+ return host->ops->read_b(host, reg);
+ else
+ return readb(host->ioaddr + reg);
+}
+
+#else
+
+static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+ writel(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
+{
+ writew(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+ writeb(val, host->ioaddr + reg);
+}
+static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
+{
+ return readl(host->ioaddr + reg);
+}
+
+static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
+{
+ return readw(host->ioaddr + reg);
+}
+
+static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
+{
+ return readb(host->ioaddr + reg);
+}
+#endif
+
+int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
+#endif /* __SDHCI_HW_H */
} ACTION;
typedef struct entry {
- char *key;
+ const char *key;
char *data;
} ENTRY;
#ifndef __SERIAL_H__
#define __SERIAL_H__
+#include <post.h>
+
#define NAMESIZE 16
-#define CTLRSIZE 8
struct serial_device {
char name[NAMESIZE];
- char ctlr[CTLRSIZE];
int (*init) (void);
int (*uninit) (void);
int (*tstc) (void);
void (*putc) (const char c);
void (*puts) (const char *s);
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+ void (*loop) (int);
+#endif
struct serial_device *next;
};
#include <xilinx.h>
-extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size );
-extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int Spartan2_info( Xilinx_desc *desc );
+extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int Spartan2_info(Xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
#include <xilinx.h>
-extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size );
-extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int Spartan3_info( Xilinx_desc *desc );
+extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int Spartan3_info(Xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
const char *name;
+ /* Total flash size */
u32 size;
-
+ /* Write (page) size */
+ u32 page_size;
+ /* Erase (sector) size */
u32 sector_size;
int (*read)(struct spi_flash *flash, u32 offset,
return IS_ERR_VALUE((unsigned long)ptr);
}
-/* Force a compilation error if condition is true */
-#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
-
/* module */
#define THIS_MODULE 0
#define try_module_get(...) 1
#ifndef __VERSION_H__
#define __VERSION_H__
+#include <timestamp.h>
+
#ifndef DO_DEPS_ONLY
#include "version_autogenerated.h"
#endif
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
+ U_BOOT_TIME ")" CONFIG_IDENT_STRING
+
+#ifndef __ASSEMBLY__
+extern const char version_string[];
+#endif /* __ASSEMBLY__ */
#endif /* __VERSION_H__ */
#include <xilinx.h>
-extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size );
-extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int Virtex2_info( Xilinx_desc *desc );
+extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int Virtex2_info(Xilinx_desc *desc);
/*
* Slave SelectMap Implementation function table.
/* Generic Xilinx Functions
*********************************************************************/
-extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size );
-extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int xilinx_info( Xilinx_desc *desc );
+extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int xilinx_info(Xilinx_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
LIB = $(obj)libgeneric.o
+ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
COBJS-$(CONFIG_BZIP2) += bzlib.o
COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
COBJS-y += crc7.o
COBJS-y += crc16.o
COBJS-y += crc32.o
-COBJS-y += ctype.o
COBJS-y += display_options.o
-COBJS-y += div64.o
COBJS-y += errno.o
COBJS-$(CONFIG_GZIP) += gunzip.o
COBJS-y += hashtable.o
COBJS-y += qsort.o
COBJS-$(CONFIG_SHA1) += sha1.o
COBJS-$(CONFIG_SHA256) += sha256.o
-COBJS-y += string.o
COBJS-y += strmhz.o
+COBJS-$(CONFIG_RBTREE) += rbtree.o
+endif
+
+COBJS-y += ctype.o
+COBJS-y += div64.o
+COBJS-y += string.o
COBJS-y += time.o
COBJS-y += vsprintf.o
-COBJS-$(CONFIG_RBTREE) += rbtree.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#include <config.h>
#include <common.h>
+#include <version.h>
#include <linux/ctype.h>
#include <asm/io.h>
int display_options (void)
{
- extern char version_string[];
-
#if defined(BUILD_TAG)
printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG);
#else
if (htab->table[i].used > 0) {
ENTRY *ep = &htab->table[i].entry;
- free(ep->key);
+ free((void *)ep->key);
free(ep->data);
}
}
/* free used ENTRY */
debug("hdelete: DELETING key \"%s\"\n", key);
- free(ep->key);
+ free((void *)ep->key);
free(ep->data);
htab->table[idx].used = -1;
* export sorted list of result data
*/
for (i = 0, p = res; i < n; ++i) {
- char *s;
+ const char *s;
s = list[i]->key;
while (*s)
return offset;
}
+int _fdt_check_prop_offset(const void *fdt, int offset)
+{
+ if ((offset < 0) || (offset % FDT_TAGSIZE)
+ || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP))
+ return -FDT_ERR_BADOFFSET;
+
+ return offset;
+}
+
int fdt_next_node(const void *fdt, int offset, int *depth)
{
int nextoffset = 0;
return i;
}
+static int _nextprop(const void *fdt, int offset)
+{
+ uint32_t tag;
+ int nextoffset;
+
+ do {
+ tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+ switch (tag) {
+ case FDT_END:
+ if (nextoffset >= 0)
+ return -FDT_ERR_BADSTRUCTURE;
+ else
+ return nextoffset;
+
+ case FDT_PROP:
+ return offset;
+ }
+ offset = nextoffset;
+ } while (tag == FDT_NOP);
+
+ return -FDT_ERR_NOTFOUND;
+}
+
int fdt_subnode_offset_namelen(const void *fdt, int offset,
const char *name, int namelen)
{
return NULL;
}
-const struct fdt_property *fdt_get_property_namelen(const void *fdt,
- int nodeoffset,
- const char *name,
- int namelen, int *lenp)
+int fdt_first_property_offset(const void *fdt, int nodeoffset)
+{
+ int offset;
+
+ if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+ return offset;
+
+ return _nextprop(fdt, offset);
+}
+
+int fdt_next_property_offset(const void *fdt, int offset)
+{
+ if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0)
+ return offset;
+
+ return _nextprop(fdt, offset);
+}
+
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+ int offset,
+ int *lenp)
{
- uint32_t tag;
- const struct fdt_property *prop;
- int offset, nextoffset;
int err;
+ const struct fdt_property *prop;
- if (((err = fdt_check_header(fdt)) != 0)
- || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
- goto fail;
+ if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) {
+ if (lenp)
+ *lenp = err;
+ return NULL;
+ }
- nextoffset = err;
- do {
- offset = nextoffset;
+ prop = _fdt_offset_ptr(fdt, offset);
- tag = fdt_next_tag(fdt, offset, &nextoffset);
- switch (tag) {
- case FDT_END:
- if (nextoffset < 0)
- err = nextoffset;
- else
- /* FDT_END tag with unclosed nodes */
- err = -FDT_ERR_BADSTRUCTURE;
- goto fail;
+ if (lenp)
+ *lenp = fdt32_to_cpu(prop->len);
- case FDT_PROP:
- prop = _fdt_offset_ptr(fdt, offset);
- if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff),
- name, namelen)) {
- /* Found it! */
- if (lenp)
- *lenp = fdt32_to_cpu(prop->len);
-
- return prop;
- }
+ return prop;
+}
+
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+ int offset,
+ const char *name,
+ int namelen, int *lenp)
+{
+ for (offset = fdt_first_property_offset(fdt, offset);
+ (offset >= 0);
+ (offset = fdt_next_property_offset(fdt, offset))) {
+ const struct fdt_property *prop;
+
+ if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) {
+ offset = -FDT_ERR_INTERNAL;
break;
}
- } while ((tag != FDT_BEGIN_NODE) && (tag != FDT_END_NODE));
+ if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff),
+ name, namelen))
+ return prop;
+ }
- err = -FDT_ERR_NOTFOUND;
- fail:
if (lenp)
- *lenp = err;
+ *lenp = offset;
return NULL;
}
return prop->data;
}
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+ const char **namep, int *lenp)
+{
+ const struct fdt_property *prop;
+
+ prop = fdt_get_property_by_offset(fdt, offset, lenp);
+ if (!prop)
+ return NULL;
+ if (namep)
+ *namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
+ return prop->data;
+}
+
const void *fdt_getprop(const void *fdt, int nodeoffset,
const char *name, int *lenp)
{
const uint32_t *php;
int len;
- php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
- if (!php || (len != sizeof(*php)))
- return 0;
+ /* FIXME: This is a bit sub-optimal, since we potentially scan
+ * over all the properties twice. */
+ php = fdt_getprop(fdt, nodeoffset, "phandle", &len);
+ if (!php || (len != sizeof(*php))) {
+ php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
+ if (!php || (len != sizeof(*php)))
+ return 0;
+ }
return fdt32_to_cpu(*php);
}
int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
{
+ int offset;
+
if ((phandle == 0) || (phandle == -1))
return -FDT_ERR_BADPHANDLE;
- phandle = cpu_to_fdt32(phandle);
- return fdt_node_offset_by_prop_value(fdt, -1, "linux,phandle",
- &phandle, sizeof(phandle));
+
+ FDT_CHECK_HEADER(fdt);
+
+ /* FIXME: The algorithm here is pretty horrible: we
+ * potentially scan each property of a node in
+ * fdt_get_phandle(), then if that didn't find what
+ * we want, we scan over them again making our way to the next
+ * node. Still it's the easiest to implement approach;
+ * performance can come later. */
+ for (offset = fdt_next_node(fdt, -1, NULL);
+ offset >= 0;
+ offset = fdt_next_node(fdt, offset, NULL)) {
+ if (fdt_get_phandle(fdt, offset) == phandle)
+ return offset;
+ }
+
+ return offset; /* error from fdt_next_node() */
}
static int _fdt_stringlist_contains(const char *strlist, int listlen,
}
int _fdt_check_node_offset(const void *fdt, int offset);
+int _fdt_check_prop_offset(const void *fdt, int offset);
const char *_fdt_find_string(const char *strtab, int tabsize, const char *s);
int _fdt_node_end_offset(void *fdt, int nodeoffset);
unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src;
char *d8, *s8;
+ if (src == dest)
+ return dest;
+
/* while all data is aligned (common case), copy a word at a time */
if ( (((ulong)dest | (ulong)src) & (sizeof(*dl) - 1)) == 0) {
while (count >= sizeof(*dl)) {
{
char *tmp, *s;
+ if (src == dest)
+ return dest;
+
if (dest <= src) {
tmp = (char *) dest;
s = (char *) src;
udelay (100000); /* allow messages to go out */
do_reset (NULL, 0, 0, NULL);
#endif
+ while (1)
+ ;
}
echo "/* Automatically generated - do not edit */" >>config.h
for i in ${TARGETS} ; do
- i="`echo ${i} | sed '/=/ {s/=/\t/;q } ; { s/$/\t1/ }'`"
+ i="`echo ${i} | sed '/=/ {s/=/ /;q; } ; { s/$/ 1/; }'`"
echo "#define CONFIG_${i}" >>config.h ;
done
LDFLAGS = -Bstatic -T $(mmcobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_MMC_SPL
CFLAGS += -DCONFIG_MMC_SPL
-CFLAGS += -DCONFIG_PRELOADER
+CFLAGS += -DCONFIG_SPL_BUILD
SOBJS = start.o mem_setup.o lowlevel_init.o
COBJS = mmc_boot.o
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
SOBJS = start.o _udivsi3.o _divsi3.o
COBJS = cpu.o davinci_nand.o ns16550.o div0.o davinci_pinmux.o psc.o \
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
SOBJS = start.o lowlevel_init.o
COBJS = nand_boot_fsl_nfc.o
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
SOBJS = start.o lowlevel_init.o
COBJS = nand_boot_fsl_nfc.o
NetOurNISDomain[size] = 0;
}
break;
+#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_NTPSERVER)
+ case 42: /* NTP server IP */
+ NetCopyIP(&NetNtpServerIP, (IPaddr_t *) (ext + 2));
+ break;
+#endif
/* Application layer fields */
case 43: /* Vendor specific info - Not yet supported */
/*
if (NetBootFileSize)
debug("NetBootFileSize: %d\n", NetBootFileSize);
+
+#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_NTPSERVER)
+ if (NetNtpServerIP)
+ debug("NetNtpServerIP : %pI4\n", &NetNtpServerIP);
+#endif
}
/*
* Handle a BOOTP received packet.
*e++ = 32;
e += 32;
#endif
+#if defined(CONFIG_BOOTP_NTPSERVER)
+ *e++ = 42;
+ *e++ = 4;
+ e += 4;
+#endif
*e++ = 255; /* End of the list */
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
-AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
-CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
+AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
+CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
SOBJS := low_levelinit.o
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
-AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
-CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
+AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
+CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
SOBJS += start.o
{"+ 5 V standby", "V", &sysmon_pic, NULL, NULL,
100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C},
};
-static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
+static int sysmon_table_size = ARRAY_SIZE(sysmon_table);
static int conversion_done = 0;
static int ctlr_list[][2] = { };
#endif
-#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
-
static struct {
void (*init) (int index);
void (*halt) (int index);
ctlr_proc[CTLR_SCC].send = scc_send;
ctlr_proc[CTLR_SCC].recv = scc_recv;
- for (i = 0; i < CTRL_LIST_SIZE; i++) {
+ for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
res = -1;
}
{826, "MD_DBRAM1", 0x00000000, 0x00000000},
};
-static int spr_test_list_size =
- sizeof (spr_test_list) / sizeof (spr_test_list[0]);
+static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
int spr_post_test (int flags)
{
static int ctlr_list[][2] = { };
#endif
-#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
-
static struct {
void (*init) (int index);
void (*halt) (int index);
ctlr_proc[CTLR_SCC].putc = scc_putc;
ctlr_proc[CTLR_SCC].getc = scc_getc;
- for (i = 0; i < CTRL_LIST_SIZE; i++) {
+ for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
res = -1;
}
{0x3f3, "DBDR", 0x00000000, 0x00000000},
};
-static int spr_test_list_size =
- sizeof (spr_test_list) / sizeof (spr_test_list[0]);
+static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
int spr_post_test (int flags)
{
LIB = libpostdrivers.o
-COBJS-$(CONFIG_HAS_POST) += i2c.o memory.o rtc.o
+COBJS-$(CONFIG_HAS_POST) += flash.o i2c.o memory.o rtc.o
include $(TOPDIR)/post/rules.mk
--- /dev/null
+/*
+ * Parallel NOR Flash tests
+ *
+ * Copyright (c) 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <post.h>
+#include <flash.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_FLASH
+
+/*
+ * This code will walk over the declared sectors erasing them,
+ * then programming them, then verifying the written contents.
+ * Possible future work:
+ * - verify sectors before/after are not erased/written
+ * - verify partial writes (e.g. programming only middle of sector)
+ * - verify the contents of the erased sector
+ * - better seed pattern than 0x00..0xff
+ */
+
+#ifndef CONFIG_SYS_POST_FLASH_NUM
+# define CONFIG_SYS_POST_FLASH_NUM 0
+#endif
+#if CONFIG_SYS_POST_FLASH_START >= CONFIG_SYS_POST_FLASH_END
+# error "invalid flash block start/end"
+#endif
+
+extern flash_info_t flash_info[];
+
+static void *seed_src_data(void *ptr, ulong *old_len, ulong new_len)
+{
+ unsigned char *p;
+ ulong i;
+
+ p = ptr = realloc(ptr, new_len);
+ if (!ptr)
+ return ptr;
+
+ for (i = *old_len; i < new_len; ++i)
+ p[i] = i;
+
+ *old_len = new_len;
+
+ return ptr;
+}
+
+int flash_post_test(int flags)
+{
+ ulong len;
+ void *src;
+ int ret, n, n_start, n_end;
+ flash_info_t *info;
+
+ /* the output from the common flash layers needs help */
+ puts("\n");
+
+ len = 0;
+ src = NULL;
+ info = &flash_info[CONFIG_SYS_POST_FLASH_NUM];
+ n_start = CONFIG_SYS_POST_FLASH_START;
+ n_end = CONFIG_SYS_POST_FLASH_END;
+
+ for (n = n_start; n < n_end; ++n) {
+ ulong s_start, s_len, s_off;
+
+ s_start = info->start[n];
+ s_len = flash_sector_size(info, n);
+ s_off = s_start - info->start[0];
+
+ src = seed_src_data(src, &len, s_len);
+ if (!src) {
+ printf("malloc(%#lx) failed\n", s_len);
+ return 1;
+ }
+
+ printf("\tsector %i: %#lx +%#lx", n, s_start, s_len);
+
+ ret = flash_erase(info, n, n + 1);
+ if (ret) {
+ flash_perror(ret);
+ break;
+ }
+
+ ret = write_buff(info, src, s_start, s_len);
+ if (ret) {
+ flash_perror(ret);
+ break;
+ }
+
+ ret = memcmp(src, (void *)s_start, s_len);
+ if (ret) {
+ printf(" verify failed with %i\n", ret);
+ break;
+ }
+ }
+
+ free(src);
+
+ return ret;
+}
+
+#endif
static int memory_post_dataline(unsigned long long * pmem)
{
unsigned long long temp64 = 0;
- int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+ int num_patterns = ARRAY_SIZE(pattern);
int i;
unsigned int hi, lo, pathi, patlo;
int ret = 0;
return ret;
}
+/*
+ * !! this is only valid, if you have contiguous memory banks !!
+ */
__attribute__((weak))
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
bd_t *bd = gd->bd;
+
*vstart = CONFIG_SYS_SDRAM_BASE;
- *size = (bd->bi_memsize >= 256 << 20 ?
- 256 << 20 : bd->bi_memsize) - (1 << 20);
+ *size = (gd->ram_size >= 256 << 20 ?
+ 256 << 20 : gd->ram_size) - (1 << 20);
/* Limit area to be tested with the board info struct */
if ((*vstart) + (*size) > (ulong)bd)
unsigned long i;
for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
if (ret == 0)
- ret = memory_post_tests(i << 20, 0x800);
+ ret = memory_post_tests(vstart +
+ (i << 20), 0x800);
if (ret == 0)
- ret = memory_post_tests(
+ ret = memory_post_tests(vstart +
(i << 20) + 0xff800, 0x800);
}
}
0x80000000
},
};
-static unsigned int cpu_post_andi_size =
- sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s);
+static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table);
int cpu_post_test_andi (void)
{
0x04
},
};
-static unsigned int cpu_post_cmp_size =
- sizeof (cpu_post_cmp_table) / sizeof (struct cpu_post_cmp_s);
+static unsigned int cpu_post_cmp_size = ARRAY_SIZE(cpu_post_cmp_table);
int cpu_post_test_cmp (void)
{
0x04
},
};
-static unsigned int cpu_post_cmpi_size =
- sizeof (cpu_post_cmpi_table) / sizeof (struct cpu_post_cmpi_s);
+static unsigned int cpu_post_cmpi_size = ARRAY_SIZE(cpu_post_cmpi_table);
int cpu_post_test_cmpi (void)
{
0xaaaaaaaa,
0x55555555,
};
-static unsigned int cpu_post_cr_size1 =
- sizeof (cpu_post_cr_table1) / sizeof (ulong);
+static unsigned int cpu_post_cr_size1 = ARRAY_SIZE(cpu_post_cr_table1);
static struct cpu_post_cr_s2 {
ulong xer;
5
},
};
-static unsigned int cpu_post_cr_size2 =
- sizeof (cpu_post_cr_table2) / sizeof (struct cpu_post_cr_s2);
+static unsigned int cpu_post_cr_size2 = ARRAY_SIZE(cpu_post_cr_table2);
static struct cpu_post_cr_s3 {
ulong cr;
0x71234567
},
};
-static unsigned int cpu_post_cr_size3 =
- sizeof (cpu_post_cr_table3) / sizeof (struct cpu_post_cr_s3);
+static unsigned int cpu_post_cr_size3 = ARRAY_SIZE(cpu_post_cr_table3);
static struct cpu_post_cr_s4 {
ulong cmd;
0x0000ffff
},
};
-static unsigned int cpu_post_cr_size4 =
- sizeof (cpu_post_cr_table4) / sizeof (struct cpu_post_cr_s4);
+static unsigned int cpu_post_cr_size4 = ARRAY_SIZE(cpu_post_cr_table4);
int cpu_post_test_cr (void)
{
{
unsigned int i;
- for (i = 0; i < sizeof (expected) / sizeof (expected[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(expected); i++)
{
tstmul (expected[i].p1, expected[i].p2, expected[i].res);
tstmul (expected[i].p2, expected[i].p1, expected[i].res);
1
},
};
-static unsigned int cpu_post_load_size =
- sizeof (cpu_post_load_table) / sizeof (struct cpu_post_load_s);
+static unsigned int cpu_post_load_size = ARRAY_SIZE(cpu_post_load_table);
int cpu_post_test_load (void)
{
ASM_BLR,
};
- for (i = 0; i < sizeof(src) / sizeof(src[0]); i ++)
+ for (i = 0; i < ARRAY_SIZE(src); ++i)
{
src[i] = i;
dst[i] = 0;
0xffaaffff
},
};
-static unsigned int cpu_post_rlwimi_size =
- sizeof (cpu_post_rlwimi_table) / sizeof (struct cpu_post_rlwimi_s);
+static unsigned int cpu_post_rlwimi_size = ARRAY_SIZE(cpu_post_rlwimi_table);
int cpu_post_test_rlwimi (void)
{
0x0000ff00
},
};
-static unsigned int cpu_post_rlwinm_size =
- sizeof (cpu_post_rlwinm_table) / sizeof (struct cpu_post_rlwinm_s);
+static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);
int cpu_post_test_rlwinm (void)
{
0x0000ff00
},
};
-static unsigned int cpu_post_rlwnm_size =
- sizeof (cpu_post_rlwnm_table) / sizeof (struct cpu_post_rlwnm_s);
+static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table);
int cpu_post_test_rlwnm (void)
{
0xf0000000
},
};
-static unsigned int cpu_post_srawi_size =
- sizeof (cpu_post_srawi_table) / sizeof (struct cpu_post_srawi_s);
+static unsigned int cpu_post_srawi_size = ARRAY_SIZE(cpu_post_srawi_table);
int cpu_post_test_srawi (void)
{
0xff
},
};
-static unsigned int cpu_post_store_size =
- sizeof (cpu_post_store_table) / sizeof (struct cpu_post_store_s);
+static unsigned int cpu_post_store_size = ARRAY_SIZE(cpu_post_store_table);
int cpu_post_test_store (void)
{
0x40
},
};
-static unsigned int cpu_post_three_size =
- sizeof (cpu_post_three_table) / sizeof (struct cpu_post_three_s);
+static unsigned int cpu_post_three_size = ARRAY_SIZE(cpu_post_three_table);
int cpu_post_test_three (void)
{
0xffff8000
},
};
-static unsigned int cpu_post_threei_size =
- sizeof (cpu_post_threei_table) / sizeof (struct cpu_post_threei_s);
+static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
int cpu_post_test_threei (void)
{
0x1000
},
};
-static unsigned int cpu_post_threex_size =
- sizeof (cpu_post_threex_table) / sizeof (struct cpu_post_threex_s);
+static unsigned int cpu_post_threex_size = ARRAY_SIZE(cpu_post_threex_table);
int cpu_post_test_threex (void)
{
~5
},
};
-static unsigned int cpu_post_two_size =
- sizeof (cpu_post_two_table) / sizeof (struct cpu_post_two_s);
+static unsigned int cpu_post_two_size = ARRAY_SIZE(cpu_post_two_table);
int cpu_post_test_two (void)
{
12
},
};
-static unsigned int cpu_post_twox_size =
- sizeof (cpu_post_twox_table) / sizeof (struct cpu_post_twox_s);
+static unsigned int cpu_post_twox_size = ARRAY_SIZE(cpu_post_twox_table);
int cpu_post_test_twox (void)
{
#include <watchdog.h>
#include <post.h>
+#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO
+#include <asm/gpio.h>
+#endif
+
#ifdef CONFIG_LOGBUFFER
#include <logbuff.h>
#endif
*/
int __post_hotkeys_pressed(void)
{
+#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO
+ int ret;
+ unsigned gpio = CONFIG_SYS_POST_HOTKEYS_GPIO;
+
+ ret = gpio_request(gpio, "hotkeys");
+ if (ret) {
+ printf("POST: gpio hotkey request failed\n");
+ return 0;
+ }
+
+ gpio_direction_input(gpio);
+ ret = gpio_get_value(gpio);
+ gpio_free(gpio);
+
+ return ret;
+#endif
+
return 0; /* No hotkeys supported */
}
int post_hotkeys_pressed(void)
POST_CRITICAL };
char *var[] = { "post_poweron", "post_normal", "post_slowtest",
"post_critical" };
- int varnum = sizeof (var) / sizeof (var[0]);
+ int varnum = ARRAY_SIZE(var);
char list[128]; /* long enough for POST list */
char *name;
char *s;
gd->flags |= GD_FLG_POSTSTOP;
}
} else {
- if ((*test->test) (flags) != 0) {
- post_log ("FAILED\n");
- show_boot_progress (-32);
- show_post_progress(i, POST_AFTER, POST_FAILED);
- if (test_flags & POST_CRITICAL)
- gd->flags |= GD_FLG_POSTFAIL;
- if (test_flags & POST_STOP)
- gd->flags |= GD_FLG_POSTSTOP;
- }
- else
- post_log ("PASSED\n");
- show_post_progress(i, POST_AFTER, POST_PASSED);
+ if ((*test->test)(flags) != 0) {
+ post_log("FAILED\n");
+ show_boot_progress(-32);
+ show_post_progress(i, POST_AFTER, POST_FAILED);
+ if (test_flags & POST_CRITICAL)
+ gd->flags |= GD_FLG_POSTFAIL;
+ if (test_flags & POST_STOP)
+ gd->flags |= GD_FLG_POSTSTOP;
+ } else {
+ post_log("PASSED\n");
+ show_post_progress(i, POST_AFTER, POST_PASSED);
+ }
}
if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) {
extern int dsp_post_test (int flags);
extern int codec_post_test (int flags);
extern int ecc_post_test (int flags);
+extern int flash_post_test(int flags);
extern int dspic_init_post_test (int flags);
extern int dspic_post_test (int flags);
NULL,
NULL,
CONFIG_SYS_POST_COPROC
- }
+ },
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_FLASH
+ {
+ "Parallel NOR flash test",
+ "flash",
+ "This test verifies parallel flash operations.",
+ POST_RAM | POST_SLOWTEST | POST_MANUAL,
+ &flash_post_test,
+ NULL,
+ NULL,
+ CONFIG_SYS_POST_FLASH
+ },
#endif
};
-unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);
+unsigned int post_list_size = ARRAY_SIZE(post_list);
@rm -f $@
@touch $@
@for f in $(SRCS); do \
- g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
+ g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
$(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
done
@for f in $(HOSTSRCS); do \
- g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
+ g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
$(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
done
$(NOPEDOBJS): $(obj)%.o: %.c
$(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
+$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
+ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s
+ @echo Generating $@
+ $(TOPDIR)/tools/scripts/make-asm-offsets $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s $@
+
+$(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
+ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c
+ $(CC) -DDO_DEPS_ONLY \
+ $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c -c -S
#########################################################################
--- /dev/null
+u-boot-spl
+u-boot-spl.bin
+u-boot-spl.lds
+u-boot-spl.map
--- /dev/null
+#
+# (C) Copyright 2000-2011
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011
+# Daniel Schwierzeck, daniel.schwierzeck@googlemail.com.
+#
+# (C) Copyright 2011
+# Texas Instruments Incorporated - http://www.ti.com/
+# Aneesh V <aneesh@ti.com>
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Based on top-level Makefile.
+#
+
+CONFIG_SPL_BUILD := y
+export CONFIG_SPL_BUILD
+
+include $(TOPDIR)/config.mk
+
+# We want the final binaries in this directory
+obj := $(OBJTREE)/spl/
+
+HAVE_VENDOR_COMMON_LIB := $(shell [ -f $(SRCTREE)/board/$(VENDOR)/common/Makefile ] \
+ && echo y || echo n)
+
+START := $(CPUDIR)/start.o
+
+LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+LIBS-y += $(CPUDIR)/lib$(CPU).o
+ifdef SOC
+LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
+endif
+LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o
+LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
+
+LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
+LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o
+LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o
+LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o
+LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o
+LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o
+LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
+LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
+LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
+LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
+
+ifeq ($(SOC),omap3)
+LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
+endif
+ifeq ($(SOC),omap4)
+LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
+endif
+
+START := $(addprefix $(SPLTREE)/,$(START))
+LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))
+
+__START := $(subst $(obj),,$(START))
+__LIBS := $(subst $(obj),,$(LIBS))
+
+# Linker Script
+ifdef CONFIG_SPL_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(addprefix $(SRCTREE)/,$(subst ",,$(CONFIG_SPL_LDSCRIPT)))
+endif
+
+ifeq ($(wildcard $(LDSCRIPT)),)
+ LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-spl.lds
+endif
+ifeq ($(wildcard $(LDSCRIPT)),)
+ LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds
+endif
+ifeq ($(wildcard $(LDSCRIPT)),)
+$(error could not find linker script)
+endif
+
+# Special flags for CPP when processing the linker script.
+# Pass the version down so we can handle backwards compatibility
+# on the fly.
+LDPPFLAGS += \
+ -include $(TOPDIR)/include/u-boot/u-boot.lds.h \
+ -include $(OBJTREE)/include/config.h \
+ $(shell $(LD) --version | \
+ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+
+ALL-y += $(obj)u-boot-spl.bin
+
+all: $(ALL-y)
+
+$(obj)u-boot-spl.bin: $(obj)u-boot-spl
+ $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
+
+GEN_UBOOT = \
+ UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) | \
+ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__START) \
+ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
+ -Map u-boot-spl.map -o u-boot-spl
+
+$(obj)u-boot-spl: depend $(START) $(LIBS) $(obj)u-boot-spl.lds
+ $(GEN_UBOOT)
+
+$(START): depend
+ $(MAKE) -C $(SRCTREE)/$(CPUDIR) $@
+
+$(LIBS): depend
+ $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
+
+$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - < $< > $@
+
+depend: $(obj).depend
+.PHONY: depend
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
CONFIG_LCD_LOGO = y
CONFIG_CMD_LOADS = y
CONFIG_CMD_NET = y
-CONFIG_INCA_IP = y
+CONFIG_XWAY_SWAP_BYTES = y
CONFIG_NETCONSOLE = y
CONFIG_SHA1_CHECK_UB_IMG = y
endif
BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
-BIN_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes$(SFX)
+BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
BIN_FILES-y += mkimage$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
NOPED_OBJ_FILES-y += fit_image.o
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
-OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
+OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
NOPED_OBJ_FILES-y += kwbimage.o
NOPED_OBJ_FILES-y += imximage.o
NOPED_OBJ_FILES-y += mkimage.o
OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
NOPED_OBJ_FILES-y += os_support.o
OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
+NOPED_OBJ_FILES-y += ublimage.o
# Don't build by default
#ifeq ($(ARCH),ppc)
ifeq ($(VENDOR),syteco)
LOGO_BMP= logos/syteco.bmp
endif
+ifeq ($(VENDOR),intercontrol)
+LOGO_BMP= logos/intercontrol.bmp
+endif
# now $(obj) is defined
HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
-$(obj)inca-swap-bytes$(SFX): $(obj)inca-swap-bytes.o
+$(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
$(obj)mkimage.o \
$(obj)os_support.o \
$(obj)sha1.o \
+ $(obj)ublimage.o \
$(LIBFDT_OBJS)
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
# endif
#endif /* CONFIG_ENV_IS_IN_FLASH */
+#if defined(ENV_IS_EMBEDDED) && !defined(CONFIG_BUILD_ENVCRC)
+# define CONFIG_BUILD_ENVCRC 1
+#endif
+
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1)
#else
extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int);
-#ifdef ENV_IS_EMBEDDED
+#ifdef CONFIG_BUILD_ENVCRC
extern unsigned int env_size;
extern unsigned char environment;
-#endif /* ENV_IS_EMBEDDED */
+#endif /* CONFIG_BUILD_ENVCRC */
int main (int argc, char **argv)
{
-#ifdef ENV_IS_EMBEDDED
+#ifdef CONFIG_BUILD_ENVCRC
unsigned char pad = 0x00;
uint32_t crc;
unsigned char *envptr = &environment,
init_fit_image_type ();
/* Init Default image generation/list support */
init_default_image_type ();
+ /* Init Davinci UBL support */
+ init_ubl_image_type();
params.cmdname = *argv;
params.addr = params.ep = 0;
void init_imx_image_type (void);
void init_default_image_type (void);
void init_fit_image_type (void);
+void init_ubl_image_type(void);
#endif /* _MKIIMAGE_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "ublimage.h"
+
+/*
+ * Supported commands for configuration file
+ */
+static table_entry_t ublimage_cmds[] = {
+ {CMD_BOOT_MODE, "MODE", "UBL special modes", },
+ {CMD_ENTRY, "ENTRY", "Entry point addr for bootloader", },
+ {CMD_PAGE, "PAGES",
+ "number of pages (size of bootloader)", },
+ {CMD_ST_BLOCK, "START_BLOCK",
+ "block number where bootloader is present", },
+ {CMD_ST_PAGE, "START_PAGE",
+ "page number where bootloader is present", },
+ {CMD_LD_ADDR, "LD_ADDR",
+ "load addr", },
+ {-1, "", "", },
+};
+
+/*
+ * Supported Boot options for configuration file
+ * this is needed to set the correct flash offset
+ */
+static table_entry_t ublimage_bootops[] = {
+ {UBL_MAGIC_SAFE, "safe", "Safe boot mode", },
+ {-1, "", "Invalid", },
+};
+
+static struct ubl_header ublimage_header;
+
+static uint32_t get_cfg_value(char *token, char *name, int linenr)
+{
+ char *endptr;
+ uint32_t value;
+
+ errno = 0;
+ value = strtoul(token, &endptr, 16);
+ if (errno || (token == endptr)) {
+ fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
+ name, linenr, token);
+ exit(EXIT_FAILURE);
+ }
+ return value;
+}
+
+static void print_hdr(struct ubl_header *ubl_hdr)
+{
+ printf("Image Type : Davinci UBL Boot Image\n");
+ printf("UBL magic : %08x\n", ubl_hdr->magic);
+ printf("Entry Point: %08x\n", ubl_hdr->entry);
+ printf("nr of pages: %08x\n", ubl_hdr->pages);
+ printf("start block: %08x\n", ubl_hdr->block);
+ printf("start page : %08x\n", ubl_hdr->page);
+}
+
+static void parse_cfg_cmd(struct ubl_header *ublhdr, int32_t cmd, char *token,
+ char *name, int lineno, int fld, int dcd_len)
+{
+ static int cmd_ver_first = ~0;
+
+ switch (cmd) {
+ case CMD_BOOT_MODE:
+ ublhdr->magic = get_table_entry_id(ublimage_bootops,
+ "ublimage special boot mode", token);
+ if (ublhdr->magic == -1) {
+ fprintf(stderr, "Error: %s[%d] -Invalid boot mode"
+ "(%s)\n", name, lineno, token);
+ exit(EXIT_FAILURE);
+ }
+ ublhdr->magic += UBL_MAGIC_BASE;
+ if (unlikely(cmd_ver_first != 1))
+ cmd_ver_first = 0;
+ break;
+ case CMD_ENTRY:
+ ublhdr->entry = get_cfg_value(token, name, lineno);
+ break;
+ case CMD_PAGE:
+ ublhdr->pages = get_cfg_value(token, name, lineno);
+ break;
+ case CMD_ST_BLOCK:
+ ublhdr->block = get_cfg_value(token, name, lineno);
+ break;
+ case CMD_ST_PAGE:
+ ublhdr->page = get_cfg_value(token, name, lineno);
+ break;
+ case CMD_LD_ADDR:
+ ublhdr->pll_m = get_cfg_value(token, name, lineno);
+ break;
+ }
+}
+
+static void parse_cfg_fld(struct ubl_header *ublhdr, int32_t *cmd,
+ char *token, char *name, int lineno, int fld, int *dcd_len)
+{
+
+ switch (fld) {
+ case CFG_COMMAND:
+ *cmd = get_table_entry_id(ublimage_cmds,
+ "ublimage commands", token);
+ if (*cmd < 0) {
+ fprintf(stderr, "Error: %s[%d] - Invalid command"
+ "(%s)\n", name, lineno, token);
+ exit(EXIT_FAILURE);
+ }
+ break;
+ case CFG_REG_VALUE:
+ parse_cfg_cmd(ublhdr, *cmd, token, name, lineno, fld, *dcd_len);
+ break;
+ default:
+ break;
+ }
+}
+static uint32_t parse_cfg_file(struct ubl_header *ublhdr, char *name)
+{
+ FILE *fd = NULL;
+ char *line = NULL;
+ char *token, *saveptr1, *saveptr2;
+ int lineno = 0;
+ int i;
+ char *ptr = (char *)ublhdr;
+ int fld;
+ size_t len;
+ int dcd_len = 0;
+ int32_t cmd;
+ int ublhdrlen = sizeof(struct ubl_header);
+
+ fd = fopen(name, "r");
+ if (fd == 0) {
+ fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
+ exit(EXIT_FAILURE);
+ }
+
+ /* Fill header with 0xff */
+ for (i = 0; i < ublhdrlen; i++) {
+ *ptr = 0xff;
+ ptr++;
+ }
+
+ /*
+ * Very simple parsing, line starting with # are comments
+ * and are dropped
+ */
+ while ((getline(&line, &len, fd)) > 0) {
+ lineno++;
+
+ token = strtok_r(line, "\r\n", &saveptr1);
+ if (token == NULL)
+ continue;
+
+ /* Check inside the single line */
+ for (fld = CFG_COMMAND, cmd = CMD_INVALID,
+ line = token; ; line = NULL, fld++) {
+ token = strtok_r(line, " \t", &saveptr2);
+ if (token == NULL)
+ break;
+
+ /* Drop all text starting with '#' as comments */
+ if (token[0] == '#')
+ break;
+
+ parse_cfg_fld(ublhdr, &cmd, token, name,
+ lineno, fld, &dcd_len);
+ }
+ }
+ fclose(fd);
+
+ return dcd_len;
+}
+
+static int ublimage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_UBLIMAGE)
+ return EXIT_SUCCESS;
+ else
+ return EXIT_FAILURE;
+}
+
+static int ublimage_verify_header(unsigned char *ptr, int image_size,
+ struct mkimage_params *params)
+{
+ return 0;
+}
+
+static void ublimage_print_header(const void *ptr)
+{
+ struct ubl_header *ubl_hdr = (struct ubl_header *) ptr;
+
+ print_hdr(ubl_hdr);
+}
+
+static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct mkimage_params *params)
+{
+ struct ubl_header *ublhdr = (struct ubl_header *)ptr;
+
+ /* Parse configuration file */
+ parse_cfg_file(ublhdr, params->imagename);
+}
+
+int ublimage_check_params(struct mkimage_params *params)
+{
+ if (!params)
+ return CFG_INVALID;
+ if (!strlen(params->imagename)) {
+ fprintf(stderr, "Error: %s - Configuration file not"
+ "specified, it is needed for ublimage generation\n",
+ params->cmdname);
+ return CFG_INVALID;
+ }
+ /*
+ * Check parameters:
+ * XIP is not allowed and verify that incompatible
+ * parameters are not sent at the same time
+ * For example, if list is required a data image must not be provided
+ */
+ return (params->dflag && (params->fflag || params->lflag)) ||
+ (params->fflag && (params->dflag || params->lflag)) ||
+ (params->lflag && (params->dflag || params->fflag)) ||
+ (params->xflag) || !(strlen(params->imagename));
+}
+
+/*
+ * ublimage parameters
+ */
+static struct image_type_params ublimage_params = {
+ .name = "Davinci UBL boot support",
+ .header_size = sizeof(struct ubl_header),
+ .hdr = (void *)&ublimage_header,
+ .check_image_type = ublimage_check_image_types,
+ .verify_header = ublimage_verify_header,
+ .print_header = ublimage_print_header,
+ .set_header = ublimage_set_header,
+ .check_params = ublimage_check_params,
+};
+
+void init_ubl_image_type(void)
+{
+ mkimage_register(&ublimage_params);
+}
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Vased on:
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _UBLIMAGE_H_
+#define _UBLIMAGE_H_
+
+#include <config.h>
+
+#if !defined(CONFIG_SYS_UBL_BLOCK)
+#define CONFIG_SYS_UBL_BLOCK 512
+#endif
+
+enum ublimage_cmd {
+ CMD_INVALID,
+ CMD_BOOT_MODE,
+ CMD_ENTRY,
+ CMD_PAGE,
+ CMD_ST_BLOCK,
+ CMD_ST_PAGE,
+ CMD_LD_ADDR
+};
+
+enum ublimage_fld_types {
+ CFG_INVALID = -1,
+ CFG_COMMAND,
+ CFG_REG_VALUE
+};
+
+/*
+ * from sprufg5a.pdf Table 110
+ * Used by RBL when doing NAND boot
+ */
+#define UBL_MAGIC_BASE (0xA1ACED00)
+/* Safe boot mode */
+#define UBL_MAGIC_SAFE (0x00)
+/* DMA boot mode */
+#define UBL_MAGIC_DMA (0x11)
+/* I Cache boot mode */
+#define UBL_MAGIC_IC (0x22)
+/* Fast EMIF boot mode */
+#define UBL_MAGIC_FAST (0x33)
+/* DMA + ICache boot mode */
+#define UBL_MAGIC_DMA_IC (0x44)
+/* DMA + ICache + Fast EMIF boot mode */
+#define UBL_MAGIC_DMA_IC_FAST (0x55)
+
+/* Define max UBL image size */
+#define UBL_IMAGE_SIZE (0x00003800u)
+
+/* from sprufg5a.pdf Table 109 */
+struct ubl_header {
+ uint32_t magic; /* Magic Number, see UBL_* defines */
+ uint32_t entry; /* entry point address for bootloader */
+ uint32_t pages; /* number of pages (size of bootloader) */
+ uint32_t block; /*
+ * blocknumber where user bootloader is
+ * present
+ */
+ uint32_t page; /*
+ * page number where user bootloader is
+ * present.
+ */
+ uint32_t pll_m; /*
+ * PLL setting -Multiplier (only valid if
+ * Magic Number indicates PLL enable).
+ */
+ uint32_t pll_n; /*
+ * PLL setting -Divider (only valid if
+ * Magic Number indicates PLL enable).
+ */
+ uint32_t emif; /*
+ * fast EMIF setting (only valid if
+ * Magic Number indicates fast EMIF boot).
+ */
+ /* to fit in one nand block */
+ unsigned char res[CONFIG_SYS_UBL_BLOCK - 8 * 4];
+};
+
+#endif /* _UBLIMAGE_H_ */
projects / platform / kernel / u-boot.git / commitdiff
