M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html
+F: board/efi/efi-x86_app
+F: configs/efi-x86_app*
+F: doc/develop/uefi/u-boot_on_efi.rst
F: lib/efi/efi_app.c
+F: scripts/build-efi.sh
EFI PAYLOAD
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
ifeq ($(CONFIG_DEPRECATED),y)
$(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.")
endif
-ifeq ($(CONFIG_OF_EMBED),y)
+ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
@echo >&2 "be used for debugging purposes. Please use"
-Wl,-Map,u-boot.map; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
else
+# Note: Linking efi-x86_app64 causes a segfault in the linker at present
+# when using x86_64-linux-gnu-ld.bfd
+# For now, disable --whole-archive which makes things link, although not
+# correctly
quiet_cmd_u-boot__ ?= LD $@
cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-T u-boot.lds $(u-boot-init) \
- --whole-archive \
+ $(if $(CONFIG_EFI_APP_64BIT),,--whole-archive) \
$(u-boot-main) \
- --no-whole-archive \
+ $(if $(CONFIG_EFI_APP_64BIT),,--no-whole-archive) \
$(PLATFORM_LIBS) -Map u-boot.map; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
endif
U-Boot needs to get its device tree from somewhere. This can
be done using one of the three options below:
- CONFIG_OF_EMBED
- If this variable is defined, U-Boot will embed a device tree
- binary in its image. This device tree file should be in the
- board directory and called <soc>-<board>.dts. The binary file
- is then picked up in board_init_f() and made available through
- the global data structure as gd->fdt_blob.
-
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
binary. It will be called u-boot.dtb. Architecture-specific
CONFIG_SPL
Enable building of SPL globally.
- CONFIG_SPL_LDSCRIPT
- LDSCRIPT for linking the SPL binary.
-
CONFIG_SPL_MAX_FOOTPRINT
Maximum size in memory allocated to the SPL, BSS included.
When defined, the linker checks that the actual memory
CONFIG_SYS_SPL_MALLOC_SIZE
The size of the malloc pool used in SPL.
- CONFIG_SPL_OS_BOOT
- Enable booting directly to an OS from SPL.
- See also: doc/README.falcon
-
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
imply SPL_MMC if MMC
imply SPL_POWER
imply SPL_SERIAL
+ imply SYSRESET
+ imply SYSRESET_WATCHDOG
+ imply SYSRESET_WATCHDOG_AUTO
imply USB_GADGET
imply WDT
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif
* This function jumps to an image with argument. Normally an FDT or ATAGS
* image.
*/
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
#ifdef CONFIG_ARM64
void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
{
#include <common.h>
#include <asm/armv8/mmu.h>
-#ifdef CONFIG_EXYNOS7420
+#if CONFIG_IS_ENABLED(EXYNOS7420)
+
static struct mm_region exynos7420_mem_map[] = {
{
.virt = 0x10000000UL,
};
struct mm_region *mem_map = exynos7420_mem_map;
-#endif
-#ifdef CONFIG_EXYNOS7870
+#elif CONFIG_IS_ENABLED(EXYNOS7870)
+
static struct mm_region exynos7870_mem_map[] = {
{
.virt = 0x10000000UL,
};
struct mm_region *mem_map = exynos7870_mem_map;
-#endif
-#ifdef CONFIG_EXYNOS7880
+#elif CONFIG_IS_ENABLED(EXYNOS7880)
+
static struct mm_region exynos7880_mem_map[] = {
{
.virt = 0x10000000UL,
return regs.regs[0];
}
+ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ meson_init_shmem();
+
+ memcpy(shmem_input, buffer, size);
+
+ regs.regs[0] = FN_EFUSE_WRITE;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+
+ smc_call(®s);
+
+ if (regs.regs[0] == 0)
+ return -1;
+
+ return 0;
+}
+
#define SM_CHIP_ID_LENGTH 119
#define SM_CHIP_ID_OFFSET 4
#define SM_CHIP_ID_SIZE 12
return CMD_RET_SUCCESS;
}
+static int do_efuse_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address, offset, size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ offset = simple_strtoul(argv[1], NULL, 0);
+ size = simple_strtoul(argv[2], NULL, 0);
+
+ address = simple_strtoul(argv[3], NULL, 0);
+
+ ret = meson_sm_read_efuse(offset, (void *)address, size);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_efuse_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address, offset, size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ offset = simple_strtoul(argv[1], NULL, 0);
+ size = simple_strtoul(argv[2], NULL, 0);
+
+ address = simple_strtoul(argv[3], NULL, 0);
+
+ ret = meson_sm_write_efuse(offset, (void *)address, size);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
static struct cmd_tbl cmd_sm_sub[] = {
U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
+ U_BOOT_CMD_MKENT(efuseread, 4, 1, do_efuse_read, "", ""),
+ U_BOOT_CMD_MKENT(efusewrite, 4, 0, do_efuse_write, "", ""),
};
static int do_sm(struct cmd_tbl *cmdtp, int flag, int argc,
sm, 5, 0, do_sm,
"Secure Monitor Control",
"serial <address> - read chip unique id to memory address\n"
- "sm reboot_reason [name] - get reboot reason and store to to environment"
+ "sm reboot_reason [name] - get reboot reason and store to to environment\n"
+ "sm efuseread <offset> <size> <address> - read efuse to memory address\n"
+ "sm efusewrite <offset> <size> <address> - write into efuse from memory address"
);
}
#endif
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
while (1) { }
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
#define __raw_readl(a) __arch_getl(a)
#define __raw_readq(a) __arch_getq(a)
+/* adding for cadence_qspi_apb.c */
+#define memcpy_fromio(a, c, l) memcpy((a), (c), (l))
+#define memcpy_toio(c, a, l) memcpy((c), (a), (l))
+
#define dmb() mb()
#define __iormb() rmb()
#define __iowmb() wmb()
void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
+int sbi_get_impl_version(long *version);
int sbi_probe_extension(int ext);
void sbi_srst_reset(unsigned long type, unsigned long reason);
}
/**
+ * sbi_get_impl_version() - get SBI implementation version
+ *
+ * @version: pointer to receive version
+ * Return: 0 on success, -ENOTSUPP otherwise
+ */
+int sbi_get_impl_version(long *version)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION,
+ 0, 0, 0, 0, 0, 0);
+ if (ret.error)
+ return -ENOTSUPP;
+ if (version)
+ *version = ret.value;
+ return 0;
+}
+
+/**
* sbi_probe_extension() - Check if an SBI extension ID is supported or not.
* @extid: The extension ID to be probed.
*
obj-y += lpc.o
obj-y += lpss.o
obj-$(CONFIG_$(SPL_)INTEL_GENERIC_WIFI) += generic_wifi.o
-ifndef CONFIG_TARGET_EFI_APP
+ifndef CONFIG_EFI_APP
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64
obj-y += microcode.o
/DISCARD/ : { *(.u_boot_list_2_cmd_*) }
#endif
+#ifdef CONFIG_SYS_TEXT_BASE
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
+#endif
__text_start = .;
.text.start : { *(.text.start); }
#
obj-y += cpu.o interrupts.o setjmp.o
+
+ifndef CONFIG_EFI
+obj-y += misc.o
+endif
#include <cpu_func.h>
#include <debug_uart.h>
#include <init.h>
-
-/*
- * Global declaration of gd.
- *
- * As we write to it before relocation we have to make sure it is not put into
- * a .bss section which may overlap a .rela section. Initialization forces it
- * into a .data section which cannot overlap any .rela section.
- */
-struct global_data *global_data_ptr = (struct global_data *)~0;
-
-void arch_setup_gd(gd_t *new_gd)
-{
- global_data_ptr = new_gd;
-}
+#include <asm/global_data.h>
int cpu_has_64bit(void)
{
return 0;
}
-int misc_init_r(void)
-{
- return 0;
-}
-
-#ifndef CONFIG_SYS_COREBOOT
-int checkcpu(void)
-{
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- return 0;
-}
-#endif
-
int x86_cpu_reinit_f(void)
{
return 0;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Global declaration of gd.
+ *
+ * As we write to it before relocation we have to make sure it is not put into
+ * a .bss section which may overlap a .rela section. Initialization forces it
+ * into a .data section which cannot overlap any .rela section.
+ */
+struct global_data *global_data_ptr = (struct global_data *)~0;
+
+void arch_setup_gd(gd_t *new_gd)
+{
+ global_data_ptr = new_gd;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+#ifndef CONFIG_SYS_COREBOOT
+int checkcpu(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return 0;
+}
+#endif
compatible = "efi,reset";
u-boot,dm-pre-reloc;
};
+ efi-fb {
+ compatible = "efi-fb";
+ };
+
};
void *board_fdt_blob_setup(int *err)
{
*err = 0;
-#if CONFIG_IS_ENABLED(OF_BOARD)
+#if defined(CONFIG_OF_BOARD)
return (void *)(ulong)gd->arch.firmware_fdt_addr;
-#elif CONFIG_IS_ENABLED(OF_SEPARATE)
+#elif defined(CONFIG_OF_SEPARATE)
return (void *)CONFIG_SYS_FDT_BASE;
#else
*err = -EINVAL;
--- /dev/null
+JetHome JetHub
+M: Vyacheslav Bocharov <adeep@lexina.in>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/jethub-j100/
+F: configs/jethub_j100_defconfig
+F: doc/board/amlogic/jethub-j100.rst
+F: include/configs/jethub.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021 Vyacheslav Bocharov
+# Author: Vyacheslav Bocharov <adeep@lexina.in>
+
+obj-y := jethub-j100.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+#include <u-boot/crc.h>
+
+int misc_init_r(void)
+{
+ u8 mac_addr[ARP_HLEN];
+ char serial[SM_SERIAL_SIZE];
+ u32 sid;
+
+ if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) {
+ sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE);
+ /* Ensure the NIC specific bytes of the mac are not all 0 */
+ if ((sid & 0xffff) == 0)
+ sid |= 0x800000;
+
+ /* OUI registered MAC address */
+ mac_addr[0] = 0x10;
+ mac_addr[1] = 0x27;
+ mac_addr[2] = 0xBE;
+ mac_addr[3] = (sid >> 16) & 0xff;
+ mac_addr[4] = (sid >> 8) & 0xff;
+ mac_addr[5] = (sid >> 0) & 0xff;
+
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ }
+
+ return 0;
+}
L: u-boot-amlogic@groups.io
F: board/amlogic/jethub-j80/
F: configs/jethub_j80_defconfig
-F: configs/jethub_j100_defconfig
F: doc/board/amlogic/jethub-j80.rst
-F: doc/board/amlogic/jethub-j100.rst
+F: include/configs/jethub.h
prompt "Mainboard model"
optional
-config TARGET_EFI_APP
- bool "efi application"
+config TARGET_EFI_APP32
+ bool "32-bit efi application"
+ select EFI_APP
help
This target is used for running U-Boot on top of EFI. In
this case EFI does the early initialisation, and U-Boot
takes over once the RAM, video and CPU are fully running.
U-Boot is loaded as an application from EFI.
+config TARGET_EFI_APP64
+ bool "64-bit efi application"
+ select EFI_APP
+ select X86_64
+ help
+ This target is used for running U-Boot on top of EFI in 64-bit mode.
+ In this case EFI does the early initialisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as an application from EFI.
+
config TARGET_EFI_PAYLOAD
bool "efi payload"
help
-if TARGET_EFI_APP
+if EFI_APP
config SYS_BOARD
default "efi-x86_app"
config SYS_CONFIG_NAME
default "efi-x86_app"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ imply VIDEO_EFI
+
endif
-EFI-X86_APP BOARD
+EFI-X86_APP32 BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/efi/efi-x86_app/
F: include/configs/efi-x86_app.h
-F: configs/efi-x86_app_defconfig
+F: configs/efi-x86_app32_defconfig
+
+EFI-X86_APP64 BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/efi/efi-x86_app/
+F: include/configs/efi-x86_app.h
+F: configs/efi-x86_app64_defconfig
if TARGET_ESPRESSO7420
+config EXYNOS7420
+ def_bool y
+
config SYS_BOARD
default "espresso7420"
help
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- int i;
+ int i, impl_id;
long ret;
ret = sbi_get_spec_version();
if (ret >= 0)
- printf("SBI %ld.%ld\n", ret >> 24, ret & 0xffffff);
- ret = sbi_get_impl_id();
- if (ret >= 0) {
+ printf("SBI %ld.%ld", ret >> 24, ret & 0xffffff);
+ impl_id = sbi_get_impl_id();
+ if (impl_id >= 0) {
for (i = 0; i < ARRAY_SIZE(implementations); ++i) {
- if (ret == implementations[i].id) {
- printf("%s\n", implementations[i].name);
+ if (impl_id == implementations[i].id) {
+ long vers;
+
+ printf("\n%s ", implementations[i].name);
+ ret = sbi_get_impl_version(&vers);
+ if (ret < 0)
+ break;
+ if (impl_id == 1)
+ printf("%ld.%ld",
+ vers >> 16, vers & 0xffff);
+ else
+ printf("0x%lx", vers);
break;
}
}
if (i == ARRAY_SIZE(implementations))
- printf("Unknown implementation ID %ld\n", ret);
+ printf("Unknown implementation ID %ld", ret);
}
- printf("Extensions:\n");
+ printf("\nExtensions:\n");
for (i = 0; i < ARRAY_SIZE(extensions); ++i) {
ret = sbi_probe_extension(extensions[i].id);
if (ret > 0)
debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
#if defined(DEBUG)
- if (IS_ENABLED(CONFIG_CMD_BDI)
+ if (IS_ENABLED(CONFIG_CMD_BDI))
do_bdinfo(NULL, 0, 0, NULL);
#endif
* 0 to not start u-boot
* positive if u-boot should start
*/
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
__weak int spl_start_uboot(void)
{
puts(SPL_TPL_PROMPT
panic("** no mkimage signature but raw image not supported");
#endif
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
ulong start, end;
if (!bootz_setup((ulong)header, &start, &end)) {
spl_invoke_opensbi(&spl_image);
break;
#endif
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
case IH_OS_LINUX:
debug("Jumping to Linux\n");
#if defined(CONFIG_SYS_SPL_ARGS_ADDR)
return err < 0;
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
int spl_load_image_ext_os(struct spl_image_info *spl_image,
struct blk_desc *block_dev, int partition)
{
return (err <= 0);
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
int spl_load_image_fat_os(struct spl_image_info *spl_image,
struct blk_desc *block_dev, int partition)
{
}
#endif
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
struct mmc *mmc)
{
header = spl_get_load_buffer(0, sizeof(*header));
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
/*
* load parameter image
*/
spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
/*
* Load Linux from its location in NOR flash to its defined
return -ENODEV;
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() ||
spl_load_image_fat_os(spl_image, stor_dev,
CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
#include <asm/global_data.h>
#include <dm/ofnode.h>
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
/*
* Load the kernel, check for a valid header we can parse, and if found load
* the kernel and then device tree.
payload_offs);
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header))
#endif
{
info.leb_start = CONFIG_SPL_UBI_LEB_START;
info.peb_count = CONFIG_SPL_UBI_MAX_PEBS - info.peb_offset;
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_KERNEL_ID;
volumes[0].load_addr = (void *)CONFIG_SYS_LOAD_ADDR;
debug("boot mode - FAT\n");
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() ||
spl_load_image_fat_os(spl_image, stor_dev, partition))
#endif
static int spl_xip(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
spl_image->arg = (void *)CONFIG_SYS_FDT_BASE;
spl_image->name = "Linux";
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_MCFUART=y
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x80140000
CONFIG_USB_ETHER=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_AM335X_LCD=y
+CONFIG_BMP_16BPP=y
CONFIG_SPL_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_SPL_OF_LIBFDT=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_MCFUART=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_MCFUART=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_IPROC=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_BAUDRATE=19200
+CONFIG_MCFUART=y
CONFIG_FIT=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_CONTROLCENTERDC=y
CONFIG_ENV_SIZE=0x10000
CONFIG_BOARD_LATE_INIT=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_I2C=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_SPLASH_SCREEN=y
CONFIG_VIDEO_VCXK=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_SPLASH_SCREEN=y
CONFIG_VIDEO_VCXK=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_VENDOR_EFI=y
-CONFIG_TARGET_EFI_APP=y
+CONFIG_TARGET_EFI_APP32=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_DM_ETH is not set
# CONFIG_REGEX is not set
# CONFIG_GZIP is not set
CONFIG_EFI=y
--- /dev/null
+CONFIG_X86=y
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_ENV_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
+CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_VENDOR_EFI=y
+CONFIG_TARGET_EFI_APP64=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_PART=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_REGEX is not set
+# CONFIG_GZIP is not set
+CONFIG_EFI=y
+CONFIG_EFI_APP_64BIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_TARGET_MX6DL_MAMOJ=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_IMX_HAB=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x021f0000
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_PHANBELL=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_ARM=y
+CONFIG_SYS_BOARD="jethub-j100"
CONFIG_SYS_CONFIG_NAME="jethub"
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x1c000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_LEN=0x102000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SNOR=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_WDT_MTK=y
CONFIG_LZO=y
CONFIG_HEXDUMP=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_TFTP_TSIZE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PICO_IMX8MQ=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_BOOTARGS="console=ttySC0,115200"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum"
+CONFIG_DISPLAY_BOARDINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_MCFUART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_WATCHDOG=y
+++ /dev/null
----------------------------------------------------------------------
-Cleanup of AMCC eval boards (Walnut/Sycamore, Bubinga, Ebony, Ocotea)
----------------------------------------------------------------------
-
-Changes to all AMCC eval boards:
---------------------------------
-
-o Changed u-boot image size to 256 kBytes instead of 512 kBytes on most
- boards.
-
-o Use 115200 baud as default console baudrate.
-
-o Added config option to use redundant environment in flash. This is also
- the default setting. Option for environment in nvram is still available
- for backward compatibility.
-
-o Merged board specific flash drivers to common flash driver:
- board/amcc/common/flash.c
-
-
-Sycamore/Walnut (one port supporting both eval boards):
--------------------------------------------------------
-
-o Cleanup to allow easier "cloning" for different (custom) boards:
-
- o Moved EBC configuration from board specific asm-file "init.S"
- using defines in board configuration file. No board specific
- asm file needed anymore.
-
-
-August 01 2005, Stefan Roese <sr@denx.de>
+++ /dev/null
------------------------------
-NAND boot on PPC440 platforms
------------------------------
-
-This document describes the U-Boot NAND boot feature as it
-is implemented for the AMCC Sequoia (PPC440EPx) board.
-
-The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
-completely without NOR FLASH. This can be done by using the NAND
-boot feature of the 440 NAND flash controller (NDFC).
-
-Here a short description of the different boot stages:
-
-a) IPL (Initial Program Loader, integrated inside CPU)
-------------------------------------------------------
-Will load first 4k from NAND (SPL) into cache and execute it from there.
-
-b) SPL (Secondary Program Loader)
----------------------------------
-Will load special U-Boot version (NUB) from NAND and execute it. This SPL
-has to fit into 4kByte. It sets up the CPU and configures the SDRAM
-controller and the NAND controller so that the special U-Boot image can be
-loaded from NAND to SDRAM.
-This special image is build in the directory "nand_spl".
-
-c) NUB (NAND U-Boot)
---------------------
-This NAND U-Boot (NUB) is a special U-Boot version which can be started
-from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
-
-On 440EPx the SPL is copied to internal SRAM before the NAND controller
-is set up. While still running from cache, I experienced problems accessing
-the NAND controller.
-
-
-Example: Build and install NAND boot image for Sequoia (440EPx):
-
-a) Configure for sequoia with NAND boot support:
-# make sequoia_nand_config
-
-b) Build image(s)
-# make
-
-This will generate the SPL image in the "nand_spl" directory:
-nand_spl/u-boot-spl.bin
-Also another image is created spanning a whole NAND block (16kBytes):
-nand_spl/u-boot-spl-16k.bin
-The main NAND U-Boot image is generated in the toplevel directory:
-u-boot.bin
-A combined image of u-boot-spl-16k.bin and u-boot.bin is also created:
-u-boot-nand.bin
-
-This image should be programmed at offset 0 in the NAND flash:
-
-# tftp 100000 /tftpboot/sequoia/u-boot-nand.bin
-# nand erase 0 60000
-# nand write 100000 0 60000
-
-
-September 07 2006, Stefan Roese <sr@denx.de>
opt for using QEMU [1] and the OVMF [2], as detailed below.
To build U-Boot as an EFI application (32-bit EFI required), enable CONFIG_EFI
-and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app_defconfig) is set up
+and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app32_defconfig) is set up
for this. Just build U-Boot as normal, e.g.::
- make efi-x86_app_defconfig
+ make efi-x86_app32_defconfig
make
To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), enable
EFI (or vice versa). Also it will often fail to print an error message if
you get this wrong.
+You may find the script `scripts/build-efi.sh` helpful for building and testing
+U-Boot on UEFI on QEMU. It also includes links to UEFI binaries dating from
+2021.
+
+See `Example run`_ for an example run.
Inner workings
--------------
Everything else is built as a normal U-Boot, so is always 32-bit on x86 at
present.
+Example run
+-----------
+
+This shows running with serial enabled (see `include/configs/efi-x86_app.h`)::
+
+ $ scripts/build-efi.sh -wsPr
+ Packaging efi-x86_app32
+ Running qemu-system-i386
+
+ BdsDxe: failed to load Boot0001 "UEFI QEMU HARDDISK QM00005 " from PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0): Not Found
+ BdsDxe: loading Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1)
+ BdsDxe: starting Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1)
+
+ UEFI Interactive Shell v2.2
+ EDK II
+ UEFI v2.70 (EDK II, 0x00010000)
+ Mapping table
+ FS0: Alias(s):HD0a65535a1:;BLK1:
+ PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)/HD(1,GPT,0FFD5E61-3B0C-4326-8049-BDCDC910AF72,0x800,0xB000)
+ BLK0: Alias(s):
+ PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)
+
+ Press ESC in 5 seconds to skip startup.nsh or any other key to continue.
+ Shell> fs0:u-boot-app.efi
+ U-Boot EFI App (using allocated RAM address 47d4000) key=8d4, image=06a6f610
+ starting
+
+
+ U-Boot 2022.01-rc4 (Sep 19 2021 - 14:03:20 -0600)
+
+ CPU: x86, vendor Intel, device 663h
+ DRAM: 32 MiB
+ 0: efi_media_0 PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)
+ 1: <partition> PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)/HD(1,GPT,0FFD5E61-3B0C-4326-8049-BDCDC910AF72,0x800,0xB000)
+ Loading Environment from nowhere... OK
+ Model: EFI x86 Application
+ Hit any key to stop autoboot: 0
+
+ Partition Map for EFI device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000800 0x0000b7ff "boot"
+ attrs: 0x0000000000000000
+ type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+ guid: 0ffd5e61-3b0c-4326-8049-bdcdc910af72
+ 19 startup.nsh
+ 528384 u-boot-app.efi
+ 10181 NvVars
+
+ 3 file(s), 0 dir(s)
+
+ => QEMU: Terminated
+
+
Future work
-----------
This work could be extended in a number of ways:
- Add ARM support
-- Add 64-bit application support
+- Add 64-bit application support (in progress)
- Figure out how to solve the interrupt problem
-- Add more drivers to the application side (e.g. video, block devices, USB,
+- Add more drivers to the application side (e.g. block devices, USB,
environment access). This would mostly be an academic exercise as a strong
use case is not readily apparent, but it might be fun.
mode
speed mode to set.
- CONFIG_MMC_SPEED_MODE_SET should be enabled. The required speed mode is
- passed as the index from the following list.
-
- 0 - MMC_LEGACY
- 1 - MMC_HS
- 2 - SD_HS
- 3 - MMC_HS_52
- 4 - MMC_DDR_52
- 5 - UHS_SDR12
- 6 - UHS_SDR25
- 7 - UHS_SDR50
- 8 - UHS_DDR50
- 9 - UHS_SDR104
- 10 - MMC_HS_200
- 11 - MMC_HS_400
- 12 - MMC_HS_400_ES
+ CONFIG_MMC_SPEED_MODE_SET should be enabled. The requested speed mode is
+ passed as a decimal number according to the following table:
+
+ ========== ==========================
+ Speed mode Description
+ ========== ==========================
+ 0 MMC legacy
+ 1 MMC High Speed (26MHz)
+ 2 SD High Speed (50MHz)
+ 3 MMC High Speed (52MHz)
+ 4 MMC DDR52 (52MHz)
+ 5 UHS SDR12 (25MHz)
+ 6 UHS SDR25 (50MHz)
+ 7 UHS SDR50 (100MHz)
+ 8 UHS DDR50 (50MHz)
+ 9 UHS SDR104 (208MHz)
+ 10 HS200 (200MHz)
+ 11 HS400 (200MHz)
+ 12 HS400ES (200MHz)
+ ========== ==========================
A speed mode can be set only if it has already been enabled in the device tree
ret = dfu_flush(dfu, NULL, 0, i);
if (ret)
pr_err("DFU flush failed!");
+ puts("\n");
return ret;
}
config SYS_NAND_BLOCK_SIZE
hex "NAND chip eraseblock size"
depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
help
Number of data bytes in one eraseblock for the NAND chip on the
board. This is the multiple of NAND_PAGE_SIZE and the number of
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of data bytes in one page for the NAND chip on the
board, not including the OOB area.
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of bytes in the Out-Of-Band area for the NAND chip on
the board.
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
+ /* Program the data strobe */
+ advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
+
retry_count = 0;
retry:
#define PCIE_DEV_REV_OFF 0x0008
#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
+#define PCIE_EXP_ROM_BAR_OFF 0x0030
#define PCIE_CAPAB_OFF 0x0060
#define PCIE_CTRL_STAT_OFF 0x0068
#define PCIE_HEADER_LOG_4_OFF 0x0128
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
-#define PCIE_CONF_ADDR(dev, reg) \
- (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
- PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
+#define PCIE_CONF_ADDR(b, d, f, reg) \
+ (PCIE_CONF_BUS(b) | PCIE_CONF_DEV(d) | \
+ PCIE_CONF_FUNC(f) | PCIE_CONF_REG(reg) | \
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_MASK_OFF 0x1910
#define PCIE_MASK_ENABLE_INTS (0xf << 24)
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE BIT(0)
+#define PCIE_CTRL_RC_MODE BIT(1)
#define PCIE_STAT_OFF 0x1a04
#define PCIE_STAT_BUS (0xff << 8)
#define PCIE_STAT_DEV (0x1f << 16)
int devfn;
u32 lane_mask;
int first_busno;
- int local_dev;
+ int sec_busno;
char name[16];
unsigned int mem_target;
unsigned int mem_attr;
unsigned int io_target;
unsigned int io_attr;
+ u32 cfgcache[0x34 - 0x10];
};
/*
* and 64K of I/O space when registered.
*/
static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
-#define PCIE_MEM_SIZE (128 << 20)
static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
writel(stat, pcie->base + PCIE_STAT_OFF);
}
-static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
-{
- u32 stat;
-
- stat = readl(pcie->base + PCIE_STAT_OFF);
- return (stat & PCIE_STAT_BUS) >> 8;
-}
-
-static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
-{
- u32 stat;
-
- stat = readl(pcie->base + PCIE_STAT_OFF);
- return (stat & PCIE_STAT_DEV) >> 16;
-}
-
static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
{
return container_of(hose, struct mvebu_pcie, hose);
}
-static int mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, pci_dev_t bdf)
+static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
+ int busno, int dev, int func)
{
- /*
- * There are two devices visible on local bus:
- * * on slot configured by function mvebu_pcie_set_local_dev_nr()
- * (by default this register is set to 0) there is a
- * "Marvell Memory controller", which isn't useful in root complex
- * mode,
- * * on all other slots the real PCIe card connected to the PCIe slot.
- *
- * We therefore allow access only to the real PCIe card.
- */
- if (PCI_BUS(bdf) == pcie->first_busno &&
- PCI_DEV(bdf) != !pcie->local_dev)
- return 0;
+ /* On primary bus is only one PCI Bridge */
+ if (busno == pcie->first_busno && (dev != 0 || func != 0))
+ return false;
- return 1;
+ /* Access to other buses is possible when link is up */
+ if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie))
+ return false;
+
+ /* On secondary bus can be only one PCIe device */
+ if (busno == pcie->sec_busno && dev != 0)
+ return false;
+
+ return true;
}
static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- u32 data;
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
+ u32 addr, data;
debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- if (!mvebu_pcie_valid_addr(pcie, bdf)) {
+ if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
debug("- out of range\n");
*valuep = pci_get_ff(size);
return 0;
}
+ /*
+ * mvebu has different internal registers mapped into PCI config space
+ * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
+ * for this range and instead read content from driver virtual cfgcache
+ */
+ if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
+ offset, size, data);
+ *valuep = pci_conv_32_to_size(data, offset, size);
+ return 0;
+ } else if (busno == pcie->first_busno &&
+ (offset & ~3) == PCI_ROM_ADDRESS1) {
+ /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
+ offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
+ }
+
+ /*
+ * PCI bridge is device 0 at primary bus but mvebu has it mapped on
+ * secondary bus with device number 1.
+ */
+ if (busno == pcie->first_busno)
+ addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
+ else
+ addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+
/* write address */
- writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
/* read data */
- data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+ switch (size) {
+ case PCI_SIZE_8:
+ data = readb(pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
+ break;
+ case PCI_SIZE_16:
+ data = readw(pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
+ break;
+ case PCI_SIZE_32:
+ data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (busno == pcie->first_busno &&
+ (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
+ /*
+ * Change Header Type of PCI Bridge device to Type 1
+ * (0x01, used by PCI Bridges) because mvebu reports
+ * Type 0 (0x00, used by Upstream and Endpoint devices).
+ */
+ data = pci_conv_size_to_32(data, 0, offset, size);
+ data &= ~0x007f0000;
+ data |= PCI_HEADER_TYPE_BRIDGE << 16;
+ data = pci_conv_32_to_size(data, offset, size);
+ }
+
debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
- *valuep = pci_conv_32_to_size(data, offset, size);
+ *valuep = data;
return 0;
}
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- u32 data;
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
+ u32 addr, data;
debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
- if (!mvebu_pcie_valid_addr(pcie, bdf)) {
+ if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
debug("- out of range\n");
return 0;
}
+ /*
+ * mvebu has different internal registers mapped into PCI config space
+ * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
+ * for this range and instead write content to driver virtual cfgcache
+ */
+ if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
+ debug("Writing to cfgcache only\n");
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ data = pci_conv_size_to_32(data, value, offset, size);
+ /* mvebu PCI bridge does not have configurable bars */
+ if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
+ (offset & ~3) == PCI_BASE_ADDRESS_1)
+ data = 0x0;
+ pcie->cfgcache[(offset - 0x10) / 4] = data;
+ /* mvebu has its own way how to set PCI primary bus number */
+ if (offset == PCI_PRIMARY_BUS) {
+ pcie->first_busno = data & 0xff;
+ debug("Primary bus number was changed to %d\n",
+ pcie->first_busno);
+ }
+ /* mvebu has its own way how to set PCI secondary bus number */
+ if (offset == PCI_SECONDARY_BUS ||
+ (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
+ pcie->sec_busno = (data >> 8) & 0xff;
+ mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno);
+ debug("Secondary bus number was changed to %d\n",
+ pcie->sec_busno);
+ }
+ return 0;
+ } else if (busno == pcie->first_busno &&
+ (offset & ~3) == PCI_ROM_ADDRESS1) {
+ /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
+ offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
+ }
+
+ /*
+ * PCI bridge is device 0 at primary bus but mvebu has it mapped on
+ * secondary bus with device number 1.
+ */
+ if (busno == pcie->first_busno)
+ addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
+ else
+ addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+
/* write address */
- writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
/* write data */
- data = pci_conv_size_to_32(0, value, offset, size);
- writel(data, pcie->base + PCIE_CONF_DATA_OFF);
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
+ break;
+ case PCI_SIZE_16:
+ writew(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
+ break;
+ case PCI_SIZE_32:
+ writel(value, pcie->base + PCIE_CONF_DATA_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
return 0;
}
struct mvebu_pcie *pcie = dev_get_plat(dev);
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- int bus = dev_seq(dev);
u32 reg;
- debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
- pcie->port, pcie->lane, (u32)pcie->base);
-
- /* Read Id info and local bus/dev */
- debug("direct conf read %08x, local bus %d, local dev %d\n",
- readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
- mvebu_pcie_get_local_dev_nr(pcie));
+ /* Setup PCIe controller to Root Complex mode */
+ reg = readl(pcie->base + PCIE_CTRL_OFF);
+ reg |= PCIE_CTRL_RC_MODE;
+ writel(reg, pcie->base + PCIE_CTRL_OFF);
- pcie->first_busno = bus;
- pcie->local_dev = 1;
+ /*
+ * Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
+ * because default value is Memory controller (0x508000) which
+ * U-Boot cannot recognize as P2P Bridge.
+ *
+ * Note that this mvebu PCI Bridge does not have compliant Type 1
+ * Configuration Space. Header Type is reported as Type 0 and in
+ * range 0x10-0x34 it has aliased internal mvebu registers 0x10-0x34
+ * (e.g. PCIE_BAR_LO_OFF) and register 0x38 is reserved.
+ *
+ * Driver for this range redirects access to virtual cfgcache[] buffer
+ * which avoids changing internal mvebu registers. And changes Header
+ * Type response value to Type 1.
+ */
+ reg = readl(pcie->base + PCIE_DEV_REV_OFF);
+ reg &= ~0xffffff00;
+ reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+ writel(reg, pcie->base + PCIE_DEV_REV_OFF);
- mvebu_pcie_set_local_bus_nr(pcie, bus);
- mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev);
+ /*
+ * mvebu uses local bus number and local device number to determinate
+ * type of config request. Type 0 is used if target bus number equals
+ * local bus number and target device number differs from local device
+ * number. Type 1 is used if target bus number differs from local bus
+ * number. And when target bus number equals local bus number and
+ * target device equals local device number then request is routed to
+ * PCI Bridge which represent local PCIe Root Port.
+ *
+ * It means that PCI primary and secondary buses shares one bus number
+ * which is configured via local bus number. Determination if config
+ * request should go to primary or secondary bus is done based on local
+ * device number.
+ *
+ * PCIe is point-to-point bus, so at secondary bus is always exactly one
+ * device with number 0. So set local device number to 1, it would not
+ * conflict with any device on secondary bus number and will ensure that
+ * accessing secondary bus and all buses behind secondary would work
+ * automatically and correctly. Therefore this configuration of local
+ * device number implies that setting of local bus number configures
+ * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
+ * later configure it via config write requests to the correct value.
+ * mvebu_pcie_write_config() catches config write requests which tries
+ * to change primary/secondary bus number and correctly updates local
+ * bus number based on new secondary bus number.
+ *
+ * With this configuration is PCI Bridge available at secondary bus as
+ * device number 1. But it must be available at primary bus as device
+ * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
+ * functions rewrite address to the real one when accessing primary bus.
+ */
+ mvebu_pcie_set_local_bus_nr(pcie, 0);
+ mvebu_pcie_set_local_dev_nr(pcie, 1);
pcie->mem.start = (u32)mvebu_pcie_membase;
- pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
- mvebu_pcie_membase += PCIE_MEM_SIZE;
+ pcie->mem.end = pcie->mem.start + MBUS_PCI_MEM_SIZE - 1;
+ mvebu_pcie_membase += MBUS_PCI_MEM_SIZE;
if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
(phys_addr_t)pcie->mem.start,
- PCIE_MEM_SIZE)) {
+ MBUS_PCI_MEM_SIZE)) {
printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
- (u32)pcie->mem.start, PCIE_MEM_SIZE);
+ (u32)pcie->mem.start, MBUS_PCI_MEM_SIZE);
}
pcie->io.start = (u32)mvebu_pcie_iobase;
/* Setup windows and configure host bridge */
mvebu_pcie_setup_wins(pcie);
- /* Master + slave enable. */
- reg = readl(pcie->base + PCIE_CMD_OFF);
- reg |= PCI_COMMAND_MEMORY;
- reg |= PCI_COMMAND_IO;
- reg |= PCI_COMMAND_MASTER;
- reg |= BIT(10); /* disable interrupts */
- writel(reg, pcie->base + PCIE_CMD_OFF);
-
/* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start,
- pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
+ pcie->mem.start, MBUS_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
0, 0,
gd->ram_size,
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
+ /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
+ pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
+ PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
+ pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
+ PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
+
return 0;
}
if (ret < 0)
goto err;
- /* Check link and skip ports that have no link */
- if (!mvebu_pcie_link_up(pcie)) {
- debug("%s: %s - down\n", __func__, pcie->name);
- ret = -ENODEV;
- goto err;
- }
-
return 0;
err:
struct udevice *dev;
ofnode subnode;
- /* Lookup eth driver */
+ /* Lookup pci driver */
drv = lists_uclass_lookup(UCLASS_PCI);
if (!drv) {
puts("Cannot find PCI driver\n");
#include <asm/arch/pinmux.h>
#include "pinctrl-exynos.h"
-static struct pinctrl_ops exynos78x0_pinctrl_ops = {
+static const struct pinctrl_ops exynos78x0_pinctrl_ops = {
.set_state = exynos_pinctrl_set_state
};
/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
-static struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
+static const struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
EXYNOS_PIN_BANK(6, 0x000, "etc0"),
EXYNOS_PIN_BANK(3, 0x020, "etc1"),
EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
};
/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
-static struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
+static const struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
};
/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
-static struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
+static const struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
};
/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
-static struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
+static const struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
};
/* pin banks of exynos78x0 pin-controller 6 (TOP) */
-static struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
+static const struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
};
-struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
+const struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
{
/* pin-controller instance 0 Alive data */
.pin_banks = exynos78x0_pin_banks0,
tcnt = period_ns / rate_ns;
tcmp = duty_ns / rate_ns;
debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
+
+ /* Ensure that the comparitor will actually hit the target */
+ if (tcmp == tcnt)
+ tcmp = tcnt - 1;
offset = channel * 3;
writel(tcnt, ®s->tcntb0 + offset);
writel(tcmp, ®s->tcmpb0 + offset);
This enables the system reset driver support over TI System Control
Interface available on some new TI's SoCs.
-endif
-
config SYSRESET_SYSCON
bool "Enable support for mfd syscon reboot driver"
select REGMAP
help
Reboot support for generic watchdog reset.
+config SYSRESET_WATCHDOG_AUTO
+ bool "Automatically register first watchdog with sysreset"
+ depends on SYSRESET_WATCHDOG
+ help
+ If enabled, the first watchdog (as selected by the watchdog uclass)
+ will automatically be registered with the watchdog reboot driver.
+
config SYSRESET_RESETCTL
bool "Enable support for reset controller reboot driver"
select DM_RESET
help
Reboot support for NXP MPC83xx SoCs.
+endif
+
endmenu
.request = gpio_reboot_request,
};
-int gpio_reboot_probe(struct udevice *dev)
+static int gpio_reboot_probe(struct udevice *dev)
{
struct gpio_reboot_priv *priv = dev_get_priv(dev);
.request = resetctl_reboot_request,
};
-int resetctl_reboot_probe(struct udevice *dev)
+static int resetctl_reboot_probe(struct udevice *dev)
{
struct resetctl_reboot_priv *priv = dev_get_priv(dev);
.request = syscon_reboot_request,
};
-int syscon_reboot_probe(struct udevice *dev)
+static int syscon_reboot_probe(struct udevice *dev)
{
struct syscon_reboot_priv *priv = dev_get_priv(dev);
int err;
#include <common.h>
#include <dm.h>
+#include <dm/device-internal.h>
#include <errno.h>
+#include <malloc.h>
#include <sysreset.h>
#include <wdt.h>
-struct wdt_reboot_priv {
+struct wdt_reboot_plat {
struct udevice *wdt;
};
static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type)
{
- struct wdt_reboot_priv *priv = dev_get_priv(dev);
+ struct wdt_reboot_plat *plat = dev_get_plat(dev);
int ret;
- ret = wdt_expire_now(priv->wdt, 0);
+ ret = wdt_expire_now(plat->wdt, 0);
if (ret)
return ret;
.request = wdt_reboot_request,
};
-int wdt_reboot_probe(struct udevice *dev)
+static int wdt_reboot_of_to_plat(struct udevice *dev)
{
- struct wdt_reboot_priv *priv = dev_get_priv(dev);
+ struct wdt_reboot_plat *plat = dev_get_plat(dev);
int err;
err = uclass_get_device_by_phandle(UCLASS_WDT, dev,
- "wdt", &priv->wdt);
+ "wdt", &plat->wdt);
if (err) {
pr_err("unable to find wdt device\n");
return err;
.name = "wdt_reboot",
.id = UCLASS_SYSRESET,
.of_match = wdt_reboot_ids,
+ .of_to_plat = wdt_reboot_of_to_plat,
+ .plat_auto = sizeof(struct wdt_reboot_plat),
.ops = &wdt_reboot_ops,
- .priv_auto = sizeof(struct wdt_reboot_priv),
- .probe = wdt_reboot_probe,
};
+
+#if IS_ENABLED(CONFIG_SYSRESET_WATCHDOG_AUTO)
+int sysreset_register_wdt(struct udevice *dev)
+{
+ struct wdt_reboot_plat *plat = malloc(sizeof(*plat));
+ int ret;
+
+ if (!plat)
+ return -ENOMEM;
+
+ plat->wdt = dev;
+
+ ret = device_bind(dev, DM_DRIVER_GET(wdt_reboot),
+ dev->name, plat, ofnode_null(), NULL);
+ if (ret) {
+ free(plat);
+ return ret;
+ }
+
+ return 0;
+}
+#endif
memset(gpd, 0, QMU_GPD_RING_SIZE);
ring->dma = (dma_addr_t)gpd;
gpd_ring_init(ring, gpd);
+ mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd));
return 0;
}
config VIDEO_EFI
bool "Enable EFI framebuffer driver support"
- depends on EFI_STUB
+ depends on EFI_STUB || EFI_APP
help
Turn on this option to enable a framebuffeer driver when U-Boot is
loaded as a payload (see README.u-boot_on_efi) by an EFI BIOS where
*size = len;
}
+static int get_mode_info(struct vesa_mode_info *vesa)
+{
+ efi_guid_t efi_gop_guid = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID;
+ struct efi_boot_services *boot = efi_get_boot();
+ struct efi_gop_mode *mode;
+ struct efi_gop *gop;
+ int ret;
+
+ if (!boot)
+ return log_msg_ret("sys", -ENOSYS);
+ ret = boot->locate_protocol(&efi_gop_guid, NULL, (void **)&gop);
+ if (ret)
+ return log_msg_ret("prot", -ENOTSUPP);
+
+ mode = gop->mode;
+ vesa->phys_base_ptr = mode->fb_base;
+ vesa->x_resolution = mode->info->width;
+ vesa->y_resolution = mode->info->height;
+
+ return 0;
+}
+
static int save_vesa_mode(struct vesa_mode_info *vesa)
{
struct efi_entry_gopmode *mode;
int size;
int ret;
- ret = efi_info_get(EFIET_GOP_MODE, (void **)&mode, &size);
- if (ret == -ENOENT) {
- debug("efi graphics output protocol mode not found\n");
- return -ENXIO;
+ if (IS_ENABLED(CONFIG_EFI_APP)) {
+ ret = get_mode_info(vesa);
+ if (ret) {
+ printf("EFI graphics output protocol not found\n");
+ return -ENXIO;
+ }
+ } else {
+ ret = efi_info_get(EFIET_GOP_MODE, (void **)&mode, &size);
+ if (ret == -ENOENT) {
+ printf("EFI graphics output protocol mode not found\n");
+ return -ENXIO;
+ }
+ vesa->phys_base_ptr = mode->fb_base;
+ vesa->x_resolution = mode->info->width;
+ vesa->y_resolution = mode->info->height;
}
- vesa->phys_base_ptr = mode->fb_base;
- vesa->x_resolution = mode->info->width;
- vesa->y_resolution = mode->info->height;
-
if (mode->info->pixel_format < EFI_GOT_BITMASK) {
fbinfo = &efi_framebuffer_format_map[mode->info->pixel_format];
vesa->red_mask_size = fbinfo->red.size;
config WATCHDOG_AUTOSTART
bool "Automatically start watchdog timer"
depends on WDT
+ default n if ARCH_SUNXI
default y
help
Automatically start watchdog timer and start servicing it during
#include <errno.h>
#include <hang.h>
#include <log.h>
+#include <sysreset.h>
#include <time.h>
#include <wdt.h>
#include <asm/global_data.h>
priv = dev_get_uclass_priv(dev);
+ if (IS_ENABLED(CONFIG_SYSRESET_WATCHDOG_AUTO)) {
+ ret = sysreset_register_wdt(dev);
+ if (ret)
+ printf("WDT: Failed to register %s for sysreset\n",
+ dev->name);
+ }
+
if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) {
printf("WDT: Not starting %s\n", dev->name);
return;
+config YAFFS_DIRECT
+ bool
+
+config YAFFS_PROVIDE_DEFS
+ bool
+
+config YAFFSFS_PROVIDE_VALUES
+ bool
+
config YAFFS2
bool "YAFFS2 filesystem support"
+ select YAFFS_DIRECT
+ select YAFFS_PROVIDE_DEFS
+ select YAFFSFS_PROVIDE_VALUES
help
This provides access to YAFFS2 filesystems. Yet Another Flash
Filesystem 2 is a filesystem designed specifically for NAND flash.
yaffs_packedtags1.o yaffs_packedtags2.o yaffs_qsort.o \
yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \
yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o
-
-ccflags-y = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM \
- -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \
- -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG /* disable watchdog */
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
/* Configuration for environment
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
#endif
#endif
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
#endif
#endif
#endif /* ! CONFIG_SPL_BUILD */
-#define CONFIG_BMP_16BPP
#define SPLASH_SCREEN_NAND_PART "nand0,10"
#define SPLASH_SCREEN_BMP_FILE_SIZE 0x26000
#define SPLASH_SCREEN_BMP_LOAD_ADDR 0x82000000
#define CONFIG_HOSTNAME "AMCORE"
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
#define CONFIG_BOOTCOMMAND "bootm ffc20000"
"erase 0xfff00000 0xffffffff; " \
"cp.b 0x20000 0xfff00000 ${filesize}\0"
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_CLK 45000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
/* Register Base Addrs */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 325
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 375
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_REMAKE_ELF
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/* Networking */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#include "mx6_common.h"
-#undef CONFIG_DISPLAY_BOARDINFO
-
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
* in u-boot command interface
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (2)
#define CONFIG_SYS_UART2_ALT3_GPIO
#define CONFIG_SYS_NS16550_COM1 0xf040c000
-#define CONFIG_SYS_TEXT_BASE 0x10100000
#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
#include "bcmstb.h"
#define CONFIG_SYS_NS16550_COM1 0xf040ab00
-#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
#include "bcmstb.h"
#define CONFIG_SYS_BOOTM_LEN 0x01800000
/* Access eMMC Boot_1 and Boot_2 partitions */
-#define CONFIG_SUPPORT_EMMC_BOOT
/* enable 64-bit PCI resources */
#define CONFIG_SYS_PCI_64BIT 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-
-#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_OVERWRITE
#define __CONFIG_CI20_H__
/* Ingenic JZ4780 clock configuration. */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 1200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* Network */
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
"echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
"echo USB boot attempt ...; run usbbootscript; "
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#endif
/* Ethernet */
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_FEC_XCV_TYPE RGMII
#define IMX_FEC_BASE ENET_BASE_ADDR
* ---
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
/* ---
#define CONFIG_REMAKE_ELF
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#include "mx6_common.h"
-#undef CONFIG_DISPLAY_BOARDINFO
-
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000
-
/* Physical memory map */
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (256 * SZ_1M)
#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_I2C
-
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
-#define CONFIG_SPL_MMC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
* High Level Configuration Options (easy to change) *
*----------------------------------------------------------------------*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
#undef CONFIG_TPM_TIS_BASE_ADDRESS
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
- "stdout=vga,serial\0" \
- "stderr=vga,serial\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
+ "stdout=vidconsole\0" \
+ "stderr=vidconsole\0"
#endif
/* High Level Configuration Options */
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_EXYNOS7420 /* Exynos7 Family */
#define CONFIG_S5P
#include <asm/arch/cpu.h> /* get chip and board defs */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/*
* Ethernet
*/
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x1f
/*
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
#ifdef CONFIG_MX6UL
# define DRAM_OFFSET(x) 0x87##x
# define FDT_ADDR __stringify(DRAM_OFFSET(800000))
/* SPL */
#ifdef CONFIG_SPL
-# ifdef CONFIG_ENV_IS_IN_NAND
-# define CONFIG_SPL_NAND_SUPPORT
-# else
-# define CONFIG_SPL_MMC
-# endif
-
# include "imx6_spl.h"
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_BOOTCOMMAND "run boot${boot-mode}"
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-
-#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
/* FUSE command */
/* Boot M4 */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-
-#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x22050000
#define CONFIG_SPL_BSS_START_ADDR 0x22048000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_MALLOC_F_ADDR 0x22040000
-#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x95000000 /* SPL_RAM needed */
-
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
"else run netboot; fi"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#endif
#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#define SDRAM_CFG_BI 0x00000001
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_MMC
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
#define CONFIG_SPL_MAX_SIZE 0x1a000
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_I2C
-
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC
+
#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
#define CONFIG_SPL_STACK 0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#ifdef CONFIG_SPL
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_MII
#include "mx6_common.h"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
#include "imx6_spl.h"
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
#define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#ifndef __CONFIG_MT7620_H
#define __CONFIG_MT7620_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#ifndef __CONFIG_MT7628_H
#define __CONFIG_MT7628_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* MMC */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DRIVERS_MISC
-#endif
-
#endif
/* Network */
-#define CONFIG_FEC_MXC
-
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* Network */
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DRIVERS_MISC
-#endif
-
/*
* If we have defined the OPTEE ram size and not OPTEE it means that we were
* launched by OPTEE, because of that we shall skip all the low level
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
"fi; " \
"fi"
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
/* SPL */
#ifndef CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NO_CPU_SUPPORT
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
#define CONFIG_LBA48
#endif
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#if defined(CONFIG_MMC_OCTEONTX)
#define MMC_SUPPORTS_TUNING
/** EMMC specific defines */
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
#endif
/** EMMC specific defines */
#if defined(CONFIG_MMC_OCTEONTX)
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
#endif
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
/*
* Memory Info
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* USB Configs */
#define CONFIG_BOARD_SIZE_LIMIT 715776
/* Ethernet Configuration */
-#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
/* Network support */
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
#include <config_distro_bootcmd.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#include <config_distro_bootcmd.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 1
#define FEC_QUIRK_ENET_MAC
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
-#define CONFIG_SYS_HZ 1000
/* Environment options */
#define CONFIG_CPU_SH7751 1
#define __LITTLE_ENDIAN__ 1
-#define CONFIG_DISPLAY_BOARDINFO
-
/* SCIF */
#define CONFIG_CONS_SCIF1 1
/* Not used: not need IRQ/FIQ stuff */
#undef CONFIG_USE_IRQ
/* decrementer freq: 1ms ticks */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* System initialize options (board_init_f)
#endif
/* SPL */
-#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x301000
-#define CONFIG_SPL_STACK_R
-#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
#else
/*
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
"run mmcboot; " \
"fi; " \
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#endif
#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
"ramdisk_addr_r=0xC0438000\0" \
BOOTENV
-#define CONFIG_DISPLAY_BOARDINFO
-
/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_HOSTNAME "stmark2"
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
#define LDS_BOARD_TEXT \
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
-#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
#else
#define SDRAM_OFFSET(x) 0x4##x
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
-#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000
#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
#endif
#define __CONFIG_H
/* Timers for fasp(TIMCLK) */
-#define CONFIG_SYS_HZ 1000 /* 1 msec */
#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
/*
/* General configuration */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-/* No falcon support */
-#undef CONFIG_SPL_OS_BOOT
-
/* FPGA commands that we don't use */
/* Extras */
#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \
"if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \
"fi; fi; run $modeboot"
-#undef CONFIG_DISPLAY_BOARDINFO
#endif /* __CONFIG_TOPIC_MIAMI_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 280
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
func(MMC, mmc, 1) \
#ifndef CONFIG_TPL_BUILD
-
-#define CONFIG_SPL_OS_BOOT
-
/* Falcon Mode */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
"fi; " \
"fi"
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/*
* NS16550 Configuration
*/
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
-# define CONFIG_SPL_ENV_SUPPORT
# define CONFIG_SPL_HASH
# define CONFIG_ENV_MAX_ENTRIES 10
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (128 << 20)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
*
* @return pointer to EFI system table
*/
-
struct efi_system_table *efi_get_sys_table(void);
/**
+ * efi_get_boot() - Get access to the EFI boot services table
+ *
+ * @return pointer to EFI boot services table
+ */
+struct efi_boot_services *efi_get_boot(void);
+
+/**
* efi_get_ram_base() - Find the base of RAM
*
* This is used when U-Boot is built as an EFI application.
*/
void reset_cpu(void);
+/**
+ * sysreset_register_wdt() - register a watchdog for use with sysreset
+ *
+ * This registers the given watchdog timer to be used to reset the system.
+ *
+ * @dev: WDT device
+ * @return: 0 if OK, -errno if error
+ */
+int sysreset_register_wdt(struct udevice *dev);
+
#endif
*/
u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
+/**
+ * submit user specified data to the TPM and get response
+ *
+ * @dev TPM device
+ * @sendbuf: Buffer of the data to send
+ * @recvbuf: Buffer to save the response to
+ * @recv_size: Pointer to the size of the response buffer
+ *
+ * @return code of the operation
+ */
+u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
+ u8 *recvbuf, size_t *recv_size);
+
#endif /* __TPM_V2_H */
endchoice
-config EFI_RAM_SIZE
- hex "Amount of EFI RAM for U-Boot"
+choice
+ prompt "EFI app 32/64-bit selection"
depends on EFI_APP
- default 0x2000000
help
- Set the amount of EFI RAM which is claimed by U-Boot for its own
- use. U-Boot allocates this from EFI on start-up (along with a few
- other smaller amounts) and it can never be increased after that.
- It is used as the RAM size in with U-Boot.
+ EFI does not support mixing 32-bit and 64-bit modes. This is a
+ significant problem because it means that you must build a stub with
+ the correct type for EFI to load it correctly. If you are using
+ 32-bit EFI, select 32-bit here, else select 64-bit. Failure to do
+ this may produce no error message - it just won't start!
+
+config EFI_APP_32BIT
+ bool "Produce an app for running with 32-bit EFI"
+
+config EFI_APP_64BIT
+ bool "Produce an app for running with 64-bit EFI"
+
+endchoice
choice
- prompt "EFI 32/64-bit selection"
+ prompt "EFI stub 32/64-bit selection"
depends on EFI_STUB
help
EFI does not support mixing 32-bit and 64-bit modes. This is a
bool "Produce a stub for running with 64-bit EFI"
endchoice
+
+config EFI_RAM_SIZE
+ hex "Amount of EFI RAM for U-Boot"
+ depends on EFI_APP
+ default 0x10000000
+ help
+ Set the amount of EFI RAM which is claimed by U-Boot for its own
+ use. U-Boot allocates this from EFI on start-up (along with a few
+ other smaller amounts) and it can never be increased after that.
+ It is used as the RAM size in with U-Boot.
#include <efi_api.h>
/*
+ * Global declaration of gd.
+ *
+ * As we write to it before relocation we have to make sure it is not put into
+ * a .bss section which may overlap a .rela section. Initialization forces it
+ * into a .data section which cannot overlap any .rela section.
+ */
+struct global_data *global_data_ptr = (struct global_data *)~0;
+
+/*
* Unfortunately we cannot access any code outside what is built especially
* for the stub. lib/string.c is already being built for the U-Boot payload
* so it uses the wrong compiler flags. Add our own memset() here.
return global_priv->sys_table;
}
+struct efi_boot_services *efi_get_boot(void)
+{
+ return global_priv->boot;
+}
+
unsigned long efi_get_ram_base(void)
{
return global_priv->ram_base;
}
+int efi_info_get(enum efi_entry_t type, void **datap, int *sizep)
+{
+ return -ENOSYS;
+}
+
static efi_status_t setup_memory(struct efi_priv *priv)
{
struct efi_boot_services *boot = priv->boot;
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
depends on BLK
depends on DM_ETH || !NET
+ depends on !EFI_APP
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
select LIB_UUID
select PARTITION_UUIDS
}
#if defined(CONFIG_EFI_CAPSULE_AUTHENTICATE)
-int __weak efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
+int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
{
const void *fdt_blob = gd->fdt_blob;
const void *blob;
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/sha512.h>
-#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/generic.h>
#include <hexdump.h>
* Return: status code
*/
static efi_status_t EFIAPI
-efi_tcg2_submit_command(__maybe_unused struct efi_tcg2_protocol *this,
- u32 __maybe_unused input_param_block_size,
- u8 __maybe_unused *input_param_block,
- u32 __maybe_unused output_param_block_size,
- u8 __maybe_unused *output_param_block)
+efi_tcg2_submit_command(struct efi_tcg2_protocol *this,
+ u32 input_param_block_size,
+ u8 *input_param_block,
+ u32 output_param_block_size,
+ u8 *output_param_block)
{
- return EFI_UNSUPPORTED;
+ struct udevice *dev;
+ efi_status_t ret;
+ u32 rc;
+ size_t resp_buf_size = output_param_block_size;
+
+ EFI_ENTRY("%p, %u, %p, %u, %p", this, input_param_block_size,
+ input_param_block, output_param_block_size, output_param_block);
+
+ if (!this || !input_param_block || !input_param_block_size) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ ret = platform_get_tpm2_device(&dev);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ rc = tpm2_submit_command(dev, input_param_block,
+ output_param_block, &resp_buf_size);
+ if (rc) {
+ ret = (rc == -ENOSPC) ? EFI_OUT_OF_RESOURCES : EFI_DEVICE_ERROR;
+
+ goto out;
+ }
+
+out:
+ return EFI_EXIT(ret);
}
/**
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00000570, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000038, "\x00\x00\x00\x00\x40\x00\x00\x00"}, /* ....@... */ \
+ {0x00000040, "\x50\x45\x00\x00\xc2\x01\x02\x00"}, /* PE...... */ \
+ {0x00000050, "\x00\x00\x00\x00\x90\x00\x0e\x03"}, /* ........ */ \
+ {0x00000058, "\x0b\x01\x02\x14\x38\x04\x00\x00"}, /* ....8... */ \
+ {0x00000068, "\x38\x01\x00\x00\x38\x01\x00\x00"}, /* 8...8... */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000090, "\x70\x05\x00\x00\x38\x01\x00\x00"}, /* p...8... */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000b0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x000000e8, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000108, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000110, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000118, "\x38\x04\x00\x00\x38\x01\x00\x00"}, /* 8...8... */ \
+ {0x00000120, "\x38\x04\x00\x00\x38\x01\x00\x00"}, /* 8...8... */ \
+ {0x00000130, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000138, "\x07\x40\x2d\xe9\x24\x10\x8f\xe2"}, /* .@-.$... */ \
+ {0x00000140, "\x00\x00\x91\xe5\x01\x10\x80\xe0"}, /* ........ */ \
+ {0x00000148, "\x15\x0e\x4f\xe2\x5a\x00\x00\xeb"}, /* ..O.Z... */ \
+ {0x00000150, "\x00\x00\x30\xe3\x01\x00\x00\x1a"}, /* ..0..... */ \
+ {0x00000158, "\x03\x00\x9d\xe8\x2e\x00\x00\xeb"}, /* ........ */ \
+ {0x00000160, "\x0c\xd0\x8d\xe2\x04\xf0\x9d\xe4"}, /* ........ */ \
+ {0x00000168, "\xa8\x03\x00\x00\x02\x30\xa0\xe3"}, /* .....0.. */ \
+ {0x00000170, "\x30\x40\x2d\xe9\x14\xd0\x4d\xe2"}, /* 0@-...M. */ \
+ {0x00000178, "\x3c\x20\x91\xe5\x2c\x50\x91\xe5"}, /* < ..,P.. */ \
+ {0x00000180, "\x04\x30\x8d\xe5\x00\x30\xa0\xe3"}, /* .0...0.. */ \
+ {0x00000188, "\x7c\x10\x9f\xe5\x00\x30\x8d\xe5"}, /* |....0.. */ \
+ {0x00000190, "\x98\x40\x92\xe5\x01\x10\x8f\xe0"}, /* .@...... */ \
+ {0x00000198, "\x0c\x20\x8d\xe2\x34\xff\x2f\xe1"}, /* . ..4./. */ \
+ {0x000001a0, "\x00\x40\x50\xe2\x07\x00\x00\x0a"}, /* .@P..... */ \
+ {0x000001a8, "\x60\x10\x9f\xe5\x05\x00\xa0\xe1"}, /* `....... */ \
+ {0x000001b0, "\x04\x30\x95\xe5\x01\x10\x8f\xe0"}, /* .0...... */ \
+ {0x000001b8, "\x33\xff\x2f\xe1\x04\x00\xa0\xe1"}, /* 3./..... */ \
+ {0x000001c0, "\x14\xd0\x8d\xe2\x30\x80\xbd\xe8"}, /* ....0... */ \
+ {0x000001c8, "\x0c\x10\x9d\xe5\x40\x20\x9f\xe5"}, /* ....@ .. */ \
+ {0x000001d0, "\x20\x30\x91\xe5\x02\x20\x8f\xe0"}, /* 0... .. */ \
+ {0x000001d8, "\x02\x00\x53\xe1\x03\x00\x00\x8a"}, /* ..S..... */ \
+ {0x000001e0, "\x28\x10\x91\xe5\x01\x30\x83\xe0"}, /* (....0.. */ \
+ {0x000001e8, "\x02\x00\x53\xe1\xf2\xff\xff\x8a"}, /* ..S..... */ \
+ {0x000001f0, "\x20\x10\x9f\xe5\x05\x00\xa0\xe1"}, /* ....... */ \
+ {0x000001f8, "\x04\x30\x95\xe5\x01\x10\x8f\xe0"}, /* .0...... */ \
+ {0x00000200, "\x33\xff\x2f\xe1\x3a\x41\xa0\xe3"}, /* 3./.:A.. */ \
+ {0x00000208, "\xeb\xff\xff\xea\xac\x03\x00\x00"}, /* ........ */ \
+ {0x00000210, "\x34\x02\x00\x00\x90\xff\xff\xff"}, /* 4....... */ \
+ {0x00000218, "\x36\x02\x00\x00\xf0\x40\x2d\xe9"}, /* 6....@-. */ \
+ {0x00000220, "\x14\xd0\x4d\xe2\x0d\x70\xa0\xe1"}, /* ..M..p.. */ \
+ {0x00000228, "\x00\x50\xa0\xe1\x01\x40\xa0\xe1"}, /* .P...@.. */ \
+ {0x00000230, "\x2c\x60\x91\xe5\x74\x10\x9f\xe5"}, /* ,`..t... */ \
+ {0x00000238, "\x10\x20\xa0\xe3\x01\x10\x8f\xe0"}, /* . ...... */ \
+ {0x00000240, "\x07\x00\xa0\xe1\x60\x00\x00\xeb"}, /* ....`... */ \
+ {0x00000248, "\x64\x10\x9f\xe5\x04\x30\x96\xe5"}, /* d....0.. */ \
+ {0x00000250, "\x01\x10\x8f\xe0\x06\x00\xa0\xe1"}, /* ........ */ \
+ {0x00000258, "\x33\xff\x2f\xe1\x04\x10\xa0\xe1"}, /* 3./..... */ \
+ {0x00000260, "\x05\x00\xa0\xe1\xc0\xff\xff\xeb"}, /* ........ */ \
+ {0x00000268, "\x00\x00\x50\xe3\x0e\x11\xa0\x03"}, /* ..P..... */ \
+ {0x00000270, "\x05\x00\x00\x0a\x3c\x10\x9f\xe5"}, /* ....<... */ \
+ {0x00000278, "\x06\x00\xa0\xe1\x01\x10\x8f\xe0"}, /* ........ */ \
+ {0x00000280, "\x04\x30\x96\xe5\x33\xff\x2f\xe1"}, /* .0..3./. */ \
+ {0x00000288, "\x3a\x11\xa0\xe3\x3c\x30\x94\xe5"}, /* :...<0.. */ \
+ {0x00000290, "\x10\x20\xa0\xe3\x78\x40\x93\xe5"}, /* . ..x@.. */ \
+ {0x00000298, "\x05\x00\xa0\xe1\x07\x30\xa0\xe1"}, /* .....0.. */ \
+ {0x000002a0, "\x34\xff\x2f\xe1\x00\x00\xa0\xe3"}, /* 4./..... */ \
+ {0x000002a8, "\x14\xd0\x8d\xe2\xf0\x80\xbd\xe8"}, /* ........ */ \
+ {0x000002b0, "\xb8\x02\x00\x00\x2a\x02\x00\x00"}, /* ........ */ \
+ {0x000002b8, "\x3a\x02\x00\x00\x00\x30\xa0\xe3"}, /* :....0.. */ \
+ {0x000002c0, "\x03\x20\xa0\xe1\x03\xc0\xa0\xe1"}, /* . ...... */ \
+ {0x000002c8, "\x04\xe0\x2d\xe5\x00\xe0\x91\xe5"}, /* ..-..... */ \
+ {0x000002d0, "\x00\x00\x5e\xe3\x03\x00\x00\x1a"}, /* ..^..... */ \
+ {0x000002d8, "\x02\x10\x93\xe1\x0c\x00\x00\x1a"}, /* ........ */ \
+ {0x000002e0, "\x00\x00\xa0\xe3\x04\xf0\x9d\xe4"}, /* ........ */ \
+ {0x000002e8, "\x12\x00\x5e\xe3\x04\xc0\x91\x05"}, /* ..^..... */ \
+ {0x000002f0, "\x05\x00\x00\x0a\x13\x00\x5e\xe3"}, /* ......^. */ \
+ {0x000002f8, "\x04\x20\x91\x05\x02\x00\x00\x0a"}, /* . ...... */ \
+ {0x00000300, "\x11\x00\x5e\xe3\x04\x30\x91\x05"}, /* ..^..0.. */ \
+ {0x00000308, "\x03\x30\x80\x00\x08\x10\x81\xe2"}, /* .0...... */ \
+ {0x00000310, "\xed\xff\xff\xea\x00\x00\x52\xe3"}, /* ......R. */ \
+ {0x00000318, "\x00\x00\x53\x13\x09\x00\x00\x1a"}, /* ..S..... */ \
+ {0x00000320, "\x06\x01\xa0\xe3\x04\xf0\x9d\xe4"}, /* ........ */ \
+ {0x00000328, "\x04\x10\xd3\xe5\x02\xc0\x4c\xe0"}, /* ......L. */ \
+ {0x00000330, "\x17\x00\x51\xe3\x00\xe0\x93\x05"}, /* ..Q..... */ \
+ {0x00000338, "\x02\x30\x83\xe0\x0e\x10\x90\x07"}, /* .0...... */ \
+ {0x00000340, "\x00\x10\x81\x00\x0e\x10\x80\x07"}, /* ........ */ \
+ {0x00000348, "\x00\x00\x5c\xe3\xf5\xff\xff\xca"}, /* ..\..... */ \
+ {0x00000350, "\xe2\xff\xff\xea\x01\x10\x41\xe2"}, /* ......A. */ \
+ {0x00000358, "\x02\x20\x80\xe0\x02\x00\x50\xe1"}, /* . ....P. */ \
+ {0x00000360, "\x01\x00\x00\x1a\x00\x00\xa0\xe3"}, /* ........ */ \
+ {0x00000368, "\x1e\xff\x2f\xe1\x00\x30\xd0\xe5"}, /* ../..0.. */ \
+ {0x00000370, "\x01\xc0\xf1\xe5\x0c\x00\x53\xe1"}, /* ......S. */ \
+ {0x00000378, "\x01\x00\x00\x0a\x0c\x00\x43\xe0"}, /* ......C. */ \
+ {0x00000380, "\x1e\xff\x2f\xe1\x01\x00\x80\xe2"}, /* ../..... */ \
+ {0x00000388, "\xf3\xff\xff\xea\x01\x00\x50\xe1"}, /* ......P. */ \
+ {0x00000390, "\x02\x30\x81\xe0\x01\x20\x40\x92"}, /* .0... @. */ \
+ {0x00000398, "\x08\x00\x00\x9a\x00\x10\xa0\xe1"}, /* ........ */ \
+ {0x000003a0, "\x02\x20\x80\xe0\x01\x00\x52\xe1"}, /* . ....R. */ \
+ {0x000003a8, "\x1e\xff\x2f\x01\x01\xc0\x73\xe5"}, /* ../...s. */ \
+ {0x000003b0, "\x01\xc0\x62\xe5\xfa\xff\xff\xea"}, /* ..b..... */ \
+ {0x000003b8, "\x01\xc0\xd1\xe4\x01\xc0\xe2\xe5"}, /* ........ */ \
+ {0x000003c0, "\x03\x00\x51\xe1\xfb\xff\xff\x1a"}, /* ..Q..... */ \
+ {0x000003c8, "\x1e\xff\x2f\xe1\xee\xff\xff\xea"}, /* ../..... */ \
+ {0x000003d0, "\x00\x30\xa0\xe1\x02\x20\x80\xe0"}, /* .0... .. */ \
+ {0x000003d8, "\x02\x00\x53\xe1\x1e\xff\x2f\x01"}, /* ..S.../. */ \
+ {0x000003e0, "\x01\x10\xc3\xe4\xfb\xff\xff\xea"}, /* ........ */ \
+ {0x000003e8, "\x1e\xff\x2f\xe1\x1e\xff\x2f\xe1"}, /* ../.../. */ \
+ {0x000003f0, "\x43\x00\x6f\x00\x75\x00\x6c\x00"}, /* C.o.u.l. */ \
+ {0x000003f8, "\x64\x00\x20\x00\x6e\x00\x6f\x00"}, /* d. .n.o. */ \
+ {0x00000400, "\x74\x00\x20\x00\x6f\x00\x70\x00"}, /* t. .o.p. */ \
+ {0x00000408, "\x65\x00\x6e\x00\x20\x00\x6c\x00"}, /* e.n. .l. */ \
+ {0x00000410, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x00000418, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x00000420, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x00000428, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x00000430, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x00000438, "\x00\x00\x49\x00\x6e\x00\x63\x00"}, /* ..I.n.c. */ \
+ {0x00000440, "\x6f\x00\x72\x00\x72\x00\x65\x00"}, /* o.r.r.e. */ \
+ {0x00000448, "\x63\x00\x74\x00\x20\x00\x69\x00"}, /* c.t. .i. */ \
+ {0x00000450, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000458, "\x5f\x00\x62\x00\x61\x00\x73\x00"}, /* _.b.a.s. */ \
+ {0x00000460, "\x65\x00\x20\x00\x6f\x00\x72\x00"}, /* e. .o.r. */ \
+ {0x00000468, "\x20\x00\x69\x00\x6d\x00\x61\x00"}, /* .i.m.a. */ \
+ {0x00000470, "\x67\x00\x65\x00\x5f\x00\x73\x00"}, /* g.e._.s. */ \
+ {0x00000478, "\x69\x00\x7a\x00\x65\x00\x0a\x00"}, /* i.z.e... */ \
+ {0x00000480, "\x00\x00\x45\x00\x46\x00\x49\x00"}, /* ..E.F.I. */ \
+ {0x00000488, "\x20\x00\x61\x00\x70\x00\x70\x00"}, /* .a.p.p. */ \
+ {0x00000490, "\x6c\x00\x69\x00\x63\x00\x61\x00"}, /* l.i.c.a. */ \
+ {0x00000498, "\x74\x00\x69\x00\x6f\x00\x6e\x00"}, /* t.i.o.n. */ \
+ {0x000004a0, "\x20\x00\x63\x00\x61\x00\x6c\x00"}, /* .c.a.l. */ \
+ {0x000004a8, "\x6c\x00\x69\x00\x6e\x00\x67\x00"}, /* l.i.n.g. */ \
+ {0x000004b0, "\x20\x00\x45\x00\x78\x00\x69\x00"}, /* .E.x.i. */ \
+ {0x000004b8, "\x74\x00\x0a\x00\x00\x00\x4c\x00"}, /* t.....L. */ \
+ {0x000004c0, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x000004c8, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x000004d0, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x000004d8, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x000004e0, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x000004e8, "\x20\x00\x6d\x00\x69\x00\x73\x00"}, /* .m.i.s. */ \
+ {0x000004f0, "\x73\x00\x69\x00\x6e\x00\x67\x00"}, /* s.i.n.g. */ \
+ {0x000004f8, "\x0a\x00\x00\x00\x53\x00\x55\x00"}, /* ....S.U. */ \
+ {0x00000500, "\x43\x00\x43\x00\x45\x00\x53\x00"}, /* C.C.E.S. */ \
+ {0x00000508, "\x53\x00\x00\x00\x00\x00\x00\x00"}, /* S....... */ \
+ {0x00000510, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000548, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000550, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000558, "\x10\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x000011e0, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000038, "\x41\x52\x4d\x64\x40\x00\x00\x00"}, /* ARMd@... */ \
+ {0x00000040, "\x50\x45\x00\x00\x64\xaa\x02\x00"}, /* PE..d... */ \
+ {0x00000050, "\x00\x00\x00\x00\xa0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000058, "\x0b\x02\x02\x14\xd8\x04\x00\x00"}, /* ........ */ \
+ {0x00000068, "\x48\x01\x00\x00\x48\x01\x00\x00"}, /* H...H... */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000090, "\x20\x06\x00\x00\x48\x01\x00\x00"}, /* ...H... */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000c0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x000000f8, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000118, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000120, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000128, "\xd8\x04\x00\x00\x48\x01\x00\x00"}, /* ....H... */ \
+ {0x00000130, "\xd8\x04\x00\x00\x48\x01\x00\x00"}, /* ....H... */ \
+ {0x00000140, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000148, "\xfd\x7b\xbe\xa9\xfd\x03\x00\x91"}, /* .{...... */ \
+ {0x00000150, "\xe0\x07\x01\xa9\x60\xf5\xff\x10"}, /* ....`... */ \
+ {0x00000158, "\x01\x00\x00\x90\x21\xc0\x14\x91"}, /* ....!... */ \
+ {0x00000160, "\x5a\x00\x00\x94\x60\x00\x00\xb5"}, /* Z...`... */ \
+ {0x00000168, "\xe0\x07\x41\xa9\x2d\x00\x00\x94"}, /* ..A.-... */ \
+ {0x00000170, "\xfd\x7b\xc2\xa8\xc0\x03\x5f\xd6"}, /* .{...._. */ \
+ {0x00000178, "\xfd\x7b\xbd\xa9\x45\x00\x80\x52"}, /* .{..E..R */ \
+ {0x00000180, "\x04\x00\x80\xd2\x03\x00\x80\xd2"}, /* ........ */ \
+ {0x00000188, "\xfd\x03\x00\x91\xf3\x53\x01\xa9"}, /* .....S.. */ \
+ {0x00000190, "\xa2\xa3\x00\x91\x33\x20\x40\xf9"}, /* ....3 @. */ \
+ {0x00000198, "\x21\x30\x40\xf9\x26\x8c\x40\xf9"}, /* !0@.&.@. */ \
+ {0x000001a0, "\x01\x00\x00\x90\x21\xc0\x17\x91"}, /* ....!... */ \
+ {0x000001a8, "\xc0\x00\x3f\xd6\xf4\x03\x00\xaa"}, /* ..?..... */ \
+ {0x000001b0, "\x40\x01\x00\xb4\x62\x06\x40\xf9"}, /* @...b.@. */ \
+ {0x000001b8, "\x01\x00\x00\x90\xe0\x03\x13\xaa"}, /* ........ */ \
+ {0x000001c0, "\x21\x50\x10\x91\x40\x00\x3f\xd6"}, /* !P..@.?. */ \
+ {0x000001c8, "\xe0\x03\x14\xaa\xf3\x53\x41\xa9"}, /* .....SA. */ \
+ {0x000001d0, "\xfd\x7b\xc3\xa8\xc0\x03\x5f\xd6"}, /* .{...._. */ \
+ {0x000001d8, "\xa2\x17\x40\xf9\x00\x00\x00\x90"}, /* ..@..... */ \
+ {0x000001e0, "\x00\xe0\x05\x91\x41\x20\x40\xf9"}, /* ....A @. */ \
+ {0x000001e8, "\x3f\x00\x00\xeb\xa8\x00\x00\x54"}, /* ?......T */ \
+ {0x000001f0, "\x42\x24\x40\xf9\x21\x00\x02\x8b"}, /* B$@.!... */ \
+ {0x000001f8, "\x3f\x00\x00\xeb\x68\xfe\xff\x54"}, /* ?...h..T */ \
+ {0x00000200, "\x62\x06\x40\xf9\xd4\x01\x80\xd2"}, /* b.@..... */ \
+ {0x00000208, "\x01\x00\x00\x90\xe0\x03\x13\xaa"}, /* ........ */ \
+ {0x00000210, "\x21\x78\x11\x91\x14\x00\xf0\xf2"}, /* !x...... */ \
+ {0x00000218, "\x40\x00\x3f\xd6\xeb\xff\xff\x17"}, /* @.?..... */ \
+ {0x00000220, "\xfd\x7b\xbc\xa9\x02\x02\x80\xd2"}, /* .{...... */ \
+ {0x00000228, "\xfd\x03\x00\x91\xf5\x5b\x02\xa9"}, /* .....[.. */ \
+ {0x00000230, "\xb6\xc3\x00\x91\xf3\x53\x01\xa9"}, /* .....S.. */ \
+ {0x00000238, "\xf5\x03\x00\xaa\xf4\x03\x01\xaa"}, /* ........ */ \
+ {0x00000240, "\xe0\x03\x16\xaa\x33\x20\x40\xf9"}, /* ....3 @. */ \
+ {0x00000248, "\x01\x00\x00\x90\x21\x80\x14\x91"}, /* ....!... */ \
+ {0x00000250, "\x67\x00\x00\x94\x01\x00\x00\x90"}, /* g....... */ \
+ {0x00000258, "\xe0\x03\x13\xaa\x62\x06\x40\xf9"}, /* ....b.@. */ \
+ {0x00000260, "\x21\x98\x12\x91\x40\x00\x3f\xd6"}, /* !...@.?. */ \
+ {0x00000268, "\xe1\x03\x14\xaa\xe0\x03\x15\xaa"}, /* ........ */ \
+ {0x00000270, "\xc2\xff\xff\x97\x60\x02\x00\xb4"}, /* ....`... */ \
+ {0x00000278, "\x62\x06\x40\xf9\x01\x00\x00\x90"}, /* b.@..... */ \
+ {0x00000280, "\xe0\x03\x13\xaa\x21\x88\x13\x91"}, /* ....!... */ \
+ {0x00000288, "\x40\x00\x3f\xd6\xc1\x01\x80\xd2"}, /* @.?..... */ \
+ {0x00000290, "\x01\x00\xf0\xf2\x80\x32\x40\xf9"}, /* .....2@. */ \
+ {0x00000298, "\xe3\x03\x16\xaa\x02\x02\x80\xd2"}, /* ........ */ \
+ {0x000002a0, "\x04\x6c\x40\xf9\xe0\x03\x15\xaa"}, /* .l@..... */ \
+ {0x000002a8, "\x80\x00\x3f\xd6\x00\x00\x80\xd2"}, /* ..?..... */ \
+ {0x000002b0, "\xf3\x53\x41\xa9\xf5\x5b\x42\xa9"}, /* .SA..[B. */ \
+ {0x000002b8, "\xfd\x7b\xc4\xa8\xc0\x03\x5f\xd6"}, /* .{...._. */ \
+ {0x000002c0, "\xe1\x0b\x41\xb2\xf4\xff\xff\x17"}, /* ..A..... */ \
+ {0x000002c8, "\x21\x20\x00\x91\x02\x00\x80\xd2"}, /* ! ...... */ \
+ {0x000002d0, "\x04\x00\x80\xd2\x03\x00\x80\xd2"}, /* ........ */ \
+ {0x000002d8, "\x25\x80\x5f\xf8\x25\x01\x00\xb5"}, /* %._.%... */ \
+ {0x000002e0, "\x5f\x00\x00\xf1\xe1\x17\x9f\x1a"}, /* _....... */ \
+ {0x000002e8, "\x9f\x00\x00\xf1\xe5\x17\x9f\x1a"}, /* ........ */ \
+ {0x000002f0, "\x3f\x00\x05\x6a\x20\x02\x00\x54"}, /* ?..j ..T */ \
+ {0x000002f8, "\x00\x00\x80\xd2\xc0\x03\x5f\xd6"}, /* ......_. */ \
+ {0x00000300, "\xbf\x20\x00\xf1\x20\x01\x00\x54"}, /* . .. ..T */ \
+ {0x00000308, "\xbf\x24\x00\xf1\x20\x01\x00\x54"}, /* .$.. ..T */ \
+ {0x00000310, "\xbf\x1c\x00\xf1\x61\x00\x00\x54"}, /* ....a..T */ \
+ {0x00000318, "\x22\x00\x40\xf9\x02\x00\x02\x8b"}, /* ".@..... */ \
+ {0x00000320, "\x21\x40\x00\x91\xed\xff\xff\x17"}, /* !@...... */ \
+ {0x00000328, "\x23\x00\x40\xf9\xfd\xff\xff\x17"}, /* #.@..... */ \
+ {0x00000330, "\x24\x00\x40\xf9\xfb\xff\xff\x17"}, /* $.@..... */ \
+ {0x00000338, "\x21\x00\x05\x2a\xa1\x01\x00\x35"}, /* !......5 */ \
+ {0x00000340, "\x7f\x00\x00\xf1\xad\xfd\xff\x54"}, /* .......T */ \
+ {0x00000348, "\x41\x08\x40\xb9\x3f\x0c\x10\xf1"}, /* A.@.?... */ \
+ {0x00000350, "\xa1\x00\x00\x54\x45\x00\x40\xf9"}, /* ...TE.@. */ \
+ {0x00000358, "\x41\x08\x40\xf9\x21\x00\x00\x8b"}, /* A.@.!... */ \
+ {0x00000360, "\xa1\x68\x20\xf8\x42\x00\x04\x8b"}, /* .h .B... */ \
+ {0x00000368, "\x63\x00\x04\xcb\xf5\xff\xff\x17"}, /* c....... */ \
+ {0x00000370, "\xe0\x07\x41\xb2\xc0\x03\x5f\xd6"}, /* ..A..._. */ \
+ {0x00000378, "\x04\x00\x80\xd2\x5f\x00\x04\xeb"}, /* ...._... */ \
+ {0x00000380, "\x61\x00\x00\x54\x00\x00\x80\x52"}, /* a..T...R */ \
+ {0x00000388, "\xc0\x03\x5f\xd6\x03\x68\x64\x38"}, /* .._..hd8 */ \
+ {0x00000390, "\x84\x04\x00\x91\x25\x00\x04\x8b"}, /* ....%... */ \
+ {0x00000398, "\xa5\xf0\x5f\x38\x7f\x00\x05\x6b"}, /* .._8...k */ \
+ {0x000003a0, "\xe0\xfe\xff\x54\x60\x00\x05\x4b"}, /* ...T`..K */ \
+ {0x000003a8, "\xc0\x03\x5f\xd6\x1f\x00\x01\xeb"}, /* .._..... */ \
+ {0x000003b0, "\x68\x01\x00\x54\x03\x00\x80\xd2"}, /* h..T.... */ \
+ {0x000003b8, "\x7f\x00\x02\xeb\x41\x00\x00\x54"}, /* ....A..T */ \
+ {0x000003c0, "\xc0\x03\x5f\xd6\x24\x68\x63\x38"}, /* .._.$hc8 */ \
+ {0x000003c8, "\x04\x68\x23\x38\x63\x04\x00\x91"}, /* .h#8c... */ \
+ {0x000003d0, "\xfa\xff\xff\x17\x23\x68\x62\x38"}, /* ....#hb8 */ \
+ {0x000003d8, "\x03\x68\x22\x38\x42\x04\x00\xd1"}, /* .h"8B... */ \
+ {0x000003e0, "\x5f\x04\x00\xb1\x81\xff\xff\x54"}, /* _......T */ \
+ {0x000003e8, "\xc0\x03\x5f\xd6\xf0\xff\xff\x17"}, /* .._..... */ \
+ {0x000003f0, "\x03\x00\x80\xd2\x5f\x00\x03\xeb"}, /* ...._... */ \
+ {0x000003f8, "\x41\x00\x00\x54\xc0\x03\x5f\xd6"}, /* A..T.._. */ \
+ {0x00000400, "\x01\x68\x23\x38\x63\x04\x00\x91"}, /* .h#8c... */ \
+ {0x00000408, "\xfb\xff\xff\x17\xc0\x03\x5f\xd6"}, /* ......_. */ \
+ {0x00000410, "\xc0\x03\x5f\xd6\x43\x00\x6f\x00"}, /* .._.C.o. */ \
+ {0x00000418, "\x75\x00\x6c\x00\x64\x00\x20\x00"}, /* u.l.d. . */ \
+ {0x00000420, "\x6e\x00\x6f\x00\x74\x00\x20\x00"}, /* n.o.t. . */ \
+ {0x00000428, "\x6f\x00\x70\x00\x65\x00\x6e\x00"}, /* o.p.e.n. */ \
+ {0x00000430, "\x20\x00\x6c\x00\x6f\x00\x61\x00"}, /* .l.o.a. */ \
+ {0x00000438, "\x64\x00\x65\x00\x64\x00\x20\x00"}, /* d.e.d. . */ \
+ {0x00000440, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000448, "\x65\x00\x20\x00\x70\x00\x72\x00"}, /* e. .p.r. */ \
+ {0x00000450, "\x6f\x00\x74\x00\x6f\x00\x63\x00"}, /* o.t.o.c. */ \
+ {0x00000458, "\x6f\x00\x6c\x00\x00\x00\x49\x00"}, /* o.l...I. */ \
+ {0x00000460, "\x6e\x00\x63\x00\x6f\x00\x72\x00"}, /* n.c.o.r. */ \
+ {0x00000468, "\x72\x00\x65\x00\x63\x00\x74\x00"}, /* r.e.c.t. */ \
+ {0x00000470, "\x20\x00\x69\x00\x6d\x00\x61\x00"}, /* .i.m.a. */ \
+ {0x00000478, "\x67\x00\x65\x00\x5f\x00\x62\x00"}, /* g.e._.b. */ \
+ {0x00000480, "\x61\x00\x73\x00\x65\x00\x20\x00"}, /* a.s.e. . */ \
+ {0x00000488, "\x6f\x00\x72\x00\x20\x00\x69\x00"}, /* o.r. .i. */ \
+ {0x00000490, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000498, "\x5f\x00\x73\x00\x69\x00\x7a\x00"}, /* _.s.i.z. */ \
+ {0x000004a0, "\x65\x00\x0a\x00\x00\x00\x45\x00"}, /* e.....E. */ \
+ {0x000004a8, "\x46\x00\x49\x00\x20\x00\x61\x00"}, /* F.I. .a. */ \
+ {0x000004b0, "\x70\x00\x70\x00\x6c\x00\x69\x00"}, /* p.p.l.i. */ \
+ {0x000004b8, "\x63\x00\x61\x00\x74\x00\x69\x00"}, /* c.a.t.i. */ \
+ {0x000004c0, "\x6f\x00\x6e\x00\x20\x00\x63\x00"}, /* o.n. .c. */ \
+ {0x000004c8, "\x61\x00\x6c\x00\x6c\x00\x69\x00"}, /* a.l.l.i. */ \
+ {0x000004d0, "\x6e\x00\x67\x00\x20\x00\x45\x00"}, /* n.g. .E. */ \
+ {0x000004d8, "\x78\x00\x69\x00\x74\x00\x0a\x00"}, /* x.i.t... */ \
+ {0x000004e0, "\x00\x00\x4c\x00\x6f\x00\x61\x00"}, /* ..L.o.a. */ \
+ {0x000004e8, "\x64\x00\x65\x00\x64\x00\x20\x00"}, /* d.e.d. . */ \
+ {0x000004f0, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x000004f8, "\x65\x00\x20\x00\x70\x00\x72\x00"}, /* e. .p.r. */ \
+ {0x00000500, "\x6f\x00\x74\x00\x6f\x00\x63\x00"}, /* o.t.o.c. */ \
+ {0x00000508, "\x6f\x00\x6c\x00\x20\x00\x6d\x00"}, /* o.l. .m. */ \
+ {0x00000510, "\x69\x00\x73\x00\x73\x00\x69\x00"}, /* i.s.s.i. */ \
+ {0x00000518, "\x6e\x00\x67\x00\x0a\x00\x00\x00"}, /* n.g..... */ \
+ {0x00000520, "\x53\x00\x55\x00\x43\x00\x43\x00"}, /* S.U.C.C. */ \
+ {0x00000528, "\x45\x00\x53\x00\x53\x00\x00\x00"}, /* E.S.S... */ \
+ {0x00000530, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000540, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000548, "\xb0\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000550, "\x05\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000558, "\x00\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000560, "\x06\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000568, "\x00\x10\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000570, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000578, "\xaa\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000580, "\x0b\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000588, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000005f0, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x000005f8, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000618, "\x30\x05\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0x00001018, "\x00\x00\x00\x00\x03\x00\x01\x00"}, /* ........ */ \
+ {0x00001030, "\x00\x00\x00\x00\x03\x00\x03\x00"}, /* ........ */ \
+ {0x00001038, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001048, "\x33\x00\x00\x00\x12\x00\x01\x00"}, /* 3....... */ \
+ {0x00001050, "\xac\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001058, "\x40\x00\x00\x00\x00\x00\x00\x00"}, /* @....... */ \
+ {0x00001060, "\x5b\x00\x00\x00\x12\x00\x01\x00"}, /* [....... */ \
+ {0x00001068, "\x10\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001070, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001078, "\x79\x00\x00\x00\x10\x00\x01\x00"}, /* y....... */ \
+ {0x00001080, "\x30\x05\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0x00001090, "\x01\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001098, "\x20\x02\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x000010a0, "\xa8\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010a8, "\x0a\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x000010b0, "\xec\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010b8, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010c0, "\x96\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010c8, "\x20\x06\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x000010d8, "\x22\x00\x00\x00\x12\x00\x01\x00"}, /* "....... */ \
+ {0x000010e0, "\xc8\x02\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010e8, "\xb0\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010f0, "\x91\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010f8, "\x20\x06\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x00001108, "\x2c\x00\x00\x00\x12\x00\x01\x00"}, /* ,....... */ \
+ {0x00001110, "\x78\x03\x00\x00\x00\x00\x00\x00"}, /* x....... */ \
+ {0x00001118, "\x34\x00\x00\x00\x00\x00\x00\x00"}, /* 4....... */ \
+ {0x00001120, "\x73\x00\x00\x00\x10\x00\x01\x00"}, /* s....... */ \
+ {0x00001138, "\x9f\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001140, "\xf0\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001150, "\x11\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001168, "\x42\x00\x00\x00\x12\x00\x01\x00"}, /* B....... */ \
+ {0x00001170, "\x0c\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001178, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001180, "\x3b\x00\x00\x00\x12\x00\x01\x00"}, /* ;....... */ \
+ {0x00001188, "\xf0\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001190, "\x1c\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001198, "\x8b\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000011a0, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000011b0, "\x1b\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000011b8, "\x20\x06\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x000011c8, "\x80\x00\x00\x00\x10\x00\xf1\xff"}, /* ........ */ \
+ {0x000011d0, "\x30\x05\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00001200, { \
+ {0x00000000, "\x4d\x5a\x90\x00\x03\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000008, "\x04\x00\x00\x00\xff\xff\x00\x00"}, /* ........ */ \
+ {0x00000010, "\xb8\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000018, "\x40\x00\x00\x00\x00\x00\x00\x00"}, /* @....... */ \
+ {0x00000038, "\x00\x00\x00\x00\x80\x00\x00\x00"}, /* ........ */ \
+ {0x00000040, "\x0e\x1f\xba\x0e\x00\xb4\x09\xcd"}, /* ........ */ \
+ {0x00000048, "\x21\xb8\x01\x4c\xcd\x21\x54\x68"}, /* !..L.!Th */ \
+ {0x00000050, "\x69\x73\x20\x70\x72\x6f\x67\x72"}, /* is progr */ \
+ {0x00000058, "\x61\x6d\x20\x63\x61\x6e\x6e\x6f"}, /* am canno */ \
+ {0x00000060, "\x74\x20\x62\x65\x20\x72\x75\x6e"}, /* t be run */ \
+ {0x00000068, "\x20\x69\x6e\x20\x44\x4f\x53\x20"}, /* in DOS */ \
+ {0x00000070, "\x6d\x6f\x64\x65\x2e\x0d\x0d\x0a"}, /* mode.... */ \
+ {0x00000078, "\x24\x00\x00\x00\x00\x00\x00\x00"}, /* $....... */ \
+ {0x00000080, "\x50\x45\x00\x00\x4c\x01\x06\x00"}, /* PE..L... */ \
+ {0x00000090, "\x00\x00\x00\x00\xe0\x00\x0e\x03"}, /* ........ */ \
+ {0x00000098, "\x0b\x01\x02\x1e\x00\x04\x00\x00"}, /* ........ */ \
+ {0x000000a0, "\x00\x0a\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000000a8, "\x00\x10\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x000000b0, "\x00\x30\x00\x00\x00\x00\x00\x00"}, /* .0...... */ \
+ {0x000000b8, "\x00\x10\x00\x00\x00\x02\x00\x00"}, /* ........ */ \
+ {0x000000d0, "\x00\x70\x00\x00\x00\x04\x00\x00"}, /* .p...... */ \
+ {0x000000d8, "\x6c\xdf\x00\x00\x0a\x00\x00\x00"}, /* l....... */ \
+ {0x000000f0, "\x00\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x00000120, "\x00\x50\x00\x00\x0a\x00\x00\x00"}, /* .P...... */ \
+ {0x00000178, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000180, "\x1b\x02\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x00000188, "\x00\x04\x00\x00\x00\x04\x00\x00"}, /* ........ */ \
+ {0x00000198, "\x00\x00\x00\x00\x20\x00\x30\x60"}, /* .... .0` */ \
+ {0x000001a0, "\x2e\x73\x64\x61\x74\x61\x00\x00"}, /* .sdata.. */ \
+ {0x000001a8, "\x0c\x00\x00\x00\x00\x20\x00\x00"}, /* ..... .. */ \
+ {0x000001b0, "\x00\x02\x00\x00\x00\x08\x00\x00"}, /* ........ */ \
+ {0x000001c0, "\x00\x00\x00\x00\x40\x00\x30\xc0"}, /* ....@.0. */ \
+ {0x000001c8, "\x2e\x64\x61\x74\x61\x00\x00\x00"}, /* .data... */ \
+ {0x000001d0, "\x38\x01\x00\x00\x00\x30\x00\x00"}, /* 8....0.. */ \
+ {0x000001d8, "\x00\x02\x00\x00\x00\x0a\x00\x00"}, /* ........ */ \
+ {0x000001e8, "\x00\x00\x00\x00\x40\x00\x40\xc0"}, /* ....@.@. */ \
+ {0x000001f0, "\x2e\x64\x79\x6e\x61\x6d\x69\x63"}, /* .dynamic */ \
+ {0x000001f8, "\x70\x00\x00\x00\x00\x40\x00\x00"}, /* p....@.. */ \
+ {0x00000200, "\x00\x02\x00\x00\x00\x0c\x00\x00"}, /* ........ */ \
+ {0x00000210, "\x00\x00\x00\x00\x40\x00\x30\xc0"}, /* ....@.0. */ \
+ {0x00000218, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000220, "\x0a\x00\x00\x00\x00\x50\x00\x00"}, /* .....P.. */ \
+ {0x00000228, "\x00\x02\x00\x00\x00\x0e\x00\x00"}, /* ........ */ \
+ {0x00000238, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000240, "\x2e\x64\x79\x6e\x73\x79\x6d\x00"}, /* .dynsym. */ \
+ {0x00000248, "\x30\x00\x00\x00\x00\x60\x00\x00"}, /* 0....`.. */ \
+ {0x00000250, "\x00\x02\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x00000260, "\x00\x00\x00\x00\x40\x00\x30\x40"}, /* ....@.0@ */ \
+ {0x00000400, "\x55\x89\xe5\xff\x75\x0c\xff\x75"}, /* U...u..u */ \
+ {0x00000408, "\x08\xe8\x00\x00\x00\x00\x58\x89"}, /* ......X. */ \
+ {0x00000410, "\xc3\x05\xf2\xef\xff\xff\x81\xc3"}, /* ........ */ \
+ {0x00000418, "\xf2\x2f\x00\x00\x53\x50\xe8\x20"}, /* ./..SP. */ \
+ {0x00000420, "\x01\x00\x00\x5b\x5b\x85\xc0\x75"}, /* ...[[..u */ \
+ {0x00000428, "\x05\xe8\x8a\x00\x00\x00\xc9\xc3"}, /* ........ */ \
+ {0x00000430, "\x57\x56\x53\x83\xec\x18\xe8\x00"}, /* WVS..... */ \
+ {0x00000438, "\x01\x00\x00\x81\xc6\xc5\x0f\x00"}, /* ........ */ \
+ {0x00000440, "\x00\x8b\x44\x24\x2c\x8b\x58\x2c"}, /* ..D$,.X, */ \
+ {0x00000448, "\x8b\x40\x3c\x6a\x02\x6a\x00\x6a"}, /* .@<j.j.j */ \
+ {0x00000450, "\x00\x8d\x54\x24\x20\x52\x8d\x96"}, /* ..T$ R.. */ \
+ {0x00000458, "\x28\x11\x00\x00\x52\xff\x74\x24"}, /* (...R.t$ */ \
+ {0x00000460, "\x3c\xff\x90\x98\x00\x00\x00\x89"}, /* <....... */ \
+ {0x00000468, "\xc7\x83\xc4\x20\x85\xc0\x74\x12"}, /* ... ..t. */ \
+ {0x00000470, "\x52\x52\x8d\x86\x02\x10\x00\x00"}, /* RR...... */ \
+ {0x00000478, "\x50\x53\xff\x53\x04\x83\xc4\x10"}, /* PS.S.... */ \
+ {0x00000480, "\xeb\x2d\x8b\x4c\x24\x0c\x8b\x41"}, /* .-.L$..A */ \
+ {0x00000488, "\x20\x8d\x96\x30\xf0\xff\xff\x39"}, /* ..0...9 */ \
+ {0x00000490, "\xd0\x77\x07\x03\x41\x28\x39\xd0"}, /* .w..A(9. */ \
+ {0x00000498, "\x77\x15\x50\x50\x8d\x86\x4c\x10"}, /* w.PP..L. */ \
+ {0x000004a0, "\x00\x00\x50\x53\xff\x53\x04\x83"}, /* ..PS.S.. */ \
+ {0x000004a8, "\xc4\x10\xbf\x0e\x00\x00\x80\x89"}, /* ........ */ \
+ {0x000004b0, "\xf8\x83\xc4\x10\x5b\x5e\x5f\xc3"}, /* ....[^_. */ \
+ {0x000004b8, "\x55\x57\x56\x53\x83\xec\x1c\xe8"}, /* UWVS.... */ \
+ {0x000004c0, "\x7b\x00\x00\x00\x81\xc5\x3c\x0f"}, /* {.....<. */ \
+ {0x000004c8, "\x00\x00\x8b\x44\x24\x34\x8b\x58"}, /* ...D$4.X */ \
+ {0x000004d0, "\x2c\x89\xe7\x8d\xb5\x0e\x11\x00"}, /* ,....... */ \
+ {0x000004d8, "\x00\xb9\x04\x00\x00\x00\xf3\xa5"}, /* ........ */ \
+ {0x000004e0, "\x52\x52\x8d\x85\x94\x10\x00\x00"}, /* RR...... */ \
+ {0x000004e8, "\x50\x53\xff\x53\x04\x59\x5e\xff"}, /* PS.S.Y^. */ \
+ {0x000004f0, "\x74\x24\x3c\xff\x74\x24\x3c\xe8"}, /* t$<.t$<. */ \
+ {0x000004f8, "\x34\xff\xff\xff\x83\xc4\x10\xba"}, /* 4....... */ \
+ {0x00000500, "\x03\x00\x00\x80\x85\xc0\x74\x15"}, /* ......t. */ \
+ {0x00000508, "\x50\x50\x8d\x85\xd0\x10\x00\x00"}, /* PP...... */ \
+ {0x00000510, "\x50\x53\xff\x53\x04\x83\xc4\x10"}, /* PS.S.... */ \
+ {0x00000518, "\xba\x0e\x00\x00\x80\x8b\x44\x24"}, /* ......D$ */ \
+ {0x00000520, "\x34\x8b\x40\x3c\x89\xe1\x51\x6a"}, /* 4.@<..Qj */ \
+ {0x00000528, "\x10\x52\xff\x74\x24\x3c\xff\x50"}, /* .R.t$<.P */ \
+ {0x00000530, "\x78\x31\xc0\x83\xc4\x2c\x5b\x5e"}, /* x1...,[^ */ \
+ {0x00000538, "\x5f\x5d\xc3\x8b\x34\x24\xc3\x8b"}, /* _]..4$.. */ \
+ {0x00000540, "\x2c\x24\xc3\x57\x56\x53\x8b\x7c"}, /* ,$.WVS.| */ \
+ {0x00000548, "\x24\x10\x8b\x44\x24\x14\x83\xc0"}, /* $..D$... */ \
+ {0x00000550, "\x04\x31\xd2\x31\xc9\x31\xdb\x8b"}, /* .1.1.1.. */ \
+ {0x00000558, "\x70\xfc\x85\xf6\x74\x20\x83\xfe"}, /* p...t .. */ \
+ {0x00000560, "\x12\x74\x10\x83\xfe\x13\x74\x0f"}, /* .t....t. */ \
+ {0x00000568, "\x83\xfe\x11\x75\x0c\x8b\x10\x01"}, /* ...u.... */ \
+ {0x00000570, "\xfa\xeb\x06\x8b\x18\xeb\x02\x8b"}, /* ........ */ \
+ {0x00000578, "\x08\x83\xc0\x08\xeb\xd9\xb8\x01"}, /* ........ */ \
+ {0x00000580, "\x00\x00\x80\x85\xd2\x75\x08\x85"}, /* .....u.. */ \
+ {0x00000588, "\xc9\x75\x1e\x31\xc0\xeb\x1a\x85"}, /* .u.1.... */ \
+ {0x00000590, "\xc9\x74\x16\x85\xdb\x7e\xf4\x80"}, /* .t...~.. */ \
+ {0x00000598, "\x7a\x04\x08\x75\x06\x8b\x02\x01"}, /* z..u.... */ \
+ {0x000005a0, "\xf8\x01\x38\x01\xca\x29\xcb\xeb"}, /* ..8..).. */ \
+ {0x000005a8, "\xea\x5b\x5e\x5f\xc3\x57\x56\x53"}, /* .[^_.WVS */ \
+ {0x000005b0, "\x53\x89\xc7\x31\xf6\x39\xf1\x74"}, /* S..1.9.t */ \
+ {0x000005b8, "\x1c\x8a\x1c\x37\x46\x8a\x44\x32"}, /* ...7F.D2 */ \
+ {0x000005c0, "\xff\x88\x44\x24\x03\x38\xc3\x74"}, /* ..D$.8.t */ \
+ {0x000005c8, "\xec\x0f\xb6\xc3\x0f\xb6\x54\x24"}, /* ......T$ */ \
+ {0x000005d0, "\x03\x29\xd0\xeb\x02\x31\xc0\x5a"}, /* .)...1.Z */ \
+ {0x000005d8, "\x5b\x5e\x5f\xc3\x56\x53\x89\xce"}, /* [^_.VS.. */ \
+ {0x000005e0, "\x39\xd0\x77\x0f\x31\xdb\x39\xde"}, /* 9.w.1.9. */ \
+ {0x000005e8, "\x74\x18\x8a\x0c\x1a\x88\x0c\x18"}, /* t....... */ \
+ {0x000005f0, "\x43\xeb\xf3\x85\xf6\x74\x0b\x8a"}, /* C....t.. */ \
+ {0x000005f8, "\x5c\x32\xff\x88\x5c\x30\xff\x4e"}, /* \2..\0.N */ \
+ {0x00000600, "\xeb\xf1\x5b\x5e\xc3\xe9\xd2\xff"}, /* ..[^.... */ \
+ {0x00000608, "\xff\xff\x53\x31\xdb\x39\xd9\x74"}, /* ..S1.9.t */ \
+ {0x00000610, "\x06\x88\x14\x18\x43\xeb\xf6\x5b"}, /* ....C..[ */ \
+ {0x00000618, "\xc3\xc3\xc3\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000800, "\x00\x40\x00\x00\x00\x00\x00\x00"}, /* .@...... */ \
+ {0x00000a00, "\x00\x00\x43\x00\x6f\x00\x75\x00"}, /* ..C.o.u. */ \
+ {0x00000a08, "\x6c\x00\x64\x00\x20\x00\x6e\x00"}, /* l.d. .n. */ \
+ {0x00000a10, "\x6f\x00\x74\x00\x20\x00\x6f\x00"}, /* o.t. .o. */ \
+ {0x00000a18, "\x70\x00\x65\x00\x6e\x00\x20\x00"}, /* p.e.n. . */ \
+ {0x00000a20, "\x6c\x00\x6f\x00\x61\x00\x64\x00"}, /* l.o.a.d. */ \
+ {0x00000a28, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000a30, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000a38, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000a40, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000a48, "\x6c\x00\x00\x00\x49\x00\x6e\x00"}, /* l...I.n. */ \
+ {0x00000a50, "\x63\x00\x6f\x00\x72\x00\x72\x00"}, /* c.o.r.r. */ \
+ {0x00000a58, "\x65\x00\x63\x00\x74\x00\x20\x00"}, /* e.c.t. . */ \
+ {0x00000a60, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000a68, "\x65\x00\x5f\x00\x62\x00\x61\x00"}, /* e._.b.a. */ \
+ {0x00000a70, "\x73\x00\x65\x00\x20\x00\x6f\x00"}, /* s.e. .o. */ \
+ {0x00000a78, "\x72\x00\x20\x00\x69\x00\x6d\x00"}, /* r. .i.m. */ \
+ {0x00000a80, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000a88, "\x73\x00\x69\x00\x7a\x00\x65\x00"}, /* s.i.z.e. */ \
+ {0x00000a90, "\x0a\x00\x00\x00\x45\x00\x46\x00"}, /* ....E.F. */ \
+ {0x00000a98, "\x49\x00\x20\x00\x61\x00\x70\x00"}, /* I. .a.p. */ \
+ {0x00000aa0, "\x70\x00\x6c\x00\x69\x00\x63\x00"}, /* p.l.i.c. */ \
+ {0x00000aa8, "\x61\x00\x74\x00\x69\x00\x6f\x00"}, /* a.t.i.o. */ \
+ {0x00000ab0, "\x6e\x00\x20\x00\x63\x00\x61\x00"}, /* n. .c.a. */ \
+ {0x00000ab8, "\x6c\x00\x6c\x00\x69\x00\x6e\x00"}, /* l.l.i.n. */ \
+ {0x00000ac0, "\x67\x00\x20\x00\x45\x00\x78\x00"}, /* g. .E.x. */ \
+ {0x00000ac8, "\x69\x00\x74\x00\x0a\x00\x00\x00"}, /* i.t..... */ \
+ {0x00000ad0, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000ad8, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000ae0, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000ae8, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000af0, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000af8, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000b00, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x00000b08, "\x67\x00\x0a\x00\x00\x00\x53\x00"}, /* g.....S. */ \
+ {0x00000b10, "\x55\x00\x43\x00\x43\x00\x45\x00"}, /* U.C.C.E. */ \
+ {0x00000b18, "\x53\x00\x53\x00\x00\x00\x00\x00"}, /* S.S..... */ \
+ {0x00000b28, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000b30, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000c00, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c08, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c10, "\xf5\xfe\xff\x6f\x14\x70\x00\x00"}, /* ...o.p.. */ \
+ {0x00000c18, "\x05\x00\x00\x00\x00\x70\x00\x00"}, /* .....p.. */ \
+ {0x00000c20, "\x06\x00\x00\x00\x00\x60\x00\x00"}, /* .....`.. */ \
+ {0x00000c28, "\x0a\x00\x00\x00\x13\x00\x00\x00"}, /* ........ */ \
+ {0x00000c30, "\x0b\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x00000c38, "\x1e\x00\x00\x00\x02\x00\x00\x00"}, /* ........ */ \
+ {0x00000e00, "\x20\x31\x00\x00\x0a\x00\x00\x00"}, /* 1...... */ \
+ {0x00001010, "\x01\x00\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x00001018, "\x00\x00\x00\x00\x10\x00\x02\x00"}, /* ........ */ \
+ {0x00001020, "\x08\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001028, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00001130, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000030, "\x52\x49\x53\x43\x56\x00\x00\x00"}, /* RISCV... */ \
+ {0x00000038, "\x52\x53\x43\x05\x40\x00\x00\x00"}, /* RSC.@... */ \
+ {0x00000040, "\x50\x45\x00\x00\x32\x50\x02\x00"}, /* PE..2P.. */ \
+ {0x00000050, "\x00\x00\x00\x00\xe0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000058, "\x0b\x01\x02\x14\xb8\x03\x00\x00"}, /* ........ */ \
+ {0x00000068, "\x88\x01\x00\x00\x88\x01\x00\x00"}, /* ........ */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000080, "\x00\x00\x00\x00\x01\x00\x00\x00"}, /* ........ */ \
+ {0x00000090, "\x40\x05\x00\x00\x88\x01\x00\x00"}, /* @....... */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000b0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x00000138, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000158, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000160, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000168, "\xb8\x03\x00\x00\x88\x01\x00\x00"}, /* ........ */ \
+ {0x00000170, "\xb8\x03\x00\x00\x88\x01\x00\x00"}, /* ........ */ \
+ {0x00000180, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000188, "\x51\x11\x2a\xc0\x2e\xc2\x06\xc4"}, /* Q....... */ \
+ {0x00000190, "\x17\x05\x00\x00\x13\x05\x05\xe7"}, /* ........ */ \
+ {0x00000198, "\x97\x05\x00\x00\x93\x85\x85\x30"}, /* .......0 */ \
+ {0x000001a0, "\xe5\x28\x09\xe5\x92\x45\x02\x45"}, /* .(...E.E */ \
+ {0x000001a8, "\x9d\x28\xa2\x40\x31\x01\x82\x80"}, /* .(.@1... */ \
+ {0x000001b0, "\x01\x11\x22\xcc\x06\xce\x26\xca"}, /* .."...&. */ \
+ {0x000001b8, "\xdc\x5d\xc4\x55\x01\x47\x03\xa8"}, /* .].U.G.. */ \
+ {0x000001c0, "\x87\x09\x81\x46\x89\x47\x70\x00"}, /* ...F.Gp. */ \
+ {0x000001c8, "\x97\x05\x00\x00\x93\x85\x85\x35"}, /* .......5 */ \
+ {0x000001d0, "\x02\x98\x2a\x84\x11\xcd\xdc\x40"}, /* .......@ */ \
+ {0x000001d8, "\x97\x05\x00\x00\x93\x85\x05\x1a"}, /* ........ */ \
+ {0x000001e0, "\x26\x85\x82\x97\xf2\x40\x22\x85"}, /* &....@". */ \
+ {0x000001e8, "\x62\x44\xd2\x44\x05\x61\x82\x80"}, /* bD.D.a.. */ \
+ {0x000001f0, "\xb2\x46\x17\x07\x00\x00\x13\x07"}, /* .F...... */ \
+ {0x000001f8, "\xe7\xfb\x9c\x52\x63\x66\xf7\x00"}, /* ...Rcf.. */ \
+ {0x00000200, "\x94\x56\xb6\x97\xe3\x60\xf7\xfe"}, /* .V...`.. */ \
+ {0x00000208, "\xdc\x40\x97\x05\x00\x00\x93\x85"}, /* .@...... */ \
+ {0x00000210, "\xa5\x1b\x26\x85\x37\x04\x00\x80"}, /* ..&.7... */ \
+ {0x00000218, "\x82\x97\x39\x04\xe1\xb7\x79\x71"}, /* ..9...yq */ \
+ {0x00000220, "\x06\xd6\x22\xd4\x26\xd2\x4e\xce"}, /* ..".&.N. */ \
+ {0x00000228, "\x4a\xd0\x03\xa9\xc5\x02\x8a\x89"}, /* J....... */ \
+ {0x00000230, "\xaa\x84\x2e\x84\x41\x46\x97\x05"}, /* ....AF.. */ \
+ {0x00000238, "\x00\x00\x93\x85\x25\x25\x4e\x85"}, /* ....%%N. */ \
+ {0x00000240, "\x39\x2a\x83\x27\x49\x00\x97\x05"}, /* 9..'I... */ \
+ {0x00000248, "\x00\x00\x93\x85\x65\x1c\x4a\x85"}, /* ....e.J. */ \
+ {0x00000250, "\x82\x97\xa2\x85\x26\x85\xa9\x3f"}, /* ....&..? */ \
+ {0x00000258, "\x1d\xc9\x83\x27\x49\x00\x97\x05"}, /* ...'I... */ \
+ {0x00000260, "\x00\x00\x93\x85\xa5\x1e\x4a\x85"}, /* ......J. */ \
+ {0x00000268, "\x82\x97\xb7\x07\x00\x80\x93\x85"}, /* ........ */ \
+ {0x00000270, "\xe7\x00\x5c\x5c\xce\x86\x26\x85"}, /* ..\\..&. */ \
+ {0x00000278, "\xbc\x5f\x41\x46\x82\x97\xb2\x50"}, /* ._AF...P */ \
+ {0x00000280, "\x22\x54\x92\x54\x02\x59\xf2\x49"}, /* "T.T.Y.I */ \
+ {0x00000288, "\x01\x45\x45\x61\x82\x80\xb7\x07"}, /* .EEa.... */ \
+ {0x00000290, "\x00\x80\x93\x85\x37\x00\xf1\xbf"}, /* ....7... */ \
+ {0x00000298, "\x81\x47\x01\x47\x81\x46\x21\x48"}, /* .G.G.F!H */ \
+ {0x000002a0, "\xa5\x48\x1d\x43\x90\x41\x09\xe6"}, /* .H.C.A.. */ \
+ {0x000002a8, "\x95\xe3\x1d\xe3\x01\x45\x82\x80"}, /* .....E.. */ \
+ {0x000002b0, "\x63\x0a\x06\x01\x63\x0a\x16\x01"}, /* c...c... */ \
+ {0x000002b8, "\x63\x14\x66\x00\xdc\x41\xaa\x97"}, /* c.f..A.. */ \
+ {0x000002c0, "\xa1\x05\xcd\xb7\xd4\x41\xed\xbf"}, /* .....A.. */ \
+ {0x000002c8, "\xd8\x41\xdd\xbf\x0d\x48\x05\xe3"}, /* .A...H.. */ \
+ {0x000002d0, "\x37\x05\x00\x80\x05\x05\x82\x80"}, /* 7....... */ \
+ {0x000002d8, "\x03\xc6\x47\x00\x63\x1c\x06\x01"}, /* ..G.c... */ \
+ {0x000002e0, "\x90\x43\x8c\x47\x99\x8e\x2a\x96"}, /* .C.G.... */ \
+ {0x000002e8, "\xaa\x95\x0c\xc2\xba\x97\xe3\x45"}, /* .......E */ \
+ {0x000002f0, "\xd0\xfe\x6d\xbf\x01\xa0\x01\x47"}, /* ..m....G */ \
+ {0x000002f8, "\x63\x14\xe6\x00\x01\x45\x82\x80"}, /* c....E.. */ \
+ {0x00000300, "\xb3\x07\xe5\x00\x05\x07\xb3\x86"}, /* ........ */ \
+ {0x00000308, "\xe5\x00\x83\xc7\x07\x00\x83\xc6"}, /* ........ */ \
+ {0x00000310, "\xf6\xff\xe3\x83\xd7\xfe\x33\x85"}, /* ......3. */ \
+ {0x00000318, "\xd7\x40\x82\x80\x63\xf5\xa5\x02"}, /* .@..c... */ \
+ {0x00000320, "\x93\x46\xf6\xff\x81\x47\xfd\x17"}, /* .F...G.. */ \
+ {0x00000328, "\x63\x91\xd7\x02\x82\x80\x33\x87"}, /* c.....3. */ \
+ {0x00000330, "\xf5\x00\x83\x46\x07\x00\x33\x07"}, /* ...F..3. */ \
+ {0x00000338, "\xf5\x00\x85\x07\x23\x00\xd7\x00"}, /* ....#... */ \
+ {0x00000340, "\xe3\x97\xc7\xfe\x82\x80\x81\x47"}, /* .......G */ \
+ {0x00000348, "\xe5\xbf\x33\x07\xf6\x00\x33\x88"}, /* ..3...3. */ \
+ {0x00000350, "\xe5\x00\x03\x48\x08\x00\x2a\x97"}, /* ...H.... */ \
+ {0x00000358, "\x23\x00\x07\x01\xe9\xb7\x7d\xbf"}, /* #.....}. */ \
+ {0x00000360, "\x2a\x96\xaa\x87\x63\x93\xc7\x00"}, /* ....c... */ \
+ {0x00000368, "\x82\x80\x85\x07\xa3\x8f\xb7\xfe"}, /* ........ */ \
+ {0x00000370, "\xd5\xbf\x82\x80\x82\x80\x00\x00"}, /* ........ */ \
+ {0x00000378, "\x43\x00\x6f\x00\x75\x00\x6c\x00"}, /* C.o.u.l. */ \
+ {0x00000380, "\x64\x00\x20\x00\x6e\x00\x6f\x00"}, /* d. .n.o. */ \
+ {0x00000388, "\x74\x00\x20\x00\x6f\x00\x70\x00"}, /* t. .o.p. */ \
+ {0x00000390, "\x65\x00\x6e\x00\x20\x00\x6c\x00"}, /* e.n. .l. */ \
+ {0x00000398, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x000003a0, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x000003a8, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x000003b0, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x000003b8, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x000003c0, "\x00\x00\x00\x00\x49\x00\x6e\x00"}, /* ....I.n. */ \
+ {0x000003c8, "\x63\x00\x6f\x00\x72\x00\x72\x00"}, /* c.o.r.r. */ \
+ {0x000003d0, "\x65\x00\x63\x00\x74\x00\x20\x00"}, /* e.c.t. . */ \
+ {0x000003d8, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x000003e0, "\x65\x00\x5f\x00\x62\x00\x61\x00"}, /* e._.b.a. */ \
+ {0x000003e8, "\x73\x00\x65\x00\x20\x00\x6f\x00"}, /* s.e. .o. */ \
+ {0x000003f0, "\x72\x00\x20\x00\x69\x00\x6d\x00"}, /* r. .i.m. */ \
+ {0x000003f8, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000400, "\x73\x00\x69\x00\x7a\x00\x65\x00"}, /* s.i.z.e. */ \
+ {0x00000408, "\x0a\x00\x00\x00\x45\x00\x46\x00"}, /* ....E.F. */ \
+ {0x00000410, "\x49\x00\x20\x00\x61\x00\x70\x00"}, /* I. .a.p. */ \
+ {0x00000418, "\x70\x00\x6c\x00\x69\x00\x63\x00"}, /* p.l.i.c. */ \
+ {0x00000420, "\x61\x00\x74\x00\x69\x00\x6f\x00"}, /* a.t.i.o. */ \
+ {0x00000428, "\x6e\x00\x20\x00\x63\x00\x61\x00"}, /* n. .c.a. */ \
+ {0x00000430, "\x6c\x00\x6c\x00\x69\x00\x6e\x00"}, /* l.l.i.n. */ \
+ {0x00000438, "\x67\x00\x20\x00\x45\x00\x78\x00"}, /* g. .E.x. */ \
+ {0x00000440, "\x69\x00\x74\x00\x0a\x00\x00\x00"}, /* i.t..... */ \
+ {0x00000448, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000450, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000458, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000460, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000468, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000470, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000478, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x00000480, "\x67\x00\x0a\x00\x00\x00\x00\x00"}, /* g....... */ \
+ {0x00000488, "\x53\x00\x55\x00\x43\x00\x43\x00"}, /* S.U.C.C. */ \
+ {0x00000490, "\x45\x00\x53\x00\x53\x00\x00\x00"}, /* E.S.S... */ \
+ {0x000004a0, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004a8, "\x04\x00\x00\x00\xac\x20\x00\x00"}, /* ..... .. */ \
+ {0x000004b0, "\xf5\xfe\xff\x6f\x44\x21\x00\x00"}, /* ...oD!.. */ \
+ {0x000004b8, "\x05\x00\x00\x00\x00\x20\x00\x00"}, /* ..... .. */ \
+ {0x000004c0, "\x06\x00\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x000004c8, "\x0a\x00\x00\x00\xaa\x00\x00\x00"}, /* ........ */ \
+ {0x000004d0, "\x0b\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x000004d8, "\x07\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004e0, "\x08\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004e8, "\x09\x00\x00\x00\x0c\x00\x00\x00"}, /* ........ */ \
+ {0x00000520, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000528, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000530, "\xa0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001018, "\x00\x00\x00\x00\x03\x00\x01\x00"}, /* ........ */ \
+ {0x00001020, "\x42\x00\x00\x00\x72\x03\x00\x00"}, /* B...r... */ \
+ {0x00001028, "\x02\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001030, "\x73\x00\x00\x00\x00\x00\x00\x00"}, /* s....... */ \
+ {0x00001038, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001040, "\x3b\x00\x00\x00\x60\x03\x00\x00"}, /* ;...`... */ \
+ {0x00001048, "\x12\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001050, "\x96\x00\x00\x00\x40\x05\x00\x00"}, /* ....@... */ \
+ {0x00001058, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001060, "\x22\x00\x00\x00\x98\x02\x00\x00"}, /* "....... */ \
+ {0x00001068, "\x5e\x00\x00\x00\x12\x00\x01\x00"}, /* ^....... */ \
+ {0x00001070, "\x2c\x00\x00\x00\xf6\x02\x00\x00"}, /* ,....... */ \
+ {0x00001078, "\x26\x00\x00\x00\x12\x00\x01\x00"}, /* &....... */ \
+ {0x00001080, "\x1b\x00\x00\x00\x40\x05\x00\x00"}, /* ....@... */ \
+ {0x00001088, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001090, "\x5b\x00\x00\x00\x74\x03\x00\x00"}, /* [...t... */ \
+ {0x00001098, "\x02\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x000010a0, "\x9f\x00\x00\x00\xa0\x00\x00\x00"}, /* ........ */ \
+ {0x000010a8, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010b0, "\x79\x00\x00\x00\xa0\x04\x00\x00"}, /* y....... */ \
+ {0x000010b8, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x000010c0, "\x33\x00\x00\x00\x1c\x03\x00\x00"}, /* 3....... */ \
+ {0x000010c8, "\x42\x00\x00\x00\x12\x00\x01\x00"}, /* B....... */ \
+ {0x000010d0, "\x01\x00\x00\x00\x1e\x02\x00\x00"}, /* ........ */ \
+ {0x000010d8, "\x7a\x00\x00\x00\x12\x00\x01\x00"}, /* z....... */ \
+ {0x000010e0, "\x91\x00\x00\x00\x40\x05\x00\x00"}, /* ....@... */ \
+ {0x000010e8, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010f0, "\x11\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010f8, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001100, "\x80\x00\x00\x00\xa0\x04\x00\x00"}, /* ........ */ \
+ {0x00001108, "\x00\x00\x00\x00\x10\x00\xf1\xff"}, /* ........ */ \
+ {0x00001110, "\x0a\x00\x00\x00\x5e\x03\x00\x00"}, /* ....^... */ \
+ {0x00001118, "\x02\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001120, "\x8b\x00\x00\x00\x20\x05\x00\x00"}, /* .... ... */ \
+ {0x00001128, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x000011c8, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000030, "\x52\x49\x53\x43\x56\x00\x00\x00"}, /* RISCV... */ \
+ {0x00000038, "\x52\x53\x43\x05\x40\x00\x00\x00"}, /* RSC.@... */ \
+ {0x00000040, "\x50\x45\x00\x00\x64\x50\x02\x00"}, /* PE..dP.. */ \
+ {0x00000050, "\x00\x00\x00\x00\xf0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000058, "\x0b\x02\x02\x14\x58\x04\x00\x00"}, /* ....X... */ \
+ {0x00000068, "\x98\x01\x00\x00\x98\x01\x00\x00"}, /* ........ */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000080, "\x00\x00\x00\x00\x01\x00\x00\x00"}, /* ........ */ \
+ {0x00000090, "\xf0\x05\x00\x00\x98\x01\x00\x00"}, /* ........ */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000c0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x00000148, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000168, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000170, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000178, "\x58\x04\x00\x00\x98\x01\x00\x00"}, /* X....... */ \
+ {0x00000180, "\x58\x04\x00\x00\x98\x01\x00\x00"}, /* X....... */ \
+ {0x00000190, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000198, "\x21\x11\x2a\xe0\x2e\xe4\x06\xe8"}, /* !....... */ \
+ {0x000001a0, "\x17\x05\x00\x00\x13\x05\x05\xe6"}, /* ........ */ \
+ {0x000001a8, "\x97\x05\x00\x00\x93\x85\x85\x31"}, /* .......1 */ \
+ {0x000001b0, "\xef\x00\x20\x0f\x63\x17\x05\x00"}, /* .. .c... */ \
+ {0x000001b8, "\xa2\x65\x02\x65\xef\x00\x80\x07"}, /* .e.e.... */ \
+ {0x000001c0, "\xc2\x60\x61\x01\x82\x80\x79\x71"}, /* .`a...yq */ \
+ {0x000001c8, "\x22\xf0\x06\xf4\x26\xec\xbc\x71"}, /* "...&..q */ \
+ {0x000001d0, "\xa4\x61\x01\x47\x03\xb8\x87\x11"}, /* .a.G.... */ \
+ {0x000001d8, "\x81\x46\x89\x47\x30\x00\x97\x05"}, /* .F.G0... */ \
+ {0x000001e0, "\x00\x00\x93\x85\x25\x3f\x02\x98"}, /* ....%?.. */ \
+ {0x000001e8, "\x2a\x84\x11\xcd\x9c\x64\x97\x05"}, /* .....d.. */ \
+ {0x000001f0, "\x00\x00\x93\x85\x25\x1a\x26\x85"}, /* ....%.&. */ \
+ {0x000001f8, "\x82\x97\x22\x85\xa2\x70\x02\x74"}, /* .."..p.t */ \
+ {0x00000200, "\xe2\x64\x45\x61\x82\x80\xa2\x66"}, /* .dEa...f */ \
+ {0x00000208, "\x17\x07\x00\x00\x13\x07\xe7\xfb"}, /* ........ */ \
+ {0x00000210, "\xbc\x62\x63\x66\xf7\x00\xb4\x66"}, /* .bcf...f */ \
+ {0x00000218, "\xb6\x97\xe3\x60\xf7\xfe\x9c\x64"}, /* ...`...d */ \
+ {0x00000220, "\x7d\x54\x97\x05\x00\x00\x93\x85"}, /* }T...... */ \
+ {0x00000228, "\xe5\x1b\x26\x85\x7e\x14\x82\x97"}, /* ..&.~... */ \
+ {0x00000230, "\x39\x04\xe1\xb7\x79\x71\x97\x07"}, /* 9...yq.. */ \
+ {0x00000238, "\x00\x00\x93\x87\x27\x27\x26\xec"}, /* ....''&. */ \
+ {0x00000240, "\x4a\xe8\x06\xf4\x22\xf0\x98\x63"}, /* J..."..c */ \
+ {0x00000248, "\x9c\x67\xa0\x61\x3a\xe0\x3e\xe4"}, /* .g.a:.>. */ \
+ {0x00000250, "\x1c\x64\x2a\x89\xae\x84\x22\x85"}, /* .d....". */ \
+ {0x00000258, "\x97\x05\x00\x00\x93\x85\x05\x1d"}, /* ........ */ \
+ {0x00000260, "\x82\x97\xa6\x85\x4a\x85\xef\xf0"}, /* ....J... */ \
+ {0x00000268, "\x1f\xf6\x05\xc9\x1c\x64\x97\x05"}, /* .....d.. */ \
+ {0x00000270, "\x00\x00\x93\x85\xa5\x1f\x22\x85"}, /* ......". */ \
+ {0x00000278, "\x82\x97\xfd\x55\xfe\x15\xb9\x05"}, /* ...U.... */ \
+ {0x00000280, "\xbc\x70\x8a\x86\x4a\x85\xfc\x6f"}, /* .p..J..o */ \
+ {0x00000288, "\x41\x46\x82\x97\xa2\x70\x02\x74"}, /* AF...p.t */ \
+ {0x00000290, "\xe2\x64\x42\x69\x01\x45\x45\x61"}, /* .dBi.EEa */ \
+ {0x00000298, "\x82\x80\xfd\x55\xfe\x15\x8d\x05"}, /* ...U.... */ \
+ {0x000002a0, "\xc5\xb7\xa1\x05\x81\x47\x01\x47"}, /* .....G.G */ \
+ {0x000002a8, "\x81\x46\x21\x48\xa5\x48\x1d\x43"}, /* .F!H.H.C */ \
+ {0x000002b0, "\x03\xb6\x85\xff\x09\xe6\x95\xe3"}, /* ........ */ \
+ {0x000002b8, "\x31\xe7\x01\x45\x82\x80\x63\x0a"}, /* 1..E..c. */ \
+ {0x000002c0, "\x06\x01\x63\x0a\x16\x01\x63\x14"}, /* ..c...c. */ \
+ {0x000002c8, "\x66\x00\x9c\x61\xaa\x97\xc1\x05"}, /* f..a.... */ \
+ {0x000002d0, "\xc5\xb7\x94\x61\xed\xbf\x98\x61"}, /* ...a...a */ \
+ {0x000002d8, "\xdd\xbf\x0d\xc7\x7d\x56\x01\x92"}, /* ....}V.. */ \
+ {0x000002e0, "\x8d\x48\xe3\x5c\xd0\xfc\x8c\x67"}, /* .H.\...g */ \
+ {0x000002e8, "\xf1\x8d\x63\x9c\x15\x01\x8c\x63"}, /* ..c....c */ \
+ {0x000002f0, "\x03\xb8\x07\x01\x99\x8e\xaa\x95"}, /* ........ */ \
+ {0x000002f8, "\x2a\x98\x23\xb0\x05\x01\xba\x97"}, /* ..#..... */ \
+ {0x00000300, "\xcd\xb7\x01\xa0\x7d\x55\x7e\x15"}, /* ....}U~. */ \
+ {0x00000308, "\x05\x05\x82\x80\x01\x47\x63\x14"}, /* .....Gc. */ \
+ {0x00000310, "\xe6\x00\x01\x45\x82\x80\xb3\x07"}, /* ...E.... */ \
+ {0x00000318, "\xe5\x00\x05\x07\xb3\x86\xe5\x00"}, /* ........ */ \
+ {0x00000320, "\x83\xc7\x07\x00\x83\xc6\xf6\xff"}, /* ........ */ \
+ {0x00000328, "\xe3\x83\xd7\xfe\x3b\x85\xd7\x40"}, /* ....;..@ */ \
+ {0x00000330, "\x82\x80\x63\xf5\xa5\x02\x93\x46"}, /* ..c....F */ \
+ {0x00000338, "\xf6\xff\x81\x47\xfd\x17\x63\x91"}, /* ...G..c. */ \
+ {0x00000340, "\xd7\x02\x82\x80\x33\x87\xf5\x00"}, /* ....3... */ \
+ {0x00000348, "\x83\x46\x07\x00\x33\x07\xf5\x00"}, /* .F..3... */ \
+ {0x00000350, "\x85\x07\x23\x00\xd7\x00\xe3\x17"}, /* ..#..... */ \
+ {0x00000358, "\xf6\xfe\x82\x80\x81\x47\xe5\xbf"}, /* .....G.. */ \
+ {0x00000360, "\x33\x07\xf6\x00\x33\x88\xe5\x00"}, /* 3...3... */ \
+ {0x00000368, "\x03\x48\x08\x00\x2a\x97\x23\x00"}, /* .H....#. */ \
+ {0x00000370, "\x07\x01\xe9\xb7\x6f\xf0\xff\xfb"}, /* ....o... */ \
+ {0x00000378, "\x2a\x96\xaa\x87\x63\x93\xc7\x00"}, /* ....c... */ \
+ {0x00000380, "\x82\x80\x85\x07\xa3\x8f\xb7\xfe"}, /* ........ */ \
+ {0x00000388, "\xd5\xbf\x82\x80\x82\x80\x00\x00"}, /* ........ */ \
+ {0x00000390, "\x43\x00\x6f\x00\x75\x00\x6c\x00"}, /* C.o.u.l. */ \
+ {0x00000398, "\x64\x00\x20\x00\x6e\x00\x6f\x00"}, /* d. .n.o. */ \
+ {0x000003a0, "\x74\x00\x20\x00\x6f\x00\x70\x00"}, /* t. .o.p. */ \
+ {0x000003a8, "\x65\x00\x6e\x00\x20\x00\x6c\x00"}, /* e.n. .l. */ \
+ {0x000003b0, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x000003b8, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x000003c0, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x000003c8, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x000003d0, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x000003e0, "\x49\x00\x6e\x00\x63\x00\x6f\x00"}, /* I.n.c.o. */ \
+ {0x000003e8, "\x72\x00\x72\x00\x65\x00\x63\x00"}, /* r.r.e.c. */ \
+ {0x000003f0, "\x74\x00\x20\x00\x69\x00\x6d\x00"}, /* t. .i.m. */ \
+ {0x000003f8, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000400, "\x62\x00\x61\x00\x73\x00\x65\x00"}, /* b.a.s.e. */ \
+ {0x00000408, "\x20\x00\x6f\x00\x72\x00\x20\x00"}, /* .o.r. . */ \
+ {0x00000410, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000418, "\x65\x00\x5f\x00\x73\x00\x69\x00"}, /* e._.s.i. */ \
+ {0x00000420, "\x7a\x00\x65\x00\x0a\x00\x00\x00"}, /* z.e..... */ \
+ {0x00000428, "\x45\x00\x46\x00\x49\x00\x20\x00"}, /* E.F.I. . */ \
+ {0x00000430, "\x61\x00\x70\x00\x70\x00\x6c\x00"}, /* a.p.p.l. */ \
+ {0x00000438, "\x69\x00\x63\x00\x61\x00\x74\x00"}, /* i.c.a.t. */ \
+ {0x00000440, "\x69\x00\x6f\x00\x6e\x00\x20\x00"}, /* i.o.n. . */ \
+ {0x00000448, "\x63\x00\x61\x00\x6c\x00\x6c\x00"}, /* c.a.l.l. */ \
+ {0x00000450, "\x69\x00\x6e\x00\x67\x00\x20\x00"}, /* i.n.g. . */ \
+ {0x00000458, "\x45\x00\x78\x00\x69\x00\x74\x00"}, /* E.x.i.t. */ \
+ {0x00000460, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000468, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000470, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000478, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000480, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000488, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000490, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000498, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x000004a0, "\x67\x00\x0a\x00\x00\x00\x00\x00"}, /* g....... */ \
+ {0x000004a8, "\x53\x00\x55\x00\x43\x00\x43\x00"}, /* S.U.C.C. */ \
+ {0x000004b0, "\x45\x00\x53\x00\x53\x00\x00\x00"}, /* E.S.S... */ \
+ {0x000004c0, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004d0, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004d8, "\xb0\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x000004e0, "\xf5\xfe\xff\x6f\x00\x00\x00\x00"}, /* ...o.... */ \
+ {0x000004e8, "\x48\x21\x00\x00\x00\x00\x00\x00"}, /* H!...... */ \
+ {0x000004f0, "\x05\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004f8, "\x00\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000500, "\x06\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000508, "\x00\x10\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000510, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000518, "\xaa\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000520, "\x0b\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000528, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000530, "\x07\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000540, "\x08\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000550, "\x09\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000558, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000560, "\x1e\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000568, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000005d0, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x000005d8, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x000005e0, "\xc0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001018, "\x00\x00\x00\x00\x03\x00\x01\x00"}, /* ........ */ \
+ {0x00001030, "\x42\x00\x00\x00\x12\x00\x01\x00"}, /* B....... */ \
+ {0x00001038, "\x8a\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001040, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001048, "\x73\x00\x00\x00\x10\x00\x01\x00"}, /* s....... */ \
+ {0x00001060, "\x3b\x00\x00\x00\x12\x00\x01\x00"}, /* ;....... */ \
+ {0x00001068, "\x78\x03\x00\x00\x00\x00\x00\x00"}, /* x....... */ \
+ {0x00001070, "\x12\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001078, "\x96\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001080, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001090, "\x1b\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001098, "\xa2\x02\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010a0, "\x6a\x00\x00\x00\x00\x00\x00\x00"}, /* j....... */ \
+ {0x000010a8, "\x25\x00\x00\x00\x12\x00\x01\x00"}, /* %....... */ \
+ {0x000010b0, "\x0c\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010b8, "\x26\x00\x00\x00\x00\x00\x00\x00"}, /* &....... */ \
+ {0x000010c0, "\x14\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010c8, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010d8, "\x5b\x00\x00\x00\x12\x00\x01\x00"}, /* [....... */ \
+ {0x000010e0, "\x8c\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010e8, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010f0, "\x9f\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010f8, "\x30\x01\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0x00001108, "\x79\x00\x00\x00\x10\x00\x01\x00"}, /* y....... */ \
+ {0x00001110, "\xc0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001120, "\x2c\x00\x00\x00\x12\x00\x01\x00"}, /* ,....... */ \
+ {0x00001128, "\x32\x03\x00\x00\x00\x00\x00\x00"}, /* 2....... */ \
+ {0x00001130, "\x42\x00\x00\x00\x00\x00\x00\x00"}, /* B....... */ \
+ {0x00001138, "\x01\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001140, "\x34\x02\x00\x00\x00\x00\x00\x00"}, /* 4....... */ \
+ {0x00001148, "\x6e\x00\x00\x00\x00\x00\x00\x00"}, /* n....... */ \
+ {0x00001150, "\x91\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001158, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001168, "\x0a\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001180, "\x80\x00\x00\x00\x10\x00\xf1\xff"}, /* ........ */ \
+ {0x00001188, "\xc0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001198, "\x34\x00\x00\x00\x12\x00\x01\x00"}, /* 4....... */ \
+ {0x000011a0, "\x74\x03\x00\x00\x00\x00\x00\x00"}, /* t....... */ \
+ {0x000011a8, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000011b0, "\x8b\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000011b8, "\xd0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00001000, { \
+ {0x00000000, "\x4d\x5a\x90\x00\x03\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000008, "\x04\x00\x00\x00\xff\xff\x00\x00"}, /* ........ */ \
+ {0x00000010, "\xb8\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000018, "\x40\x00\x00\x00\x00\x00\x00\x00"}, /* @....... */ \
+ {0x00000038, "\x00\x00\x00\x00\x80\x00\x00\x00"}, /* ........ */ \
+ {0x00000040, "\x0e\x1f\xba\x0e\x00\xb4\x09\xcd"}, /* ........ */ \
+ {0x00000048, "\x21\xb8\x01\x4c\xcd\x21\x54\x68"}, /* !..L.!Th */ \
+ {0x00000050, "\x69\x73\x20\x70\x72\x6f\x67\x72"}, /* is progr */ \
+ {0x00000058, "\x61\x6d\x20\x63\x61\x6e\x6e\x6f"}, /* am canno */ \
+ {0x00000060, "\x74\x20\x62\x65\x20\x72\x75\x6e"}, /* t be run */ \
+ {0x00000068, "\x20\x69\x6e\x20\x44\x4f\x53\x20"}, /* in DOS */ \
+ {0x00000070, "\x6d\x6f\x64\x65\x2e\x0d\x0d\x0a"}, /* mode.... */ \
+ {0x00000078, "\x24\x00\x00\x00\x00\x00\x00\x00"}, /* $....... */ \
+ {0x00000080, "\x50\x45\x00\x00\x64\x86\x05\x00"}, /* PE..d... */ \
+ {0x00000090, "\x00\x00\x00\x00\xf0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000098, "\x0b\x02\x02\x1e\x00\x04\x00\x00"}, /* ........ */ \
+ {0x000000a0, "\x00\x08\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000000a8, "\x00\x20\x00\x00\x00\x20\x00\x00"}, /* . ... .. */ \
+ {0x000000b8, "\x00\x10\x00\x00\x00\x02\x00\x00"}, /* ........ */ \
+ {0x000000d0, "\x00\x70\x00\x00\x00\x04\x00\x00"}, /* .p...... */ \
+ {0x000000d8, "\x24\xe3\x00\x00\x0a\x00\x00\x00"}, /* $....... */ \
+ {0x00000100, "\x00\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x00000130, "\x00\x30\x00\x00\x0a\x00\x00\x00"}, /* .0...... */ \
+ {0x00000188, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000190, "\x29\x02\x00\x00\x00\x20\x00\x00"}, /* ).... .. */ \
+ {0x00000198, "\x00\x04\x00\x00\x00\x04\x00\x00"}, /* ........ */ \
+ {0x000001a8, "\x00\x00\x00\x00\x20\x00\x30\x60"}, /* .... .0` */ \
+ {0x000001b0, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x000001b8, "\x0a\x00\x00\x00\x00\x30\x00\x00"}, /* .....0.. */ \
+ {0x000001c0, "\x00\x02\x00\x00\x00\x08\x00\x00"}, /* ........ */ \
+ {0x000001d0, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x000001d8, "\x2e\x64\x61\x74\x61\x00\x00\x00"}, /* .data... */ \
+ {0x000001e0, "\x38\x01\x00\x00\x00\x40\x00\x00"}, /* 8....@.. */ \
+ {0x000001e8, "\x00\x02\x00\x00\x00\x0a\x00\x00"}, /* ........ */ \
+ {0x000001f8, "\x00\x00\x00\x00\x40\x00\x50\xc0"}, /* ....@.P. */ \
+ {0x00000200, "\x2e\x64\x79\x6e\x61\x6d\x69\x63"}, /* .dynamic */ \
+ {0x00000208, "\xe0\x00\x00\x00\x00\x50\x00\x00"}, /* .....P.. */ \
+ {0x00000210, "\x00\x02\x00\x00\x00\x0c\x00\x00"}, /* ........ */ \
+ {0x00000220, "\x00\x00\x00\x00\x40\x00\x40\xc0"}, /* ....@.@. */ \
+ {0x00000228, "\x2e\x64\x79\x6e\x73\x79\x6d\x00"}, /* .dynsym. */ \
+ {0x00000230, "\x48\x00\x00\x00\x00\x60\x00\x00"}, /* H....`.. */ \
+ {0x00000238, "\x00\x02\x00\x00\x00\x0e\x00\x00"}, /* ........ */ \
+ {0x00000248, "\x00\x00\x00\x00\x40\x00\x40\x40"}, /* ....@.@@ */ \
+ {0x00000400, "\x48\x83\xec\x08\x51\x52\x48\x8d"}, /* H...QRH. */ \
+ {0x00000408, "\x0d\xf3\xdf\xff\xff\x48\x8d\x15"}, /* .....H.. */ \
+ {0x00000410, "\xec\x2f\x00\x00\xe8\x24\x01\x00"}, /* ./...$.. */ \
+ {0x00000418, "\x00\x5a\x59\x48\x85\xc0\x75\x05"}, /* .ZYH..u. */ \
+ {0x00000420, "\xe8\x8f\x00\x00\x00\x48\x83\xc4"}, /* .....H.. */ \
+ {0x00000428, "\x08\xc3\x56\x45\x31\xc9\x53\x48"}, /* ..VE1.SH */ \
+ {0x00000430, "\x83\xec\x48\x48\x8b\x42\x60\x48"}, /* ..HH.B`H */ \
+ {0x00000438, "\x8b\x5a\x40\x4c\x8d\x44\x24\x38"}, /* .Z@L.D$8 */ \
+ {0x00000440, "\xc7\x44\x24\x28\x02\x00\x00\x00"}, /* .D$(.... */ \
+ {0x00000448, "\x48\xc7\x44\x24\x20\x00\x00\x00"}, /* H.D$ ... */ \
+ {0x00000450, "\x00\x48\x8d\x15\xc8\x20\x00\x00"}, /* .H... .. */ \
+ {0x00000458, "\xff\x90\x18\x01\x00\x00\x48\x85"}, /* ......H. */ \
+ {0x00000460, "\xc0\x48\x89\xc6\x74\x0f\x48\x8d"}, /* .H..t.H. */ \
+ {0x00000468, "\x15\x95\x1f\x00\x00\x48\x89\xd9"}, /* .....H.. */ \
+ {0x00000470, "\xff\x53\x08\xeb\x35\x48\x8b\x4c"}, /* .S..5H.L */ \
+ {0x00000478, "\x24\x38\x48\x8d\x15\xa9\xff\xff"}, /* $8H..... */ \
+ {0x00000480, "\xff\x48\x8b\x41\x40\x48\x39\xd0"}, /* .H.A@H9. */ \
+ {0x00000488, "\x77\x09\x48\x03\x41\x48\x48\x39"}, /* w.H.AHH9 */ \
+ {0x00000490, "\xd0\x77\x17\x48\x8d\x15\xb2\x1f"}, /* .w.H.... */ \
+ {0x00000498, "\x00\x00\x48\x89\xd9\x48\xbe\x0e"}, /* ..H..H.. */ \
+ {0x000004a0, "\x00\x00\x00\x00\x00\x00\x80\xff"}, /* ........ */ \
+ {0x000004a8, "\x53\x08\x48\x83\xc4\x48\x48\x89"}, /* S.H..HH. */ \
+ {0x000004b0, "\xf0\x5b\x5e\xc3\x57\x48\x89\xcf"}, /* .[^.WH.. */ \
+ {0x000004b8, "\x56\x48\x89\xd6\x53\x48\x83\xec"}, /* VH..SH.. */ \
+ {0x000004c0, "\x30\x48\x8b\x5a\x40\x48\x8b\x05"}, /* 0H.Z@H.. */ \
+ {0x000004c8, "\x42\x20\x00\x00\x48\x8b\x15\x43"}, /* B ..H..C */ \
+ {0x000004d0, "\x20\x00\x00\x48\x89\xd9\x48\x89"}, /* ..H..H. */ \
+ {0x000004d8, "\x44\x24\x20\x48\x89\x54\x24\x28"}, /* D$ H.T$( */ \
+ {0x000004e0, "\x48\x8d\x15\xad\x1f\x00\x00\xff"}, /* H....... */ \
+ {0x000004e8, "\x53\x08\x48\x89\xf2\x48\x89\xf9"}, /* S.H..H.. */ \
+ {0x000004f0, "\xe8\x35\xff\xff\xff\x48\xba\x03"}, /* .5...H.. */ \
+ {0x000004f8, "\x00\x00\x00\x00\x00\x00\x80\x48"}, /* .......H */ \
+ {0x00000500, "\x85\xc0\x74\x17\x48\x8d\x15\xc5"}, /* ..t.H... */ \
+ {0x00000508, "\x1f\x00\x00\x48\x89\xd9\xff\x53"}, /* ...H...S */ \
+ {0x00000510, "\x08\x48\xba\x0e\x00\x00\x00\x00"}, /* .H...... */ \
+ {0x00000518, "\x00\x00\x80\x48\x8b\x46\x60\x4c"}, /* ...H.F`L */ \
+ {0x00000520, "\x8d\x4c\x24\x20\x48\x89\xf9\x41"}, /* .L$ H..A */ \
+ {0x00000528, "\xb8\x10\x00\x00\x00\xff\x90\xd8"}, /* ........ */ \
+ {0x00000530, "\x00\x00\x00\x48\x83\xc4\x30\x31"}, /* ...H..01 */ \
+ {0x00000538, "\xc0\x5b\x5e\x5f\xc3\x48\x83\xc2"}, /* .[^_.H.. */ \
+ {0x00000540, "\x08\x31\xc0\x45\x31\xc9\x45\x31"}, /* .1.E1.E1 */ \
+ {0x00000548, "\xc0\x4c\x8b\x52\xf8\x4d\x85\xd2"}, /* .L.R.M.. */ \
+ {0x00000550, "\x74\x28\x49\x83\xfa\x08\x74\x14"}, /* t(I...t. */ \
+ {0x00000558, "\x49\x83\xfa\x09\x74\x13\x49\x83"}, /* I...t.I. */ \
+ {0x00000560, "\xfa\x07\x75\x10\x48\x8b\x02\x48"}, /* ..u.H..H */ \
+ {0x00000568, "\x01\xc8\xeb\x08\x4c\x8b\x02\xeb"}, /* ....L... */ \
+ {0x00000570, "\x03\x4c\x8b\x0a\x48\x83\xc2\x10"}, /* .L..H... */ \
+ {0x00000578, "\xeb\xcf\x48\x85\xc0\x41\x0f\x94"}, /* ..H..A.. */ \
+ {0x00000580, "\xc2\x4d\x85\xc9\x0f\x94\xc2\x45"}, /* .M.....E */ \
+ {0x00000588, "\x84\xd2\x74\x07\x84\xd2\x74\x23"}, /* ..t...t# */ \
+ {0x00000590, "\x31\xc0\xc3\x84\xd2\x75\x1c\x4d"}, /* 1....u.M */ \
+ {0x00000598, "\x85\xc0\x7e\xf4\x83\x78\x08\x08"}, /* ..~..x.. */ \
+ {0x000005a0, "\x75\x09\x48\x8b\x10\x48\x01\xca"}, /* u.H..H.. */ \
+ {0x000005a8, "\x48\x01\x0a\x4c\x01\xc8\x4d\x29"}, /* H..L..M) */ \
+ {0x000005b0, "\xc8\xeb\xe4\x48\xb8\x01\x00\x00"}, /* ...H.... */ \
+ {0x000005b8, "\x00\x00\x00\x00\x80\xc3\x31\xc9"}, /* ......1. */ \
+ {0x000005c0, "\x48\x39\xca\x74\x16\x0f\xb6\x04"}, /* H9.t.... */ \
+ {0x000005c8, "\x0f\x48\xff\xc1\x44\x0f\xb6\x44"}, /* .H..D..D */ \
+ {0x000005d0, "\x0e\xff\x44\x38\xc0\x74\xe9\x44"}, /* ..D8.t.D */ \
+ {0x000005d8, "\x29\xc0\xc3\x31\xc0\xc3\x48\x39"}, /* )..1..H9 */ \
+ {0x000005e0, "\xf7\x48\x89\xf8\x77\x15\x31\xc9"}, /* .H..w.1. */ \
+ {0x000005e8, "\x48\x39\xca\x74\x0d\x40\x8a\x3c"}, /* H9.t.@.< */ \
+ {0x000005f0, "\x0e\x40\x88\x3c\x08\x48\xff\xc1"}, /* .@.<.H.. */ \
+ {0x000005f8, "\xeb\xee\xc3\x48\x85\xd2\x74\x0d"}, /* ...H..t. */ \
+ {0x00000600, "\x8a\x4c\x16\xff\x88\x4c\x10\xff"}, /* .L...L.. */ \
+ {0x00000608, "\x48\xff\xca\xeb\xee\xc3\xe9\xcb"}, /* H....... */ \
+ {0x00000610, "\xff\xff\xff\x48\x89\xf8\x31\xc9"}, /* ...H..1. */ \
+ {0x00000618, "\x48\x39\xca\x74\x09\x40\x88\x34"}, /* H9.t.@.4 */ \
+ {0x00000620, "\x08\x48\xff\xc1\xeb\xf2\xc3\xc3"}, /* .H...... */ \
+ {0x00000628, "\xc3\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000800, "\x30\x11\x00\x00\x0a\x00\x00\x00"}, /* 0....... */ \
+ {0x00000a00, "\x00\x00\x43\x00\x6f\x00\x75\x00"}, /* ..C.o.u. */ \
+ {0x00000a08, "\x6c\x00\x64\x00\x20\x00\x6e\x00"}, /* l.d. .n. */ \
+ {0x00000a10, "\x6f\x00\x74\x00\x20\x00\x6f\x00"}, /* o.t. .o. */ \
+ {0x00000a18, "\x70\x00\x65\x00\x6e\x00\x20\x00"}, /* p.e.n. . */ \
+ {0x00000a20, "\x6c\x00\x6f\x00\x61\x00\x64\x00"}, /* l.o.a.d. */ \
+ {0x00000a28, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000a30, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000a38, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000a40, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000a48, "\x6c\x00\x00\x00\x49\x00\x6e\x00"}, /* l...I.n. */ \
+ {0x00000a50, "\x63\x00\x6f\x00\x72\x00\x72\x00"}, /* c.o.r.r. */ \
+ {0x00000a58, "\x65\x00\x63\x00\x74\x00\x20\x00"}, /* e.c.t. . */ \
+ {0x00000a60, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000a68, "\x65\x00\x5f\x00\x62\x00\x61\x00"}, /* e._.b.a. */ \
+ {0x00000a70, "\x73\x00\x65\x00\x20\x00\x6f\x00"}, /* s.e. .o. */ \
+ {0x00000a78, "\x72\x00\x20\x00\x69\x00\x6d\x00"}, /* r. .i.m. */ \
+ {0x00000a80, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000a88, "\x73\x00\x69\x00\x7a\x00\x65\x00"}, /* s.i.z.e. */ \
+ {0x00000a90, "\x0a\x00\x00\x00\x45\x00\x46\x00"}, /* ....E.F. */ \
+ {0x00000a98, "\x49\x00\x20\x00\x61\x00\x70\x00"}, /* I. .a.p. */ \
+ {0x00000aa0, "\x70\x00\x6c\x00\x69\x00\x63\x00"}, /* p.l.i.c. */ \
+ {0x00000aa8, "\x61\x00\x74\x00\x69\x00\x6f\x00"}, /* a.t.i.o. */ \
+ {0x00000ab0, "\x6e\x00\x20\x00\x63\x00\x61\x00"}, /* n. .c.a. */ \
+ {0x00000ab8, "\x6c\x00\x6c\x00\x69\x00\x6e\x00"}, /* l.l.i.n. */ \
+ {0x00000ac0, "\x67\x00\x20\x00\x45\x00\x78\x00"}, /* g. .E.x. */ \
+ {0x00000ac8, "\x69\x00\x74\x00\x0a\x00\x00\x00"}, /* i.t..... */ \
+ {0x00000ad0, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000ad8, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000ae0, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000ae8, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000af0, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000af8, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000b00, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x00000b08, "\x67\x00\x0a\x00\x00\x00\x53\x00"}, /* g.....S. */ \
+ {0x00000b10, "\x55\x00\x43\x00\x43\x00\x45\x00"}, /* U.C.C.E. */ \
+ {0x00000b18, "\x53\x00\x53\x00\x00\x00\x00\x00"}, /* S.S..... */ \
+ {0x00000b20, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000b28, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000c00, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c10, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c20, "\xf5\xfe\xff\x6f\x00\x00\x00\x00"}, /* ...o.... */ \
+ {0x00000c28, "\x00\x80\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c30, "\x05\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c38, "\x00\x70\x00\x00\x00\x00\x00\x00"}, /* .p...... */ \
+ {0x00000c40, "\x06\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c48, "\x00\x60\x00\x00\x00\x00\x00\x00"}, /* .`...... */ \
+ {0x00000c50, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c58, "\x13\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c60, "\x0b\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c68, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c70, "\x1e\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c78, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000e18, "\x01\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00000e20, "\x00\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000e30, "\x08\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0, NULL} } }
#include <efi_selftest.h>
#include <efi_tcg2.h>
+/*
+ * Include containing the miniapp.efi application.
+ * Note that tcg2 selftest measures the PE/COFF image,
+ * so we must have the pre-build efi application for
+ * each architecture.
+ */
+#if defined(__arm__)
+#include "efi_miniapp_tcg2_arm.h"
+#elif defined(__aarch64__)
+#include "efi_miniapp_tcg2_arm64.h"
+#elif defined(__i386__)
+#include "efi_miniapp_tcg2_ia32.h"
+#elif defined(__x86_64__)
+#include "efi_miniapp_tcg2_x86_64.h"
+#elif defined(__riscv) && (__riscv_xlen == 32)
+#include "efi_miniapp_tcg2_riscv32.h"
+#elif defined(__riscv) && (__riscv_xlen == 64)
+#include "efi_miniapp_tcg2_riscv64.h"
+#endif
+
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <mapmem.h>
+#include <smbios.h>
+#include <tables_csum.h>
static struct efi_boot_services *boottime;
static const efi_guid_t guid_tcg2 = EFI_TCG2_PROTOCOL_GUID;
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+static efi_handle_t image_handle;
+/* Decompressed file image */
+static u8 *image;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+static struct efi_tcg2_event *efi_tcg2_event;
+
+static struct efi_runtime_services *runtime;
+#define BOOT_NAME_1000 u"Boot1000"
+#define BOOT_NAME_1001 u"Boot1001"
+#define BOOT_NAME_1002 u"Boot1002"
+
+#define DEFAULT_ATTR (EFI_VARIABLE_NON_VOLATILE | \
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+ EFI_VARIABLE_RUNTIME_ACCESS)
+
+/* "efidebug boot add -b 1000 test1000 virtio 0:1 /EFI/debian/grubaa64.efi" */
+static const u8 boot_1000[] = {
+0x01, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x74, 0x00, 0x65, 0x00, 0x73, 0x00,
+0x74, 0x00, 0x30, 0x00, 0x00, 0x00, 0x01, 0x04, 0x14, 0x00, 0xb9, 0x73,
+0x1d, 0xe6, 0x84, 0xa3, 0xcc, 0x4a, 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3,
+0x62, 0x8b, 0x01, 0x04, 0x15, 0x00, 0x92, 0x37, 0x29, 0x63, 0xf5, 0xad,
+0x25, 0x93, 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e, 0x00, 0x04,
+0x01, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+0x5a, 0x47, 0xc2, 0x35, 0x27, 0x44, 0x47, 0x9f, 0x01, 0x67, 0xfe, 0xfa,
+0x1d, 0x06, 0xae, 0x02, 0x02, 0x04, 0x04, 0x36, 0x00, 0x5c, 0x00, 0x45,
+0x00, 0x46, 0x00, 0x49, 0x00, 0x5c, 0x00, 0x64, 0x00, 0x65, 0x00, 0x62,
+0x00, 0x69, 0x00, 0x61, 0x00, 0x6e, 0x00, 0x5c, 0x00, 0x67, 0x00, 0x72,
+0x00, 0x75, 0x00, 0x62, 0x00, 0x61, 0x00, 0x61, 0x00, 0x36, 0x00, 0x34,
+0x00, 0x2e, 0x00, 0x65, 0x00, 0x66, 0x00, 0x69, 0x00, 0x00, 0x00, 0x7f,
+0xff, 0x04, 0x00 };
+
+/* "efidebug boot add -b 1001 test1001 virtio 0:1 /EFI/debian/grubaa64.efi" */
+static const u8 boot_1001[] = {
+0x01, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x74, 0x00, 0x65, 0x00, 0x73, 0x00,
+0x74, 0x00, 0x31, 0x00, 0x00, 0x00, 0x01, 0x04, 0x14, 0x00, 0xb9, 0x73,
+0x1d, 0xe6, 0x84, 0xa3, 0xcc, 0x4a, 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3,
+0x62, 0x8b, 0x01, 0x04, 0x15, 0x00, 0x92, 0x37, 0x29, 0x63, 0xf5, 0xad,
+0x25, 0x93, 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e, 0x00, 0x04,
+0x01, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+0x5a, 0x47, 0xc2, 0x35, 0x27, 0x44, 0x47, 0x9f, 0x01, 0x67, 0xfe, 0xfa,
+0x1d, 0x06, 0xae, 0x02, 0x02, 0x04, 0x04, 0x36, 0x00, 0x5c, 0x00, 0x45,
+0x00, 0x46, 0x00, 0x49, 0x00, 0x5c, 0x00, 0x64, 0x00, 0x65, 0x00, 0x62,
+0x00, 0x69, 0x00, 0x61, 0x00, 0x6e, 0x00, 0x5c, 0x00, 0x67, 0x00, 0x72,
+0x00, 0x75, 0x00, 0x62, 0x00, 0x61, 0x00, 0x61, 0x00, 0x36, 0x00, 0x34,
+0x00, 0x2e, 0x00, 0x65, 0x00, 0x66, 0x00, 0x69, 0x00, 0x00, 0x00, 0x7f,
+0xff, 0x04, 0x00 };
+
+/* "efidebug boot add -b 1002 test1002 virtio 0:1 /EFI/debian/grubaa64.efi" */
+static const u8 boot_1002[] = {
+0x01, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x74, 0x00, 0x65, 0x00, 0x73, 0x00,
+0x74, 0x00, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x14, 0x00, 0xb9, 0x73,
+0x1d, 0xe6, 0x84, 0xa3, 0xcc, 0x4a, 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3,
+0x62, 0x8b, 0x01, 0x04, 0x15, 0x00, 0x92, 0x37, 0x29, 0x63, 0xf5, 0xad,
+0x25, 0x93, 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e, 0x00, 0x04,
+0x01, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+0x5a, 0x47, 0xc2, 0x35, 0x27, 0x44, 0x47, 0x9f, 0x01, 0x67, 0xfe, 0xfa,
+0x1d, 0x06, 0xae, 0x02, 0x02, 0x04, 0x04, 0x36, 0x00, 0x5c, 0x00, 0x45,
+0x00, 0x46, 0x00, 0x49, 0x00, 0x5c, 0x00, 0x64, 0x00, 0x65, 0x00, 0x62,
+0x00, 0x69, 0x00, 0x61, 0x00, 0x6e, 0x00, 0x5c, 0x00, 0x67, 0x00, 0x72,
+0x00, 0x75, 0x00, 0x62, 0x00, 0x61, 0x00, 0x61, 0x00, 0x36, 0x00, 0x34,
+0x00, 0x2e, 0x00, 0x65, 0x00, 0x66, 0x00, 0x69, 0x00, 0x00, 0x00, 0x7f,
+0xff, 0x04, 0x00};
+
+/* "efidebug boot order 1002 1000 1001" */
+static u8 boot_order[] = {0x02, 0x10, 0x00, 0x10, 0x01, 0x10};
+
+static void *orig_smbios_table;
+static u64 dmi_addr = U32_MAX;
+#define SMBIOS_ENTRY_HEADER_SIZE 0x20
+/* smbios table for the measurement test */
+static u8 smbios_table_test[] = {
+0x5f, 0x53, 0x4d, 0x5f, 0x2c, 0x1f, 0x03, 0x00, 0x54, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xe4, 0x5c, 0x01,
+0x20, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
+0x01, 0x02, 0x00, 0x00, 0x03, 0x00, 0x80, 0x08, 0x01, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x0c, 0x15, 0x0a, 0xff, 0xff, 0x55, 0x2d, 0x42, 0x6f,
+0x6f, 0x74, 0x00, 0x32, 0x30, 0x32, 0x31, 0x2e, 0x31, 0x30, 0x2d, 0x72,
+0x63, 0x34, 0x2d, 0x30, 0x30, 0x30, 0x30, 0x35, 0x2d, 0x67, 0x37, 0x32,
+0x37, 0x63, 0x33, 0x66, 0x33, 0x32, 0x35, 0x39, 0x2d, 0x64, 0x69, 0x72,
+0x74, 0x79, 0x00, 0x31, 0x30, 0x2f, 0x30, 0x31, 0x2f, 0x32, 0x30, 0x32,
+0x31, 0x00, 0x00, 0x01, 0x1b, 0x01, 0x00, 0x01, 0x02, 0x00, 0x03, 0x31,
+0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77,
+0x6e, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x20, 0x50, 0x72,
+0x6f, 0x64, 0x75, 0x63, 0x74, 0x00, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+0x37, 0x38, 0x00, 0x00, 0x02, 0x0e, 0x02, 0x00, 0x01, 0x02, 0x00, 0x04,
+0x03, 0x01, 0x01, 0x01, 0x00, 0x0a, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77,
+0x6e, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x20, 0x50, 0x72,
+0x6f, 0x64, 0x75, 0x63, 0x74, 0x00, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x00, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x00,
+0x00, 0x03, 0x15, 0x03, 0x00, 0x01, 0x03, 0x00, 0x02, 0x03, 0x03, 0x03,
+0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x6e,
+0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x00, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+0x37, 0x38, 0x00, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x00,
+0x00, 0x04, 0x30, 0x04, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x01, 0x06, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x02, 0x03, 0x04,
+0x04, 0x04, 0x08, 0x00, 0x00, 0x02, 0x00, 0x08, 0x00, 0x08, 0x00, 0x01,
+0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x00, 0x31, 0x32, 0x33,
+0x34, 0x35, 0x36, 0x37, 0x38, 0x00, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x00, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x00,
+0x00, 0x20, 0x0b, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x7f, 0x04, 0x06, 0x00, 0x00, 0x00
+};
+
+#define IDX_ARRAY_SZ 3 /* support 24 PCRs */
+#define TPM2_CMD_BUF_SIZE 64
+/* TPM command is big endian */
+#define __MSB(x) ((x) >> 8)
+#define __LSB(x) ((x) & 0xFF)
+#define tpm_u16(x) __MSB(x), __LSB(x)
+#define tpm_u32(x) tpm_u16((x) >> 16), tpm_u16((x) & 0xFFFF)
+#define TPM2_PCR_READ_HEADER_SIZE 30
+
+static u8 (*pcrs)[TPM2_SHA256_DIGEST_SIZE];
+static u8 expected_pcrs[EFI_TCG2_MAX_PCR_INDEX + 1][TPM2_SHA256_DIGEST_SIZE] = {
+ {0x91, 0x21, 0x37, 0xc7, 0x1a, 0x49, 0x19, 0xc8,
+ 0xf1, 0xfb, 0xa9, 0x84, 0x5c, 0x65, 0xa9, 0xdd,
+ 0x7b, 0xb9, 0xfe, 0xa1, 0xcd, 0x64, 0x49, 0xdd,
+ 0xed, 0xe2, 0x65, 0x82, 0xc5, 0x3e, 0xf4, 0xc4},
+
+ {0xf5, 0x79, 0xf3, 0x20, 0x62, 0x6e, 0x8b, 0x58,
+ 0x62, 0xa3, 0x4e, 0x2f, 0xb7, 0x10, 0xac, 0x34,
+ 0x4e, 0x68, 0x94, 0x37, 0x87, 0x29, 0xc4, 0xbe,
+ 0xa3, 0xc4, 0xd9, 0x14, 0x2b, 0x66, 0x79, 0x9b},
+
+ {0x3d, 0x45, 0x8c, 0xfe, 0x55, 0xcc, 0x03, 0xea,
+ 0x1f, 0x44, 0x3f, 0x15, 0x62, 0xbe, 0xec, 0x8d,
+ 0xf5, 0x1c, 0x75, 0xe1, 0x4a, 0x9f, 0xcf, 0x9a,
+ 0x72, 0x34, 0xa1, 0x3f, 0x19, 0x8e, 0x79, 0x69},
+
+ {0x3d, 0x45, 0x8c, 0xfe, 0x55, 0xcc, 0x03, 0xea,
+ 0x1f, 0x44, 0x3f, 0x15, 0x62, 0xbe, 0xec, 0x8d,
+ 0xf5, 0x1c, 0x75, 0xe1, 0x4a, 0x9f, 0xcf, 0x9a,
+ 0x72, 0x34, 0xa1, 0x3f, 0x19, 0x8e, 0x79, 0x69},
+
+ /* PCR[4] is different per architecture */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x3d, 0x45, 0x8c, 0xfe, 0x55, 0xcc, 0x03, 0xea,
+ 0x1f, 0x44, 0x3f, 0x15, 0x62, 0xbe, 0xec, 0x8d,
+ 0xf5, 0x1c, 0x75, 0xe1, 0x4a, 0x9f, 0xcf, 0x9a,
+ 0x72, 0x34, 0xa1, 0x3f, 0x19, 0x8e, 0x79, 0x69},
+
+ /* PCR[6] is different per architecture */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x96, 0x74, 0xae, 0xcd, 0x3f, 0x40, 0xb4, 0xa9,
+ 0x36, 0xae, 0x19, 0xc8, 0x84, 0x8a, 0xb9, 0x5a,
+ 0x87, 0x99, 0xd8, 0x89, 0x7f, 0xfc, 0x40, 0x48,
+ 0x05, 0x99, 0x65, 0x2e, 0x55, 0xd4, 0x93, 0x32},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+};
+
+/*
+ * PCR[4] and PCR[6] have the PE/COFF image measurement,
+ * this PCRs have different value in each architecture.
+ */
+#if defined(__arm__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0xcd, 0xa2, 0x06, 0xad, 0x83, 0x9b, 0x8f, 0x92,
+ 0x01, 0xf9, 0xc8, 0x3d, 0xc9, 0x54, 0x66, 0xb3,
+ 0x97, 0x35, 0x88, 0xe1, 0xea, 0xd3, 0x1a, 0xd6,
+ 0x56, 0xee, 0x43, 0x1c, 0xdb, 0x4b, 0xf9, 0x1f},
+ /* PCR[6] */
+ {0x9c, 0xb8, 0x9d, 0x4a, 0xf6, 0x63, 0x95, 0xb0,
+ 0x95, 0xfe, 0x44, 0x30, 0x0f, 0x3a, 0x0b, 0x7c,
+ 0xef, 0xc7, 0xb6, 0x6a, 0x59, 0xae, 0xcb, 0xf6,
+ 0xbd, 0x2d, 0xb5, 0xb9, 0xb4, 0x95, 0x7d, 0xaf}
+};
+#elif defined(__aarch64__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x69, 0xdb, 0x01, 0x5e, 0x07, 0xed, 0x9c, 0xbb,
+ 0x27, 0x65, 0xb1, 0xf0, 0x7b, 0x04, 0xbc, 0x31,
+ 0xd1, 0xec, 0x00, 0xe4, 0xe1, 0x49, 0xdb, 0x1e,
+ 0x8b, 0x2d, 0xa2, 0x26, 0xb5, 0x8d, 0x07, 0xe2},
+ /* PCR[6] */
+ {0x53, 0x1b, 0x27, 0xb2, 0x6f, 0x2d, 0xab, 0x9b,
+ 0x6f, 0xbc, 0xd1, 0x8f, 0xc9, 0x14, 0x48, 0xe7,
+ 0x6d, 0x1b, 0xfb, 0x1b, 0x53, 0xc5, 0x8e, 0xf4,
+ 0x41, 0x50, 0x79, 0x24, 0x66, 0x57, 0x7b, 0xf8}
+};
+#elif defined(__i386__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0xec, 0x5e, 0xdb, 0x68, 0x13, 0x48, 0x36, 0x0a,
+ 0x3a, 0xbc, 0x7b, 0x7b, 0xbc, 0x74, 0x7a, 0xa5,
+ 0x55, 0xea, 0xb9, 0x09, 0x6a, 0x6e, 0xc3, 0x21,
+ 0x51, 0x46, 0x22, 0xd2, 0x9d, 0xc9, 0xd5, 0x6a},
+ /* PCR[6] */
+ {0x26, 0x14, 0xe7, 0xde, 0x91, 0xd1, 0xf3, 0xde,
+ 0x7a, 0xc2, 0x78, 0xaf, 0x4b, 0x2e, 0x05, 0x9d,
+ 0x35, 0x17, 0xee, 0xcc, 0x0e, 0x77, 0x8d, 0x3f,
+ 0x7e, 0x20, 0x75, 0xfa, 0xbc, 0xbc, 0x24, 0x3e}
+};
+#elif defined(__x86_64__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x9a, 0x75, 0x99, 0x8b, 0x74, 0x45, 0xb6, 0x26,
+ 0x50, 0xe0, 0xbb, 0xfa, 0x2a, 0xa6, 0x19, 0xec,
+ 0x97, 0x12, 0x0c, 0xb5, 0xc8, 0x2a, 0xfe, 0xe5,
+ 0x29, 0xc8, 0xd3, 0x98, 0xe9, 0xd1, 0x9d, 0xd5},
+ /* PCR[6] */
+ {0xa2, 0xa2, 0xd3, 0xa7, 0x84, 0xc2, 0x95, 0x2a,
+ 0xab, 0x6f, 0xe7, 0xe8, 0x86, 0x9f, 0x99, 0xc6,
+ 0x6a, 0x8c, 0xcc, 0x5c, 0xb8, 0x83, 0xfa, 0x86,
+ 0x56, 0x5e, 0x91, 0x17, 0x0b, 0x5f, 0x54, 0xa8}
+};
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x64, 0xe9, 0x25, 0xb3, 0xd8, 0x33, 0xb3, 0x1b,
+ 0x74, 0x0c, 0x81, 0x45, 0xef, 0x61, 0xf1, 0x87,
+ 0xef, 0x65, 0x67, 0x28, 0x1a, 0x54, 0x97, 0xb2,
+ 0xd3, 0x62, 0x00, 0xe7, 0xb6, 0x7a, 0xd5, 0x8e},
+ /* PCR[6] */
+ {0x82, 0xab, 0xc5, 0x6a, 0xbf, 0x08, 0x43, 0x3f,
+ 0x85, 0xbd, 0x8f, 0x8e, 0x23, 0x62, 0x48, 0x4a,
+ 0x44, 0x53, 0xf0, 0xae, 0x8d, 0x4c, 0xda, 0x04,
+ 0x89, 0x9c, 0x0b, 0x81, 0x3a, 0x53, 0xf3, 0xac}
+};
+#elif defined(__riscv) && (__riscv_xlen == 64)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x9b, 0x5f, 0x10, 0x24, 0x28, 0x5d, 0x7d, 0x1f,
+ 0x9f, 0xee, 0xe9, 0x90, 0xf1, 0x7a, 0x03, 0xb1,
+ 0x68, 0x7b, 0x28, 0x45, 0x98, 0x5e, 0xf5, 0x5e,
+ 0xc1, 0x22, 0x61, 0x8c, 0x2f, 0xb5, 0xbf, 0x80},
+ /* PCR[6] */
+ {0x6d, 0x16, 0x17, 0xf4, 0x9a, 0xa8, 0x49, 0xc2,
+ 0xf4, 0x9c, 0x35, 0x30, 0x0c, 0xde, 0x65, 0xdb,
+ 0xd3, 0x37, 0x9c, 0xe2, 0x9f, 0x14, 0x81, 0x74,
+ 0xc3, 0x94, 0x8a, 0x9e, 0x26, 0xbf, 0xfb, 0xb2}
+};
+#endif
+
+struct boot_variable {
+ u16 name[16];
+ u8 *buf;
+ efi_uintn_t size;
+ u32 attr;
+ const u8 *test_data;
+ efi_uintn_t test_data_size;
+};
+
+static struct boot_variable boot_variable_test[] = {
+ {u"BootOrder", NULL, 0, DEFAULT_ATTR, boot_order, sizeof(boot_order)},
+ {BOOT_NAME_1000, NULL, 0, DEFAULT_ATTR, boot_1000, sizeof(boot_1000)},
+ {BOOT_NAME_1001, NULL, 0, DEFAULT_ATTR, boot_1001, sizeof(boot_1001)},
+ {BOOT_NAME_1002, NULL, 0, DEFAULT_ATTR, boot_1002, sizeof(boot_1002)},
+};
+
+/*
+ * efi_status_t decompress() - Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+/*
+ * efi_status_t setup_boot_variable() - configure dummy boot variables
+ *
+ * Preexisting variable values are saved and will be restored by
+ * calling restore_boot_variable().
+ *
+ * @return status code
+ */
+static efi_status_t setup_boot_variable(void)
+{
+ efi_status_t ret;
+ u32 i;
+ efi_uintn_t size;
+
+ for (i = 0; i < ARRAY_SIZE(boot_variable_test); i++) {
+ size = 0;
+ ret = runtime->get_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ &boot_variable_test[i].attr,
+ &size,
+ NULL);
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ /* Variable exists, save the current value */
+ boot_variable_test[i].size = size;
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ boot_variable_test[i].size,
+ (void **)&boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to allocate buffer for boot variable\n");
+ return ret;
+ }
+ ret = runtime->get_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ &boot_variable_test[i].attr,
+ &boot_variable_test[i].size,
+ boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get current boot variable\n");
+ return ret;
+ }
+ }
+
+ /* set boot variable for the measurement test */
+ ret = runtime->set_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ boot_variable_test[i].attr,
+ boot_variable_test[i].test_data_size,
+ boot_variable_test[i].test_data);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to set test boot variable(%d)n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * efi_status_t restore_boot_variable() - restore original values
+ *
+ * Restore the variable values saved in setup_boot_variable().
+ *
+ * @return status code
+ */
+static efi_status_t restore_boot_variable(void)
+{
+ int i;
+ efi_status_t ret;
+
+ for (i = 0; i < ARRAY_SIZE(boot_variable_test); i++) {
+ if (boot_variable_test[i].buf) {
+ ret = runtime->set_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ boot_variable_test[i].attr,
+ boot_variable_test[i].size,
+ boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to restore boot variable\n");
+ return ret;
+ }
+ ret = boottime->free_pool(boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free boot variable\n");
+ return ret;
+ }
+ } else {
+ /* delete the variable used only for testing */
+ ret = runtime->set_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ 0, 0, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to delete boot variable\n");
+ return ret;
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * void *find_smbios_table() - Find smbios table
+ *
+ * @systable system table
+ * @return status code
+ */
+static void *find_smbios_table(const struct efi_system_table *systable)
+{
+ u32 i;
+
+ for (i = 0; i < systable->nr_tables; i++) {
+ if (!guidcmp(&smbios_guid, &systable->tables[i].guid))
+ return systable->tables[i].table;
+ }
+
+ return NULL;
+}
+
+/**
+ * efi_status_t setup_smbios_table() - Prepare the dummy SMBIOS table
+ *
+ * @systable system table
+ * @return status code
+ */
+static efi_status_t setup_smbios_table(const struct efi_system_table *systable)
+{
+ struct smbios_entry *se;
+ efi_status_t ret;
+ /* Map within the low 32 bits, to allow for 32bit SMBIOS tables */
+ void *dmi;
+ char *istart;
+ int isize;
+
+ if (sizeof(smbios_table_test) > EFI_PAGE_SIZE)
+ return EFI_OUT_OF_RESOURCES;
+
+ orig_smbios_table = find_smbios_table(systable);
+
+ /* Reserve 4kiB page for SMBIOS */
+ ret = boottime->allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RUNTIME_SERVICES_DATA, 1, &dmi_addr);
+
+ if (ret != EFI_SUCCESS) {
+ /* Could not find space in lowmem, use highmem instead */
+ ret = boottime->allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_RUNTIME_SERVICES_DATA, 1,
+ &dmi_addr);
+
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+
+ dmi = (void *)(uintptr_t)dmi_addr;
+ se = dmi;
+ boottime->copy_mem(se, smbios_table_test, sizeof(smbios_table_test));
+
+ /* update smbios table start address */
+ se->struct_table_address = (uintptr_t)((u8 *)dmi + SMBIOS_ENTRY_HEADER_SIZE);
+
+ /* calculate checksums */
+ istart = (char *)se + SMBIOS_INTERMEDIATE_OFFSET;
+ isize = sizeof(struct smbios_entry) - SMBIOS_INTERMEDIATE_OFFSET;
+ se->intermediate_checksum = table_compute_checksum(istart, isize);
+ se->checksum = table_compute_checksum(se, sizeof(struct smbios_entry));
+
+ /* Install SMBIOS information as configuration table */
+ ret = boottime->install_configuration_table(&smbios_guid, dmi);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot install SMBIOS table\n");
+ boottime->free_pages(dmi_addr, 1);
+ }
+
+ return ret;
+}
+
/**
* efi_st_tcg2_setup() - setup test
*
static int efi_st_tcg2_setup(const efi_handle_t img_handle,
const struct efi_system_table *systable)
{
+ efi_status_t ret;
+ struct uefi_image_load_event image_load_event;
+
+ image_handle = img_handle;
boottime = systable->boottime;
+ runtime = systable->runtime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ sizeof(struct efi_tcg2_event) +
+ sizeof(struct uefi_image_load_event),
+ (void **)&efi_tcg2_event);
+ if (!efi_tcg2_event)
+ return EFI_ST_FAILURE;
+
+ efi_tcg2_event->size = sizeof(struct efi_tcg2_event) +
+ sizeof(struct uefi_image_load_event);
+ efi_tcg2_event->header.header_size = sizeof(struct efi_tcg2_event_header);
+ efi_tcg2_event->header.header_version = 1;
+ efi_tcg2_event->header.pcr_index = 6;
+ efi_tcg2_event->header.event_type = EV_EFI_RUNTIME_SERVICES_DRIVER;
+ image_load_event.image_location_in_memory = 0x12345678;
+ image_load_event.image_length_in_memory = 0x300000;
+ image_load_event.image_link_time_address = 0x87654321;
+ image_load_event.length_of_device_path = 0;
+ boottime->copy_mem(efi_tcg2_event->event, &image_load_event,
+ sizeof(struct uefi_image_load_event));
+
+ ret = setup_boot_variable();
+ if (ret != EFI_SUCCESS)
+ return EFI_ST_FAILURE;
+
+ ret = setup_smbios_table(systable);
+ if (ret != EFI_SUCCESS)
+ return EFI_ST_FAILURE;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ (EFI_TCG2_MAX_PCR_INDEX + 1) *
+ TPM2_SHA256_DIGEST_SIZE,
+ (void **)&pcrs);
+ if (!pcrs)
+ return EFI_ST_FAILURE;
+
+ boottime->set_mem(pcrs, (EFI_TCG2_MAX_PCR_INDEX + 1) * TPM2_SHA256_DIGEST_SIZE, 0);
+
+ /* setup expected PCRs per architecture */
+ boottime->copy_mem(&expected_pcrs[4], &expected_pcrs_per_arch[0], TPM2_SHA256_DIGEST_SIZE);
+ boottime->copy_mem(&expected_pcrs[6], &expected_pcrs_per_arch[1], TPM2_SHA256_DIGEST_SIZE);
+
+ return EFI_ST_SUCCESS;
+}
+
+/**
+ * efi_status_t get_manufacturer_id() - Get manufacturer_id through submit_command API
+ *
+ * @tcg2 tcg2 protocol
+ * @manufacturer_id pointer to the manufacturer_id
+ * @return status code
+ */
+static efi_status_t get_manufacturer_id(struct efi_tcg2_protocol *tcg2, u32 *manufacturer_id)
+{
+ efi_status_t ret;
+ u8 cmd[TPM2_CMD_BUF_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(22), /* Length */
+ tpm_u32(TPM2_CC_GET_CAPABILITY), /* Command code */
+
+ tpm_u32(TPM2_CAP_TPM_PROPERTIES), /* Capability */
+ tpm_u32(TPM2_PT_MANUFACTURER), /* Property */
+ tpm_u32(1), /* Property count */
+ };
+ u8 resp[TPM2_CMD_BUF_SIZE];
+ unsigned int value_off;
+
+ ret = tcg2->submit_command(tcg2, 22, cmd,
+ TPM2_CMD_BUF_SIZE, resp);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ /*
+ * In the response buffer, the properties are located after the:
+ * tag (u16), response size (u32), response code (u32),
+ * YES/NO flag (u8), TPM_CAP (u32).
+ * The value is located after count (u32), property (u32).
+ */
+ value_off = sizeof(u16) + sizeof(u32) + sizeof(u32) +
+ sizeof(u8) + sizeof(u32) + sizeof(u32) + sizeof(u32);
+ *manufacturer_id = get_unaligned_be32(&resp[value_off]);
+
+ return ret;
+}
+
+/**
+ * efi_status_t get_manufacturer_id_buffer_small() - call submit_command with small resp buffer
+ *
+ * @tcg2 tcg2 protocol
+ * @manufacturer_id pointer to the manufacturer_id
+ * @return status code
+ */
+static efi_status_t get_manufacturer_id_buffer_small(struct efi_tcg2_protocol *tcg2)
+{
+ efi_status_t ret;
+ u8 cmd[TPM2_CMD_BUF_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(22), /* Length */
+ tpm_u32(TPM2_CC_GET_CAPABILITY), /* Command code */
+
+ tpm_u32(TPM2_CAP_TPM_PROPERTIES), /* Capability */
+ tpm_u32(TPM2_PT_MANUFACTURER), /* Property */
+ tpm_u32(1), /* Property count */
+ };
+ u8 resp[1]; /* set smaller buffer than expected */
+
+ ret = tcg2->submit_command(tcg2, 22, cmd, 1, resp);
+
+ return ret;
+}
+
+/**
+ * efi_status_t read_pcr() - Read the PCR from the TPM device
+ *
+ * @tcg2 tcg2 protocol
+ * @idx pcr index to read
+ * @return status code
+ */
+static efi_status_t read_pcr(struct efi_tcg2_protocol *tcg2, u32 idx)
+{
+ efi_status_t ret;
+ u32 cmd_len = 17 + IDX_ARRAY_SZ;
+ u8 cmd[TPM2_CMD_BUF_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(cmd_len), /* Length */
+ tpm_u32(TPM2_CC_PCR_READ), /* Command code */
+ /* TPML_PCR_SELECTION */
+ tpm_u32(1), /* Number of selections */
+ tpm_u16(TPM2_ALG_SHA256), /* Algorithm of the hash */
+ IDX_ARRAY_SZ, /* Array size for selection */
+ /* bitmap(idx), Selected PCR bitmap */
+ };
+ u8 resp[TPM2_CMD_BUF_SIZE];
+ u32 pcr_sel_idx = idx / 8;
+ u8 pcr_sel_bit = BIT(idx % 8);
+
+ cmd[17 + pcr_sel_idx] = pcr_sel_bit;
+ ret = tcg2->submit_command(tcg2, cmd_len, cmd,
+ TPM2_CMD_BUF_SIZE, resp);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->submit_command fail to read PCR\n");
+ return ret;
+ }
+
+ boottime->copy_mem(pcrs[idx], &resp[TPM2_PCR_READ_HEADER_SIZE],
+ TPM2_SHA256_DIGEST_SIZE);
+
+ return ret;
+}
+
+/**
+ * int validate_pcrs() - Compare the expected and actual pcrs
+ *
+ * @return status code
+ */
+static int validate_pcrs(void)
+{
+ u32 i;
+
+ /*
+ * - Skip PCR[0] validation. PCR[0] contains U-Boot version measurement
+ * it contains the commit hash, so the measurement varies every build
+ * with different commit hash.
+ * - Skip PCR[7] validation. PCR[7] contains UEFI Secure Boot variables
+ * measurement. These variables can not be updated through efi_selftest and
+ * vary depending on the platform.
+ * - Skip PCR[17..22] validation, they are not used in TCG PC Client
+ * Platform Firmware Profile Specification
+ */
+ for (i = 1; i < (EFI_TCG2_MAX_PCR_INDEX + 1); i++) {
+ if (i == 7 || (i > 16 && i < 23))
+ continue; /* skip validation */
+
+ if (memcmp(pcrs[i], expected_pcrs[i], TPM2_SHA256_DIGEST_SIZE)) {
+ efi_st_error("PCR[%d] is not the expected value\n", i);
+ return EFI_ST_FAILURE;
+ }
+ }
return EFI_ST_SUCCESS;
}
/**
* efi_st_tcg2_execute() - execute test
*
- * Call the GetCapability service of the EFI_TCG2_PROTOCOL.
+ * Call EFI_TCG2_PROTOCOL services and check the
+ * Measured Boot behavior.
*
* Return: status code
*/
struct efi_tcg2_protocol *tcg2;
struct efi_tcg2_boot_service_capability capability;
efi_status_t ret;
+ u32 active_pcr_banks;
+ u64 eventlog, eventlog_last_entry;
+ bool eventlog_truncated;
+ efi_handle_t handle;
+ efi_uintn_t exit_data_size = 0;
+ u16 *exit_data = NULL;
+ u32 i;
+ u32 manufacturer_id;
ret = boottime->locate_protocol(&guid_tcg2, NULL, (void **)&tcg2);
if (ret != EFI_SUCCESS) {
efi_st_error("TCG2 protocol is not available.\n");
return EFI_ST_FAILURE;
}
+
+ /* EFI_TCG2_PROTOCOL.GetCapability test */
capability.size = sizeof(struct efi_tcg2_boot_service_capability) - 1;
ret = tcg2->get_capability(tcg2, &capability);
if (ret != EFI_BUFFER_TOO_SMALL) {
}
efi_st_printf("TPM supports 0x%.8x event logs\n",
capability.supported_event_logs);
+
+ /* EFI_TCG2_PROTOCOL.GetActivePcrBanks test */
+ ret = tcg2->get_active_pcr_banks(tcg2, &active_pcr_banks);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->get_active_pcr_banks failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (active_pcr_banks != capability.active_pcr_banks) {
+ efi_st_error("tcg2->get_active_pcr_banks return wrong value\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* EFI_TCG2_PROTOCOL.HashLogExtendEvent test */
+ ret = tcg2->hash_log_extend_event(tcg2, EFI_TCG2_EXTEND_ONLY,
+ (uintptr_t)image,
+ img.length, efi_tcg2_event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->hash_log_extend_event(EXTEND_ONLY) failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = tcg2->hash_log_extend_event(tcg2, PE_COFF_IMAGE, (uintptr_t)image,
+ img.length, efi_tcg2_event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->hash_log_extend_event(PE_COFF_IMAGE) failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* EFI_TCG2_PROTOCOL.SubmitCommand test */
+ ret = get_manufacturer_id_buffer_small(tcg2);
+ if (ret != EFI_OUT_OF_RESOURCES) {
+ efi_st_error("get_manufacturer_id buffer too small failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = get_manufacturer_id(tcg2, &manufacturer_id);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("get_manufacturer_id failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (capability.manufacturer_id != manufacturer_id) {
+ efi_st_error("tcg2->submit_command test failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* tcg2_measure_pe_image test */
+ ret = boottime->load_image(false, image_handle, NULL, image,
+ img.length, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* measure ready_to_boot event(boot variables, smbios table, etc.) */
+ /* TODO: add GPT measurement test */
+ ret = boottime->start_image(handle, &exit_data_size, &exit_data);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("Wrong return value from application\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(exit_data);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free exit data\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* validate PCR read from the TPM device */
+ for (i = 0; i < (EFI_TCG2_MAX_PCR_INDEX + 1); i++) {
+ ret = read_pcr(tcg2, i);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("read pcr error\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (validate_pcrs()) {
+ efi_st_error("PCR validation failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* EFI_TCG2_PROTOCOL.GetEventLog test */
+ ret = tcg2->get_eventlog(tcg2, TCG2_EVENT_LOG_FORMAT_TCG_2, &eventlog,
+ &eventlog_last_entry, &eventlog_truncated);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->get_eventlog failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* TODO: eventlog format check */
+
return EFI_ST_SUCCESS;
}
+/*
+ * efi_st_tcg2_teardown() - Tear down unit test
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int efi_st_tcg2_teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (image) {
+ r = boottime->free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (efi_tcg2_event) {
+ r = boottime->free_pool(efi_tcg2_event);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free efi_tcg2_event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (pcrs) {
+ r = boottime->free_pool(pcrs);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free pcr\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ r = restore_boot_variable();
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to restore boot variables\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Restore SMBIOS table
+ * If orig_smbios_table is NULL, calling install_configuration_table()
+ * removes dummy SMBIOS table form systab.
+ */
+ r = boottime->install_configuration_table(&smbios_guid, orig_smbios_table);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to restore SMBOIS table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ if (dmi_addr) {
+ r = boottime->free_pages(dmi_addr, 1);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free dummy smbios table\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ return r;
+}
+
EFI_UNIT_TEST(tcg2) = {
.name = "tcg2",
.phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
.execute = efi_st_tcg2_execute,
.setup = efi_st_tcg2_setup,
+ .teardown = efi_st_tcg2_teardown,
+ .on_request = true,
};
return 0;
}
+
+u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
+ u8 *recvbuf, size_t *recv_size)
+{
+ return tpm_sendrecv_command(dev, sendbuf, recvbuf, recv_size);
+}
--- /dev/null
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Script to build an EFI thing suitable for booting with QEMU, possibly running
+# it also.
+
+# This just an example. It assumes that
+
+# - you build U-Boot in ${ubdir}/<name> where <name> is the U-Boot board config
+# - /mnt/x is a directory used for mounting
+# - you have access to the 'pure UEFI' builds for QEMU
+#
+# UEFI binaries for QEMU used for testing this script:
+#
+# OVMF-pure-efi.i386.fd at
+# https://drive.google.com/file/d/1jWzOAZfQqMmS2_dAK2G518GhIgj9r2RY/view?usp=sharing
+
+# OVMF-pure-efi.x64.fd at
+# https://drive.google.com/file/d/1c39YI9QtpByGQ4V0UNNQtGqttEzS-eFV/view?usp=sharing
+
+set -e
+
+usage() {
+ echo "Usage: $0 [-a | -p] [other opts]" 1>&2
+ echo 1>&2
+ echo " -a - Package up the app" 1>&2
+ echo " -o - Use old EFI app build (before 32/64 split)" 1>&2
+ echo " -p - Package up the payload" 1>&2
+ echo " -P - Create a partition table" 1>&2
+ echo " -r - Run QEMU with the image" 1>&2
+ echo " -s - Run QEMU with serial only (no display)" 1>&2
+ echo " -w - Use word version (32-bit)" 1>&2
+ exit 1
+}
+
+# 32- or 64-bit EFI
+bitness=64
+
+# app or payload ?
+type=app
+
+# create a partition table and put the filesystem in that (otherwise put the
+# filesystem in the raw device)
+part=
+
+# run the image with QEMU
+run=
+
+# run QEMU without a display (U-Boot must be set to stdout=serial)
+serial=
+
+# before the 32/64 split of the app
+old=
+
+# Set ubdir to the build directory where you build U-Boot out-of-tree
+# We avoid in-tree build because it gets confusing trying different builds
+ubdir=/tmp/b/
+
+while getopts "aopPrsw" opt; do
+ case "${opt}" in
+ a)
+ type=app
+ ;;
+ p)
+ type=payload
+ ;;
+ r)
+ run=1
+ ;;
+ s)
+ serial=1
+ ;;
+ w)
+ bitness=32
+ ;;
+ o)
+ old=1
+ ;;
+ P)
+ part=1
+ ;;
+ *)
+ usage
+ ;;
+ esac
+done
+
+run_qemu() {
+ extra=
+ if [[ "${bitness}" = "64" ]]; then
+ qemu=qemu-system-x86_64
+ bios=OVMF-pure-efi.x64.fd
+ else
+ qemu=qemu-system-i386
+ bios=OVMF-pure-efi.i386.fd
+ fi
+ if [[ -n "${serial}" ]]; then
+ extra="-display none -serial mon:stdio"
+ fi
+ echo "Running ${qemu}"
+ # Use 512MB since U-Boot EFI likes to have 256MB to play with
+ "${qemu}" -bios "${bios}" \
+ -m 512 \
+ -drive id=disk,file="${IMG}",if=none,format=raw \
+ -nic none -device ahci,id=ahci \
+ -device ide-hd,drive=disk,bus=ahci.0 ${extra}
+}
+
+setup_files() {
+ echo "Packaging ${BUILD}"
+ mkdir -p $TMP
+ cat >$TMP/startup.nsh <<EOF
+fs0:u-boot-${type}.efi
+EOF
+ sudo cp ${ubdir}/${BUILD}/u-boot-${type}.efi $TMP
+
+ # Can copy in other files here:
+ #sudo cp ${ubdir}/$BUILD/image.bin $TMP/chromeos.rom
+ #sudo cp /boot/vmlinuz-5.4.0-77-generic $TMP/vmlinuz
+}
+
+# Copy files into the filesystem
+copy_files() {
+ sudo cp $TMP/* $MNT
+}
+
+# Create a filesystem on a raw device and copy in the files
+setup_raw() {
+ mkfs.vfat "${IMG}" >/dev/null
+ sudo mount -o loop "${IMG}" $MNT
+ copy_files
+ sudo umount $MNT
+}
+
+# Create a partition table and put the filesystem in the first partition
+# then copy in the files
+setup_part() {
+ # Create a gpt partition table with one partition
+ parted "${IMG}" mklabel gpt 2>/dev/null
+
+ # This doesn't work correctly. It creates:
+ # Number Start End Size File system Name Flags
+ # 1 1049kB 24.1MB 23.1MB boot msftdata
+ # Odd if the same is entered interactively it does set the FS type
+ parted -s -a optimal -- "${IMG}" mkpart boot fat32 1MiB 23MiB
+
+ # Map this partition to a loop device
+ kp="$(sudo kpartx -av ${IMG})"
+ read boot_dev<<<$(grep -o 'loop.*p.' <<< "${kp}")
+ test "${boot_dev}"
+ dev="/dev/mapper/${boot_dev}"
+
+ mkfs.vfat "${dev}" >/dev/null
+
+ sudo mount -o loop "${dev}" $MNT
+
+ copy_files
+
+ # Sync here since this makes kpartx more likely to work the first time
+ sync
+ sudo umount $MNT
+
+ # For some reason this needs a sleep or it sometimes fails, if it was
+ # run recently (in the last few seconds)
+ if ! sudo kpartx -d "${IMG}" > /dev/null; then
+ sleep .5
+ sudo kpartx -d "${IMG}" > /dev/null || \
+ echo "Failed to remove ${boot_dev}, use: sudo kpartx -d ${IMG}"
+ fi
+}
+
+TMP="/tmp/efi${bitness}${type}"
+MNT=/mnt/x
+BUILD="efi-x86_${type}${bitness}"
+IMG=try.img
+
+if [[ -n "${old}" && "${bitness}" = "32" ]]; then
+ BUILD="efi-x86_${type}"
+fi
+
+setup_files
+
+qemu-img create "${IMG}" 24M >/dev/null
+
+if [[ -n "${part}" ]]; then
+ setup_part
+else
+ setup_raw
+fi
+
+if [[ -n "${run}" ]]; then
+ run_qemu
+fi
CONFIG_XGI_XG22_BASE
CONFIG_XSENGINE
CONFIG_XTFPGA
-CONFIG_YAFFSFS_PROVIDE_VALUES
CONFIG_YAFFS_AUTO_UNICODE
CONFIG_YAFFS_CASE_INSENSITIVE
CONFIG_YAFFS_DEFINES_TYPES
-CONFIG_YAFFS_DIRECT
-CONFIG_YAFFS_PROVIDE_DEFS
CONFIG_YAFFS_UNICODE
CONFIG_YAFFS_UTIL
CONFIG_YAFFS_WINCE
IMAGE_CFG_DATA,
IMAGE_CFG_DATA_DELAY,
IMAGE_CFG_BAUDRATE,
+ IMAGE_CFG_UART_PORT,
+ IMAGE_CFG_UART_MPP,
IMAGE_CFG_DEBUG,
IMAGE_CFG_KAK,
IMAGE_CFG_CSK,
[IMAGE_CFG_DATA] = "DATA",
[IMAGE_CFG_DATA_DELAY] = "DATA_DELAY",
[IMAGE_CFG_BAUDRATE] = "BAUDRATE",
+ [IMAGE_CFG_UART_PORT] = "UART_PORT",
+ [IMAGE_CFG_UART_MPP] = "UART_MPP",
[IMAGE_CFG_DEBUG] = "DEBUG",
[IMAGE_CFG_KAK] = "KAK",
[IMAGE_CFG_CSK] = "CSK",
struct ext_hdr_v0_reg regdata;
unsigned int regdata_delay;
unsigned int baudrate;
+ unsigned int uart_port;
+ unsigned int uart_mpp;
unsigned int debug;
const char *key_name;
int csk_idx;
return e->sec_specialized_img;
}
+static int image_get_bootfrom(void)
+{
+ struct image_cfg_element *e;
+
+ e = image_find_option(IMAGE_CFG_BOOT_FROM);
+ if (!e)
+ /* fallback to SPI if no BOOT_FROM is not provided */
+ return IBR_HDR_SPI_ID;
+
+ return e->bootfrom;
+}
+
/*
* Compute a 8-bit checksum of a memory area. This algorithm follows
* the requirements of the Marvell SoC BootROM specifications.
return ret;
}
+static size_t image_headersz_align(size_t headersz, uint8_t blockid)
+{
+ /*
+ * Header needs to be 4-byte aligned, which is already ensured by code
+ * above. Moreover UART images must have header aligned to 128 bytes
+ * (xmodem block size), NAND images to 256 bytes (ECC calculation),
+ * and SATA and SDIO images to 512 bytes (storage block size).
+ * Note that SPI images do not have to have header size aligned
+ * to 256 bytes because it is possible to read from SPI storage from
+ * any offset (read offset does not have to be aligned to block size).
+ */
+ if (blockid == IBR_HDR_UART_ID)
+ return ALIGN(headersz, 128);
+ else if (blockid == IBR_HDR_NAND_ID)
+ return ALIGN(headersz, 256);
+ else if (blockid == IBR_HDR_SATA_ID || blockid == IBR_HDR_SDIO_ID)
+ return ALIGN(headersz, 512);
+ else
+ return headersz;
+}
+
+static size_t image_headersz_v0(int *hasext)
+{
+ size_t headersz;
+
+ headersz = sizeof(struct main_hdr_v0);
+ if (image_count_options(IMAGE_CFG_DATA) > 0) {
+ headersz += sizeof(struct ext_hdr_v0);
+ if (hasext)
+ *hasext = 1;
+ }
+
+ return image_headersz_align(headersz, image_get_bootfrom());
+}
+
static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
int payloadsz)
{
* Calculate the size of the header and the size of the
* payload
*/
- headersz = sizeof(struct main_hdr_v0);
-
- if (image_count_options(IMAGE_CFG_DATA) > 0) {
- has_ext = 1;
- headersz += sizeof(struct ext_hdr_v0);
- }
+ headersz = image_headersz_v0(&has_ext);
image = malloc(headersz);
if (!image) {
/* Fill in the main header */
main_hdr->blocksize =
- cpu_to_le32(payloadsz - headersz);
+ cpu_to_le32(payloadsz);
main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = has_ext;
+ main_hdr->version = 0;
main_hdr->destaddr = cpu_to_le32(params->addr);
main_hdr->execaddr = cpu_to_le32(params->ep);
+ main_hdr->blockid = image_get_bootfrom();
- e = image_find_option(IMAGE_CFG_BOOT_FROM);
- if (e)
- main_hdr->blockid = e->bootfrom;
e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
if (e)
main_hdr->nandeccmode = e->nandeccmode;
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
+ /*
+ * For SATA srcaddr is specified in number of sectors starting from
+ * sector 0. The main header is stored at sector number 1.
+ * This expects the sector size to be 512 bytes.
+ * Header size is already aligned.
+ */
+ if (main_hdr->blockid == IBR_HDR_SATA_ID)
+ main_hdr->srcaddr = cpu_to_le32(headersz / 512 + 1);
+
+ /*
+ * For SDIO srcaddr is specified in number of sectors starting from
+ * sector 0. The main header is stored at sector number 0.
+ * This expects sector size to be 512 bytes.
+ * Header size is already aligned.
+ */
+ if (main_hdr->blockid == IBR_HDR_SDIO_ID)
+ main_hdr->srcaddr = cpu_to_le32(headersz / 512);
+
+ /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
+ if (main_hdr->blockid == IBR_HDR_PEX_ID)
+ main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
+
/* Generate the ext header */
if (has_ext) {
struct ext_hdr_v0 *ext_hdr;
*hasext = 1;
}
- /*
- * The payload should be aligned on some reasonable
- * boundary
- */
- return ALIGN(headersz, 4096);
+ return image_headersz_align(headersz, image_get_bootfrom());
}
int add_binary_header_v1(uint8_t **cur, uint8_t **next_ext,
{
struct image_cfg_element *e;
struct main_hdr_v1 *main_hdr;
+ struct opt_hdr_v1 *ohdr;
struct register_set_hdr_v1 *register_set_hdr;
struct secure_hdr_v1 *secure_hdr = NULL;
size_t headersz;
/* Fill the main header */
main_hdr->blocksize =
- cpu_to_le32(payloadsz - headersz);
+ cpu_to_le32(payloadsz);
main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
main_hdr->destaddr = cpu_to_le32(params->addr);
main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
main_hdr->version = 1;
- e = image_find_option(IMAGE_CFG_BOOT_FROM);
- if (e)
- main_hdr->blockid = e->bootfrom;
+ main_hdr->blockid = image_get_bootfrom();
+
e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
if (e)
main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
main_hdr->nandbadblklocation = e->nandbadblklocation;
e = image_find_option(IMAGE_CFG_BAUDRATE);
if (e)
- main_hdr->options = baudrate_to_option(e->baudrate);
+ main_hdr->options |= baudrate_to_option(e->baudrate);
+ e = image_find_option(IMAGE_CFG_UART_PORT);
+ if (e)
+ main_hdr->options |= (e->uart_port & 3) << 3;
+ e = image_find_option(IMAGE_CFG_UART_MPP);
+ if (e)
+ main_hdr->options |= (e->uart_mpp & 7) << 5;
e = image_find_option(IMAGE_CFG_DEBUG);
if (e)
main_hdr->flags = e->debug ? 0x1 : 0;
return NULL;
}
- if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz,
+ if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz + headersz,
headersz, image, secure_hdr))
return NULL;
main_hdr->checksum = image_checksum8(main_hdr, headersz);
*imagesz = headersz;
+
+ /* Fill the real header size without padding into the main header */
+ headersz = sizeof(*main_hdr);
+ for_each_opt_hdr_v1 (ohdr, main_hdr)
+ headersz += opt_hdr_v1_size(ohdr);
+ main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
+ main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
+
return image;
}
case IMAGE_CFG_BAUDRATE:
el->baudrate = strtoul(value1, NULL, 10);
break;
+ case IMAGE_CFG_UART_PORT:
+ el->uart_port = strtoul(value1, NULL, 16);
+ break;
+ case IMAGE_CFG_UART_MPP:
+ el->uart_mpp = strtoul(value1, NULL, 16);
+ break;
case IMAGE_CFG_DEBUG:
el->debug = strtoul(value1, NULL, 10);
break;
return e->version;
}
-static int image_get_bootfrom(void)
-{
- struct image_cfg_element *e;
-
- e = image_find_option(IMAGE_CFG_BOOT_FROM);
- if (!e)
- return -1;
-
- return e->bootfrom;
-}
-
static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
void *image = NULL;
int version;
size_t headersz = 0;
+ size_t datasz;
uint32_t checksum;
+ struct stat s;
int ret;
+ /*
+ * Do not use sbuf->st_size as it contains size with padding.
+ * We need original image data size, so stat original file.
+ */
+ if (stat(params->datafile, &s)) {
+ fprintf(stderr, "Could not stat data file %s: %s\n",
+ params->datafile, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ datasz = ALIGN(s.st_size, 4);
+
fcfg = fopen(params->imagename, "r");
if (!fcfg) {
fprintf(stderr, "Could not open input file %s\n",
*/
case -1:
case 0:
- image = image_create_v0(&headersz, params, sbuf->st_size);
+ image = image_create_v0(&headersz, params, datasz + 4);
break;
case 1:
- image = image_create_v1(&headersz, params, ptr, sbuf->st_size);
+ image = image_create_v1(&headersz, params, ptr, datasz + 4);
break;
default:
free(image_cfg);
- /* Build and add image checksum header */
+ /* Build and add image data checksum */
checksum = cpu_to_le32(image_checksum32((uint8_t *)ptr + headersz,
- sbuf->st_size - headersz - sizeof(uint32_t)));
- memcpy((uint8_t *)ptr + sbuf->st_size - sizeof(uint32_t), &checksum,
- sizeof(uint32_t));
+ datasz));
+ memcpy((uint8_t *)ptr + headersz + datasz, &checksum, sizeof(uint32_t));
/* Finally copy the header into the image area */
memcpy(ptr, image, headersz);
struct image_tool_params *params)
{
size_t header_size = kwbheader_size(ptr);
+ uint8_t blockid;
+ uint32_t offset;
+ uint32_t size;
uint8_t csum;
if (header_size > image_size)
if (csum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
+
+ blockid = mhdr->blockid;
+ offset = le32_to_cpu(mhdr->srcaddr);
+ size = le32_to_cpu(mhdr->blocksize);
} else if (kwbimage_version(ptr) == 1) {
struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
const uint8_t *mhdr_end;
struct opt_hdr_v1 *ohdr;
- uint32_t offset;
- uint32_t size;
mhdr_end = (uint8_t *)mhdr + header_size;
for_each_opt_hdr_v1 (ohdr, ptr)
if (!opt_hdr_v1_valid_size(ohdr, mhdr_end))
return -FDT_ERR_BADSTRUCTURE;
+ blockid = mhdr->blockid;
offset = le32_to_cpu(mhdr->srcaddr);
+ size = le32_to_cpu(mhdr->blocksize);
+ } else {
+ return -FDT_ERR_BADSTRUCTURE;
+ }
- /*
- * For SATA srcaddr is specified in number of sectors.
- * The main header is must be stored at sector number 1.
- * This expects that sector size is 512 bytes and recalculates
- * data offset to bytes relative to the main header.
- */
- if (mhdr->blockid == IBR_HDR_SATA_ID) {
- if (offset < 1)
- return -FDT_ERR_BADSTRUCTURE;
- offset -= 1;
- offset *= 512;
- }
+ /*
+ * For SATA srcaddr is specified in number of sectors.
+ * The main header is must be stored at sector number 1.
+ * This expects that sector size is 512 bytes and recalculates
+ * data offset to bytes relative to the main header.
+ */
+ if (blockid == IBR_HDR_SATA_ID) {
+ if (offset < 1)
+ return -FDT_ERR_BADSTRUCTURE;
+ offset -= 1;
+ offset *= 512;
+ }
- /*
- * For SDIO srcaddr is specified in number of sectors.
- * This expects that sector size is 512 bytes and recalculates
- * data offset to bytes.
- */
- if (mhdr->blockid == IBR_HDR_SDIO_ID)
- offset *= 512;
+ /*
+ * For SDIO srcaddr is specified in number of sectors.
+ * This expects that sector size is 512 bytes and recalculates
+ * data offset to bytes.
+ */
+ if (blockid == IBR_HDR_SDIO_ID)
+ offset *= 512;
- /*
- * For PCIe srcaddr is always set to 0xFFFFFFFF.
- * This expects that data starts after all headers.
- */
- if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
- offset = header_size;
+ /*
+ * For PCIe srcaddr is always set to 0xFFFFFFFF.
+ * This expects that data starts after all headers.
+ */
+ if (blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
+ offset = header_size;
- if (offset > image_size || offset % 4 != 0)
- return -FDT_ERR_BADSTRUCTURE;
+ if (offset > image_size || offset % 4 != 0)
+ return -FDT_ERR_BADSTRUCTURE;
- size = le32_to_cpu(mhdr->blocksize);
- if (size < 4 || offset + size > image_size || size % 4 != 0)
- return -FDT_ERR_BADSTRUCTURE;
+ if (size < 4 || offset + size > image_size || size % 4 != 0)
+ return -FDT_ERR_BADSTRUCTURE;
- if (image_checksum32(ptr + offset, size - 4) !=
- *(uint32_t *)(ptr + offset + size - 4))
- return -FDT_ERR_BADSTRUCTURE;
- } else {
+ if (image_checksum32(ptr + offset, size - 4) !=
+ *(uint32_t *)(ptr + offset + size - 4))
return -FDT_ERR_BADSTRUCTURE;
- }
return 0;
}
*/
case -1:
case 0:
- alloc_len = sizeof(struct main_hdr_v0) +
- sizeof(struct ext_hdr_v0);
+ alloc_len = image_headersz_v0(NULL);
break;
case 1:
* The resulting image needs to be 4-byte aligned. At least
* the Marvell hdrparser tool complains if its unaligned.
* After the image data is stored 4-byte checksum.
+ * Final UART image must be aligned to 128 bytes.
* Final SPI and NAND images must be aligned to 256 bytes.
* Final SATA and SDIO images must be aligned to 512 bytes.
*/
return 4 + (256 - (alloc_len + s.st_size + 4) % 256) % 256;
else if (bootfrom == IBR_HDR_SATA_ID || bootfrom == IBR_HDR_SDIO_ID)
return 4 + (512 - (alloc_len + s.st_size + 4) % 512) % 512;
+ else if (bootfrom == IBR_HDR_UART_ID)
+ return 4 + (128 - (alloc_len + s.st_size + 4) % 128) % 128;
else
return 4 + (4 - s.st_size % 4) % 4;
}
char *msg = "Configuration file for kwbimage creation omitted";
fprintf(stderr, "Error:%s - %s\n", params->cmdname, msg);
- return CFG_INVALID;
+ return 1;
}
return (params->dflag && (params->fflag || params->lflag)) ||
uint8_t nandeccmode; /* 0x1 */
uint16_t nandpagesize; /* 0x2-0x3 */
uint32_t blocksize; /* 0x4-0x7 */
- uint32_t rsvd1; /* 0x8-0xB */
+ uint8_t version; /* 0x8 */
+ uint8_t rsvd1[3]; /* 0x9-0xB */
uint32_t srcaddr; /* 0xC-0xF */
uint32_t destaddr; /* 0x10-0x13 */
uint32_t execaddr; /* 0x14-0x17 */
#define OPT_HDR_V1_BINARY_TYPE 0x2
#define OPT_HDR_V1_REGISTER_TYPE 0x3
-enum kwbimage_cmd {
- CMD_INVALID,
- CMD_BOOT_FROM,
- CMD_NAND_ECC_MODE,
- CMD_NAND_PAGE_SIZE,
- CMD_SATA_PIO_MODE,
- CMD_DDR_INIT_DELAY,
- CMD_DATA
-};
-
-enum kwbimage_cmd_types {
- CFG_INVALID = -1,
- CFG_COMMAND,
- CFG_DATA0,
- CFG_DATA1
-};
-
-/*
- * functions
- */
-void init_kwb_image_type (void);
-
/*
* Byte 8 of the image header contains the version number. In the v0
* header, byte 8 was reserved, and always set to 0. In the v1 header,
#define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */
#define KWBOOT_HDR_RSP_TIMEO 10000 /* ms */
-/* ARM code making baudrate changing function return to original exec address */
-static unsigned char kwboot_pre_baud_code[] = {
- /* exec_addr: */
- 0x00, 0x00, 0x00, 0x00, /* .word 0 */
- 0x0c, 0xe0, 0x1f, 0xe5, /* ldr lr, exec_addr */
-};
-
-/* ARM code for binary header injection to change baudrate */
+/* ARM code to change baudrate */
static unsigned char kwboot_baud_code[] = {
/* ; #define UART_BASE 0xd0012000 */
- /* ; #define THR 0x00 */
/* ; #define DLL 0x00 */
/* ; #define DLH 0x04 */
/* ; #define LCR 0x0c */
/* ; #define DLAB 0x80 */
/* ; #define LSR 0x14 */
- /* ; #define THRE 0x20 */
/* ; #define TEMT 0x40 */
/* ; #define DIV_ROUND(a, b) ((a + b/2) / b) */
/* ; */
/* ; u32 set_baudrate(u32 old_b, u32 new_b) { */
- /* ; const u8 *str = "$baudratechange"; */
- /* ; u8 c; */
- /* ; do { */
- /* ; c = *str++; */
- /* ; writel(UART_BASE + THR, c); */
- /* ; } while (c); */
/* ; while */
/* ; (!(readl(UART_BASE + LSR) & TEMT)); */
/* ; u32 lcr = readl(UART_BASE + LCR); */
/* ; writel(UART_BASE + DLL, new_dll); */
/* ; writel(UART_BASE + DLH, new_dlh); */
/* ; writel(UART_BASE + LCR, lcr & ~DLAB); */
- /* ; msleep(1); */
+ /* ; msleep(5); */
/* ; return 0; */
/* ; } */
- 0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */
-
/* ; r0 = UART_BASE */
- 0x02, 0x0a, 0xa0, 0xe3, /* mov r0, #0x2000 */
- 0x01, 0x00, 0x4d, 0xe3, /* movt r0, #0xd001 */
-
- /* ; r2 = address of preamble string */
- 0xd0, 0x20, 0x8f, 0xe2, /* adr r2, preamble */
-
- /* ; Send preamble string over UART */
- /* .Lloop_preamble: */
- /* */
- /* ; Wait until Transmitter Holding is Empty */
- /* .Lloop_thre: */
- /* ; r1 = UART_BASE[LSR] & THRE */
- 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
- 0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */
- 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */
-
- /* ; Put character into Transmitter FIFO */
- /* ; r1 = *r2++ */
- 0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */
- /* ; UART_BASE[THR] = r1 */
- 0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */
-
- /* ; Loop until end of preamble string */
- 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
- 0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */
+ 0x0d, 0x02, 0xa0, 0xe3, /* mov r0, #0xd0000000 */
+ 0x12, 0x0a, 0x80, 0xe3, /* orr r0, r0, #0x12000 */
/* ; Wait until Transmitter FIFO is Empty */
/* .Lloop_txempty: */
/* ; Read old baudrate value */
/* ; r2 = old_baudrate */
- 0x8c, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */
+ 0x74, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */
/* ; Calculate base clock */
/* ; r1 = r2 * r1 */
0x92, 0x01, 0x01, 0xe0, /* mul r1, r2, r1 */
/* ; Read new baudrate value */
- /* ; r2 = baudrate */
- 0x88, 0x20, 0x9f, 0xe5, /* ldr r2, baudrate */
+ /* ; r2 = new_baudrate */
+ 0x70, 0x20, 0x9f, 0xe5, /* ldr r2, new_baudrate */
/* ; Calculate new Divisor Latch */
/* ; r1 = DIV_ROUND(r1, r2) = */
0x80, 0x10, 0xc1, 0xe3, /* bic r1, r1, #0x80 */
0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */
- /* ; Sleep 1ms ~~ 600000 cycles at 1200 MHz */
- /* ; r1 = 600000 */
- 0x9f, 0x1d, 0xa0, 0xe3, /* mov r1, #0x27c0 */
- 0x09, 0x10, 0x40, 0xe3, /* movt r1, #0x0009 */
+ /* ; Loop 0x2dc000 (2998272) cycles */
+ /* ; which is about 5ms on 1200 MHz CPU */
+ /* ; r1 = 0x2dc000 */
+ 0xb7, 0x19, 0xa0, 0xe3, /* mov r1, #0x2dc000 */
/* .Lloop_sleep: */
0x01, 0x10, 0x41, 0xe2, /* sub r1, r1, #1 */
0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
0xfc, 0xff, 0xff, 0x1a, /* bne .Lloop_sleep */
- /* ; Return 0 - no error */
- 0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */
- 0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */
-
- /* ; Preamble string */
- /* preamble: */
- 0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */
- 0x64, 0x72, 0x61, 0x74,
- 0x65, 0x63, 0x68, 0x61,
- 0x6e, 0x67, 0x65, 0x00,
+ /* ; Jump to the end of execution */
+ 0x01, 0x00, 0x00, 0xea, /* b end */
/* ; Placeholder for old baudrate value */
/* old_baudrate: */
/* ; Placeholder for new baudrate value */
/* new_baudrate: */
0x00, 0x00, 0x00, 0x00, /* .word 0 */
+
+ /* end: */
};
-#define KWBOOT_BAUDRATE_BIN_HEADER_SZ (sizeof(kwboot_baud_code) + \
- sizeof(struct opt_hdr_v1) + 8 + 16)
+/* ARM code from binary header executed by BootROM before changing baudrate */
+static unsigned char kwboot_baud_code_binhdr_pre[] = {
+ /* ; #define UART_BASE 0xd0012000 */
+ /* ; #define THR 0x00 */
+ /* ; #define LSR 0x14 */
+ /* ; #define THRE 0x20 */
+ /* ; */
+ /* ; void send_preamble(void) { */
+ /* ; const u8 *str = "$baudratechange"; */
+ /* ; u8 c; */
+ /* ; do { */
+ /* ; while */
+ /* ; ((readl(UART_BASE + LSR) & THRE)); */
+ /* ; c = *str++; */
+ /* ; writel(UART_BASE + THR, c); */
+ /* ; } while (c); */
+ /* ; } */
+
+ /* ; Preserve registers for BootROM */
+ 0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */
+
+ /* ; r0 = UART_BASE */
+ 0x0d, 0x02, 0xa0, 0xe3, /* mov r0, #0xd0000000 */
+ 0x12, 0x0a, 0x80, 0xe3, /* orr r0, r0, #0x12000 */
+
+ /* ; r2 = address of preamble string */
+ 0x00, 0x20, 0x8f, 0xe2, /* adr r2, .Lstr_preamble */
+
+ /* ; Skip preamble data section */
+ 0x03, 0x00, 0x00, 0xea, /* b .Lloop_preamble */
+
+ /* ; Preamble string */
+ /* .Lstr_preamble: */
+ 0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */
+ 0x64, 0x72, 0x61, 0x74,
+ 0x65, 0x63, 0x68, 0x61,
+ 0x6e, 0x67, 0x65, 0x00,
+
+ /* ; Send preamble string over UART */
+ /* .Lloop_preamble: */
+ /* */
+ /* ; Wait until Transmitter Holding is Empty */
+ /* .Lloop_thre: */
+ /* ; r1 = UART_BASE[LSR] & THRE */
+ 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
+ 0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */
+ 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */
+
+ /* ; Put character into Transmitter FIFO */
+ /* ; r1 = *r2++ */
+ 0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */
+ /* ; UART_BASE[THR] = r1 */
+ 0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */
+
+ /* ; Loop until end of preamble string */
+ 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
+ 0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */
+};
+
+/* ARM code for returning from binary header back to BootROM */
+static unsigned char kwboot_baud_code_binhdr_post[] = {
+ /* ; Return 0 - no error */
+ 0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */
+ 0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */
+};
+
+/* ARM code for jumping to the original image exec_addr */
+static unsigned char kwboot_baud_code_data_jump[] = {
+ 0x04, 0xf0, 0x1f, 0xe5, /* ldr pc, exec_addr */
+ /* ; Placeholder for exec_addr */
+ /* exec_addr: */
+ 0x00, 0x00, 0x00, 0x00, /* .word 0 */
+};
static const char kwb_baud_magic[16] = "$baudratechange";
}
static int
-kwboot_tty_send(int fd, const void *buf, size_t len)
+kwboot_tty_send(int fd, const void *buf, size_t len, int nodrain)
{
if (!buf)
return 0;
if (kwboot_write(fd, buf, len) < 0)
return -1;
+ if (nodrain)
+ return 0;
+
return tcdrain(fd);
}
static int
kwboot_tty_send_char(int fd, unsigned char c)
{
- return kwboot_tty_send(fd, &c, 1);
+ return kwboot_tty_send(fd, &c, 1, 0);
}
static speed_t
cfmakeraw(&tio);
tio.c_cflag |= CREAD | CLOCAL;
+ tio.c_cflag &= ~(CSTOPB | HUPCL | CRTSCTS);
tio.c_cc[VMIN] = 1;
tio.c_cc[VTIME] = 0;
break;
for (count = 0; count < 128; count++) {
- rc = kwboot_tty_send(tty, msg, 8);
+ rc = kwboot_tty_send(tty, msg, 8, 0);
if (rc) {
usleep(msg_req_delay * 1000);
continue;
if (rc)
break;
- rc = kwboot_tty_send(tty, msg, 8);
+ rc = kwboot_tty_send(tty, msg, 8, 0);
if (rc) {
usleep(msg_req_delay * 1000);
continue;
}
static int
-kwboot_xm_recv_reply(int fd, char *c, int allow_non_xm, int *non_xm_print,
+kwboot_xm_recv_reply(int fd, char *c, int nak_on_non_xm,
+ int allow_non_xm, int *non_xm_print,
int baudrate, int *baud_changed)
{
int timeout = allow_non_xm ? KWBOOT_HDR_RSP_TIMEO : blk_rsp_timeo;
uint64_t recv_until = _now() + timeout;
int rc;
- if (non_xm_print)
- *non_xm_print = 0;
- if (baud_changed)
- *baud_changed = 0;
-
while (1) {
rc = kwboot_tty_recv(fd, c, 1, timeout);
if (rc) {
*non_xm_print = 1;
}
} else {
+ if (nak_on_non_xm) {
+ *c = NAK;
+ break;
+ }
timeout = recv_until - _now();
if (timeout < 0) {
errno = ETIMEDOUT;
char c;
*done_print = 0;
+ non_xm_print = 0;
+ baud_changed = 0;
- retries = 16;
+ retries = 0;
do {
- rc = kwboot_tty_send(fd, block, sizeof(*block));
+ rc = kwboot_tty_send(fd, block, sizeof(*block), 1);
if (rc)
return rc;
*done_print = 1;
}
- rc = kwboot_xm_recv_reply(fd, &c, allow_non_xm, &non_xm_print,
+ rc = kwboot_xm_recv_reply(fd, &c, retries < 3,
+ allow_non_xm, &non_xm_print,
baudrate, &baud_changed);
if (rc)
goto can;
if (!allow_non_xm && c != ACK)
kwboot_progress(-1, '+');
- } while (c == NAK && retries-- > 0);
+ } while (c == NAK && retries++ < 16);
if (non_xm_print)
kwboot_printv("\n");
kwboot_printv("Finishing transfer\n");
- retries = 16;
+ retries = 0;
do {
rc = kwboot_tty_send_char(fd, EOT);
if (rc)
return rc;
- rc = kwboot_xm_recv_reply(fd, &c, 0, NULL, 0, NULL);
+ rc = kwboot_xm_recv_reply(fd, &c, retries < 3,
+ 0, NULL, 0, NULL);
if (rc)
return rc;
- } while (c == NAK && retries-- > 0);
+ } while (c == NAK && retries++ < 16);
return _xm_reply_to_error(c);
}
hdrsz = kwbheader_size(img);
+ /*
+ * If header size is not aligned to xmodem block size (which applies
+ * for all images in kwbimage v0 format) then we have to ensure that
+ * the last xmodem block of header contains beginning of the data
+ * followed by the header. So align header size to xmodem block size.
+ */
+ hdrsz += (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) % KWBOOT_XM_BLKSZ;
+
kwboot_printv("Waiting 2s and flushing tty\n");
sleep(2); /* flush isn't effective without it */
tcflush(tty, TCIOFLUSH);
if (rc)
return rc;
- img += hdrsz;
- size -= hdrsz;
-
- rc = kwboot_xmodem_one(tty, &pnum, 0, img, size, 0);
- if (rc)
- return rc;
+ /*
+ * If we have already sent image data as a part of the last
+ * xmodem header block then we have nothing more to send.
+ */
+ if (hdrsz < size) {
+ img += hdrsz;
+ size -= hdrsz;
+ rc = kwboot_xmodem_one(tty, &pnum, 0, img, size, 0);
+ if (rc)
+ return rc;
+ }
rc = kwboot_xm_finish(tty);
if (rc)
return rc;
if (baudrate) {
- char buf[sizeof(kwb_baud_magic)];
-
- /* Wait 1s for baudrate change magic */
- rc = kwboot_tty_recv(tty, buf, sizeof(buf), 1000);
- if (rc)
- return rc;
-
- if (memcmp(buf, kwb_baud_magic, sizeof(buf))) {
- errno = EPROTO;
- return -1;
- }
-
kwboot_printv("\nChanging baudrate back to 115200 Bd\n\n");
rc = kwboot_tty_change_baudrate(tty, 115200);
if (rc)
fd_set rfds;
int nfds = 0;
+ FD_ZERO(&rfds);
FD_SET(tty, &rfds);
nfds = nfds < tty ? tty : nfds;
return csum;
}
+static uint32_t *
+kwboot_img_csum32_ptr(void *img)
+{
+ struct main_hdr_v1 *hdr = img;
+ uint32_t datasz;
+
+ datasz = le32_to_cpu(hdr->blocksize) - sizeof(uint32_t);
+
+ return img + le32_to_cpu(hdr->srcaddr) + datasz;
+}
+
+static uint32_t
+kwboot_img_csum32(const void *img)
+{
+ const struct main_hdr_v1 *hdr = img;
+ uint32_t datasz, csum = 0;
+ const uint32_t *data;
+
+ datasz = le32_to_cpu(hdr->blocksize) - sizeof(csum);
+ if (datasz % sizeof(uint32_t))
+ return 0;
+
+ data = img + le32_to_cpu(hdr->srcaddr);
+ while (datasz > 0) {
+ csum += le32_to_cpu(*data++);
+ datasz -= 4;
+ }
+
+ return cpu_to_le32(csum);
+}
+
static int
kwboot_img_is_secure(void *img)
{
}
static void *
-kwboot_img_grow_data_left(void *img, size_t *size, size_t grow)
+kwboot_img_grow_data_right(void *img, size_t *size, size_t grow)
{
- uint32_t hdrsz, datasz, srcaddr;
struct main_hdr_v1 *hdr = img;
- uint8_t *data;
-
- srcaddr = le32_to_cpu(hdr->srcaddr);
+ void *result;
- hdrsz = kwbheader_size(hdr);
- data = (uint8_t *)img + srcaddr;
- datasz = *size - srcaddr;
-
- /* only move data if there is not enough space */
- if (hdrsz + grow > srcaddr) {
- size_t need = hdrsz + grow - srcaddr;
-
- /* move data by enough bytes */
- memmove(data + need, data, datasz);
- *size += need;
- srcaddr += need;
- }
-
- srcaddr -= grow;
- hdr->srcaddr = cpu_to_le32(srcaddr);
- hdr->destaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) - grow);
+ /*
+ * 32-bit checksum comes after end of image code, so we will be putting
+ * new code there. So we get this pointer and then increase data size
+ * (since increasing data size changes kwboot_img_csum32_ptr() return
+ * value).
+ */
+ result = kwboot_img_csum32_ptr(img);
hdr->blocksize = cpu_to_le32(le32_to_cpu(hdr->blocksize) + grow);
+ *size += grow;
- return (uint8_t *)img + srcaddr;
+ return result;
}
static void
{
uint32_t hdrsz, datasz, srcaddr;
struct main_hdr_v1 *hdr = img;
+ struct opt_hdr_v1 *ohdr;
uint8_t *data;
srcaddr = le32_to_cpu(hdr->srcaddr);
- hdrsz = kwbheader_size(img);
+ /* calculate real used space in kwbimage header */
+ if (kwbimage_version(img) == 0) {
+ hdrsz = kwbheader_size(img);
+ } else {
+ hdrsz = sizeof(*hdr);
+ for_each_opt_hdr_v1 (ohdr, hdr)
+ hdrsz += opt_hdr_v1_size(ohdr);
+ }
+
data = (uint8_t *)img + srcaddr;
datasz = *size - srcaddr;
if (kwbimage_version(img) == 1) {
hdrsz += grow;
- hdr->headersz_msb = hdrsz >> 16;
- hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff);
+ if (hdrsz > kwbheader_size(img)) {
+ hdr->headersz_msb = hdrsz >> 16;
+ hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff);
+ }
}
}
uint32_t num_args;
uint32_t offset;
uint32_t ohdrsz;
+ uint8_t *prev_ext;
if (hdr->ext & 0x1) {
for_each_opt_hdr_v1 (ohdr, img)
if (opt_hdr_v1_next(ohdr) == NULL)
break;
- *opt_hdr_v1_ext(ohdr) |= 1;
- ohdr = opt_hdr_v1_next(ohdr);
+ prev_ext = opt_hdr_v1_ext(ohdr);
+ ohdr = _opt_hdr_v1_next(ohdr);
} else {
- hdr->ext |= 1;
ohdr = (void *)(hdr + 1);
+ prev_ext = &hdr->ext;
}
/*
ohdrsz = sizeof(*ohdr) + 4 + 4 * num_args + binsz + 4;
kwboot_img_grow_hdr(hdr, size, ohdrsz);
+ *prev_ext |= 1;
+
ohdr->headertype = OPT_HDR_V1_BINARY_TYPE;
ohdr->headersz_msb = ohdrsz >> 16;
ohdr->headersz_lsb = cpu_to_le16(ohdrsz & 0xffff);
}
static void
-_copy_baudrate_change_code(struct main_hdr_v1 *hdr, void *dst, int pre,
- int old_baud, int new_baud)
+_inject_baudrate_change_code(void *img, size_t *size, int for_data,
+ int old_baud, int new_baud)
{
- size_t codesz = sizeof(kwboot_baud_code);
- uint8_t *code = dst;
-
- if (pre) {
- size_t presz = sizeof(kwboot_pre_baud_code);
+ struct main_hdr_v1 *hdr = img;
+ uint32_t orig_datasz;
+ uint32_t codesz;
+ uint8_t *code;
- /*
- * We need to prepend code that loads lr register with original
- * value of hdr->execaddr. We do this by putting the original
- * exec address before the code that loads it relatively from
- * it's beginning.
- * Afterwards we change the exec address to this code (which is
- * at offset 4, because the first 4 bytes contain the original
- * exec address).
- */
- memcpy(code, kwboot_pre_baud_code, presz);
- *(uint32_t *)code = hdr->execaddr;
+ if (for_data) {
+ orig_datasz = le32_to_cpu(hdr->blocksize) - sizeof(uint32_t);
- hdr->execaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) + 4);
+ codesz = sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_data_jump);
+ code = kwboot_img_grow_data_right(img, size, codesz);
+ } else {
+ codesz = sizeof(kwboot_baud_code_binhdr_pre) +
+ sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_binhdr_post);
+ code = kwboot_add_bin_ohdr_v1(img, size, codesz);
- code += presz;
+ codesz = sizeof(kwboot_baud_code_binhdr_pre);
+ memcpy(code, kwboot_baud_code_binhdr_pre, codesz);
+ code += codesz;
}
- memcpy(code, kwboot_baud_code, codesz - 8);
- *(uint32_t *)(code + codesz - 8) = cpu_to_le32(old_baud);
- *(uint32_t *)(code + codesz - 4) = cpu_to_le32(new_baud);
+ codesz = sizeof(kwboot_baud_code) - 2 * sizeof(uint32_t);
+ memcpy(code, kwboot_baud_code, codesz);
+ code += codesz;
+ *(uint32_t *)code = cpu_to_le32(old_baud);
+ code += sizeof(uint32_t);
+ *(uint32_t *)code = cpu_to_le32(new_baud);
+ code += sizeof(uint32_t);
+
+ if (for_data) {
+ codesz = sizeof(kwboot_baud_code_data_jump) - sizeof(uint32_t);
+ memcpy(code, kwboot_baud_code_data_jump, codesz);
+ code += codesz;
+ *(uint32_t *)code = hdr->execaddr;
+ code += sizeof(uint32_t);
+ hdr->execaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) + orig_datasz);
+ } else {
+ codesz = sizeof(kwboot_baud_code_binhdr_post);
+ memcpy(code, kwboot_baud_code_binhdr_post, codesz);
+ code += codesz;
+ }
}
static int
*size < le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize))
goto err;
+ if (kwboot_img_csum32(img) != *kwboot_img_csum32_ptr(img))
+ goto err;
+
is_secure = kwboot_img_is_secure(img);
if (hdr->blockid != IBR_HDR_UART_ID) {
}
if (!is_secure) {
+ if (image_ver == 1) {
+ /*
+ * Tell BootROM to send BootROM messages to UART port
+ * number 0 (used also for UART booting) with default
+ * baudrate (which should be 115200) and do not touch
+ * UART MPP configuration.
+ */
+ hdr->options &= ~0x1F;
+ hdr->options |= MAIN_HDR_V1_OPT_BAUD_DEFAULT;
+ hdr->options |= 0 << 3;
+ }
if (image_ver == 0)
((struct main_hdr_v0 *)img)->nandeccmode = IBR_HDR_ECC_DISABLED;
hdr->nandpagesize = 0;
}
if (baudrate) {
- uint32_t codesz = sizeof(kwboot_baud_code);
- void *code;
-
if (image_ver == 0) {
fprintf(stderr,
"Cannot inject code for changing baudrate into v0 image header\n");
*/
kwboot_printv("Injecting binary header code for changing baudrate to %d Bd\n",
baudrate);
-
- code = kwboot_add_bin_ohdr_v1(img, size, codesz);
- _copy_baudrate_change_code(hdr, code, 0, 115200, baudrate);
+ _inject_baudrate_change_code(img, size, 0, 115200, baudrate);
/*
* Now inject code that changes the baudrate back to 115200 Bd.
- * This code is prepended to the data part of the image, so it
- * is executed before U-Boot proper.
+ * This code is appended after the data part of the image, and
+ * execaddr is changed so that it is executed before U-Boot
+ * proper.
*/
kwboot_printv("Injecting code for changing baudrate back\n");
+ _inject_baudrate_change_code(img, size, 1, baudrate, 115200);
- codesz += sizeof(kwboot_pre_baud_code);
- code = kwboot_img_grow_data_left(img, size, codesz);
- _copy_baudrate_change_code(hdr, code, 1, baudrate, 115200);
+ /* Update the 32-bit data checksum */
+ *kwboot_img_csum32_ptr(img) = kwboot_img_csum32(img);
/* recompute header size */
hdrsz = kwbheader_size(hdr);
}
if (hdrsz % KWBOOT_XM_BLKSZ) {
- size_t offset = (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) %
- KWBOOT_XM_BLKSZ;
+ size_t grow = KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ;
if (is_secure) {
fprintf(stderr, "Cannot align image with secure header\n");
}
kwboot_printv("Aligning image header to Xmodem block size\n");
- kwboot_img_grow_hdr(img, size, offset);
+ kwboot_img_grow_hdr(img, size, grow);
}
hdr->checksum = kwboot_hdr_csum8(hdr) - csum;
static void
kwboot_usage(FILE *stream, char *progname)
{
- fprintf(stream, "kwboot version %s\n", PLAIN_VERSION);
fprintf(stream,
"Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n",
progname);
after_img_rsv = KWBOOT_XM_BLKSZ;
baudrate = 115200;
+ printf("kwboot version %s\n", PLAIN_VERSION);
+
kwboot_verbose = isatty(STDOUT_FILENO);
do {
baudrate = 0;
else
/* ensure we have enough space for baudrate change code */
- after_img_rsv += KWBOOT_BAUDRATE_BIN_HEADER_SZ +
- sizeof(kwboot_pre_baud_code) +
- sizeof(kwboot_baud_code);
+ after_img_rsv += sizeof(struct opt_hdr_v1) + 8 + 16 +
+ sizeof(kwboot_baud_code_binhdr_pre) +
+ sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_binhdr_post) +
+ KWBOOT_XM_BLKSZ +
+ sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_data_jump) +
+ KWBOOT_XM_BLKSZ;
if (imgpath) {
img = kwboot_read_image(imgpath, &size, after_img_rsv);
projects / platform / kernel / u-boot.git / commitdiff