select CPU_V7M
select DM
select DM_SERIAL
- select GPIO_EXTRA_HEADER
imply CMD_DM
config ARCH_STI
select DM_GPIO
select DM_RESET
select DM_SERIAL
- select GPIO_EXTRA_HEADER
select MISC
select OF_CONTROL
select OF_LIBFDT
pinctrl1 = &pinctrl_z;
};
+ binman: binman {
+ multiple-images;
+ };
+
clocks {
u-boot,dm-pre-reloc;
};
resets = <&rcc UART8_R>;
};
+#if defined(CONFIG_STM32MP15x_STM32IMAGE)
+&binman {
+ u-boot-stm32 {
+ filename = "u-boot.stm32";
+ mkimage {
+ args = "-T stm32image -a 0xC0100000 -e 0xC0100000";
+ u-boot {
+ };
+ };
+ };
+};
+#endif
+
+#if defined(CONFIG_SPL)
+&binman {
+ spl-stm32 {
+ filename = "u-boot-spl.stm32";
+ mkimage {
+ args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500";
+ u-boot-spl {
+ };
+ };
+ };
+};
+#endif
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
};
};
-&gpiof {
- snor-nwp {
- gpio-hog;
- gpios = <7 0>;
- output-high;
- line-name = "spi-nor-nwp";
- };
-};
-
&i2c4 {
u-boot,dm-pre-reloc;
};
u-boot,dm-spl;
};
-&gpiof {
- snor-nwp {
- gpio-hog;
- gpios = <7 0>;
- output-high;
- line-name = "spi-nor-nwp";
- };
-};
-
&i2c4 {
u-boot,dm-pre-reloc;
};
cs42l51_tx_endpoint: endpoint@0 {
reg = <0>;
remote-endpoint = <&sai2a_endpoint>;
- frame-master;
- bitclock-master;
+ frame-master = <&cs42l51_tx_endpoint>;
+ bitclock-master = <&cs42l51_tx_endpoint>;
};
cs42l51_rx_endpoint: endpoint@1 {
reg = <1>;
remote-endpoint = <&sai2b_endpoint>;
- frame-master;
- bitclock-master;
+ frame-master = <&cs42l51_rx_endpoint>;
+ bitclock-master = <&cs42l51_rx_endpoint>;
};
};
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-
-#include <asm/arch-stm32/gpio.h>
-
-#endif /* _STM32_GPIO_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-
-#include <asm/arch-stm32/gpio.h>
-
-#endif /* _STM32_GPIO_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-
-#include <asm/arch-stm32/gpio.h>
-
-#endif /* _STM32_GPIO_H_ */
config STM32MP15x
bool "Support STMicroelectronics STM32MP15x Soc"
- select ARCH_SUPPORT_PSCI if !TFABOOT
- select ARM_SMCCC if TFABOOT
+ select ARCH_SUPPORT_PSCI
+ select BINMAN
select CPU_V7A
- select CPU_V7_HAS_NONSEC if !TFABOOT
+ select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select OF_BOARD_SETUP
select PINCTRL_STM32
select STM32_SERIAL
select SYS_ARCH_TIMER
imply CMD_NVEDIT_INFO
- imply SYSRESET_PSCI if TFABOOT
- imply SYSRESET_SYSCON if !TFABOOT
help
support of STMicroelectronics SOC STM32MP15x family
STM32MP157, STM32MP153 or STM32MP151
config DDR_CACHEABLE_SIZE
hex "Size of the DDR marked cacheable in pre-reloc stage"
- default 0x10000000 if TFABOOT
default 0x40000000
help
Define the size of the DDR marked as cacheable in U-Boot
u32 tmp_data = 0;
int ret;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_OTP,
otp, 0, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_SHADOW,
otp, 0, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_PROG_OTP,
otp, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRITE_SHADOW,
otp, val);
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
{
- if (!IS_ENABLED(CONFIG_TFABOOT))
+ if (!IS_ENABLED(CONFIG_ARM_SMCCC) || IS_ENABLED(CONFIG_SPL_BUILD))
return -ENOTSUPP;
if (val == 1)
/*
* update unlocked shadow for OTP cleared by the rom code
- * only executed in U-Boot proper when TF-A is not used
+ * only executed in SPL, it is done in TF-A for TFABOOT
*/
-
- if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
plat = dev_get_plat(dev);
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
-
config CMD_STM32PROG
bool "command stm32prog for STM32CudeProgrammer"
select DFU
help
activate the command "stm32prog serial" for STM32MP soc family
with the tools STM32CubeProgrammer using U-Boot serial device
- and UART protocol.
\ No newline at end of file
+ and UART protocol.
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-#
-# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
-#
-
-ifndef CONFIG_SPL
-INPUTS-$(CONFIG_STM32MP15x_STM32IMAGE) += u-boot.stm32
-else
-ifdef CONFIG_SPL_BUILD
-INPUTS-y += u-boot-spl.stm32
-endif
-endif
-
-MKIMAGEFLAGS_u-boot.stm32 = -T stm32image -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
-
-u-boot.stm32: MKIMAGEOUTPUT = u-boot.stm32.log
-
-u-boot.stm32: u-boot.bin FORCE
- $(call if_changed,mkimage)
-
-MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
-
-spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log
-
-spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage)
-
-u-boot-spl.stm32 : spl/u-boot-spl.stm32
- $(call if_changed,copy)
struct lmb lmb;
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-#ifndef CONFIG_TFABOOT
static void security_init(void)
{
/* Disable the backup domain write protection */
writel(BIT(0), RCC_MP_AHB5ENSETR);
writel(0x0, GPIOZ_SECCFGR);
}
-#endif /* CONFIG_TFABOOT */
/*
* Debug init
* done in TF-A for TRUSTED boot and
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
*/
- if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
+ if (bsec_dbgswenable()) {
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
}
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
dbgmcu_init();
+
+ /* force probe of BSEC driver to shadow the upper OTP */
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
+ if (ret)
+ log_warning("BSEC probe failed: %d\n", ret);
}
-#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
-#if !defined(CONFIG_TFABOOT) && \
- (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* get bootmode from ROM code boot context: saved in TAMP register */
static void update_bootmode(void)
{
TAMP_BOOT_MODE_MASK,
boot_mode << TAMP_BOOT_MODE_SHIFT);
}
-#endif
u32 get_bootmode(void)
{
/* early armv7 timer init: needed for polling */
timer_init();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-#ifndef CONFIG_TFABOOT
- security_init();
- update_bootmode();
-#endif
- /* Reset Coprocessor state unless it wakes up from Standby power mode */
- if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
- writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
- writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ security_init();
+ update_bootmode();
+ }
+/* reset copro state in SPL, when used, or in U-Boot */
+ if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Reset Coprocessor state unless it wakes up from Standby power mode */
+ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
+ writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
+ writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
+ }
}
-#endif
boot_mode = get_bootmode();
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#if defined(CONFIG_DEBUG_UART) && \
- !defined(CONFIG_TFABOOT) && \
- (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- else
+ else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
debug_uart_init();
-#endif
return 0;
}
soc_type[type], soc_pkg[pkg], soc_rev[rev]);
}
-#if defined(CONFIG_DISPLAY_CPUINFO)
+/* used when CONFIG_DISPLAY_CPUINFO is activated */
int print_cpuinfo(void)
{
char name[SOC_NAME_SIZE];
return 0;
}
-#endif /* CONFIG_DISPLAY_CPUINFO */
static void setup_boot_mode(void)
{
*/
__weak int setup_mac_address(void)
{
-#if defined(CONFIG_NET)
int ret;
int i;
u32 otp[2];
uchar enetaddr[6];
struct udevice *dev;
+ if (!IS_ENABLED(CONFIG_NET))
+ return 0;
+
/* MAC already in environment */
if (eth_env_get_enetaddr("ethaddr", enetaddr))
return 0;
ret = eth_env_set_enetaddr("ethaddr", enetaddr);
if (ret)
log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
-#endif
return 0;
}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2016
- * Vikas Manocha, <vikas.manocha@st.com>
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-#include <asm/gpio.h>
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- u8 port;
- u8 pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
- unsigned int gpio_range;
-};
-
-int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
-
-#endif /* _STM32_GPIO_H_ */
default "dhelectronics"
config SYS_CONFIG_NAME
- default "dh_stm32mp1"
+ default "stm32mp15_dh_dhsom"
config ENV_SECT_SIZE
default 0x10000 if ENV_IS_IN_SPI_FLASH
F: board/dhelectronics/dh_stm32mp1/
F: configs/stm32mp15_dhcom_basic_defconfig
F: configs/stm32mp15_dhcor_basic_defconfig
-F: include/configs/stm32mp1.h
+F: include/configs/stm32mp15_dh_dhsom.h
obj-y += ../../st/common/stpmic1.o board.o
-obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += ../../st/common/stm32mp_mtdparts.o
obj-$(CONFIG_SET_DFU_ALT_INFO) += ../../st/common/stm32mp_dfu.o
default "engicam"
config SYS_CONFIG_NAME
- default "stm32mp1"
+ default "stm32mp15_common"
endif
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/syscfg.h>
#include <asm/gpio.h>
#include <linux/delay.h>
default "st"
config SYS_CONFIG_NAME
- default "stm32mp1"
+ default "stm32mp15_st_common"
source "board/st/common/Kconfig"
endif
F: configs/stm32mp15_defconfig
F: configs/stm32mp15_basic_defconfig
F: configs/stm32mp15_trusted_defconfig
-F: include/configs/stm32mp1.h
+F: include/configs/stm32mp15_common.h
+F: include/configs/stm32mp15_st_common.h
if (IS_ENABLED(CONFIG_DM_REGULATOR))
regulators_enable_boot_on(_DEBUG);
- if (!IS_ENABLED(CONFIG_TFABOOT))
+ /*
+ * sysconf initialisation done only when U-Boot is running in secure
+ * done in TF-A for TFABOOT.
+ */
+ if (IS_ENABLED(CONFIG_ARMV7_NONSEC))
sysconf_init();
if (CONFIG_IS_ENABLED(LED))
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x4C0000
CONFIG_TYPEC_STUSB160X=y
+# CONFIG_ARMV7_NONSEC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)"
# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=10000000
+CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_STM32_ADC=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_DFU_VIRT=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
-CONFIG_SYS_MTDPARTS_RUNTIME=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_DM_VIDEO=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
-CONFIG_VIDEO_STM32=y
-CONFIG_VIDEO_STM32_DSI=y
-CONFIG_VIDEO_STM32_MAX_XRES=1280
-CONFIG_VIDEO_STM32_MAX_YRES=800
-CONFIG_VIDEO_BMP_RLE8=y
-CONFIG_BMP_16BPP=y
-CONFIG_BMP_24BPP=y
-CONFIG_BMP_32BPP=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)"
# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=10000000
+CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_VIRT=y
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_DM_VIDEO=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
-CONFIG_VIDEO_STM32=y
-CONFIG_VIDEO_STM32_DSI=y
-CONFIG_VIDEO_STM32_MAX_XRES=1280
-CONFIG_VIDEO_STM32_MAX_YRES=800
-CONFIG_VIDEO_BMP_RLE8=y
-CONFIG_BMP_16BPP=y
-CONFIG_BMP_24BPP=y
-CONFIG_BMP_32BPP=y
+CONFIG_FAT_WRITE=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_STM32MP15x_STM32IMAGE=y
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
+# CONFIG_ARMV7_NONSEC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_TFABOOT
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_BUILD)
/* activate clock tree initialization in the driver */
#define STM32MP1_CLOCK_TREE_INIT
#endif
-#endif
#define MAX_HSI_HZ 64000000
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include "stm32_gpio_priv.h"
+
#define STM32_GPIOS_PER_BANK 16
#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
-#ifndef _GPIO_H_
-#define _GPIO_H_
+#ifndef _STM32_GPIO_PRIV_H_
+#define _STM32_GPIO_PRIV_H_
enum stm32_gpio_mode {
STM32_GPIO_MODE_IN = 0,
int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
-#endif /* _GPIO_H_ */
+#endif /* _STM32_GPIO_PRIV_H_ */
#include <hwspinlock.h>
#include <log.h>
#include <malloc.h>
-#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/libfdt.h>
+#include "../gpio/stm32_gpio_priv.h"
+
#define MAX_PINS_ONE_IP 70
#define MODE_BITS_MASK 3
#define OSPEED_MASK 3
priv->info.base = STM32_DDR_BASE;
-#if !defined(CONFIG_TFABOOT) && \
- (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- priv->info.size = 0;
- ret = stm32mp1_ddr_setup(dev);
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ priv->info.size = 0;
+ ret = stm32mp1_ddr_setup(dev);
+
+ return log_ret(ret);
+ }
- return log_ret(ret);
-#else
ofnode node = stm32mp1_ddr_get_ofnode(dev);
priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
return 0;
-#endif
}
static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
#include <panel.h>
#include <video.h>
#include <asm/io.h>
-#include <asm/arch/gpio.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <video.h>
#include <video_bridge.h>
#include <asm/io.h>
-#include <asm/arch/gpio.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <video.h>
#include <video_bridge.h>
#include <asm/io.h>
-#include <asm/arch/gpio.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
* Configuration settings for the STM32MP15x CPU
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_STM32MP15_COMMMON_H
+#define __CONFIG_STM32MP15_COMMMON_H
#include <linux/sizes.h>
#include <asm/arch/stm32.h>
-#ifndef CONFIG_TFABOOT
+#ifdef CONFIG_ARMV7_PSCI
/* PSCI support */
#define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE
#define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE
BOOT_TARGET_PXE(func)
/*
- * bootcmd for stm32mp1:
+ * default bootcmd for stm32mp1:
* for serial/usb: execute the stm32prog command
- * for mmc boot (eMMC, SD card), boot only on the same device
- * for nand or spi-nand boot, boot with on ubifs partition on UBI partition
- * for nor boot, use the default order
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for nand or spi-nand boot, distro boot with ubifs on UBI partition
+ * for nor boot, use the default distro order in ${boot_targets}
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT
/* eMMC default partitions for fastboot command: oem format */
-#define PARTS_DEFAULT \
+#define STM32MP_PARTS_DEFAULT \
"partitions=" \
"name=ssbl,size=2M;" \
"name=bootfs,size=64MB,bootable;" \
"name=rootfs,size=746M;" \
"name=userfs,size=-\0"
#else
-#define PARTS_DEFAULT
+#define STM32MP_PARTS_DEFAULT
#endif
+#define STM32MP_EXTRA \
+ "altbootcmd=run bootcmd\0" \
+ "env_check=if env info -p -d -q; then env save; fi\0" \
+ "boot_net_usb_start=true\0"
+
#include <config_distro_bootcmd.h>
/*
* 1M fdt, 1M script, 1M pxe and 1M for overlay
* and the ramdisk at the end.
*/
+#define __KERNEL_ADDR_R __stringify(0xc2000000)
+#define __FDT_ADDR_R __stringify(0xc4000000)
+#define __SCRIPT_ADDR_R __stringify(0xc4100000)
+#define __PXEFILE_ADDR_R __stringify(0xc4200000)
+#define __FDTOVERLAY_ADDR_R __stringify(0xc4300000)
+#define __RAMDISK_ADDR_R __stringify(0xc4400000)
+
+#define STM32MP_MEM_LAYOUT \
+ "kernel_addr_r=" __KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" __FDT_ADDR_R "\0" \
+ "scriptaddr=" __SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
+ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
+ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0xc2000000\0" \
- "fdt_addr_r=0xc4000000\0" \
- "scriptaddr=0xc4100000\0" \
- "pxefile_addr_r=0xc4200000\0" \
- "fdtoverlay_addr_r=0xc4300000\0" \
- "ramdisk_addr_r=0xc4400000\0" \
- "altbootcmd=run bootcmd\0" \
- "env_check=if env info -p -d -q; then env save; fi\0" \
+ STM32MP_MEM_LAYOUT \
STM32MP_BOOTCMD \
- PARTS_DEFAULT \
+ STM32MP_PARTS_DEFAULT \
BOOTENV \
- "boot_net_usb_start=true\0"
+ STM32MP_EXTRA
#endif /* ifndef CONFIG_SPL_BUILD */
#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_STM32MP15_COMMMON_H */
* Configuration settings for the DH STM32MP15x SoMs
*/
-#ifndef __CONFIG_DH_STM32MP1_H__
-#define __CONFIG_DH_STM32MP1_H__
+#ifndef __CONFIG_STM32MP15_DH_DHSOM_H__
+#define __CONFIG_STM32MP15_DH_DHSOM_H__
-#include <configs/stm32mp1.h>
+#include <configs/stm32mp15_common.h>
#define CONFIG_SPL_TARGET "u-boot.itb"
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STMicroelectonics STM32MP15x boards
+ */
+
+#ifndef __CONFIG_STM32MP15_ST_COMMON_H__
+#define __CONFIG_STM32MP15_ST_COMMON_H__
+
+#include <configs/stm32mp15_common.h>
+
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
+/*
+ * default bootcmd for stm32mp1 STMicroelectronics boards:
+ * for serial/usb: execute the stm32prog command
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for nand or spi-nand boot, distro boot with ubifs on UBI partition
+ * for nor boot, distro boot on SD card = mmc0 ONLY !
+ */
+#define ST_STM32MP1_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+ "then stm32prog ${boot_device} ${boot_instance}; " \
+ "else " \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "if test ${boot_device} = nand ||" \
+ " test ${boot_device} = spi-nand ;" \
+ "then env set boot_targets ubifs0; fi;" \
+ "if test ${boot_device} = nor;" \
+ "then env set boot_targets mmc0; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ ST_STM32MP1_BOOTCMD \
+ STM32MP_PARTS_DEFAULT \
+ BOOTENV \
+ STM32MP_EXTRA
+
+#endif
+#endif
projects / platform / kernel / u-boot.git / commitdiff