OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
+OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
+
+spl/u-boot-spl.hex: spl/u-boot-spl FORCE
+ $(call if_changed,objcopy)
+
binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
* Copyright (C) Adam Ford
*/
-/ {
- chosen {
- stdout-path = &serial2;
- };
-
- aliases {
- i2c0 = &i2c0;
- spi0 = &spi1;
- };
-};
-
&flash {
compatible = "m25p64", "spi-flash";
};
compatible = "ti,da850-evm", "ti,da850";
model = "DA850/AM1808/OMAP-L138 EVM";
- soc@1c00000 {
- pmx_core: pinmux@14120 {
- status = "okay";
-
- mcasp0_pins: pinmux_mcasp0_pins {
- pinctrl-single,bits = <
- /*
- * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
- * AFSR, AMUTE
- */
- 0x00 0x11111111 0xffffffff
- /* AXR11, AXR12 */
- 0x04 0x00011000 0x000ff000
- >;
- };
- nand_pins: nand_pins {
- pinctrl-single,bits = <
- /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
- 0x1c 0x10110110 0xf0ff0ff0
- /*
- * EMA_D[0], EMA_D[1], EMA_D[2],
- * EMA_D[3], EMA_D[4], EMA_D[5],
- * EMA_D[6], EMA_D[7]
- */
- 0x24 0x11111111 0xffffffff
- /* EMA_A[1], EMA_A[2] */
- 0x30 0x01100000 0x0ff00000
- >;
- };
- };
- serial0: serial@42000 {
- status = "okay";
- };
- serial1: serial@10c000 {
- status = "okay";
- };
- serial2: serial@10d000 {
- status = "okay";
- };
- rtc0: rtc@23000 {
- status = "okay";
- };
- i2c0: i2c@22000 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
-
- tps: tps@48 {
- reg = <0x48>;
- };
- tlv320aic3106: tlv320aic3106@18 {
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3106";
- reg = <0x18>;
- status = "okay";
-
- /* Regulators */
- IOVDD-supply = <&vdcdc2_reg>;
- /* Derived from VBAT: Baseboard 3.3V / 1.8V */
- AVDD-supply = <&vbat>;
- DRVDD-supply = <&vbat>;
- DVDD-supply = <&vbat>;
- };
- tca6416: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
- wdt: wdt@21000 {
- status = "okay";
- };
- mmc0: mmc@40000 {
- max-frequency = <50000000>;
- bus-width = <4>;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
- };
- spi1: spi@30e000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
- flash: m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p64";
- spi-max-frequency = <30000000>;
- m25p,fast-read;
- reg = <0>;
- partition@0 {
- label = "U-Boot-SPL";
- reg = <0x00000000 0x00010000>;
- read-only;
- };
- partition@1 {
- label = "U-Boot";
- reg = <0x00010000 0x00080000>;
- read-only;
- };
- partition@2 {
- label = "U-Boot-Env";
- reg = <0x00090000 0x00010000>;
- read-only;
- };
- partition@3 {
- label = "Kernel";
- reg = <0x000a0000 0x00280000>;
- };
- partition@4 {
- label = "Filesystem";
- reg = <0x00320000 0x00400000>;
- };
- partition@5 {
- label = "MAC-Address";
- reg = <0x007f0000 0x00010000>;
- read-only;
- };
- };
- };
- mdio: mdio@224000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
- bus_freq = <2200000>;
- };
- eth0: ethernet@220000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mii_pins>;
- };
- gpio: gpio@226000 {
- status = "okay";
- };
+ chosen {
+ stdout-path = &serial2;
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ ethernet0 = ð0;
+ spi0 = &spi1;
};
+
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
};
};
+&pmx_core {
+ status = "okay";
+
+ mcasp0_pins: pinmux_mcasp0_pins {
+ pinctrl-single,bits = <
+ /*
+ * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
+ * AFSR, AMUTE
+ */
+ 0x00 0x11111111 0xffffffff
+ /* AXR11, AXR12 */
+ 0x04 0x00011000 0x000ff000
+ >;
+ };
+ nand_pins: nand_pins {
+ pinctrl-single,bits = <
+ /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
+ 0x1c 0x10110110 0xf0ff0ff0
+ /*
+ * EMA_D[0], EMA_D[1], EMA_D[2],
+ * EMA_D[3], EMA_D[4], EMA_D[5],
+ * EMA_D[6], EMA_D[7]
+ */
+ 0x24 0x11111111 0xffffffff
+ /* EMA_A[1], EMA_A[2] */
+ 0x30 0x01100000 0x0ff00000
+ >;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ tps: tps@48 {
+ reg = <0x48>;
+ };
+ tlv320aic3106: tlv320aic3106@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x18>;
+ status = "okay";
+
+ /* Regulators */
+ IOVDD-supply = <&vdcdc2_reg>;
+ /* Derived from VBAT: Baseboard 3.3V / 1.8V */
+ AVDD-supply = <&vbat>;
+ DRVDD-supply = <&vbat>;
+ DVDD-supply = <&vbat>;
+ };
+ tca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&wdt {
+ status = "okay";
+};
+
+&mmc0 {
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>;
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ spi-max-frequency = <30000000>;
+ m25p,fast-read;
+ reg = <0>;
+ partition@0 {
+ label = "U-Boot-SPL";
+ reg = <0x00000000 0x00010000>;
+ read-only;
+ };
+ partition@1 {
+ label = "U-Boot";
+ reg = <0x00010000 0x00080000>;
+ read-only;
+ };
+ partition@2 {
+ label = "U-Boot-Env";
+ reg = <0x00090000 0x00010000>;
+ read-only;
+ };
+ partition@3 {
+ label = "Kernel";
+ reg = <0x000a0000 0x00280000>;
+ };
+ partition@4 {
+ label = "Filesystem";
+ reg = <0x00320000 0x00400000>;
+ };
+ partition@5 {
+ label = "MAC-Address";
+ reg = <0x007f0000 0x00010000>;
+ read-only;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ bus_freq = <2200000>;
+};
+
+ð0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mii_pins>;
+};
+
+&gpio {
+ status = "okay";
+};
+
/include/ "tps6507x.dtsi"
&tps {
};
};
+&usb_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
&vpif {
pinctrl-names = "default";
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
-#ifdef CONFIG_SPL_I2C_SUPPORT
+#if defined(CONFIG_SPL_I2C_SUPPORT) && !defined(CONFIG_DM_I2C)
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
#ifndef _SDRAM_S10_H_
#define _SDRAM_S10_H_
-unsigned long sdram_calculate_size(void);
+phys_size_t sdram_calculate_size(void);
int sdram_mmr_init_full(unsigned int sdr_phy_reg);
int sdram_calibration_full(void);
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
+
+#ifdef CONFIG_FSL_ESDHC
+ /* eSDHC pin as faster speed */
+ out_8(&gpio->srcr_sdhc, 0x03);
+
+ /* All esdhc pins as SD */
+ out_8(&gpio->par_sdhch, 0xff);
+ out_8(&gpio->par_sdhcl, 0xff);
+#endif
#endif /* CONFIG_MCF5441x */
#ifdef CONFIG_MCF5445x
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
#endif
}
+
#endif
temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
gd->bus_clk = vco / temp; /* bus clock */
+ temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
+ gd->arch.sdhc_clk = vco / temp;
}
#endif
#include <asm/types.h>
#ifdef __GNUC__
-#define __sw16(x) \
- ((__u16)( \
- (((__u16)(x) & (__u16)0x00ffU) << 8) | \
- (((__u16)(x) & (__u16)0xff00U) >> 8) ))
-#define __sw32(x) \
- ((__u32)( \
- (((__u32)(x)) << 24) | \
- (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
- (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
- (((__u32)(x)) >> 24) ))
+
+static inline __u32 __sw32(__u32 x)
+{
+ __u32 v = x;
+
+ return v << 24 |
+ (v & (__u32)0x0000ff00UL) << 8 |
+ (v & (__u32)0x00ff0000UL) >> 8 |
+ v >> 24;
+}
+
+static inline __u16 __sw16(__u16 x)
+{
+ __u16 v = x;
+
+ return (v & (__u16)0x00ffU) << 8 |
+ (v & (__u16)0xff00U) >> 8;
+}
static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
- unsigned result = *addr;
- return __sw16(result);
+ return __sw16(*addr);
}
static __inline__ void st_le16(volatile unsigned short *addr,
static __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
- unsigned result = *addr;
- return __sw32(result);
+ return __sw32(*addr);
}
static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
unsigned long vco_clk;
unsigned long flb_clk;
#endif
+#ifdef CONFIG_MCF5441x
+ unsigned long sdhc_clk;
+#endif
};
#include <asm-generic/global_data.h>
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CONFIG_SYS_NUM_IRQS (192)
#endif /* CONFIG_M54418 */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#if !defined(CONFIG_CPU_SH2)
+#include <asm/processor.h>
+
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
+#endif
+
#endif
#define PYDR 0xA405016A
#define PZDR 0xA405016C
-/* Ether */
-#define EDMR 0xA4600000
-
/* UBC */
/* H-UDI */
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <sh_tmu.h>
-#define TCR_TPSC 0x07
+#if defined(CONFIG_CPU_SH3)
+#define TSTR 0x2
+#define TCR0 0xc
+#endif /* CONFIG_CPU_SH3 */
-static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
+#define TSTR 0x4
+#define TCR0 0x10
+#endif /* CONFIG_CPU_SH4 */
-unsigned long get_tbclk(void)
-{
- u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
- return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
-}
-
-unsigned long timer_read_counter(void)
-{
- return ~readl(&tmu->tcnt0);
-}
-
-static void tmu_timer_start(unsigned int timer)
-{
- if (timer > 2)
- return;
- writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
-}
-
-static void tmu_timer_stop(unsigned int timer)
-{
- if (timer > 2)
- return;
- writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
-}
+#define TCR_TPSC 0x07
+#define TSTR_STR0 BIT(0)
int timer_init(void)
{
- u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
- writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
-
- tmu_timer_stop(0);
- tmu_timer_start(0);
+ writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0);
+ writeb(readb(TMU_BASE + TSTR) & ~TSTR_STR0, TMU_BASE + TSTR);
+ writeb(readb(TMU_BASE + TSTR) | TSTR_STR0, TMU_BASE + TSTR);
return 0;
}
#
# Copyright (c) 2017 Intel Corporation
-obj-y += car.o tangier.o sdram.o sysreset.o
+obj-y += car.o tangier.o sdram.o sysreset.o pinmux.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Emlid Limited
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/read.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/scu.h>
+#include <linux/io.h>
+
+#define BUFCFG_OFFSET 0x100
+
+#define MRFLD_FAMILY_LEN 0x400
+
+/* These are taken from Linux kernel */
+#define MRFLD_PINMODE_MASK 0x07
+
+#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
+
+struct mrfld_family {
+ unsigned int family_number;
+ unsigned int pin_base;
+ size_t npins;
+ void __iomem *regs;
+};
+
+#define MRFLD_FAMILY(b, s, e) \
+ { \
+ .family_number = (b), \
+ .pin_base = (s), \
+ .npins = (e) - (s) + 1, \
+ }
+
+/* Now we only support I2C family of pins */
+static struct mrfld_family mrfld_families[] = {
+ MRFLD_FAMILY(7, 101, 114),
+};
+
+struct mrfld_pinctrl {
+ const struct mrfld_family *families;
+ size_t nfamilies;
+};
+
+static const struct mrfld_family *
+mrfld_get_family(struct mrfld_pinctrl *mp, unsigned int pin)
+{
+ const struct mrfld_family *family;
+ unsigned int i;
+
+ for (i = 0; i < mp->nfamilies; i++) {
+ family = &mp->families[i];
+ if (pin >= family->pin_base &&
+ pin < family->pin_base + family->npins)
+ return family;
+ }
+
+ pr_err("failed to find family for pin %u\n", pin);
+ return NULL;
+}
+
+static void __iomem *
+mrfld_get_bufcfg(struct mrfld_pinctrl *pinctrl, unsigned int pin)
+{
+ const struct mrfld_family *family;
+ unsigned int bufno;
+
+ family = mrfld_get_family(pinctrl, pin);
+ if (!family)
+ return NULL;
+
+ bufno = pin_to_bufno(family, pin);
+
+ return family->regs + BUFCFG_OFFSET + bufno * 4;
+}
+
+static void
+mrfld_setup_families(void *base_addr,
+ struct mrfld_family *families, unsigned int nfam)
+{
+ for (int i = 0; i < nfam; i++) {
+ struct mrfld_family *family = &families[i];
+
+ family->regs = base_addr +
+ family->family_number * MRFLD_FAMILY_LEN;
+ }
+}
+
+static int mrfld_pinconfig_protected(unsigned int pin, u32 mask, u32 bits)
+{
+ struct mrfld_pinctrl *pinctrl;
+ struct udevice *dev;
+ void __iomem *bufcfg;
+ u32 v, value;
+ int ret;
+
+ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+ if (ret)
+ return ret;
+
+ pinctrl = dev_get_priv(dev);
+
+ bufcfg = mrfld_get_bufcfg(pinctrl, pin);
+ if (!bufcfg)
+ return -EINVAL;
+
+ value = readl(bufcfg);
+
+ v = (value & ~mask) | (bits & mask);
+
+ debug("scu: v: 0x%x p: 0x%x bits: %d, mask: %d bufcfg: 0x%p\n",
+ v, (u32)bufcfg, bits, mask, bufcfg);
+
+ ret = scu_ipc_raw_command(IPCMSG_INDIRECT_WRITE, 0, &v, 4,
+ NULL, 0, (u32)bufcfg, 0);
+ if (ret)
+ pr_err("Failed to set mode via SCU for pin %u (%d)\n",
+ pin, ret);
+
+ return ret;
+}
+
+static int mrfld_pinctrl_cfg_pin(ofnode pin_node)
+{
+ bool is_protected;
+ int pad_offset;
+ int mode;
+ u32 mask;
+ int ret;
+
+ /* For now we only support just protected Family of pins */
+ is_protected = ofnode_read_bool(pin_node, "protected");
+ if (!is_protected)
+ return -ENOTSUPP;
+
+ pad_offset = ofnode_read_s32_default(pin_node, "pad-offset", -1);
+ if (pad_offset == -1)
+ return -EINVAL;
+
+ mode = ofnode_read_s32_default(pin_node, "mode-func", -1);
+ if (mode == -1)
+ return -EINVAL;
+
+ mask = MRFLD_PINMODE_MASK;
+
+ /* We don't support modes not in range 0..7 */
+ if (mode & ~mask)
+ return -ENOTSUPP;
+
+ ret = mrfld_pinconfig_protected(pad_offset, mask, mode);
+
+ return ret;
+}
+
+static int tangier_pinctrl_probe(struct udevice *dev)
+{
+ void *base_addr = syscon_get_first_range(X86_SYSCON_PINCONF);
+ struct mrfld_pinctrl *pinctrl = dev_get_priv(dev);
+ ofnode pin_node;
+ int ret;
+
+ mrfld_setup_families(base_addr, mrfld_families,
+ ARRAY_SIZE(mrfld_families));
+
+ pinctrl->families = mrfld_families;
+ pinctrl->nfamilies = ARRAY_SIZE(mrfld_families);
+
+ ofnode_for_each_subnode(pin_node, dev_ofnode(dev)) {
+ ret = mrfld_pinctrl_cfg_pin(pin_node);
+ if (ret) {
+ pr_err("%s: invalid configuration for the pin %ld\n",
+ __func__, pin_node.of_offset);
+ }
+ }
+
+ return 0;
+}
+
+static const struct udevice_id tangier_pinctrl_match[] = {
+ { .compatible = "intel,pinctrl-tangier", .data = X86_SYSCON_PINCONF },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(tangier_pinctrl) = {
+ .name = "tangier_pinctrl",
+ .id = UCLASS_SYSCON,
+ .of_match = tangier_pinctrl_match,
+ .probe = tangier_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct mrfld_pinctrl),
+};
compatible = "intel,reset-tangier";
u-boot,dm-pre-reloc;
};
+
+ pinctrl {
+ compatible = "intel,pinctrl-tangier";
+ reg = <0xff0c0000 0x8000>;
+
+ /*
+ * Initial configuration came from the firmware.
+ * Which quite likely has been used in the phones, where I2C #8,
+ * that is not part of Atom peripheral, is in use.
+ * Thus we need to override the leftover.
+ */
+ i2c6_scl@0 {
+ pad-offset = <111>;
+ mode-func = <1>;
+ protected;
+ };
+ i2c6_sda@0 {
+ pad-offset = <112>;
+ mode-func = <1>;
+ protected;
+ };
+ };
};
}
}
+ Device (I2C6)
+ {
+ Name (_ADR, 0x00090001)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA_VISIBLE)
+ }
+ }
+
Device (GPIO)
{
Name (_ADR, 0x000c0000)
#define _X86_ASM_SCU_IPC_H_
/* IPC defines the following message types */
+#define IPCMSG_INDIRECT_READ 0x02
+#define IPCMSG_INDIRECT_WRITE 0x05
#define IPCMSG_WARM_RESET 0xf0
#define IPCMSG_COLD_RESET 0xf1
#define IPCMSG_SOFT_RESET 0xf2
/* Issue commands to the SCU with or without data */
int scu_ipc_simple_command(u32 cmd, u32 sub);
int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen);
+int scu_ipc_raw_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out,
+ int outlen, u32 dptr, u32 sptr);
#endif /* _X86_ASM_SCU_IPC_H_ */
}
/**
+ * scu_ipc_raw_command() - IPC command with data and pointers
+ * @cmd: IPC command code
+ * @sub: IPC command sub type
+ * @in: input data of this IPC command
+ * @inlen: input data length in dwords
+ * @out: output data of this IPC command
+ * @outlen: output data length in dwords
+ * @dptr: data writing to SPTR register
+ * @sptr: data writing to DPTR register
+ *
+ * Send an IPC command to SCU with input/output data and source/dest pointers.
+ *
+ * Return: an IPC error code or 0 on success.
+ */
+int scu_ipc_raw_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out,
+ int outlen, u32 dptr, u32 sptr)
+{
+ int inbuflen = DIV_ROUND_UP(inlen, 4);
+ struct udevice *dev;
+ struct scu *scu;
+ int ret;
+
+ ret = syscon_get_by_driver_data(X86_SYSCON_SCU, &dev);
+ if (ret)
+ return ret;
+
+ scu = dev_get_priv(dev);
+
+ /* Up to 16 bytes */
+ if (inbuflen > 4)
+ return -EINVAL;
+
+ writel(dptr, &scu->regs->dptr);
+ writel(sptr, &scu->regs->sptr);
+
+ /*
+ * SRAM controller doesn't support 8-bit writes, it only
+ * supports 32-bit writes, so we have to copy input data into
+ * the temporary buffer, and SCU FW will use the inlen to
+ * determine the actual input data length in the temporary
+ * buffer.
+ */
+
+ u32 inbuf[4] = {0};
+
+ memcpy(inbuf, in, inlen);
+
+ return scu_ipc_cmd(scu->regs, cmd, sub, inbuf, inlen, out, outlen);
+}
+
+/**
* scu_ipc_simple_command() - send a simple command
* @cmd: command
* @sub: sub type
return scu_ipc_check_status(scu->regs);
}
+/**
+ * scu_ipc_command - command with data
+ * @cmd: command
+ * @sub: sub type
+ * @in: input data
+ * @inlen: input length in dwords
+ * @out: output data
+ * @outlen: output length in dwords
+ *
+ * Issue a command to the SCU which involves data transfers.
+ */
int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen)
{
struct scu *scu;
F: include/configs/da850evm.h
F: configs/da850_am18xxevm_defconfig
F: configs/da850evm_defconfig
+F: configs/da850evm_nand_defconfig
F: configs/da850evm_direct_nor_defconfig
OMAPL138_LCDK BOARD
return 0;
}
+#ifndef CONFIG_DM_MMC
#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
return davinci_mmc_init(bis, &mmc_sd0);
}
#endif
+#endif
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
return 0;
}
+#ifndef CONFIG_DM_MMC
#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
return davinci_mmc_init(bis, &mmc_sd0);
}
#endif
+#endif
volatile unsigned int ctr;
u32 reset;
+#if !defined(CONFIG_DM_I2C)
#ifdef CONFIG_SYS_I2C_OMAP24XX
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
-
+#endif
omap_die_id_display();
am3517_evm_musb_init();
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
+#include <asm/omap_mmc.h>
#include <asm/mach-types.h>
#include <linux/mtd/rawnand.h>
#include <asm/omap_musb.h>
DECLARE_GLOBAL_DATA_PTR;
+/* This is only needed until SPL gets OF support */
+#ifdef CONFIG_SPL_BUILD
+static const struct ns16550_platdata omap3logic_serial = {
+ .base = OMAP34XX_UART1,
+ .reg_shift = 2,
+ .clock = V_NS16550_CLK,
+ .fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DEVICE(omap3logic_uart) = {
+ "ns16550_serial",
+ &omap3logic_serial
+};
+
+static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = {
+ .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
+ .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
+ .cfg.f_min = 400000,
+ .cfg.f_max = 52000000,
+ .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
+ .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+U_BOOT_DEVICE(am335x_mmc0) = {
+ .name = "omap_hsmmc",
+ .platdata = &omap3_logic_mmc0_platdata,
+};
+
+#endif
+
/*
* two dimensional array of strucures containining board name and Linux
* machine IDs; row it selected based on CPU column is slected based
#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
#define CPLD_DONE_DAT 0x20
-#define HIZCRB ((vu_short *)0xA405015A)
-
/* data */
#define CPLD_NOMAL_START 0xA0A80000
#define CPLD_SAFE_START 0xA0AC0000
if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
return;
- *HIZCRB = 0x0000;
+ *((vu_short *)HIZCRB) = 0x0000;
*CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
/* write CPLD data from NOR flash to device */
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
+# CONFIG_TWL4030_POWER is not set
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
+CONFIG_DM_MMC=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_PARTITIONS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_BLK=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_SYS_TEXT_BASE=0xc1080000
+CONFIG_TARGET_DA850EVM=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_BOOTDELAY=3
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CRC32_VERIFY=y
+# CONFIG_CMD_EEPROM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_GPT is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_TIME is not set
+# CONFIG_CMD_EXT4 is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand512"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand512:128k(u-boot env),512k(u-boot),128k(spl-os),8m(kernel),-(rootfs)"
+CONFIG_CMD_DIAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_NAND=y
+CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
+CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
+# CONFIG_FAT_WRITE is not set
+CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
+# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SPL_DM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_DM_I2C=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x08000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SYS_I2C_DAVINCI=y
+CONFIG_DM_MMC=y
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
* Calculate SDRAM device size based on SDRAM controller parameters.
* Size is specified in bytes.
*/
-unsigned long sdram_calculate_size(void)
+phys_size_t sdram_calculate_size(void)
{
u32 dramaddrw = hmc_readl(DRAMADDRW);
- u32 size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+ phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
#include <asm/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
+#include <dt-bindings/gpio/gpio.h>
#ifndef CONFIG_DM_GPIO
static struct gpio_registry {
static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset)
{
struct davinci_gpio_bank *bank = dev_get_priv(dev);
+ unsigned int addr;
- /* The device tree is not broken into banks but the infrastructure is
+ /*
+ * The device tree is not broken into banks but the infrastructure is
* expecting it this way, so we'll first include the 0x10 offset, then
* calculate the bank manually based on the offset.
+ * Casting 'addr' as Unsigned long is needed to make the math work.
*/
-
- return ((struct davinci_gpio *)bank->base) + 0x10 + (offset >> 5);
+ addr = ((unsigned long)(struct davinci_gpio *)bank->base) +
+ 0x10 + (0x28 * (offset >> 5));
+ return (struct davinci_gpio *)addr;
}
static int davinci_gpio_direction_input(struct udevice *dev, unsigned int offset)
{
struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
- _gpio_direction_input(base, offset);
+ /*
+ * Fetch the address based on GPIO, but only pass the masked low 32-bits
+ */
+ _gpio_direction_input(base, (offset & 0x1f));
return 0;
}
{
struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
- _gpio_direction_output(base, offset, value);
+ _gpio_direction_output(base, (offset & 0x1f), value);
return 0;
}
{
struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
- return _gpio_get_value(base, offset);
+ return _gpio_get_value(base, (offset & 0x1f));
}
static int davinci_gpio_set_value(struct udevice *dev, unsigned int offset,
{
struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
- _gpio_set_value(base, offset, value);
+ _gpio_set_value(base, (offset & 0x1f), value);
return 0;
}
return GPIOF_OUTPUT;
}
+static int davinci_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ desc->offset = args->args[0];
+
+ if (args->args[1] & GPIO_ACTIVE_LOW)
+ desc->flags = GPIOD_ACTIVE_LOW;
+ else
+ desc->flags = 0;
+ return 0;
+}
+
static const struct dm_gpio_ops gpio_davinci_ops = {
.direction_input = davinci_gpio_direction_input,
.direction_output = davinci_gpio_direction_output,
.get_value = davinci_gpio_get_value,
.set_value = davinci_gpio_set_value,
.get_function = davinci_gpio_get_function,
+ .xlate = davinci_gpio_xlate,
};
static int davinci_gpio_probe(struct udevice *dev)
#include <dm/lists.h>
#include <dm/root.h>
#include <errno.h>
+#include <reset.h>
DECLARE_GLOBAL_DATA_PTR;
#define GPIO_PORTA_EOI 0x4c
#define GPIO_EXT_PORT(p) (0x50 + (p) * 4)
+struct gpio_dwapb_priv {
+ struct reset_ctl_bulk resets;
+};
+
struct gpio_dwapb_platdata {
const char *name;
int bank;
return 0;
}
+static int dwapb_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ u32 gpio;
+
+ gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank));
+
+ if (gpio & BIT(offset))
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
static const struct dm_gpio_ops gpio_dwapb_ops = {
.direction_input = dwapb_gpio_direction_input,
.direction_output = dwapb_gpio_direction_output,
.get_value = dwapb_gpio_get_value,
.set_value = dwapb_gpio_set_value,
+ .get_function = dwapb_gpio_get_function,
};
+static int gpio_dwapb_reset(struct udevice *dev)
+{
+ int ret;
+ struct gpio_dwapb_priv *priv = dev_get_priv(dev);
+
+ ret = reset_get_bulk(dev, &priv->resets);
+ if (ret) {
+ /* Return 0 if error due to !CONFIG_DM_RESET and reset
+ * DT property is not present.
+ */
+ if (ret == -ENOENT || ret == -ENOTSUPP)
+ return 0;
+
+ dev_warn(dev, "Can't get reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_deassert_bulk(&priv->resets);
+ if (ret) {
+ reset_release_bulk(&priv->resets);
+ dev_err(dev, "Failed to reset: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int gpio_dwapb_probe(struct udevice *dev)
{
struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
struct gpio_dwapb_platdata *plat = dev->platdata;
- if (!plat)
- return 0;
+ if (!plat) {
+ /* Reset on parent device only */
+ return gpio_dwapb_reset(dev);
+ }
priv->gpio_count = plat->pins;
priv->bank_name = plat->name;
if (plat)
return 0;
- base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE) {
debug("Can't get the GPIO register base address\n");
return -ENXIO;
return ret;
}
+static int gpio_dwapb_remove(struct udevice *dev)
+{
+ struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_priv *priv = dev_get_priv(dev);
+
+ if (!plat && priv)
+ return reset_release_bulk(&priv->resets);
+
+ return 0;
+}
+
static const struct udevice_id gpio_dwapb_ids[] = {
{ .compatible = "snps,dw-apb-gpio" },
{ }
.ops = &gpio_dwapb_ops,
.bind = gpio_dwapb_bind,
.probe = gpio_dwapb_probe,
+ .remove = gpio_dwapb_remove,
+ .priv_auto_alloc_size = sizeof(struct gpio_dwapb_priv),
};
struct gpio_bank *bank = dev_get_priv(dev);
struct omap_gpio_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- int banknum;
char name[18], *str;
- banknum = plat->bank_index;
- sprintf(name, "GPIO%d_", banknum + 1);
+ sprintf(name, "gpio@%4x_", (unsigned int)plat->base);
str = strdup(name);
if (!str)
return -ENOMEM;
}
#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id omap_gpio_ids[] = {
{ .compatible = "ti,omap3-gpio" },
{ .compatible = "ti,omap4-gpio" },
{ }
};
-#if CONFIG_IS_ENABLED(OF_CONTROL)
static int omap_gpio_ofdata_to_platdata(struct udevice *dev)
{
struct omap_gpio_platdata *plat = dev_get_platdata(dev);
.name = "gpio_omap",
.id = UCLASS_GPIO,
#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .of_match = omap_gpio_ids,
.ofdata_to_platdata = of_match_ptr(omap_gpio_ofdata_to_platdata),
- .bind = dm_scan_fdt_dev,
.platdata_auto_alloc_size = sizeof(struct omap_gpio_platdata),
+#endif
#else
.bind = omap_gpio_bind,
#endif
.ops = &gpio_omap_ops,
- .of_match = omap_gpio_ids,
.probe = omap_gpio_probe,
.priv_auto_alloc_size = sizeof(struct gpio_bank),
.flags = DM_FLAG_PRE_RELOC,
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
-obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
return ops->deblock(bus);
}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip)
{
int addr;
static int i2c_post_probe(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
i2c->speed_hz = dev_read_u32_default(dev, "clock-frequency", 100000);
static int i2c_child_post_bind(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_i2c_chip *plat = dev_get_parent_platdata(dev);
if (!dev_of_valid(dev))
.id = UCLASS_I2C,
.name = "i2c",
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind = dm_scan_fdt_dev,
#endif
.post_probe = i2c_post_probe,
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Freescale i.MX28 I2C Driver
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Partly based on Linux kernel i2c-mxs.c driver:
- * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
- *
- * Which was based on a (non-working) driver which was:
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <i2c.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define MXS_I2C_MAX_TIMEOUT 1000000
-
-static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
-{
- if (adap->hwadapnr == 0)
- return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
- else
- return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
-}
-
-static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
-{
- struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
- uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
- uint32_t timing0;
-
- timing0 = readl(&i2c_regs->hw_i2c_timing0);
- /*
- * This is a reverse version of the algorithm presented in
- * i2c_set_bus_speed(). Please refer there for details.
- */
- return clk / ((((timing0 >> 16) - 3) * 2) + 38);
-}
-
-static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
-{
- struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
- /*
- * The timing derivation algorithm. There is no documentation for this
- * algorithm available, it was derived by using the scope and fiddling
- * with constants until the result observed on the scope was good enough
- * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
- * possible to assume the algorithm works for other frequencies as well.
- *
- * Note it was necessary to cap the frequency on both ends as it's not
- * possible to configure completely arbitrary frequency for the I2C bus
- * clock.
- */
- uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
- uint32_t base = ((clk / speed) - 38) / 2;
- uint16_t high_count = base + 3;
- uint16_t low_count = base - 3;
- uint16_t rcv_count = (high_count * 3) / 4;
- uint16_t xmit_count = low_count / 4;
-
- if (speed > 540000) {
- printf("MXS I2C: Speed too high (%d Hz)\n", speed);
- return -EINVAL;
- }
-
- if (speed < 12000) {
- printf("MXS I2C: Speed too low (%d Hz)\n", speed);
- return -EINVAL;
- }
-
- writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
- writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
-
- writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
- (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
- &i2c_regs->hw_i2c_timing2);
-
- return 0;
-}
-
-static void mxs_i2c_reset(struct i2c_adapter *adap)
-{
- struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
- int ret;
- int speed = mxs_i2c_get_bus_speed(adap);
-
- ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
- if (ret) {
- debug("MXS I2C: Block reset timeout\n");
- return;
- }
-
- writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
- I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
- I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
- &i2c_regs->hw_i2c_ctrl1_clr);
-
- writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
-
- mxs_i2c_set_bus_speed(adap, speed);
-}
-
-static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
-{
- struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
-
- writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
- I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
- (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
- &i2c_regs->hw_i2c_queuecmd);
-
- writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
-
- writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
- (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
- I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
-
- writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
-}
-
-static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buf, int blen, int stop)
-{
- struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
- uint32_t data, tmp;
- int i, remain, off;
- int timeout = MXS_I2C_MAX_TIMEOUT;
-
- if ((alen > 4) || (alen == 0)) {
- debug("MXS I2C: Invalid address length\n");
- return -EINVAL;
- }
-
- if (stop)
- stop = I2C_QUEUECMD_POST_SEND_STOP;
-
- writel(I2C_QUEUECMD_PRE_SEND_START |
- I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
- ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
- &i2c_regs->hw_i2c_queuecmd);
-
- data = (chip << 1) << 24;
-
- for (i = 0; i < alen; i++) {
- data >>= 8;
- data |= ((char *)&addr)[alen - i - 1] << 24;
- if ((i & 3) == 2)
- writel(data, &i2c_regs->hw_i2c_data);
- }
-
- off = i;
- for (; i < off + blen; i++) {
- data >>= 8;
- data |= buf[i - off] << 24;
- if ((i & 3) == 2)
- writel(data, &i2c_regs->hw_i2c_data);
- }
-
- remain = 24 - ((i & 3) * 8);
- if (remain)
- writel(data >> remain, &i2c_regs->hw_i2c_data);
-
- writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
-
- while (--timeout) {
- tmp = readl(&i2c_regs->hw_i2c_queuestat);
- if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
- break;
- }
-
- if (!timeout) {
- debug("MXS I2C: Failed transmitting data!\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
-{
- struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
- uint32_t tmp;
- int timeout = MXS_I2C_MAX_TIMEOUT;
-
- for (;;) {
- tmp = readl(&i2c_regs->hw_i2c_ctrl1);
- if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
- debug("MXS I2C: No slave ACK\n");
- goto err;
- }
-
- if (tmp & (
- I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
- I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
- debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
- goto err;
- }
-
- if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
- break;
-
- if (!timeout--) {
- debug("MXS I2C: Operation timed out\n");
- goto err;
- }
-
- udelay(1);
- }
-
- return 0;
-
-err:
- mxs_i2c_reset(adap);
- return 1;
-}
-
-static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
- uint addr, int alen, uint8_t *buffer,
- int len)
-{
- struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
- uint32_t tmp = 0;
- int timeout = MXS_I2C_MAX_TIMEOUT;
- int ret;
- int i;
-
- ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
- if (ret) {
- debug("MXS I2C: Failed writing address\n");
- return ret;
- }
-
- ret = mxs_i2c_wait_for_ack(adap);
- if (ret) {
- debug("MXS I2C: Failed writing address\n");
- return ret;
- }
-
- mxs_i2c_setup_read(adap, chip, len);
- ret = mxs_i2c_wait_for_ack(adap);
- if (ret) {
- debug("MXS I2C: Failed reading address\n");
- return ret;
- }
-
- for (i = 0; i < len; i++) {
- if (!(i & 3)) {
- while (--timeout) {
- tmp = readl(&i2c_regs->hw_i2c_queuestat);
- if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
- break;
- }
-
- if (!timeout) {
- debug("MXS I2C: Failed receiving data!\n");
- return -ETIMEDOUT;
- }
-
- tmp = readl(&i2c_regs->hw_i2c_queuedata);
- }
- buffer[i] = tmp & 0xff;
- tmp >>= 8;
- }
-
- return 0;
-}
-
-static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
- uint addr, int alen, uint8_t *buffer,
- int len)
-{
- int ret;
- ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
- if (ret) {
- debug("MXS I2C: Failed writing address\n");
- return ret;
- }
-
- ret = mxs_i2c_wait_for_ack(adap);
- if (ret)
- debug("MXS I2C: Failed writing address\n");
-
- return ret;
-}
-
-static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
-{
- int ret;
- ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
- if (!ret)
- ret = mxs_i2c_wait_for_ack(adap);
- mxs_i2c_reset(adap);
- return ret;
-}
-
-static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- mxs_i2c_reset(adap);
- mxs_i2c_set_bus_speed(adap, speed);
-
- return;
-}
-
-U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
- mxs_i2c_if_read, mxs_i2c_if_write,
- mxs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, 0, 0)
-U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
- mxs_i2c_if_read, mxs_i2c_if_write,
- mxs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, 0, 1)
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
{
struct omap_i2c *priv = dev_get_priv(bus);
return 0;
}
-static const struct dm_i2c_ops omap_i2c_ops = {
- .xfer = omap_i2c_xfer,
- .probe_chip = omap_i2c_probe_chip,
- .set_bus_speed = omap_i2c_set_bus_speed,
-};
-
static const struct udevice_id omap_i2c_ids[] = {
{ .compatible = "ti,omap3-i2c" },
{ .compatible = "ti,omap4-i2c" },
{ }
};
+#endif
+
+static const struct dm_i2c_ops omap_i2c_ops = {
+ .xfer = omap_i2c_xfer,
+ .probe_chip = omap_i2c_probe_chip,
+ .set_bus_speed = omap_i2c_set_bus_speed,
+};
U_BOOT_DRIVER(i2c_omap) = {
.name = "i2c_omap",
.id = UCLASS_I2C,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_i2c_ids,
.ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
+#endif
.probe = omap_i2c_probe,
.priv_auto_alloc_size = sizeof(struct omap_i2c),
.ops = &omap_i2c_ops,
#include <config.h>
#include <common.h>
-#include <command.h>
+#include <dm.h>
#include <errno.h>
#include <mmc.h>
+#include <command.h>
#include <part.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/sdmmc_defs.h>
+#include <asm-generic/gpio.h>
#define DAVINCI_MAX_BLOCKS (32)
#define WATCHDOG_COUNT (100000)
#define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
+#ifdef CONFIG_DM_MMC
+struct davinci_of_data {
+ const char *name;
+ u8 version;
+};
+
+/* Davinci MMC board definitions */
+struct davinci_mmc_priv {
+ struct davinci_mmc_regs *reg_base; /* Register base address */
+ uint input_clk; /* Input clock to MMC controller */
+ uint version; /* MMC Controller version */
+ struct gpio_desc cd_gpio; /* Card Detect GPIO */
+ struct gpio_desc wp_gpio; /* Write Protect GPIO */
+};
+
+struct davinci_mmc_plat
+{
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+#endif
+
/* Set davinci clock prescalar value based on the required clock in HZ */
+#if !CONFIG_IS_ENABLED(DM_MMC)
static void dmmc_set_clock(struct mmc *mmc, uint clock)
{
struct davinci_mmc *host = mmc->priv;
+#else
+
+static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
+{
+ struct davinci_mmc_priv *host = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#endif
struct davinci_mmc_regs *regs = host->reg_base;
uint clkrt, sysclk2, act_clock;
}
/*
- * Sends a command out on the bus. Takes the mmc pointer,
+ * Sends a command out on the bus. Takes the device pointer,
* a command pointer, and an optional data pointer.
*/
-static int
-dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct davinci_mmc *host = mmc->priv;
+#else
+static int
+davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ struct davinci_mmc_priv *host = dev_get_priv(dev);
+#endif
volatile struct davinci_mmc_regs *regs = host->reg_base;
uint mmcstatus, status_rdy, status_err;
uint i, cmddata, bytes_left = 0;
}
/* Initialize Davinci MMC controller */
+#if !CONFIG_IS_ENABLED(DM_MMC)
static int dmmc_init(struct mmc *mmc)
{
struct davinci_mmc *host = mmc->priv;
+#else
+static int davinci_dm_mmc_init(struct udevice *dev)
+{
+ struct davinci_mmc_priv *host = dev_get_priv(dev);
+#endif
struct davinci_mmc_regs *regs = host->reg_base;
/* Clear status registers explicitly - soft reset doesn't clear it
}
/* Set buswidth or clock as indicated by the MMC framework */
+#if !CONFIG_IS_ENABLED(DM_MMC)
static int dmmc_set_ios(struct mmc *mmc)
{
struct davinci_mmc *host = mmc->priv;
struct davinci_mmc_regs *regs = host->reg_base;
+#else
+static int davinci_mmc_set_ios(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct davinci_mmc_priv *host = dev_get_priv(dev);
+ struct davinci_mmc_regs *regs = host->reg_base;
+#endif
/* Set the bus width */
if (mmc->bus_width == 4)
set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
/* Set clock speed */
- if (mmc->clock)
+ if (mmc->clock) {
+#if !CONFIG_IS_ENABLED(DM_MMC)
dmmc_set_clock(mmc, mmc->clock);
-
+#else
+ davinci_mmc_set_clock(dev, mmc->clock);
+#endif
+ }
return 0;
}
+#if !CONFIG_IS_ENABLED(DM_MMC)
static const struct mmc_ops dmmc_ops = {
- .send_cmd = dmmc_send_cmd,
- .set_ios = dmmc_set_ios,
- .init = dmmc_init,
+ .send_cmd = dmmc_send_cmd,
+ .set_ios = dmmc_set_ios,
+ .init = dmmc_init,
+};
+#else
+
+static int davinci_mmc_getcd(struct udevice *dev)
+{
+ int value = -1;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct davinci_mmc_priv *priv = dev_get_priv(dev);
+ value = dm_gpio_get_value(&priv->cd_gpio);
+#endif
+ /* if no CD return as 1 */
+ if (value < 0)
+ return 1;
+
+ return value;
+}
+
+static int davinci_mmc_getwp(struct udevice *dev)
+{
+ int value = -1;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct davinci_mmc_priv *priv = dev_get_priv(dev);
+
+ value = dm_gpio_get_value(&priv->wp_gpio);
+#endif
+ /* if no WP return as 0 */
+ if (value < 0)
+ return 0;
+
+ return value;
+}
+
+static const struct dm_mmc_ops davinci_mmc_ops = {
+ .send_cmd = davinci_mmc_send_cmd,
+ .set_ios = davinci_mmc_set_ios,
+ .get_cd = davinci_mmc_getcd,
+ .get_wp = davinci_mmc_getwp,
};
+#endif
+#if !CONFIG_IS_ENABLED(DM_MMC)
/* Called from board_mmc_init during startup. Can be called multiple times
- * depending on the number of slots available on board and controller
- */
+* depending on the number of slots available on board and controller
+*/
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
{
host->cfg.name = "davinci";
return 0;
}
+#else
+
+
+static int davinci_mmc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct davinci_mmc_priv *priv = dev_get_priv(dev);
+ struct mmc_config *cfg = &plat->cfg;
+ struct davinci_of_data *data =
+ (struct davinci_of_data *)dev_get_driver_data(dev);
+ cfg->f_min = 200000;
+ cfg->f_max = 25000000;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
+ cfg->b_max = DAVINCI_MAX_BLOCKS;
+
+ if (data) {
+ cfg->name = data->name;
+ priv->version = data->version;
+ }
+
+ priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
+ priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ /* These GPIOs are optional */
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
+#endif
+
+ upriv->mmc = &plat->mmc;
+
+ return davinci_dm_mmc_init(dev);
+}
+
+static int davinci_mmc_bind(struct udevice *dev)
+{
+ struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+
+const struct davinci_of_data davinci_mmc_host_info[] = {
+ {
+ .name = "dm6441-mmc",
+ .version = MMC_CTLR_VERSION_1,
+ },
+ {
+ .name = "da830-mmc",
+ .version = MMC_CTLR_VERSION_2,
+ },
+ {},
+};
+
+static const struct udevice_id davinci_mmc_ids[] = {
+ {
+ .compatible = "ti,dm6441-mmc",
+ .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_1]
+ },
+ {
+ .compatible = "ti,da830-mmc",
+ .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_2]
+ },
+ {},
+};
+
+U_BOOT_DRIVER(davinci_mmc_drv) = {
+ .name = "davinci_mmc",
+ .id = UCLASS_MMC,
+ .of_match = davinci_mmc_ids,
+#if CONFIG_BLK
+ .bind = davinci_mmc_bind,
+#endif
+ .probe = davinci_mmc_probe,
+ .ops = &davinci_mmc_ops,
+ .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
+ .priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
+};
+#endif
static int omap_hsmmc_getcd(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
- int value;
-
+ int value = -1;
+#if CONFIG_IS_ENABLED(DM_GPIO)
value = dm_gpio_get_value(&priv->cd_gpio);
+#endif
/* if no CD return as 1 */
if (value < 0)
return 1;
static int omap_hsmmc_getwp(struct udevice *dev)
{
+ int value = 0;
+#if CONFIG_IS_ENABLED(DM_GPIO)
struct omap_hsmmc_data *priv = dev_get_priv(dev);
- int value;
-
value = dm_gpio_get_value(&priv->wp_gpio);
+#endif
/* if no WP return as 0 */
if (value < 0)
return 0;
device_get_supply_regulator(dev, "pbias-supply",
&priv->pbias_supply);
#endif
-#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
+#if defined(OMAP_HSMMC_USE_GPIO)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
+#endif
mmc->dev = dev;
upriv->mmc = mmc;
static const struct udevice_id pbias_ids[] = {
{ .compatible = "ti,pbias-dra7" },
+ { .compatible = "ti,pbias-omap2" },
+ { .compatible = "ti,pbias-omap3" },
+ { .compatible = "ti,pbias-omap4" },
+ { .compatible = "ti,pbias-omap5" },
{ }
};
#include <asm/io.h>
#include <dm.h>
#include "ehci.h"
+#include <power/regulator.h>
/*
* Even though here we don't explicitly use "struct ehci_ctrl"
struct clk *clocks;
struct reset_ctl *resets;
struct phy phy;
+#ifdef CONFIG_DM_REGULATOR
+ struct udevice *vbus_supply;
+#endif
int clock_count;
int reset_count;
};
+#ifdef CONFIG_DM_REGULATOR
+static int ehci_enable_vbus_supply(struct udevice *dev)
+{
+ struct generic_ehci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = device_get_supply_regulator(dev, "vbus-supply",
+ &priv->vbus_supply);
+ if (ret && ret != -ENOENT)
+ return ret;
+
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply, true);
+ if (ret) {
+ dev_err(dev, "Error enabling VBUS supply\n");
+ return ret;
+ }
+ } else {
+ dev_dbg(dev, "No vbus supply\n");
+ }
+
+ return 0;
+}
+
+static int ehci_disable_vbus_supply(struct generic_ehci *priv)
+{
+ if (priv->vbus_supply)
+ return regulator_set_enable(priv->vbus_supply, false);
+ else
+ return 0;
+}
+#else
+static int ehci_enable_vbus_supply(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ehci_disable_vbus_supply(struct generic_ehci *priv)
+{
+ return 0;
+}
+#endif
+
static int ehci_usb_probe(struct udevice *dev)
{
struct generic_ehci *priv = dev_get_priv(dev);
}
}
- err = ehci_setup_phy(dev, &priv->phy, 0);
+ err = ehci_enable_vbus_supply(dev);
if (err)
goto reset_err;
+ err = ehci_setup_phy(dev, &priv->phy, 0);
+ if (err)
+ goto regulator_err;
+
hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
if (ret)
dev_err(dev, "failed to shutdown usb phy\n");
+regulator_err:
+ ret = ehci_disable_vbus_supply(priv);
+ if (ret)
+ dev_err(dev, "failed to disable VBUS supply\n");
+
reset_err:
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
if (ret)
return ret;
+ ret = ehci_disable_vbus_supply(priv);
+ if (ret)
+ return ret;
+
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
return ret;
*/
ubi = open_ubi(name, UBI_READONLY);
if (IS_ERR(ubi)) {
- pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d",
+ pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d\n",
current->pid, name, (int)PTR_ERR(ubi));
return ERR_CAST(ubi);
}
* UBIFS_BLOCK_SIZE. It is assumed that both are powers of 2.
*/
if (PAGE_CACHE_SIZE < UBIFS_BLOCK_SIZE) {
- pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes",
+ pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes\n",
current->pid, (unsigned int)PAGE_CACHE_SIZE);
return -EINVAL;
}
err = register_filesystem(&ubifs_fs_type);
if (err) {
- pr_err("UBIFS error (pid %d): cannot register file system, error %d",
+ pr_err("UBIFS error (pid %d): cannot register file system, error %d\n",
current->pid, err);
goto out_dbg;
}
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#endif /* __MIGO_R_H */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#include <configs/ti_omap3_common.h>
-#undef CONFIG_SDRC /* Disable SDRC since we have EMIF4 */
+#undef CONFIG_DM_I2C_COMPAT
#define CONFIG_REVISION_TAG
/* Hardware drivers */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#endif /* __AP325RXA_H */
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __AP_SH4A_4A_H */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
#define CONFIG_SYS_DCACHE_OFF
/* STACK */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __ARMADILLO_800EVA_H */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* ENV setting */
#if !defined(CONFIG_MTD_NOR_FLASH)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_ARCH_CPU_INIT
* Flash & Environment
*/
#ifdef CONFIG_NAND
+#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_ENV_SECT_SIZE (128 << 10)
+#endif
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
#endif
#ifdef CONFIG_USE_SPIFLASH
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 << 10)
#define CONFIG_ENV_OFFSET (512 << 10)
-#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#endif
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_SPI_FLASH_MTD
#endif
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 41666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __ECOVEC_H */
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (1)
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Clocks */
#define CONFIG_SYS_CLK_FREQ 24000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
/* UART */
#define CONFIG_CONS_SCIF0 1
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
/* PCMCIA */
#define CONFIG_IDE_PCMCIA 1
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#endif /* __MS7722SE_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __MS7750SE_H */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __R0P7734_H */
* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_TMU_TIMER
#ifndef CONFIG_PINCTRL_PFC
#define CONFIG_SH_GPIO_PFC
#endif
#undef CONFIG_SPI_FLASH_MTD
#endif
+/* Timer */
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE (32500000 / 4) /* CP/4 */
+
#endif /* __RCAR_GEN2_COMMON_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 36000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 66125000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7752EVB_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7753EVB_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7757LCR_H */
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (1)
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7785LCR_H */
#else
#define CONFIG_SYS_CLK_FREQ 33333333
#endif /* CONFIG_T_SH7706LSR */
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* Network device */
#define CONFIG_DRIVER_NE2000
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
* 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
*
*/
+#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
/* SPL SDMMC boot support */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif /* __CONFIG_H */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NS16550_SERIAL
#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#endif /* !CONFIG_DM_SERIAL */
-#endif /* CONFIG_SPL_BUILD */
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
- 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_PORT_MAPPED
/*-----------------------------------------------------------------------
+++ /dev/null
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SH_TMU_H
-#define __SH_TMU_H
-
-#include <asm/types.h>
-
-#if defined(CONFIG_CPU_SH3)
-struct tmu_regs {
- u8 tocr;
- u8 reserved0;
- u8 tstr;
- u8 reserved1;
- u32 tcor0;
- u32 tcnt0;
- u16 tcr0;
- u16 reserved2;
- u32 tcor1;
- u32 tcnt1;
- u16 tcr1;
- u16 reserved3;
- u32 tcor2;
- u32 tcnt2;
- u16 tcr2;
- u16 reserved4;
- u32 tcpr2;
-};
-#endif /* CONFIG_CPU_SH3 */
-
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
-struct tmu_regs {
- u32 reserved;
- u8 tstr;
- u8 reserved2[3];
- u32 tcor0;
- u32 tcnt0;
- u16 tcr0;
- u16 reserved3;
- u32 tcor1;
- u32 tcnt1;
- u16 tcr1;
- u16 reserved4;
- u32 tcor2;
- u32 tcnt2;
- u16 tcr2;
- u16 reserved5;
-};
-#endif /* CONFIG_CPU_SH4 */
-
-static inline unsigned long get_tmu0_clk_rate(void)
-{
- return CONFIG_SH_TMU_CLK_FREQ;
-}
-
-#endif /* __SH_TMU_H */
CONFIG_SYS_TMRINTR_PRI
CONFIG_SYS_TMRPND_REG
CONFIG_SYS_TMR_BASE
-CONFIG_SYS_TMU_CLK_DIV
CONFIG_SYS_TSEC1
CONFIG_SYS_TSEC1_OFFSET
CONFIG_SYS_TSEC2
projects / platform / kernel / u-boot.git / commitdiff