# For min/max
--ignore MINMAX
+
+# enable more tests
+--strict
P3G4 MPC7410
- PCIPPC2 MPC750
- PCIPPC6 MPC750
-
Phil Edworthy <phil.edworthy@renesas.com>
rsk7264 SH7264
Anatolij Gustschin <agust@denx.de>
+ ac14xx MPC5121e
O2D MPC5200
O2D300 MPC5200
O2DNT2 MPC5200
Stefan Roese <sr@denx.de>
a3m071 MPC5200
+ a4m2k MPC5200
P3M7448 MPC7448
#-----------------------------------------------------------------------
kill_children() {
- local pgid=`ps -p $$ --no-headers -o "%r" | tr -d ' '`
- local children=`pgrep -g $pgid | grep -v $$ | grep -v $pgid`
+ local OS=$(uname -s)
+ local children=""
+ case "${OS}" in
+ "Darwin")
+ # Mac OS X is known to have BSD style ps
+ local pgid=$(ps -p $$ -o pgid | sed -e "/PGID/d")
+ children=$(ps -g $pgid -o pid | sed -e "/PID\|$$\|$pgid/d")
+ ;;
+ *)
+ # everything else tries the GNU style
+ local pgid=$(ps -p $$ --no-headers -o "%r" | tr -d ' ')
+ children=$(pgrep -g $pgid | sed -e "/$$\|$pgid/d")
+ ;;
+ esac
kill $children 2> /dev/null
wait $children 2> /dev/null
(requires CONFIG_CMD_MEMORY and CONFIG_MD5)
CONFIG_CMD_MEMINFO * Display detailed memory information
CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
- loop, loopw, mtest
+ loop, loopw
+ CONFIG_CMD_MEMTEST mtest
CONFIG_CMD_MISC Misc functions like sleep etc
CONFIG_CMD_MMC * MMC memory mapped support
CONFIG_CMD_MII * MII utility commands
If defined, don't allow the -f switch to env set override variable
access flags.
+- CONFIG_SYS_GENERIC_BOARD
+ This selects the architecture-generic board system instead of the
+ architecture-specific board files. It is intended to move boards
+ to this new framework over time. Defining this will disable the
+ arch/foo/lib/board.c file and use common/board_f.c and
+ common/board_r.c instead. To use this option your architecture
+ must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in
+ its config.mk file). If you find problems enabling this option on
+ your board please report the problem and send patches!
+
+- CONFIG_SYS_SYM_OFFSETS
+ This is set by architectures that use offsets for link symbols
+ instead of absolute values. So bss_start is obtained using an
+ offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
+ directly. You should not need to touch this setting.
+
+
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
following configurations:
endif
endif
+# Support generic board on ARM
+__HAVE_ARCH_GENERIC_BOARD := y
+
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
# Choose between ARM/Thumb instruction sets
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} >.sdram
}
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
- __bss_end__ = .;
+ __bss_end = .;
_end = .;
}
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
#endif
/* Third, we clear the BSS. */
- memset(__bss_start, 0, __bss_end__ - __bss_start);
+ memset(__bss_start, 0, __bss_end - __bss_start);
/* Finally, setup gd and move to the next step. */
gd = &gdata;
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
_end = .;
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
_end = .;
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
#ifdef CONFIG_NAND_U_BOOT
.globl _end
_end:
- .word __bss_end__
+ .word __bss_end
#endif
#ifdef CONFIG_USE_IRQ
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} >.sdram
}
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} >.sdram
}
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} >.sdram
. = ALIGN(8);
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- ___bssend___ = .;
+ __bss_end = .;
}
- .bss_end ___bssend___ (OVERLAY) : {
- KEEP(*(.__bss_end__));
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
.globl _bss_end_ofs
_bss_end_ofs:
- .word __bss_end__ - _start
+ .word __bss_end - _start
.globl _end_ofs
_end_ofs:
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
/DISCARD/ : { *(.dynstr*) }
}
#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
-ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
+ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
#endif
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- ___bssend___ = .;
+ __bss_end = .;
}
- .bss_end ___bssend___ (OVERLAY) : {
- KEEP(*(.__bss_end__));
+
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
}
#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
-ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
+ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
#endif
/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
+ * Copyright (c) 2012 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef _I2C_H_
-#define _I2C_H_
-
-#include <common.h>
-
-extern int i2c_read_byte (u8 * data,
- u8 dev,
- u8 offset);
-
-extern unsigned int i2c_reset (void);
+#ifndef __ASM_ARM_SECTIONS_H
+#define __ASM_ARM_SECTIONS_H
+#include <asm-generic/sections.h>
#endif
#include <asm/arch/spl.h>
/* Linker symbols. */
-extern char __bss_start[], __bss_end__[];
+extern char __bss_start[], __bss_end[];
extern gd_t gdata;
#define _U_BOOT_ARM_H_ 1
/* for the following variables, see start.S */
-extern ulong _bss_start_ofs; /* BSS start relative to _start */
-extern ulong _bss_end_ofs; /* BSS end relative to _start */
-extern ulong _end_ofs; /* end of image relative to _start */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
-extern ulong _TEXT_BASE; /* code start */
extern ulong _datarel_start_ofs;
extern ulong _datarelrolocal_start_ofs;
extern ulong _datarellocal_start_ofs;
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
+#ifndef __ASSEMBLY__
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong size;
} bi_dram[CONFIG_NR_DRAM_BANKS];
} bd_t;
+#endif
+
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_ARM
SOBJS-y += crt0.o
ifndef CONFIG_SPL_BUILD
-COBJS-y += bss.o
+ifndef CONFIG_SYS_GENERIC_BOARD
COBJS-y += board.o
+endif
+COBJS-y += bss.o
+
COBJS-y += bootm.o
COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
#include <fdtdec.h>
#include <post.h>
#include <logbuff.h>
+#include <asm/sections.h>
#ifdef CONFIG_BITBANGMII
#include <miiphy.h>
*/
char __bss_start[0] __attribute__((used, section(".__bss_start")));
-char __bss_end__[0] __attribute__((used, section(".__bss_end__")));
+char __bss_end[0] __attribute__((used, section(".__bss_end")));
*/
.globl __bss_start
-.globl __bss_end__
+.globl __bss_end
/*
* entry point of crt0 sequence
bl c_runtime_cpu_setup /* we still call old routine here */
ldr r0, =__bss_start /* this is auto-relocated! */
- ldr r1, =__bss_end__ /* this is auto-relocated! */
+ ldr r1, =__bss_end /* this is auto-relocated! */
mov r2, #0x00000000 /* prepare zero to clear BSS */
asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
/* Clear the BSS. */
- memset(__bss_start, 0, __bss_end__ - __bss_start);
+ memset(__bss_start, 0, __bss_end - __bss_start);
/* Set global data pointer. */
gd = &gdata;
/* zero out .bss */
mov r0, 0
mov r1, 0
- lda.w r9, __bss_end__
+ lda.w r9, __bss_end
sub r9, r8
1: st.d r10++, r0
sub r9, 8
*(.bss.*)
}
. = ALIGN(8);
- __bss_end__ = .;
+ __bss_end = .;
}
#ifndef __ASM_AVR32_SECTIONS_H
#define __ASM_AVR32_SECTIONS_H
+#include <asm-generic/sections.h>
+
/* References to section boundaries */
-extern char _text[], _etext[];
-extern char _data[], __data_lma[], _edata[], __edata_lma[];
+extern char __data_lma[], __edata_lma[];
extern char __got_start[], __got_lma[], __got_end[];
-extern char __bss_end__[];
#endif /* __ASM_AVR32_SECTIONS_H */
printf ("\n\n%s\n\n", version_string);
printf ("U-Boot code: %08lx -> %08lx data: %08lx -> %08lx\n",
(unsigned long)_text, (unsigned long)_etext,
- (unsigned long)_data, (unsigned long)__bss_end__);
+ (unsigned long)_data, (unsigned long)__bss_end);
return 0;
}
* - stack
*/
addr = CONFIG_SYS_SDRAM_BASE + sdram_size;
- monitor_len = __bss_end__ - _text;
+ monitor_len = (char *)__bss_end - _text;
/*
* Reserve memory for u-boot code, data and bss.
#ifdef CONFIG_FB_ADDR
printf("LCD: Frame buffer allocated at preset 0x%08x\n",
CONFIG_FB_ADDR);
- gd->fb_base = (void *)CONFIG_FB_ADDR;
+ gd->fb_base = CONFIG_FB_ADDR;
#else
addr = lcd_setmem(addr);
printf("LCD: Frame buffer allocated at 0x%08lx\n", addr);
- gd->fb_base = (void *)addr;
+ gd->fb_base = addr;
#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
ulong bfin_poweron_retx;
-__attribute__ ((__noreturn__))
void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
{
#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
/* Architecture-specific global data */
struct arch_global_data {
+ unsigned long board_type;
};
#include <asm-generic/global_data.h>
/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
+ * Copyright (c) 2012 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef _FPGA_SERIAL_H_
-#define _FPGA_SERIAL_H_
+#ifndef __ASM_BLACKFIN_SECTIONS_H
+#define __ASM_BLACKFIN_SECTIONS_H
-extern void fpga_serial_init (int);
-extern void fpga_serial_putc (char);
-extern int fpga_serial_getc (void);
-extern int fpga_serial_tstc (void);
-extern void fpga_serial_setbrg (void);
+#include <asm-generic/sections.h>
#endif
bd = gd->bd;
printf(" gd: %p\n", gd);
printf(" |-flags: %lx\n", gd->flags);
- printf(" |-board_type: %lx\n", gd->board_type);
+ printf(" |-board_type: %lx\n", gd->arch.board_type);
printf(" |-baudrate: %u\n", gd->baudrate);
printf(" |-have_console: %lx\n", gd->have_console);
printf(" |-ram_size: %lx\n", gd->ram_size);
/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
+ * Copyright (c) 2012 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef _NS16550_H_
-#define _NS16550_H_
-
-#define NS16550_RBR 0x00
-#define NS16550_IER 0x01
-#define NS16550_FCR 0x02
-#define NS16550_LCR 0x03
-#define NS16550_MCR 0x04
-#define NS16550_LSR 0x05
-#define NS16550_MSR 0x06
-#define NS16550_SCR 0x07
+#ifndef __ASM_M68K_SECTIONS_H
+#define __ASM_M68K_SECTIONS_H
-#define NS16550_THR NS16550_RBR
-#define NS16550_IIR NS16550_FCR
-#define NS16550_DLL NS16550_RBR
-#define NS16550_DLM NS16550_IER
+#include <asm-generic/sections.h>
#endif
#include <environment.h>
extern ulong __init_end;
-extern ulong __bss_end__;
+extern ulong __bss_end;
#if defined(CONFIG_WATCHDOG)
+# undef INIT_FUNC_WATCHDOG_INIT
# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
# define WATCHDOG_DISABLE watchdog_disable
* - monitor code
* - board info struct
*/
- len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE;
+ len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
+ * Copyright (c) 2012 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef _SCONSOLE_H_
-#define _SCONSOLE_H_
-
-#include <config.h>
-
-typedef struct sconsole_buffer_s {
- unsigned long size;
- unsigned long max_size;
- unsigned long pos;
- unsigned long baud;
- char data[1];
-} sconsole_buffer_t;
-
-#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR)
-
-extern void (* sconsole_putc) (char);
-extern void (* sconsole_puts) (const char *);
-extern int (* sconsole_getc) (void);
-extern int (* sconsole_tstc) (void);
-extern void (* sconsole_setbrg) (void);
+#ifndef __ASM_MICROBLAZE_SECTIONS_H
+#define __ASM_MICROBLAZE_SECTIONS_H
-extern void sconsole_flush (void);
-extern int sconsole_get_baudrate (void);
+#include <asm-generic/sections.h>
#endif
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_MIPS_SECTIONS_H
+#define __ASM_MIPS_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
static inline unsigned long bss_start(void)
{
- extern ulong __bss_start;
+ extern char __bss_start[];
return (unsigned long) &__bss_start;
}
static inline unsigned long image_copy_end(void)
{
- extern ulong __image_copy_end;
+ extern char __image_copy_end[];
return (unsigned long) &__image_copy_end;
}
clear_bss:
la $r0, __bss_start /* r0 <- rel __bss_start in FLASH */
add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
- la $r1, __bss_end__ /* r1 <- rel __bss_end in RAM */
+ la $r1, __bss_end /* r1 <- rel __bss_end in RAM */
add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
li $r2, 0x00000000 /* clear */
__bss_start = .;
*(.bss)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
}
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS32_SECTIONS_H
+#define __ASM_NDS32_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
#define _U_BOOT_NDS32_H_ 1
/* for the following variables, see start.S */
-extern ulong __bss_start; /* BSS start relative to _start */
-extern ulong __bss_end__; /* BSS end relative to _start */
-extern ulong _end; /* end of image relative to _start */
-extern ulong _start; /* start of image relative to _start */
+extern char __bss_start[]; /* BSS start relative to _start */
+extern ulong __bss_end; /* BSS end relative to _start */
+extern char _end[]; /* end of image relative to _start */
+extern void _start(void); /* start of image relative to _start */
extern ulong _TEXT_BASE; /* code start */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
- gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start);
+ gd->mon_len = (unsigned int)(&__bss_end) - (unsigned int)(&_start);
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0)
3:
/* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
- * and between __bss_start and __bss_end__.
+ * and between __bss_start and __bss_end.
*/
movhi r5, %hi(__bss_start)
ori r5, r5, %lo(__bss_start)
- movhi r6, %hi(__bss_end__)
- ori r6, r6, %lo(__bss_end__)
+ movhi r6, %hi(__bss_end)
+ ori r6, r6, %lo(__bss_end)
beq r5, r6, 5f
4: stwio r0, 0(r5)
*(.scommon)
}
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
PROVIDE (end = .);
/* DEBUG -- symbol table, string table, etc. etc.
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_SECTIONS_H
+#define __ASM_NIOS2_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_OPENRISC_SECTIONS_H
+#define __ASM_OPENRISC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
PLATFORM_LDFLAGS += -n
+# Support generic board on PPC
+__HAVE_ARCH_GENERIC_BOARD := y
+
#
# When cross-compiling on NetBSD, we have to define __PPC__ or else we
# will pick up a va_list declaration that is incompatible with the
}
-#if !defined(CONFIG_PCIPPC2) && \
- !defined(CONFIG_BAB7xx) && \
+#if !defined(CONFIG_BAB7xx) && \
!defined(CONFIG_ELPPC) && \
!defined(CONFIG_PPMC7XX)
/* no generic way to do board reset. simply call soft_reset. */
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
-#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
+#if !defined(CONFIG_BAB7xx)
void
watchdog_reset(void)
{
}
-#endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
+#endif /* !CONFIG_BAB7xx */
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
#include <common.h>
#include <asm/io.h>
+#include <asm/mpc512x.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
+ /* Local Window and chip select configuration */
+#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
+ out_be32(&im->sysconf.lpcs0aw,
+ CSAW_START(CONFIG_SYS_CS0_START) |
+ CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
+ sync_law(&im->sysconf.lpcs0aw);
+#endif
+#if defined(CONFIG_SYS_CS0_CFG)
+ out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
+ out_be32(&im->sysconf.lpcs1aw,
+ CSAW_START(CONFIG_SYS_CS1_START) |
+ CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
+ sync_law(&im->sysconf.lpcs1aw);
+#endif
+#if defined(CONFIG_SYS_CS1_CFG)
+ out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
+ out_be32(&im->sysconf.lpcs2aw,
+ CSAW_START(CONFIG_SYS_CS2_START) |
+ CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
+ sync_law(&im->sysconf.lpcs2aw);
+#endif
+#if defined(CONFIG_SYS_CS2_CFG)
+ out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
+ out_be32(&im->sysconf.lpcs3aw,
+ CSAW_START(CONFIG_SYS_CS3_START) |
+ CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
+ sync_law(&im->sysconf.lpcs3aw);
+#endif
+#if defined(CONFIG_SYS_CS3_CFG)
+ out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
+ out_be32(&im->sysconf.lpcs4aw,
+ CSAW_START(CONFIG_SYS_CS4_START) |
+ CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
+ sync_law(&im->sysconf.lpcs4aw);
+#endif
+#if defined(CONFIG_SYS_CS4_CFG)
+ out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
+ out_be32(&im->sysconf.lpcs5aw,
+ CSAW_START(CONFIG_SYS_CS5_START) |
+ CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
+ sync_law(&im->sysconf.lpcs5aw);
+#endif
+#if defined(CONFIG_SYS_CS5_CFG)
+ out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
+ out_be32(&im->sysconf.lpcs6aw,
+ CSAW_START(CONFIG_SYS_CS6_START) |
+ CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
+ sync_law(&im->sysconf.lpcs6aw);
+#endif
+#if defined(CONFIG_SYS_CS6_CFG)
+ out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
+ out_be32(&im->sysconf.lpcs7aw,
+ CSAW_START(CONFIG_SYS_CS7_START) |
+ CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
+ sync_law(&im->sysconf.lpcs7aw);
+#endif
+#if defined(CONFIG_SYS_CS7_CFG)
+ out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
+#endif
+
+#if defined CONFIG_SYS_CS_ALETIMING
+ if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
+ out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+#endif
+#if defined CONFIG_SYS_CS_BURST
+ out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
+#endif
+#if defined CONFIG_SYS_CS_DEADCYCLE
+ out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
+#endif
+#if defined CONFIG_SYS_CS_HOLDCYCLE
+ out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
+#endif
+
/* system performance tweaking */
#ifdef CONFIG_SYS_ACR_PIPE_DEP
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
out_be32(&im->clk.scfr[0], ips_div);
+#ifdef SCFR1_LPC_DIV
+ clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
+ SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
+#endif
+
+#ifdef SCFR1_NFC_DIV
+ clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
+ SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
+#endif
+
+#ifdef SCFR1_DIU_DIV
+ clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
+ SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
+#endif
+
/*
* Enable Time Base/Decrementer
*
* during FLASH chip identification etc.
*/
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
+
+ /*
+ * Enable clocks
+ */
+ out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+ out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+ setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
}
int cpu_init_r (void)
sync_law(&im->sysconf.ddrlaw.ar);
/* DDR Enable */
- out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN);
+ /*
+ * the "enable" combination: DRAM controller out of reset,
+ * clock enabled, command mode -- BUT leave CKE low for now
+ */
+ i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK;
+ out_be32(&im->mddrc.ddr_sys_config, i);
+ /* maintain 200 microseconds of stable power and clock */
+ udelay(200);
+ /* apply a NOP, it shouldn't harm */
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP);
+ /* now assert CKE (high) */
+ i |= MDDRC_SYS_CFG_CKE_MASK;
+ out_be32(&im->mddrc.ddr_sys_config, i);
/* Initialize DDR Priority Manager */
out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
+ /* Allow for the DLL to startup before accessing data */
+ udelay(10);
+
msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
/* Fix DDR Local Window for new size */
out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
}
return;
}
+
+void iopin_initialize_bits(iopin_t *ioregs_init, int len)
+{
+ short i, j, p;
+ u32 *reg, mask;
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ reg = (u32 *)&(im->io_ctrl);
+
+ /* iterate over table entries */
+ for (i = 0; i < len; i++) {
+ /* iterate over pins within a table entry */
+ for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
+ p < ioregs_init[i].nr_pins; p++, j++) {
+ if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) {
+ /* replace all settings at once */
+ out_be32(reg + j, ioregs_init[i].val);
+ } else {
+ /*
+ * only replace individual parts, but
+ * REPLACE them instead of just ORing
+ * them in and "inheriting" previously
+ * set bits which we don't want
+ */
+ mask = 0;
+ if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX)
+ mask |= IO_PIN_FMUX(3);
+
+ if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD)
+ mask |= IO_PIN_HOLD(3);
+
+ if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL)
+ mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1);
+
+ if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG)
+ mask |= IO_PIN_ST(1);
+
+ if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR)
+ mask |= IO_PIN_DS(3);
+ /*
+ * DON'T do the "mask, then insert"
+ * in place on the register, it may
+ * break access to external hardware
+ * (like boot ROMs) when configuring
+ * LPB related pins, while the code to
+ * configure the pin is read from this
+ * very address region
+ */
+ clrsetbits_be32(reg + j, mask,
+ ioregs_init[i].val & mask);
+ }
+ }
+ }
+}
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
. = env_start;
.ppcenv :
end_align = (u32)__spl_flash_end;
/*
- * First we need to initialize the SDRAM, so that the real
- * U-Boot or the OS (Linux) can be loaded
+ * On MPC5200, the initial RAM (and gd) is located in the internal
+ * SRAM. So we can actually call the preloader console init code
+ * before calling initdram(). This makes serial output (printf)
+ * available very early, even before SDRAM init, which has been
+ * an U-Boot priciple from day 1.
*/
- initdram(0);
-
- /* Clear bss */
- memset(__bss_start, '\0', __bss_end__ - __bss_start);
/*
* Init global_data pointer. Has to be done before calling
preloader_console_init();
/*
+ * First we need to initialize the SDRAM, so that the real
+ * U-Boot or the OS (Linux) can be loaded
+ */
+ initdram(0);
+
+ /* Clear bss */
+ memset(__bss_start, '\0', __bss_end - __bss_start);
+
+ /*
* Call board_init_r() (SPL framework version) to load and boot
* real U-Boot or OS
*/
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
#endif
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} > sdram
}
*(.sbss*)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
#if defined(CONFIG_FADS)
GOT_ENTRY(environment)
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
#if defined(CONFIG_HYMOD)
GOT_ENTRY(environment)
*/
lwz r4,GOT(environment)
#else
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
#endif
cmplw 0, r3, r4
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(__bss_start)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
#ifndef MINIMAL_SPL
GOT_ENTRY(_FIXUP_TABLE_)
*/
lwz r4,GOT(environment)
#else
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
#endif
cmplw 0, r3, r4
.bss (NOLOAD) : {
*(.*bss)
}
- __bss_end__ = .;
+ __bss_end = .;
}
ENTRY(_start)
-ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big");
+ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
#endif
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0,r3,r4
beq 6f
} :bss
. = ALIGN(4);
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(.sbss*)
*(.bss*)
}
- __bss_end__ = .;
+ __bss_end = .;
}
ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");
*(.sbss*)
*(.bss*)
}
- __bss_end__ = .;
+ __bss_end = .;
}
} :bss
. = ALIGN(4);
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end__)
+ GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
#endif /* CONFIG_NAND_SPL */
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end__)
+ lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 7f
} :bss
. = ALIGN(4);
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
#define CLOCK_SCCR2_IIM_EN 0x00080000
/* SCFR1 System Clock Frequency Register 1 */
+#ifndef SCFR1_IPS_DIV
#define SCFR1_IPS_DIV 0x3
+#endif
#define SCFR1_IPS_DIV_MASK 0x03800000
#define SCFR1_IPS_DIV_SHIFT 23
#define SCFR1_LPC_DIV_MASK 0x00003800
#define SCFR1_LPC_DIV_SHIFT 11
+#define SCFR1_NFC_DIV_MASK 0x00000700
+#define SCFR1_NFC_DIV_SHIFT 8
+
+#define SCFR1_DIU_DIV_MASK 0x000000FF
+#define SCFR1_DIU_DIV_SHIFT 0
+
/* SCFR2 System Clock Frequency Register 2 */
#define SCFR2_SYS_DIV 0xFC000000
#define SCFR2_SYS_DIV_SHIFT 26
/* MDDRC SYS CFG and Timing CFG0 Registers */
#define MDDRC_SYS_CFG_EN 0xF0000000
+#define MDDRC_SYS_CFG_CKE_MASK 0x40000000
#define MDDRC_SYS_CFG_CMD_MASK 0x10000000
#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF
void iopin_initialize(iopin_t *,int);
/*
+ * support to adjust individual parts of the IO pin setup
+ */
+
+#define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */
+#define IO_PIN_OVER_FMUX (1 << 1)
+#define IO_PIN_OVER_HOLD (1 << 2)
+#define IO_PIN_OVER_PULL (1 << 3)
+#define IO_PIN_OVER_STRIG (1 << 4)
+#define IO_PIN_OVER_DRVSTR (1 << 5)
+
+void iopin_initialize_bits(iopin_t *, int);
+
+/*
* IIM
*/
typedef struct iim512x {
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_POWERPC_SECTIONS_H
+#define __ASM_POWERPC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
#define BOOT_DEVICE_NOR 1
/* Linker symbols */
-extern char __bss_start[], __bss_end__[];
+extern char __bss_start[], __bss_end[];
#endif
* include/asm-ppc/u-boot.h
*/
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
#ifndef __ASSEMBLY__
typedef struct bd_info {
#endif /* __ASSEMBLY__ */
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_PPC
COBJS-$(CONFIG_BAT_RW) += bat_rw.o
ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_SYS_GENERIC_BOARD
COBJS-y += board.o
endif
+endif
COBJS-y += bootm.o
COBJS-y += cache.o
COBJS-y += extable.o
#endif
extern ulong __init_end;
-extern ulong __bss_end__;
+extern ulong __bss_end;
ulong monitor_flash_len;
#if defined(CONFIG_CMD_BEDBUG)
/***********************************************************************/
#if defined(CONFIG_WATCHDOG)
-static int init_func_watchdog_init(void)
+int init_func_watchdog_init(void)
{
puts(" Watchdog enabled\n");
WATCHDOG_RESET();
return 0;
}
-#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
-
-static int init_func_watchdog_reset(void)
+int init_func_watchdog_reset(void)
{
WATCHDOG_RESET();
return 0;
}
-
-#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
-#else
-#define INIT_FUNC_WATCHDOG_INIT /* undef */
-#define INIT_FUNC_WATCHDOG_RESET /* undef */
#endif /* CONFIG_WATCHDOG */
/*
#ifdef CONFIG_POST
post_init_f,
#endif
- INIT_FUNC_WATCHDOG_RESET init_func_ram,
+ INIT_FUNC_WATCHDOG_RESET
+ init_func_ram,
#if defined(CONFIG_SYS_DRAM_TEST)
testdram,
#endif /* CONFIG_SYS_DRAM_TEST */
* - monitor code
* - board info struct
*/
- len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE;
+ len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
/*
* Subtract specified amount of memory to hide so that it won't
#ifndef __SANDBOX_SECTIONS_H
#define __SANDBOX_SECTIONS_H
+#include <asm-generic/sections.h>
+
struct sb_cmdline_option;
extern struct sb_cmdline_option *__u_boot_sandbox_option_start[],
}
PROVIDE (bss_end = .);
- PROVIDE (__bss_end__ = .);
+ PROVIDE (__bss_end = .);
}
}
PROVIDE (bss_end = .);
- PROVIDE (__bss_end__ = .);
+ PROVIDE (__bss_end = .);
}
}
PROVIDE (bss_end = .);
- PROVIDE (__bss_end__ = .);
+ PROVIDE (__bss_end = .);
}
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_SH_SECTIONS_H
+#define __ASM_SH_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
#if defined(CONFIG_WATCHDOG)
extern int watchdog_init(void);
extern int watchdog_disable(void);
+# undef INIT_FUNC_WATCHDOG_INIT
# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
# define WATCHDOG_DISABLE watchdog_disable
#else
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
-$(START): $(START:.o=.S)
- $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ \
- -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -I$(TOPDIR)/include \
- -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \
- $(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \
- -I$(TOPDIR)/board -c -o $(START) $(START:.o=.S)
-
sinclude $(obj).depend
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
-/* Force cache miss each time a serial controller reg is read */
-#define CACHE_BYPASS 1
-
-#ifdef CACHE_BYPASS
-#define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)&(var))
-#define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)&(var))
-#define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)&(var))
-#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var))
-#endif
-
static int leon2_serial_init(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
-$(START): $(START:.o=.S)
- $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ \
- -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -I$(TOPDIR)/include \
- -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \
- $(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \
- -I$(TOPDIR)/board -c -o $(START) $(START:.o=.S)
-
sinclude $(obj).depend
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
-/* Force cache miss each time a serial controller reg is read */
-#define CACHE_BYPASS 1
-
-#ifdef CACHE_BYPASS
-#define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)&(var))
-#define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)&(var))
-#define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)&(var))
-#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var))
-#endif
-
ambapp_dev_apbuart *leon3_apbuart = NULL;
static int leon3_serial_init(void)
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_SPARC_SECTIONS_H
+#define __ASM_SPARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
+# Support generic board on x86
+__HAVE_ARCH_GENERIC_BOARD := y
+
PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
#include <asm/u-boot-x86.h>
#include <asm/global_data.h>
#include <asm/processor.h>
+#include <asm/sections.h>
#include <asm/arch/sysinfo.h>
#include <asm/arch/tables.h>
. = ALIGN(4);
__data_end = .;
+ __init_end = .;
. = ALIGN(4);
.dynsym : { *(.dynsym*) }
. = ALIGN(4);
_end = .;
- . = ALIGN(4);
-
- __end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_BOARD
#endif
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_X86_SECTIONS_H
+#define __ASM_X86_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
#ifndef _U_BOOT_I386_H_
#define _U_BOOT_I386_H_ 1
-/* Exports from the Linker Script */
-extern ulong __text_start;
-extern ulong __data_end;
-extern ulong __rel_dyn_start;
-extern ulong __rel_dyn_end;
-extern ulong __bss_start;
-extern ulong __bss_end;
-extern ulong _end;
-
/* cpu/.../cpu.c */
int x86_cpu_init_r(void);
int cpu_init_r(void);
#include <config.h>
#include <compiler.h>
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
+#ifndef __ASSEMBLY__
+
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
}bi_dram[CONFIG_NR_DRAM_BANKS];
} bd_t;
+#endif /* __ASSEMBLY__ */
+
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_I386
LIB = $(obj)lib$(ARCH).o
+ifeq ($(CONFIG_SYS_GENERIC_BOARD),)
COBJS-y += board.o
+endif
+
COBJS-y += bootm.o
COBJS-y += cmd_boot.o
COBJS-y += gcc.o
#include <asm/u-boot-x86.h>
#include <asm/relocate.h>
#include <asm/processor.h>
+#include <asm/sections.h>
#include <asm/init_helpers.h>
#include <asm/init_wrappers.h>
void board_init_f(ulong boot_flags)
{
- gd->fdt_blob = gd->arch.new_fdt = NULL;
+ gd->fdt_blob = gd->new_fdt = NULL;
gd->flags = boot_flags;
do_init_loop(init_sequence_f);
#include <spi.h>
#include <status_led.h>
#include <asm/processor.h>
+#include <asm/sections.h>
#include <asm/u-boot-x86.h>
#include <linux/compiler.h>
*/
if (gd->fdt_blob) {
dest_addr -= fdt_size;
- gd->arch.new_fdt = (void *)dest_addr;
+ gd->new_fdt = (void *)dest_addr;
dest_addr &= ~15;
}
#endif
#include <malloc.h>
#include <asm/u-boot-x86.h>
#include <asm/relocate.h>
+#include <asm/sections.h>
#include <elf.h>
int copy_uboot_to_ram(void)
int copy_fdt_to_ram(void)
{
- if (gd->arch.new_fdt) {
+ if (gd->new_fdt) {
ulong fdt_size;
fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
- memcpy(gd->arch.new_fdt, gd->fdt_blob, fdt_size);
+ memcpy(gd->new_fdt, gd->fdt_blob, fdt_size);
debug("Relocated fdt from %p to %p, size %lx\n",
- gd->fdt_blob, gd->arch.new_fdt, fdt_size);
- gd->fdt_blob = gd->arch.new_fdt;
+ gd->fdt_blob, gd->new_fdt, fdt_size);
+ gd->fdt_blob = gd->new_fdt;
}
return 0;
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
All this can be integrated into an environment command:
=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \
- fdt addr 1800000;fdt boardsetup;erase fc060000 fc07ffff; \
+ fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc060000 fc07ffff; \
cp.b 1800000 fc060000 10000'
=> saveenv
#include <mpc5xxx.h>
#include <pci.h>
#include <miiphy.h>
+#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>
+#ifdef CONFIG_A4M2K
+#include "is46r16320d.h"
+#else
#include "mt46v16m16-75.h"
+#endif
DECLARE_GLOBAL_DATA_PTR;
/* normal operation */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+
+ /*
+ * Wait a short while for the DLL to lock before accessing
+ * the SDRAM
+ */
+ udelay(100);
}
#endif
struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
u8 val;
- /*
- * Figure out failsavelevel
- * see ticket dsvk#59
- */
- *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
-
/* read digitalboard-version from TMR[2..4] */
val = 0;
val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
*digiboardversion = val;
+ /*
+ * A4M2K only supports digiboardversion. No failsavelevel and
+ * fpgaversion here.
+ */
+#if !defined(CONFIG_A4M2K)
+ /*
+ * Figure out failsavelevel
+ * see ticket dsvk#59
+ */
+ *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
+
if (*digiboardversion == 0) {
*failsavelevel = 1; /* digiboard-version ok */
if (*fpgaversion == 1)
*failsavelevel = 2; /* fpga-version ok */
}
+#endif
}
/*
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_A4M2K)
+ /* enable CS3 and CS5 (FPGA) */
+ setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
+#else
int digiboardversion;
int failsavelevel;
int fpgaversion;
/* And write new value back to register */
out_be32(&mm->ipbi_ws_ctrl, val);
+#endif
/*
* No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
* MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
* set bit 0(msb) to 1
*/
- setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0));
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
+
+#if defined(CONFIG_A4M2K)
+ /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
+
+ /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
+ gpio->simple_ddr |= 1 << (31 - 15);
+ gpio->simple_ddr |= 1 << (31 - 14);
+ gpio->simple_ddr |= 1 << (31 - 13);
+ gpio->simple_ddr |= 1 << (31 - 12);
+
+ /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 15);
+ gpio->simple_gpioe |= 1 << (31 - 14);
+ gpio->simple_gpioe |= 1 << (31 - 13);
+ gpio->simple_gpioe |= 1 << (31 - 12);
+
+ /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
+
+ /* set PSC2[0..2] (STSLED[0..2]) direction to output */
+ gpio->simple_ddr |= 1 << (31 - 27);
+ gpio->simple_ddr |= 1 << (31 - 26);
+ gpio->simple_ddr |= 1 << (31 - 25);
+
+ /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 27);
+ gpio->simple_gpioe |= 1 << (31 - 26);
+ gpio->simple_gpioe |= 1 << (31 - 25);
+
+ /* Setup PSC6[2] as MRST2 self reset GPIO output */
+
+ /* set PSC6[2]/IRDA_TX (MRST2) direction to output */
+ gpio->simple_ddr |= 1 << (31 - 3);
+
+ /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
+ gpio->simple_ode |= 1 << (31 - 3);
+ /* set PSC6[2]/IRDA_TX (MRST2) output as default high */
+ gpio->simple_dvo |= 1 << (31 - 3);
+
+ /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 3);
+
+ /* Setup PSC6[3] as HARNSSCD harness code GPIO input */
+
+ /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
+ gpio->simple_ddr |= 0 << (31 - 2);
+
+ /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 2);
+#else
/* setup GPIOs for status-leds if needed - see ticket #57 */
if (failsavelevel > 0) {
/* digiboard-version is OK */
* already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
*/
}
-
+#endif
}
int checkboard(void)
get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+#ifdef CONFIG_A4M2K
+ puts("Board: A4M2K\n");
+ printf(" digiboard IO version %u\n", digiboardversion);
+#else
puts("Board: A3M071\n");
printf("Rev: failsave level %u\n", failsavelevel);
printf(" digiboard IO version %u\n", digiboardversion);
if (failsavelevel > 0) /* only if fpga-version red */
printf(" fpga IO version %u\n", fpgaversion);
+#endif
return 0;
}
return 1;
}
#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+static int watchdog_toggle;
+
+void hw_watchdog_reset(void)
+{
+ int val;
+
+ /*
+ * Check if watchdog is enabled via user command
+ */
+ if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
+ /* Set direction to output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
+
+ /*
+ * Toggle watchdog output
+ */
+ val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+ CONFIG_WDOG_GPIO_PIN);
+ if (val) {
+ clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
+ CONFIG_WDOG_GPIO_PIN);
+ } else {
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
+ CONFIG_WDOG_GPIO_PIN);
+ }
+ }
+}
+
+int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 2)
+ goto usage;
+
+ if (strncmp(argv[1], "on", 2) == 0)
+ watchdog_toggle = 1;
+ else if (strncmp(argv[1], "off", 3) == 0)
+ watchdog_toggle = 0;
+ else
+ goto usage;
+
+ return 0;
+usage:
+ printf("Usage: wdogtoggle %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
+ "toggle GPIO pin to service watchdog",
+ "[on/off] - Switch watchdog toggling via GPIO pin on/off"
+);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define SDRAM_DDR /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
+
+/* SDRAM Config Standard timing */
+#define SDRAM_MODE 0x008d0000
+#define SDRAM_EMODE 0x40010000
+#define SDRAM_CONTROL 0x70430f00
+#define SDRAM_CONFIG1 0x33622930
+#define SDRAM_CONFIG2 0x46670000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- ___bssend___ = .;
+ __bss_end = .;
}
- .bss_end ___bssend___ (OVERLAY) : {
- KEEP(*(.__bss_end__));
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- ___bssend___ = .;
+ __bss_end = .;
}
- .bss_end ___bssend___ (OVERLAY) : {
- KEEP(*(.__bss_end__));
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- ___bssend___ = .;
+ __bss_end = .;
}
- .bss_end ___bssend___ (OVERLAY) : {
- KEEP(*(.__bss_end__));
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} >.sram
__image_copy_end = .;
*(.scommon)
}
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
PROVIDE (end = .);
/* DEBUG -- symbol table, string table, etc. etc.
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
#include <common.h>
#include <linux/byteorder/swab.h>
+#include <asm/sections.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#include <common.h>
#include <linux/byteorder/swab.h>
+#include <asm/sections.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
} :bss
. = ALIGN(4);
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
DECLARE_GLOBAL_DATA_PTR;
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
- CLOCK_SCCR1_LPC_EN | \
- CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
- CLOCK_SCCR1_PSCFIFO_EN | \
- CLOCK_SCCR1_DDR_EN | \
- CLOCK_SCCR1_FEC_EN | \
- CLOCK_SCCR1_NFC_EN | \
- CLOCK_SCCR1_PATA_EN | \
- CLOCK_SCCR1_PCI_EN | \
- CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
- CLOCK_SCCR2_SPDIF_EN | \
- CLOCK_SCCR2_DIU_EN | \
- CLOCK_SCCR2_I2C_EN)
-
-int board_early_init_f(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 spridr;
-
- /*
- * Initialize Local Window for the On Board FPGA access
- */
- out_be32(&im->sysconf.lpcs2aw,
- CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
- CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
- );
- out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
- sync_law(&im->sysconf.lpcs2aw);
-
- /*
- * Initialize Local Window for the On Board SRAM access
- */
- out_be32(&im->sysconf.lpcs6aw,
- CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
- CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
- );
- out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
- sync_law(&im->sysconf.lpcs6aw);
-
- /*
- * Configure Flash Speed
- */
- out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
- spridr = in_be32(&im->sysconf.spridr);
-
- if (SVR_MJREV(spridr) >= 2)
- out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
- /*
- * Enable clocks
- */
- out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
- out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
- setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
- return 0;
-}
-
phys_size_t initdram (int board_type)
{
return fixed_sdram(NULL, NULL, 0);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} >.sram
__image_copy_end = .;
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
_end = .;
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- ___bssend___ = .;
+ __bss_end = .;
}
- .bss_end ___bssend___ (OVERLAY) : {
- KEEP(*(.__bss_end__));
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
DECLARE_GLOBAL_DATA_PTR;
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
- CLOCK_SCCR1_LPC_EN | \
- CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
- CLOCK_SCCR1_PSCFIFO_EN | \
- CLOCK_SCCR1_DDR_EN | \
- CLOCK_SCCR1_FEC_EN | \
- CLOCK_SCCR1_NFC_EN | \
- CLOCK_SCCR1_PCI_EN | \
- CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
- CLOCK_SCCR2_I2C_EN)
-
int eeprom_write_enable(unsigned dev_addr, int state)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
int board_early_init_f(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 spridr;
int i;
/*
- * Initialize Local Window for NOR FLASH access
- */
- out_be32(&im->sysconf.lpcs0aw,
- CSAW_START(CONFIG_SYS_FLASH_BASE) |
- CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
- sync_law(&im->sysconf.lpcs0aw);
-
- /*
* Initialize Local Window for boot access
*/
out_be32(&im->sysconf.lpbaw,
sync_law(&im->sysconf.lpbaw);
/*
- * Initialize Local Window for VPC3 access
- */
- out_be32(&im->sysconf.lpcs1aw,
- CSAW_START(CONFIG_SYS_VPC3_BASE) |
- CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
- sync_law(&im->sysconf.lpcs1aw);
-
- /*
- * Configure Flash Speed
- */
- out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
- /*
- * Configure VPC3 Speed
- */
- out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
-
- spridr = in_be32(&im->sysconf.spridr);
- if (SVR_MJREV(spridr) >= 2)
- out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
- /*
- * Enable clocks
- */
- out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
- out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
- setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
- /*
* Configure MSCAN clocks
*/
for (i=0; i<4; ++i) {
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
DECLARE_GLOBAL_DATA_PTR;
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
- CLOCK_SCCR1_DDR_EN | \
- CLOCK_SCCR1_FEC_EN | \
- CLOCK_SCCR1_LPC_EN | \
- CLOCK_SCCR1_NFC_EN | \
- CLOCK_SCCR1_PATA_EN | \
- CLOCK_SCCR1_PCI_EN | \
- CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
- CLOCK_SCCR1_PSCFIFO_EN | \
- CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
- CLOCK_SCCR2_I2C_EN | \
- CLOCK_SCCR2_MEM_EN | \
- CLOCK_SCCR2_SPDIF_EN | \
- CLOCK_SCCR2_USB1_EN | \
- CLOCK_SCCR2_USB2_EN)
-
void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
int board_early_init_f(void)
{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 spridr;
-
- /*
- * Initialize Local Window for the CPLD registers access (CS2 selects
- * the CPLD chip)
- */
- out_be32(&im->sysconf.lpcs2aw,
- CSAW_START(CONFIG_SYS_CPLD_BASE) |
- CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
- );
- out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
- sync_law(&im->sysconf.lpcs2aw);
-
/*
* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
*
out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
}
#endif
- /*
- * Configure Flash Speed
- */
- out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
- spridr = in_be32(&im->sysconf.spridr);
-
- if (SVR_MJREV (spridr) >= 2)
- out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
- /*
- * Enable clocks
- */
- out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
- out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
- setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
return 0;
}
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- ___bssend___ = .;
+ __bss_end = .;
}
- .bss_end ___bssend___ (OVERLAY) : {
- KEEP(*(.__bss_end__));
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.bss*) }
. = ALIGN(16); /* to speed clearing of bss up */
}
__bss_end = . ;
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
/* Relocated into main memory */
. = ALIGN(16); /* to speed clearing of bss up */
}
__bss_end = . ;
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
/* Relocated into main memory */
. = ALIGN(16); /* to speed clearing of bss up */
}
__bss_end = . ;
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
/* Relocated into main memory */
. = ALIGN(16); /* to speed clearing of bss up */
}
__bss_end = . ;
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
/* Relocated into main memory */
. = ALIGN(16); /* to speed clearing of bss up */
}
__bss_end = . ;
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
/* Relocated into main memory */
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
.ppcenv:
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
common/env_embedded.o (.ppcenv)
}
. = ALIGN(4);
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
common/env_embedded.o (.ppcenv)
}
. = ALIGN(4);
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
_ebss = .;
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
--- /dev/null
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2010 ifm ecomatic GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_configure(void)
+{
+ immap_t *im;
+ gpio512x_t *gpioregs;
+
+ im = (immap_t *) CONFIG_SYS_IMMR;
+ gpioregs = &im->gpio;
+ out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
+ out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
+
+ /*
+ * out_be32(&gpioregs->gpdir, 0xC2293020);
+ * workaround for a hardware affect: configure direction in pieces,
+ * setting all outputs at once drops the reset line too low and
+ * makes us lose the MII connection (breaks ethernet for us)
+ */
+ out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
+ setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
+ udelay(10);
+ setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
+ udelay(10);
+ setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
+ udelay(10);
+ setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
+
+ /* to turn from red to yellow when U-Boot runs */
+ setbits_be32(&gpioregs->gpdat, 0x00002020);
+ out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
+ out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
+ out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
+ out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
+}
+
+/* the physical location of the pins */
+#define GPIOKEY_ROW_BITMASK 0x40000000
+#define GPIOKEY_ROW_UPPER 0
+#define GPIOKEY_ROW_LOWER 1
+
+#define GPIOKEY_COL0_BITMASK 0x20000000
+#define GPIOKEY_COL1_BITMASK 0x10000000
+#define GPIOKEY_COL2_BITMASK 0x08000000
+
+/* the logical presentation of pressed keys */
+#define GPIOKEY_BIT_FNLEFT (1 << 5)
+#define GPIOKEY_BIT_FNRIGHT (1 << 4)
+#define GPIOKEY_BIT_DIRUP (1 << 3)
+#define GPIOKEY_BIT_DIRLEFT (1 << 2)
+#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
+#define GPIOKEY_BIT_DIRDOWN (1 << 0)
+
+/* the hotkey combination which starts recovery */
+#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
+ GPIOKEY_BIT_DIRDOWN)
+
+static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
+{
+
+ if (row)
+ setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+ else
+ clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+ udelay(10);
+}
+
+static u32 gpio_querykbd(void)
+{
+ immap_t *im;
+ gpio512x_t *gpioregs;
+ u32 keybits;
+ u32 input;
+
+ im = (immap_t *)CONFIG_SYS_IMMR;
+ gpioregs = &im->gpio;
+ keybits = 0;
+
+ /* query upper row */
+ gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
+ input = in_be32(&gpioregs->gpdat);
+ if ((input & GPIOKEY_COL0_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_FNLEFT;
+ if ((input & GPIOKEY_COL1_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRUP;
+ if ((input & GPIOKEY_COL2_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_FNRIGHT;
+
+ /* query lower row */
+ gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
+ input = in_be32(&gpioregs->gpdat);
+ if ((input & GPIOKEY_COL0_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRLEFT;
+ if ((input & GPIOKEY_COL1_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRRIGHT;
+ if ((input & GPIOKEY_COL2_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRDOWN;
+
+ /* return bit pattern for keys */
+ return keybits;
+}
+
+/* excerpt from the recovery's hw_info.h */
+
+static int eeprom_diag = 1;
+
+struct __attribute__ ((__packed__)) eeprom_layout {
+ char magic[3]; /** 'ifm' */
+ u8 len[2]; /** content length without magic/len fields */
+ u8 version[3]; /** structure version */
+ u8 type; /** type of PCB */
+ u8 reserved[0x37]; /** padding up to offset 0x40 */
+ u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
+};
+
+#define HW_COMP_MAINCPU 2
+
+static struct eeprom_layout eeprom_content;
+static int eeprom_was_read; /* has_been_read */
+static int eeprom_is_valid;
+static int eeprom_version;
+
+#define get_eeprom_field_int(name) ({ \
+ int value; \
+ int idx; \
+ value = 0; \
+ for (idx = 0; idx < sizeof(name); idx++) { \
+ value <<= 8; \
+ value |= name[idx]; \
+ } \
+ value; \
+})
+
+static int read_eeprom(void)
+{
+ int eeprom_datalen;
+ int ret;
+
+ if (eeprom_was_read)
+ return 0;
+
+ eeprom_is_valid = 0;
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (uchar *)&eeprom_content, sizeof(eeprom_content));
+ if (eeprom_diag) {
+ printf("DIAG: %s() read rc[%d], size[%d]\n",
+ __func__, ret, sizeof(eeprom_content));
+ }
+
+ if (ret != 0)
+ return -1;
+
+ eeprom_was_read = 1;
+
+ /*
+ * check validity of EEPROM content
+ * (check version, length, optionally checksum)
+ */
+ eeprom_is_valid = 1;
+ eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
+ eeprom_version = get_eeprom_field_int(eeprom_content.version);
+
+ if (eeprom_diag) {
+ printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
+ __func__, eeprom_content.magic[0],
+ eeprom_content.magic[1], eeprom_content.magic[2],
+ eeprom_datalen, eeprom_version, eeprom_content.type);
+ }
+ if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
+ eeprom_is_valid = 0;
+ if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
+ eeprom_is_valid = 0;
+ if ((eeprom_version != 1) && (eeprom_version != 2))
+ eeprom_is_valid = 0;
+ if (eeprom_content.type != HW_COMP_MAINCPU)
+ eeprom_is_valid = 0;
+
+ if (eeprom_diag)
+ printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
+
+ return ret;
+}
+
+int mac_read_from_eeprom(void)
+{
+ const u8 *mac;
+
+ if (read_eeprom()) {
+ printf("I2C EEPROM read failed.\n");
+ return -1;
+ }
+
+ if (!eeprom_is_valid) {
+ printf("I2C EEPROM content not valid\n");
+ return -1;
+ }
+
+ mac = NULL;
+ switch (eeprom_version) {
+ case 1:
+ case 2:
+ mac = (const u8 *)&eeprom_content.macaddress;
+ break;
+ }
+
+ if (mac && is_valid_ether_addr(mac)) {
+ eth_setenv_enetaddr("ethaddr", mac);
+ printf("DIAG: %s() MAC value [%s]\n",
+ __func__, getenv("ethaddr"));
+ }
+
+ return 0;
+}
+
+/*
+ * BEWARE!
+ * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
+ * which the ADS, Aria or PDM360NG boards are using
+ * (the steps outlined here refer to the Micron datasheet)
+ */
+u32 sdram_init_seq[] = {
+ /* item 6, at least one NOP after CKE went high */
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 7, precharge all; item 8, tRP (20ns) */
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 9, extended mode register; item 10, tMRD 10ns) */
+ CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 11, (base) mode register _with_ reset DLL;
+ * item 12, tMRD (10ns)
+ */
+ CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
+ CONFIG_SYS_MICRON_BMODE_PARAM,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 13, precharge all; item 14, tRP (20ns) */
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 15, auto refresh (i.e. refresh with CKE held high);
+ * item 16, tRFC (70ns)
+ */
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 17, auto refresh (i.e. refresh with CKE held high);
+ * item 18, tRFC (70ns)
+ */
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
+ CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 21, "actually done", but make sure 200 DRAM clock cycles
+ * have passed after DLL reset before READ requests are issued
+ * (200 cycles at 160MHz -> 1.25 usec)
+ */
+ /* EMPTY, optional, we don't do it */
+};
+
+phys_size_t initdram(int board_type)
+{
+ return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
+}
+
+int misc_init_r(void)
+{
+ u32 keys;
+ char *s;
+ int want_recovery;
+
+ /* we use bus I2C-0 for the on-board eeprom */
+ i2c_set_bus_num(0);
+
+ /* setup GPIO directions and initial values */
+ gpio_configure();
+
+ /*
+ * check the GPIO keyboard,
+ * enforced start of the recovery when
+ * - the appropriate keys were pressed
+ * - a previous installation was aborted or has failed
+ * - "some" external software told us to
+ */
+ want_recovery = 0;
+ keys = gpio_querykbd();
+ printf("GPIO keyboard status [0x%08X]\n", keys);
+ /* XXX insist in the _exact_ combination? */
+ if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
+ printf("GPIO keyboard requested RECOVERY\n");
+ /* XXX TODO
+ * refine the logic to detect the first keypress, and
+ * wait to recheck IF it was the recovery combination?
+ */
+ want_recovery = 1;
+ }
+ s = getenv("install_in_progress");
+ if ((s != NULL) && (*s != '\0')) {
+ printf("previous installation aborted, running RECOVERY\n");
+ want_recovery = 1;
+ }
+ s = getenv("install_failed");
+ if ((s != NULL) && (*s != '\0')) {
+ printf("previous installation FAILED, running RECOVERY\n");
+ want_recovery = 1;
+ }
+ s = getenv("want_recovery");
+ if ((s != NULL) && (*s != '\0')) {
+ printf("running RECOVERY according to the request\n");
+ want_recovery = 1;
+ }
+
+ if (want_recovery)
+ setenv("bootcmd", "run recovery");
+
+ /*
+ * boot the recovery system without waiting; boot the
+ * production system without waiting by default, only
+ * insert a pause (to provide a chance to get a prompt)
+ * when GPIO keys were pressed during power on
+ */
+ if (want_recovery)
+ setenv("bootdelay", "0");
+ else if (!keys)
+ setenv("bootdelay", "0");
+ else
+ setenv("bootdelay", "2");
+
+ /* get the ethernet MAC from I2C EEPROM */
+ mac_read_from_eeprom();
+
+ return 0;
+}
+
+/* setup specific IO pad configuration */
+static iopin_t ioregs_init[] = {
+ { /* LPC CS3 */
+ offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* LPC CS1 */
+ offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC CS2 */
+ offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC CS4, CS5 */
+ offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* SDHC CLK, CMD, D0, D1, D2, D3 */
+ offsetof(struct ioctrl512x, io_control_pata_ior), 6,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* GPIO keyboard */
+ offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO DN1 PF, LCD power, DN2 PF */
+ offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO reset AS-i */
+ offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO reset safety */
+ offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO reset netX */
+ offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO ma2 en */
+ offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO SD CD, SD WP */
+ offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* FEC RX DV */
+ offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(2),
+ },
+ { /* GPIO AS-i prog, AS-i done, LCD backlight */
+ offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO AS-i wdg */
+ offsetof(struct ioctrl512x, io_control_pci_req2), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO safety wdg */
+ offsetof(struct ioctrl512x, io_control_pci_req1), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO netX wdg */
+ offsetof(struct ioctrl512x, io_control_pci_req0), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO IRQ powerfail */
+ offsetof(struct ioctrl512x, io_control_pci_inta), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO AS-i PWRD */
+ offsetof(struct ioctrl512x, io_control_pci_frame), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO LED0, LED1 */
+ offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
+ offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* DIU clk */
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(2),
+ },
+ { /* FEC TX ER, CRS */
+ offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
+ offsetof(struct ioctrl512x, io_control_irq0), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /*
+ * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
+ * rdx 3-0, mdio, rx clk
+ */
+ offsetof(struct ioctrl512x, io_control_psc0_0), 15,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ /* optional: make sure PSC3 remains the serial console */
+ { /* LPC CS6 */
+ offsetof(struct ioctrl512x, io_control_psc3_4), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ /* make sure PSC4 remains available for SPI,
+ *BUT* PSC4_1 is a GPIO kind of SS! */
+ { /* enforce drive strength on the SPI pin */
+ offsetof(struct ioctrl512x, io_control_psc4_0), 5,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_1), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ /* optional: make sure PSC5 remains available for SPI */
+ { /* enforce drive strength on the SPI pin */
+ offsetof(struct ioctrl512x, io_control_psc5_0), 5,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(1),
+ },
+ { /* LPC TSIZ1 */
+ offsetof(struct ioctrl512x, io_control_psc6_0), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* DIU hsync */
+ offsetof(struct ioctrl512x, io_control_psc6_1), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* DIU vsync */
+ offsetof(struct ioctrl512x, io_control_psc6_4), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* PSC7, part of DIU RGB */
+ offsetof(struct ioctrl512x, io_control_psc7_0), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* PSC7, safety UART */
+ offsetof(struct ioctrl512x, io_control_psc7_2), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(0) | IO_PIN_DS(1),
+ },
+ { /* DIU (part of) RGB[] */
+ offsetof(struct ioctrl512x, io_control_psc8_3), 16,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* DIU data enable */
+ offsetof(struct ioctrl512x, io_control_psc11_4), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ /* reduce LPB drive strength for improved EMI */
+ { /* LPC OE, LPC RW */
+ offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC AX03 through LPC AD00 */
+ offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC CS5 */
+ offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* SDHC CLK */
+ offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* SDHC DATA */
+ offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+};
+
+int checkboard(void)
+{
+ puts("Board: ifm AC14xx\n");
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+ iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
#include <libfdt.h>
#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
-#endif
-
#include "../common/common.h"
/*
* will toggle once what forces the mgocge3un part to restart
* immediately.
*/
-void handle_mgcoge3un_reset(void)
+static void handle_mgcoge3un_reset(void)
{
char *bobcatreset = getenv("bobcatreset");
if (bobcatreset) {
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(.sbss*)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \
- fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o
-
-SOBJS =
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _CPC710_H_
-#define _CPC710_H_
-
-/* Revision */
-#define CPC710_TYPE_100 0x80
-#define CPC710_TYPE_100P 0x90
-
-/* System control area */
-#define HW_PHYS_SCA 0xff000000
-
-#define HW_SCA_CPC0 0x000000
-#define HW_SCA_SDRAM0 0x000000
-#define HW_SCA_DMA0 0x1C0000
-
-#define HW_PHYS_CPC0 (HW_PHYS_SCA + HW_SCA_CPC0)
-#define HW_PHYS_SDRAM0 (HW_PHYS_SCA + HW_SCA_SDRAM0)
-
-#define HW_CPC0_PCICNFR 0x000c
-#define HW_CPC0_RSTR 0x0010
-#define HW_CPC0_SPOR 0x00e8
-#define HW_CPC0_UCTL 0x1000
-#define HW_CPC0_SIOC0 0x1020
-#define HW_CPC0_ABCNTL 0x1030
-#define HW_CPC0_SESR 0x1060
-#define HW_CPC0_SEAR 0x1070
-#define HW_CPC0_PGCHP 0x1100
-#define HW_CPC0_RGBAN0 0x1110
-#define HW_CPC0_RGBAN1 0x1120
-
-#define HW_CPC0_GPDIR 0x1130
-#define HW_CPC0_GPIN 0x1140
-#define HW_CPC0_GPOUT 0x1150
-
-#define HW_CPC0_ATAS 0x1160
-
-#define HW_CPC0_PCIBAR 0x200018
-#define HW_CPC0_PCIENB 0x201000
-
-#define HW_SDRAM0_MCCR 0x1200
-#define HW_SDRAM0_MESR 0x1220
-#define HW_SDRAM0_MEAR 0x1230
-
-#define HW_SDRAM0_MCER0 0x1300
-#define HW_SDRAM0_MCER1 0x1310
-#define HW_SDRAM0_MCER2 0x1320
-#define HW_SDRAM0_MCER3 0x1330
-#define HW_SDRAM0_MCER4 0x1340
-#define HW_SDRAM0_MCER5 0x1350
-#define HW_SDRAM0_MCER6 0x1360
-#define HW_SDRAM0_MCER7 0x1370
-
-#define HW_BRIDGE_PCIDG 0xf6120
-#define HW_BRIDGE_INTACK 0xf7700
-#define HW_BRIDGE_PIBAR 0xf7800
-#define HW_BRIDGE_PMBAR 0xf7810
-#define HW_BRIDGE_CRR 0xf7ef0
-#define HW_BRIDGE_PR 0xf7f20
-#define HW_BRIDGE_ACR 0xf7f30
-#define HW_BRIDGE_MSIZE 0xf7f40
-#define HW_BRIDGE_IOSIZE 0xf7f60
-#define HW_BRIDGE_SMBAR 0xf7f80
-#define HW_BRIDGE_SIBAR 0xf7fc0
-#define HW_BRIDGE_CFGADDR 0xf8000
-#define HW_BRIDGE_CFGDATA 0xf8010
-#define HW_BRIDGE_PSSIZE 0xf8100
-#define HW_BRIDGE_BARPS 0xf8120
-#define HW_BRIDGE_PSBAR 0xf8140
-
-/* Configuration space registers */
-#define CPC710_BUS_NUMBER 0x40
-#define CPC710_SUB_BUS_NUMBER 0x41
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-
-#include "pcippc2.h"
-#include "i2c.h"
-
-typedef struct cpc710_mem_org_s {
- u8 rows;
- u8 cols;
- u8 banks2;
- u8 org;
-} cpc710_mem_org_t;
-
-static int cpc710_compute_mcer (u32 * mcer,
- unsigned long *size, unsigned int sdram);
-static int cpc710_eeprom_checksum (unsigned int sdram);
-static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset);
-
-static u32 cpc710_mcer_mem[] = {
- 0x000003f3, /* 18 lines, 4 Mb */
- 0x000003e3, /* 19 lines, 8 Mb */
- 0x000003c3, /* 20 lines, 16 Mb */
- 0x00000383, /* 21 lines, 32 Mb */
- 0x00000303, /* 22 lines, 64 Mb */
- 0x00000203, /* 23 lines, 128 Mb */
- 0x00000003, /* 24 lines, 256 Mb */
- 0x00000002, /* 25 lines, 512 Mb */
- 0x00000001 /* 26 lines, 1024 Mb */
-};
-static cpc710_mem_org_t cpc710_mem_org[] = {
- {0x0c, 0x09, 0x02, 0x00}, /* 0000: 12/ 9/2 */
- {0x0d, 0x09, 0x02, 0x00}, /* 0000: 13/ 9/2 */
- {0x0d, 0x0a, 0x02, 0x00}, /* 0000: 13/10/2 */
- {0x0d, 0x0b, 0x02, 0x00}, /* 0000: 13/11/2 */
- {0x0d, 0x0c, 0x02, 0x00}, /* 0000: 13/12/2 */
- {0x0e, 0x0c, 0x02, 0x00}, /* 0000: 14/12/2 */
- {0x0b, 0x08, 0x02, 0x01}, /* 0001: 11/ 8/2 */
- {0x0b, 0x09, 0x01, 0x02}, /* 0010: 11/ 9/1 */
- {0x0b, 0x0a, 0x01, 0x03}, /* 0011: 11/10/1 */
- {0x0c, 0x08, 0x02, 0x04}, /* 0100: 12/ 8/2 */
- {0x0c, 0x0a, 0x02, 0x05}, /* 0101: 12/10/2 */
- {0x0d, 0x08, 0x01, 0x06}, /* 0110: 13/ 8/1 */
- {0x0d, 0x08, 0x02, 0x07}, /* 0111: 13/ 8/2 */
- {0x0d, 0x09, 0x01, 0x08}, /* 1000: 13/ 9/1 */
- {0x0d, 0x0a, 0x01, 0x09}, /* 1001: 13/10/1 */
- {0x0b, 0x08, 0x01, 0x0a}, /* 1010: 11/ 8/1 */
- {0x0c, 0x08, 0x01, 0x0b}, /* 1011: 12/ 8/1 */
- {0x0c, 0x09, 0x01, 0x0c}, /* 1100: 12/ 9/1 */
- {0x0e, 0x09, 0x02, 0x0d}, /* 1101: 14/ 9/2 */
- {0x0e, 0x0a, 0x02, 0x0e}, /* 1110: 14/10/2 */
- {0x0e, 0x0b, 0x02, 0x0f} /* 1111: 14/11/2 */
-};
-
-unsigned long cpc710_ram_init (void)
-{
- unsigned long memsize = 0;
- unsigned long bank_size;
- u32 mcer;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* Clear memory banks
- */
- out32 (REG (SDRAM0, MCER0), 0);
- out32 (REG (SDRAM0, MCER1), 0);
- out32 (REG (SDRAM0, MCER2), 0);
- out32 (REG (SDRAM0, MCER3), 0);
- out32 (REG (SDRAM0, MCER4), 0);
- out32 (REG (SDRAM0, MCER5), 0);
- out32 (REG (SDRAM0, MCER6), 0);
- out32 (REG (SDRAM0, MCER7), 0);
- iobarrier_rw ();
-
- /* Disable memory
- */
- out32 (REG (SDRAM0, MCCR), 0x13b06000);
- iobarrier_rw ();
-#endif
-
- /* Only the first memory bank is initialised now
- */
- if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) {
- puts ("Unsupported SDRAM type !\n");
- hang ();
- }
- memsize += bank_size;
-#ifndef CONFIG_SYS_RAMBOOT
- /* Enable bank, zero start
- */
- out32 (REG (SDRAM0, MCER0), mcer | 0x80000000);
- iobarrier_rw ();
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* Enable memory
- */
- out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000);
-
- /* Wait until initialisation finished
- */
- while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) {
- iobarrier_rw ();
- }
-
- /* Clear Memory Error Status and Address registers
- */
- out32 (REG (SDRAM0, MESR), 0);
- out32 (REG (SDRAM0, MEAR), 0);
- iobarrier_rw ();
-
- /* ECC is not configured now
- */
-#endif
-
- /* Memory size counter
- */
- out32 (REG (CPC0, RGBAN1), memsize);
-
- return memsize;
-}
-
-static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram)
-{
- u8 rows;
- u8 cols;
- u8 banks2;
- unsigned int lines;
- u32 mc = 0;
- unsigned int i;
- cpc710_mem_org_t *org = 0;
-
- if (!i2c_reset ()) {
- puts ("Can't reset I2C!\n");
- hang ();
- }
-
- if (!cpc710_eeprom_checksum (sdram)) {
- puts ("Invalid EEPROM checksum !\n");
- hang ();
- }
-
- rows = cpc710_eeprom_read (sdram, 3);
- cols = cpc710_eeprom_read (sdram, 4);
- /* Can be 2 or 4 banks; divide by 2
- */
- banks2 = cpc710_eeprom_read (sdram, 17) / 2;
-
- lines = rows + cols + banks2;
-
- if (lines < 18 || lines > 26) {
- /* Unsupported configuration
- */
- return 0;
- }
-
- mc |= cpc710_mcer_mem[lines - 18] << 6;
-
- for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t);
- i++) {
- cpc710_mem_org_t *corg = cpc710_mem_org + i;
-
- if (corg->rows == rows && corg->cols == cols
- && corg->banks2 == banks2) {
- org = corg;
-
- break;
- }
- }
-
- if (!org) {
- /* Unsupported configuration
- */
- return 0;
- }
-
- mc |= (u32) org->org << 2;
-
- /* Supported configuration
- */
- *mcer = mc;
- *size = 1l << (lines + 4);
-
- return 1;
-}
-
-static int cpc710_eeprom_checksum (unsigned int sdram)
-{
- u8 sum = 0;
- unsigned int i;
-
- for (i = 0; i < 63; i++) {
- sum += cpc710_eeprom_read (sdram, i);
- }
-
- return sum == cpc710_eeprom_read (sdram, 63);
-}
-
-static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset)
-{
- u8 dev = (sdram << 1) | 0xa0;
- u8 data;
-
- if (!i2c_read_byte (&data, dev, offset)) {
- puts ("I2C error !\n");
- hang ();
- }
-
- return data;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#include "hardware.h"
-#include "pcippc2.h"
-
-struct pci_controller local_hose, cpci_hose;
-
-static u32 cpc710_mapped_ram;
-
- /* Enable PCI retry timeouts
- */
-void cpc710_pci_enable_timeout (void)
-{
- out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, CFGDATA), 0x32000000);
- iobarrier_rw();
-
- out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
- iobarrier_rw();
-}
-
-void cpc710_pci_init (void)
-{
- u32 sdram_size = pcippc2_sdram_size();
-
- cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ?
- sdram_size : PCI_MEMORY_MAXSIZE;
-
- /* Select the local PCI
- */
- out32(REG(CPC0, PCICNFR), 0x80000002);
- iobarrier_rw();
-
- out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS);
- iobarrier_rw();
-
- /* Enable PCI bridge address decoding
- */
- out32(REG(CPC0, PCIENB), 0x80000000);
- iobarrier_rw();
-
- /* Select the CPCI bridge
- */
- out32(REG(CPC0, PCICNFR), 0x80000003);
- iobarrier_rw();
-
- out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS);
- iobarrier_rw();
-
- /* Enable PCI bridge address decoding
- */
- out32(REG(CPC0, PCIENB), 0x80000000);
- iobarrier_rw();
-
- /* Disable configuration accesses
- */
- out32(REG(CPC0, PCICNFR), 0x80000000);
- iobarrier_rw();
-
- /* Initialise the local PCI
- */
- out32(BRIDGE(LOCAL, CRR), 0x7c000000);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, PCIDG), 0x40000000);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS);
- out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS);
- out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS);
- out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS);
- out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, PR), 0x00ffe000);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, ACR), 0xfe000000);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24);
- out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24);
- out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
- iobarrier_rw();
-
- /* Initialise the CPCI bridge
- */
- out32(BRIDGE(CPCI, CRR), 0x7c000000);
- iobarrier_rw();
- out32(BRIDGE(CPCI, PCIDG), 0xC0000000);
- iobarrier_rw();
- out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS);
- out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS);
- out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE);
- iobarrier_rw();
- out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS);
- out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS);
- out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE);
- iobarrier_rw();
- out32(BRIDGE(CPCI, PR), 0x80ffe000);
- iobarrier_rw();
- out32(BRIDGE(CPCI, ACR), 0xdf000000);
- iobarrier_rw();
- out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24);
- out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24);
- out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
- iobarrier_rw();
-
- /* Local PCI
- */
-
- out32(BRIDGE(LOCAL, CFGADDR), 0x04000080);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, CFGDATA), 0x56010000);
- iobarrier_rw();
-
- out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
- iobarrier_rw();
-
- /* Set bus and subbus numbers
- */
- out32(BRIDGE(LOCAL, CFGADDR), 0x40000080);
- iobarrier_rw();
- out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
- iobarrier_rw();
-
- out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
- iobarrier_rw();
- /* PCI retry timeouts will be enabled later
- */
- out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
- iobarrier_rw();
-
- /* CPCI
- */
-
- /* Set bus and subbus numbers
- */
- out32(BRIDGE(CPCI, CFGADDR), 0x40000080);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CFGDATA), 0x01010000);
- iobarrier_rw();
-
- out32(BRIDGE(CPCI, CFGADDR), 0x04000180);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CFGDATA), 0x56010000);
- iobarrier_rw();
-
- out32(BRIDGE(CPCI, CFGADDR), 0x0c000180);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
- iobarrier_rw();
-
- /* Write to the PSBAR */
- out32(BRIDGE(CPCI, CFGADDR), 0x10000180);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS));
- iobarrier_rw();
-
- /* Set bus and subbus numbers
- */
- out32(BRIDGE(CPCI, CFGADDR), 0x40000180);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000);
- iobarrier_rw();
-
- out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
- /* PCI retry timeouts will be enabled later
- */
- out32(BRIDGE(CPCI, CFGDATA), 0x00000000);
- iobarrier_rw();
-
- /* Remove reset on the PCI buses
- */
- out32(BRIDGE(LOCAL, CRR), 0xfc000000);
- iobarrier_rw();
- out32(BRIDGE(CPCI, CRR), 0xfc000000);
- iobarrier_rw();
-
- local_hose.first_busno = 0;
- local_hose.last_busno = 0xff;
-
- /* System memory space */
- pci_set_region(local_hose.regions + 0,
- PCI_MEMORY_BUS,
- PCI_MEMORY_PHYS,
- PCI_MEMORY_MAXSIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(local_hose.regions + 1,
- BRIDGE_LOCAL_MEM_BUS,
- BRIDGE_LOCAL_MEM_PHYS,
- BRIDGE_LOCAL_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(local_hose.regions + 2,
- BRIDGE_LOCAL_IO_BUS,
- BRIDGE_LOCAL_IO_PHYS,
- BRIDGE_LOCAL_IO_SIZE,
- PCI_REGION_IO);
-
- local_hose.region_count = 3;
-
- pci_setup_indirect(&local_hose,
- BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR,
- BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA);
-
- pci_register_hose(&local_hose);
-
- /* Initialize PCI32 bus registers */
- pci_hose_write_config_byte(&local_hose,
- PCI_BDF(local_hose.first_busno,0,0),
- CPC710_BUS_NUMBER,
- local_hose.first_busno);
- pci_hose_write_config_byte(&local_hose,
- PCI_BDF(local_hose.first_busno,0,0),
- CPC710_SUB_BUS_NUMBER,
- local_hose.last_busno);
-
- local_hose.last_busno = pci_hose_scan(&local_hose);
-
- /* Write out correct max subordinate bus number for local hose */
- pci_hose_write_config_byte(&local_hose,
- PCI_BDF(local_hose.first_busno,0,0),
- CPC710_SUB_BUS_NUMBER,
- local_hose.last_busno);
-
- cpci_hose.first_busno = local_hose.last_busno + 1;
- cpci_hose.last_busno = 0xff;
-
- /* System memory space */
- pci_set_region(cpci_hose.regions + 0,
- PCI_MEMORY_BUS,
- PCI_MEMORY_PHYS,
- PCI_MEMORY_MAXSIZE,
- PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(cpci_hose.regions + 1,
- BRIDGE_CPCI_MEM_BUS,
- BRIDGE_CPCI_MEM_PHYS,
- BRIDGE_CPCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(cpci_hose.regions + 2,
- BRIDGE_CPCI_IO_BUS,
- BRIDGE_CPCI_IO_PHYS,
- BRIDGE_CPCI_IO_SIZE,
- PCI_REGION_IO);
-
- cpci_hose.region_count = 3;
-
- pci_setup_indirect(&cpci_hose,
- BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR,
- BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA);
-
- pci_register_hose(&cpci_hose);
-
- /* Initialize PCI64 bus registers */
- pci_hose_write_config_byte(&cpci_hose,
- PCI_BDF(cpci_hose.first_busno,0,0),
- CPC710_BUS_NUMBER,
- cpci_hose.first_busno);
- pci_hose_write_config_byte(&cpci_hose,
- PCI_BDF(cpci_hose.first_busno,0,0),
- CPC710_SUB_BUS_NUMBER,
- cpci_hose.last_busno);
-
- cpci_hose.last_busno = pci_hose_scan(&cpci_hose);
-
- /* Write out correct max subordinate bus number for cpci hose */
- pci_hose_write_config_byte(&cpci_hose,
- PCI_BDF(cpci_hose.first_busno,0,0),
- CPC710_SUB_BUS_NUMBER,
- cpci_hose.last_busno);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _CPC710_PCI_H_
-#define _CPC710_PCI_H_
-
-#define PCI_MEMORY_PHYS 0x00000000
-#define PCI_MEMORY_BUS 0x80000000
-#define PCI_MEMORY_MAXSIZE 0x20000000
-
-#define BRIDGE_CPCI_PHYS 0xff500000
-#define BRIDGE_CPCI_MEM_SIZE 0x08000000
-#define BRIDGE_CPCI_MEM_PHYS 0xf0000000
-#define BRIDGE_CPCI_MEM_BUS 0x00000000
-#define BRIDGE_CPCI_IO_SIZE 0x02000000
-#define BRIDGE_CPCI_IO_PHYS 0xfc000000
-#define BRIDGE_CPCI_IO_BUS 0x00000000
-
-#define BRIDGE_LOCAL_PHYS 0xff400000
-#define BRIDGE_LOCAL_MEM_SIZE 0x04000000
-#define BRIDGE_LOCAL_MEM_PHYS 0xf8000000
-#define BRIDGE_LOCAL_MEM_BUS 0x40000000
-#define BRIDGE_LOCAL_IO_SIZE 0x01000000
-#define BRIDGE_LOCAL_IO_PHYS 0xfe000000
-#define BRIDGE_LOCAL_IO_BUS 0x04000000
-
-#define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x)
-
-#define PCI_LATENCY_TIMER_VAL 0xff
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static ulong flash_get_size (ulong addr, flash_info_t *info);
-static int flash_get_offsets (ulong base, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_reset (ulong addr);
-
-unsigned long flash_init (void)
-{
- unsigned int i;
- unsigned long flash_size = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = 0;
- flash_info[i].size = 0;
- }
-
- DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
-
- flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
-
- DEBUGF("## Flash bank size: %08lx\n", flash_size);
-
- if (flash_size) {
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
- CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- } else {
- puts ("Warning: the BOOT Flash is not initialised !");
- }
-
- return flash_size;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (ulong addr, flash_info_t *info)
-{
- short i;
- uchar value;
-
- /* Write auto select command: read Manufacturer ID */
- out8(addr + 0x0555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x02AA, 0x55);
- iobarrier_rw();
- out8(addr + 0x0555, 0x90);
- iobarrier_rw();
-
- value = in8(addr);
- iobarrier_rw();
-
- DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
-
- switch (value | (value << 16)) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
-
- case STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- flash_reset (addr);
- return 0;
- }
-
- value = in8(addr + 1); /* device ID */
- iobarrier_rw();
-
- DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
-
- switch ((ulong)value) {
- case AMD_ID_F040B:
- DEBUGF("Am29F040B\n");
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case AMD_ID_LV040B:
- DEBUGF("Am29LV040B\n");
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case AMD_ID_LV400T:
- DEBUGF("Am29LV400T\n");
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- DEBUGF("Am29LV400B\n");
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- DEBUGF("Am29LV800T\n");
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- DEBUGF("Am29LV400B\n");
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- DEBUGF("Am29LV160T\n");
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- DEBUGF("Am29LV160B\n");
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV320T:
- DEBUGF("Am29LV320T\n");
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
-#if 0
- /* Has the same ID as AMD_ID_LV320T, to be fixed */
- case AMD_ID_LV320B:
- DEBUGF("Am29LV320B\n");
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
-
- case AMD_ID_LV033C:
- DEBUGF("Am29LV033C\n");
- info->flash_id += FLASH_AM033C;
- info->sector_count = 64;
- info->size = 0x01000000;
- break; /* => 16Mb */
-
- case STM_ID_F040B:
- DEBUGF("M29F040B\n");
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- flash_reset (addr);
- return (0); /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- if (! flash_get_offsets (addr, info)) {
- flash_reset (addr);
- return 0;
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- value = in8(info->start[i] + 2);
- iobarrier_rw();
- info->protect[i] = (value & 1) != 0;
- }
-
- /*
- * Reset bank to read mode
- */
- flash_reset (addr);
-
- return (info->size);
-}
-
-static int flash_get_offsets (ulong base, flash_info_t *info)
-{
- unsigned int i;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- /* set sector offsets for uniform sector type */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + i * info->size /
- info->sector_count;
- }
- break;
- default:
- return 0;
- }
-
- return 1;
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile ulong addr = info->start[0];
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if (s_first < 0 || s_first > s_last) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
- out8(addr + 0x555, 0x80);
- iobarrier_rw();
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = info->start[sect];
- out8(addr, 0x30);
- iobarrier_rw();
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = info->start[l_sect];
-
- DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
-
- while ((in8(addr) & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- flash_reset (info->start[0]);
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- iobarrier_rw();
- }
-
-DONE:
- /* reset to read mode */
- flash_reset (info->start[0]);
-
- printf (" done\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile ulong addr = info->start[0];
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((in32(dest) & data) != data) {
- return (2);
- }
-
- /* write each byte out */
- for (i = 0; i < 4; i++) {
- char *data_ch = (char *)&data;
- int flag = disable_interrupts();
-
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
- out8(addr + 0x555, 0xA0);
- iobarrier_rw();
- out8(dest+i, data_ch[i]);
- iobarrier_rw();
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flash_reset (addr);
- return (1);
- }
- iobarrier_rw();
- }
- }
-
- flash_reset (addr);
- return (0);
-}
-
-/*
- * Reset bank to read mode
- */
-static void flash_reset (ulong addr)
-{
- out8(addr, 0xF0); /* reset bank */
- iobarrier_rw();
-}
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_STM: printf ("SGS THOMSON "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size % 0x100000 == 0) {
- printf (" Size: %ld MB in %d Sectors\n",
- info->size / 0x100000, info->sector_count);
- } else if (info->size % 0x400 == 0) {
- printf (" Size: %ld KB in %d Sectors\n",
- info->size / 0x400, info->sector_count);
- } else {
- printf (" Size: %ld B in %d Sectors\n",
- info->size, info->sector_count);
- }
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-
-#include "fpga_serial.h"
-#include "hardware.h"
-#include "pcippc2.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
- /* 8 data, 1 stop, no parity
- */
-#define LCRVAL 0x03
- /* RTS/DTR
- */
-#define MCRVAL 0x03
- /* Clear & enable FIFOs
- */
-#define FCRVAL 0x07
-
-static void fpga_serial_wait (void);
-static void fpga_serial_print (char c);
-
-void fpga_serial_init (int baudrate)
-{
- int clock_divisor = 115200 / baudrate;
-
- out8 (FPGA (INT, SERIAL_CONFIG), 0x24);
- iobarrier_rw ();
-
- fpga_serial_wait ();
-
- out8 (UART (IER), 0);
- out8 (UART (LCR), LCRVAL | 0x80);
- iobarrier_rw ();
- out8 (UART (DLL), clock_divisor & 0xff);
- out8 (UART (DLM), clock_divisor >> 8);
- iobarrier_rw ();
- out8 (UART (LCR), LCRVAL);
- iobarrier_rw ();
- out8 (UART (MCR), MCRVAL);
- out8 (UART (FCR), FCRVAL);
- iobarrier_rw ();
-}
-
-void fpga_serial_putc (char c)
-{
- if (c) {
- fpga_serial_print (c);
- }
-}
-
-int fpga_serial_getc (void)
-{
- while ((in8 (UART (LSR)) & 0x01) == 0);
-
- return in8 (UART (RBR));
-}
-
-int fpga_serial_tstc (void)
-{
- return (in8 (UART (LSR)) & 0x01) != 0;
-}
-
-void fpga_serial_setbrg (void)
-{
- int clock_divisor = 115200 / gd->baudrate;
-
- fpga_serial_wait ();
-
- out8 (UART (LCR), LCRVAL | 0x80);
- iobarrier_rw ();
- out8 (UART (DLL), clock_divisor & 0xff);
- out8 (UART (DLM), clock_divisor >> 8);
- iobarrier_rw ();
- out8 (UART (LCR), LCRVAL);
- iobarrier_rw ();
-}
-
-static void fpga_serial_wait (void)
-{
- while ((in8 (UART (LSR)) & 0x40) == 0);
-}
-
-static void fpga_serial_print (char c)
-{
- if (c == '\n') {
- while ((in8 (UART (LSR)) & 0x20) == 0);
-
- out8 (UART (THR), '\r');
- iobarrier_rw ();
- }
-
- while ((in8 (UART (LSR)) & 0x20) == 0);
-
- out8 (UART (THR), c);
- iobarrier_rw ();
-
- if (c == '\n') {
- fpga_serial_wait ();
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _HARDWARE_H_
-#define _HARDWARE_H_
-
-#include "cpc710.h"
-#include "cpc710_pci.h"
-#include "pcippc2_fpga.h"
-#include "ns16550.h"
-
-#define REG(r, x) (HW_PHYS_##r + HW_##r##_##x)
-
- /* Address map:
- *
- * 0x00000000-0x20000000 SDRAM
- * 0x40000000-0x00008000 Init RAM in the CPU DCache
- * 0xf0000000-0xf8000000 CPCI MEM
- * 0xf8000000-0xfc000000 Local PCI MEM
- * 0xfc000000-0xfe000000 CPCI I/O
- * 0xfe000000-0xff000000 Local PCI I/O
- * 0xff000000-0xff201000 System configuration space
- * 0xff400000-0xff500000 Local PCI bridge space
- * 0xff500000-0xff600000 CPCI bridge space
- * 0xfff00000-0xfff80000 Boot Flash
- */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-
-#include "hardware.h"
-#include "i2c.h"
-
-static void i2c_start (void);
-static void i2c_stop (void);
-static int i2c_write (u8 data);
-static void i2c_read (u8 * data);
-
-static inline void i2c_port_start (void);
-static inline void i2c_clock (unsigned int val);
-static inline void i2c_data (unsigned int val);
-static inline unsigned int
- i2c_in (void);
-static inline void i2c_write_bit (unsigned int val);
-static inline unsigned int
- i2c_read_bit (void);
-
-static inline void i2c_udelay (unsigned int time);
-
-int i2c_read_byte (
- u8 * data,
- u8 dev,
- u8 offset)
-{
- int err = 0;
-
- i2c_start();
-
- err = ! i2c_write(dev);
-
- if (! err)
- {
- err = ! i2c_write(offset);
- }
-
- if (! err)
- {
- i2c_start();
- }
-
- if (! err)
- {
- err = ! i2c_write(dev | 0x01);
- }
-
- if (! err)
- {
- i2c_read(data);
- }
-
- i2c_stop();
-
- return ! err;
-}
-
-static inline void i2c_udelay (
- unsigned int time)
-{
- int v;
-
- asm volatile("mtdec %0" : : "r" (time * ((CONFIG_SYS_BUS_CLK / 4) / 1000000)));
-
- do
- {
- asm volatile("isync; mfdec %0" : "=r" (v));
- } while (v >= 0);
-}
-
- /* Low-level hardware access
- */
-
-#define BIT_GPDATA 0x80000000
-#define BIT_GPCLK 0x40000000
-
-static inline void i2c_port_start (void)
-{
- out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~(BIT_GPCLK | BIT_GPDATA));
- out32(REG(CPC0, GPOUT), in32(REG(CPC0, GPOUT)) & ~(BIT_GPCLK | BIT_GPDATA));
- iobarrier_rw();
-
- i2c_udelay(1);
-}
-
-static inline void i2c_clock (
- unsigned int val)
-{
- if (val)
- {
- out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPCLK);
- }
- else
- {
- out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPCLK);
- }
-
- iobarrier_rw();
-
- i2c_udelay(1);
-}
-
-static inline void i2c_data (
- unsigned int val)
-{
- if (val)
- {
- out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPDATA);
- }
- else
- {
- out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPDATA);
- }
-
- iobarrier_rw();
-
- i2c_udelay(1);
-}
-
-static inline unsigned int i2c_in (void)
-{
- unsigned int val = ((in32(REG(CPC0, GPIN)) & BIT_GPDATA) != 0)?1:0;
-
- iobarrier_rw();
-
- return val;
-}
-
-
- /* Protocol implementation
- */
-
-static inline void i2c_write_bit (
- unsigned int val)
-{
- i2c_data(val);
- i2c_udelay(10);
- i2c_clock(1);
- i2c_udelay(10);
- i2c_clock(0);
- i2c_udelay(10);
-}
-
-static inline unsigned int i2c_read_bit (void)
-{
- unsigned int val;
-
- i2c_data(1);
- i2c_udelay(10);
-
- i2c_clock(1);
- i2c_udelay(10);
-
- val = i2c_in();
-
- i2c_clock(0);
- i2c_udelay(10);
-
- return val;
-}
-
-unsigned int i2c_reset (void)
-{
- unsigned int val;
- int i;
-
- i2c_port_start();
-
- i=0;
- do {
- i2c_udelay(10);
- i2c_clock(0);
- i2c_udelay(10);
- i2c_clock(1);
- i2c_udelay(10);
- val = i2c_in();
- i++;
- } while ((i<9)&&(val==0));
- return (val);
-}
-
-
-static void i2c_start (void)
-{
- i2c_data(1);
- i2c_clock(1);
- i2c_udelay(10);
- i2c_data(0);
- i2c_udelay(10);
- i2c_clock(0);
- i2c_udelay(10);
-}
-
-static void i2c_stop (void)
-{
- i2c_data(0);
- i2c_udelay(10);
- i2c_clock(1);
- i2c_udelay(10);
- i2c_data(1);
- i2c_udelay(10);
-}
-
-static int i2c_write (
- u8 data)
-{
- unsigned int i;
-
- for (i = 0; i < 8; i++)
- {
- i2c_write_bit(data >> 7);
- data <<= 1;
- }
-
- return i2c_read_bit() == 0;
-}
-
-static void i2c_read (
- u8 * data)
-{
- unsigned int i;
- u8 val = 0;
-
- for (i = 0; i < 8; i++)
- {
- val <<= 1;
- val |= i2c_read_bit();
- }
-
- *data = val;
- i2c_write_bit(1); /* NoAck */
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <linux/mtd/doc2000.h>
-#include <watchdog.h>
-#include <pci.h>
-#include <netdev.h>
-#include <serial.h>
-
-#include "hardware.h"
-#include "pcippc2.h"
-#include "sconsole.h"
-#include "fpga_serial.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_WATCHDOG)
-
-static int pcippc2_wdt_init_done = 0;
-
-void pcippc2_wdt_init (void);
-
-#endif
-
- /* Check board identity
- */
-int checkboard (void)
-{
-#ifdef CONFIG_PCIPPC2
- puts ("Board: Gespac PCIPPC-2\n");
-#else
- puts ("Board: Gespac PCIPPC-6\n");
-#endif
- return 0;
-}
-
- /* RAM size is stored in CPC0_RGBAN1
- */
-u32 pcippc2_sdram_size (void)
-{
- return in32 (REG (CPC0, RGBAN1));
-}
-
-phys_size_t initdram (int board_type)
-{
- return cpc710_ram_init ();
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- out32 (REG (CPC0, SPOR), 0);
- iobarrier_rw ();
- while (1);
- /* notreached */
- return (-1);
-}
-
-int board_early_init_f (void)
-{
- out32 (REG (CPC0, RSTR), 0xC0000000);
- iobarrier_rw ();
-
- out32 (REG (CPC0, RSTR), 0xF0000000);
- iobarrier_rw ();
-
- out32 (REG (CPC0, UCTL), 0x00F80000);
-
- out32 (REG (CPC0, SIOC0), 0x30000000);
-
- out32 (REG (CPC0, ABCNTL), 0x00000000);
-
- out32 (REG (CPC0, SESR), 0x00000000);
- out32 (REG (CPC0, SEAR), 0x00000000);
-
- /* Detect IBM Avignon CPC710 Revision */
- if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
- out32 (REG (CPC0, PGCHP), 0xA0000040);
- else
- out32 (REG (CPC0, PGCHP), 0x80800040);
-
-
- out32 (REG (CPC0, ATAS), 0x709C2508);
-
- iobarrier_rw ();
-
- return 0;
-}
-
-void after_reloc (ulong dest_addr)
-{
- /* Jump to the main U-Boot board init code
- */
- board_init_r ((gd_t *)gd, dest_addr);
-}
-
-int misc_init_r (void)
-{
- pcippc2_fpga_init ();
-
- pcippc2_cpci3264_init ();
-
-#if defined(CONFIG_WATCHDOG)
- pcippc2_wdt_init ();
-#endif
-
- fpga_serial_init (sconsole_get_baudrate ());
-
- sconsole_putc = fpga_serial_putc;
- sconsole_puts = default_serial_puts;
- sconsole_getc = fpga_serial_getc;
- sconsole_tstc = fpga_serial_tstc;
- sconsole_setbrg = fpga_serial_setbrg;
-
- sconsole_flush ();
- return (0);
-}
-
-void pci_init_board (void)
-{
- cpc710_pci_init ();
-
- /* FPGA requires no retry timeouts to be enabled
- */
- cpc710_pci_enable_timeout ();
-}
-
-#ifdef CONFIG_CMD_DOC
-void doc_init (void)
-{
- doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
-}
-#endif
-
-void pcippc2_cpci3264_init (void)
-{
- pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
-
- if (bdf == -1)
- {
- puts("Unable to find FPGA !\n");
- hang();
- }
-
- if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
- /* 32-bits Compact PCI bus - LSB bit */
- {
- iobarrier_rw();
- out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */
- iobarrier_rw();
- }
-}
-
-#if defined(CONFIG_WATCHDOG)
-
-void pcippc2_wdt_init (void)
-{
- out16r (FPGA (WDT, PROG), 0xffff);
- out8 (FPGA (WDT, CTRL), 0x1);
-
- pcippc2_wdt_init_done = 1;
-}
-
-void pcippc2_wdt_done (void)
-{
- out8 (FPGA (WDT, CTRL), 0x0);
-
- pcippc2_wdt_init_done = 0;
-}
-
-void pcippc2_wdt_reset (void)
-{
- if (pcippc2_wdt_init_done == 1)
- out8 (FPGA (WDT, REFRESH), 0x56);
-}
-
-void watchdog_reset (void)
-{
- int re_enable = disable_interrupts ();
-
- pcippc2_wdt_reset ();
- if (re_enable)
- enable_interrupts ();
-}
-
-#if defined(CONFIG_CMD_BSP)
-int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- switch (argc) {
- case 1:
- printf ("Watchdog timer status is %s\n",
- pcippc2_wdt_init_done == 1 ? "on" : "off");
-
- return 0;
- case 2:
- if (!strcmp(argv[1],"on")) {
- pcippc2_wdt_init();
- printf("Watchdog timer now is on\n");
-
- return 0;
-
- } else if (!strcmp(argv[1],"off")) {
- pcippc2_wdt_done();
- printf("Watchdog timer now is off\n");
-
- return 0;
-
- } else
- break;
- default:
- break;
- }
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- wd, 2, 1, do_wd,
- "check and set watchdog",
- "on - switch watchDog on\n"
- "wd off - switch watchdog off\n"
- "wd - print current status"
-);
-
-#endif
-#endif /* CONFIG_WATCHDOG */
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _PCIPPC2_H_
-#define _PCIPPC2_H_
-
-#include <config.h>
-#include <common.h>
-
-#include "hardware.h"
-
-#define FPGA(r, p) (pcippc2_fpga0_phys + HW_FPGA0_##r##_##p)
-#define UART(r) (pcippc2_fpga0_phys + HW_FPGA0_UART1 + NS16550_##r * 4)
-#define RTC(r) (pcippc2_fpga1_phys + HW_FPGA1_RTC + r)
-
-extern u32 pcippc2_fpga0_phys;
-extern u32 pcippc2_fpga1_phys;
-
-extern u32 pcippc2_sdram_size (void);
-
-extern void pcippc2_fpga_init (void);
-
-extern void pcippc2_cpci3264_init (void);
-
-extern void cpc710_pci_init (void);
-extern void cpc710_pci_enable_timeout (void);
-
-extern unsigned long
- cpc710_ram_init (void);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-
-#include "pci.h"
-
-#include "hardware.h"
-#include "pcippc2.h"
-
-u32 pcippc2_fpga0_phys;
-u32 pcippc2_fpga1_phys;
-
-void pcippc2_fpga_init (void)
-{
- pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
- unsigned int addr;
- u16 cmd;
-
- if (bdf == -1)
- {
- puts("Unable to find FPGA !\n");
- hang();
- }
-
- pci_read_config_word(bdf, PCI_COMMAND, &cmd);
- if ((cmd & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) != (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))
- {
- puts("FPGA is not configured !\n");
- hang();
- }
-
- pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &addr);
- if (addr & 0x1)
- {
- /* IO space
- */
- pcippc2_fpga0_phys = pci_io_to_phys(bdf, addr & 0xfffffffc);
- }
- else
- {
- /* Memory space
- */
- pcippc2_fpga0_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0);
- }
-
- pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
- if (addr & 0x1)
- {
- /* IO space
- */
- pcippc2_fpga1_phys = pci_io_to_phys(bdf, addr & 0xfffffffc);
- }
- else
- {
- /* Memory space
- */
- pcippc2_fpga1_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0);
- }
-
- /* Interrupts are not used
- */
- out32(FPGA(INT, INTR_MASK), 0xffffffff);
- iobarrier_rw();
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _PCIPPC2_FPGA_H_
-#define _PCIPPC2_FPGA_H_
-
-#define FPGA_VENDOR_ID 0x1310
-#define FPGA_DEVICE_ID 0x000d
-
-#define HW_FPGA0_INT 0x0000
-#define HW_FPGA0_BOARD 0x0060
-#define HW_FPGA0_UART1 0x0080
-#define HW_FPGA0_UART2 0x0100
-#define HW_FPGA0_RTC 0x2000
-#define HW_FPGA0_DOC 0x4000
-#define HW_FPGA1_RTC 0x0000
-#define HW_FPGA1_DOC 0x4000
-
-#define HW_FPGA0_INT_INTR_MASK 0x30
-#define HW_FPGA0_INT_INTR_STATUS 0x34
-#define HW_FPGA0_INT_INTR_EOI 0x40
-#define HW_FPGA0_INT_SERIAL_CONFIG 0x5c
-
-#define HW_FPGA0_WDT_CTRL 0x44
-#define HW_FPGA0_WDT_PROG 0x48
-#define HW_FPGA0_WDT_VAL 0x4c
-#define HW_FPGA0_WDT_REFRESH 0x50
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "sconsole.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void (*sconsole_putc) (char) = 0;
-void (*sconsole_puts) (const char *) = 0;
-int (*sconsole_getc) (void) = 0;
-int (*sconsole_tstc) (void) = 0;
-void (*sconsole_setbrg) (void) = 0;
-
-static int sconsole_serial_init(void)
-{
- sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
- sb->pos = 0;
- sb->size = 0;
- sb->baud = gd->baudrate;
- sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
-
- return (0);
-}
-
-static void sconsole_serial_putc(char c)
-{
- if (sconsole_putc) {
- (*sconsole_putc) (c);
- } else {
- sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
- if (c) {
- sb->data[sb->pos++] = c;
- if (sb->pos == sb->max_size) {
- sb->pos = 0;
- }
- if (sb->size < sb->max_size) {
- sb->size++;
- }
- }
- }
-}
-
-static void sconsole_serial_puts(const char *s)
-{
- if (sconsole_puts) {
- (*sconsole_puts) (s);
- } else {
- sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
- while (*s) {
- sb->data[sb->pos++] = *s++;
- if (sb->pos == sb->max_size) {
- sb->pos = 0;
- }
- if (sb->size < sb->max_size) {
- sb->size++;
- }
- }
- }
-}
-
-static int sconsole_serial_getc(void)
-{
- if (sconsole_getc) {
- return (*sconsole_getc) ();
- } else {
- return 0;
- }
-}
-
-static int sconsole_serial_tstc(void)
-{
- if (sconsole_tstc) {
- return (*sconsole_tstc) ();
- } else {
- return 0;
- }
-}
-
-static void sconsole_serial_setbrg(void)
-{
- if (sconsole_setbrg) {
- (*sconsole_setbrg) ();
- } else {
- sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
- sb->baud = gd->baudrate;
- }
-}
-
-static struct serial_device sconsole_serial_drv = {
- .name = "sconsole_serial",
- .start = sconsole_serial_init,
- .stop = NULL,
- .setbrg = sconsole_serial_setbrg,
- .putc = sconsole_serial_putc,
- .puts = sconsole_serial_puts,
- .getc = sconsole_serial_getc,
- .tstc = sconsole_serial_tstc,
-};
-
-void sconsole_serial_initialize(void)
-{
- serial_register(&sconsole_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &sconsole_serial_drv;
-}
-
-int sconsole_get_baudrate (void)
-{
- sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
- return sb->baud;
-}
-
-void sconsole_flush (void)
-{
- if (sconsole_putc) {
- sconsole_buffer_t *sb = SCONSOLE_BUFFER;
- unsigned int end = sb->pos < sb->size
- ? sb->pos + sb->max_size - sb->size
- : sb->pos - sb->size;
-
- while (sb->size) {
- (*sconsole_putc) (sb->data[end++]);
- if (end == sb->max_size) {
- end = 0;
- }
- sb->size--;
- }
- }
-}
extern flash_info_t flash_info[];
ulong flash_get_size (phys_addr_t base, int banknum);
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
- CLOCK_SCCR1_LPC_EN | \
- CLOCK_SCCR1_NFC_EN | \
- CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
- CLOCK_SCCR1_PSCFIFO_EN | \
- CLOCK_SCCR1_DDR_EN | \
- CLOCK_SCCR1_FEC_EN | \
- CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
- CLOCK_SCCR2_SPDIF_EN | \
- CLOCK_SCCR2_DIU_EN | \
- CLOCK_SCCR2_I2C_EN)
-
-int board_early_init_f(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
- /*
- * Initialize Local Window for FLASH-Bank1 access (CS1)
- */
- out_be32(&im->sysconf.lpcs1aw,
- CSAW_START(CONFIG_SYS_FLASH1_BASE) |
- CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
- );
- out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
-
- /*
- * Local Window for MRAM access (CS2)
- */
- out_be32(&im->sysconf.lpcs2aw,
- CSAW_START(CONFIG_SYS_MRAM_BASE) |
- CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
- );
- out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-
- sync_law(&im->sysconf.lpcs2aw);
-
- /*
- * Configure Flash Speed
- */
- out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
- out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
- /*
- * Enable clocks
- */
- out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
- out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
- setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
- return 0;
-}
-
sdram_conf_t mddrc_config[] = {
{
(512 << 20), /* 512 MB RAM configuration */
int rc, i = 0;
ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
. = ALIGN(128 * 1024);
.ppcenv :
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
}
PROVIDE (bss_end = .);
- PROVIDE (__bss_end__ = .);
+ PROVIDE (__bss_end = .);
}
}
PROVIDE (bss_end = .);
- PROVIDE (__bss_end__ = .);
+ PROVIDE (__bss_end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
__bss_start = .;
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
} >.sram
}
__bss_start = .;
*(.bss)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
/DISCARD/ : { *(.dynstr*) }
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
*(COMMON)
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
PROVIDE (end = .);
}
__bss_start = .;
*(.bss)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
/DISCARD/ : { *(.bss*) }
woodburn_init();
/* Clear the BSS. */
- memset(__bss_start, 0, __bss_end__ - __bss_start);
+ memset(__bss_start, 0, __bss_end - __bss_start);
/* Set global data pointer. */
gd = &gdata;
EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
EVB64260_750CX powerpc 74xx_7xx evb64260 - - EVB64260
P3G4 powerpc 74xx_7xx evb64260
-PCIPPC2 powerpc 74xx_7xx pcippc2
-PCIPPC6 powerpc 74xx_7xx pcippc2
ppmc7xx powerpc 74xx_7xx
ZUMA powerpc 74xx_7xx evb64260
ELPPC powerpc 74xx_7xx elppc eltec
mecp5123 powerpc mpc512x - esd
mpc5121ads powerpc mpc512x mpc5121ads freescale
mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2
+ac14xx powerpc mpc512x ac14xx ifm
cmi_mpc5xx powerpc mpc5xx cmi
PATI powerpc mpc5xx pati mpl
a3m071 powerpc mpc5xxx a3m071
a4m072 powerpc mpc5xxx a4m072
+a4m2k powerpc mpc5xxx a3m071 - - a3m071:A4M2K
BC3450 powerpc mpc5xxx bc3450
canmb powerpc mpc5xxx
cm5200 powerpc mpc5xxx
COBJS-y += xyzModem.o
COBJS-y += cmd_disk.o
+# boards
+COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
+COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+
# core command
COBJS-y += cmd_boot.o
COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <version.h>
+#include <environment.h>
+#include <fdtdec.h>
+#if defined(CONFIG_CMD_IDE)
+#include <ide.h>
+#endif
+#include <i2c.h>
+#include <initcall.h>
+#include <logbuff.h>
+
+/* TODO: Can we move these into arch/ headers? */
+#ifdef CONFIG_8xx
+#include <mpc8xx.h>
+#endif
+#ifdef CONFIG_5xx
+#include <mpc5xx.h>
+#endif
+#ifdef CONFIG_MPC5xxx
+#include <mpc5xxx.h>
+#endif
+
+#include <post.h>
+#include <spi.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#ifdef CONFIG_MP
+#include <asm/mp.h>
+#endif
+#include <asm/sections.h>
+#ifdef CONFIG_X86
+#include <asm/init_helpers.h>
+#include <asm/relocate.h>
+#endif
+#include <linux/compiler.h>
+
+/*
+ * Pointer to initial global data area
+ *
+ * Here we initialize it if needed.
+ */
+#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
+#undef XTRN_DECLARE_GLOBAL_DATA_PTR
+#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
+DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
+#else
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+/*
+ * sjg: IMO this code should be
+ * refactored to a single function, something like:
+ *
+ * void led_set_state(enum led_colour_t colour, int on);
+ */
+/************************************************************************
+ * Coloured LED functionality
+ ************************************************************************
+ * May be supplied by boards if desired
+ */
+inline void __coloured_LED_init(void) {}
+void coloured_LED_init(void)
+ __attribute__((weak, alias("__coloured_LED_init")));
+inline void __red_led_on(void) {}
+void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
+inline void __red_led_off(void) {}
+void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
+inline void __green_led_on(void) {}
+void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
+inline void __green_led_off(void) {}
+void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
+inline void __yellow_led_on(void) {}
+void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
+inline void __yellow_led_off(void) {}
+void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
+inline void __blue_led_on(void) {}
+void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
+inline void __blue_led_off(void) {}
+void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
+
+/*
+ * Why is gd allocated a register? Prior to reloc it might be better to
+ * just pass it around to each function in this file?
+ *
+ * After reloc one could argue that it is hardly used and doesn't need
+ * to be in a register. Or if it is it should perhaps hold pointers to all
+ * global data for all modules, so that post-reloc we can avoid the massive
+ * literal pool we get on ARM. Or perhaps just encourage each module to use
+ * a structure...
+ */
+
+/*
+ * Could the CONFIG_SPL_BUILD infection become a flag in gd?
+ */
+
+#if defined(CONFIG_WATCHDOG)
+static int init_func_watchdog_init(void)
+{
+ puts(" Watchdog enabled\n");
+ WATCHDOG_RESET();
+
+ return 0;
+}
+
+int init_func_watchdog_reset(void)
+{
+ WATCHDOG_RESET();
+
+ return 0;
+}
+#endif /* CONFIG_WATCHDOG */
+
+void __board_add_ram_info(int use_default)
+{
+ /* please define platform specific board_add_ram_info() */
+}
+
+void board_add_ram_info(int)
+ __attribute__ ((weak, alias("__board_add_ram_info")));
+
+static int init_baud_rate(void)
+{
+ gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+ return 0;
+}
+
+static int display_text_info(void)
+{
+ ulong bss_start, bss_end;
+
+#ifdef CONFIG_SYS_SYM_OFFSETS
+ bss_start = _bss_start_ofs + _TEXT_BASE;
+ bss_end = _bss_end_ofs + _TEXT_BASE;
+#else
+ bss_start = (ulong)&__bss_start;
+ bss_end = (ulong)&__bss_end;
+#endif
+ debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
+ CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
+
+#ifdef CONFIG_MODEM_SUPPORT
+ debug("Modem Support enabled\n");
+#endif
+#ifdef CONFIG_USE_IRQ
+ debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
+ debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
+#endif
+
+ return 0;
+}
+
+static int announce_dram_init(void)
+{
+ puts("DRAM: ");
+ return 0;
+}
+
+#ifdef CONFIG_PPC
+static int init_func_ram(void)
+{
+#ifdef CONFIG_BOARD_TYPES
+ int board_type = gd->board_type;
+#else
+ int board_type = 0; /* use dummy arg */
+#endif
+
+ gd->ram_size = initdram(board_type);
+
+ if (gd->ram_size > 0)
+ return 0;
+
+ puts("*** failed ***\n");
+ return 1;
+}
+#endif
+
+static int show_dram_config(void)
+{
+ ulong size;
+
+#ifdef CONFIG_NR_DRAM_BANKS
+ int i;
+
+ debug("\nRAM Configuration:\n");
+ for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ size += gd->bd->bi_dram[i].size;
+ debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+#ifdef DEBUG
+ print_size(gd->bd->bi_dram[i].size, "\n");
+#endif
+ }
+ debug("\nDRAM: ");
+#else
+ size = gd->ram_size;
+#endif
+
+ print_size(size, "");
+ board_add_ram_info(0);
+ putc('\n');
+
+ return 0;
+}
+
+ulong get_effective_memsize(void)
+{
+#ifndef CONFIG_VERY_BIG_RAM
+ return gd->ram_size;
+#else
+ /* limit stack to what we can reasonable map */
+ return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+ CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+#endif
+}
+
+void __dram_init_banksize(void)
+{
+#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = get_effective_memsize();
+#endif
+}
+
+void dram_init_banksize(void)
+ __attribute__((weak, alias("__dram_init_banksize")));
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+static int init_func_i2c(void)
+{
+ puts("I2C: ");
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ puts("ready\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_HARD_SPI)
+static int init_func_spi(void)
+{
+ puts("SPI: ");
+ spi_init();
+ puts("ready\n");
+ return 0;
+}
+#endif
+
+__maybe_unused
+static int zero_global_data(void)
+{
+ memset((void *)gd, '\0', sizeof(gd_t));
+
+ return 0;
+}
+
+static int setup_mon_len(void)
+{
+#ifdef CONFIG_SYS_SYM_OFFSETS
+ gd->mon_len = _bss_end_ofs;
+#else
+ /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
+ gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+#endif
+ return 0;
+}
+
+__weak int arch_cpu_init(void)
+{
+ return 0;
+}
+
+static int setup_fdt(void)
+{
+#ifdef CONFIG_OF_EMBED
+ /* Get a pointer to the FDT */
+ gd->fdt_blob = _binary_dt_dtb_start;
+#elif defined CONFIG_OF_SEPARATE
+ /* FDT is at end of image */
+# ifdef CONFIG_SYS_SYM_OFFSETS
+ gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE);
+# else
+ gd->fdt_blob = (ulong *)&_end;
+# endif
+#endif
+ /* Allow the early environment to override the fdt address */
+ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
+ (uintptr_t)gd->fdt_blob);
+ return 0;
+}
+
+/* Get the top of usable RAM */
+__weak ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top;
+}
+
+static int setup_dest_addr(void)
+{
+ debug("Monitor len: %08lX\n", gd->mon_len);
+ /*
+ * Ram is setup, size stored in gd !!
+ */
+ debug("Ram size: %08lX\n", (ulong)gd->ram_size);
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ /*
+ * Subtract specified amount of memory to hide so that it won't
+ * get "touched" at all by U-Boot. By fixing up gd->ram_size
+ * the Linux kernel should now get passed the now "corrected"
+ * memory size and won't touch it either. This should work
+ * for arch/ppc and arch/powerpc. Only Linux board ports in
+ * arch/powerpc with bootwrapper support, that recalculate the
+ * memory size from the SDRAM controller setup will have to
+ * get fixed.
+ */
+ gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#ifdef CONFIG_SYS_SDRAM_BASE
+ gd->ram_top = CONFIG_SYS_SDRAM_BASE;
+#endif
+ gd->ram_top += get_effective_memsize();
+ gd->ram_top = board_get_usable_ram_top(gd->mon_len);
+ gd->dest_addr = gd->ram_top;
+ debug("Ram top: %08lX\n", (ulong)gd->ram_top);
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+ /*
+ * We need to make sure the location we intend to put secondary core
+ * boot code is reserved and not used by any part of u-boot
+ */
+ if (gd->dest_addr > determine_mp_bootpg(NULL)) {
+ gd->dest_addr = determine_mp_bootpg(NULL);
+ debug("Reserving MP boot page to %08lx\n", gd->dest_addr);
+ }
+#endif
+ gd->dest_addr_sp = gd->dest_addr;
+ return 0;
+}
+
+#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
+static int reserve_logbuffer(void)
+{
+ /* reserve kernel log buffer */
+ gd->dest_addr -= LOGBUFF_RESERVE;
+ debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
+ gd->dest_addr);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PRAM
+/* reserve protected RAM */
+static int reserve_pram(void)
+{
+ ulong reg;
+
+ reg = getenv_ulong("pram", 10, CONFIG_PRAM);
+ gd->dest_addr -= (reg << 10); /* size is in kB */
+ debug("Reserving %ldk for protected RAM at %08lx\n", reg,
+ gd->dest_addr);
+ return 0;
+}
+#endif /* CONFIG_PRAM */
+
+/* Round memory pointer down to next 4 kB limit */
+static int reserve_round_4k(void)
+{
+ gd->dest_addr &= ~(4096 - 1);
+ return 0;
+}
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
+ defined(CONFIG_ARM)
+static int reserve_mmu(void)
+{
+ /* reserve TLB table */
+ gd->arch.tlb_size = 4096 * 4;
+ gd->dest_addr -= gd->arch.tlb_size;
+
+ /* round down to next 64 kB limit */
+ gd->dest_addr &= ~(0x10000 - 1);
+
+ gd->arch.tlb_addr = gd->dest_addr;
+ debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_LCD
+static int reserve_lcd(void)
+{
+#ifdef CONFIG_FB_ADDR
+ gd->fb_base = CONFIG_FB_ADDR;
+#else
+ /* reserve memory for LCD display (always full pages) */
+ gd->dest_addr = lcd_setmem(gd->dest_addr);
+ gd->fb_base = gd->dest_addr;
+#endif /* CONFIG_FB_ADDR */
+ return 0;
+}
+#endif /* CONFIG_LCD */
+
+#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \
+ && !defined(CONFIG_ARM) && !defined(CONFIG_X86)
+static int reserve_video(void)
+{
+ /* reserve memory for video display (always full pages) */
+ gd->dest_addr = video_setmem(gd->dest_addr);
+ gd->fb_base = gd->dest_addr;
+
+ return 0;
+}
+#endif
+
+static int reserve_uboot(void)
+{
+ /*
+ * reserve memory for U-Boot code, data & bss
+ * round down to next 4 kB limit
+ */
+ gd->dest_addr -= gd->mon_len;
+ gd->dest_addr &= ~(4096 - 1);
+#ifdef CONFIG_E500
+ /* round down to next 64 kB limit so that IVPR stays aligned */
+ gd->dest_addr &= ~(65536 - 1);
+#endif
+
+ debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
+ gd->dest_addr);
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+/* reserve memory for malloc() area */
+static int reserve_malloc(void)
+{
+ gd->dest_addr_sp = gd->dest_addr - TOTAL_MALLOC_LEN;
+ debug("Reserving %dk for malloc() at: %08lx\n",
+ TOTAL_MALLOC_LEN >> 10, gd->dest_addr_sp);
+ return 0;
+}
+
+/* (permanently) allocate a Board Info struct */
+static int reserve_board(void)
+{
+ gd->dest_addr_sp -= sizeof(bd_t);
+ gd->bd = (bd_t *)gd->dest_addr_sp;
+ memset(gd->bd, '\0', sizeof(bd_t));
+ debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+ sizeof(bd_t), gd->dest_addr_sp);
+ return 0;
+}
+#endif
+
+static int setup_machine(void)
+{
+#ifdef CONFIG_MACH_TYPE
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+ return 0;
+}
+
+static int reserve_global_data(void)
+{
+ gd->dest_addr_sp -= sizeof(gd_t);
+ gd->new_gd = (gd_t *)gd->dest_addr_sp;
+ debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+ sizeof(gd_t), gd->dest_addr_sp);
+ return 0;
+}
+
+static int reserve_fdt(void)
+{
+ /*
+ * If the device tree is sitting immediate above our image then we
+ * must relocate it. If it is embedded in the data section, then it
+ * will be relocated with other data.
+ */
+ if (gd->fdt_blob) {
+ gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+ gd->dest_addr_sp -= gd->fdt_size;
+ gd->new_fdt = (void *)gd->dest_addr_sp;
+ debug("Reserving %lu Bytes for FDT at: %p\n",
+ gd->fdt_size, gd->new_fdt);
+ }
+
+ return 0;
+}
+
+static int reserve_stacks(void)
+{
+#ifdef CONFIG_SPL_BUILD
+# ifdef CONFIG_ARM
+ gd->dest_addr_sp -= 128; /* leave 32 words for abort-stack */
+ gd->irq_sp = gd->dest_addr_sp;
+# endif
+#else
+# ifdef CONFIG_PPC
+ ulong *s;
+# endif
+
+ /* setup stack pointer for exceptions */
+ gd->dest_addr_sp -= 16;
+ gd->dest_addr_sp &= ~0xf;
+ gd->irq_sp = gd->dest_addr_sp;
+
+ /*
+ * Handle architecture-specific things here
+ * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack()
+ * to handle this and put in arch/xxx/lib/stack.c
+ */
+# ifdef CONFIG_ARM
+# ifdef CONFIG_USE_IRQ
+ gd->dest_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+ debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+ CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->dest_addr_sp);
+
+ /* 8-byte alignment for ARM ABI compliance */
+ gd->dest_addr_sp &= ~0x07;
+# endif
+ /* leave 3 words for abort-stack, plus 1 for alignment */
+ gd->dest_addr_sp -= 16;
+# elif defined(CONFIG_PPC)
+ /* Clear initial stack frame */
+ s = (ulong *) gd->dest_addr_sp;
+ *s = 0; /* Terminate back chain */
+ *++s = 0; /* NULL return address */
+# endif /* Architecture specific code */
+
+ return 0;
+#endif
+}
+
+static int display_new_sp(void)
+{
+ debug("New Stack Pointer is: %08lx\n", gd->dest_addr_sp);
+
+ return 0;
+}
+
+#ifdef CONFIG_PPC
+static int setup_board_part1(void)
+{
+ bd_t *bd = gd->bd;
+
+ /*
+ * Save local variables to board info struct
+ */
+
+ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
+ bd->bi_memsize = gd->ram_size; /* size in bytes */
+
+#ifdef CONFIG_SYS_SRAM_BASE
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+ bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
+#endif
+
+#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+ defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+ bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
+#endif
+#if defined(CONFIG_MPC5xxx)
+ bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+#endif
+#if defined(CONFIG_MPC83xx)
+ bd->bi_immrbar = CONFIG_SYS_IMMR;
+#endif
+#if defined(CONFIG_MPC8220)
+ bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+ bd->bi_inpfreq = gd->arch.inp_clk;
+ bd->bi_pcifreq = gd->pci_clk;
+ bd->bi_vcofreq = gd->arch.vco_clk;
+ bd->bi_pevfreq = gd->arch.pev_clk;
+ bd->bi_flbfreq = gd->arch.flb_clk;
+
+ /* store bootparam to sram (backward compatible), here? */
+ {
+ u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE;
+
+ *sram++ = gd->ram_size;
+ *sram++ = gd->bus_clk;
+ *sram++ = gd->arch.inp_clk;
+ *sram++ = gd->cpu_clk;
+ *sram++ = gd->arch.vco_clk;
+ *sram++ = gd->arch.flb_clk;
+ *sram++ = 0xb8c3ba11; /* boot signature */
+ }
+#endif
+
+ return 0;
+}
+
+static int setup_board_part2(void)
+{
+ bd_t *bd = gd->bd;
+
+ bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
+ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
+#if defined(CONFIG_CPM2)
+ bd->bi_cpmfreq = gd->arch.cpm_clk;
+ bd->bi_brgfreq = gd->arch.brg_clk;
+ bd->bi_sccfreq = gd->arch.scc_clk;
+ bd->bi_vco = gd->arch.vco_out;
+#endif /* CONFIG_CPM2 */
+#if defined(CONFIG_MPC512X)
+ bd->bi_ipsfreq = gd->arch.ips_clk;
+#endif /* CONFIG_MPC512X */
+#if defined(CONFIG_MPC5xxx)
+ bd->bi_ipbfreq = gd->arch.ipb_clk;
+ bd->bi_pcifreq = gd->pci_clk;
+#endif /* CONFIG_MPC5xxx */
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_EXTBDINFO
+static int setup_board_extra(void)
+{
+ bd_t *bd = gd->bd;
+
+ strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
+ strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
+ sizeof(bd->bi_r_version));
+
+ bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
+ bd->bi_plb_busfreq = gd->bus_clk;
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ bd->bi_pci_busfreq = get_PCI_freq();
+ bd->bi_opbfreq = get_OPB_freq();
+#elif defined(CONFIG_XILINX_405)
+ bd->bi_pci_busfreq = get_PCI_freq();
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_POST
+static int init_post(void)
+{
+ post_bootmode_init();
+ post_run(NULL, POST_ROM | post_bootmode_get(0));
+
+ return 0;
+}
+#endif
+
+static int setup_baud_rate(void)
+{
+ /* Ick, can we get rid of this line? */
+ gd->bd->bi_baudrate = gd->baudrate;
+
+ return 0;
+}
+
+static int setup_dram_config(void)
+{
+ /* Ram is board specific, so move it to board code ... */
+ dram_init_banksize();
+
+ return 0;
+}
+
+static int reloc_fdt(void)
+{
+ if (gd->new_fdt) {
+ memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
+ gd->fdt_blob = gd->new_fdt;
+ }
+
+ return 0;
+}
+
+static int setup_reloc(void)
+{
+ gd->relocaddr = gd->dest_addr;
+ gd->start_addr_sp = gd->dest_addr_sp;
+ gd->reloc_off = gd->dest_addr - CONFIG_SYS_TEXT_BASE;
+ memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
+
+ debug("Relocation Offset is: %08lx\n", gd->reloc_off);
+ debug("Relocating to %08lx, new gd at %p, sp at %08lx\n",
+ gd->dest_addr, gd->new_gd, gd->dest_addr_sp);
+
+ return 0;
+}
+
+/* ARM calls relocate_code from its crt0.S */
+#if !defined(CONFIG_ARM)
+
+static int jump_to_copy(void)
+{
+ /*
+ * x86 is special, but in a nice way. It uses a trampoline which
+ * enables the dcache if possible.
+ *
+ * For now, other archs use relocate_code(), which is implemented
+ * similarly for all archs. When we do generic relocation, hopefully
+ * we can make all archs enable the dcache prior to relocation.
+ */
+#ifdef CONFIG_X86
+ /*
+ * SDRAM and console are now initialised. The final stack can now
+ * be setup in SDRAM. Code execution will continue in Flash, but
+ * with the stack in SDRAM and Global Data in temporary memory
+ * (CPU cache)
+ */
+ board_init_f_r_trampoline(gd->start_addr_sp);
+#else
+ relocate_code(gd->dest_addr_sp, gd->new_gd, gd->dest_addr);
+#endif
+
+ return 0;
+}
+#endif
+
+/* Record the board_init_f() bootstage (after arch_cpu_init()) */
+static int mark_bootstage(void)
+{
+ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
+
+ return 0;
+}
+
+static init_fnc_t init_sequence_f[] = {
+#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
+ !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
+ !defined(CONFIG_MPC86xx)
+ zero_global_data,
+#endif
+ setup_fdt,
+ setup_mon_len,
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ /* TODO: can this go into arch_cpu_init()? */
+ probecpu,
+#endif
+ arch_cpu_init, /* basic arch cpu dependent setup */
+#ifdef CONFIG_X86
+ cpu_init_f, /* TODO(sjg@chromium.org): remove */
+# ifdef CONFIG_OF_CONTROL
+ find_fdt, /* TODO(sjg@chromium.org): remove */
+# endif
+#endif
+ mark_bootstage,
+#ifdef CONFIG_OF_CONTROL
+ fdtdec_check_fdt,
+#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+ board_early_init_f,
+#endif
+ /* TODO: can any of this go into arch_cpu_init()? */
+#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT)
+ get_clocks, /* get CPU and bus clocks (etc.) */
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
+ adjust_sdram_tbs_8xx,
+#endif
+ /* TODO: can we rename this to timer_init()? */
+ init_timebase,
+#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+ board_early_init_f,
+#endif
+#ifdef CONFIG_ARM
+ timer_init, /* initialize timer */
+#endif
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+ board_postclk_init,
+#endif
+#ifdef CONFIG_FSL_ESDHC
+ get_clocks,
+#endif
+#ifdef CONFIG_SYS_ALLOC_DPRAM
+#if !defined(CONFIG_CPM2)
+ dpram_init,
+#endif
+#endif
+#if defined(CONFIG_BOARD_POSTCLK_INIT)
+ board_postclk_init,
+#endif
+ env_init, /* initialize environment */
+#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
+ /* get CPU and bus clocks according to the environment variable */
+ get_clocks_866,
+ /* adjust sdram refresh rate according to the new clock */
+ sdram_adjust_866,
+ init_timebase,
+#endif
+ init_baud_rate, /* initialze baudrate settings */
+ serial_init, /* serial communications setup */
+ console_init_f, /* stage 1 init of console */
+#if defined(CONFIG_X86) && defined(CONFIG_OF_CONTROL)
+ prepare_fdt, /* TODO(sjg@chromium.org): remove */
+#endif
+ display_options, /* say that we are here */
+ display_text_info, /* show debugging info if required */
+#if defined(CONFIG_8260)
+ prt_8260_rsr,
+ prt_8260_clks,
+#endif /* CONFIG_8260 */
+#if defined(CONFIG_MPC83xx)
+ prt_83xx_rsr,
+#endif
+#ifdef CONFIG_PPC
+ checkcpu,
+#endif
+#if defined(CONFIG_DISPLAY_CPUINFO)
+ print_cpuinfo, /* display cpu info (and speed) */
+#endif
+#if defined(CONFIG_MPC5xxx)
+ prt_mpc5xxx_clks,
+#endif /* CONFIG_MPC5xxx */
+#if defined(CONFIG_MPC8220)
+ prt_mpc8220_clks,
+#endif
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+ checkboard, /* display board info */
+#endif
+ INIT_FUNC_WATCHDOG_INIT
+#if defined(CONFIG_MISC_INIT_F)
+ misc_init_f,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ init_func_i2c,
+#endif
+#if defined(CONFIG_HARD_SPI)
+ init_func_spi,
+#endif
+#ifdef CONFIG_X86
+ dram_init_f, /* configure available RAM banks */
+ /* x86 would prefer that this happens after relocation */
+ dram_init,
+#endif
+ announce_dram_init,
+ /* TODO: unify all these dram functions? */
+#ifdef CONFIG_ARM
+ dram_init, /* configure available RAM banks */
+#endif
+#ifdef CONFIG_PPC
+ init_func_ram,
+#endif
+#ifdef CONFIG_POST
+ post_init_f,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_SYS_DRAM_TEST)
+ testdram,
+#endif /* CONFIG_SYS_DRAM_TEST */
+ INIT_FUNC_WATCHDOG_RESET
+
+#ifdef CONFIG_POST
+ init_post,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+ /*
+ * Now that we have DRAM mapped and working, we can
+ * relocate the code and continue running from DRAM.
+ *
+ * Reserve memory at end of RAM for (top down in that order):
+ * - area that won't get touched by U-Boot and Linux (optional)
+ * - kernel log buffer
+ * - protected RAM
+ * - LCD framebuffer
+ * - monitor code
+ * - board info struct
+ */
+ setup_dest_addr,
+#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
+ reserve_logbuffer,
+#endif
+#ifdef CONFIG_PRAM
+ reserve_pram,
+#endif
+ reserve_round_4k,
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
+ defined(CONFIG_ARM)
+ reserve_mmu,
+#endif
+#ifdef CONFIG_LCD
+ reserve_lcd,
+#endif
+ /* TODO: Why the dependency on CONFIG_8xx? */
+#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \
+ && !defined(CONFIG_ARM) && !defined(CONFIG_X86)
+ reserve_video,
+#endif
+ reserve_uboot,
+#ifndef CONFIG_SPL_BUILD
+ reserve_malloc,
+ reserve_board,
+#endif
+ setup_machine,
+ reserve_global_data,
+ reserve_fdt,
+ reserve_stacks,
+ setup_dram_config,
+ show_dram_config,
+#ifdef CONFIG_PPC
+ setup_board_part1,
+ INIT_FUNC_WATCHDOG_RESET
+ setup_board_part2,
+#endif
+ setup_baud_rate,
+ display_new_sp,
+#ifdef CONFIG_SYS_EXTBDINFO
+ setup_board_extra,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+ reloc_fdt,
+ setup_reloc,
+#ifndef CONFIG_ARM
+ jump_to_copy,
+#endif
+ NULL,
+};
+
+void board_init_f(ulong boot_flags)
+{
+#ifndef CONFIG_X86
+ gd_t data;
+
+ gd = &data;
+#endif
+
+ gd->flags = boot_flags;
+
+ if (initcall_run_list(init_sequence_f))
+ hang();
+
+#ifndef CONFIG_ARM
+ /* NOTREACHED - jump_to_copy() does not return */
+ hang();
+#endif
+}
+
+#ifdef CONFIG_X86
+/*
+ * For now this code is only used on x86.
+ *
+ * init_sequence_f_r is the list of init functions which are run when
+ * U-Boot is executing from Flash with a semi-limited 'C' environment.
+ * The following limitations must be considered when implementing an
+ * '_f_r' function:
+ * - 'static' variables are read-only
+ * - Global Data (gd->xxx) is read/write
+ *
+ * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
+ * supported). It _should_, if possible, copy global data to RAM and
+ * initialise the CPU caches (to speed up the relocation process)
+ *
+ * NOTE: At present only x86 uses this route, but it is intended that
+ * all archs will move to this when generic relocation is implemented.
+ */
+static init_fnc_t init_sequence_f_r[] = {
+ init_cache_f_r,
+ copy_uboot_to_ram,
+ clear_bss,
+ do_elf_reloc_fixups,
+
+ NULL,
+};
+
+void board_init_f_r(void)
+{
+ if (initcall_run_list(init_sequence_f_r))
+ hang();
+
+ /*
+ * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
+ * Transfer execution from Flash to RAM by calculating the address
+ * of the in-RAM copy of board_init_r() and calling it
+ */
+ (board_init_r + gd->reloc_off)(gd, gd->relocaddr);
+
+ /* NOTREACHED - board_init_r() does not return */
+ hang();
+}
+#endif /* CONFIG_X86 */
+
+void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;);
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/* TODO: can we just include all these headers whether needed or not? */
+#if defined(CONFIG_CMD_BEDBUG)
+#include <bedbug/type.h>
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+#endif
+#include <environment.h>
+#include <fdtdec.h>
+#if defined(CONFIG_CMD_IDE)
+#include <ide.h>
+#endif
+#include <initcall.h>
+#ifdef CONFIG_PS2KBD
+#include <keyboard.h>
+#endif
+#if defined(CONFIG_CMD_KGDB)
+#include <kgdb.h>
+#endif
+#include <logbuff.h>
+#include <malloc.h>
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+#include <mmc.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <scsi.h>
+#include <serial.h>
+#include <spi.h>
+#include <stdio_dev.h>
+#include <watchdog.h>
+#ifdef CONFIG_ADDR_MAP
+#include <asm/mmu.h>
+#endif
+#include <asm/sections.h>
+#ifdef CONFIG_X86
+#include <asm/init_helpers.h>
+#endif
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+int __board_flash_wp_on(void)
+{
+ /*
+ * Most flashes can't be detected when write protection is enabled,
+ * so provide a way to let U-Boot gracefully ignore write protected
+ * devices.
+ */
+ return 0;
+}
+
+int board_flash_wp_on(void)
+ __attribute__ ((weak, alias("__board_flash_wp_on")));
+
+void __cpu_secondary_init_r(void)
+{
+}
+
+void cpu_secondary_init_r(void)
+ __attribute__ ((weak, alias("__cpu_secondary_init_r")));
+
+static int initr_secondary_cpu(void)
+{
+ /*
+ * after non-volatile devices & environment is setup and cpu code have
+ * another round to deal with any initialization that might require
+ * full access to the environment or loading of some image (firmware)
+ * from a non-volatile device
+ */
+ /* TODO: maybe define this for all archs? */
+ cpu_secondary_init_r();
+
+ return 0;
+}
+
+static int initr_reloc(void)
+{
+ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
+
+ return 0;
+}
+
+#ifdef CONFIG_ARM
+/*
+ * Some of these functions are needed purely because the functions they
+ * call return void. If we change them to return 0, these stubs can go away.
+ */
+static int initr_caches(void)
+{
+ /* Enable caches */
+ enable_caches();
+ return 0;
+}
+#endif
+
+__weak int fixup_cpu(void)
+{
+ return 0;
+}
+
+static int initr_reloc_global_data(void)
+{
+#ifdef CONFIG_SYS_SYM_OFFSETS
+ monitor_flash_len = _end_ofs;
+#else
+ monitor_flash_len = (ulong)&__init_end - gd->dest_addr;
+#endif
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ /*
+ * The gd->cpu pointer is set to an address in flash before relocation.
+ * We need to update it to point to the same CPU entry in RAM.
+ * TODO: why not just add gd->reloc_ofs?
+ */
+ gd->arch.cpu += gd->dest_addr - CONFIG_SYS_MONITOR_BASE;
+
+ /*
+ * If we didn't know the cpu mask & # cores, we can save them of
+ * now rather than 'computing' them constantly
+ */
+ fixup_cpu();
+#endif
+#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
+ /*
+ * Some systems need to relocate the env_addr pointer early because the
+ * location it points to will get invalidated before env_relocate is
+ * called. One example is on systems that might use a L2 or L3 cache
+ * in SRAM mode and initialize that cache from SRAM mode back to being
+ * a cache in cpu_init_r.
+ */
+ gd->env_addr += gd->dest_addr - CONFIG_SYS_MONITOR_BASE;
+#endif
+ return 0;
+}
+
+static int initr_serial(void)
+{
+ serial_initialize();
+ return 0;
+}
+
+#ifdef CONFIG_PPC
+static int initr_trap(void)
+{
+ /*
+ * Setup trap handlers
+ */
+ trap_init(gd->dest_addr);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_ADDR_MAP
+static int initr_addr_map(void)
+{
+ init_addr_map();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_LOGBUFFER
+unsigned long logbuffer_base(void)
+{
+ return gd->ram_top - LOGBUFF_LEN;
+}
+
+static int initr_logbuffer(void)
+{
+ logbuff_init_ptrs();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_POST
+static int initr_post_backlog(void)
+{
+ post_output_backlog();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_DELAYED_ICACHE
+static int initr_icache_enable(void)
+{
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
+static int initr_unlock_ram_in_cache(void)
+{
+ unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI
+static int initr_pci(void)
+{
+ pci_init();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_WINBOND_83C553
+static int initr_w83c553f(void)
+{
+ /*
+ * Initialise the ISA bridge
+ */
+ initialise_w83c553f();
+ return 0;
+}
+#endif
+
+static int initr_barrier(void)
+{
+#ifdef CONFIG_PPC
+ /* TODO: Can we not use dmb() macros for this? */
+ asm("sync ; isync");
+#endif
+ return 0;
+}
+
+static int initr_malloc(void)
+{
+ ulong malloc_start;
+
+ /* The malloc area is immediately below the monitor copy in DRAM */
+ malloc_start = gd->dest_addr - TOTAL_MALLOC_LEN;
+ mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+ return 0;
+}
+
+__weak int power_init_board(void)
+{
+ return 0;
+}
+
+static int initr_announce(void)
+{
+ debug("Now running in RAM - U-Boot at: %08lx\n", gd->dest_addr);
+ return 0;
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+static int initr_flash(void)
+{
+ ulong flash_size = 0;
+ bd_t *bd = gd->bd;
+ int ok;
+
+ puts("Flash: ");
+
+ if (board_flash_wp_on()) {
+ printf("Uninitialized - Write Protect On\n");
+ /* Since WP is on, we can't find real size. Set to 0 */
+ ok = 1;
+ } else {
+ flash_size = flash_init();
+ ok = flash_size > 0;
+ }
+ if (!ok) {
+ puts("*** failed ***\n");
+#ifdef CONFIG_PPC
+ /* Why does PPC do this? */
+ hang();
+#endif
+ return -1;
+ }
+ print_size(flash_size, "");
+#ifdef CONFIG_SYS_FLASH_CHECKSUM
+ /*
+ * Compute and print flash CRC if flashchecksum is set to 'y'
+ *
+ * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
+ */
+ if (getenv_yesno("flashchecksum") == 1) {
+ printf(" CRC: %08X", crc32(0,
+ (const unsigned char *) CONFIG_SYS_FLASH_BASE,
+ flash_size));
+ }
+#endif /* CONFIG_SYS_FLASH_CHECKSUM */
+ putc('\n');
+
+ /* update start of FLASH memory */
+#ifdef CONFIG_SYS_FLASH_BASE
+ bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
+ /* size of FLASH memory (final value) */
+ bd->bi_flashsize = flash_size;
+
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+ /* Make a update of the Memctrl. */
+ update_flash_size(flash_size);
+#endif
+
+
+#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
+ /* flash mapped at end of memory map */
+ bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
+#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
+ bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PPC
+static int initr_spi(void)
+{
+ /* PPC does this here */
+#ifdef CONFIG_SPI
+#if !defined(CONFIG_ENV_IS_IN_EEPROM)
+ spi_init_f();
+#endif
+ spi_init_r();
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NAND
+/* go init the NAND */
+int initr_nand(void)
+{
+ puts("NAND: ");
+ nand_init();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+/* go init the NAND */
+int initr_onenand(void)
+{
+ puts("NAND: ");
+ onenand_init();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int initr_mmc(void)
+{
+ puts("MMC: ");
+ mmc_initialize(gd->bd);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+int initr_dataflash(void)
+{
+ AT91F_DataflashInit();
+ dataflash_print_info();
+ return 0;
+}
+#endif
+
+/*
+ * Tell if it's OK to load the environment early in boot.
+ *
+ * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
+ * if this is OK (defaulting to saying it's OK).
+ *
+ * NOTE: Loading the environment early can be a bad idea if security is
+ * important, since no verification is done on the environment.
+ *
+ * @return 0 if environment should not be loaded, !=0 if it is ok to load
+ */
+static int should_load_env(void)
+{
+#ifdef CONFIG_OF_CONTROL
+ return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
+#elif defined CONFIG_DELAY_ENVIRONMENT
+ return 0;
+#else
+ return 1;
+#endif
+}
+
+static int initr_env(void)
+{
+ /* initialize environment */
+ if (should_load_env())
+ env_relocate();
+ else
+ set_default_env(NULL);
+
+ /* Initialize from environment */
+ load_addr = getenv_ulong("loadaddr", 16, load_addr);
+#if defined(CONFIG_SYS_EXTBDINFO)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
+#if defined(CONFIG_I2CFAST)
+ /*
+ * set bi_iic_fast for linux taking environment variable
+ * "i2cfast" into account
+ */
+ {
+ char *s = getenv("i2cfast");
+
+ if (s && ((*s == 'y') || (*s == 'Y'))) {
+ gd->bd->bi_iic_fast[0] = 1;
+ gd->bd->bi_iic_fast[1] = 1;
+ }
+ }
+#endif /* CONFIG_I2CFAST */
+#endif /* CONFIG_405GP, CONFIG_405EP */
+#endif /* CONFIG_SYS_EXTBDINFO */
+ return 0;
+}
+
+#ifdef CONFIG_HERMES
+static int initr_hermes(void)
+{
+ if ((gd->board_type >> 16) == 2)
+ gd->bd->bi_ethspeed = gd->board_type & 0xFFFF;
+ else
+ gd->bd->bi_ethspeed = 0xFFFF;
+ return 0;
+}
+
+static int initr_hermes_start(void)
+{
+ if (gd->bd->bi_ethspeed != 0xFFFF)
+ hermes_start_lxt980((int) gd->bd->bi_ethspeed);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SC3
+/* TODO: with new initcalls, move this into the driver */
+extern void sc3_read_eeprom(void);
+
+static int initr_sc3_read_eeprom(void)
+{
+ sc3_read_eeprom();
+ return 0;
+}
+#endif
+
+static int initr_jumptable(void)
+{
+ jumptable_init();
+ return 0;
+}
+
+#if defined(CONFIG_API)
+static int initr_api(void)
+{
+ /* Initialize API */
+ api_init();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
+static int show_model_r(void)
+{
+ /* Put this here so it appears on the LCD, now it is ready */
+# ifdef CONFIG_OF_CONTROL
+ const char *model;
+
+ model = (char *)fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ printf("Model: %s\n", model ? model : "<unknown>");
+# else
+ checkboard();
+# endif
+}
+#endif
+
+/* enable exceptions */
+#ifdef CONFIG_ARM
+static int initr_enable_interrupts(void)
+{
+ enable_interrupts();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+static int initr_ethaddr(void)
+{
+ bd_t *bd = gd->bd;
+
+ /* kept around for legacy kernels only ... ignore the next section */
+ eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
+#ifdef CONFIG_HAS_ETH1
+ eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
+#endif
+#ifdef CONFIG_HAS_ETH2
+ eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
+#endif
+#ifdef CONFIG_HAS_ETH3
+ eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
+#endif
+#ifdef CONFIG_HAS_ETH4
+ eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
+#endif
+#ifdef CONFIG_HAS_ETH5
+ eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
+#endif
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_KGDB
+static int initr_kgdb(void)
+{
+ puts("KGDB: ");
+ kgdb_init();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+static int initr_status_led(void)
+{
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_SCSI)
+static int initr_scsi(void)
+{
+ /* Not supported properly on ARM yet */
+#ifndef CONFIG_ARM
+ puts("SCSI: ");
+ scsi_init();
+#endif
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+
+#if defined(CONFIG_CMD_DOC)
+static int initr_doc(void)
+{
+ puts("DOC: ");
+ doc_init();
+}
+#endif
+
+#ifdef CONFIG_BITBANGMII
+static int initr_bbmii(void)
+{
+ bb_miiphy_init();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+static int initr_net(void)
+{
+ puts("Net: ");
+ eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+ debug("Reset Ethernet PHY\n");
+ reset_phy();
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_POST
+static int initr_post(void)
+{
+ post_run(NULL, POST_RAM | post_bootmode_get(0));
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
+static int initr_pcmcia(void)
+{
+ puts("PCMCIA:");
+ pcmcia_init();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE)
+static int initr_ide(void)
+{
+#ifdef CONFIG_IDE_8xx_PCCARD
+ puts("PCMCIA:");
+#else
+ puts("IDE: ");
+#endif
+#if defined(CONFIG_START_IDE)
+ if (board_start_ide())
+ ide_init();
+#else
+ ide_init();
+#endif
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
+/*
+ * Export available size of memory for Linux, taking into account the
+ * protected RAM at top of memory
+ */
+int initr_mem(void)
+{
+ ulong pram = 0;
+ char memsz[32];
+
+# ifdef CONFIG_PRAM
+ pram = getenv_ulong("pram", 10, CONFIG_PRAM);
+# endif
+# if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
+ /* Also take the logbuffer into account (pram is in kB) */
+ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
+# endif
+ sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram);
+ setenv("mem", memsz);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_BEDBUG
+static int initr_bedbug(void)
+{
+ bedbug_init();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PS2KBD
+static int initr_kbd(void)
+{
+ puts("PS/2: ");
+ kbd_init();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int initr_modem(void)
+{
+ /* TODO: with new initcalls, move this into the driver */
+ extern int do_mdm_init;
+
+ do_mdm_init = gd->do_mdm_init;
+ return 0;
+}
+#endif
+
+static int run_main_loop(void)
+{
+ /* main_loop() can return to retry autoboot, if so just run it again */
+ for (;;)
+ main_loop();
+ return 0;
+}
+
+/*
+ * Over time we hope to remove these functions with code fragments and
+ * stub funtcions, and instead call the relevant function directly.
+ *
+ * We also hope to remove most of the driver-related init and do it if/when
+ * the driver is later used.
+ *
+ * TODO: perhaps reset the watchdog in the initcall function after each call?
+ */
+init_fnc_t init_sequence_r[] = {
+ initr_reloc,
+ /* TODO: could x86/PPC have this also perhaps? */
+#ifdef CONFIG_ARM
+ initr_caches,
+ board_init, /* Setup chipselects */
+#endif
+ /*
+ * TODO: printing of the clock inforamtion of the board is now
+ * implemented as part of bdinfo command. Currently only support for
+ * davinci SOC's is added. Remove this check once all the board
+ * implement this.
+ */
+#ifdef CONFIG_CLOCKS
+ set_cpu_clk_info, /* Setup clock information */
+#endif
+#ifdef CONFIG_X86
+ init_bd_struct_r,
+#endif
+ initr_reloc_global_data,
+ initr_serial,
+ initr_announce,
+ INIT_FUNC_WATCHDOG_RESET
+#ifdef CONFIG_PPC
+ initr_trap,
+#endif
+#ifdef CONFIG_ADDR_MAP
+ initr_addr_map,
+#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_R)
+ board_early_init_r,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#ifdef CONFIG_LOGBUFFER
+ initr_logbuffer,
+#endif
+#ifdef CONFIG_POST
+ initr_post_backlog,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#ifdef CONFIG_SYS_DELAYED_ICACHE
+ initr_icache_enable,
+#endif
+#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
+ initr_unlock_ram_in_cache,
+#endif
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
+ /*
+ * Do early PCI configuration _before_ the flash gets initialised,
+ * because PCU ressources are crucial for flash access on some boards.
+ */
+ initr_pci,
+#endif
+#ifdef CONFIG_WINBOND_83C553
+ initr_w83c553f,
+#endif
+ initr_barrier,
+ initr_malloc,
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+ arch_early_init_r,
+#endif
+ power_init_board,
+#ifndef CONFIG_SYS_NO_FLASH
+ initr_flash,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_PPC) || defined(CONFIG_X86)
+ /* initialize higher level parts of CPU like time base and timers */
+ cpu_init_r,
+#endif
+#ifdef CONFIG_PPC
+ initr_spi,
+#endif
+#if defined(CONFIG_X86) && defined(CONFIG_SPI)
+ init_func_spi,
+#endif
+#ifdef CONFIG_CMD_NAND
+ initr_nand,
+#endif
+#ifdef CONFIG_CMD_ONENAND
+ initr_onenand,
+#endif
+#ifdef CONFIG_GENERIC_MMC
+ initr_mmc,
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ initr_dataflash,
+#endif
+ initr_env,
+ INIT_FUNC_WATCHDOG_RESET
+ initr_secondary_cpu,
+#ifdef CONFIG_SC3
+ initr_sc3_read_eeprom,
+#endif
+#ifdef CONFIG_HERMES
+ initr_hermes,
+#endif
+#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
+ mac_read_from_eeprom,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
+ /*
+ * Do pci configuration
+ */
+ initr_pci,
+#endif
+ stdio_init,
+ initr_jumptable,
+#ifdef CONFIG_API
+ initr_api,
+#endif
+ console_init_r, /* fully init console as a device */
+#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
+ show_model_r,
+#endif
+#ifdef CONFIG_ARCH_MISC_INIT
+ arch_misc_init, /* miscellaneous arch-dependent init */
+#endif
+#ifdef CONFIG_MISC_INIT_R
+ misc_init_r, /* miscellaneous platform-dependent init */
+#endif
+#ifdef CONFIG_HERMES
+ initr_hermes_start,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#ifdef CONFIG_CMD_KGDB
+ initr_kgdb,
+#endif
+#ifdef CONFIG_X86
+ board_early_init_r,
+#endif
+ interrupt_init,
+#if defined(CONFIG_ARM) || defined(CONFIG_x86)
+ initr_enable_interrupts,
+#endif
+#ifdef CONFIG_X86
+ timer_init, /* initialize timer */
+#endif
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ initr_status_led,
+#endif
+ /* PPC has a udelay(20) here dating from 2002. Why? */
+#ifdef CONFIG_CMD_NET
+ initr_ethaddr,
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+ board_late_init,
+#endif
+#ifdef CONFIG_CMD_SCSI
+ INIT_FUNC_WATCHDOG_RESET
+ initr_scsi,
+#endif
+#ifdef CONFIG_CMD_DOC
+ INIT_FUNC_WATCHDOG_RESET
+ initr_doc,
+#endif
+#ifdef CONFIG_BITBANGMII
+ initr_bbmii,
+#endif
+#ifdef CONFIG_CMD_NET
+ INIT_FUNC_WATCHDOG_RESET
+ initr_net,
+#endif
+#ifdef CONFIG_POST
+ initr_post,
+#endif
+#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
+ initr_pcmcia,
+#endif
+#if defined(CONFIG_CMD_IDE)
+ initr_ide,
+#endif
+#ifdef CONFIG_LAST_STAGE_INIT
+ INIT_FUNC_WATCHDOG_RESET
+ /*
+ * Some parts can be only initialized if all others (like
+ * Interrupts) are up and running (i.e. the PC-style ISA
+ * keyboard).
+ */
+ last_stage_init,
+#endif
+#ifdef CONFIG_CMD_BEDBUG
+ INIT_FUNC_WATCHDOG_RESET
+ initr_bedbug,
+#endif
+#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
+ initr_mem,
+#endif
+#ifdef CONFIG_PS2KBD
+ initr_kbd,
+#endif
+#ifdef CONFIG_MODEM_SUPPORT
+ initr_modem,
+#endif
+ run_main_loop,
+};
+
+void board_init_r(gd_t *new_gd, ulong dest_addr)
+{
+#ifndef CONFIG_X86
+ gd = new_gd;
+#endif
+ if (initcall_run_list(init_sequence_r))
+ hang();
+
+ /* NOTREACHED - run_main_loop() does not return */
+ hang();
+}
#include <linux/err.h>
#include <nand.h>
-#ifdef CONFIG_SILENT_CONSOLE
+#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
static void fixup_silent_linux(void);
#endif
bootstage_mark(BOOTSTAGE_ID_CHECK_BOOT_OS);
-#ifdef CONFIG_SILENT_CONSOLE
+#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
if (images.os.os == IH_OS_LINUX)
fixup_silent_linux();
#endif
/*******************************************************************/
/* helper routines */
/*******************************************************************/
-#ifdef CONFIG_SILENT_CONSOLE
+#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
static void fixup_silent_linux(void)
{
char buf[256], *start, *end;
usb_stop();
#endif
-#ifdef CONFIG_SILENT_CONSOLE
+#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
fixup_silent_linux();
#endif
arch_preboot_os();
+++ /dev/null
-/*
- * Command for accessing DataFlash.
- *
- * Copyright (C) 2008 Atmel Corporation
- */
-#include <common.h>
-#include <df.h>
-
-static int do_df(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- const char *cmd;
-
- /* need at least two arguments */
- if (argc < 2)
- goto usage;
-
- cmd = argv[1];
-
- if (strcmp(cmd, "init") == 0) {
- df_init(0, 0, 1000000);
- return 0;
- }
-
- if (strcmp(cmd, "info") == 0) {
- df_show_info();
- return 0;
- }
-
-usage:
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
- sf, 2, 1, do_serial_flash,
- "Serial flash sub-system",
- "probe [bus:]cs - init flash device on given SPI bus and CS")
" If 'pos' is omitted, 0 is used. 'pos' requires 'bytes'.\n"
" 'bytes' gives the size to load. If 'bytes' is 0 or omitted,\n"
" the load stops on end of file.\n"
+ " If either 'pos' or 'bytes' are not aligned to\n"
+ " ARCH_DMA_MINALIGN then a misaligned buffer warning will\n"
+ " be printed and performance will suffer for the load.\n"
" All numeric parameters are assumed to be hex."
);
}
#endif /* CONFIG_LOOPW */
+#ifdef CONFIG_CMD_MEMTEST
static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
vu_long *dummy)
{
return ret; /* not reached */
}
-
+#endif /* CONFIG_CMD_MEMTEST */
/* Modify memory.
*
);
#endif /* CONFIG_LOOPW */
+#ifdef CONFIG_CMD_MEMTEST
U_BOOT_CMD(
mtest, 5, 1, do_mem_mtest,
"simple RAM read/write test",
"[start [end [pattern [iterations]]]]"
);
+#endif /* CONFIG_CMD_MEMTEST */
#ifdef CONFIG_MX_CYCLIC
U_BOOT_CMD(
return 1;
if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) {
- printf("generated mtdparts too long, reseting to null\n");
+ printf("generated mtdparts too long, resetting to null\n");
return 1;
}
return 0;
index_partitions();
if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) {
- printf("generated mtdparts too long, reseting to null\n");
+ printf("generated mtdparts too long, resetting to null\n");
return 1;
}
return 0;
}
if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) {
- printf("generated mtdparts too long, reseting to null\n");
+ printf("generated mtdparts too long, resetting to null\n");
return 1;
}
int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char message[CONFIG_SYS_CBSIZE];
- int size = CONFIG_SYS_CBSIZE - 1;
- int i, len, pos;
+ int i, len, pos, size;
char *local_args[4];
+ char *endptr;
local_args[0] = argv[0];
local_args[1] = argv[1];
local_args[2] = NULL;
local_args[3] = NULL;
- /* Check the syntax */
- switch (argc) {
- case 1:
+ /*
+ * Check the syntax:
+ *
+ * env_ask envname [message1 ...] [size]
+ */
+ if (argc == 1)
return CMD_RET_USAGE;
- case 2: /* env_ask envname */
- sprintf(message, "Please enter '%s':", argv[1]);
- break;
-
- case 3: /* env_ask envname size */
- sprintf(message, "Please enter '%s':", argv[1]);
- size = simple_strtoul(argv[2], NULL, 10);
- break;
+ /*
+ * We test the last argument if it can be converted
+ * into a decimal number. If yes, we assume it's
+ * the size. Otherwise we echo it as part of the
+ * message.
+ */
+ i = simple_strtoul(argv[argc - 1], &endptr, 10);
+ if (*endptr != '\0') { /* no size */
+ size = CONFIG_SYS_CBSIZE - 1;
+ } else { /* size given */
+ size = i;
+ --argc;
+ }
- default: /* env_ask envname message1 ... messagen size */
- for (i = 2, pos = 0; i < argc - 1; i++) {
+ if (argc <= 2) {
+ sprintf(message, "Please enter '%s': ", argv[1]);
+ } else {
+ /* env_ask envname message1 ... messagen [size] */
+ for (i = 2, pos = 0; i < argc; i++) {
if (pos)
message[pos++] = ' ';
strcpy(message + pos, argv[i]);
pos += strlen(argv[i]);
}
-
+ message[pos++] = ' ';
message[pos] = '\0';
- size = simple_strtoul(argv[argc - 1], NULL, 10);
- break;
}
if (size >= CONFIG_SYS_CBSIZE)
askenv, CONFIG_SYS_MAXARGS, 1, do_env_ask,
"get environment variables from stdin",
"name [message] [size]\n"
- " - get environment variable 'name' from stdin (max 'size' chars)\n"
- "askenv name\n"
- " - get environment variable 'name' from stdin\n"
- "askenv name size\n"
- " - get environment variable 'name' from stdin (max 'size' chars)\n"
- "askenv name [message] size\n"
- " - display 'message' string and get environment variable 'name'"
- "from stdin (max 'size' chars)"
+ " - get environment variable 'name' from stdin (max 'size' chars)"
);
#endif
U_BOOT_CMD(
part, 5, 1, do_part,
"disk partition related commands",
- "
part uuid <interface> <dev>:<part>\n"
+ "uuid <interface> <dev>:<part>\n"
" - print partition UUID\n"
"part uuid <interface> <dev>:<part> <varname>\n"
" - set environment variable to partition UUID\n"
* Watch for 'delay' seconds for autoboot stop or autoboot delay string.
* returns: 0 - no key string, allow autoboot 1 - got key string, abort
*/
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+#if defined(CONFIG_BOOTDELAY)
# if defined(CONFIG_AUTOBOOT_KEYED)
#ifndef CONFIG_MENU
static inline
return abort;
}
# endif /* CONFIG_AUTOBOOT_KEYED */
-#endif /* CONFIG_BOOTDELAY >= 0 */
+#endif /* CONFIG_BOOTDELAY */
/*
* Runs the given boot command securely. Specifically:
* printing the error message to console.
*/
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) && \
- defined(CONFIG_OF_CONTROL)
+#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL)
static void secure_boot_cmd(char *cmd)
{
cmd_tbl_t *cmdtp;
int rc = 1;
int flag;
#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) && \
- defined(CONFIG_OF_CONTROL)
+#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL)
char *env;
#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+#if defined(CONFIG_BOOTDELAY)
char *s;
int bootdelay;
#endif
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
+#if defined CONFIG_OF_CONTROL
+ set_working_fdt_addr((void *)gd->fdt_blob);
+#endif /* CONFIG_OF_CONTROL */
+
#ifdef CONFIG_BOOTCOUNT_LIMIT
bootcount = bootcount_load();
bootcount++;
update_tftp (0UL);
#endif /* CONFIG_UPDATE_TFTP */
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+#if defined(CONFIG_BOOTDELAY)
s = getenv ("bootdelay");
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
#endif /* CONFIG_MENUKEY */
#endif /* CONFIG_BOOTDELAY */
-#if defined CONFIG_OF_CONTROL
- set_working_fdt_addr((void *)gd->fdt_blob);
-#endif /* CONFIG_OF_CONTROL */
-
/*
* Main Loop for Monitor Command Processing
*/
CPPFLAGS += -DCONFIG_SPL_BUILD
endif
+# Does this architecture support generic board init?
+ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
+ifneq ($(CONFIG_SYS_GENERIC_BOARD),)
+$(error Your architecture does not support generic board. Please undefined \
+CONFIG_SYS_GENERIC_BOARD in your board config file)
+endif
+endif
+
ifneq ($(RESET_VECTOR_ADDRESS),)
CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS)
endif
--- /dev/null
+The most frequent cause of problems when porting U-Boot to new
+hardware, or when using a sloppy port on some board, is memory errors.
+In most cases these are not caused by failing hardware, but by
+incorrect initialization of the memory controller. So it appears to
+be a good idea to always test if the memory is working correctly,
+before looking for any other potential causes of any problems.
+
+U-Boot implements 3 different approaches to perform memory tests:
+
+1. The get_ram_size() function (see "common/memsize.c").
+
+ This function is supposed to be used in each and every U-Boot port
+ determine the presence and actual size of each of the potential
+ memory banks on this piece of hardware. The code is supposed to be
+ very fast, so running it for each reboot does not hurt. It is a
+ little known and generally underrated fact that this code will also
+ catch 99% of hardware related (i. e. reliably reproducible) memory
+ errors. It is strongly recommended to always use this function, in
+ each and every port of U-Boot.
+
+2. The "mtest" command.
+
+ This is probably the best known memory test utility in U-Boot.
+ Unfortunately, it is also the most problematic, and the most
+ useless one.
+
+ There are a number of serious problems with this command:
+
+ - It is terribly slow. Running "mtest" on the whole system RAM
+ takes a _long_ time before there is any significance in the fact
+ that no errors have been found so far.
+
+ - It is difficult to configure, and to use. And any errors here
+ will reliably crash or hang your system. "mtest" is dumb and has
+ no knowledge about memory ranges that may be in use for other
+ purposes, like exception code, U-Boot code and data, stack,
+ malloc arena, video buffer, log buffer, etc. If you let it, it
+ will happily "test" all such areas, which of course will cause
+ some problems.
+
+ - It is not easy to configure and use, and a large number of
+ systems are seriously misconfigured. The original idea was to
+ test basically the whole system RAM, with only exempting the
+ areas used by U-Boot itself - on most systems these are the areas
+ used for the exception vectors (usually at the very lower end of
+ system memory) and for U-Boot (code, data, etc. - see above;
+ these are usually at the very upper end of system memory). But
+ experience has shown that a very large number of ports use
+ pretty much bogus settings of CONFIG_SYS_MEMTEST_START and
+ CONFIG_SYS_MEMTEST_END; this results in useless tests (because
+ the ranges is too small and/or badly located) or in critical
+ failures (system crashes).
+
+ Because of these issues, the "mtest" command is considered depre-
+ cated. It should not be enabled in most normal ports of U-Boot,
+ especially not in production. If you really need a memory test,
+ then see 1. and 3. above resp. below.
+
+3. The most thorough memory test facility is available as part of the
+ POST (Power-On Self Test) sub-system, see "post/drivers/memory.c".
+
+ If you really need to perform memory tests (for example, because
+ it is mandatory part of your requirement specification), then
+ enable this test which is generic and should work on all archi-
+ tectures.
+
+WARNING:
+
+It should pointed out that _all_ these memory tests have one
+fundamental, unfixable design flaw: they are based on the assumption
+that memory errors can be found by writing to and reading from memory.
+Unfortunately, this is only true for the relatively harmless, usually
+static errors like shorts between data or address lines, unconnected
+pins, etc. All the really nasty errors which will first turn your
+hair gray, only to make you tear it out later, are dynamical errors,
+which usually happen not with simple read or write cycles on the bus,
+but when performing back-to-back data transfers in burst mode. Such
+accesses usually happen only for certain DMA operations, or for heavy
+cache use (instruction fetching, cache flushing). So far I am not
+aware of any freely available code that implements a generic, and
+efficient, memory test like that. The best known test case to stress
+a system like that is to boot Linux with root file system mounted over
+NFS, and then build some larger software package natively (say,
+compile a Linux kernel on the system) - this will cause enough context
+switches, network traffic (and thus DMA transfers from the network
+controller), varying RAM use, etc. to trigger any weak spots in this
+area.
+
+Note: An attempt was made once to implement such a test to catch
+memory problems on a specific board. The code is pretty much board
+specific (for example, it includes setting specific GPIO signals to
+provide triggers for an attached logic analyzer), but you can get an
+idea how it works: see "examples/standalone/test_burst*".
+
+Note 2: Ironically enough, the "test_burst" did not catch any RAM
+errors, not a single one ever. The problems this code was supposed
+to catch did not happen when accessing the RAM, but when reading from
+NOR flash.
adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi <adrian.filipi@eurotech.com>
R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. Landau <zachary.landau@labxtechnologies.com>
CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de>
+PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk <wd@denx.de>
- When booting a linux kernel, the "bootargs" are fixed up so that
the argument "console=" will be in the command line, no matter how
- it was set in "bootargs" before.
+ it was set in "bootargs" before. If you don't want the linux command
+ line to be affected, define CONFIG_SILENT_U_BOOT_ONLY in your board
+ config file as well, and this part of the feature will be disabled.
----------------
Standard driver, uses indirect functions.
- 8) pcippc2/cpc710_pci.c
- -----------------------
- Standard driver, uses indirect functions, has two busses.
-
9) Marvell/db64360/pci.c
------------------------
Standard driver, uses dword for read/write ops, has two busses.
Only function proxy call. Code cleanup needed.
- 45) board/pcippc2/pcippc2.c
- ---------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
46) board/pcs440ep/pcs440ep.c
-----------------------------
The driver is standard HW watchdog. Simple conversion is possible.
---------------------------
+What: Remove CONFIG_CMD_MEMTEST from default list
+When: Release v2013.07
+
+Why: The "mtest" command is of little practical use (if any), and
+ experience has shown that a large number of board configu-
+ rations define useless or even dangerous start and end
+ addresses. If not even the board maintainers are able to
+ figure out which memory range can be reliably tested, how can
+ we expect such from the end users? As this problem comes up
+ repeatedly, we rather do not enable this command by default,
+ so only people who know what they are doing will be confronted
+ with it.
+
+Who: Wolfgang Denk <wd@denx.de>
+
+---------------------------
+
What: Users of the legacy miiphy_* code
When: undetermined
* Sanity checks:
* - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
* - for ide_preinit to make sense, we need at least one of
- * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET;
- * - for inde_preinit to be called, we need CONFIG_IDE_PREINIT.
+ * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
+ * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
* Fail with an explanation message if these conditions are not met.
* This is particularly important for CONFIG_IDE_PREINIT, because
* its lack would not cause a build error.
#endif
}
-#if 0
-static void SetI2CSDA(int x)
-{
- rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
-}
-#endif
-
static void SetI2CSCL(int x)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
&i2c->iicstat);
i = 0;
- while ((i < data_len) && (result = I2C_OK)) {
+ while ((i < data_len) && (result == I2C_OK)) {
result = WaitForXfer(i2c);
writel(data[i], &i2c->iicds);
ReadWriteByte(i2c);
result = WaitForXfer(i2c);
/* send STOP */
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
ReadWriteByte(i2c);
break;
case I2C_READ:
if (addr && addr_len) {
- writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
writel(chip, &i2c->iicds);
/* send START */
- writel(readl(&i2c->iicstat) | I2C_START_STOP,
- &i2c->iicstat);
+ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
+ &i2c->iicstat);
result = WaitForXfer(i2c);
if (IsACK(i2c)) {
i = 0;
}
} else {
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
writel(chip, &i2c->iicds);
/* send START */
- writel(readl(&i2c->iicstat) | I2C_START_STOP,
- &i2c->iicstat);
+ writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
+ &i2c->iicstat);
result = WaitForXfer(i2c);
if (IsACK(i2c)) {
out8(RTC_PORT_DATA, val);
}
-#elif defined(CONFIG_PCIPPC2)
-
-#include "../board/pcippc2/pcippc2.h"
-
-static uchar rtc_read (short reg)
-{
- return in8(RTC(reg));
-}
-
-static void rtc_write (short reg, uchar val)
-{
- out8(RTC(reg),val);
-}
-
#elif defined(CONFIG_EVAL5200)
static uchar rtc_read (short reg)
defined(CONFIG_AM33XX)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
- serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
+ serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
serial_out(0, &com_port->dll);
serial_out(0, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
#include <_exports.h>
}
-extern unsigned long __bss_start, _end;
+#include <asm/sections.h>
void app_startup(char * const *argv)
{
- unsigned char * cp = (unsigned char *) &__bss_start;
+ char *cp = __bss_start;
/* Zero out BSS */
- while (cp < (unsigned char *)&_end) {
+ while (cp < _end)
*cp++ = 0;
- }
#if defined(CONFIG_X86)
/* x86 does not have a dedicated register for passing global_data */
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
unsigned long reloc_off;
struct global_data *new_gd; /* relocated global data */
const void *fdt_blob; /* Our device tree, NULL if none */
+ void *new_fdt; /* Relocated FDT */
+ unsigned long fdt_size; /* Space reserved for relocated FDT */
void **jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */
struct arch_global_data arch; /* architecture-specific data */
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Taken from Linux kernel, commit f56c3196 */
+
+#ifndef _ASM_GENERIC_SECTIONS_H_
+#define _ASM_GENERIC_SECTIONS_H_
+
+/* References to section boundaries */
+
+extern char _text[], _stext[], _etext[];
+extern char _data[], _sdata[], _edata[];
+extern char __bss_start[], __bss_stop[];
+extern char __init_begin[], __init_end[];
+extern char _sinittext[], _einittext[];
+extern char _end[];
+extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[];
+extern char __kprobes_text_start[], __kprobes_text_end[];
+extern char __entry_text_start[], __entry_text_end[];
+extern char __initdata_begin[], __initdata_end[];
+extern char __start_rodata[], __end_rodata[];
+
+/* Start and end of .ctors section - used for constructor calls. */
+extern char __ctors_start[], __ctors_end[];
+
+/* function descriptor handling (if any). Override
+ * in asm/sections.h */
+#ifndef dereference_function_descriptor
+#define dereference_function_descriptor(p) (p)
+#endif
+
+/* random extra sections (if any). Override
+ * in asm/sections.h */
+#ifndef arch_is_kernel_text
+static inline int arch_is_kernel_text(unsigned long addr)
+{
+ return 0;
+}
+#endif
+
+#ifndef arch_is_kernel_data
+static inline int arch_is_kernel_data(unsigned long addr)
+{
+ return 0;
+}
+#endif
+
+/* U-Boot-specific things begin here */
+
+/* Start of U-Boot text region */
+extern char __text_start[];
+
+/* This marks the end of the text region which must be relocated */
+extern char __image_copy_end[];
+
+/*
+ * This is the U-Boot entry point - prior to relocation it should be same
+ * as __text_start
+ */
+extern void _start(void);
+
+/*
+ * ARM needs to use offsets for symbols, since the values of some symbols
+ * are not resolved prior to relocation (and are just 0). Maybe this can be
+ * resolved, or maybe other architectures are similar, iwc this should be
+ * promoted to an architecture option.
+ */
+#ifdef CONFIG_ARM
+#define CONFIG_SYS_SYM_OFFSETS
+#endif
+
+#ifdef CONFIG_SYS_SYM_OFFSETS
+/* Start/end of the relocation entries, as an offset from _start */
+extern ulong _rel_dyn_start_ofs;
+extern ulong _rel_dyn_end_ofs;
+
+/* Start/end of the relocation symbol table, as an offset from _start */
+extern ulong _dynsym_start_ofs;
+
+/* End of the region to be relocated, as an offset form _start */
+extern ulong _image_copy_end_ofs;
+
+extern ulong _bss_start_ofs; /* BSS start relative to _start */
+extern ulong _bss_end_ofs; /* BSS end relative to _start */
+extern ulong _end_ofs; /* end of image relative to _start */
+
+extern ulong _TEXT_BASE; /* code start */
+
+#else /* don't use offsets: */
+
+/* Exports from the Linker Script */
+extern ulong __data_end;
+extern ulong __rel_dyn_start;
+extern ulong __rel_dyn_end;
+extern ulong __bss_end;
+
+extern ulong _TEXT_BASE; /* code start */
+
+#endif
+
+#endif /* _ASM_GENERIC_SECTIONS_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_GENERIC_U_BOOT_H__
+#define __ASM_GENERIC_U_BOOT_H__
+
+/*
+ * Board information passed to Linux kernel from U-Boot
+ *
+ * include/asm-ppc/u-boot.h
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct bd_info {
+ unsigned long bi_memstart; /* start of DRAM memory */
+ phys_size_t bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+ unsigned long bi_sramstart; /* start of SRAM memory */
+ unsigned long bi_sramsize; /* size of SRAM memory */
+#ifdef CONFIG_ARM
+ unsigned long bi_arm_freq; /* arm frequency */
+ unsigned long bi_dsp_freq; /* dsp core frequency */
+ unsigned long bi_ddr_freq; /* ddr frequency */
+#endif
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+ unsigned long bi_immr_base; /* base of IMMR register */
+#endif
+#if defined(CONFIG_MPC5xxx)
+ unsigned long bi_mbar_base; /* base of internal registers */
+#endif
+#if defined(CONFIG_MPC83xx)
+ unsigned long bi_immrbar;
+#endif
+#if defined(CONFIG_MPC8220)
+ unsigned long bi_mbar_base; /* base of internal registers */
+ unsigned long bi_inpfreq; /* Input Freq, In MHz */
+ unsigned long bi_pcifreq; /* PCI Freq, in MHz */
+ unsigned long bi_pevfreq; /* PEV Freq, in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */
+ unsigned long bi_vcofreq; /* VCO Freq, in MHz */
+#endif
+ unsigned long bi_bootflags; /* boot / reboot flag (Unused) */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */
+ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
+ unsigned long bi_intfreq; /* Internal Freq, in MHz */
+ unsigned long bi_busfreq; /* Bus Freq, in MHz */
+#if defined(CONFIG_CPM2)
+ unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
+ unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
+ unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
+ unsigned long bi_vco; /* VCO Out from PLL, in MHz */
+#endif
+#if defined(CONFIG_MPC512X)
+ unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
+#endif /* CONFIG_MPC512X */
+#if defined(CONFIG_MPC5xxx)
+ unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
+ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
+#endif
+ unsigned int bi_baudrate; /* Console Baudrate */
+#if defined(CONFIG_405) || \
+ defined(CONFIG_405GP) || \
+ defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || \
+ defined(CONFIG_405EZ) || \
+ defined(CONFIG_405EX) || \
+ defined(CONFIG_440)
+ unsigned char bi_s_version[4]; /* Version of this structure */
+ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
+ unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
+ unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
+ unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
+ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
+#endif
+#if defined(CONFIG_HYMOD)
+ hymod_conf_t bi_hymod_conf; /* hymod configuration information */
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+ unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH2
+ unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH3
+ unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH4
+ unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH5
+ unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */
+#endif
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+ defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ unsigned int bi_opbfreq; /* OPB clock in Hz */
+ int bi_iic_fast[2]; /* Use fast i2c mode */
+#endif
+#if defined(CONFIG_NX823)
+ unsigned char bi_sernum[8];
+#endif
+#if defined(CONFIG_4xx)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ int bi_phynum[4]; /* Determines phy mapping */
+ int bi_phymode[4]; /* Determines phy mode */
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
+ int bi_phynum[2]; /* Determines phy mapping */
+ int bi_phymode[2]; /* Determines phy mode */
+#else
+ int bi_phynum[1]; /* Determines phy mapping */
+ int bi_phymode[1]; /* Determines phy mode */
+#endif
+#endif /* defined(CONFIG_4xx) */
+ ulong bi_arch_number; /* unique id for this board */
+ ulong bi_boot_params; /* where this board expects params */
+#ifdef CONFIG_NR_DRAM_BANKS
+ struct { /* RAM configuration */
+ ulong start;
+ ulong size;
+ } bi_dram[CONFIG_NR_DRAM_BANKS];
+#endif /* CONFIG_NR_DRAM_BANKS */
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_GENERIC_U_BOOT_H__ */
int mac_read_from_eeprom(void);
extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */
int set_cpu_clk_info(void);
+int print_cpuinfo(void);
+int update_flash_size(int flash_size);
/**
* Show the DRAM size in a board-specific way
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMINFO /* meminfo */
-#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */
+#define CONFIG_CMD_MEMTEST /* mtest */
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#endif
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
-#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */
+#define CONFIG_CMD_MEMTEST /* mtest */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
+++ /dev/null
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the PCIPPC-2 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_PREBOOT ""
-#define CONFIG_BOOTDELAY 5
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
-/* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
- CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-
-/*
- * Temporary buffer for serial data until the real serial driver
- * is initialised (memtest will destroy this buffer)
- */
-#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
-
-/* SDRAM 0 - 256MB
- */
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \
- BATU_BL_256M | BATU_VS | BATU_VP)
-/* SDRAM 1 - 256MB
- */
-#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
- BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
- BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Init RAM in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \
- BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \
- BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* I/O and PCI memory at 0xf0000000
- */
-#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
-#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
-#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the PCIPPC2 user's manual.
- */
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */
-#define CONFIG_SYS_CPU_CLK 300000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-/*
- * Note: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * L2 cache
- */
-#undef CONFIG_SYS_L2
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-/*-----------------------------------------------------------------------
- RTC m48t59
-*/
-#define CONFIG_RTC_MK48T59
-
-#define CONFIG_WATCHDOG
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_TULIP
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the PCIPPC-6 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_PREBOOT ""
-#define CONFIG_BOOTDELAY 5
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
-/* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
- CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-
-/*
- * Temporary buffer for serial data until the real serial driver
- * is initialised (memtest will destroy this buffer)
- */
-#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
-
-/* SDRAM 0 - 256MB
- */
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \
- BATU_BL_256M | BATU_VS | BATU_VP)
-/* SDRAM 1 - 256MB
- */
-#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
- BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
- BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Init RAM in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \
- BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \
- BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* I/O and PCI memory at 0xf0000000
- */
-#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
-#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
-#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the PCIPPC2 user's manual.
- */
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */
-#define CONFIG_SYS_CPU_CLK 300000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-/*
- * Note: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * L2 cache
- */
-#undef CONFIG_SYS_L2
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-/*-----------------------------------------------------------------------
- RTC m48t59
-*/
-#define CONFIG_RTC_MK48T59
-
-#define CONFIG_WATCHDOG
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_TULIP
-
-
-#define CONFIG_SCSI_SYM53C8XX
-#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */
-#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */
-#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
-#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
-#define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#endif /* __CONFIG_H */
#define CONFIG_MPC5200
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_A3M071 /* ... on A3M071 board */
-#define CONFIG_MPC5200_DDR /* ... use DDR RAM */
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
+#define CONFIG_SPL_TARGET "u-boot-img.bin"
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
+#ifdef CONFIG_A4M2K
+#define CONFIG_HOSTNAME a4m2k
+#else
+#define CONFIG_HOSTNAME a3m071
+#endif
+
/*
* Serial console configuration
*/
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_REGINFO
*/
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/* define for 66MHz speed - undef for 33MHz PCI clock speed */
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#else
#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
* NOR flash configuration
*/
#define CONFIG_SYS_FLASH_BASE 0xfc000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_FLASH_SIZE 0x02000000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
*/
#define CONFIG_MPC5xxx_FEC
#define CONFIG_MPC5xxx_FEC_MII100
+#ifdef CONFIG_A4M2K
+#define CONFIG_PHY_ADDR 0x01
+#else
#define CONFIG_PHY_ADDR 0x00
+#endif
/*
* GPIO configuration
* 2 means fpga ok
*/
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805
+#else
/* for failsave-level 0 - full failsave */
#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
/* for failsave-level 1 - only digiboard ok */
#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005
/* for failsave-level 2 - all ok */
#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005
+#endif
+
+#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
+#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
+#endif
/*
* Configuration matrix
* MSB LSB
- * failsave 0 0x1005C005 00010000000001011100000001100101 ( full failsave )
- * failsave 1 0x1005C005 00010000000001011100000001100101 ( digib.-ver ok )
- * failsave 2 0x1005C005 00010000000001011100000001100101 ( all ok )
+ * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
+ * failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok )
+ * failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok )
* || ||| || | ||| | | | |
* || ||| || | ||| | | | | bit rev name
* ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+
+#ifdef CONFIG_A4M2K
+/* external MRAM */
+#define CONFIG_SYS_CS1_START 0xf1000000
+#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
+#endif
+
#define CONFIG_SYS_CS2_START 0xe0000000
#define CONFIG_SYS_CS2_SIZE 0x00100000
-/* FPGA slave io (512kiB) - see ticket #66 */
+/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
#define CONFIG_SYS_CS3_START 0xE9000000
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_CS3_SIZE 0x00100000
+#else
#define CONFIG_SYS_CS3_SIZE 0x00080000
+#endif
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
#define CONFIG_SYS_CS3_CFG 0x0032B900
+#ifndef CONFIG_A4M2K
/* Diagnosis Interface - see ticket #63 */
#define CONFIG_SYS_CS4_START 0xEA000000
#define CONFIG_SYS_CS4_SIZE 0x00000001
/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
#define CONFIG_SYS_CS4_CFG 0x0002B900
+#endif
-/* FPGA master io (64kiB) - see ticket #66 */
+/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
#define CONFIG_SYS_CS5_START 0xE8000000
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_CS5_SIZE 0x00100000
+#else
#define CONFIG_SYS_CS5_SIZE 0x00010000
+#endif
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
#define CONFIG_SYS_CS5_CFG 0x0032B900
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
-#define CONFIG_SYS_CS1_CFG 0x0004FB00
+#define CONFIG_SYS_CS1_CFG 0x0008FD00
#define CONFIG_SYS_CS2_CFG 0x0006F90C
#else /* for pci_clk = 33 MHz */
#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
#define CONFIG_SYS_OS_BASE 0xfc080000
#define CONFIG_SYS_FDT_BASE 0xfc060000
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
"netdev=eth0\0" \
"verify=no\0" \
+ "loadaddr=200000\0" \
+ "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
+ "kernel_addr_r=1000000\0" \
+ "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
+ "fdt_addr_r=1800000\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
+ __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "rootpath=/opt/eldk-5.2.1/powerpc/" \
+ "core-image-minimal-mtdutils-dropbear-generic\0" \
"consoledev=ttyPSC0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\
+ "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_mtd=run mtdargs addip addtty;" \
"bootm ${kernel_addr} - ${fdtaddr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
- "net_nfs=sleep 2; tftp ${loadaddr} ${bootfile};" \
- "tftp c00000 ${fdtfile};" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdtfile};" \
"run nfsargs addip addtty;" \
- "bootm ${loadaddr} - c00000\0" \
- "load=tftp ${loadaddr} u-boot.bin\0" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
+ "/u-boot-img.bin\0" \
"update=protect off fc000000 fc03ffff; " \
- "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\
+ "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \
"upd=run load;run update\0" \
- "fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0" \
- "fdtfile=dtbFile\0" \
- "kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0" \
+ "bootdelay=3\0" \
+ "bootcmd=run net_nfs\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_mtd"
*/
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xfc000000
#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
--- /dev/null
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2010 DAVE Srl <www.dave.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * ifm AC14xx (MPC5121e based) board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AC14XX 1
+/*
+ * Memory map for the ifm AC14xx board:
+ *
+ * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
+ * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
+ * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
+ * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx)
+ * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC512X 1 /* MPC512X family */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */
+#define SCFR1_IPS_DIV 2
+#define SCFR1_LPC_DIV 2
+#define SCFR1_NFC_DIV 2
+#define SCFR1_DIU_DIV 240
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR 0x80000000
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
+
+/* more aggressive 'mtest' over a wider address range */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x0FE00000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE 256 /* MB */
+#define CONFIG_SYS_DDR_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
+
+/*
+ * DDR Controller Configuration XXX TODO
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Ready Delay: 2
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Disabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */
+
+/*
+ * NOTE: although this board uses DDR1 only, the common source brings defaults
+ * for DDR2 init sequences, that's why we have to keep those here as well
+ */
+
+/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
+#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0))
+
+#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
+ | (1 << 31) /* RST_B */ \
+ | (1 << 30) /* CKE */ \
+ | (1 << 29) /* CLK_ON */ \
+ | (0 << 28) /* CMD_MODE */ \
+ | (5 << 25) /* DRAM_ROW_SELECT */ \
+ | (5 << 21) /* DRAM_BANK_SELECT */ \
+ | (0 << 18) /* SELF_REF_EN */ \
+ | (0 << 17) /* 16BIT_MODE */ \
+ | (4 << 13) /* RDLY */ \
+ | (1 << 12) /* HALF_DQS_DLY */ \
+ | (0 << 11) /* QUART_DQS_DLY */ \
+ | (1 << 8) /* WDLY */ \
+ | (0 << 7) /* EARLY_ODT */ \
+ | (0 << 6) /* ON_DIE_TERMINATE */ \
+ | (0 << 5) /* FIFO_OV_CLEAR */ \
+ | (0 << 4) /* FIFO_UV_CLEAR */ \
+ | (0 << 1) /* FIFO_OV_EN */ \
+ | (0 << 0) /* FIFO_UV_EN */ \
+ )
+
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124
+#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147
+#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864
+
+/* register address only, i.e. template without values */
+#define CONFIG_SYS_MICRON_BMODE 0x01000000
+#define CONFIG_SYS_MICRON_EMODE 0x01010000
+#define CONFIG_SYS_MICRON_EMODE2 0x01020000
+#define CONFIG_SYS_MICRON_EMODE3 0x01030000
+/*
+ * values for mode registers (without mode register address)
+ */
+/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
+#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062
+#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100
+/* DLL enable, reduced drive strength */
+#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002
+
+#define CONFIG_SYS_DDRCMD_NOP 0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
+#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \
+ (0 << 22) | /* DRAM_CS */ \
+ (0 << 21) | /* DRAM_RAS */ \
+ (0 << 20) | /* DRAM_CAS */ \
+ (0 << 19) | /* DRAM_WEB */ \
+ (1 << 16) | /* DRAM_BS[2:0] */ \
+ (0 << 15) | /* */ \
+ (0 << 12) | /* A12->out */ \
+ (0 << 11) | /* A11->RDQS */ \
+ (0 << 10) | /* A10->DQS# */ \
+ (0 << 7) | /* OCD program */ \
+ (0 << 6) | /* Rtt1 */ \
+ (0 << 3) | /* posted CAS# */ \
+ (0 << 2) | /* Rtt0 */ \
+ (1 << 1) | /* ODS */ \
+ (0 << 0) /* DLL */ \
+ )
+#define CONFIG_SYS_MICRON_EMR2 0x01020000
+#define CONFIG_SYS_MICRON_EMR3 0x01030000
+#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
+#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \
+ (0 << 22) | /* DRAM_CS */ \
+ (0 << 21) | /* DRAM_RAS */ \
+ (0 << 20) | /* DRAM_CAS */ \
+ (0 << 19) | /* DRAM_WEB */ \
+ (1 << 16) | /* DRAM_BS[2:0] */ \
+ (0 << 15) | /* */ \
+ (0 << 12) | /* A12->out */ \
+ (0 << 11) | /* A11->RDQS */ \
+ (1 << 10) | /* A10->DQS# */ \
+ (7 << 7) | /* OCD program */ \
+ (0 << 6) | /* Rtt1 */ \
+ (0 << 3) | /* posted CAS# */ \
+ (1 << 2) | /* Rtt0 */ \
+ (0 << 1) | /* ODS */ \
+ (0 << 0) /* DLL */ \
+ )
+
+/*
+ * Backward compatible definitions,
+ * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
+ */
+#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
+#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
+#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { \
+ CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
+ }
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * SRAM support
+ */
+#define CONFIG_SYS_SRAM_BASE 0x30000000
+#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
+
+/*
+ * CS related parameters
+ * TODO document these
+ */
+/* CS0 Flash */
+#define CONFIG_SYS_CS0_CFG 0x00031110
+#define CONFIG_SYS_CS0_START 0xFC000000
+#define CONFIG_SYS_CS0_SIZE 0x04000000
+/* CS1 FRAM */
+#define CONFIG_SYS_CS1_CFG 0x00011000
+#define CONFIG_SYS_CS1_START 0xE0000000
+#define CONFIG_SYS_CS1_SIZE 0x00010000
+/* CS2 AS-i 1 */
+#define CONFIG_SYS_CS2_CFG 0x00009100
+#define CONFIG_SYS_CS2_START 0xE0100000
+#define CONFIG_SYS_CS2_SIZE 0x00080000
+/* CS3 netX */
+#define CONFIG_SYS_CS3_CFG 0x000A1140
+#define CONFIG_SYS_CS3_START 0xE0300000
+#define CONFIG_SYS_CS3_SIZE 0x00020000
+/* CS5 safety */
+#define CONFIG_SYS_CS5_CFG 0x0011F000
+#define CONFIG_SYS_CS5_START 0xE0400000
+#define CONFIG_SYS_CS5_SIZE 0x00010000
+/* CS6 AS-i 2 */
+#define CONFIG_SYS_CS6_CFG 0x00009100
+#define CONFIG_SYS_CS6_START 0xE0200000
+#define CONFIG_SYS_CS6_SIZE 0x00080000
+
+/* Don't use alternative CS timing for any CS */
+#define CONFIG_SYS_CS_ALETIMING 0x00000000
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x00000020
+#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
+#define CONFIG_SYS_PSC3
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
+
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSC_EN(7) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
+
+#define CONFIG_CMDLINE_EDITING 1 /* command line history */
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration for Atmel AT24C01:
+ * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC 1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 0x1F
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_FEC_AN_TIMEOUT 1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+/* This has to be a multiple of the flash sector size */
+#define CONFIG_ENV_ADDR 0xFFF40000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_EXT2
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "ac14xx> " /* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 32
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 32768
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
+#endif
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ICE)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01
+#define BOOTFLAG_WARM 0x02
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME ac14xx
+#define CONFIG_BOOTFILE "ac14xx/uImage"
+#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
+
+/* default load addr for tftp and bootm */
+#define CONFIG_LOADADDR 400000
+
+#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
+
+/* XXX TODO need to specify the builtin environment */
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
+ "muster_nr=00\0" \
+ "fromram=run ramargs addip addtty; " \
+ "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \
+ "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \
+ "tftp ${ramdisk_addr_r} k6m2/uFS-${muster_nr}; " \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+ "fromnfs=run nfsargs addip addtty; " \
+ "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \
+ "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "fromflash=run nfsargs addip addtty; " \
+ "bootm fc020000 - fc000000\0" \
+ "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \
+ "recovery=run mtdargsrec addip addtty; " \
+ "bootm ffd20000 - ffee0000\0" \
+ "production=run ramargs addip addtty; " \
+ "bootm fc020000 fc400000 fc000000\0" \
+ "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \
+ "prodmtd=run mtdargs addip addtty; " \
+ "bootm fc020000 - fc000000\0" \
+ ""
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u-boot_addr_r=200000\0" \
+ "kernel_addr_r=600000\0" \
+ "fdt_addr_r=a00000\0" \
+ "ramdisk_addr_r=b00000\0" \
+ "u-boot_addr=FFF00000\0" \
+ "kernel_addr=FC020000\0" \
+ "fdt_addr=FC000000\0" \
+ "ramdisk_addr=FC400000\0" \
+ "verify=n\0" \
+ "ramdiskfile=ac14xx/uRamdisk\0" \
+ "u-boot=ac14xx/u-boot.bin\0" \
+ "bootfile=ac14xx/uImage\0" \
+ "fdtfile=ac14xx/ac14xx.dtb\0" \
+ "rootpath=/opt/eldk/ppc_6xx\n" \
+ "netdev=eth0\0" \
+ "consdev=ttyPSC0\0" \
+ "hostname=ac14xx\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}-${muster_nr}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdtfile};" \
+ "run nfsargs addip addtty;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "net_self=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
+ "tftp ${fdt_addr_r} ${fdtfile};" \
+ "run ramargs addip addtty;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+ "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
+ "update=protect off ${u-boot_addr} +${filesize};" \
+ "era ${u-boot_addr} +${filesize};" \
+ "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
+ CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
+ "upd=run load update\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run production"
+
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
+
+#define OF_CPU "PowerPC,5121@0"
+#define OF_SOC_COMPAT "fsl,mpc5121-immr"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_IMMR 0x80000000
#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
CONFIG_SYS_SRAM_SIZE)
#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
+#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE
+#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE
#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
CONFIG_SYS_ARIA_SRAM_SIZE)
#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
+#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE
+#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE
+
#define CONFIG_SYS_CS0_CFG 0x05059150
#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
(5 << 16) | \
#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
#define FSL_ATA_CTRL_IORDY_EN 0x01000000
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PATA_EN | \
+ CLOCK_SCCR1_PCI_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
#endif /* __CONFIG_H */
#include <asm/arch/cpu.h> /* get chip and board defs */
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#ifndef __CONFIG_KEYMILE_H
#define __CONFIG_KEYMILE_H
-/* Do boardspecific init for all boards */
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
#define CONFIG_BOOTCOUNT_LIMIT
/*
#ifndef __CONFIG_KEYMILE_POWERPC_H
#define __CONFIG_KEYMILE_POWERPC_H
+/* Do boardspecific init for all boards */
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_CMD_DTT
#define CONFIG_SYS_SRAM_BASE 0x30000000
#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
+/* Initialize Local Window for NOR FLASH access */
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+
/* ALE active low, data size 4bytes */
#define CONFIG_SYS_CS0_CFG 0x05051150
#define CONFIG_SYS_CS1_CFG 0x1f1f3090
#define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */
#define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */
+/* Initialize Local Window for VPC3 access */
+#define CONFIG_SYS_CS1_START CONFIG_SYS_VPC3_BASE
+#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_VPC3_SIZE
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */
#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PCI_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
+
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
*/
#define CONFIG_SYS_CPLD_BASE 0x82000000
#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
+#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE
#define CONFIG_SYS_SRAM_BASE 0x30000000
#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
#endif
/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PATA_EN | \
+ CLOCK_SCCR1_PCI_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN | \
+ CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_USB1_EN | \
+ CLOCK_SCCR2_USB2_EN)
+
+/*
* PCI
*/
#ifdef CONFIG_PCI
#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_IMMR 0x80000000
#define CONFIG_SYS_SRAM_BASE 0x50000000
#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
+#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE
+#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
+
/* ALE active low, data size 4 bytes */
#define CONFIG_SYS_CS0_CFG 0x05059350
/* ALE active low, data size 4 bytes */
#define CONFIG_SYS_MRAM_BASE 0x50040000
#define CONFIG_SYS_MRAM_SIZE 0x00020000
+#define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE
+
/* ALE active low, data size 4 bytes */
#define CONFIG_SYS_CS2_CFG 0x05059110
#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
+/*
* Used PSC UART devices
*/
#define CONFIG_SYS_PSC1
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SYS_GENERIC_BOARD
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER
void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
+/**
+ * board_start_ide() - Start up the board IDE interfac
+ *
+ * @return 0 if ok
+ */
+int board_start_ide(void);
+
#endif /* _IDE_H */
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef int (*init_fnc_t)(void);
+
+int initcall_run_list(init_fnc_t init_sequence[]);
#ifndef _WATCHDOG_H_
#define _WATCHDOG_H_
+#if !defined(__ASSEMBLY__)
+/*
+ * Reset the watchdog timer, always returns 0
+ *
+ * This function is here since it is shared between board_f() and board_r(),
+ * and the legacy arch/<arch>/board.c code.
+ */
+int init_func_watchdog_reset(void);
+#endif
+
+#ifdef CONFIG_WATCHDOG
+#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
+#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
+#else
+#define INIT_FUNC_WATCHDOG_INIT
+#define INIT_FUNC_WATCHDOG_RESET
+#endif
+
#if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG)
# error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together."
#endif
COBJS-$(CONFIG_GZIP) += gunzip.o
COBJS-$(CONFIG_GZIP_COMPRESSED) += gzip.o
COBJS-y += hashtable.o
+COBJS-y += initcall.o
COBJS-$(CONFIG_LMB) += lmb.o
COBJS-y += ldiv.o
COBJS-$(CONFIG_MD5) += md5.o
linelen = DEFAULT_LINE_LENGTH_BYTES / width;
while (count) {
+ uint thislinelen = linelen;
printf("%08lx:", addr);
/* check for overflow condition */
- if (count < linelen)
- linelen = count;
+ if (count < thislinelen)
+ thislinelen = count;
/* Copy from memory into linebuf and print hex values */
- for (i = 0; i < linelen; i++) {
+ for (i = 0; i < thislinelen; i++) {
uint32_t x;
if (width == 4)
x = lb.ui[i] = *(volatile uint32_t *)data;
data += width;
}
+ while (thislinelen < linelen) {
+ /* fill line with whitespace for nice ASCII print */
+ for (i=0; i<width*2+1; i++)
+ puts(" ");
+ linelen--;
+ }
+
/* Print data in ASCII characters */
- for (i = 0; i < linelen * width; i++) {
+ for (i = 0; i < thislinelen * width; i++) {
if (!isprint(lb.uc[i]) || lb.uc[i] >= 0x80)
lb.uc[i] = '.';
}
printf(" %s\n", lb.uc);
/* update references */
- addr += linelen * width;
- count -= linelen;
+ addr += thislinelen * width;
+ count -= thislinelen;
if (ctrlc())
return -1;
--- /dev/null
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <initcall.h>
+
+int initcall_run_list(init_fnc_t init_sequence[])
+{
+ init_fnc_t *init_fnc_ptr;
+
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+ debug("initcall: %p\n", *init_fnc_ptr);
+ if ((*init_fnc_ptr)()) {
+ debug("initcall sequence %p failed at call %p\n",
+ init_sequence, *init_fnc_ptr);
+ return -1;
+ }
+ }
+ return 0;
+}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
}
. = ALIGN(4);
}
- __bss_end__ = . ;
+ __bss_end = . ;
}
.bss (NOLOAD) : {
*(.*bss)
}
- __bss_end__ = .;
+ __bss_end = .;
}
ENTRY(_start)
-ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big");
+ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
__bss_start = .;
*(.bss)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
/DISCARD/ : { *(.bss*) }
__bss_start = .;
*(.bss)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
/DISCARD/ : { *(.bss*) }
__bss_start = .;
*(.bss)
. = ALIGN(4);
- __bss_end__ = .;
+ __bss_end = .;
}
}
. = ALIGN(8);
__bss_start = .;
.bss (NOLOAD) : { *(.*bss) }
- __bss_end__ = .;
+ __bss_end = .;
}
ENTRY(_start)
-ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big");
+ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
my @ignore = ();
my $help = 0;
my $configuration_file = ".checkpatch.conf";
+my $max_line_length = 80;
sub help {
my ($exitcode) = @_;
-f, --file treat FILE as regular source file
--subjective, --strict enable more subjective tests
--ignore TYPE(,TYPE2...) ignore various comma separated message types
+ --max-line-length=n set the maximum line length, if exceeded, warn
--show-types show the message "types" in the output
--root=PATH PATH to the kernel tree root
--no-summary suppress the per-file summary
'strict!' => \$check,
'ignore=s' => \@ignore,
'show-types!' => \$show_types,
+ 'max-line-length=i' => \$max_line_length,
'root=s' => \$root,
'summary!' => \$summary,
'mailback!' => \$mailback,
our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]};
our $Lval = qr{$Ident(?:$Member)*};
-our $Constant = qr{(?:[0-9]+|0x[0-9a-fA-F]+)[UL]*};
-our $Assignment = qr{(?:\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=)};
+our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
+our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
+our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?};
+our $Float = qr{$Float_hex|$Float_dec|$Float_int};
+our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*};
+our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=};
our $Compare = qr{<=|>=|==|!=|<|>};
our $Operators = qr{
<=|>=|==|!=|
our $Type;
our $Declare;
-our $UTF8 = qr {
- [\x09\x0A\x0D\x20-\x7E] # ASCII
- | [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte
+our $NON_ASCII_UTF8 = qr{
+ [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte
| \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs
| [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte
| \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates
| \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16
}x;
+our $UTF8 = qr{
+ [\x09\x0A\x0D\x20-\x7E] # ASCII
+ | $NON_ASCII_UTF8
+}x;
+
our $typeTypedefs = qr{(?x:
(?:__)?(?:u|s|be|le)(?:8|16|32|64)|
atomic_t
$NonptrType = qr{
(?:$Modifier\s+|const\s+)*
(?:
- (?:typeof|__typeof__)\s*\(\s*\**\s*$Ident\s*\)|
+ (?:typeof|__typeof__)\s*\([^\)]*\)|
(?:$typeTypedefs\b)|
(?:${all}\b)
)
}x;
$Type = qr{
$NonptrType
- (?:[\s\*]+\s*const|[\s\*]+|(?:\s*\[\s*\])+)?
+ (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)?
(?:\s+$Inline|\s+$Modifier)*
}x;
$Declare = qr{(?:$Storage\s+)?$Type};
}
build_types();
-our $match_balanced_parentheses = qr/(\((?:[^\(\)]+|(-1))*\))/;
our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*};
-our $LvalOrFunc = qr{($Lval)\s*($match_balanced_parentheses{0,1})\s*};
+
+# Using $balanced_parens, $LvalOrFunc, or $FuncArg
+# requires at least perl version v5.10.0
+# Any use must be runtime checked with $^V
+
+our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/;
+our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*};
+our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)};
sub deparenthesize {
my ($string) = @_;
$chk_signoff = 0 if ($file);
-my @dep_includes = ();
-my @dep_functions = ();
-my $removal = "Documentation/feature-removal-schedule.txt";
-if ($tree && -f "$root/$removal") {
- open(my $REMOVE, '<', "$root/$removal") ||
- die "$P: $removal: open failed - $!\n";
- while (<$REMOVE>) {
- if (/^Check:\s+(.*\S)/) {
- for my $entry (split(/[, ]+/, $1)) {
- if ($entry =~ m@include/(.*)@) {
- push(@dep_includes, $1);
-
- } elsif ($entry !~ m@/@) {
- push(@dep_functions, $entry);
- }
- }
- }
- }
- close($REMOVE);
-}
-
my @rawlines = ();
my @lines = ();
my $vname;
}
}
return 1;
- }
+}
sub parse_email {
my ($formatted_email) = @_;
if ($off >= $len) {
last;
}
+ if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) {
+ $level++;
+ $type = '#';
+ }
}
$p = $c;
$c = substr($blk, $off, 1);
last;
}
}
+ # Preprocessor commands end at the newline unless escaped.
+ if ($type eq '#' && $c eq "\n" && $p ne "\\") {
+ $level--;
+ $type = '';
+ $off++;
+ last;
+ }
$off++;
}
# We are truly at the end, so shuffle to the next line.
} elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') {
print "CAST($1)\n" if ($dbg_values > 1);
push(@av_paren_type, $type);
- $type = 'C';
+ $type = 'c';
} elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) {
print "DECLARE($1)\n" if ($dbg_values > 1);
case|
else|
asm|__asm__|
- do
+ do|
+ \#|
+ \#\#|
)(?:\s|$)|
^(?:typedef|struct|enum)\b
)}x;
}
}
+sub pos_last_openparen {
+ my ($line) = @_;
+
+ my $pos = 0;
+
+ my $opens = $line =~ tr/\(/\(/;
+ my $closes = $line =~ tr/\)/\)/;
+
+ my $last_openparen = 0;
+
+ if (($opens == 0) || ($closes >= $opens)) {
+ return -1;
+ }
+
+ my $len = length($line);
+
+ for ($pos = 0; $pos < $len; $pos++) {
+ my $string = substr($line, $pos);
+ if ($string =~ /^($FuncArg|$balanced_parens)/) {
+ $pos += length($1) - 1;
+ } elsif (substr($line, $pos, 1) eq '(') {
+ $last_openparen = $pos;
+ } elsif (index($string, '(') == -1) {
+ last;
+ }
+ }
+
+ return $last_openparen + 1;
+}
+
sub process {
my $filename = shift;
my $signoff = 0;
my $is_patch = 0;
+ my $in_header_lines = 1;
+ my $in_commit_log = 0; #Scanning lines before patch
+
+ my $non_utf8_charset = 0;
+
our @report = ();
our $cnt_lines = 0;
our $cnt_error = 0;
my %suppress_ifbraces;
my %suppress_whiletrailers;
my %suppress_export;
+ my $suppress_statement = 0;
+
+ my %camelcase = ();
# Pre-scan the patch sanitizing the lines.
# Pre-scan the patch looking for any __setup documentation.
%suppress_ifbraces = ();
%suppress_whiletrailers = ();
%suppress_export = ();
+ $suppress_statement = 0;
next;
# track the line number as we move through the hunk, note that
if ($line =~ /^diff --git.*?(\S+)$/) {
$realfile = $1;
$realfile =~ s@^([^/]*)/@@;
-
+ $in_commit_log = 0;
} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
$realfile = $1;
$realfile =~ s@^([^/]*)/@@;
+ $in_commit_log = 0;
$p1_prefix = $1;
if (!$file && $tree && $p1_prefix ne '' &&
# Check the patch for a signoff:
if ($line =~ /^\s*signed-off-by:/i) {
$signoff++;
+ $in_commit_log = 0;
}
# Check signature styles
- if ($line =~ /^(\s*)($signature_tags)(\s*)(.*)/) {
+ if (!$in_header_lines &&
+ $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) {
my $space_before = $1;
my $sign_off = $2;
my $space_after = $3;
my $email = $4;
my $ucfirst_sign_off = ucfirst(lc($sign_off));
+ if ($sign_off !~ /$signature_tags/) {
+ WARN("BAD_SIGN_OFF",
+ "Non-standard signature: $sign_off\n" . $herecurr);
+ }
if (defined $space_before && $space_before ne "") {
WARN("BAD_SIGN_OFF",
"Do not use whitespace before $ucfirst_sign_off\n" . $herecurr);
"Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr);
}
+# Check if it's the start of a commit log
+# (not a header line and we haven't seen the patch filename)
+ if ($in_header_lines && $realfile =~ /^$/ &&
+ $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) {
+ $in_header_lines = 0;
+ $in_commit_log = 1;
+ }
+
+# Check if there is UTF-8 in a commit log when a mail header has explicitly
+# declined it, i.e defined some charset where it is missing.
+ if ($in_header_lines &&
+ $rawline =~ /^Content-Type:.+charset="(.+)".*$/ &&
+ $1 !~ /utf-8/i) {
+ $non_utf8_charset = 1;
+ }
+
+ if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ &&
+ $rawline =~ /$NON_ASCII_UTF8/) {
+ WARN("UTF8_BEFORE_PATCH",
+ "8-bit UTF-8 used in possible commit log\n" . $herecurr);
+ }
+
# ignore non-hunk lines and lines being removed
next if (!$hunk_line || $line =~ /^-/);
# Only applies when adding the entry originally, after that we do not have
# sufficient context to determine whether it is indeed long enough.
if ($realfile =~ /Kconfig/ &&
- $line =~ /\+\s*(?:---)?help(?:---)?$/) {
+ $line =~ /.\s*config\s+/) {
my $length = 0;
my $cnt = $realcnt;
my $ln = $linenr + 1;
my $f;
+ my $is_start = 0;
my $is_end = 0;
- while ($cnt > 0 && defined $lines[$ln - 1]) {
+ for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) {
$f = $lines[$ln - 1];
$cnt-- if ($lines[$ln - 1] !~ /^-/);
$is_end = $lines[$ln - 1] =~ /^\+/;
- $ln++;
next if ($f =~ /^-/);
+
+ if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) {
+ $is_start = 1;
+ } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) {
+ $length = -1;
+ }
+
$f =~ s/^.//;
$f =~ s/#.*//;
$f =~ s/^\s+//;
$length++;
}
WARN("CONFIG_DESCRIPTION",
- "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_end && $length < 4);
- #print "is_end<$is_end> length<$length>\n";
+ "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4);
+ #print "is_start<$is_start> is_end<$is_end> length<$length>\n";
+ }
+
+# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig.
+ if ($realfile =~ /Kconfig/ &&
+ $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) {
+ WARN("CONFIG_EXPERIMENTAL",
+ "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+ }
+
+ if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&
+ ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) {
+ my $flag = $1;
+ my $replacement = {
+ 'EXTRA_AFLAGS' => 'asflags-y',
+ 'EXTRA_CFLAGS' => 'ccflags-y',
+ 'EXTRA_CPPFLAGS' => 'cppflags-y',
+ 'EXTRA_LDFLAGS' => 'ldflags-y',
+ };
+
+ WARN("DEPRECATED_VARIABLE",
+ "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag});
}
# check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
-#80 column limit
+#line length limit
if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ &&
$rawline !~ /^.\s*\*\s*\@$Ident\s/ &&
!($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ ||
$line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
- $length > 80)
+ $length > $max_line_length)
{
WARN("LONG_LINE",
- "line over 80 characters\n" . $herecurr);
+ "line over $max_line_length characters\n" . $herecurr);
+ }
+
+# Check for user-visible strings broken across lines, which breaks the ability
+# to grep for the string. Limited to strings used as parameters (those
+# following an open parenthesis), which almost completely eliminates false
+# positives, as well as warning only once per parameter rather than once per
+# line of the string. Make an exception when the previous string ends in a
+# newline (multiple lines in one string constant) or \n\t (common in inline
+# assembly to indent the instruction on the following line).
+ if ($line =~ /^\+\s*"/ &&
+ $prevline =~ /"\s*$/ &&
+ $prevline =~ /\(/ &&
+ $prevrawline !~ /\\n(?:\\t)*"\s*$/) {
+ WARN("SPLIT_STRING",
+ "quoted string split across lines\n" . $hereprev);
}
# check for spaces before a quoted newline
"please, no space before tabs\n" . $herevet);
}
+# check for && or || at the start of a line
+ if ($rawline =~ /^\+\s*(&&|\|\|)/) {
+ CHK("LOGICAL_CONTINUATIONS",
+ "Logical continuations should be on the previous line\n" . $hereprev);
+ }
+
+# check multi-line statement indentation matches previous line
+ if ($^V && $^V ge 5.10.0 &&
+ $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) {
+ $prevline =~ /^\+(\t*)(.*)$/;
+ my $oldindent = $1;
+ my $rest = $2;
+
+ my $pos = pos_last_openparen($rest);
+ if ($pos >= 0) {
+ $line =~ /^(\+| )([ \t]*)/;
+ my $newindent = $2;
+
+ my $goodtabindent = $oldindent .
+ "\t" x ($pos / 8) .
+ " " x ($pos % 8);
+ my $goodspaceindent = $oldindent . " " x $pos;
+
+ if ($newindent ne $goodtabindent &&
+ $newindent ne $goodspaceindent) {
+ CHK("PARENTHESIS_ALIGNMENT",
+ "Alignment should match open parenthesis\n" . $hereprev);
+ }
+ }
+ }
+
+ if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) {
+ CHK("SPACING",
+ "No space is necessary after a cast\n" . $hereprev);
+ }
+
+ if ($realfile =~ m@^(drivers/net/|net/)@ &&
+ $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
+ $prevrawline =~ /^\+[ \t]*$/) {
+ WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+ "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
+ }
+
+ if ($realfile =~ m@^(drivers/net/|net/)@ &&
+ $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */
+ $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/
+ $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/
+ $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */
+ WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+ "networking block comments put the trailing */ on a separate line\n" . $herecurr);
+ }
+
# check for spaces at the beginning of a line.
# Exceptions:
# 1) within comments
# check we are in a valid C source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c)$/);
+# discourage the addition of CONFIG_EXPERIMENTAL in #if(def).
+ if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) {
+ WARN("CONFIG_EXPERIMENTAL",
+ "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+ }
+
# check for RCS/CVS revision markers
if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) {
WARN("CVS_KEYWORD",
"use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
}
+# check for old HOTPLUG __dev<foo> section markings
+ if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) {
+ WARN("HOTPLUG_SECTION",
+ "Using $1 is unnecessary\n" . $herecurr);
+ }
+
# Check for potential 'bare' types
my ($stat, $cond, $line_nr_next, $remain_next, $off_next,
$realline_next);
- if ($realcnt && $line =~ /.\s*\S/) {
+#print "LINE<$line>\n";
+ if ($linenr >= $suppress_statement &&
+ $realcnt && $line =~ /.\s*\S/) {
($stat, $cond, $line_nr_next, $remain_next, $off_next) =
ctx_statement_block($linenr, $realcnt, 0);
$stat =~ s/\n./\n /g;
$cond =~ s/\n./\n /g;
+#print "linenr<$linenr> <$stat>\n";
+ # If this statement has no statement boundaries within
+ # it there is no point in retrying a statement scan
+ # until we hit end of it.
+ my $frag = $stat; $frag =~ s/;+\s*$//;
+ if ($frag !~ /(?:{|;)/) {
+#print "skip<$line_nr_next>\n";
+ $suppress_statement = $line_nr_next;
+ }
+
# Find the real next line.
$realline_next = $line_nr_next;
if (defined $realline_next &&
my $pre_ctx = "$1$2";
my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);
+
+ if ($line =~ /^\+\t{6,}/) {
+ WARN("DEEP_INDENTATION",
+ "Too many leading tabs - consider code refactoring\n" . $herecurr);
+ }
+
my $ctx_cnt = $realcnt - $#ctx - 1;
my $ctx = join("\n", @ctx);
# Check relative indent for conditionals and blocks.
if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
+ ($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+ ctx_statement_block($linenr, $realcnt, 0)
+ if (!defined $stat);
my ($s, $c) = ($stat, $cond);
substr($s, 0, length($c), '');
my $path = $1;
if ($path =~ m{//}) {
ERROR("MALFORMED_INCLUDE",
- "malformed #include filename\n" .
- $herecurr);
+ "malformed #include filename\n" . $herecurr);
+ }
+ if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) {
+ ERROR("UAPI_INCLUDE",
+ "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr);
}
}
# XXX(foo);
# EXPORT_SYMBOL(something_foo);
my $name = $1;
- if ($stat =~ /^.([A-Z_]+)\s*\(\s*($Ident)/ &&
+ if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ &&
$name =~ /^${Ident}_$2/) {
#print "FOO C name<$name>\n";
$suppress_export{$realline_next} = 1;
# * goes on variable not on type
# (char*[ const])
- if ($line =~ m{\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\)}) {
- my ($from, $to) = ($1, $1);
+ while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) {
+ #print "AA<$1>\n";
+ my ($from, $to) = ($2, $2);
# Should start with a space.
$to =~ s/^(\S)/ $1/;
ERROR("POINTER_LOCATION",
"\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr);
}
- } elsif ($line =~ m{\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident)}) {
- my ($from, $to, $ident) = ($1, $1, $2);
+ }
+ while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) {
+ #print "BB<$1>\n";
+ my ($from, $to, $ident) = ($2, $2, $3);
# Should start with a space.
$to =~ s/^(\S)/ $1/;
}
}
+ if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) {
+ my $orig = $1;
+ my $level = lc($orig);
+ $level = "warn" if ($level eq "warning");
+ my $level2 = $level;
+ $level2 = "dbg" if ($level eq "debug");
+ WARN("PREFER_PR_LEVEL",
+ "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr);
+ }
+
+ if ($line =~ /\bpr_warning\s*\(/) {
+ WARN("PREFER_PR_LEVEL",
+ "Prefer pr_warn(... to pr_warning(...\n" . $herecurr);
+ }
+
+ if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
+ my $orig = $1;
+ my $level = lc($orig);
+ $level = "warn" if ($level eq "warning");
+ $level = "dbg" if ($level eq "debug");
+ WARN("PREFER_DEV_LEVEL",
+ "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr);
+ }
+
# function brace can't be on same line, except for #defines of do while,
# or if closed on same line
if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and
my ($where, $prefix) = ($-[1], $1);
if ($prefix !~ /$Type\s+$/ &&
($where != 0 || $prefix !~ /^.\s+$/) &&
- $prefix !~ /{\s+$/) {
+ $prefix !~ /[{,]\s+$/) {
ERROR("BRACKET_SPACE",
"space prohibited before open square bracket '['\n" . $herecurr);
}
"space prohibited between function name and open parenthesis '('\n" . $herecurr);
}
}
+
+# check for whitespace before a non-naked semicolon
+ if ($line =~ /^\+.*\S\s+;/) {
+ CHK("SPACING",
+ "space prohibited before semicolon\n" . $herecurr);
+ }
+
# Check operator spacing.
if (!($line=~/\#\s*include/)) {
my $ops = qr{
# Flatten any parentheses
$value =~ s/\(/ \(/g;
$value =~ s/\)/\) /g;
- while ($value =~ s/\[[^\{\}]*\]/1/ ||
+ while ($value =~ s/\[[^\[\]]*\]/1/ ||
$value !~ /(?:$Ident|-?$Constant)\s*
$Compare\s*
(?:$Ident|-?$Constant)/x &&
}
}
-# typecasts on min/max could be min_t/max_t
- if ($line =~ /^\+(?:.*?)\b(min|max)\s*\($Typecast{0,1}($LvalOrFunc)\s*,\s*$Typecast{0,1}($LvalOrFunc)\s*\)/) {
- if (defined $2 || defined $8) {
- my $call = $1;
- my $cast1 = deparenthesize($2);
- my $arg1 = $3;
- my $cast2 = deparenthesize($8);
- my $arg2 = $9;
- my $cast;
-
- if ($cast1 ne "" && $cast2 ne "") {
- $cast = "$cast1 or $cast2";
- } elsif ($cast1 ne "") {
- $cast = $cast1;
- } else {
- $cast = $cast2;
- }
- WARN("MINMAX",
- "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . $herecurr);
- }
- }
-
# Need a space before open parenthesis after if, while etc
if ($line=~/\b(if|while|for|switch)\(/) {
ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr);
# Check for illegal assignment in if conditional -- and check for trailing
# statements after the conditional.
if ($line =~ /do\s*(?!{)/) {
+ ($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+ ctx_statement_block($linenr, $realcnt, 0)
+ if (!defined $stat);
my ($stat_next) = ctx_statement_block($line_nr_next,
$remain_next, $off_next);
$stat_next =~ s/\n./\n /g;
}
}
-#studly caps, commented out until figure out how to distinguish between use of existing and adding new
-# if (($line=~/[\w_][a-z\d]+[A-Z]/) and !($line=~/print/)) {
-# print "No studly caps, use _\n";
-# print "$herecurr";
-# $clean = 0;
-# }
+#CamelCase
+ while ($line =~ m{($Constant|$Lval)}g) {
+ my $var = $1;
+ if ($var !~ /$Constant/ &&
+ $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ &&
+ $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
+ !defined $camelcase{$var}) {
+ $camelcase{$var} = 1;
+ WARN("CAMELCASE",
+ "Avoid CamelCase: <$var>\n" . $herecurr);
+ }
+ }
#no spaces allowed after \ in define
if ($line=~/\#\s*define.*\\\s$/) {
my $cnt = $realcnt;
my ($off, $dstat, $dcond, $rest);
my $ctx = '';
-
- my $args = defined($1);
-
- # Find the end of the macro and limit our statement
- # search to that.
- while ($cnt > 0 && defined $lines[$ln - 1] &&
- $lines[$ln - 1] =~ /^(?:-|..*\\$)/)
- {
- $ctx .= $rawlines[$ln - 1] . "\n";
- $cnt-- if ($lines[$ln - 1] !~ /^-/);
- $ln++;
- }
- $ctx .= $rawlines[$ln - 1];
-
($dstat, $dcond, $ln, $cnt, $off) =
- ctx_statement_block($linenr, $ln - $linenr + 1, 0);
+ ctx_statement_block($linenr, $realcnt, 0);
+ $ctx = $dstat;
#print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n";
#print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n";
- # Extract the remainder of the define (if any) and
- # rip off surrounding spaces, and trailing \'s.
- $rest = '';
- while ($off != 0 || ($cnt > 0 && $rest =~ /\\\s*$/)) {
- #print "ADDING cnt<$cnt> $off <" . substr($lines[$ln - 1], $off) . "> rest<$rest>\n";
- if ($off != 0 || $lines[$ln - 1] !~ /^-/) {
- $rest .= substr($lines[$ln - 1], $off) . "\n";
- $cnt--;
- }
- $ln++;
- $off = 0;
- }
- $rest =~ s/\\\n.//g;
- $rest =~ s/^\s*//s;
- $rest =~ s/\s*$//s;
-
- # Clean up the original statement.
- if ($args) {
- substr($dstat, 0, length($dcond), '');
- } else {
- $dstat =~ s/^.\s*\#\s*define\s+$Ident\s*//;
- }
+ $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//;
$dstat =~ s/$;//g;
$dstat =~ s/\\\n.//g;
$dstat =~ s/^\s*//s;
# Flatten any parentheses and braces
while ($dstat =~ s/\([^\(\)]*\)/1/ ||
$dstat =~ s/\{[^\{\}]*\}/1/ ||
- $dstat =~ s/\[[^\{\}]*\]/1/)
+ $dstat =~ s/\[[^\[\]]*\]/1/)
+ {
+ }
+
+ # Flatten any obvious string concatentation.
+ while ($dstat =~ s/("X*")\s*$Ident/$1/ ||
+ $dstat =~ s/$Ident\s*("X*")/$1/)
{
}
my $exceptions = qr{
$Declare|
module_param_named|
- MODULE_PARAM_DESC|
+ MODULE_PARM_DESC|
DECLARE_PER_CPU|
DEFINE_PER_CPU|
__typeof__\(|
^\"|\"$
}x;
#print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
- if ($rest ne '' && $rest ne ',') {
- if ($rest !~ /while\s*\(/ &&
- $dstat !~ /$exceptions/)
- {
- ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
- "Macros with multiple statements should be enclosed in a do - while loop\n" . "$here\n$ctx\n");
+ if ($dstat ne '' &&
+ $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(),
+ $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo();
+ $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo
+ $dstat !~ /^'X'$/ && # character constants
+ $dstat !~ /$exceptions/ &&
+ $dstat !~ /^\.$Ident\s*=/ && # .foo =
+ $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...)
+ $dstat !~ /^for\s*$Constant$/ && # for (...)
+ $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar()
+ $dstat !~ /^do\s*{/ && # do {...
+ $dstat !~ /^\({/) # ({...
+ {
+ $ctx =~ s/\n*$//;
+ my $herectx = $here . "\n";
+ my $cnt = statement_rawlines($ctx);
+
+ for (my $n = 0; $n < $cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";
}
- } elsif ($ctx !~ /;/) {
- if ($dstat ne '' &&
- $dstat !~ /^(?:$Ident|-?$Constant)$/ &&
- $dstat !~ /$exceptions/ &&
- $dstat !~ /^\.$Ident\s*=/ &&
- $dstat =~ /$Operators/)
- {
+ if ($dstat =~ /;/) {
+ ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
+ "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx");
+ } else {
ERROR("COMPLEX_MACRO",
- "Macros with complex values should be enclosed in parenthesis\n" . "$here\n$ctx\n");
+ "Macros with complex values should be enclosed in parenthesis\n" . "$herectx");
+ }
+ }
+
+# check for line continuations outside of #defines, preprocessor #, and asm
+
+ } else {
+ if ($prevline !~ /^..*\\$/ &&
+ $line !~ /^\+\s*\#.*\\$/ && # preprocessor
+ $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm
+ $line =~ /^\+.*\\$/) {
+ WARN("LINE_CONTINUATIONS",
+ "Avoid unnecessary line continuations\n" . $herecurr);
+ }
+ }
+
+# do {} while (0) macro tests:
+# single-statement macros do not need to be enclosed in do while (0) loop,
+# macro should not end with a semicolon
+ if ($^V && $^V ge 5.10.0 &&
+ $realfile !~ m@/vmlinux.lds.h$@ &&
+ $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) {
+ my $ln = $linenr;
+ my $cnt = $realcnt;
+ my ($off, $dstat, $dcond, $rest);
+ my $ctx = '';
+ ($dstat, $dcond, $ln, $cnt, $off) =
+ ctx_statement_block($linenr, $realcnt, 0);
+ $ctx = $dstat;
+
+ $dstat =~ s/\\\n.//g;
+
+ if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) {
+ my $stmts = $2;
+ my $semis = $3;
+
+ $ctx =~ s/\n*$//;
+ my $cnt = statement_rawlines($ctx);
+ my $herectx = $here . "\n";
+
+ for (my $n = 0; $n < $cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";
+ }
+
+ if (($stmts =~ tr/;/;/) == 1 &&
+ $stmts !~ /^\s*(if|while|for|switch)\b/) {
+ WARN("SINGLE_STATEMENT_DO_WHILE_MACRO",
+ "Single statement macros should not use a do {} while (0) loop\n" . "$herectx");
+ }
+ if (defined $semis && $semis ne "") {
+ WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON",
+ "do {} while (0) macros should not be semicolon terminated\n" . "$herectx");
}
}
}
#print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n";
#print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n";
if ($#chunks > 0 && $level == 0) {
- my $allowed = 0;
+ my @allowed = ();
+ my $allow = 0;
my $seen = 0;
my $herectx = $here . "\n";
my $ln = $linenr - 1;
my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s);
my $offset = statement_rawlines($whitespace) - 1;
+ $allowed[$allow] = 0;
#print "COND<$cond> whitespace<$whitespace> offset<$offset>\n";
# We have looked at and allowed this specific line.
$seen++ if ($block =~ /^\s*{/);
- #print "cond<$cond> block<$block> allowed<$allowed>\n";
+ #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n";
if (statement_lines($cond) > 1) {
#print "APW: ALLOWED: cond<$cond>\n";
- $allowed = 1;
+ $allowed[$allow] = 1;
}
if ($block =~/\b(?:if|for|while)\b/) {
#print "APW: ALLOWED: block<$block>\n";
- $allowed = 1;
+ $allowed[$allow] = 1;
}
if (statement_block_size($block) > 1) {
#print "APW: ALLOWED: lines block<$block>\n";
- $allowed = 1;
+ $allowed[$allow] = 1;
}
+ $allow++;
}
- if ($seen && !$allowed) {
- WARN("BRACES",
- "braces {} are not necessary for any arm of this statement\n" . $herectx);
+ if ($seen) {
+ my $sum_allowed = 0;
+ foreach (@allowed) {
+ $sum_allowed += $_;
+ }
+ if ($sum_allowed == 0) {
+ WARN("BRACES",
+ "braces {} are not necessary for any arm of this statement\n" . $herectx);
+ } elsif ($sum_allowed != $allow &&
+ $seen != $allow) {
+ CHK("BRACES",
+ "braces {} should be used on all arms of this statement\n" . $herectx);
+ }
}
}
}
}
}
if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) {
- my $herectx = $here . "\n";;
+ my $herectx = $here . "\n";
my $cnt = statement_rawlines($block);
for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";;
+ $herectx .= raw_line($linenr, $n) . "\n";
}
WARN("BRACES",
}
}
-# don't include deprecated include files (uses RAW line)
- for my $inc (@dep_includes) {
- if ($rawline =~ m@^.\s*\#\s*include\s*\<$inc>@) {
- ERROR("DEPRECATED_INCLUDE",
- "Don't use <$inc>: see Documentation/feature-removal-schedule.txt\n" . $herecurr);
- }
+# check for unnecessary blank lines around braces
+ if (($line =~ /^..*}\s*$/ && $prevline =~ /^.\s*$/)) {
+ CHK("BRACES",
+ "Blank lines aren't necessary before a close brace '}'\n" . $hereprev);
}
-
-# don't use deprecated functions
- for my $func (@dep_functions) {
- if ($line =~ /\b$func\b/) {
- ERROR("DEPRECATED_FUNCTION",
- "Don't use $func(): see Documentation/feature-removal-schedule.txt\n" . $herecurr);
- }
+ if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
+ CHK("BRACES",
+ "Blank lines aren't necessary after an open brace '{'\n" . $hereprev);
}
# no volatiles please
$herecurr);
}
-# check for needless kfree() checks
- if ($prevline =~ /\bif\s*\(([^\)]*)\)/) {
- my $expr = $1;
- if ($line =~ /\bkfree\(\Q$expr\E\);/) {
- WARN("NEEDLESS_KFREE",
- "kfree(NULL) is safe this check is probably not required\n" . $hereprev);
- }
- }
-# check for needless usb_free_urb() checks
- if ($prevline =~ /\bif\s*\(([^\)]*)\)/) {
- my $expr = $1;
- if ($line =~ /\busb_free_urb\(\Q$expr\E\);/) {
- WARN("NEEDLESS_USB_FREE_URB",
- "usb_free_urb(NULL) is safe this check is probably not required\n" . $hereprev);
+# check for needless "if (<foo>) fn(<foo>)" uses
+ if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) {
+ my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;';
+ if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) {
+ WARN('NEEDLESS_IF',
+ "$1(NULL) is safe this check is probably not required\n" . $hereprev);
}
}
# prefer usleep_range over udelay
- if ($line =~ /\budelay\s*\(\s*(\w+)\s*\)/) {
+ if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) {
# ignore udelay's < 10, however
- if (! (($1 =~ /(\d+)/) && ($1 < 10)) ) {
+ if (! ($1 < 10) ) {
CHK("USLEEP_RANGE",
"usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line);
}
"__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
}
+# Check for __attribute__ format(printf, prefer __printf
+ if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
+ WARN("PREFER_PRINTF",
+ "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr);
+ }
+
+# Check for __attribute__ format(scanf, prefer __scanf
+ if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
+ WARN("PREFER_SCANF",
+ "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr);
+ }
+
# check for sizeof(&)
if ($line =~ /\bsizeof\s*\(\s*\&/) {
WARN("SIZEOF_ADDRESS",
"sizeof(& should be avoided\n" . $herecurr);
}
+# check for sizeof without parenthesis
+ if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) {
+ WARN("SIZEOF_PARENTHESIS",
+ "sizeof $1 should be sizeof($1)\n" . $herecurr);
+ }
+
# check for line continuations in quoted strings with odd counts of "
if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
WARN("LINE_CONTINUATIONS",
"Avoid line continuations in quoted strings\n" . $herecurr);
}
+# check for struct spinlock declarations
+ if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) {
+ WARN("USE_SPINLOCK_T",
+ "struct spinlock should be spinlock_t\n" . $herecurr);
+ }
+
+# Check for misused memsets
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) {
+
+ my $ms_addr = $2;
+ my $ms_val = $7;
+ my $ms_size = $12;
+
+ if ($ms_size =~ /^(0x|)0$/i) {
+ ERROR("MEMSET",
+ "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n");
+ } elsif ($ms_size =~ /^(0x|)1$/i) {
+ WARN("MEMSET",
+ "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n");
+ }
+ }
+
+# typecasts on min/max could be min_t/max_t
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) {
+ if (defined $2 || defined $7) {
+ my $call = $1;
+ my $cast1 = deparenthesize($2);
+ my $arg1 = $3;
+ my $cast2 = deparenthesize($7);
+ my $arg2 = $8;
+ my $cast;
+
+ if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) {
+ $cast = "$cast1 or $cast2";
+ } elsif ($cast1 ne "") {
+ $cast = $cast1;
+ } else {
+ $cast = $cast2;
+ }
+ WARN("MINMAX",
+ "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n");
+ }
+ }
+
+# check usleep_range arguments
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) {
+ my $min = $1;
+ my $max = $7;
+ if ($min eq $max) {
+ WARN("USLEEP_RANGE",
+ "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+ } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ &&
+ $min > $max) {
+ WARN("USLEEP_RANGE",
+ "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+ }
+ }
+
# check for new externs in .c files.
if ($realfile =~ /\.c$/ && defined $stat &&
$stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
"unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
}
+# check for alloc argument mismatch
+ if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) {
+ WARN("ALLOC_ARRAY_ARGS",
+ "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
+ }
+
# check for multiple semicolons
if ($line =~ /;\s*;\s*$/) {
- WARN("ONE_SEMICOLON",
- "Statements terminations use 1 semicolon\n" . $herecurr);
+ WARN("ONE_SEMICOLON",
+ "Statements terminations use 1 semicolon\n" . $herecurr);
}
-# check for whitespace before semicolon - not allowed at end-of-line
- if ($line =~ /\s+;$/) {
- WARN("SPACEBEFORE_SEMICOLON",
- "Whitespace before semicolon\n" . $herecurr);
+# check for switch/default statements without a break;
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) {
+ my $ctx = '';
+ my $herectx = $here . "\n";
+ my $cnt = statement_rawlines($stat);
+ for (my $n = 0; $n < $cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";
+ }
+ WARN("DEFAULT_NO_BREAK",
+ "switch default: should use break\n" . $herectx);
}
# check for gcc specific __FUNCTION__
"__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr);
}
+# check for use of yield()
+ if ($line =~ /\byield\s*\(\s*\)/) {
+ WARN("YIELD",
+ "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr);
+ }
+
# check for semaphores initialized locked
if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
WARN("CONSIDER_COMPLETION",
"consider using a completion\n" . $herecurr);
-
}
-# recommend kstrto* over simple_strto*
- if ($line =~ /\bsimple_(strto.*?)\s*\(/) {
+
+# recommend kstrto* over simple_strto* and strict_strto*
+ if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) {
WARN("CONSIDER_KSTRTO",
- "consider using kstrto* in preference to simple_$1\n" . $herecurr);
+ "$1 is obsolete, use k$3 instead\n" . $herecurr);
}
+
# check for __initcall(), use device_initcall() explicitly please
if ($line =~ /^.\s*__initcall\s*\(/) {
WARN("USE_DEVICE_INITCALL",
"please use device_initcall() instead of __initcall()\n" . $herecurr);
}
+
# check for various ops structs, ensure they are const.
my $struct_ops = qr{acpi_dock_ops|
address_space_operations|
WARN("EXPORTED_WORLD_WRITABLE",
"Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
}
-
- # Check for memset with swapped arguments
- if ($line =~ /memset.*\,(\ |)(0x|)0(\ |0|)\);/) {
- ERROR("MEMSET",
- "memset size is 3rd argument, not the second.\n" . $herecurr);
- }
}
# If we have no input at all, then there is nothing to report on
}
if ($quiet == 0) {
+
+ if ($^V lt 5.10.0) {
+ print("NOTE: perl $^V is not modern enough to detect all possible issues.\n");
+ print("An upgrade to at least perl v5.10.0 is suggested.\n\n");
+ }
+
# If there were whitespace errors which cleanpatch can fix
# then suggest that.
if ($rpt_cleaners) {
}
}
- if (keys %ignore_type) {
+ if ($quiet == 0 && keys %ignore_type) {
print "NOTE: Ignored message types:";
foreach my $ignore (sort keys %ignore_type) {
print " $ignore";
}
- print "\n";
- print "\n" if ($quiet == 0);
+ print "\n\n";
}
if ($clean == 1 && $quiet == 0) {
in the root directory of the U-Boot distribution. For example,
make HOSTCC=arm-linux-gcc env
-For the run-time utiltity configuration uncomment the line
+For the run-time utility configuration uncomment the line
#define CONFIG_FILE "/etc/fw_env.config"
in fw_env.h.
#define DEVICE2_ESIZE 0x4000
#define DEVICE2_ENVSECTORS 2
-Un-define HAVE_REDUND, if you want to use the utlities on a system
+Un-define HAVE_REDUND, if you want to use the utilities on a system
that does not have support for redundant environment enabled.
If HAVE_REDUND is undefined, DEVICE2_NAME is ignored,
as is ENV2_SIZE and DEVICE2_ESIZE.
erase.start = blockstart;
ioctl (fd, MEMUNLOCK, &erase);
-
- /* Dataflash does not need an explicit erase cycle */
- if (mtd_type != MTD_DATAFLASH)
+ /* These do not need an explicit erase cycle */
+ if (mtd_type != MTD_ABSENT &&
+ mtd_type != MTD_DATAFLASH)
if (ioctl (fd, MEMERASE, &erase) != 0) {
fprintf (stderr, "MTD erase error on %s: %s\n",
DEVNAME (dev),
static int flash_read (int fd)
{
struct mtd_info_user mtdinfo;
+ struct stat st;
int rc;
- rc = ioctl (fd, MEMGETINFO, &mtdinfo);
+ rc = fstat(fd, &st);
if (rc < 0) {
- perror ("Cannot get MTD information");
+ fprintf(stderr, "Cannot stat the file %s\n",
+ DEVNAME(dev_current));
return -1;
}
- if (mtdinfo.type != MTD_NORFLASH &&
- mtdinfo.type != MTD_NANDFLASH &&
- mtdinfo.type != MTD_DATAFLASH) {
- fprintf (stderr, "Unsupported flash type %u\n", mtdinfo.type);
- return -1;
+ if (S_ISCHR(st.st_mode)) {
+ rc = ioctl(fd, MEMGETINFO, &mtdinfo);
+ if (rc < 0) {
+ fprintf(stderr, "Cannot get MTD information for %s\n",
+ DEVNAME(dev_current));
+ return -1;
+ }
+ if (mtdinfo.type != MTD_NORFLASH &&
+ mtdinfo.type != MTD_NANDFLASH &&
+ mtdinfo.type != MTD_DATAFLASH) {
+ fprintf (stderr, "Unsupported flash type %u on %s\n",
+ mtdinfo.type, DEVNAME(dev_current));
+ return -1;
+ }
+ } else {
+ memset(&mtdinfo, 0, sizeof(mtdinfo));
+ mtdinfo.type = MTD_ABSENT;
}
DEVTYPE(dev_current) = mtdinfo.type;
# NAND example
#/dev/mtd0 0x4000 0x4000 0x20000 2
+
+# Block device example
+#/dev/mmcblk0 0xc0000 0x20000
projects / platform / kernel / u-boot.git / commitdiff