VERSION = 2019
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
#include <netdev.h>
#include <spl.h>
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/sys_proto.h>
#include <netdev.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int cpu_mmc_init(bd_t *bis)
{
return fsl_esdhc_mmc_init(bis);
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
return 0;
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
#endif
return 0;
imx6-apalis.dtb \
imx6q-display5.dtb \
imx6q-logicpd.dtb \
- imx6q-novena.dtb
-
-dtb-$(CONFIG_TARGET_TBS2910) += \
+ imx6q-novena.dtb \
imx6q-tbs2910.dtb
dtb-$(CONFIG_MX6QDL) += \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
imx6dl-mamoj.dtb \
+ imx6dl-sabreauto.dtb \
+ imx6dl-sabresd.dtb \
+ imx6dl-wandboard-revb1.dtb \
imx6q-cm-fx6.dtb \
imx6q-icore.dtb \
imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
imx6q-sabreauto.dtb \
imx6q-sabresd.dtb \
- imx6dl-sabreauto.dtb \
- imx6dl-sabresd.dtb \
+ imx6q-wandboard-revb1.dtb \
imx6qp-sabreauto.dtb \
- imx6qp-sabresd.dtb
-
-dtb-$(CONFIG_TARGET_WANDBOARD) += \
- imx6dl-wandboard-revb1.dtb
+ imx6qp-sabresd.dtb \
+ imx6qp-wandboard-revd1.dtb
dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
at91-vinco.dtb
dtb-$(CONFIG_ARCH_BCM283X) += \
- bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-a.dtb \
+ bcm2835-rpi-a-plus.dtb \
+ bcm2835-rpi-b.dtb \
bcm2835-rpi-b-plus.dtb \
bcm2835-rpi-b-rev2.dtb \
- bcm2835-rpi-b.dtb \
- bcm2835-rpi-zero-w.dtb \
+ bcm2835-rpi-cm1-io1.dtb \
+ bcm2835-rpi-zero.dtb \
+ bcm2835-rpi-zero-w.dtb\
bcm2836-rpi-2-b.dtb \
- bcm2837-rpi-3-b.dtb
+ bcm2837-rpi-3-a-plus.dtb \
+ bcm2837-rpi-3-b.dtb \
+ bcm2837-rpi-3-b-plus.dtb \
+ bcm2837-rpi-cm3-io3.dtb
dtb-$(CONFIG_ARCH_BCM63158) += \
bcm963158.dtb
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
leds {
act {
- gpios = <&gpio 47 0>;
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
- gpios = <&gpio 35 0>;
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
- gpio-line-names = "SDA0",
- "SCL0",
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
leds {
act {
- gpios = <&gpio 16 1>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
leds {
act {
- gpios = <&gpio 47 0>;
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
- gpios = <&gpio 35 0>;
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
- gpio-line-names = "SDA0",
- "SCL0",
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
leds {
act {
- gpios = <&gpio 16 1>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};
};
&hdmi {
- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
+ status = "okay";
};
&uart0 {
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
leds {
act {
- gpios = <&gpio 16 1>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2835-rpi-cm1.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ compatible = "raspberrypi,compute-module", "brcm,bcm2835";
+ model = "Raspberry Pi Compute Module IO board rev1";
+};
+
+&gpio {
+ /*
+ * This is based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "GPIO0",
+ "GPIO1",
+ "GPIO2",
+ "GPIO3",
+ "GPIO4",
+ "GPIO5",
+ "GPIO6",
+ "GPIO7",
+ "GPIO8",
+ "GPIO9",
+ "GPIO10",
+ "GPIO11",
+ "GPIO12",
+ "GPIO13",
+ "GPIO14",
+ "GPIO15",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "GPIO28",
+ "GPIO29",
+ "GPIO30",
+ "GPIO31",
+ "GPIO32",
+ "GPIO33",
+ "GPIO34",
+ "GPIO35",
+ "GPIO36",
+ "GPIO37",
+ "GPIO38",
+ "GPIO39",
+ "GPIO40",
+ "GPIO41",
+ "GPIO42",
+ "GPIO43",
+ "GPIO44",
+ "GPIO45",
+ "HDMI_HPD_N",
+ /* Also used as ACT LED */
+ "EMMC_EN_N",
+ /* Used by eMMC */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0>;
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+
+/ {
+ leds {
+ act {
+ gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_3v3: fixed-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_1v8: fixed-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+};
+
+&sdhost {
+ non-removable;
+ vmmc-supply = <®_3v3>;
+ vqmmc-supply = <®_1v8>;
+};
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
+ */
+
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
-#include "bcm283x-rpi-smsc9512.dtsi"
-#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-usb-otg.dtsi"
/ {
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
model = "Raspberry Pi Zero W";
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
leds {
act {
- gpios = <&gpio 47 0>;
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+ };
};
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_gpio14>;
- status = "okay";
+&gpio {
+ /*
+ * This is based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "CAM_GPIO1", /* GPIO40 */
+ "WL_ON", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "WIFI_CLK", /* GPIO43 */
+ "CAM_GPIO0", /* GPIO44 */
+ "BT_ON", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED_N",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Wahren <stefan.wahren@i2se.com>
+ */
+
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-usb-otg.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-zero", "brcm,bcm2835";
+ model = "Raspberry Pi Zero";
+
+ leds {
+ act {
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&gpio {
+ /*
+ * This is based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "CAM_GPIO1", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "NC", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "NC", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED_N",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
+
+ /* I2S interface */
+ i2s_alt0: i2s_alt0 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
#include <dt-bindings/power/raspberrypi-power.h>
/ {
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x10000000>;
};
soc {
firmware: firmware {
- compatible = "raspberrypi,bcm2835-firmware";
+ compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
mboxes = <&mailbox>;
};
firmware = <&firmware>;
#power-domain-cells = <1>;
};
+
+ vchiq: mailbox@7e00b840 {
+ compatible = "brcm,bcm2835-vchiq";
+ reg = <0x7e00b840 0x3c>;
+ interrupts = <0 2>;
+ };
};
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio48>;
- status = "okay";
bus-width = <4>;
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
- bus-width = <4>;
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
status = "okay";
+ bus-width = <4>;
};
&usb {
power-domains = <&power RPI_POWER_DOMAIN_USB>;
};
-&v3d {
- power-domains = <&power RPI_POWER_DOMAIN_V3D>;
-};
-
&hdmi {
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
+// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
/ {
soc {
ranges = <0x7e000000 0x20000000 0x02000000>;
dma-ranges = <0x40000000 0x00000000 0x20000000>;
+ };
- arm-pmu {
- compatible = "arm,arm1176-pmu";
- };
+ arm-pmu {
+ compatible = "arm,arm1176-pmu";
};
};
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2836.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
model = "Raspberry Pi 2 Model B";
- memory {
+ memory@0 {
reg = <0 0x40000000>;
};
leds {
act {
- gpios = <&gpio 47 0>;
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
- gpios = <&gpio 35 0>;
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
&gpio {
+ /*
+ * Taken from rpi_SCH_2b_1p2_reduced.pdf and
+ * the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "", /* GPIO30 */
+ "LAN_RUN",
+ "CAM_GPIO1",
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "PWR_LOW_N",
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "USB_LIMIT",
+ "", /* GPIO39 */
+ "PWM0_OUT",
+ "CAM_GPIO0",
+ "SMPS_SCL",
+ "SMPS_SDA",
+ "ETHCLK",
+ "PWM1_OUT",
+ "HDMI_HPD_N",
+ "STATUS_LED",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm2835-rpi.dtsi"
+
+&vchiq {
+ compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq";
+};
+// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
/ {
<0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
- local_intc: local_intc {
+ local_intc: local_intc@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
};
+ };
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupt-parent = <&local_intc>;
- interrupts = <9>;
- };
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupt-parent = <&local_intc>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&local_intc>;
- interrupts = <0>, // PHYS_SECURE_PPI
- <1>, // PHYS_NONSECURE_PPI
- <3>, // VIRT_PPI
- <2>; // HYP_PPI
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
+ <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
+ <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
+ <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
always-on;
};
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-parent = <&local_intc>;
- interrupts = <8>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
&cpu_thermal {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2837.dtsi"
+#include "bcm2836-rpi.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
+ model = "Raspberry Pi 3 Model A+";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ reg = <0 0x20000000>;
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&firmware {
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "",
+ "BT_WL_ON",
+ "STATUS_LED_R",
+ "",
+ "",
+ "CAM_GPIO0",
+ "CAM_GPIO1",
+ "";
+ status = "okay";
+ };
+};
+
+&gpio {
+ /*
+ * This is mostly based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD1",
+ "RXD1",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "HDMI_HPD_N",
+ "STATUS_LED_G",
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
+ "PWM0_OUT",
+ "PWM1_OUT",
+ "", /* GPIO42 */
+ "WIFI_CLK",
+ "SDA0",
+ "SCL0",
+ "SMPS_SCL",
+ "SMPS_SDA",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
+ status = "okay";
+};
+
+/*
+ * SDHCI is used to control the SDIO for wireless
+ *
+ * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
+ * by a single GPIO. We can't give GPIO control to one of the drivers,
+ * otherwise the other part would get unexpectedly disturbed.
+ */
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ status = "okay";
+ bus-width = <4>;
+ non-removable;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SDHOST is used to drive the SD card */
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ status = "okay";
+ bus-width = <4>;
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ };
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2837.dtsi"
+#include "bcm2836-rpi.dtsi"
+#include "bcm283x-rpi-lan7515.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
+ model = "Raspberry Pi 3 Model B+";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ reg = <0 0x40000000>;
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&firmware {
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "STATUS_LED_R",
+ "LAN_RUN",
+ "",
+ "CAM_GPIO0",
+ "CAM_GPIO1",
+ "";
+ status = "okay";
+ };
+};
+
+&gpio {
+ /*
+ * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and
+ * the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD1",
+ "RXD1",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "HDMI_HPD_N",
+ "STATUS_LED_G",
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
+ "PWM0_OUT",
+ "PWM1_OUT",
+ "ETHCLK",
+ "WIFI_CLK",
+ "SDA0",
+ "SCL0",
+ "SMPS_SCL",
+ "SMPS_SDA",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
+ status = "okay";
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ status = "okay";
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&wifi_pwrseq>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SDHOST is used to drive the SD card */
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ status = "okay";
+ bus-width = <4>;
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
model = "Raspberry Pi 3 Model B";
- memory {
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
reg = <0 0x40000000>;
};
leds {
act {
- gpios = <&gpio 47 0>;
+ gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&firmware {
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "STATUS_LED",
+ "LAN_RUN",
+ "HDMI_HPD_N",
+ "CAM_GPIO0",
+ "CAM_GPIO1",
+ "PWR_LOW_N";
+ status = "okay";
+ };
+};
+
+&gpio {
+ /*
+ * Taken from rpi_SCH_3b_1p2_reduced.pdf and
+ * the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD1",
+ "RXD1",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "", /* GPIO 28 */
+ "LAN_RUN_BOOT",
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
+ "PWM0_OUT",
+ "PWM1_OUT",
+ "ETHCLK",
+ "WIFI_CLK",
+ "SDA0",
+ "SCL0",
+ "SMPS_SCL",
+ "SMPS_SDA",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
+ status = "okay";
+};
+
+&hdmi {
+ hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;
};
/* uart0 communicates with the BT module */
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+ };
};
/* uart1 is mapped to the pin header */
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
+ mmc-pwrseq = <&wifi_pwrseq>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
};
/* SDHOST is used to drive the SD card */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2837-rpi-cm3.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
+ model = "Raspberry Pi Compute Module 3 IO board V3.0";
+};
+
+&gpio {
+ /*
+ * This is based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "GPIO0",
+ "GPIO1",
+ "GPIO2",
+ "GPIO3",
+ "GPIO4",
+ "GPIO5",
+ "GPIO6",
+ "GPIO7",
+ "GPIO8",
+ "GPIO9",
+ "GPIO10",
+ "GPIO11",
+ "GPIO12",
+ "GPIO13",
+ "GPIO14",
+ "GPIO15",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "GPIO28",
+ "GPIO29",
+ "GPIO30",
+ "GPIO31",
+ "GPIO32",
+ "GPIO33",
+ "GPIO34",
+ "GPIO35",
+ "GPIO36",
+ "GPIO37",
+ "GPIO38",
+ "GPIO39",
+ "GPIO40",
+ "GPIO41",
+ "GPIO42",
+ "GPIO43",
+ "GPIO44",
+ "GPIO45",
+ "GPIO46",
+ "GPIO47",
+ /* Used by eMMC */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0>;
+};
+
+&hdmi {
+ hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2837.dtsi"
+#include "bcm2836-rpi.dtsi"
+
+/ {
+ memory@0 {
+ reg = <0 0x40000000>;
+ };
+
+ reg_3v3: fixed-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_1v8: fixed-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+};
+
+&firmware {
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "HDMI_HPD_N",
+ "EMMC_EN_N",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+ status = "okay";
+ };
+};
+
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ vmmc-supply = <®_3v3>;
+ vqmmc-supply = <®_1v8>;
+ status = "okay";
+};
<0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
- local_intc: local_intc {
+ local_intc: local_intc@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
};
};
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupt-parent = <&local_intc>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&local_intc>;
- interrupts = <0>, // PHYS_SECURE_PPI
- <1>, // PHYS_NONSECURE_PPI
- <3>, // VIRT_PPI
- <2>; // HYP_PPI
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
+ <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
+ <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
+ <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
always-on;
};
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-parent = <&local_intc>;
- interrupts = <8>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
&cpu_thermal {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/net/microchip-lan78xx.h>
+
+/ {
+ aliases {
+ ethernet0 = ðernet;
+ };
+};
+
+&usb {
+ usb-port@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb-port@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: ethernet@1 {
+ compatible = "usb424,7800";
+ reg = <1>;
+
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ eth_phy: ethernet-phy@1 {
+ reg = <1>;
+ microchip,led-modes = <
+ LAN78XX_LINK_1000_ACTIVITY
+ LAN78XX_LINK_10_100_ACTIVITY
+ >;
+ };
+ };
+ };
+ };
+ };
+};
+// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
ethernet0 = ðernet;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+&usb {
+ dr_mode = "otg";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ /*
+ * According to dwc2 the sum of all device EP
+ * fifo sizes shouldn't exceed 3776 bytes.
+ */
+ g-tx-fifo-size = <256 256 512 512 512 768 768>;
+};
#include <dt-bindings/clock/bcm2835.h>
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/soc/bcm2835-pm.h>
/* firmware-provided startup stubs live here, where the secondary CPUs are
* spinning.
#address-cells = <1>;
#size-cells = <1>;
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
chosen {
- bootargs = "earlyprintk console=ttyAMA0";
+ stdout-path = "serial0:115200n8";
};
thermal-zones {
};
};
- soc: soc {
+ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
clock-frequency = <1000000>;
};
+ txp@7e004000 {
+ compatible = "brcm,bcm2835-txp";
+ reg = <0x7e004000 0x20>;
+ interrupts = <1 11>;
+ };
+
dma: dma@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xf00>;
#interrupt-cells = <2>;
};
- watchdog@7e100000 {
- compatible = "brcm,bcm2835-pm-wdt";
- reg = <0x7e100000 0x28>;
+ pm: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x7e100000 0x114>,
+ <0x7e00a000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_V3D>,
+ <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+ <&clocks BCM2835_CLOCK_H264>,
+ <&clocks BCM2835_CLOCK_ISP>;
+ clock-names = "v3d", "peri_image", "h264", "isp";
+ system-power-controller;
};
clocks: cprman@7e101000 {
rng@7e104000 {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
+ interrupts = <2 29>;
};
mailbox: mailbox@7e00b880 {
gpclk2_gpio43: gpclk2_gpio43 {
brcm,pins = <43>;
brcm,function = <BCM2835_FSEL_ALT0>;
+ brcm,pull = <BCM2835_PUD_OFF>;
};
i2c0_gpio0: i2c0_gpio0 {
uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT3>;
+ brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
};
uart0_gpio32: uart0_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>;
+ brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
};
uart0_gpio36: uart0_gpio36 {
brcm,pins = <36 37>;
i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
- reg = <0x7e203000 0x20>,
- <0x7e101098 0x02>;
+ reg = <0x7e203000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;
interrupts = <2 14>; /* pwa1 */
};
+ dpi: dpi@7e208000 {
+ compatible = "brcm,bcm2835-dpi";
+ reg = <0x7e208000 0x8c>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>,
+ <&clocks BCM2835_CLOCK_DPI>;
+ clock-names = "core", "pixel";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
dsi0: dsi@7e209000 {
compatible = "brcm,bcm2835-dsi0";
reg = <0x7e209000 0x78>;
status = "disabled";
};
- aux: aux@0x7e215000 {
+ aux: aux@7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
compatible = "brcm,bcm2835-v3d";
reg = <0x7ec00000 0x1000>;
interrupts = <1 10>;
+ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
};
vc4: gpu {
usbphy: phy {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
};
};
-
-#include "bcm283x-uboot.dtsi"
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
memory@10000000 {
+ device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-wandboard-revb1.dtsi"
+
+/ {
+ model = "Wandboard i.MX6 Quad Board rev B1";
+ compatible = "wand,imx6q-wandboard", "fsl,imx6q";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x80000000>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
+//
+// Author: Fabio Estevam <fabio.estevam@freescale.com>
#include "imx6qdl-wandboard.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
+//
+// Author: Fabio Estevam <fabio.estevam@freescale.com>
+
+#include "imx6qdl-wandboard.dtsi"
+
+/ {
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ regulator-name = "ETH_PHY";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pmic: pfuze100@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&fec {
+ phy-supply = <®_eth_phy>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6qdl-wandboard {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+ >;
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
#include <dt-bindings/gpio/gpio.h>
/ {
+ aliases {
+ mmc0 = &usdhc3;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
sound {
compatible = "fsl,imx6-wandboard-sgtl5000",
"fsl,imx-audio-sgtl5000";
VDDIO-supply = <®_3p3v>;
lrclk-strength = <3>;
};
-
- pmic: pfuze100@8 {
- compatible = "fsl,pfuze100";
- reg = <0x08>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-boot-on;
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
};
&iomuxc {
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+/dts-v1/;
+#include "imx6qp.dtsi"
+#include "imx6qdl-wandboard-revd1.dtsi"
+
+/ {
+ model = "Wandboard i.MX6 QuadPlus Board revD1";
+ compatible = "wand,imx6qp-wandboard", "fsl,imx6qp";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x80000000>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
/* Architecture-specific global data */
struct arch_global_data {
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
u32 sdhc_clk;
#endif
};
#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006
-#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005
+#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044006
#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006
#define BCM2835_MBOX_PIXEL_ORDER_BGR 0
#include <thermal.h>
#include <sata.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
static u32 reset_cause = -1;
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <mmc.h>
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
ANATOP_BASE_ADDR;
struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_USDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
config TARGET_MT7623
bool "MediaTek MT7623 SoC"
select CPU_V7A
- select ARCH_MISC_INIT
help
The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
including NEON and GPU, Mali-450 graphics, several DDR3 options,
bool "MediaTek MT7629 SoC"
select CPU_V7A
select SPL
- select ARCH_MISC_INIT
help
The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
config TARGET_MT8516
bool "MediaTek MT8516 SoC"
select ARM64
- select ARCH_MISC_INIT
help
The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35.
including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
#include <wdt.h>
#include <dm/uclass-internal.h>
-int arch_misc_init(void)
-{
- struct udevice *wdt;
- int ret;
-
- ret = uclass_first_device_err(UCLASS_WDT, &wdt);
- if (!ret)
- wdt_stop(wdt);
-
- return 0;
-}
-
int arch_cpu_init(void)
{
icache_enable();
if segments != 0:
file.write(',')
for i in range(1, segments):
- file.write('"atf_%d"' % (i))
+ file.write('"atf_%d"' % (i + 1))
if i != (segments - 1):
file.write(',')
else:
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/* eSDHC pin as faster speed */
out_8(&gpio->srcr_sdhc, 0x03);
select DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
+ select LAST_STAGE_INIT
select MIPS_TUNE_24KC
select OF_CONTROL
select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_LITTLE_ENDIAN
- select SYS_MALLOC_CLEAR_ON_INIT
select SYSRESET
config ARCH_JZ47XX
return 0;
}
+
+int last_stage_init(void)
+{
+ void *src, *dst;
+
+ src = malloc(SZ_64K);
+ dst = malloc(SZ_64K);
+ if (!src || !dst) {
+ printf("Can't allocate buffer for cache cleanup copy!\n");
+ return 0;
+ }
+
+ /*
+ * It has been noticed, that sometimes the d-cache is not in a
+ * "clean-state" when U-Boot is running on MT7688. This was
+ * detected when using the ethernet driver (which uses d-cache)
+ * and a TFTP command does not complete. Copying an area of 64KiB
+ * in DDR at a very late bootup time in U-Boot, directly before
+ * calling into the prompt, seems to fix this issue.
+ */
+ memcpy(dst, src, SZ_64K);
+ free(src);
+ free(dst);
+
+ return 0;
+}
sandbox,silent; /* Don't emit sounds while testing */
};
+ nop-test_0 {
+ compatible = "sandbox,nop_sandbox1";
+ nop-test_1 {
+ compatible = "sandbox,nop_sandbox2";
+ bind = "True";
+ };
+ nop-test_2 {
+ compatible = "sandbox,nop_sandbox2";
+ bind = "False";
+ };
+ };
+
misc-test {
compatible = "sandbox,misc_sandbox";
};
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
M: Beniamino Galvani <b.galvani@gmail.com>
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
+L: u-boot-amlogic@groups.io
F: board/amlogic/p200/
F: configs/nanopi-k2_defconfig
F: configs/odroid-c2_defconfig
P201
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
+L: u-boot-amlogic@groups.io
F: board/amlogic/p201/
F: configs/p201_defconfig
P212
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
+L: u-boot-amlogic@groups.io
F: board/amlogic/p212/
F: include/configs/p212.h
F: configs/khadas-vim_defconfig
Q200
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
+L: u-boot-amlogic@groups.io
F: board/amlogic/q200/
F: include/configs/q200.h
F: configs/khadas-vim2_defconfig
S400
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
+L: u-boot-amlogic@groups.io
F: board/amlogic/s400/
F: include/configs/s400.h
F: configs/s400_defconfig
U200
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
+L: u-boot-amlogic@groups.io
F: board/amlogic/u200/
F: configs/u200_defconfig
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR},
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <i2c.h>
#include <pca953x.h>
#include <common.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{ USDHC3_BASE_ADDR },
};
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <miiphy.h>
#include <mmc.h>
#include <mmc.h>
#include <phy.h>
#include <netdev.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include <asm/mach-imx/mxc_i2c.h>
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11)
return 0;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_FEC_MXC
*/
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm-generic/gpio.h>
#include "common.h"
#endif /* CONFIG_SPI */
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
return ret;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void)
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define CL_SOM_IMX7_GPIO_USDHC1_CD IMX_GPIO_NR(5, 0)
PADS_SET_PROT(usdhc1_pads);
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
PADS_SET_PROT(uart1_pads);
#ifdef CONFIG_SPI
PADS_SET_PROT(espi1_pads);
#endif /* CONFIG_SPI */
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
PADS_SET_PROT(usdhc3_emmc_pads);
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_FEC_MXC
PADS_SET_PROT(phy1_rst_pads);
PADS_SET_PROT(fec1_pads);
imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | \
PADS_SET(usdhc1_pads)
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
PADS_SET(usdhc3_emmc_pads)
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_FEC_MXC
#include <common.h>
#include <spl.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch-mx7/mx7-pins.h>
#include <asm/arch-mx7/clock.h>
#include <asm/arch-mx7/mx7-ddr.h>
#include "common.h"
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
USDHC1_BASE_ADDR, 0, 4};
cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
static iomux_v3_cfg_t const led_pads[] = {
MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
#include <dm.h>
#include <dwc_ahsata.h>
#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
cm_fx6_setup_display();
/* This should be done in the MMC driver when MX6 has a clock driver */
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
if (IS_ENABLED(CONFIG_BLK)) {
int i;
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/spi.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include "common.h"
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/iomux-v3.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include "common.h"
enum ddr_config {
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <input.h>
#include <power/pmic.h>
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
#include <dwc_ahsata.h>
#include <environment.h>
#include <errno.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <fuse.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/io.h>
#include <errno.h>
#include <fuse.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <spl.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC2_BASE_ADDR},
{USDHC4_BASE_ADDR},
#include <i2c.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <errno.h>
#include <linux/libfdt.h>
#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/immap.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/iomux-mx25.h>
#include <asm/arch/clock.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{IMX_MMC_SDHC1_BASE},
};
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
/* Set up the Card Detect pin. */
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mc9sdz60.h>
#include <mc13892.h>
#include <linux/types.h>
return cpu_eth_init(bis);
}
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_IMX)
struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
#include <i2c.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
gpio_set_value(IMX_GPIO_NR(2, 14), 1);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#define ETHERNET_INT IMX_GPIO_NR(2, 31)
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC3_BASE_ADDR},
#include <i2c.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#include <power/pmic.h>
#include <dialog_pmic.h>
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC3_BASE_ADDR},
#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR},
};
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <usb.h>
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/spi.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
SETUP_IOMUX_PADS(uart4_pads);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC3_BASE_ADDR},
};
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
SETUP_IOMUX_PADS(uart1_pads);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <netdev.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/sizes.h>
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 4},
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/lpddr2.h>
#include <asm/arch/clock.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{USDHC_BASE_ADDR},
};
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
};
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <hwconfig.h>
#include <power/pmic.h>
#include <power/ltc3676_pmic.h>
}
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[2];
int board_mmc_init(bd_t *bis)
return -1;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#include <hwconfig.h>
#include <i2c.h>
#include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <jffs2/load_kernel.h>
#include <linux/ctype.h>
#include <miiphy.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#include <power/pmic.h>
#include <dialog_pmic.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <linux/fb.h>
#include <miiphy.h>
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
#include <linux/errno.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <errno.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <fuse.h>
#include <i2c.h>
#include <miiphy.h>
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
static struct fsl_esdhc_cfg usdhc_cfg[] = {
#include <asm/io.h>
#include <errno.h>
#include <fuse.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <spl.h>
#include <asm/mach-imx/video.h>
#include <dwc_ahsata.h>
#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <input.h>
#include <ipu_pixfmt.h>
#include <asm/arch/crm_regs.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
/*
* SPL boots from uSDHC card
*/
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg = {
USDHC3_BASE_ADDR, 0, 4
};
#ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init();
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
get_clocks();
#endif
void displ5_set_iomux_ecspi(void) {}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/spi.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{ USDHC4_BASE_ADDR, 0, 8, },
};
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
static void displ5_setup_ecspi(void)
{
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <bootcount.h>
#include <watchdog.h>
#include <asm/mach-imx/spi.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <netdev.h>
#include <micrel.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <miiphy.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC1_BASE_ADDR}, /* SOM */
{USDHC2_BASE_ADDR} /* Baseboard */
#include <asm/gpio.h>
#include <asm/spl.h>
#include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <ipu_pixfmt.h>
#include <linux/errno.h>
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
+#ifdef CONFIG_FSL_ESDHC_IMX
+struct fsl_esdhc_cfg esdhc_cfg = {
+ MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+ return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ };
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
{
static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/bitops.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
spl_boot_list[0] = boot_dev;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
void board_init_f(ulong dummy)
{
#include <asm/gpio.h>
#include <mmc.h>
#include <i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <nand.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/gpio.h>
#include <mmc.h>
#include <i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <nand.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/mach-imx/boot_mode.h>
#include <malloc.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <linux/sizes.h>
#include <common.h>
#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/* set environment device to boot device when booting from SD */
int board_mmc_get_env_dev(int devno)
{
{
return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_VIDEO_IPUV3
static void do_enable_hdmi(struct display_info_t const *dev)
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <spl.h>
#if defined(CONFIG_SPL_BUILD)
#include <environment.h>
#include <mmc.h>
#include <input.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mc13892.h>
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
#include <dm/platform_data/serial_mxc.h>
#include <dwc_ahsata.h>
#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <imx_thermal.h>
#include <micrel.h>
#include <miiphy.h>
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
};
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
int mx6_rgmii_rework(struct phy_device *phydev)
{
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
int board_phy_config(struct phy_device *phydev)
{
#include <cpu.h>
#include <dm/platform_data/serial_mxc.h>
#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <imx_thermal.h>
#include <micrel.h>
#include <miiphy.h>
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
int board_phy_config(struct phy_device *phydev)
{
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <jffs2/load_kernel.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/spi.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <i2c.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <i2c.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/bitops.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- Flash the u-boot.img image into the SD card:
-sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
- Insert the SD card into the slot located in the bottom of the board (same side
as the mx6 processor)
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
return 0;
}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_mx6dq()) {
+ if (!strcmp(name, "imx6q-wandboard-revb1"))
+ return 0;
+ } else if (is_mx6dqp()) {
+ if (!strcmp(name, "imx6qp-wandboard-revd1"))
+ return 0;
+ } else if (is_mx6dl() || is_mx6solo()) {
+ if (!strcmp(name, "imx6dl-wandboard-revb1"))
+ return 0;
+ }
+
+ return -EINVAL;
+}
+#endif
#include <linux/sizes.h>
#include <common.h>
#include <watchdog.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <usb.h>
#include <fsl_pmic.h>
#include <mc13892.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/types.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
return 0;
}
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_IMX)
struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
int board_mmc_init(bd_t *bis)
#ifdef CONFIG_DM
initr_dm,
#endif
-#if defined(CONFIG_WDT)
- initr_watchdog,
-#endif
#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \
defined(CONFIG_SANDBOX)
board_init, /* Setup chipselects */
stdio_init_tables,
initr_serial,
initr_announce,
+#if defined(CONFIG_WDT)
+ initr_watchdog,
+#endif
INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
CONFIG_DFU_SF=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
# CONFIG_DWC_AHSATA_AHCI is not set
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS_DT=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_VYBRID_GPIO=y
CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y
CONFIG_E1000=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_PCF8575_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_FEC_MXC=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_MII=y
CONFIG_FPGA_CYCLON2=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_OF_LIBFDT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PHYLIB=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_REGULATOR=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_DWC_AHSATA=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SYS_I2C_MXC=y
CONFIG_PWRSEQ=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_CMD_UBI=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_SYS_TEXT_BASE=0x00080000
+CONFIG_TARGET_RPI_3=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus"
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_CMD_MEMTEST=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LINFLEXUART=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_LED_STATUS_STATE5=2
CONFIG_LED_STATUS_CMD=y
CONFIG_PCA9551_LED=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_OF_LIBFDT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revb1"
+CONFIG_OF_LIST="imx6q-wandboard-revb1 imx6qp-wandboard-revd1 imx6dl-wandboard-revb1"
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_MODE=0
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_MODE=0
return 0;
}
#endif
+
+UCLASS_DRIVER(nop) = {
+ .id = UCLASS_NOP,
+ .name = "nop",
+};
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
help
- This selects support for the eSDHC (enhanced secure digital host
- controller) found on numerous Freescale/NXP SoCs.
+ This selects support for the eSDHC (Enhanced Secure Digital Host
+ Controller) found on numerous Freescale/NXP SoCs.
+
+config FSL_ESDHC_IMX
+ bool "Freescale/NXP i.MX eSDHC controller support"
+ help
+ This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
+ Controller) found on numerous Freescale/NXP SoCs.
endmenu
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_MMC_DW_SNPS) += snps_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
-#include <power/regulator.h>
#include <malloc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <dm.h>
-#include <asm-generic/gpio.h>
-#include <dm/pinctrl.h>
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
IRQSTATEN_DINT)
-#define MAX_TUNING_LOOP 40
#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
struct fsl_esdhc {
uint autoc12err; /* Auto CMD error status register */
uint hostcapblt; /* Host controller capabilities register */
uint wml; /* Watermark level register */
- uint mixctrl; /* For USDHC */
- char reserved1[4]; /* reserved */
+ char reserved1[8]; /* reserved */
uint fevt; /* Force event register */
uint admaes; /* ADMA error status register */
uint adsaddr; /* ADMA system address register */
- char reserved2[4];
- uint dllctrl;
- uint dllstat;
- uint clktunectrlstatus;
- char reserved3[4];
- uint strobe_dllctrl;
- uint strobe_dllstat;
- char reserved4[72];
- uint vendorspec;
- uint mmcboot;
- uint vendorspec2;
- uint tuning_ctrl; /* on i.MX6/7/8 */
- char reserved5[44];
+ char reserved2[160];
uint hostver; /* Host controller version register */
- char reserved6[4]; /* reserved */
+ char reserved3[4]; /* reserved */
uint dmaerraddr; /* DMA error address register */
- char reserved7[4]; /* reserved */
+ char reserved4[4]; /* reserved */
uint dmaerrattr; /* DMA error attribute register */
- char reserved8[4]; /* reserved */
+ char reserved5[4]; /* reserved */
uint hostcapblt2; /* Host controller capabilities register 2 */
- char reserved9[8]; /* reserved */
- uint tcr; /* Tuning control register */
- char reserved10[28]; /* reserved */
- uint sddirctl; /* SD direction control register */
- char reserved11[712];/* reserved */
- uint scr; /* eSDHC control register */
+ char reserved6[756]; /* reserved */
+ uint esdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
struct mmc mmc;
};
-struct esdhc_soc_data {
- u32 flags;
- u32 caps;
-};
-
/**
* struct fsl_esdhc_priv
*
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
- * @caps: controller capabilities
- * @tuning_step: tuning step setting in tuning_ctrl register
- * @start_tuning_tap: the start point for tuning in tuning_ctrl register
- * @strobe_dll_delay_target: settings in strobe_dllctrl
- * @signal_voltage: indicating the current voltage
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
unsigned int sdhc_clk;
struct clk per_clk;
unsigned int clock;
- unsigned int mode;
unsigned int bus_width;
#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
struct udevice *dev;
int non_removable;
int wp_enable;
- int vs18_enable;
- u32 flags;
- u32 caps;
- u32 tuning_step;
- u32 tuning_start_tap;
- u32 strobe_dll_delay_target;
- u32 signal_voltage;
-#if IS_ENABLED(CONFIG_DM_REGULATOR)
- struct udevice *vqmmc_dev;
- struct udevice *vmmc_dev;
-#endif
-#ifdef CONFIG_DM_GPIO
- struct gpio_desc cd_gpio;
- struct gpio_desc wp_gpio;
-#endif
};
/* Return the XFERTYP flags for a given command and data packet */
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
dma_addr_t addr;
#endif
uint wml_value;
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return -ETIMEDOUT;
}
- } else {
-#ifdef CONFIG_DM_GPIO
- if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
- printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
- return -ETIMEDOUT;
- }
-#endif
}
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
invalidate_dcache_range(start, end);
}
-#ifdef CONFIG_MCF5441x
-/*
- * Swaps 32-bit words to little-endian byte order.
- */
-static inline void sd_swap_dma_buff(struct mmc_data *data)
-{
- int i, size = data->blocksize >> 2;
- u32 *buffer = (u32 *)data->dest;
- u32 sw;
-
- while (data->blocks--) {
- for (i = 0; i < size; i++) {
- sw = __sw32(*buffer);
- *buffer++ = sw;
- }
- }
-}
-#endif
-
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
/* Send the command */
esdhc_write32(®s->cmdarg, cmd->cmdarg);
-#if defined(CONFIG_FSL_USDHC)
- esdhc_write32(®s->mixctrl,
- (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
- | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
- esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
-#else
esdhc_write32(®s->xfertyp, xfertyp);
-#endif
if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
goto out;
}
- /* Switch voltage to 1.8V if CMD11 succeeded */
- if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
- printf("Run CMD11 1.8V switch\n");
- /* Sleep for 5 ms - max time for card to switch to 1.8V */
- udelay(5000);
- }
-
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
int timeout = 6000;
*/
if (data->flags & MMC_DATA_READ) {
check_and_invalidate_dcache_range(cmd, data);
-#ifdef CONFIG_MCF5441x
- sd_swap_dma_buff(data);
-#endif
}
#endif
}
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
;
}
-
- /* If this was CMD11, then notify that power cycle is needed */
- if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
- printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
}
esdhc_write32(®s->irqstat, -1);
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
-#ifdef ARCH_MXC
-#ifdef CONFIG_MX53
- /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
- int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
-#else
- int pre_div = 1;
-#endif
-#else
int pre_div = 2;
-#endif
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
int sdhc_clk = priv->sdhc_clk;
uint clk;
clk = (pre_div << 8) | (div << 4);
-#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
-#else
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
-#endif
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
-#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
-#else
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
-#endif
priv->clock = clock;
}
}
#endif
-#ifdef MMC_SUPPORTS_TUNING
-static int esdhc_change_pinstate(struct udevice *dev)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- int ret;
-
- switch (priv->mode) {
- case UHS_SDR50:
- case UHS_DDR50:
- ret = pinctrl_select_state(dev, "state_100mhz");
- break;
- case UHS_SDR104:
- case MMC_HS_200:
- case MMC_HS_400:
- ret = pinctrl_select_state(dev, "state_200mhz");
- break;
- default:
- ret = pinctrl_select_state(dev, "default");
- break;
- }
-
- if (ret)
- printf("%s %d error\n", __func__, priv->mode);
-
- return ret;
-}
-
-static void esdhc_reset_tuning(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
-
- if (priv->flags & ESDHC_FLAG_USDHC) {
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- esdhc_clrbits32(®s->autoc12err,
- MIX_CTRL_SMPCLK_SEL |
- MIX_CTRL_EXE_TUNE);
- }
- }
-}
-
-static void esdhc_set_strobe_dll(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- u32 val;
-
- if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
- writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
-
- /*
- * enable strobe dll ctrl and adjust the delay target
- * for the uSDHC loopback read clock
- */
- val = ESDHC_STROBE_DLL_CTRL_ENABLE |
- (priv->strobe_dll_delay_target <<
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
- writel(val, ®s->strobe_dllctrl);
- /* wait 1us to make sure strobe dll status register stable */
- mdelay(1);
- val = readl(®s->strobe_dllstat);
- if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
- pr_warn("HS400 strobe DLL status REF not lock!\n");
- if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
- pr_warn("HS400 strobe DLL status SLV not lock!\n");
- }
-}
-
-static int esdhc_set_timing(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- u32 mixctrl;
-
- mixctrl = readl(®s->mixctrl);
- mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
-
- switch (mmc->selected_mode) {
- case MMC_LEGACY:
- case SD_LEGACY:
- esdhc_reset_tuning(mmc);
- writel(mixctrl, ®s->mixctrl);
- break;
- case MMC_HS_400:
- mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
- writel(mixctrl, ®s->mixctrl);
- esdhc_set_strobe_dll(mmc);
- break;
- case MMC_HS:
- case MMC_HS_52:
- case MMC_HS_200:
- case SD_HS:
- case UHS_SDR12:
- case UHS_SDR25:
- case UHS_SDR50:
- case UHS_SDR104:
- writel(mixctrl, ®s->mixctrl);
- break;
- case UHS_DDR50:
- case MMC_DDR_52:
- mixctrl |= MIX_CTRL_DDREN;
- writel(mixctrl, ®s->mixctrl);
- break;
- default:
- printf("Not supported %d\n", mmc->selected_mode);
- return -EINVAL;
- }
-
- priv->mode = mmc->selected_mode;
-
- return esdhc_change_pinstate(mmc->dev);
-}
-
-static int esdhc_set_voltage(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- int ret;
-
- priv->signal_voltage = mmc->signal_voltage;
- switch (mmc->signal_voltage) {
- case MMC_SIGNAL_VOLTAGE_330:
- if (priv->vs18_enable)
- return -EIO;
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
- ret = regulator_set_value(priv->vqmmc_dev, 3300000);
- if (ret) {
- printf("Setting to 3.3V error");
- return -EIO;
- }
- /* Wait for 5ms */
- mdelay(5);
- }
-#endif
-
- esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
- if (!(esdhc_read32(®s->vendorspec) &
- ESDHC_VENDORSPEC_VSELECT))
- return 0;
-
- return -EAGAIN;
- case MMC_SIGNAL_VOLTAGE_180:
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
- ret = regulator_set_value(priv->vqmmc_dev, 1800000);
- if (ret) {
- printf("Setting to 1.8V error");
- return -EIO;
- }
- }
-#endif
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
- if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
- return 0;
-
- return -EAGAIN;
- case MMC_SIGNAL_VOLTAGE_120:
- return -ENOTSUPP;
- default:
- return 0;
- }
-}
-
-static void esdhc_stop_tuning(struct mmc *mmc)
-{
- struct mmc_cmd cmd;
-
- cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
- cmd.cmdarg = 0;
- cmd.resp_type = MMC_RSP_R1b;
-
- dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
-}
-
-static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
-{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
- struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- struct mmc *mmc = &plat->mmc;
- u32 irqstaten = readl(®s->irqstaten);
- u32 irqsigen = readl(®s->irqsigen);
- int i, ret = -ETIMEDOUT;
- u32 val, mixctrl;
-
- /* clock tuning is not needed for upto 52MHz */
- if (mmc->clock <= 52000000)
- return 0;
-
- /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- val = readl(®s->autoc12err);
- mixctrl = readl(®s->mixctrl);
- val &= ~MIX_CTRL_SMPCLK_SEL;
- mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
-
- val |= MIX_CTRL_EXE_TUNE;
- mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
-
- writel(val, ®s->autoc12err);
- writel(mixctrl, ®s->mixctrl);
- }
-
- /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
- mixctrl = readl(®s->mixctrl);
- mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
- writel(mixctrl, ®s->mixctrl);
-
- writel(IRQSTATEN_BRR, ®s->irqstaten);
- writel(IRQSTATEN_BRR, ®s->irqsigen);
-
- /*
- * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
- * of loops reaches 40 times.
- */
- for (i = 0; i < MAX_TUNING_LOOP; i++) {
- u32 ctrl;
-
- if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
- if (mmc->bus_width == 8)
- writel(0x7080, ®s->blkattr);
- else if (mmc->bus_width == 4)
- writel(0x7040, ®s->blkattr);
- } else {
- writel(0x7040, ®s->blkattr);
- }
-
- /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
- val = readl(®s->mixctrl);
- val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
- writel(val, ®s->mixctrl);
-
- /* We are using STD tuning, no need to check return value */
- mmc_send_tuning(mmc, opcode, NULL);
-
- ctrl = readl(®s->autoc12err);
- if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
- (ctrl & MIX_CTRL_SMPCLK_SEL)) {
- /*
- * need to wait some time, make sure sd/mmc fininsh
- * send out tuning data, otherwise, the sd/mmc can't
- * response to any command when the card still out
- * put the tuning data.
- */
- mdelay(1);
- ret = 0;
- break;
- }
-
- /* Add 1ms delay for SD and eMMC */
- mdelay(1);
- }
-
- writel(irqstaten, ®s->irqstaten);
- writel(irqsigen, ®s->irqsigen);
-
- esdhc_stop_tuning(mmc);
-
- return ret;
-}
-#endif
-
static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
- int ret __maybe_unused;
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
/* Select to use peripheral clock */
esdhc_clock_control(priv, false);
- esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
+ esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
esdhc_clock_control(priv, true);
#endif
/* Set the clock speed */
if (priv->clock != mmc->clock)
set_sysctl(priv, mmc, mmc->clock);
-#ifdef MMC_SUPPORTS_TUNING
- if (mmc->clk_disable) {
-#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
-#else
- esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
-#endif
- } else {
-#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_CKEN);
-#else
- esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
-#endif
- }
-
- if (priv->mode != mmc->selected_mode) {
- ret = esdhc_set_timing(mmc);
- if (ret) {
- printf("esdhc_set_timing error %d\n", ret);
- return ret;
- }
- }
-
- if (priv->signal_voltage != mmc->signal_voltage) {
- ret = esdhc_set_voltage(mmc);
- if (ret) {
- printf("esdhc_set_voltage error %d\n", ret);
- return ret;
- }
- }
-#endif
-
/* Set the bus width */
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
return -ETIMEDOUT;
}
-#if defined(CONFIG_FSL_USDHC)
- /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
- esdhc_write32(®s->mmcboot, 0x0);
- /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
- esdhc_write32(®s->mixctrl, 0x0);
- esdhc_write32(®s->clktunectrlstatus, 0x0);
-
- /* Put VEND_SPEC to default value */
- if (priv->vs18_enable)
- esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
- ESDHC_VENDORSPEC_VSELECT));
- else
- esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
-
- /* Disable DLL_CTRL delay line */
- esdhc_write32(®s->dllctrl, 0x0);
-#endif
-
-#ifndef ARCH_MXC
/* Enable cache snooping */
- esdhc_write32(®s->scr, 0x00000040);
-#endif
+ esdhc_write32(®s->esdhcctl, 0x00000040);
-#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
-#else
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
-#endif
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
-#ifdef CONFIG_MCF5441x
- esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
-#else
/* Put the PROCTL reg back to the default */
esdhc_write32(®s->proctl, PROCTL_INIT);
-#endif
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
#if CONFIG_IS_ENABLED(DM_MMC)
if (priv->non_removable)
return 1;
-#ifdef CONFIG_DM_GPIO
- if (dm_gpio_is_valid(&priv->cd_gpio))
- return dm_gpio_get_value(&priv->cd_gpio);
-#endif
#endif
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
if (ret)
return ret;
-#ifdef CONFIG_MCF5441x
- /* ColdFire, using SDHC_DATA[3] for card detection */
- esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
-#endif
-
-#ifndef CONFIG_FSL_USDHC
- esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
- | SYSCTL_IPGEN | SYSCTL_CKEN);
- /* Clearing tuning bits in case ROM has set it already */
- esdhc_write32(®s->mixctrl, 0);
- esdhc_write32(®s->autoc12err, 0);
- esdhc_write32(®s->clktunectrlstatus, 0);
-#else
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
-#endif
-
- if (priv->vs18_enable)
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
+ SYSCTL_IPGEN | SYSCTL_CKEN);
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
cfg = &plat->cfg;
voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
-#ifdef CONFIG_MCF5441x
- /*
- * MCF5441x RM declares in more points that sdhc clock speed must
- * never exceed 25 Mhz. From this, the HS bit needs to be disabled
- * from host capabilities.
- */
- caps &= ~ESDHC_HOSTCAPBLT_HSS;
-#endif
-
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
cfg->host_caps &= ~MMC_MODE_8BIT;
#endif
- cfg->host_caps |= priv->caps;
-
cfg->f_min = 400000;
cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- writel(0, ®s->dllctrl);
- if (priv->flags & ESDHC_FLAG_USDHC) {
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- u32 val = readl(®s->tuning_ctrl);
-
- val |= ESDHC_STD_TUNING_EN;
- val &= ~ESDHC_TUNING_START_TAP_MASK;
- val |= priv->tuning_start_tap;
- val &= ~ESDHC_TUNING_STEP_MASK;
- val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
- writel(val, ®s->tuning_ctrl);
- }
- }
-
return 0;
}
priv->bus_width = cfg->max_bus_width;
priv->sdhc_clk = cfg->sdhc_clk;
priv->wp_enable = cfg->wp_enable;
- priv->vs18_enable = cfg->vs18_enable;
return 0;
};
#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
#endif
-__weak void init_clk_usdhc(u32 index)
-{
-}
-
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
- struct esdhc_soc_data *data =
- (struct esdhc_soc_data *)dev_get_driver_data(dev);
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- struct udevice *vqmmc_dev;
-#endif
fdt_addr_t addr;
unsigned int val;
struct mmc *mmc;
priv->esdhc_regs = (struct fsl_esdhc *)addr;
#endif
priv->dev = dev;
- priv->mode = -1;
- if (data) {
- priv->flags = data->flags;
- priv->caps = data->caps;
- }
val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
else
priv->bus_width = 1;
- val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
- priv->tuning_step = val;
- val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
- ESDHC_TUNING_START_TAP_DEFAULT);
- priv->tuning_start_tap = val;
- val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
- priv->strobe_dll_delay_target = val;
-
if (dev_read_bool(dev, "non-removable")) {
priv->non_removable = 1;
} else {
priv->non_removable = 0;
-#ifdef CONFIG_DM_GPIO
- gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
- GPIOD_IS_IN);
-#endif
}
- if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
- priv->wp_enable = 1;
- } else {
- priv->wp_enable = 0;
-#ifdef CONFIG_DM_GPIO
- gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
- GPIOD_IS_IN);
-#endif
- }
-
- priv->vs18_enable = 0;
-
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- /*
- * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
- * otherwise, emmc will work abnormally.
- */
- ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
- if (ret) {
- dev_dbg(dev, "no vqmmc-supply\n");
- } else {
- ret = regulator_set_enable(vqmmc_dev, true);
- if (ret) {
- dev_err(dev, "fail to enable vqmmc-supply\n");
- return ret;
- }
-
- if (regulator_get_value(vqmmc_dev) == 1800000)
- priv->vs18_enable = 1;
- }
-#endif
-
- if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
- priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
-
- /*
- * TODO:
- * Because lack of clk driver, if SDHC clk is not enabled,
- * need to enable it first before this driver is invoked.
- *
- * we use MXC_ESDHC_CLK to get clk freq.
- * If one would like to make this function work,
- * the aliases should be provided in dts as this:
- *
- * aliases {
- * mmc0 = &usdhc1;
- * mmc1 = &usdhc2;
- * mmc2 = &usdhc3;
- * mmc3 = &usdhc4;
- * };
- * Then if your board only supports mmc2 and mmc3, but we can
- * correctly get the seq as 2 and 3, then let mxc_get_clock
- * work as expected.
- */
-
- init_clk_usdhc(dev->seq);
+ priv->wp_enable = 1;
if (IS_ENABLED(CONFIG_CLK)) {
/* Assigned clock already set clock */
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
.set_ios = fsl_esdhc_set_ios,
-#ifdef MMC_SUPPORTS_TUNING
- .execute_tuning = fsl_esdhc_execute_tuning,
-#endif
};
#endif
-static struct esdhc_soc_data usdhc_imx7d_data = {
- .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
- | ESDHC_FLAG_HS400,
- .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
- MMC_MODE_HS_52MHz | MMC_MODE_HS,
-};
-
static const struct udevice_id fsl_esdhc_ids[] = {
- { .compatible = "fsl,imx53-esdhc", },
- { .compatible = "fsl,imx6ul-usdhc", },
- { .compatible = "fsl,imx6sx-usdhc", },
- { .compatible = "fsl,imx6sl-usdhc", },
- { .compatible = "fsl,imx6q-usdhc", },
- { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
- { .compatible = "fsl,imx7ulp-usdhc", },
{ .compatible = "fsl,esdhc", },
{ /* sentinel */ }
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2019 NXP Semiconductors
+ * Andy Fleming
+ * Yangbo Lu <yangbo.lu@nxp.com>
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <clk.h>
+#include <errno.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <part.h>
+#include <power/regulator.h>
+#include <malloc.h>
+#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
+#include <dm/pinctrl.h>
+
+#if !CONFIG_IS_ENABLED(BLK)
+#include "mmc_private.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
+ IRQSTATEN_CINT | \
+ IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
+ IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
+ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
+ IRQSTATEN_DINT)
+#define MAX_TUNING_LOOP 40
+#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
+
+struct fsl_esdhc {
+ uint dsaddr; /* SDMA system address register */
+ uint blkattr; /* Block attributes register */
+ uint cmdarg; /* Command argument register */
+ uint xfertyp; /* Transfer type register */
+ uint cmdrsp0; /* Command response 0 register */
+ uint cmdrsp1; /* Command response 1 register */
+ uint cmdrsp2; /* Command response 2 register */
+ uint cmdrsp3; /* Command response 3 register */
+ uint datport; /* Buffer data port register */
+ uint prsstat; /* Present state register */
+ uint proctl; /* Protocol control register */
+ uint sysctl; /* System Control Register */
+ uint irqstat; /* Interrupt status register */
+ uint irqstaten; /* Interrupt status enable register */
+ uint irqsigen; /* Interrupt signal enable register */
+ uint autoc12err; /* Auto CMD error status register */
+ uint hostcapblt; /* Host controller capabilities register */
+ uint wml; /* Watermark level register */
+ uint mixctrl; /* For USDHC */
+ char reserved1[4]; /* reserved */
+ uint fevt; /* Force event register */
+ uint admaes; /* ADMA error status register */
+ uint adsaddr; /* ADMA system address register */
+ char reserved2[4];
+ uint dllctrl;
+ uint dllstat;
+ uint clktunectrlstatus;
+ char reserved3[4];
+ uint strobe_dllctrl;
+ uint strobe_dllstat;
+ char reserved4[72];
+ uint vendorspec;
+ uint mmcboot;
+ uint vendorspec2;
+ uint tuning_ctrl; /* on i.MX6/7/8 */
+ char reserved5[44];
+ uint hostver; /* Host controller version register */
+ char reserved6[4]; /* reserved */
+ uint dmaerraddr; /* DMA error address register */
+ char reserved7[4]; /* reserved */
+ uint dmaerrattr; /* DMA error attribute register */
+ char reserved8[4]; /* reserved */
+ uint hostcapblt2; /* Host controller capabilities register 2 */
+ char reserved9[8]; /* reserved */
+ uint tcr; /* Tuning control register */
+ char reserved10[28]; /* reserved */
+ uint sddirctl; /* SD direction control register */
+ char reserved11[712];/* reserved */
+ uint scr; /* eSDHC control register */
+};
+
+struct fsl_esdhc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct esdhc_soc_data {
+ u32 flags;
+ u32 caps;
+};
+
+/**
+ * struct fsl_esdhc_priv
+ *
+ * @esdhc_regs: registers of the sdhc controller
+ * @sdhc_clk: Current clk of the sdhc controller
+ * @bus_width: bus width, 1bit, 4bit or 8bit
+ * @cfg: mmc config
+ * @mmc: mmc
+ * Following is used when Driver Model is enabled for MMC
+ * @dev: pointer for the device
+ * @non_removable: 0: removable; 1: non-removable
+ * @wp_enable: 1: enable checking wp; 0: no check
+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
+ * @caps: controller capabilities
+ * @tuning_step: tuning step setting in tuning_ctrl register
+ * @start_tuning_tap: the start point for tuning in tuning_ctrl register
+ * @strobe_dll_delay_target: settings in strobe_dllctrl
+ * @signal_voltage: indicating the current voltage
+ * @cd_gpio: gpio for card detection
+ * @wp_gpio: gpio for write protection
+ */
+struct fsl_esdhc_priv {
+ struct fsl_esdhc *esdhc_regs;
+ unsigned int sdhc_clk;
+ struct clk per_clk;
+ unsigned int clock;
+ unsigned int mode;
+ unsigned int bus_width;
+#if !CONFIG_IS_ENABLED(BLK)
+ struct mmc *mmc;
+#endif
+ struct udevice *dev;
+ int non_removable;
+ int wp_enable;
+ int vs18_enable;
+ u32 flags;
+ u32 caps;
+ u32 tuning_step;
+ u32 tuning_start_tap;
+ u32 strobe_dll_delay_target;
+ u32 signal_voltage;
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+ struct udevice *vqmmc_dev;
+ struct udevice *vmmc_dev;
+#endif
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc cd_gpio;
+ struct gpio_desc wp_gpio;
+#endif
+};
+
+/* Return the XFERTYP flags for a given command and data packet */
+static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ uint xfertyp = 0;
+
+ if (data) {
+ xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ xfertyp |= XFERTYP_DMAEN;
+#endif
+ if (data->blocks > 1) {
+ xfertyp |= XFERTYP_MSBSEL;
+ xfertyp |= XFERTYP_BCEN;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+ xfertyp |= XFERTYP_AC12EN;
+#endif
+ }
+
+ if (data->flags & MMC_DATA_READ)
+ xfertyp |= XFERTYP_DTDSEL;
+ }
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ xfertyp |= XFERTYP_CCCEN;
+ if (cmd->resp_type & MMC_RSP_OPCODE)
+ xfertyp |= XFERTYP_CICEN;
+ if (cmd->resp_type & MMC_RSP_136)
+ xfertyp |= XFERTYP_RSPTYP_136;
+ else if (cmd->resp_type & MMC_RSP_BUSY)
+ xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+ else if (cmd->resp_type & MMC_RSP_PRESENT)
+ xfertyp |= XFERTYP_RSPTYP_48;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ xfertyp |= XFERTYP_CMDTYP_ABORT;
+
+ return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
+}
+
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ uint blocks;
+ char *buffer;
+ uint databuf;
+ uint size;
+ uint irqstat;
+ ulong start;
+
+ if (data->flags & MMC_DATA_READ) {
+ blocks = data->blocks;
+ buffer = data->dest;
+ while (blocks) {
+ start = get_timer(0);
+ size = data->blocksize;
+ irqstat = esdhc_read32(®s->irqstat);
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
+ if (get_timer(start) > PIO_TIMEOUT) {
+ printf("\nData Read Failed in PIO Mode.");
+ return;
+ }
+ }
+ while (size && (!(irqstat & IRQSTAT_TC))) {
+ udelay(100); /* Wait before last byte transfer complete */
+ irqstat = esdhc_read32(®s->irqstat);
+ databuf = in_le32(®s->datport);
+ *((uint *)buffer) = databuf;
+ buffer += 4;
+ size -= 4;
+ }
+ blocks--;
+ }
+ } else {
+ blocks = data->blocks;
+ buffer = (char *)data->src;
+ while (blocks) {
+ start = get_timer(0);
+ size = data->blocksize;
+ irqstat = esdhc_read32(®s->irqstat);
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
+ if (get_timer(start) > PIO_TIMEOUT) {
+ printf("\nData Write Failed in PIO Mode.");
+ return;
+ }
+ }
+ while (size && (!(irqstat & IRQSTAT_TC))) {
+ udelay(100); /* Wait before last byte transfer complete */
+ databuf = *((uint *)buffer);
+ buffer += 4;
+ size -= 4;
+ irqstat = esdhc_read32(®s->irqstat);
+ out_le32(®s->datport, databuf);
+ }
+ blocks--;
+ }
+ }
+}
+#endif
+
+static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ struct mmc_data *data)
+{
+ int timeout;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ dma_addr_t addr;
+#endif
+ uint wml_value;
+
+ wml_value = data->blocksize/4;
+
+ if (data->flags & MMC_DATA_READ) {
+ if (wml_value > WML_RD_WML_MAX)
+ wml_value = WML_RD_WML_MAX_VAL;
+
+ esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ addr = virt_to_phys((void *)(data->dest));
+ if (upper_32_bits(addr))
+ printf("Error found for upper 32 bits\n");
+ else
+ esdhc_write32(®s->dsaddr, lower_32_bits(addr));
+#else
+ esdhc_write32(®s->dsaddr, (u32)data->dest);
+#endif
+#endif
+ } else {
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ flush_dcache_range((ulong)data->src,
+ (ulong)data->src+data->blocks
+ *data->blocksize);
+#endif
+ if (wml_value > WML_WR_WML_MAX)
+ wml_value = WML_WR_WML_MAX_VAL;
+ if (priv->wp_enable) {
+ if ((esdhc_read32(®s->prsstat) &
+ PRSSTAT_WPSPL) == 0) {
+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+#ifdef CONFIG_DM_GPIO
+ if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+ return -ETIMEDOUT;
+ }
+#endif
+ }
+
+ esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
+ wml_value << 16);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ addr = virt_to_phys((void *)(data->src));
+ if (upper_32_bits(addr))
+ printf("Error found for upper 32 bits\n");
+ else
+ esdhc_write32(®s->dsaddr, lower_32_bits(addr));
+#else
+ esdhc_write32(®s->dsaddr, (u32)data->src);
+#endif
+#endif
+ }
+
+ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
+
+ /* Calculate the timeout period for data transactions */
+ /*
+ * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
+ * 2)Timeout period should be minimum 0.250sec as per SD Card spec
+ * So, Number of SD Clock cycles for 0.25sec should be minimum
+ * (SD Clock/sec * 0.25 sec) SD Clock cycles
+ * = (mmc->clock * 1/4) SD Clock cycles
+ * As 1) >= 2)
+ * => (2^(timeout+13)) >= mmc->clock * 1/4
+ * Taking log2 both the sides
+ * => timeout + 13 >= log2(mmc->clock/4)
+ * Rounding up to next power of 2
+ * => timeout + 13 = log2(mmc->clock/4) + 1
+ * => timeout + 13 = fls(mmc->clock/4)
+ *
+ * However, the MMC spec "It is strongly recommended for hosts to
+ * implement more than 500ms timeout value even if the card
+ * indicates the 250ms maximum busy length." Even the previous
+ * value of 300ms is known to be insufficient for some cards.
+ * So, we use
+ * => timeout + 13 = fls(mmc->clock/2)
+ */
+ timeout = fls(mmc->clock/2);
+ timeout -= 13;
+
+ if (timeout > 14)
+ timeout = 14;
+
+ if (timeout < 0)
+ timeout = 0;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+ if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+ timeout++;
+#endif
+
+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+ timeout = 0xE;
+#endif
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
+
+ return 0;
+}
+
+static void check_and_invalidate_dcache_range
+ (struct mmc_cmd *cmd,
+ struct mmc_data *data) {
+ unsigned start = 0;
+ unsigned end = 0;
+ unsigned size = roundup(ARCH_DMA_MINALIGN,
+ data->blocks*data->blocksize);
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ dma_addr_t addr;
+
+ addr = virt_to_phys((void *)(data->dest));
+ if (upper_32_bits(addr))
+ printf("Error found for upper 32 bits\n");
+ else
+ start = lower_32_bits(addr);
+#else
+ start = (unsigned)data->dest;
+#endif
+ end = start + size;
+ invalidate_dcache_range(start, end);
+}
+
+#ifdef CONFIG_MCF5441x
+/*
+ * Swaps 32-bit words to little-endian byte order.
+ */
+static inline void sd_swap_dma_buff(struct mmc_data *data)
+{
+ int i, size = data->blocksize >> 2;
+ u32 *buffer = (u32 *)data->dest;
+ u32 sw;
+
+ while (data->blocks--) {
+ for (i = 0; i < size; i++) {
+ sw = __sw32(*buffer);
+ *buffer++ = sw;
+ }
+ }
+}
+#endif
+
+/*
+ * Sends a command out on the bus. Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ int err = 0;
+ uint xfertyp;
+ uint irqstat;
+ u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ unsigned long start;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ return 0;
+#endif
+
+ esdhc_write32(®s->irqstat, -1);
+
+ sync();
+
+ /* Wait for the bus to be idle */
+ while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
+ (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
+ ;
+
+ while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
+ ;
+
+ /* Wait at least 8 SD clock cycles before the next command */
+ /*
+ * Note: This is way more than 8 cycles, but 1ms seems to
+ * resolve timing issues with some cards
+ */
+ udelay(1000);
+
+ /* Set up for a data transfer if we have one */
+ if (data) {
+ err = esdhc_setup_data(priv, mmc, data);
+ if(err)
+ return err;
+
+ if (data->flags & MMC_DATA_READ)
+ check_and_invalidate_dcache_range(cmd, data);
+ }
+
+ /* Figure out the transfer arguments */
+ xfertyp = esdhc_xfertyp(cmd, data);
+
+ /* Mask all irqs */
+ esdhc_write32(®s->irqsigen, 0);
+
+ /* Send the command */
+ esdhc_write32(®s->cmdarg, cmd->cmdarg);
+#if defined(CONFIG_FSL_USDHC)
+ esdhc_write32(®s->mixctrl,
+ (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
+ | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
+ esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
+#else
+ esdhc_write32(®s->xfertyp, xfertyp);
+#endif
+
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
+ flags = IRQSTAT_BRR;
+
+ /* Wait for the command to complete */
+ start = get_timer(0);
+ while (!(esdhc_read32(®s->irqstat) & flags)) {
+ if (get_timer(start) > 1000) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+ }
+
+ irqstat = esdhc_read32(®s->irqstat);
+
+ if (irqstat & CMD_ERR) {
+ err = -ECOMM;
+ goto out;
+ }
+
+ if (irqstat & IRQSTAT_CTOE) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* Switch voltage to 1.8V if CMD11 succeeded */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+ printf("Run CMD11 1.8V switch\n");
+ /* Sleep for 5 ms - max time for card to switch to 1.8V */
+ udelay(5000);
+ }
+
+ /* Workaround for ESDHC errata ENGcm03648 */
+ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
+ int timeout = 6000;
+
+ /* Poll on DATA0 line for cmd with busy signal for 600 ms */
+ while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
+ PRSSTAT_DAT0)) {
+ udelay(100);
+ timeout--;
+ }
+
+ if (timeout <= 0) {
+ printf("Timeout waiting for DAT0 to go high!\n");
+ err = -ETIMEDOUT;
+ goto out;
+ }
+ }
+
+ /* Copy the response to the response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
+
+ cmdrsp3 = esdhc_read32(®s->cmdrsp3);
+ cmdrsp2 = esdhc_read32(®s->cmdrsp2);
+ cmdrsp1 = esdhc_read32(®s->cmdrsp1);
+ cmdrsp0 = esdhc_read32(®s->cmdrsp0);
+ cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
+ cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
+ cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
+ cmd->response[3] = (cmdrsp0 << 8);
+ } else
+ cmd->response[0] = esdhc_read32(®s->cmdrsp0);
+
+ /* Wait until all of the blocks are transferred */
+ if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ esdhc_pio_read_write(priv, data);
+#else
+ flags = DATA_COMPLETE;
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
+ flags = IRQSTAT_BRR;
+ }
+
+ do {
+ irqstat = esdhc_read32(®s->irqstat);
+
+ if (irqstat & IRQSTAT_DTOE) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (irqstat & DATA_ERR) {
+ err = -ECOMM;
+ goto out;
+ }
+ } while ((irqstat & flags) != flags);
+
+ /*
+ * Need invalidate the dcache here again to avoid any
+ * cache-fill during the DMA operations such as the
+ * speculative pre-fetching etc.
+ */
+ if (data->flags & MMC_DATA_READ) {
+ check_and_invalidate_dcache_range(cmd, data);
+#ifdef CONFIG_MCF5441x
+ sd_swap_dma_buff(data);
+#endif
+ }
+#endif
+ }
+
+out:
+ /* Reset CMD and DATA portions on error */
+ if (err) {
+ esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
+ SYSCTL_RSTC);
+ while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
+ ;
+
+ if (data) {
+ esdhc_write32(®s->sysctl,
+ esdhc_read32(®s->sysctl) |
+ SYSCTL_RSTD);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
+ ;
+ }
+
+ /* If this was CMD11, then notify that power cycle is needed */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
+ printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
+ }
+
+ esdhc_write32(®s->irqstat, -1);
+
+ return err;
+}
+
+static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int div = 1;
+#ifdef ARCH_MXC
+#ifdef CONFIG_MX53
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+#else
+ int pre_div = 1;
+#endif
+#else
+ int pre_div = 2;
+#endif
+ int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
+ int sdhc_clk = priv->sdhc_clk;
+ uint clk;
+
+ if (clock < mmc->cfg->f_min)
+ clock = mmc->cfg->f_min;
+
+ while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
+ pre_div *= 2;
+
+ while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
+ div++;
+
+ pre_div >>= 1;
+ div -= 1;
+
+ clk = (pre_div << 8) | (div << 4);
+
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
+#else
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+#endif
+
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
+
+ udelay(10000);
+
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
+#else
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+
+ priv->clock = clock;
+}
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 value;
+ u32 time_out;
+
+ value = esdhc_read32(®s->sysctl);
+
+ if (enable)
+ value |= SYSCTL_CKEN;
+ else
+ value &= ~SYSCTL_CKEN;
+
+ esdhc_write32(®s->sysctl, value);
+
+ time_out = 20;
+ value = PRSSTAT_SDSTB;
+ while (!(esdhc_read32(®s->prsstat) & value)) {
+ if (time_out == 0) {
+ printf("fsl_esdhc: Internal clock never stabilised.\n");
+ break;
+ }
+ time_out--;
+ mdelay(1);
+ }
+}
+#endif
+
+#ifdef MMC_SUPPORTS_TUNING
+static int esdhc_change_pinstate(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ switch (priv->mode) {
+ case UHS_SDR50:
+ case UHS_DDR50:
+ ret = pinctrl_select_state(dev, "state_100mhz");
+ break;
+ case UHS_SDR104:
+ case MMC_HS_200:
+ case MMC_HS_400:
+ ret = pinctrl_select_state(dev, "state_200mhz");
+ break;
+ default:
+ ret = pinctrl_select_state(dev, "default");
+ break;
+ }
+
+ if (ret)
+ printf("%s %d error\n", __func__, priv->mode);
+
+ return ret;
+}
+
+static void esdhc_reset_tuning(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ esdhc_clrbits32(®s->autoc12err,
+ MIX_CTRL_SMPCLK_SEL |
+ MIX_CTRL_EXE_TUNE);
+ }
+ }
+}
+
+static void esdhc_set_strobe_dll(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 val;
+
+ if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
+ writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
+
+ /*
+ * enable strobe dll ctrl and adjust the delay target
+ * for the uSDHC loopback read clock
+ */
+ val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ (priv->strobe_dll_delay_target <<
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+ writel(val, ®s->strobe_dllctrl);
+ /* wait 1us to make sure strobe dll status register stable */
+ mdelay(1);
+ val = readl(®s->strobe_dllstat);
+ if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
+ pr_warn("HS400 strobe DLL status REF not lock!\n");
+ if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
+ pr_warn("HS400 strobe DLL status SLV not lock!\n");
+ }
+}
+
+static int esdhc_set_timing(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 mixctrl;
+
+ mixctrl = readl(®s->mixctrl);
+ mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
+
+ switch (mmc->selected_mode) {
+ case MMC_LEGACY:
+ case SD_LEGACY:
+ esdhc_reset_tuning(mmc);
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ case MMC_HS_400:
+ mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
+ writel(mixctrl, ®s->mixctrl);
+ esdhc_set_strobe_dll(mmc);
+ break;
+ case MMC_HS:
+ case MMC_HS_52:
+ case MMC_HS_200:
+ case SD_HS:
+ case UHS_SDR12:
+ case UHS_SDR25:
+ case UHS_SDR50:
+ case UHS_SDR104:
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ case UHS_DDR50:
+ case MMC_DDR_52:
+ mixctrl |= MIX_CTRL_DDREN;
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ default:
+ printf("Not supported %d\n", mmc->selected_mode);
+ return -EINVAL;
+ }
+
+ priv->mode = mmc->selected_mode;
+
+ return esdhc_change_pinstate(mmc->dev);
+}
+
+static int esdhc_set_voltage(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret;
+
+ priv->signal_voltage = mmc->signal_voltage;
+ switch (mmc->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ if (priv->vs18_enable)
+ return -EIO;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+ ret = regulator_set_value(priv->vqmmc_dev, 3300000);
+ if (ret) {
+ printf("Setting to 3.3V error");
+ return -EIO;
+ }
+ /* Wait for 5ms */
+ mdelay(5);
+ }
+#endif
+
+ esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ if (!(esdhc_read32(®s->vendorspec) &
+ ESDHC_VENDORSPEC_VSELECT))
+ return 0;
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_180:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+ ret = regulator_set_value(priv->vqmmc_dev, 1800000);
+ if (ret) {
+ printf("Setting to 1.8V error");
+ return -EIO;
+ }
+ }
+#endif
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
+ return 0;
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_120:
+ return -ENOTSUPP;
+ default:
+ return 0;
+ }
+}
+
+static void esdhc_stop_tuning(struct mmc *mmc)
+{
+ struct mmc_cmd cmd;
+
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
+}
+
+static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ struct mmc *mmc = &plat->mmc;
+ u32 irqstaten = readl(®s->irqstaten);
+ u32 irqsigen = readl(®s->irqsigen);
+ int i, ret = -ETIMEDOUT;
+ u32 val, mixctrl;
+
+ /* clock tuning is not needed for upto 52MHz */
+ if (mmc->clock <= 52000000)
+ return 0;
+
+ /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ val = readl(®s->autoc12err);
+ mixctrl = readl(®s->mixctrl);
+ val &= ~MIX_CTRL_SMPCLK_SEL;
+ mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
+
+ val |= MIX_CTRL_EXE_TUNE;
+ mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
+
+ writel(val, ®s->autoc12err);
+ writel(mixctrl, ®s->mixctrl);
+ }
+
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
+ mixctrl = readl(®s->mixctrl);
+ mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
+ writel(mixctrl, ®s->mixctrl);
+
+ writel(IRQSTATEN_BRR, ®s->irqstaten);
+ writel(IRQSTATEN_BRR, ®s->irqsigen);
+
+ /*
+ * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
+ * of loops reaches 40 times.
+ */
+ for (i = 0; i < MAX_TUNING_LOOP; i++) {
+ u32 ctrl;
+
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
+ if (mmc->bus_width == 8)
+ writel(0x7080, ®s->blkattr);
+ else if (mmc->bus_width == 4)
+ writel(0x7040, ®s->blkattr);
+ } else {
+ writel(0x7040, ®s->blkattr);
+ }
+
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
+ val = readl(®s->mixctrl);
+ val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
+ writel(val, ®s->mixctrl);
+
+ /* We are using STD tuning, no need to check return value */
+ mmc_send_tuning(mmc, opcode, NULL);
+
+ ctrl = readl(®s->autoc12err);
+ if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
+ (ctrl & MIX_CTRL_SMPCLK_SEL)) {
+ /*
+ * need to wait some time, make sure sd/mmc fininsh
+ * send out tuning data, otherwise, the sd/mmc can't
+ * response to any command when the card still out
+ * put the tuning data.
+ */
+ mdelay(1);
+ ret = 0;
+ break;
+ }
+
+ /* Add 1ms delay for SD and eMMC */
+ mdelay(1);
+ }
+
+ writel(irqstaten, ®s->irqstaten);
+ writel(irqsigen, ®s->irqsigen);
+
+ esdhc_stop_tuning(mmc);
+
+ return ret;
+}
+#endif
+
+static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret __maybe_unused;
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ /* Select to use peripheral clock */
+ esdhc_clock_control(priv, false);
+ esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
+ esdhc_clock_control(priv, true);
+#endif
+ /* Set the clock speed */
+ if (priv->clock != mmc->clock)
+ set_sysctl(priv, mmc, mmc->clock);
+
+#ifdef MMC_SUPPORTS_TUNING
+ if (mmc->clk_disable) {
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
+#else
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+#endif
+ } else {
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
+ VENDORSPEC_CKEN);
+#else
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+ }
+
+ if (priv->mode != mmc->selected_mode) {
+ ret = esdhc_set_timing(mmc);
+ if (ret) {
+ printf("esdhc_set_timing error %d\n", ret);
+ return ret;
+ }
+ }
+
+ if (priv->signal_voltage != mmc->signal_voltage) {
+ ret = esdhc_set_voltage(mmc);
+ if (ret) {
+ printf("esdhc_set_voltage error %d\n", ret);
+ return ret;
+ }
+ }
+#endif
+
+ /* Set the bus width */
+ esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
+
+ if (mmc->bus_width == 4)
+ esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
+ else if (mmc->bus_width == 8)
+ esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
+
+ return 0;
+}
+
+static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ ulong start;
+
+ /* Reset the entire host controller */
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
+
+ /* Wait until the controller is available */
+ start = get_timer(0);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
+ if (get_timer(start) > 1000)
+ return -ETIMEDOUT;
+ }
+
+#if defined(CONFIG_FSL_USDHC)
+ /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
+ esdhc_write32(®s->mmcboot, 0x0);
+ /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
+ esdhc_write32(®s->mixctrl, 0x0);
+ esdhc_write32(®s->clktunectrlstatus, 0x0);
+
+ /* Put VEND_SPEC to default value */
+ if (priv->vs18_enable)
+ esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
+ ESDHC_VENDORSPEC_VSELECT));
+ else
+ esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
+
+ /* Disable DLL_CTRL delay line */
+ esdhc_write32(®s->dllctrl, 0x0);
+#endif
+
+#ifndef ARCH_MXC
+ /* Enable cache snooping */
+ esdhc_write32(®s->scr, 0x00000040);
+#endif
+
+#ifndef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#else
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
+#endif
+
+ /* Set the initial clock speed */
+ mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
+
+ /* Disable the BRR and BWR bits in IRQSTAT */
+ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
+
+#ifdef CONFIG_MCF5441x
+ esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
+#else
+ /* Put the PROCTL reg back to the default */
+ esdhc_write32(®s->proctl, PROCTL_INIT);
+#endif
+
+ /* Set timout to the maximum value */
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
+
+ return 0;
+}
+
+static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int timeout = 1000;
+
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+ if (CONFIG_ESDHC_DETECT_QUIRK)
+ return 1;
+#endif
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+ if (priv->non_removable)
+ return 1;
+#ifdef CONFIG_DM_GPIO
+ if (dm_gpio_is_valid(&priv->cd_gpio))
+ return dm_gpio_get_value(&priv->cd_gpio);
+#endif
+#endif
+
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
+ udelay(1000);
+
+ return timeout > 0;
+}
+
+static int esdhc_reset(struct fsl_esdhc *regs)
+{
+ ulong start;
+
+ /* reset the controller */
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
+
+ /* hardware clears the bit when it is done */
+ start = get_timer(0);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
+ if (get_timer(start) > 100) {
+ printf("MMC/SD: Reset never completed.\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int esdhc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_getcd_common(priv);
+}
+
+static int esdhc_init(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_init_common(priv, mmc);
+}
+
+static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int esdhc_set_ios(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_set_ios_common(priv, mmc);
+}
+
+static const struct mmc_ops esdhc_ops = {
+ .getcd = esdhc_getcd,
+ .init = esdhc_init,
+ .send_cmd = esdhc_send_cmd,
+ .set_ios = esdhc_set_ios,
+};
+#endif
+
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
+ struct fsl_esdhc_plat *plat)
+{
+ struct mmc_config *cfg;
+ struct fsl_esdhc *regs;
+ u32 caps, voltage_caps;
+ int ret;
+
+ if (!priv)
+ return -EINVAL;
+
+ regs = priv->esdhc_regs;
+
+ /* First reset the eSDHC controller */
+ ret = esdhc_reset(regs);
+ if (ret)
+ return ret;
+
+#ifdef CONFIG_MCF5441x
+ /* ColdFire, using SDHC_DATA[3] for card detection */
+ esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
+#endif
+
+#ifndef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
+ | SYSCTL_IPGEN | SYSCTL_CKEN);
+ /* Clearing tuning bits in case ROM has set it already */
+ esdhc_write32(®s->mixctrl, 0);
+ esdhc_write32(®s->autoc12err, 0);
+ esdhc_write32(®s->clktunectrlstatus, 0);
+#else
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
+ VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
+#endif
+
+ if (priv->vs18_enable)
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+ writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
+ cfg = &plat->cfg;
+#ifndef CONFIG_DM_MMC
+ memset(cfg, '\0', sizeof(*cfg));
+#endif
+
+ voltage_caps = 0;
+ caps = esdhc_read32(®s->hostcapblt);
+
+#ifdef CONFIG_MCF5441x
+ /*
+ * MCF5441x RM declares in more points that sdhc clock speed must
+ * never exceed 25 Mhz. From this, the HS bit needs to be disabled
+ * from host capabilities.
+ */
+ caps &= ~ESDHC_HOSTCAPBLT_HSS;
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
+ caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
+ ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
+#endif
+
+/* T4240 host controller capabilities register should have VS33 bit */
+#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ caps = caps | ESDHC_HOSTCAPBLT_VS33;
+#endif
+
+ if (caps & ESDHC_HOSTCAPBLT_VS18)
+ voltage_caps |= MMC_VDD_165_195;
+ if (caps & ESDHC_HOSTCAPBLT_VS30)
+ voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
+ if (caps & ESDHC_HOSTCAPBLT_VS33)
+ voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ cfg->name = "FSL_SDHC";
+#if !CONFIG_IS_ENABLED(DM_MMC)
+ cfg->ops = &esdhc_ops;
+#endif
+#ifdef CONFIG_SYS_SD_VOLTAGE
+ cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
+#else
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+#endif
+ if ((cfg->voltages & voltage_caps) == 0) {
+ printf("voltage not supported by controller\n");
+ return -1;
+ }
+
+ if (priv->bus_width == 8)
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ else if (priv->bus_width == 4)
+ cfg->host_caps = MMC_MODE_4BIT;
+
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+ cfg->host_caps |= MMC_MODE_DDR_52MHz;
+#endif
+
+ if (priv->bus_width > 0) {
+ if (priv->bus_width < 8)
+ cfg->host_caps &= ~MMC_MODE_8BIT;
+ if (priv->bus_width < 4)
+ cfg->host_caps &= ~MMC_MODE_4BIT;
+ }
+
+ if (caps & ESDHC_HOSTCAPBLT_HSS)
+ cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+ if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+ cfg->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
+ cfg->host_caps |= priv->caps;
+
+ cfg->f_min = 400000;
+ cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+ writel(0, ®s->dllctrl);
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ u32 val = readl(®s->tuning_ctrl);
+
+ val |= ESDHC_STD_TUNING_EN;
+ val &= ~ESDHC_TUNING_START_TAP_MASK;
+ val |= priv->tuning_start_tap;
+ val &= ~ESDHC_TUNING_STEP_MASK;
+ val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+ writel(val, ®s->tuning_ctrl);
+ }
+ }
+
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+ priv->wp_enable = cfg->wp_enable;
+ priv->vs18_enable = cfg->vs18_enable;
+
+ return 0;
+};
+
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+{
+ struct fsl_esdhc_plat *plat;
+ struct fsl_esdhc_priv *priv;
+ struct mmc *mmc;
+ int ret;
+
+ if (!cfg)
+ return -EINVAL;
+
+ priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
+ if (!priv)
+ return -ENOMEM;
+ plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
+ if (!plat) {
+ free(priv);
+ return -ENOMEM;
+ }
+
+ ret = fsl_esdhc_cfg_to_priv(cfg, priv);
+ if (ret) {
+ debug("%s xlate failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ ret = fsl_esdhc_init(priv, plat);
+ if (ret) {
+ debug("%s init failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ mmc = mmc_create(&plat->cfg, priv);
+ if (!mmc)
+ return -EIO;
+
+ priv->mmc = mmc;
+
+ return 0;
+}
+
+int fsl_esdhc_mmc_init(bd_t *bis)
+{
+ struct fsl_esdhc_cfg *cfg;
+
+ cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+ cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
+ return fsl_esdhc_initialize(bis, cfg);
+}
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+__weak int esdhc_status_fixup(void *blob, const char *compat)
+{
+#ifdef CONFIG_FSL_ESDHC_PIN_MUX
+ if (!hwconfig("esdhc")) {
+ do_fixup_by_compat(blob, compat, "status", "disabled",
+ sizeof("disabled"), 1);
+ return 1;
+ }
+#endif
+ return 0;
+}
+
+void fdt_fixup_esdhc(void *blob, bd_t *bd)
+{
+ const char *compat = "fsl,esdhc";
+
+ if (esdhc_status_fixup(blob, compat))
+ return;
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
+ gd->arch.sdhc_clk, 1);
+#else
+ do_fixup_by_compat_u32(blob, compat, "clock-frequency",
+ gd->arch.sdhc_clk, 1);
+#endif
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+#include <asm/arch/clock.h>
+__weak void init_clk_usdhc(u32 index)
+{
+}
+
+static int fsl_esdhc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ struct esdhc_soc_data *data =
+ (struct esdhc_soc_data *)dev_get_driver_data(dev);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *vqmmc_dev;
+#endif
+ fdt_addr_t addr;
+ unsigned int val;
+ struct mmc *mmc;
+#if !CONFIG_IS_ENABLED(BLK)
+ struct blk_desc *bdesc;
+#endif
+ int ret;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->esdhc_regs = (struct fsl_esdhc *)addr;
+ priv->dev = dev;
+ priv->mode = -1;
+ if (data) {
+ priv->flags = data->flags;
+ priv->caps = data->caps;
+ }
+
+ val = dev_read_u32_default(dev, "bus-width", -1);
+ if (val == 8)
+ priv->bus_width = 8;
+ else if (val == 4)
+ priv->bus_width = 4;
+ else
+ priv->bus_width = 1;
+
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
+ priv->tuning_step = val;
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
+ ESDHC_TUNING_START_TAP_DEFAULT);
+ priv->tuning_start_tap = val;
+ val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
+ priv->strobe_dll_delay_target = val;
+
+ if (dev_read_bool(dev, "non-removable")) {
+ priv->non_removable = 1;
+ } else {
+ priv->non_removable = 0;
+#ifdef CONFIG_DM_GPIO
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN);
+#endif
+ }
+
+ if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
+ priv->wp_enable = 1;
+ } else {
+ priv->wp_enable = 0;
+#ifdef CONFIG_DM_GPIO
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+ GPIOD_IS_IN);
+#endif
+ }
+
+ priv->vs18_enable = 0;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ /*
+ * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
+ * otherwise, emmc will work abnormally.
+ */
+ ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
+ if (ret) {
+ dev_dbg(dev, "no vqmmc-supply\n");
+ } else {
+ ret = regulator_set_enable(vqmmc_dev, true);
+ if (ret) {
+ dev_err(dev, "fail to enable vqmmc-supply\n");
+ return ret;
+ }
+
+ if (regulator_get_value(vqmmc_dev) == 1800000)
+ priv->vs18_enable = 1;
+ }
+#endif
+
+ if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
+ priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
+
+ /*
+ * TODO:
+ * Because lack of clk driver, if SDHC clk is not enabled,
+ * need to enable it first before this driver is invoked.
+ *
+ * we use MXC_ESDHC_CLK to get clk freq.
+ * If one would like to make this function work,
+ * the aliases should be provided in dts as this:
+ *
+ * aliases {
+ * mmc0 = &usdhc1;
+ * mmc1 = &usdhc2;
+ * mmc2 = &usdhc3;
+ * mmc3 = &usdhc4;
+ * };
+ * Then if your board only supports mmc2 and mmc3, but we can
+ * correctly get the seq as 2 and 3, then let mxc_get_clock
+ * work as expected.
+ */
+
+ init_clk_usdhc(dev->seq);
+
+ if (IS_ENABLED(CONFIG_CLK)) {
+ /* Assigned clock already set clock */
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
+
+ priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+ } else {
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
+ }
+ }
+
+ ret = fsl_esdhc_init(priv, plat);
+ if (ret) {
+ dev_err(dev, "fsl_esdhc_init failure\n");
+ return ret;
+ }
+
+ mmc = &plat->mmc;
+ mmc->cfg = &plat->cfg;
+ mmc->dev = dev;
+#if !CONFIG_IS_ENABLED(BLK)
+ mmc->priv = priv;
+
+ /* Setup dsr related values */
+ mmc->dsr_imp = 0;
+ mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
+ /* Setup the universal parts of the block interface just once */
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->if_type = IF_TYPE_MMC;
+ bdesc->removable = 1;
+ bdesc->devnum = mmc_get_next_devnum();
+ bdesc->block_read = mmc_bread;
+ bdesc->block_write = mmc_bwrite;
+ bdesc->block_erase = mmc_berase;
+
+ /* setup initial part type */
+ bdesc->part_type = mmc->cfg->part_type;
+ mmc_list_add(mmc);
+#endif
+
+ upriv->mmc = mmc;
+
+ return esdhc_init_common(priv, mmc);
+}
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_get_cd(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_getcd_common(priv);
+}
+
+static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
+}
+
+static int fsl_esdhc_set_ios(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_set_ios_common(priv, &plat->mmc);
+}
+
+static const struct dm_mmc_ops fsl_esdhc_ops = {
+ .get_cd = fsl_esdhc_get_cd,
+ .send_cmd = fsl_esdhc_send_cmd,
+ .set_ios = fsl_esdhc_set_ios,
+#ifdef MMC_SUPPORTS_TUNING
+ .execute_tuning = fsl_esdhc_execute_tuning,
+#endif
+};
+#endif
+
+static struct esdhc_soc_data usdhc_imx7d_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+ .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
+ MMC_MODE_HS_52MHz | MMC_MODE_HS,
+};
+
+static const struct udevice_id fsl_esdhc_ids[] = {
+ { .compatible = "fsl,imx53-esdhc", },
+ { .compatible = "fsl,imx6ul-usdhc", },
+ { .compatible = "fsl,imx6sx-usdhc", },
+ { .compatible = "fsl,imx6sl-usdhc", },
+ { .compatible = "fsl,imx6q-usdhc", },
+ { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
+ { .compatible = "fsl,imx7ulp-usdhc", },
+ { .compatible = "fsl,esdhc", },
+ { /* sentinel */ }
+};
+
+#if CONFIG_IS_ENABLED(BLK)
+static int fsl_esdhc_bind(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+#endif
+
+U_BOOT_DRIVER(fsl_esdhc) = {
+ .name = "fsl-esdhc-mmc",
+ .id = UCLASS_MMC,
+ .of_match = fsl_esdhc_ids,
+ .ops = &fsl_esdhc_ops,
+#if CONFIG_IS_ENABLED(BLK)
+ .bind = fsl_esdhc_bind,
+#endif
+ .probe = fsl_esdhc_probe,
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+};
+#endif
clk_release_bulk(&glue->clks);
- return dm_scan_fdt_dev(dev);
+ return 0;
}
static const struct udevice_id dwc3_glue_ids[] = {
U_BOOT_DRIVER(dwc3_generic_wrapper) = {
.name = "dwc3-generic-wrapper",
- .id = UCLASS_MISC,
+ .id = UCLASS_NOP,
.of_match = dwc3_glue_ids,
.bind = dwc3_glue_bind,
.probe = dwc3_glue_probe,
return 0;
}
+static int ehci_usb_bind(struct udevice *dev)
+{
+ /*
+ * TODO:
+ * This driver is only partly converted to DT probing and still uses
+ * a tremendous amount of hard-coded addresses. To make things worse,
+ * the driver depends on specific sequential indexing of controllers,
+ * from which it derives offsets in the PHY and ANATOP register sets.
+ *
+ * Here we attempt to calculate these indexes from DT information as
+ * well as we can. The USB controllers on all existing iMX6/iMX7 SoCs
+ * are placed next to each other, at addresses incremented by 0x200.
+ * Thus, the index is derived from the multiple of 0x200 offset from
+ * the first controller address.
+ *
+ * However, to complete conversion of this driver to DT probing, the
+ * following has to be done:
+ * - DM clock framework support for iMX must be implemented
+ * - usb_power_config() has to be converted to clock framework
+ * -> Thus, the ad-hoc "index" variable goes away.
+ * - USB PHY handling has to be factored out into separate driver
+ * -> Thus, the ad-hoc "index" variable goes away from the PHY
+ * code, the PHY driver must parse it's address from DT. This
+ * USB driver must find the PHY driver via DT phandle.
+ * -> usb_power_config() shall be moved to PHY driver
+ * With these changes in place, the ad-hoc indexing goes away and
+ * the driver is fully converted to DT probing.
+ */
+ fdt_size_t size;
+ fdt_addr_t addr = devfdt_get_addr_size_index(dev, 0, &size);
+
+ dev->req_seq = (addr - USB_BASE_ADDR) / size;
+
+ return 0;
+}
+
static int ehci_usb_probe(struct udevice *dev)
{
struct usb_platdata *plat = dev_get_platdata(dev);
.id = UCLASS_USB,
.of_match = mx6_usb_ids,
.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .bind = ehci_usb_bind,
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
return log_ret(ret);
ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
+ if (ret == -ENOSYS && !priv->polarity)
+ ret = 0;
+
return log_ret(ret);
}
#undef CONFIG_BOOTM_NETBSD
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#undef CONFIG_BOOTM_NETBSD
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define CONFIG_IMX_BOOTAUX
#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
#define I2C_MUX_CH_DEFAULT 0x8
"fdt_addr_r=0x02600000\0" \
"ramdisk_addr_r=0x02700000\0"
+#if CONFIG_IS_ENABLED(CMD_MMC)
+ #define BOOT_TARGET_MMC(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1)
+#else
+ #define BOOT_TARGET_MMC(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+ #define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+ #define BOOT_TARGET_USB(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_PXE)
+ #define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+ #define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+ #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+ #define BOOT_TARGET_DHCP(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
+ BOOT_TARGET_MMC(func) \
+ BOOT_TARGET_USB(func) \
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func)
+
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
func(SATA, sata, 0) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_MTD, /* Memory Technology Device (MTD) device */
+ UCLASS_NOP, /* No-op devices */
UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
UCLASS_NVME, /* NVM Express device */
UCLASS_PANEL, /* Display panel, such as an LCD */
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#define BCM2835_AUX_CLOCK_UART 0
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#define BCM2835_PLLA 0
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H
+#define _DT_BINDINGS_MICROCHIP_LAN78XX_H
+
+/* LED modes for LAN7800/LAN7850 embedded PHY */
+
+#define LAN78XX_LINK_ACTIVITY 0
+#define LAN78XX_LINK_1000_ACTIVITY 1
+#define LAN78XX_LINK_100_ACTIVITY 2
+#define LAN78XX_LINK_10_ACTIVITY 3
+#define LAN78XX_LINK_100_1000_ACTIVITY 4
+#define LAN78XX_LINK_10_1000_ACTIVITY 5
+#define LAN78XX_LINK_10_100_ACTIVITY 6
+#define LAN78XX_DUPLEX_COLLISION 8
+#define LAN78XX_COLLISION 9
+#define LAN78XX_ACTIVITY 10
+#define LAN78XX_AUTONEG_FAULT 12
+#define LAN78XX_FORCE_LED_OFF 14
+#define LAN78XX_FORCE_LED_ON 15
+
+#endif
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Header providing constants for bcm2835 pinctrl bindings.
*
* Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H
+#define _DT_BINDINGS_ARM_BCM2835_PM_H
+
+#define BCM2835_POWER_DOMAIN_GRAFX 0
+#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1
+#define BCM2835_POWER_DOMAIN_IMAGE 2
+#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3
+#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4
+#define BCM2835_POWER_DOMAIN_IMAGE_H264 5
+#define BCM2835_POWER_DOMAIN_USB 6
+#define BCM2835_POWER_DOMAIN_DSI0 7
+#define BCM2835_POWER_DOMAIN_DSI1 8
+#define BCM2835_POWER_DOMAIN_CAM0 9
+#define BCM2835_POWER_DOMAIN_CAM1 10
+#define BCM2835_POWER_DOMAIN_CCP2TX 11
+#define BCM2835_POWER_DOMAIN_HDMI 12
+
+#define BCM2835_POWER_DOMAIN_COUNT 13
+
+#define BCM2835_RESET_V3D 0
+#define BCM2835_RESET_ISP 1
+#define BCM2835_RESET_H264 2
+
+#define BCM2835_RESET_COUNT 3
+
+#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */
#ifndef __FSL_ESDHC_H__
#define __FSL_ESDHC_H__
-#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
-#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
-#endif
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
-#define VENDORSPEC_CKEN 0x00004000
-#define VENDORSPEC_PEREN 0x00002000
-#define VENDORSPEC_HCKEN 0x00001000
-#define VENDORSPEC_IPGEN 0x00000800
-#define VENDORSPEC_INIT 0x20007809
-
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define IRQSTAT_AC12E (0x01000000)
#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
-#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
-
-/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
-#define MIX_CTRL_DDREN BIT(3)
-#define MIX_CTRL_DTDSEL_READ BIT(4)
-#define MIX_CTRL_AC23EN BIT(7)
-#define MIX_CTRL_EXE_TUNE BIT(22)
-#define MIX_CTRL_SMPCLK_SEL BIT(23)
-#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
-#define MIX_CTRL_FBCLK_SEL BIT(25)
-#define MIX_CTRL_HS400_EN BIT(26)
-#define MIX_CTRL_HS400_ES BIT(27)
-/* Bits 3 and 6 are not SDHCI standard definitions */
-#define MIX_CTRL_SDHCI_MASK 0xb7
-/* Tuning bits */
-#define MIX_CTRL_TUNING_MASK 0x03c00000
-
-/* strobe dll register */
-#define ESDHC_STROBE_DLL_CTRL 0x70
-#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
-#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
-
-#define ESDHC_STROBE_DLL_STATUS 0x74
-#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
-#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
-#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
-
-#define ESDHC_STD_TUNING_EN BIT(24)
-/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
-#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
-#define ESDHC_TUNING_START_TAP_MASK 0xff
-#define ESDHC_TUNING_STEP_MASK 0x00070000
-#define ESDHC_TUNING_STEP_SHIFT 16
-
-#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
-#define ESDHC_FLAG_ENGCM07207 BIT(2)
-#define ESDHC_FLAG_USDHC BIT(3)
-#define ESDHC_FLAG_MAN_TUNING BIT(4)
-#define ESDHC_FLAG_STD_TUNING BIT(5)
-#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
-#define ESDHC_FLAG_ERR004536 BIT(7)
-#define ESDHC_FLAG_HS200 BIT(8)
-#define ESDHC_FLAG_HS400 BIT(9)
-#define ESDHC_FLAG_ERR010450 BIT(10)
-#define ESDHC_FLAG_HS400_ES BIT(11)
-
struct fsl_esdhc_cfg {
phys_addr_t esdhc_base;
u32 sdhc_clk;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2019 NXP
+ * Yangbo Lu <yangbo.lu@nxp.com>
+ *
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ */
+
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/byteorder.h>
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL 0x0002e02c
+#define SYSCTL_INITA 0x08000000
+#define SYSCTL_TIMEOUT_MASK 0x000f0000
+#define SYSCTL_CLOCK_MASK 0x0000fff0
+#if !defined(CONFIG_FSL_USDHC)
+#define SYSCTL_CKEN 0x00000008
+#define SYSCTL_PEREN 0x00000004
+#define SYSCTL_HCKEN 0x00000002
+#define SYSCTL_IPGEN 0x00000001
+#endif
+#define SYSCTL_RSTA 0x01000000
+#define SYSCTL_RSTC 0x02000000
+#define SYSCTL_RSTD 0x04000000
+
+#define VENDORSPEC_CKEN 0x00004000
+#define VENDORSPEC_PEREN 0x00002000
+#define VENDORSPEC_HCKEN 0x00001000
+#define VENDORSPEC_IPGEN 0x00000800
+#define VENDORSPEC_INIT 0x20007809
+
+#define IRQSTAT 0x0002e030
+#define IRQSTAT_DMAE (0x10000000)
+#define IRQSTAT_AC12E (0x01000000)
+#define IRQSTAT_DEBE (0x00400000)
+#define IRQSTAT_DCE (0x00200000)
+#define IRQSTAT_DTOE (0x00100000)
+#define IRQSTAT_CIE (0x00080000)
+#define IRQSTAT_CEBE (0x00040000)
+#define IRQSTAT_CCE (0x00020000)
+#define IRQSTAT_CTOE (0x00010000)
+#define IRQSTAT_CINT (0x00000100)
+#define IRQSTAT_CRM (0x00000080)
+#define IRQSTAT_CINS (0x00000040)
+#define IRQSTAT_BRR (0x00000020)
+#define IRQSTAT_BWR (0x00000010)
+#define IRQSTAT_DINT (0x00000008)
+#define IRQSTAT_BGE (0x00000004)
+#define IRQSTAT_TC (0x00000002)
+#define IRQSTAT_CC (0x00000001)
+
+#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+ IRQSTAT_DMAE)
+#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
+
+#define IRQSTATEN 0x0002e034
+#define IRQSTATEN_DMAE (0x10000000)
+#define IRQSTATEN_AC12E (0x01000000)
+#define IRQSTATEN_DEBE (0x00400000)
+#define IRQSTATEN_DCE (0x00200000)
+#define IRQSTATEN_DTOE (0x00100000)
+#define IRQSTATEN_CIE (0x00080000)
+#define IRQSTATEN_CEBE (0x00040000)
+#define IRQSTATEN_CCE (0x00020000)
+#define IRQSTATEN_CTOE (0x00010000)
+#define IRQSTATEN_CINT (0x00000100)
+#define IRQSTATEN_CRM (0x00000080)
+#define IRQSTATEN_CINS (0x00000040)
+#define IRQSTATEN_BRR (0x00000020)
+#define IRQSTATEN_BWR (0x00000010)
+#define IRQSTATEN_DINT (0x00000008)
+#define IRQSTATEN_BGE (0x00000004)
+#define IRQSTATEN_TC (0x00000002)
+#define IRQSTATEN_CC (0x00000001)
+
+#define ESDHCCTL 0x0002e40c
+#define ESDHCCTL_PCS (0x00080000)
+
+#define PRSSTAT 0x0002e024
+#define PRSSTAT_DAT0 (0x01000000)
+#define PRSSTAT_CLSL (0x00800000)
+#define PRSSTAT_WPSPL (0x00080000)
+#define PRSSTAT_CDPL (0x00040000)
+#define PRSSTAT_CINS (0x00010000)
+#define PRSSTAT_BREN (0x00000800)
+#define PRSSTAT_BWEN (0x00000400)
+#define PRSSTAT_SDSTB (0X00000008)
+#define PRSSTAT_DLA (0x00000004)
+#define PRSSTAT_CICHB (0x00000002)
+#define PRSSTAT_CIDHB (0x00000001)
+
+#define PROCTL 0x0002e028
+#define PROCTL_INIT 0x00000020
+#define PROCTL_DTW_4 0x00000002
+#define PROCTL_DTW_8 0x00000004
+#define PROCTL_D3CD 0x00000008
+
+#define CMDARG 0x0002e008
+
+#define XFERTYP 0x0002e00c
+#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL 0x0
+#define XFERTYP_CMDTYP_SUSPEND 0x00400000
+#define XFERTYP_CMDTYP_RESUME 0x00800000
+#define XFERTYP_CMDTYP_ABORT 0x00c00000
+#define XFERTYP_DPSEL 0x00200000
+#define XFERTYP_CICEN 0x00100000
+#define XFERTYP_CCCEN 0x00080000
+#define XFERTYP_RSPTYP_NONE 0
+#define XFERTYP_RSPTYP_136 0x00010000
+#define XFERTYP_RSPTYP_48 0x00020000
+#define XFERTYP_RSPTYP_48_BUSY 0x00030000
+#define XFERTYP_MSBSEL 0x00000020
+#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_DDREN 0x00000008
+#define XFERTYP_AC12EN 0x00000004
+#define XFERTYP_BCEN 0x00000002
+#define XFERTYP_DMAEN 0x00000001
+
+#define CINS_TIMEOUT 1000
+#define PIO_TIMEOUT 500
+
+#define DSADDR 0x2e004
+
+#define CMDRSP0 0x2e010
+#define CMDRSP1 0x2e014
+#define CMDRSP2 0x2e018
+#define CMDRSP3 0x2e01c
+
+#define DATPORT 0x2e020
+
+#define WML 0x2e044
+#define WML_WRITE 0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX 0x80
+#define WML_WR_WML_MAX 0x80
+#define WML_RD_WML_MAX_VAL 0x0
+#define WML_WR_WML_MAX_VAL 0x0
+#define WML_RD_WML_MASK 0x7f
+#define WML_WR_WML_MASK 0x7f0000
+#else
+#define WML_RD_WML_MAX 0x10
+#define WML_WR_WML_MAX 0x80
+#define WML_RD_WML_MAX_VAL 0x10
+#define WML_WR_WML_MAX_VAL 0x80
+#define WML_RD_WML_MASK 0xff
+#define WML_WR_WML_MASK 0xff0000
+#endif
+
+#define BLKATTR 0x2e004
+#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x) (x & 0x1fff)
+#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18 0x04000000
+#define ESDHC_HOSTCAPBLT_VS30 0x02000000
+#define ESDHC_HOSTCAPBLT_VS33 0x01000000
+#define ESDHC_HOSTCAPBLT_SRS 0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
+#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
+/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+#define MIX_CTRL_DDREN BIT(3)
+#define MIX_CTRL_DTDSEL_READ BIT(4)
+#define MIX_CTRL_AC23EN BIT(7)
+#define MIX_CTRL_EXE_TUNE BIT(22)
+#define MIX_CTRL_SMPCLK_SEL BIT(23)
+#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
+#define MIX_CTRL_FBCLK_SEL BIT(25)
+#define MIX_CTRL_HS400_EN BIT(26)
+#define MIX_CTRL_HS400_ES BIT(27)
+/* Bits 3 and 6 are not SDHCI standard definitions */
+#define MIX_CTRL_SDHCI_MASK 0xb7
+/* Tuning bits */
+#define MIX_CTRL_TUNING_MASK 0x03c00000
+
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL 0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
+#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+
+#define ESDHC_STROBE_DLL_STATUS 0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
+#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
+
+#define ESDHC_STD_TUNING_EN BIT(24)
+/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
+#define ESDHC_TUNING_START_TAP_MASK 0xff
+#define ESDHC_TUNING_STEP_MASK 0x00070000
+#define ESDHC_TUNING_STEP_SHIFT 16
+
+#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
+#define ESDHC_FLAG_ENGCM07207 BIT(2)
+#define ESDHC_FLAG_USDHC BIT(3)
+#define ESDHC_FLAG_MAN_TUNING BIT(4)
+#define ESDHC_FLAG_STD_TUNING BIT(5)
+#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
+#define ESDHC_FLAG_ERR004536 BIT(7)
+#define ESDHC_FLAG_HS200 BIT(8)
+#define ESDHC_FLAG_HS400 BIT(9)
+#define ESDHC_FLAG_ERR010450 BIT(10)
+#define ESDHC_FLAG_HS400_ES BIT(11)
+
+struct fsl_esdhc_cfg {
+ phys_addr_t esdhc_base;
+ u32 sdhc_clk;
+ u8 max_bus_width;
+ int wp_enable;
+ int vs18_enable; /* Use 1.8V if set to 1 */
+ struct mmc_config cfg;
+};
+
+/* Select the correct accessors depending on endianess */
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32 clrbits_le32
+#define esdhc_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32 in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32 clrbits_le32
+#define esdhc_setbits32 setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define esdhc_read32 in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#else
+#error "Endianess is not defined: please fix to continue"
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+int fsl_esdhc_mmc_init(bd_t *bis);
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+
+#endif /* __FSL_ESDHC_IMX_H__ */
# Copyright (c) 2013 Google, Inc
obj-$(CONFIG_UT_DM) += bus.o
+obj-$(CONFIG_UT_DM) += nop.o
obj-$(CONFIG_UT_DM) += test-driver.o
obj-$(CONFIG_UT_DM) += test-fdt.o
obj-$(CONFIG_UT_DM) += test-main.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for the NOP uclass
+ *
+ * (C) Copyright 2019 - Texas Instruments Incorporated - http://www.ti.com/
+ * Jean-Jacques Hiblot <jjhiblot@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <dm/lists.h>
+#include <dm/device.h>
+#include <dm/test.h>
+#include <misc.h>
+#include <test/ut.h>
+
+static int noptest_bind(struct udevice *parent)
+{
+ ofnode ofnode = dev_read_first_subnode(parent);
+
+ while (ofnode_valid(ofnode)) {
+ struct udevice *dev;
+ const char *bind_flag = ofnode_read_string(ofnode, "bind");
+
+ if (bind_flag && (strcmp(bind_flag, "True") == 0))
+ lists_bind_fdt(parent, ofnode, &dev, false);
+ ofnode = dev_read_next_subnode(ofnode);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id noptest1_ids[] = {
+ {
+ .compatible = "sandbox,nop_sandbox1",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(noptest_drv1) = {
+ .name = "noptest1_drv",
+ .of_match = noptest1_ids,
+ .id = UCLASS_NOP,
+ .bind = noptest_bind,
+};
+
+static const struct udevice_id noptest2_ids[] = {
+ {
+ .compatible = "sandbox,nop_sandbox2",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(noptest_drv2) = {
+ .name = "noptest2_drv",
+ .of_match = noptest2_ids,
+ .id = UCLASS_NOP,
+};
+
+static int dm_test_nop(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "nop-test_0", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "nop-test_1", &dev));
+ ut_asserteq(-ENODEV,
+ uclass_get_device_by_name(UCLASS_NOP, "nop-test_2", &dev));
+
+ return 0;
+}
+
+DM_TEST(dm_test_nop, DM_TESTF_FLAT_TREE | DM_TESTF_SCAN_FDT);
projects / platform / kernel / u-boot.git / commitdiff