CONFIG_CMD_BMP * BMP support
CONFIG_CMD_BSP * Board specific commands
CONFIG_CMD_BOOTD bootd
+ CONFIG_CMD_BOOTI * ARM64 Linux kernel Image support
CONFIG_CMD_CACHE * icache, dcache
CONFIG_CMD_CLK * clock command support
CONFIG_CMD_CONSOLE coninfo
config TARGET_STAMP9G20
bool "Support stamp9g20"
-config TARGET_CAM_ENC_4XX
- bool "Support cam_enc_4xx"
+config ARCH_DAVINCI
+ bool "TI DaVinci"
+ help
+ Support for TI's DaVinci platform.
-config TARGET_IPAM390
- bool "Support ipam390"
-
-config TARGET_DA830EVM
- bool "Support da830evm"
-
-config TARGET_DA850EVM
- bool "Support da850evm"
-
-config TARGET_HAWKBOARD
- bool "Support hawkboard"
-
-config TARGET_DAVINCI_DM355EVM
- bool "Support davinci_dm355evm"
-
-config TARGET_DAVINCI_DM355LEOPARD
- bool "Support davinci_dm355leopard"
-
-config TARGET_DAVINCI_DM365EVM
- bool "Support davinci_dm365evm"
-
-config TARGET_DAVINCI_DM6467EVM
- bool "Support davinci_dm6467evm"
-
-config TARGET_DAVINCI_DVEVM
- bool "Support davinci_dvevm"
-
-config TARGET_EA20
- bool "Support ea20"
-
-config TARGET_DAVINCI_SCHMOOGIE
- bool "Support davinci_schmoogie"
-
-config TARGET_DAVINCI_SFFSDR
- bool "Support davinci_sffsdr"
-
-config TARGET_DAVINCI_SONATA
- bool "Support davinci_sonata"
-
-config TARGET_ENBW_CMC
- bool "Support enbw_cmc"
-
-config TARGET_CALIMAIN
- bool "Support calimain"
-
-config TARGET_LSXL
- bool "Support lsxl"
-
-config TARGET_POGO_E02
- bool "Support pogo_e02"
-
-config TARGET_DNS325
- bool "Support dns325"
-
-config TARGET_ICONNECT
- bool "Support iconnect"
-
-config TARGET_TK71
- bool "Support tk71"
-
-config TARGET_KM_KIRKWOOD
- bool "Support km_kirkwood"
-
-config TARGET_NET2BIG_V2
- bool "Support net2big_v2"
-
-config TARGET_NETSPACE_V2
- bool "Support netspace_v2"
-
-config TARGET_WIRELESS_SPACE
- bool "Support wireless_space"
-
-config TARGET_DREAMPLUG
- bool "Support dreamplug"
-
-config TARGET_GURUPLUG
- bool "Support guruplug"
-
-config TARGET_MV88F6281GTW_GE
- bool "Support mv88f6281gtw_ge"
-
-config TARGET_OPENRD
- bool "Support openrd"
-
-config TARGET_RD6281A
- bool "Support rd6281a"
-
-config TARGET_SHEEVAPLUG
- bool "Support sheevaplug"
-
-config TARGET_IB62X0
- bool "Support ib62x0"
-
-config TARGET_DOCKSTAR
- bool "Support dockstar"
-
-config TARGET_GOFLEXHOME
- bool "Support goflexhome"
+config KIRKWOOD
+ bool "Marvell Kirkwood"
config TARGET_DEVKIT3250
bool "Support devkit3250"
config TARGET_SC_SPS_1
bool "Support sc_sps_1"
-config TARGET_NHK8815
- bool "Support nhk8815"
+config ARCH_NOMADIK
+ bool "ST-Ericsson Nomadik"
-config TARGET_EDMINIV2
- bool "Support edminiv2"
+config ORION5X
+ bool "Marvell Orion"
config TARGET_DKB
bool "Support dkb"
config TARGET_X600
bool "Support x600"
-config TARGET_VERSATILEAB
- bool "Support versatileab"
-
-config TARGET_VERSATILEPB
- bool "Support versatilepb"
-
-config TARGET_VERSATILEQEMU
- bool "Support versatileqemu"
+config ARCH_VERSATILE
+ bool "ARM Ltd. Versatile family"
config TARGET_INTEGRATORCP_CM1136
bool "Support integratorcp_cm1136"
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
-config TARGET_ARNDALE
- bool "Support arndale"
-
-config TARGET_ORIGEN
- bool "Support origen"
-
-config TARGET_SMDK5250
- bool "Support smdk5250"
-
-config TARGET_SNOW
- bool "Support snow"
-
-config TARGET_PEACH_PIT
- bool "Support peach-pit"
-
-config TARGET_SMDK5420
- bool "Support smdk5420"
-
-config TARGET_SMDKV310
- bool "Support smdkv310"
+config TARGET_BCM958300K
+ bool "Support bcm958300k"
-config TARGET_TRATS
- bool "Support trats"
+config TARGET_BCM958622HR
+ bool "Support bcm958622hr"
-config TARGET_TRATS2
- bool "Support trats2"
+config ARCH_EXYNOS
+ bool "Samsung EXYNOS"
-config TARGET_S5PC210_UNIVERSAL
- bool "Support s5pc210_universal"
+config ARCH_HIGHBANK
+ bool "Calxeda Highbank"
-config TARGET_HIGHBANK
- bool "Support highbank"
-
-config TARGET_K2E_EVM
- bool "Support k2e_evm"
-
-config TARGET_K2HK_EVM
- bool "Support k2hk_evm"
+config ARCH_KEYSTONE
+ bool "TI Keystone"
config TARGET_M53EVK
bool "Support m53evk"
config TARGET_HUMMINGBOARD
bool "Support hummingboard"
-config TARGET_OMAP3_OVERO
- bool "Support omap3_overo"
-
-config TARGET_OMAP3_PANDORA
- bool "Support omap3_pandora"
-
-config TARGET_ECO5PK
- bool "Support eco5pk"
-
-config TARGET_DIG297
- bool "Support dig297"
-
-config TARGET_CM_T35
- bool "Support cm_t35"
-
-config TARGET_TRICORDER
- bool "Support tricorder"
-
-config TARGET_MCX
- bool "Support mcx"
-
-config TARGET_OMAP3_IGEP00X0
- bool "Support omap3_igep00x0"
-
-config TARGET_AM3517_EVM
- bool "Support am3517_evm"
-
-config TARGET_OMAP3_LOGIC
- bool "Support omap3_logic"
-
-config TARGET_OMAP3_ZOOM1
- bool "Support omap3_zoom1"
-
-config TARGET_OMAP3_MVBLX
- bool "Support omap3_mvblx"
+config OMAP34XX
+ bool "OMAP34XX SoC"
-config TARGET_NOKIA_RX51
- bool "Support nokia_rx51"
+config OMAP44XX
+ bool "OMAP44XX SoC"
-config TARGET_TAO3530
- bool "Support tao3530"
+config OMAP54XX
+ bool "OMAP54XX SoC"
-config TARGET_TWISTER
- bool "Support twister"
-
-config TARGET_MT_VENTOUX
- bool "Support mt_ventoux"
-
-config TARGET_AM3517_CRANE
- bool "Support am3517_crane"
-
-config TARGET_OMAP3_BEAGLE
- bool "Support omap3_beagle"
-
-config TARGET_OMAP3_EVM
- bool "Support omap3_evm"
-
-config TARGET_OMAP3_EVM_QUICK_MMC
- bool "Support omap3_evm_quick_mmc"
-
-config TARGET_OMAP3_EVM_QUICK_NAND
- bool "Support omap3_evm_quick_nand"
-
-config TARGET_OMAP3_SDP3430
- bool "Support omap3_sdp3430"
-
-config TARGET_DEVKIT8000
- bool "Support devkit8000"
-
-config TARGET_DUOVERO
- bool "Support duovero"
-
-config TARGET_OMAP4_PANDA
- bool "Support omap4_panda"
-
-config TARGET_OMAP4_SDP4430
- bool "Support omap4_sdp4430"
-
-config TARGET_CM_T54
- bool "Support cm_t54"
-
-config TARGET_DRA7XX_EVM
- bool "Support dra7xx_evm"
-
-config TARGET_OMAP5_UEVM
- bool "Support omap5_uevm"
-
-config TARGET_ARMADILLO_800EVA
- bool "Support armadillo-800eva"
-
-config TARGET_KZM9G
- bool "Support kzm9g"
-
-config TARGET_ALT
- bool "Support alt"
-
-config TARGET_KOELSCH
- bool "Support koelsch"
-
-config TARGET_LAGER
- bool "Support lager"
+config RMOBILE
+ bool "Renesas ARM SoCs"
config TARGET_S5P_GONI
bool "Support s5p_goni"
config TARGET_VF610TWR
bool "Support vf610twr"
-config TARGET_ZYNQ_MICROZED
- bool "Support zynq_microzed"
-
-config TARGET_ZYNQ_ZC70X
- bool "Support zynq_zc70x"
-
-config TARGET_ZYNQ_ZC770
- bool "Support zynq_zc770"
-
-config TARGET_ZYNQ_ZED
- bool "Support zynq_zed"
-
-config TARGET_MEDCOM_WIDE
- bool "Support medcom-wide"
-
-config TARGET_PLUTUX
- bool "Support plutux"
-
-config TARGET_TEC
- bool "Support tec"
-
-config TARGET_PAZ00
- bool "Support paz00"
+config ZYNQ
+ bool "Xilinx Zynq Platform"
-config TARGET_TRIMSLICE
- bool "Support trimslice"
-
-config TARGET_HARMONY
- bool "Support harmony"
-
-config TARGET_SEABOARD
- bool "Support seaboard"
-
-config TARGET_VENTANA
- bool "Support ventana"
-
-config TARGET_WHISTLER
- bool "Support whistler"
-
-config TARGET_COLIBRI_T20_IRIS
- bool "Support colibri_t20_iris"
-
-config TARGET_COLIBRI_T30
- bool "Support Colibri T30"
-
-config TARGET_TEC_NG
- bool "Support tec-ng"
-
-config TARGET_BEAVER
- bool "Support beaver"
-
-config TARGET_CARDHU
- bool "Support cardhu"
-
-config TARGET_DALMORE
- bool "Support dalmore"
-
-config TARGET_JETSON_TK1
- bool "Support jetson-tk1"
-
-config TARGET_VENICE2
- bool "Support venice2"
+config TEGRA
+ bool "NVIDIA Tegra"
+ select SPL
config TARGET_VEXPRESS_AEMV8A
bool "Support vexpress_aemv8a"
endchoice
-source "board/8dtech/eco5pk/Kconfig"
+source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
+
+source "arch/arm/cpu/armv7/exynos/Kconfig"
+
+source "arch/arm/cpu/armv7/highbank/Kconfig"
+
+source "arch/arm/cpu/armv7/keystone/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
+
+source "arch/arm/cpu/armv7/omap3/Kconfig"
+
+source "arch/arm/cpu/armv7/omap4/Kconfig"
+
+source "arch/arm/cpu/armv7/omap5/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
+
+source "arch/arm/cpu/armv7/rmobile/Kconfig"
+
+source "arch/arm/cpu/armv7/tegra-common/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
+
+source "arch/arm/cpu/armv7/zynq/Kconfig"
+
source "board/aristainetos/Kconfig"
-source "board/Barix/ipam390/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
source "board/BuS/eb_cpux9k2/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
-source "board/LaCie/edminiv2/Kconfig"
-source "board/LaCie/net2big_v2/Kconfig"
-source "board/LaCie/netspace_v2/Kconfig"
-source "board/LaCie/wireless_space/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/dkb/Kconfig"
-source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/gplugd/Kconfig"
-source "board/Marvell/guruplug/Kconfig"
-source "board/Marvell/mv88f6281gtw_ge/Kconfig"
-source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/rd6281a/Kconfig"
-source "board/Marvell/sheevaplug/Kconfig"
-source "board/Seagate/dockstar/Kconfig"
-source "board/Seagate/goflexhome/Kconfig"
source "board/afeb9260/Kconfig"
-source "board/ait/cam_enc_4xx/Kconfig"
source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/integrator/Kconfig"
-source "board/armltd/versatile/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
-source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/atmel/at91rm9200ek/Kconfig"
source "board/atmel/at91sam9260ek/Kconfig"
source "board/atmel/at91sam9261ek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
-source "board/avionic-design/medcom-wide/Kconfig"
-source "board/avionic-design/plutux/Kconfig"
-source "board/avionic-design/tec-ng/Kconfig"
-source "board/avionic-design/tec/Kconfig"
source "board/balloon3/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
-source "board/buffalo/lsxl/Kconfig"
+source "board/broadcom/bcm958300k/Kconfig"
+source "board/broadcom/bcm958622hr/Kconfig"
source "board/calao/sbc35_a9g20/Kconfig"
source "board/calao/tny_a9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
-source "board/cloudengines/pogo_e02/Kconfig"
source "board/cm4008/Kconfig"
source "board/cm41xx/Kconfig"
-source "board/comelit/dig297/Kconfig"
-source "board/compal/paz00/Kconfig"
source "board/compulab/cm_t335/Kconfig"
-source "board/compulab/cm_t35/Kconfig"
-source "board/compulab/cm_t54/Kconfig"
-source "board/compulab/trimslice/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
-source "board/corscience/tricorder/Kconfig"
source "board/creative/xfi3/Kconfig"
-source "board/d-link/dns325/Kconfig"
source "board/davedenx/qong/Kconfig"
-source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/emk/top9000/Kconfig"
-source "board/enbw/enbw_cmc/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"
-source "board/gumstix/duovero/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hale/tt01/Kconfig"
-source "board/highbank/Kconfig"
-source "board/htkw/mcx/Kconfig"
source "board/icpdas/lp8x4x/Kconfig"
source "board/imx31_phycore/Kconfig"
-source "board/iomega/iconnect/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/isee/igep00x0/Kconfig"
source "board/jornada/Kconfig"
-source "board/karo/tk71/Kconfig"
source "board/karo/tx25/Kconfig"
-source "board/keymile/km_arm/Kconfig"
-source "board/kmc/kzm9g/Kconfig"
-source "board/logicpd/am3517evm/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
-source "board/logicpd/omap3som/Kconfig"
-source "board/logicpd/zoom1/Kconfig"
-source "board/matrix_vision/mvblx/Kconfig"
source "board/mpl/vcma9/Kconfig"
-source "board/nokia/rx51/Kconfig"
-source "board/nvidia/beaver/Kconfig"
-source "board/nvidia/cardhu/Kconfig"
-source "board/nvidia/dalmore/Kconfig"
-source "board/nvidia/harmony/Kconfig"
-source "board/nvidia/jetson-tk1/Kconfig"
-source "board/nvidia/seaboard/Kconfig"
-source "board/nvidia/venice2/Kconfig"
-source "board/nvidia/ventana/Kconfig"
-source "board/nvidia/whistler/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/omicron/calimain/Kconfig"
-source "board/overo/Kconfig"
source "board/palmld/Kconfig"
source "board/palmtc/Kconfig"
source "board/palmtreo680/Kconfig"
-source "board/pandora/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
-source "board/raidsonic/ib62x0/Kconfig"
source "board/raspberrypi/rpi_b/Kconfig"
-source "board/renesas/alt/Kconfig"
-source "board/renesas/koelsch/Kconfig"
-source "board/renesas/lager/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/ronetix/pm9g45/Kconfig"
-source "board/samsung/arndale/Kconfig"
source "board/samsung/goni/Kconfig"
-source "board/samsung/origen/Kconfig"
source "board/samsung/smdk2410/Kconfig"
-source "board/samsung/smdk5250/Kconfig"
-source "board/samsung/smdk5420/Kconfig"
source "board/samsung/smdkc100/Kconfig"
-source "board/samsung/smdkv310/Kconfig"
-source "board/samsung/trats/Kconfig"
-source "board/samsung/trats2/Kconfig"
-source "board/samsung/universal_c210/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
-source "board/st/nhk8815/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/taskit/stamp9g20/Kconfig"
-source "board/technexion/tao3530/Kconfig"
-source "board/technexion/twister/Kconfig"
-source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/am335x/Kconfig"
-source "board/ti/am3517crane/Kconfig"
source "board/ti/am43xx/Kconfig"
-source "board/ti/beagle/Kconfig"
-source "board/ti/dra7xx/Kconfig"
-source "board/ti/evm/Kconfig"
-source "board/ti/ks2_evm/Kconfig"
-source "board/ti/omap5_uevm/Kconfig"
-source "board/ti/panda/Kconfig"
-source "board/ti/sdp3430/Kconfig"
-source "board/ti/sdp4430/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/tnetv107xevm/Kconfig"
source "board/timll/devkit3250/Kconfig"
-source "board/timll/devkit8000/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
-source "board/toradex/colibri_t20_iris/Kconfig"
-source "board/toradex/colibri_t30/Kconfig"
source "board/trizepsiv/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/wandboard/Kconfig"
source "board/woodburn/Kconfig"
source "board/xaeniax/Kconfig"
-source "board/xilinx/zynq/Kconfig"
source "board/zipitz2/Kconfig"
endmenu
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/arm1136/start.o (.text*)
*(.text*)
} >.sram
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- arch/arm/cpu/arm920t/start.o (.text*)
- /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
- . = 0x1000;
- LONG(0x53555243)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata*) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- __bss_start = .;
- .bss : { *(.bss*) }
- __bss_end = .;
-
- .end :
- {
- *(.__end)
- }
-}
--- /dev/null
+if ARCH_DAVINCI
+
+choice
+ prompt "DaVinci board select"
+
+config TARGET_ENBW_CMC
+ bool "EnBW CMC board"
+
+config TARGET_IPAM390
+ bool "IPAM390 board"
+
+config TARGET_DA830EVM
+ bool "DA830 EVM board"
+
+config TARGET_DA850EVM
+ bool "DA850 EVM board"
+
+config TARGET_CAM_ENC_4XX
+ bool "CAM ENC 4xx board"
+
+config TARGET_HAWKBOARD
+ bool "Hawkboard"
+
+config TARGET_DAVINCI_DM355EVM
+ bool "DM355 EVM board"
+
+config TARGET_DAVINCI_DM355LEOPARD
+ bool "DM355 Leopard board"
+
+config TARGET_DAVINCI_DM365EVM
+ bool "DM365 EVM board"
+
+config TARGET_DAVINCI_DM6467EVM
+ bool "DM6467 EVM board"
+
+config TARGET_DAVINCI_DVEVM
+ bool "DVEVM board"
+
+config TARGET_EA20
+ bool "EA20 board"
+
+config TARGET_DAVINCI_SCHMOOGIE
+ bool "Schmoogie board"
+
+config TARGET_DAVINCI_SFFSDR
+ bool "SFFSDR board"
+
+config TARGET_DAVINCI_SONATA
+ bool "Sonata board"
+
+config TARGET_CALIMAIN
+ bool "Calimain board"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "arm926ejs"
+
+config SYS_SOC
+ string
+ default "davinci"
+
+source "board/enbw/enbw_cmc/Kconfig"
+source "board/ait/cam_enc_4xx/Kconfig"
+source "board/Barix/ipam390/Kconfig"
+source "board/davinci/da8xxevm/Kconfig"
+source "board/davinci/dm355evm/Kconfig"
+source "board/davinci/dm355leopard/Kconfig"
+source "board/davinci/dm365evm/Kconfig"
+source "board/davinci/dm6467evm/Kconfig"
+source "board/davinci/dvevm/Kconfig"
+source "board/davinci/ea20/Kconfig"
+source "board/davinci/schmoogie/Kconfig"
+source "board/davinci/sffsdr/Kconfig"
+source "board/davinci/sonata/Kconfig"
+source "board/omicron/calimain/Kconfig"
+
+endif
--- /dev/null
+if KIRKWOOD
+
+choice
+ prompt "Marvell Kirkwood board select"
+
+config TARGET_OPENRD
+ bool "Marvell OpenRD Board"
+
+config TARGET_MV88F6281GTW_GE
+ bool "MV88f6281GTW_GE Board"
+
+config TARGET_RD6281A
+ bool "RD6281A Board"
+
+config TARGET_DREAMPLUG
+ bool "DreamPlug Board"
+
+config TARGET_GURUPLUG
+ bool "GuruPlug Board"
+
+config TARGET_SHEEVAPLUG
+ bool "SheevaPlug Board"
+
+config TARGET_LSXL
+ bool "lsxl Board"
+
+config TARGET_POGO_E02
+ bool "pogo_e02 Board"
+
+config TARGET_DNS325
+ bool "dns325 Board"
+
+config TARGET_ICONNECT
+ bool "iconnect Board"
+
+config TARGET_TK71
+ bool "TK71 Board"
+
+config TARGET_KM_KIRKWOOD
+ bool "KM_KIRKWOOD Board"
+
+config TARGET_NET2BIG_V2
+ bool "LaCie 2Big Network v2 NAS Board"
+
+config TARGET_NETSPACE_V2
+ bool "LaCie netspace_v2 Board"
+
+config TARGET_WIRELESS_SPACE
+ bool "LaCie Wireless_space Board"
+
+config TARGET_IB62X0
+ bool "ib62x0 Board"
+
+config TARGET_DOCKSTAR
+ bool "Dockstar Board"
+
+config TARGET_GOFLEXHOME
+ bool "GoFlex Home Board"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "arm926ejs"
+
+config SYS_SOC
+ string
+ default "kirkwood"
+
+source "board/Marvell/openrd/Kconfig"
+source "board/Marvell/mv88f6281gtw_ge/Kconfig"
+source "board/Marvell/rd6281a/Kconfig"
+source "board/Marvell/dreamplug/Kconfig"
+source "board/Marvell/guruplug/Kconfig"
+source "board/Marvell/sheevaplug/Kconfig"
+source "board/buffalo/lsxl/Kconfig"
+source "board/cloudengines/pogo_e02/Kconfig"
+source "board/d-link/dns325/Kconfig"
+source "board/iomega/iconnect/Kconfig"
+source "board/karo/tk71/Kconfig"
+source "board/keymile/km_arm/Kconfig"
+source "board/LaCie/net2big_v2/Kconfig"
+source "board/LaCie/netspace_v2/Kconfig"
+source "board/LaCie/wireless_space/Kconfig"
+source "board/raidsonic/ib62x0/Kconfig"
+source "board/Seagate/dockstar/Kconfig"
+source "board/Seagate/goflexhome/Kconfig"
+
+endif
. = ALIGN(4);
.text :
{
+ *(.vectors)
arch/arm/cpu/arm926ejs/mxs/start.o (.text*)
*(.text*)
}
--- /dev/null
+if ARCH_NOMADIK
+
+choice
+ prompt "Nomadik board select"
+
+config NOMADIK_NHK8815
+ bool "ST 8815 Nomadik Hardware Kit"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "arm926ejs"
+
+config SYS_SOC
+ string
+ default "nomadik"
+
+source "board/st/nhk8815/Kconfig"
+
+endif
--- /dev/null
+if ORION5X
+
+choice
+ prompt "Marvell Orion board select"
+
+config TARGET_EDMINIV2
+ bool "LaCie Ethernet Disk mini V2"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "arm926ejs"
+
+config SYS_SOC
+ string
+ default "orion5x"
+
+source "board/LaCie/edminiv2/Kconfig"
+
+endif
--- /dev/null
+if ARCH_VERSATILE
+
+config SYS_CPU
+ string
+ default "arm926ejs"
+
+config SYS_BOARD
+ string
+ default "versatile"
+
+config SYS_VENDOR
+ string
+ default "armltd"
+
+config SYS_SOC
+ string
+ default "versatile"
+
+config SYS_CONFIG_NAME
+ string
+ default "versatile"
+
+endif
obj-y += psci.o
endif
+obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} >.sram
obj-y += clk-bcm281xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
78 * CLOCK_1M
};
+unsigned long esub_freq_tbl[8] = {
+ 78 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 208 * CLOCK_1M,
+ 208 * CLOCK_1M,
+ 208 * CLOCK_1M
+};
+
static struct bus_clk_data bsc1_apb_data = {
.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
};
.freq_tbl = slave_axi_freq_tbl,
};
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+ .clk = {
+ .name = "esub_ccu_clk",
+ .ops = &ccu_clk_ops,
+ .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+ },
+ .num_policy_masks = 1,
+ .policy_freq_offset = 0x00000008,
+ .freq_bit_shift = 8,
+ .policy_ctl_offset = 0x0000000c,
+ .policy0_mask_offset = 0x00000010,
+ .policy1_mask_offset = 0x00000014,
+ .policy2_mask_offset = 0x00000018,
+ .policy3_mask_offset = 0x0000001c,
+ .lvm_en_offset = 0x00000034,
+ .freq_id = 2,
+ .freq_tbl = esub_freq_tbl,
+};
+#endif
+
/*
* Bus clocks
*/
CLK_LK(bsc1_apb),
CLK_LK(bsc2_apb),
CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+ CLK_LK(esub_ccu),
+#endif
};
/* public array size */
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD 0xA5A500
+
+#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
+
+#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
+
+#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
+#define ESW_SYS_DIV_DIV_MASK 0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
+#define ESW_SYS_DIV_DIV_SELECT 0x4
+#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
+
+#define PLL_MAX_RETRY 100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+ int rc = -1;
+ int retry_count = 0;
+ rc = clk_get_and_enable("esub_ccu_clk");
+
+ /* Enable Access to CCU registers */
+ writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+ writel(readl(PLLE_POST_RESETB_ADDR) &
+ ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+ PLLE_POST_RESETB_ADDR);
+
+ /* Take PLL out of reset and put into normal mode */
+ writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+ PLLE_RESETB_ADDR);
+
+ /* Wait for PLL lock */
+ rc = -1;
+ while (retry_count < PLL_MAX_RETRY) {
+ udelay(100);
+ if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+ rc = 0;
+ break;
+ }
+ retry_count++;
+ }
+
+ if (rc == -1) {
+ printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+ __func__);
+ return -1;
+ }
+
+ writel(readl(PLLE_POST_RESETB_ADDR) |
+ PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+ PLLE_POST_RESETB_ADDR);
+
+ /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+ writel((readl(ESW_SYS_DIV_ADDR) &
+ ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+ ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+ ESW_SYS_DIV_ADDR);
+
+ writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+ ESW_SYS_DIV_ADDR);
+
+ /* Wait for trigger complete */
+ rc = -1;
+ retry_count = 0;
+ while (retry_count < PLL_MAX_RETRY) {
+ udelay(100);
+ if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+ rc = 0;
+ break;
+ }
+ retry_count++;
+ }
+
+ if (rc == -1) {
+ printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+ __func__);
+ return -1;
+ }
+
+ /* switch Esub AXI clock to 208MHz */
+ writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+ ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+ ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+ ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+ ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+ ESUB_AXI_DIV_DEBUG_ADDR);
+
+ writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+ ESUB_AXI_DIV_DEBUG_ADDR);
+
+ /* Wait for trigger complete */
+ rc = -1;
+ retry_count = 0;
+ while (retry_count < PLL_MAX_RETRY) {
+ udelay(100);
+ if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+ rc = 0;
+ break;
+ }
+ retry_count++;
+ }
+
+ if (rc == -1) {
+ printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+ __func__);
+ return -1;
+ }
+
+ /* Disable Access to CCU registers */
+ writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+ return rc;
+}
--- /dev/null
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define CRMU_MAIL_BOX1 0x03024028
+#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
+
+void reset_cpu(ulong ignored)
+{
+ /* Send soft reset command via Mailbox. */
+ writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);
+
+ while (1)
+ ; /* loop forever till reset */
+}
--- /dev/null
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define CRU_RESET_OFFSET 0x1803F184
+
+void reset_cpu(ulong ignored)
+{
+ /* Reset the cpu by setting software reset request bit */
+ writel(0x1, CRU_RESET_OFFSET);
+
+ while (1)
+ ; /* loop forever till reset */
+}
--- /dev/null
+if ARCH_EXYNOS
+
+choice
+ prompt "EXYNOS board select"
+
+config TARGET_SMDKV310
+ bool "Exynos4210 SMDKV310 board"
+
+config TARGET_TRATS
+ bool "Exynos4210 Trats board"
+
+config TARGET_S5PC210_UNIVERSAL
+ bool "EXYNOS4210 Universal C210 board"
+
+config TARGET_ORIGEN
+ bool "Exynos4412 Origen board"
+
+config TARGET_TRATS2
+ bool "Exynos4412 Trat2 board"
+
+config TARGET_ARNDALE
+ bool "Exynos5250 Arndale board"
+
+config TARGET_SMDK5250
+ bool "SMDK5250 board"
+
+config TARGET_SNOW
+ bool "Snow board"
+
+config TARGET_SMDK5420
+ bool "SMDK5420 board"
+
+config TARGET_PEACH_PIT
+ bool "Peach Pi board"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_SOC
+ string
+ default "exynos"
+
+source "board/samsung/smdkv310/Kconfig"
+source "board/samsung/trats/Kconfig"
+source "board/samsung/universal_c210/Kconfig"
+source "board/samsung/origen/Kconfig"
+source "board/samsung/trats2/Kconfig"
+source "board/samsung/arndale/Kconfig"
+source "board/samsung/smdk5250/Kconfig"
+source "board/samsung/smdk5420/Kconfig"
+
+endif
-if TARGET_HIGHBANK
+if ARCH_HIGHBANK
config SYS_CPU
string
--- /dev/null
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += armpll.o
+obj-y += hwinit-common.o
+obj-y += timer.o
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/iproc-common/armpll.h>
+#include <asm/iproc-common/sysmap.h>
+
+#define NELEMS(x) (sizeof(x) / sizeof(x[0]))
+
+struct armpll_parameters {
+ unsigned int mode;
+ unsigned int ndiv_int;
+ unsigned int ndiv_frac;
+ unsigned int pdiv;
+ unsigned int freqid;
+};
+
+struct armpll_parameters armpll_clk_tab[] = {
+ { 25, 64, 1, 1, 0},
+ { 100, 64, 1, 1, 2},
+ { 400, 64, 1, 1, 6},
+ { 448, 71, 713050, 1, 6},
+ { 500, 80, 1, 1, 6},
+ { 560, 89, 629145, 1, 6},
+ { 600, 96, 1, 1, 6},
+ { 800, 64, 1, 1, 7},
+ { 896, 71, 713050, 1, 7},
+ { 1000, 80, 1, 1, 7},
+ { 1100, 88, 1, 1, 7},
+ { 1120, 89, 629145, 1, 7},
+ { 1200, 96, 1, 1, 7},
+};
+
+uint32_t armpll_config(uint32_t clkmhz)
+{
+ uint32_t freqid;
+ uint32_t ndiv_frac;
+ uint32_t pll;
+ uint32_t status = 1;
+ uint32_t timeout_countdown;
+ int i;
+
+ for (i = 0; i < NELEMS(armpll_clk_tab); i++) {
+ if (armpll_clk_tab[i].mode == clkmhz) {
+ status = 0;
+ break;
+ }
+ }
+
+ if (status) {
+ printf("Error: Clock configuration not supported\n");
+ goto armpll_config_done;
+ }
+
+ /* Enable write access */
+ writel(IPROC_REG_WRITE_ACCESS, IHOST_PROC_CLK_WR_ACCESS);
+
+ if (clkmhz == 25)
+ freqid = 0;
+ else
+ freqid = 2;
+
+ /* Bypass ARM clock and run on sysclk */
+ writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
+ freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
+ freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
+ freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
+ freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
+ IHOST_PROC_CLK_POLICY_FREQ);
+
+ writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
+ 1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
+ IHOST_PROC_CLK_POLICY_CTL);
+
+ /* Poll CCU until operation complete */
+ timeout_countdown = 0x100000;
+ while (readl(IHOST_PROC_CLK_POLICY_CTL) &
+ (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
+ timeout_countdown--;
+ if (timeout_countdown == 0) {
+ printf("CCU polling timedout\n");
+ status = 1;
+ goto armpll_config_done;
+ }
+ }
+
+ if (clkmhz == 25 || clkmhz == 100) {
+ status = 0;
+ goto armpll_config_done;
+ }
+
+ /* Now it is safe to program the PLL */
+ pll = readl(IHOST_PROC_CLK_PLLARMB);
+ pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1);
+ ndiv_frac =
+ ((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1) &
+ (armpll_clk_tab[i].ndiv_frac <<
+ IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R);
+ pll |= ndiv_frac;
+ writel(pll, IHOST_PROC_CLK_PLLARMB);
+
+ writel(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK |
+ armpll_clk_tab[i].ndiv_int <<
+ IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R |
+ armpll_clk_tab[i].pdiv <<
+ IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R |
+ 1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB,
+ IHOST_PROC_CLK_PLLARMA);
+
+ /* Poll ARM PLL Lock until operation complete */
+ timeout_countdown = 0x100000;
+ while (readl(IHOST_PROC_CLK_PLLARMA) &
+ (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK)) {
+ timeout_countdown--;
+ if (timeout_countdown == 0) {
+ printf("ARM PLL lock failed\n");
+ status = 1;
+ goto armpll_config_done;
+ }
+ }
+
+ pll = readl(IHOST_PROC_CLK_PLLARMA);
+ pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB);
+ writel(pll, IHOST_PROC_CLK_PLLARMA);
+
+ /* Set the policy */
+ writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
+ armpll_clk_tab[i].freqid <<
+ IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
+ armpll_clk_tab[i].freqid <<
+ IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
+ armpll_clk_tab[i].freqid <<
+ IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
+ armpll_clk_tab[i+4].freqid <<
+ IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
+ IHOST_PROC_CLK_POLICY_FREQ);
+
+ writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE0_CLKGATE);
+ writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE1_CLKGATE);
+ writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_SWITCH_CLKGATE);
+ writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_PERIPH_CLKGATE);
+ writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_APB0_CLKGATE);
+
+ writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
+ 1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
+ IHOST_PROC_CLK_POLICY_CTL);
+
+ /* Poll CCU until operation complete */
+ timeout_countdown = 0x100000;
+ while (readl(IHOST_PROC_CLK_POLICY_CTL) &
+ (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
+ timeout_countdown--;
+ if (timeout_countdown == 0) {
+ printf("CCU polling failed\n");
+ status = 1;
+ goto armpll_config_done;
+ }
+ }
+
+ status = 0;
+armpll_config_done:
+ /* Disable access to PLL registers */
+ writel(0, IHOST_PROC_CLK_WR_ACCESS);
+
+ return status;
+}
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/iproc-common/timer.h>
+#include <asm/iproc-common/sysmap.h>
+
+static inline uint64_t timer_global_read(void)
+{
+ uint64_t cur_tick;
+ uint32_t count_h;
+ uint32_t count_l;
+
+ do {
+ count_h = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+ TIMER_GLB_HI_OFFSET);
+ count_l = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+ TIMER_GLB_LOW_OFFSET);
+ cur_tick = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+ TIMER_GLB_HI_OFFSET);
+ } while (cur_tick != count_h);
+
+ return (cur_tick << 32) + count_l;
+}
+
+void timer_global_init(void)
+{
+ writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
+ writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_LOW_OFFSET);
+ writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_HI_OFFSET);
+ writel(TIMER_GLB_TIM_CTRL_TIM_EN,
+ IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
+}
+
+int timer_init(void)
+{
+ timer_global_init();
+ return 0;
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ uint64_t count;
+ uint64_t ret;
+ uint64_t tim_clk;
+ uint64_t periph_clk;
+
+ count = timer_global_read();
+
+ /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per msec */
+ periph_clk = 500000;
+ tim_clk = lldiv(periph_clk,
+ (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+ TIMER_GLB_CTRL_OFFSET) &
+ TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
+
+ ret = lldiv(count, (uint32_t)tim_clk);
+
+ /* returns msec */
+ return ret - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ uint64_t cur_tick, end_tick;
+ uint64_t tim_clk;
+ uint64_t periph_clk;
+
+ /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec */
+ periph_clk = 500;
+
+ tim_clk = lldiv(periph_clk,
+ (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+ TIMER_GLB_CTRL_OFFSET) &
+ TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
+
+ cur_tick = timer_global_read();
+
+ end_tick = tim_clk;
+ end_tick *= usec;
+ end_tick += cur_tick;
+
+ do {
+ cur_tick = timer_global_read();
+
+ } while (cur_tick < end_tick);
+}
+
+void timer_systick_init(uint32_t tick_ms)
+{
+ /* Disable timer and clear interrupt status*/
+ writel(0, IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
+ writel(TIMER_PVT_TIM_INT_STATUS_SET,
+ IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
+ writel((PLL_AXI_CLK/1000) * tick_ms,
+ IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_LOAD_OFFSET);
+ writel(TIMER_PVT_TIM_CTRL_INT_EN |
+ TIMER_PVT_TIM_CTRL_AUTO_RELD |
+ TIMER_PVT_TIM_CTRL_TIM_EN,
+ IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
+}
+
+void timer_systick_isr(void *data)
+{
+ writel(TIMER_PVT_TIM_INT_STATUS_SET,
+ IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value in msec.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This is used in conjuction with get_ticks, which returns msec as ticks.
+ * Here we just return ticks/sec = msec/sec = 1000
+ */
+ulong get_tbclk(void)
+{
+ return 1000;
+}
--- /dev/null
+if ARCH_KEYSTONE
+
+choice
+ prompt "TI Keystone board select"
+
+config TARGET_K2HK_EVM
+ bool "TI Keystone 2 Kepler/Hawking EVM"
+
+config TARGET_K2E_EVM
+ bool "TI Keystone 2 Edison EVM"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_SOC
+ string
+ default "keystone"
+
+source "board/ti/ks2_evm/Kconfig"
+
+endif
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
--- /dev/null
+if OMAP34XX
+
+choice
+ prompt "OMAP3 board select"
+
+config TARGET_AM3517_EVM
+ bool "AM3517 EVM"
+
+config TARGET_MT_VENTOUX
+ bool "TeeJet Mt.Ventoux"
+
+config TARGET_OMAP3_SDP3430
+ bool "TI OMAP3430 SDP"
+
+config TARGET_OMAP3_BEAGLE
+ bool "TI OMAP3 BeagleBoard"
+
+config TARGET_CM_T35
+ bool "CompuLab CM-T35"
+
+config TARGET_DEVKIT8000
+ bool "TimLL OMAP3 Devkit8000"
+
+config TARGET_OMAP3_EVM
+ bool "TI OMAP3 EVM"
+
+config TARGET_OMAP3_EVM_QUICK_MMC
+ bool "TI OMAP3 EVM Quick MMC"
+
+config TARGET_OMAP3_EVM_QUICK_NAND
+ bool "TI OMAP3 EVM Quick NAND"
+
+config TARGET_OMAP3_IGEP00X0
+ bool "IGEP"
+
+config TARGET_OMAP3_OVERO
+ bool "OMAP35xx Gumstix Overo"
+
+config TARGET_OMAP3_ZOOM1
+ bool "TI Zoom1"
+
+config TARGET_AM3517_CRANE
+ bool "am3517_crane"
+
+config TARGET_OMAP3_PANDORA
+ bool "OMAP3 Pandora"
+
+config TARGET_ECO5PK
+ bool "ECO5PK"
+
+config TARGET_DIG297
+ bool "DIG297"
+
+config TARGET_TRICORDER
+ bool "Tricorder"
+
+config TARGET_MCX
+ bool "MCX"
+
+config TARGET_OMAP3_LOGIC
+ bool "OMAP3 Logic"
+
+config TARGET_OMAP3_MVBLX
+ bool "OMAP3 MVBLX"
+
+config TARGET_NOKIA_RX51
+ bool "Nokia RX51"
+
+config TARGET_TAO3530
+ bool "TAO3530"
+
+config TARGET_TWISTER
+ bool "Twister"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_SOC
+ string
+ default "omap3"
+
+source "board/logicpd/am3517evm/Kconfig"
+source "board/teejet/mt_ventoux/Kconfig"
+source "board/ti/sdp3430/Kconfig"
+source "board/ti/beagle/Kconfig"
+source "board/compulab/cm_t35/Kconfig"
+source "board/timll/devkit8000/Kconfig"
+source "board/ti/evm/Kconfig"
+source "board/isee/igep00x0/Kconfig"
+source "board/overo/Kconfig"
+source "board/logicpd/zoom1/Kconfig"
+source "board/ti/am3517crane/Kconfig"
+source "board/pandora/Kconfig"
+source "board/8dtech/eco5pk/Kconfig"
+source "board/comelit/dig297/Kconfig"
+source "board/corscience/tricorder/Kconfig"
+source "board/htkw/mcx/Kconfig"
+source "board/logicpd/omap3som/Kconfig"
+source "board/matrix_vision/mvblx/Kconfig"
+source "board/nokia/rx51/Kconfig"
+source "board/technexion/tao3530/Kconfig"
+source "board/technexion/twister/Kconfig"
+
+endif
--- /dev/null
+if OMAP44XX
+
+choice
+ prompt "OMAP4 board select"
+
+config TARGET_DUOVERO
+ bool "OMAP4430 Gumstix Duovero"
+
+config TARGET_OMAP4_PANDA
+ bool "TI OMAP4 PandaBoard"
+
+config TARGET_OMAP4_SDP4430
+ bool "TI OMAP4 SDP4430"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_SOC
+ string
+ default "omap4"
+
+source "board/gumstix/duovero/Kconfig"
+source "board/ti/panda/Kconfig"
+source "board/ti/sdp4430/Kconfig"
+
+endif
--- /dev/null
+if OMAP54XX
+
+choice
+ prompt "OMAP5 board select"
+
+config TARGET_CM_T54
+ bool "CompuLab CM-T54"
+
+config TARGET_OMAP5_UEVM
+ bool "TI OMAP5 uEVM board"
+
+config TARGET_DRA7XX_EVM
+ bool "TI DRA7XX"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_SOC
+ string
+ default "omap5"
+
+source "board/compulab/cm_t54/Kconfig"
+source "board/ti/omap5_uevm/Kconfig"
+source "board/ti/dra7xx/Kconfig"
+
+endif
--- /dev/null
+if RMOBILE
+
+choice
+ prompt "Renesus ARM SoCs board select"
+
+config TARGET_ARMADILLO_800EVA
+ bool "armadillo 800 eva board"
+
+config TARGET_KOELSCH
+ bool "Koelsch board"
+
+config TARGET_LAGER
+ bool "Lager board"
+
+config TARGET_KZM9G
+ bool "KZM9D board"
+
+config TARGET_ALT
+ bool "Alt board"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_SOC
+ string
+ default "rmobile"
+
+source "board/atmark-techno/armadillo-800eva/Kconfig"
+source "board/renesas/koelsch/Kconfig"
+source "board/renesas/lager/Kconfig"
+source "board/kmc/kzm9g/Kconfig"
+source "board/renesas/alt/Kconfig"
+
+endif
* gatting off the rest of the periperal clocks.
*/
writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
- readl(&clock_manager_base->per_pll_en),
- &clock_manager_base->per_pll_en);
+ readl(&clock_manager_base->per_pll.en),
+ &clock_manager_base->per_pll.en);
/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
- &clock_manager_base->main_pll_en);
+ &clock_manager_base->main_pll.en);
- writel(0, &clock_manager_base->sdr_pll_en);
+ writel(0, &clock_manager_base->sdr_pll.en);
/* now we can gate off the rest of the peripheral clocks */
- writel(0, &clock_manager_base->per_pll_en);
+ writel(0, &clock_manager_base->per_pll.en);
/* Put all plls in bypass */
cm_write_bypass(
* Some code might have messed with them.
*/
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
- &clock_manager_base->main_pll_vco);
+ &clock_manager_base->main_pll.vco);
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
- &clock_manager_base->per_pll_vco);
+ &clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
- &clock_manager_base->sdr_pll_vco);
+ &clock_manager_base->sdr_pll.vco);
/*
* The clocks to the flash devices and the L4_MAIN clocks can
* after exiting safe mode but before ungating the clocks.
*/
writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
- &clock_manager_base->per_pll_src);
+ &clock_manager_base->per_pll.src);
writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
- &clock_manager_base->main_pll_l4src);
+ &clock_manager_base->main_pll.l4src);
/* read back for the required 5 us delay. */
- readl(&clock_manager_base->main_pll_vco);
- readl(&clock_manager_base->per_pll_vco);
- readl(&clock_manager_base->sdr_pll_vco);
+ readl(&clock_manager_base->main_pll.vco);
+ readl(&clock_manager_base->per_pll.vco);
+ readl(&clock_manager_base->sdr_pll.vco);
/*
*/
writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->main_pll_vco);
+ &clock_manager_base->main_pll.vco);
writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->per_pll_vco);
+ &clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->sdr_pll_vco);
+ &clock_manager_base->sdr_pll.vco);
/*
* Time starts here
* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
*/
- reset_timer();
start = get_timer(0);
/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
timeout = 7;
/* main mpu */
- writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
+ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
/* main main clock */
- writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
+ writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
/* main for dbg */
- writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
+ writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
/* main for cfgs2fuser0clk */
writel(cfg->cfg2fuser0clk,
- &clock_manager_base->main_pll_cfgs2fuser0clk);
+ &clock_manager_base->main_pll.cfgs2fuser0clk);
/* Peri emac0 50 MHz default to RMII */
- writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
+ writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
/* Peri emac1 50 MHz default to RMII */
- writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
+ writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
/* Peri QSPI */
- writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
+ writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
- writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
+ writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
/* Peri pernandsdmmcclk */
writel(cfg->pernandsdmmcclk,
- &clock_manager_base->per_pll_pernandsdmmcclk);
+ &clock_manager_base->per_pll.pernandsdmmcclk);
/* Peri perbaseclk */
- writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
+ writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
/* Peri s2fuser1clk */
- writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
+ writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
/* 7 us must have elapsed before we can enable the VCO */
while (get_timer(start) < timeout)
/* Enable vco */
/* main pll vco */
writel(cfg->main_vco_base | VCO_EN_BASE,
- &clock_manager_base->main_pll_vco);
+ &clock_manager_base->main_pll.vco);
/* periferal pll */
writel(cfg->peri_vco_base | VCO_EN_BASE,
- &clock_manager_base->per_pll_vco);
+ &clock_manager_base->per_pll.vco);
/* sdram pll vco */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
- &clock_manager_base->sdr_pll_vco);
+ &clock_manager_base->sdr_pll.vco);
/* L3 MP and L3 SP */
- writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
+ writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
- writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
+ writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
- writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
+ writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
/* L4 MP, L4 SP, can0, and can1 */
- writel(cfg->perdiv, &clock_manager_base->per_pll_div);
+ writel(cfg->perdiv, &clock_manager_base->per_pll.div);
- writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
+ writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
#define LOCKED_MASK \
(CLKMGR_INTER_SDRPLLLOCKED_MASK | \
/* write the sdram clock counters before toggling outreset all */
writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
- &clock_manager_base->sdr_pll_ddrdqsclk);
+ &clock_manager_base->sdr_pll.ddrdqsclk);
writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
- &clock_manager_base->sdr_pll_ddr2xdqsclk);
+ &clock_manager_base->sdr_pll.ddr2xdqsclk);
writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
- &clock_manager_base->sdr_pll_ddrdqclk);
+ &clock_manager_base->sdr_pll.ddrdqclk);
writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
- &clock_manager_base->sdr_pll_s2fuser2clk);
+ &clock_manager_base->sdr_pll.s2fuser2clk);
/*
* after locking, but before taking out of bypass
* assert/deassert outresetall
*/
- uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
+ uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
/* assert main outresetall */
writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->main_pll_vco);
+ &clock_manager_base->main_pll.vco);
- uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
+ uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
/* assert pheriph outresetall */
writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->per_pll_vco);
+ &clock_manager_base->per_pll.vco);
/* assert sdram outresetall */
writel(cfg->sdram_vco_base | VCO_EN_BASE|
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
- &clock_manager_base->sdr_pll_vco);
+ &clock_manager_base->sdr_pll.vco);
/* deassert main outresetall */
writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->main_pll_vco);
+ &clock_manager_base->main_pll.vco);
/* deassert pheriph outresetall */
writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->per_pll_vco);
+ &clock_manager_base->per_pll.vco);
/* deassert sdram outresetall */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
- &clock_manager_base->sdr_pll_vco);
+ &clock_manager_base->sdr_pll.vco);
/*
* now that we've toggled outreset all, all the clocks
* are aligned nicely; so we can change any phase.
*/
cm_write_with_phase(cfg->ddrdqsclk,
- (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
+ (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
/* SDRAM DDR2XDQSCLK */
cm_write_with_phase(cfg->ddr2xdqsclk,
- (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
+ (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
cm_write_with_phase(cfg->ddrdqclk,
- (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
+ (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
cm_write_with_phase(cfg->s2fuser2clk,
- (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
+ (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
/* Take all three PLLs out of bypass when safe mode is cleared. */
* now that safe mode is clear with clocks gated
* it safe to change the source mux for the flashes the the L4_MAIN
*/
- writel(cfg->persrc, &clock_manager_base->per_pll_src);
- writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
+ writel(cfg->persrc, &clock_manager_base->per_pll.src);
+ writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
/* Now ungate non-hw-managed clocks */
- writel(~0, &clock_manager_base->main_pll_en);
- writel(~0, &clock_manager_base->per_pll_en);
- writel(~0, &clock_manager_base->sdr_pll_en);
+ writel(~0, &clock_manager_base->main_pll.en);
+ writel(~0, &clock_manager_base->per_pll.en);
+ writel(~0, &clock_manager_base->sdr_pll.en);
}
ifndef CONFIG_SPL_BUILD
ALL-y += u-boot.img
endif
+
+# Added for handoff support
+PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD)
#include <common.h>
#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
{
return 0;
}
+
+
+/*
+ * DesignWare Ethernet initialization
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+ /* initialize and register the emac */
+ return designware_initialize(CONFIG_EMAC_BASE,
+ CONFIG_PHY_INTERFACE_MODE);
+#else
+ return 0;
+#endif
+}
#include <spl.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/scan_manager.h>
DECLARE_GLOBAL_DATA_PTR;
. = ALIGN(4);
.text :
{
+ *(.vectors)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sdram
--- /dev/null
+if TEGRA
+
+choice
+ prompt "Tegra SoC select"
+
+config TEGRA20
+ bool "Tegra20 family"
+
+config TEGRA30
+ bool "Tegra30 family"
+
+config TEGRA114
+ bool "Tegra114 family"
+
+config TEGRA124
+ bool "Tegra124 family"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "arm720t" if SPL_BUILD
+ default "armv7" if !SPL_BUILD
+
+source "arch/arm/cpu/armv7/tegra20/Kconfig"
+source "arch/arm/cpu/armv7/tegra30/Kconfig"
+source "arch/arm/cpu/armv7/tegra114/Kconfig"
+source "arch/arm/cpu/armv7/tegra124/Kconfig"
+
+endif
--- /dev/null
+if TEGRA114
+
+choice
+ prompt "Tegra114 board select"
+
+config TARGET_DALMORE
+ bool "NVIDIA Tegra114 Dalmore evaluation board"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "tegra114"
+
+source "board/nvidia/dalmore/Kconfig"
+
+endif
--- /dev/null
+if TEGRA124
+
+choice
+ prompt "Tegra124 board select"
+
+config TARGET_JETSON_TK1
+ bool "NVIDIA Tegra124 Jetson TK1 board"
+
+config TARGET_VENICE2
+ bool "NVIDIA Tegra124 Venice2"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "tegra124"
+
+source "board/nvidia/jetson-tk1/Kconfig"
+source "board/nvidia/venice2/Kconfig"
+
+endif
--- /dev/null
+if TEGRA20
+
+choice
+ prompt "Tegra20 board select"
+
+config TARGET_HARMONY
+ bool "NVIDIA Tegra20 Harmony evaluation board"
+
+config TARGET_MEDCOM_WIDE
+ bool "Avionic Design Medcom-Wide board"
+
+config TARGET_PAZ00
+ bool "Paz00 board"
+
+config TARGET_PLUTUX
+ bool "Avionic Design Plutux board"
+
+config TARGET_SEABOARD
+ bool "NVIDIA Seaboard"
+
+config TARGET_TEC
+ bool "Avionic Design Tamonten Evaluation Carrier"
+
+config TARGET_TRIMSLICE
+ bool "Compulab TrimSlice board"
+
+config TARGET_VENTANA
+ bool "NVIDIA Tegra20 Ventana evaluation board"
+
+config TARGET_WHISTLER
+ bool "NVIDIA Tegra20 Whistler evaluation board"
+
+config TARGET_COLIBRI_T20_IRIS
+ bool "Toradex Colibri T20 board"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "tegra20"
+
+source "board/nvidia/harmony/Kconfig"
+source "board/avionic-design/medcom-wide/Kconfig"
+source "board/compal/paz00/Kconfig"
+source "board/avionic-design/plutux/Kconfig"
+source "board/nvidia/seaboard/Kconfig"
+source "board/avionic-design/tec/Kconfig"
+source "board/compulab/trimslice/Kconfig"
+source "board/nvidia/ventana/Kconfig"
+source "board/nvidia/whistler/Kconfig"
+source "board/toradex/colibri_t20_iris/Kconfig"
+
+endif
--- /dev/null
+if TEGRA30
+
+choice
+ prompt "Tegra30 board select"
+
+config TARGET_BEAVER
+ bool "NVIDIA Tegra30 Beaver evaluation board"
+
+config TARGET_CARDHU
+ bool "NVIDIA Tegra30 Cardhu evaluation board"
+
+config TARGET_COLIBRI_T30
+ bool "Toradex Colibri T30 board"
+
+config TARGET_TEC_NG
+ bool "Avionic Design TEC-NG board"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "tegra30"
+
+source "board/nvidia/beaver/Kconfig"
+source "board/nvidia/cardhu/Kconfig"
+source "board/toradex/colibri_t30/Kconfig"
+source "board/avionic-design/tec-ng/Kconfig"
+
+endif
--- /dev/null
+if ZYNQ
+
+choice
+ prompt "Xilinx Zynq board select"
+
+config TARGET_ZYNQ_ZED
+ bool "Zynq ZedBoard"
+
+config TARGET_ZYNQ_MICROZED
+ bool "Zynq MicroZed"
+
+config TARGET_ZYNQ_ZC70X
+ bool "Zynq ZC702/ZC706 Board"
+
+config TARGET_ZYNQ_ZC770
+ bool "Zynq ZC770 Board"
+
+endchoice
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_BOARD
+ string
+ default "zynq"
+
+config SYS_VENDOR
+ string
+ default "xilinx"
+
+config SYS_SOC
+ string
+ default "zynq"
+
+config SYS_CONFIG_NAME
+ string
+ default "zynq_zed" if TARGET_ZYNQ_ZED
+ default "zynq_microzed" if TARGET_ZYNQ_MICROZED
+ default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
+ default "zynq_zc770" if TARGET_ZYNQ_ZC770
+
+endif
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
#define BSC1_BASE_ADDR 0x3e016000
#define BSC2_BASE_ADDR 0x3e017000
#define BSC3_BASE_ADDR 0x3e018000
+#define DWDMA_AHB_BASE_ADDR 0x38100000
+#define ESUB_CLK_BASE_ADDR 0x38000000
+#define ESW_CONTRL_BASE_ADDR 0x38200000
#define GPIO2_BASE_ADDR 0x35003000
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_CONFIGS_H
+#define __ARCH_CONFIGS_H
+
+#include <asm/iproc-common/configs.h>
+
+/* uArchitecture specifics */
+
+/* Serial Info */
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_NS16550_CLK 100000000
+#define CONFIG_SYS_NS16550_CLK_DIV 54
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 0x18023000
+
+#endif /* __ARCH_CONFIGS_H */
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_CONFIGS_H
+#define __ARCH_CONFIGS_H
+
+#include <asm/iproc-common/configs.h>
+
+/* uArchitecture specifics */
+
+/* Serial Info */
+/* no padding */
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+
+#define CONFIG_SYS_NS16550_CLK 0x03b9aca0
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 0x18000300
+
+#endif /* __ARCH_CONFIGS_H */
extern void cm_basic_init(const cm_config_t *cfg);
+struct socfpga_clock_manager_main_pll {
+ u32 vco;
+ u32 misc;
+ u32 mpuclk;
+ u32 mainclk;
+ u32 dbgatclk;
+ u32 mainqspiclk;
+ u32 mainnandsdmmcclk;
+ u32 cfgs2fuser0clk;
+ u32 en;
+ u32 maindiv;
+ u32 dbgdiv;
+ u32 tracediv;
+ u32 l4src;
+ u32 stat;
+ u32 _pad_0x38_0x40[2];
+};
+
+struct socfpga_clock_manager_per_pll {
+ u32 vco;
+ u32 misc;
+ u32 emac0clk;
+ u32 emac1clk;
+ u32 perqspiclk;
+ u32 pernandsdmmcclk;
+ u32 perbaseclk;
+ u32 s2fuser1clk;
+ u32 en;
+ u32 div;
+ u32 gpiodiv;
+ u32 src;
+ u32 stat;
+ u32 _pad_0x34_0x40[3];
+};
+
+struct socfpga_clock_manager_sdr_pll {
+ u32 vco;
+ u32 ctrl;
+ u32 ddrdqsclk;
+ u32 ddr2xdqsclk;
+ u32 ddrdqclk;
+ u32 s2fuser2clk;
+ u32 en;
+ u32 stat;
+};
+
struct socfpga_clock_manager {
u32 ctrl;
u32 bypass;
u32 dbctrl;
u32 stat;
u32 _pad_0x18_0x3f[10];
- u32 mainpllgrp;
- u32 perpllgrp;
- u32 sdrpllgrp;
+ struct socfpga_clock_manager_main_pll main_pll;
+ struct socfpga_clock_manager_per_pll per_pll;
+ struct socfpga_clock_manager_sdr_pll sdr_pll;
u32 _pad_0xe0_0x200[72];
-
- u32 main_pll_vco;
- u32 main_pll_misc;
- u32 main_pll_mpuclk;
- u32 main_pll_mainclk;
- u32 main_pll_dbgatclk;
- u32 main_pll_mainqspiclk;
- u32 main_pll_mainnandsdmmcclk;
- u32 main_pll_cfgs2fuser0clk;
- u32 main_pll_en;
- u32 main_pll_maindiv;
- u32 main_pll_dbgdiv;
- u32 main_pll_tracediv;
- u32 main_pll_l4src;
- u32 main_pll_stat;
- u32 main_pll__pad_0x38_0x40[2];
-
- u32 per_pll_vco;
- u32 per_pll_misc;
- u32 per_pll_emac0clk;
- u32 per_pll_emac1clk;
- u32 per_pll_perqspiclk;
- u32 per_pll_pernandsdmmcclk;
- u32 per_pll_perbaseclk;
- u32 per_pll_s2fuser1clk;
- u32 per_pll_en;
- u32 per_pll_div;
- u32 per_pll_gpiodiv;
- u32 per_pll_src;
- u32 per_pll_stat;
- u32 per_pll__pad_0x34_0x40[3];
-
- u32 sdr_pll_vco;
- u32 sdr_pll_ctrl;
- u32 sdr_pll_ddrdqsclk;
- u32 sdr_pll_ddr2xdqsclk;
- u32 sdr_pll_ddrdqclk;
- u32 sdr_pll_s2fuser2clk;
- u32 sdr_pll_en;
- u32 sdr_pll_stat;
};
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
extern const uint32_t iocsr_scan_chain3_table[
((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)];
+int scan_mgr_configure_iocsr(void);
+
#endif /* _SCAN_MANAGER_H_ */
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000
+#define SOCFPGA_EMAC1_ADDRESS 0xff702000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
#ifndef _TEGRA114_H_
#define _TEGRA114_H_
-#define CONFIG_TEGRA114
-
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#ifndef _TEGRA124_H_
#define _TEGRA124_H_
-#define CONFIG_TEGRA124
-
#define NV_PA_SDRAM_BASE 0x80000000
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
#ifndef _TEGRA20_H_
#define _TEGRA20_H_
-#define CONFIG_TEGRA20
-
#define NV_PA_SDRAM_BASE 0x00000000
#include <asm/arch-tegra/tegra.h>
#ifndef _TEGRA30_H_
#define _TEGRA30_H_
-#define CONFIG_TEGRA30
-
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
#include <asm/arch-tegra/tegra.h>
#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
+#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12
+#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12)
+#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12)
#define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
+#define CCM_CSCDR2_NFC_EN (1 << 9)
+#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13)
+#define CCM_CSCDR2_NFC_CLK_INV (1 << 14)
+#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4
+#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4)
+#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4)
+
#define CCM_CSCDR2_ESDHC1_EN (1 << 29)
#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
+#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13)
+#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
#define CCM_CSCDR3_QSPI0_EN (1 << 4)
#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3)
#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
+#define CCM_CCGR10_NFC_CTRL_MASK 0x3
#define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
+#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000)
#define QSPI0_AMBA_BASE 0x20000000
#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+ PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_NFC_CN_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+ PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE)
+#define VF610_NFC_RB_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE)
#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+ VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+ VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+
+ VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+ VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
#define PAD_CTL_SPEED_MED (1 << 12)
#define PAD_CTL_SPEED_HIGH (3 << 12)
+#define PAD_CTL_SRE (1 << 11)
+
#define PAD_CTL_DSE_150ohm (1 << 6)
#define PAD_CTL_DSE_50ohm (3 << 6)
#define PAD_CTL_DSE_25ohm (6 << 6)
#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
+#define PAD_CTL_OBE_ENABLE (1 << 1)
+#define PAD_CTL_IBE_ENABLE (1 << 0)
#else
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v))
-extern inline void __raw_writesb(unsigned long addr, const void *data,
+static inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
{
uint8_t *buf = (uint8_t *)data;
__arch_putb(*buf++, addr);
}
-extern inline void __raw_writesw(unsigned long addr, const void *data,
+static inline void __raw_writesw(unsigned long addr, const void *data,
int wordlen)
{
uint16_t *buf = (uint16_t *)data;
__arch_putw(*buf++, addr);
}
-extern inline void __raw_writesl(unsigned long addr, const void *data,
+static inline void __raw_writesl(unsigned long addr, const void *data,
int longlen)
{
uint32_t *buf = (uint32_t *)data;
__arch_putl(*buf++, addr);
}
-extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
+static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
{
uint8_t *buf = (uint8_t *)data;
while(bytelen--)
*buf++ = __arch_getb(addr);
}
-extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
+static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
{
uint16_t *buf = (uint16_t *)data;
while(wordlen--)
*buf++ = __arch_getw(addr);
}
-extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
+static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
{
uint32_t *buf = (uint32_t *)data;
while(longlen--)
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARMPLL_H
+#define __ARMPLL_H
+
+#include <linux/types.h>
+
+uint32_t armpll_config(uint32_t clkmhz);
+
+#endif /*__ARMPLL_H */
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IPROC_COMMON_CONFIGS_H
+#define __IPROC_COMMON_CONFIGS_H
+
+#include <linux/stringify.h>
+
+/* Architecture, CPU, chip, etc */
+#define CONFIG_IPROC
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+/* Memory Info */
+#define CONFIG_SYS_TEXT_BASE 0x61000000
+#define CONFIG_SYS_SDRAM_BASE 0x61000000
+
+#endif /* __IPROC_COMMON_CONFIGS_H */
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SYSMAP_H
+#define __SYSMAP_H
+
+#define IHOST_PROC_CLK_PLLARMA 0X19000C00
+#define IHOST_PROC_CLK_PLLARMB 0X19000C04
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24
+
+#define IHOST_PROC_CLK_WR_ACCESS 0X19000000
+#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008
+#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8
+#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C
+#define IHOST_PROC_CLK_POLICY_CTL__GO 0
+#define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1
+#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0
+#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH 20
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK 28
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0
+#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200
+#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204
+#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210
+#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300
+#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400
+#define IPROC_CLKCT_HDELAY_SW_EN 0x00000303
+
+#define IPROC_REG_WRITE_ACCESS 0x00a5a501
+
+#define IPROC_PERIPH_BASE 0x19020000
+#define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100)
+#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200)
+#define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600)
+#define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000)
+
+#define PLL_AXI_CLK 0x1DCD6500
+
+#endif /* __SYSMAP_H */
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <linux/types.h>
+
+void timer_systick_init(uint32_t tick_ms);
+void timer_global_init(void);
+
+/* ARM A9 Private Timer */
+#define TIMER_PVT_LOAD_OFFSET 0x00000000
+#define TIMER_PVT_COUNTER_OFFSET 0x00000004
+#define TIMER_PVT_CTRL_OFFSET 0x00000008
+#define TIMER_PVT_STATUS_OFFSET 0x0000000C
+#define TIMER_PVT_TIM_CTRL_TIM_EN 0x00000001
+#define TIMER_PVT_TIM_CTRL_AUTO_RELD 0x00000002
+#define TIMER_PVT_TIM_CTRL_INT_EN 0x00000004
+#define TIMER_PVT_TIM_CTRL_PRESC_MASK 0x0000FF00
+#define TIMER_PVT_TIM_INT_STATUS_SET 0x00000001
+
+/* Global timer */
+#define TIMER_GLB_LOW_OFFSET 0x00000000
+#define TIMER_GLB_HI_OFFSET 0x00000004
+#define TIMER_GLB_CTRL_OFFSET 0x00000008
+#define TIMER_GLB_TIM_CTRL_TIM_EN 0x00000001
+#define TIMER_GLB_TIM_CTRL_COMP_EN 0x00000002
+#define TIMER_GLB_TIM_CTRL_INT_EN 0x00000004
+#define TIMER_GLB_TIM_CTRL_AUTO_INC 0x00000008
+#define TIMER_GLB_TIM_CTRL_PRESC_MASK 0x0000FF00
+#define TIMER_GLB_TIM_INT_STATUS_SET 0x00000001
+
+#endif /*__TIMER_H */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
#ifdef CONFIG_ARM64
- void (*kernel_entry)(void *fdt_addr);
+ void (*kernel_entry)(void *fdt_addr, void *res0, void *res1,
+ void *res2);
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
- kernel_entry = (void (*)(void *fdt_addr))images->ep;
+ kernel_entry = (void (*)(void *fdt_addr, void *res0, void *res1,
+ void *res2))images->ep;
debug("## Transferring control to Linux (at address %lx)...\n",
(ulong) kernel_entry);
if (!fake) {
do_nonsec_virt_switch();
- kernel_entry(images->ft_addr);
+ kernel_entry(images->ft_addr, NULL, NULL, NULL);
}
#else
unsigned long machid = gd->bd->bi_arch_number;
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> 20;
- i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+ i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <config.h>
+
/*
*************************************************************************
*
if TARGET_ECO5PK
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "eco5pk"
string
default "8dtech"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "eco5pk"
if TARGET_IPAM390
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "ipam390"
string
default "Barix"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "ipam390"
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
if TARGET_EDMINIV2
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "edminiv2"
string
default "LaCie"
-config SYS_SOC
- string
- default "orion5x"
-
config SYS_CONFIG_NAME
string
default "edminiv2"
if TARGET_NET2BIG_V2
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "net2big_v2"
string
default "LaCie"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "lacie_kw"
if TARGET_NETSPACE_V2
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "netspace_v2"
string
default "LaCie"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "lacie_kw"
if TARGET_WIRELESS_SPACE
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "wireless_space"
string
default "LaCie"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "wireless_space"
if TARGET_DREAMPLUG
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dreamplug"
string
default "Marvell"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "dreamplug"
if TARGET_GURUPLUG
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "guruplug"
string
default "Marvell"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "guruplug"
if TARGET_MV88F6281GTW_GE
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "mv88f6281gtw_ge"
string
default "Marvell"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "mv88f6281gtw_ge"
if TARGET_OPENRD
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "openrd"
string
default "Marvell"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "openrd"
if TARGET_RD6281A
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "rd6281a"
string
default "Marvell"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "rd6281a"
if TARGET_SHEEVAPLUG
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "sheevaplug"
string
default "Marvell"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "sheevaplug"
if TARGET_DOCKSTAR
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dockstar"
string
default "Seagate"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "dockstar"
if TARGET_GOFLEXHOME
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "goflexhome"
string
default "Seagate"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "goflexhome"
if TARGET_CAM_ENC_4XX
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "cam_enc_4xx"
string
default "ait"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "cam_enc_4xx"
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
#
obj-y := socfpga_cyclone5.o
-obj-$(CONFIG_SPL_BUILD) += pinmux_config.o
+obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
icache_enable();
return 0;
}
-
-/*
- * DesignWare Ethernet initialization
- */
-/* We know all the init functions have been run now */
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
+++ /dev/null
-if TARGET_VERSATILEAB
-
-config SYS_CPU
- string
- default "arm926ejs"
-
-config SYS_BOARD
- string
- default "versatile"
-
-config SYS_VENDOR
- string
- default "armltd"
-
-config SYS_SOC
- string
- default "versatile"
-
-config SYS_CONFIG_NAME
- string
- default "versatile"
-
-endif
-
-if TARGET_VERSATILEPB
-
-config SYS_CPU
- string
- default "arm926ejs"
-
-config SYS_BOARD
- string
- default "versatile"
-
-config SYS_VENDOR
- string
- default "armltd"
-
-config SYS_SOC
- string
- default "versatile"
-
-config SYS_CONFIG_NAME
- string
- default "versatile"
-
-endif
-
-if TARGET_VERSATILEQEMU
-
-config SYS_CPU
- string
- default "arm926ejs"
-
-config SYS_BOARD
- string
- default "versatile"
-
-config SYS_VENDOR
- string
- default "armltd"
-
-config SYS_SOC
- string
- default "versatile"
-
-config SYS_CONFIG_NAME
- string
- default "versatile"
-
-endif
VEXPRESS_CA5X2 BOARD
M: Matt Waddel <matt.waddel@linaro.org>
-S: Maintained
+S: Orphan (since 2014-08)
F: include/configs/vexpress_ca5x2.h
F: configs/vexpress_ca5x2_defconfig
F: include/configs/vexpress_ca9x4.h
if TARGET_ARMADILLO_800EVA
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "armadillo-800eva"
string
default "atmark-techno"
-config SYS_SOC
- string
- default "rmobile"
-
config SYS_CONFIG_NAME
string
default "armadillo-800eva"
if TARGET_MEDCOM_WIDE
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "medcom-wide"
string
default "avionic-design"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "medcom-wide"
if TARGET_PLUTUX
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "plutux"
string
default "avionic-design"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "plutux"
if TARGET_TEC_NG
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "tec-ng"
string
default "avionic-design"
-config SYS_SOC
- string
- default "tegra30"
-
config SYS_CONFIG_NAME
string
default "tec-ng"
if TARGET_TEC
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "tec"
string
default "avionic-design"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "tec"
--- /dev/null
+BCM28155_W1D BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm28155_ap.h
+F: configs/bcm28155_w1d_defconfig
--- /dev/null
+if TARGET_BCM958300K
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_BOARD
+ string
+ default "bcm_ep"
+
+config SYS_VENDOR
+ string
+ default "broadcom"
+
+config SYS_SOC
+ string
+ default "bcmcygnus"
+
+config SYS_CONFIG_NAME
+ string
+ default "bcm_ep_board"
+
+endif
--- /dev/null
+Broadcom: Cygnus
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm958300k/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958300k_defconfig
--- /dev/null
+if TARGET_BCM958622HR
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_BOARD
+ string
+ default "bcm_ep"
+
+config SYS_VENDOR
+ string
+ default "broadcom"
+
+config SYS_SOC
+ string
+ default "bcmnsp"
+
+config SYS_CONFIG_NAME
+ string
+ default "bcm_ep_board"
+
+endif
--- /dev/null
+Broadcom: Northstar Plus
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm958622hr/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958622hr_defconfig
--- /dev/null
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <config.h>
+#include <asm/system.h>
+#include <asm/iproc-common/armpll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+ /*
+ * Address of boot parameters passed to kernel
+ * Use default offset 0x100
+ */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * dram_init - sets u-boot's idea of sdram size
+ */
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+int board_early_init_f(void)
+{
+ uint32_t status = 0;
+
+ /* Setup PLL if required */
+#if defined(CONFIG_ARMCLK)
+ armpll_config(CONFIG_ARMCLK);
+#endif
+
+ return status;
+}
if TARGET_LSXL
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "lsxl"
string
default "buffalo"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "lsxl"
. = ALIGN(4);
.text : {
*(.__image_copy_start)
+ *(.vectors)
arch/arm/cpu/arm920t/start.o (.text*)
. = 0x1000;
if TARGET_POGO_E02
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "pogo_e02"
string
default "cloudengines"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "pogo_e02"
if TARGET_DIG297
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "dig297"
string
default "comelit"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "dig297"
if TARGET_PAZ00
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "paz00"
string
default "compal"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "paz00"
if TARGET_CM_T35
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "cm_t35"
string
default "compulab"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "cm_t35"
if TARGET_CM_T54
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "cm_t54"
string
default "compulab"
-config SYS_SOC
- string
- default "omap5"
-
config SYS_CONFIG_NAME
string
default "cm_t54"
if TARGET_TRIMSLICE
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "trimslice"
string
default "compulab"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "trimslice"
if TARGET_TRICORDER
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "tricorder"
string
default "corscience"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "tricorder"
if TARGET_DNS325
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dns325"
string
default "d-link"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "dns325"
if TARGET_DA830EVM
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "da8xxevm"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "da830evm"
if TARGET_DA850EVM
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "da8xxevm"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "da850evm"
if TARGET_HAWKBOARD
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "da8xxevm"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "hawkboard"
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
.text :
{
+ *(.vectors)
arch/arm/cpu/arm926ejs/start.o (.text*)
arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*)
drivers/mtd/nand/built-in.o (.text*)
if TARGET_DAVINCI_DM355EVM
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dm355evm"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_dm355evm"
if TARGET_DAVINCI_DM355LEOPARD
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dm355leopard"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_dm355leopard"
if TARGET_DAVINCI_DM365EVM
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dm365evm"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_dm365evm"
if TARGET_DAVINCI_DM6467EVM
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dm6467evm"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_dm6467evm"
if TARGET_DAVINCI_DVEVM
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "dvevm"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_dvevm"
if TARGET_EA20
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "ea20"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "ea20"
if TARGET_DAVINCI_SCHMOOGIE
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "schmoogie"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_schmoogie"
if TARGET_DAVINCI_SFFSDR
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "sffsdr"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_sffsdr"
if TARGET_DAVINCI_SONATA
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "sonata"
string
default "davinci"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "davinci_sonata"
if TARGET_ENBW_CMC
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "enbw_cmc"
string
default "enbw"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "enbw_cmc"
if TARGET_DUOVERO
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "duovero"
string
default "gumstix"
-config SYS_SOC
- string
- default "omap4"
-
config SYS_CONFIG_NAME
string
default "duovero"
if TARGET_MCX
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "mcx"
string
default "htkw"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "mcx"
if TARGET_ICONNECT
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "iconnect"
string
default "iomega"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "iconnect"
if TARGET_OMAP3_IGEP00X0
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "igep00x0"
string
default "isee"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_igep00x0"
if TARGET_TK71
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "tk71"
string
default "karo"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "tk71"
if TARGET_KM_KIRKWOOD
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "km_arm"
string
default "keymile"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "km_kirkwood"
if TARGET_KZM9G
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "kzm9g"
string
default "kmc"
-config SYS_SOC
- string
- default "rmobile"
-
config SYS_CONFIG_NAME
string
default "kzm9g"
if TARGET_AM3517_EVM
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "am3517evm"
string
default "logicpd"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "am3517_evm"
if TARGET_OMAP3_LOGIC
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "omap3som"
string
default "logicpd"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_logic"
if TARGET_OMAP3_ZOOM1
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "zoom1"
string
default "logicpd"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_zoom1"
if TARGET_OMAP3_MVBLX
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "mvblx"
string
default "matrix_vision"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_mvblx"
if TARGET_NOKIA_RX51
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "rx51"
string
default "nokia"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "nokia_rx51"
if TARGET_BEAVER
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "beaver"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra30"
-
config SYS_CONFIG_NAME
string
default "beaver"
if TARGET_CARDHU
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "cardhu"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra30"
-
config SYS_CONFIG_NAME
string
default "cardhu"
if TARGET_DALMORE
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "dalmore"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra114"
-
config SYS_CONFIG_NAME
string
default "dalmore"
if TARGET_HARMONY
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "harmony"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "harmony"
if TARGET_JETSON_TK1
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "jetson-tk1"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra124"
-
config SYS_CONFIG_NAME
string
default "jetson-tk1"
if TARGET_SEABOARD
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "seaboard"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "seaboard"
if TARGET_VENICE2
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "venice2"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra124"
-
config SYS_CONFIG_NAME
string
default "venice2"
if TARGET_VENTANA
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "ventana"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "ventana"
if TARGET_WHISTLER
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "whistler"
string
default "nvidia"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "whistler"
if TARGET_CALIMAIN
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "calimain"
string
default "omicron"
-config SYS_SOC
- string
- default "davinci"
-
config SYS_CONFIG_NAME
string
default "calimain"
if TARGET_OMAP3_OVERO
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "overo"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_overo"
if TARGET_OMAP3_PANDORA
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "pandora"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_pandora"
if TARGET_IB62X0
-config SYS_CPU
- string
- default "arm926ejs"
-
config SYS_BOARD
string
default "ib62x0"
string
default "raidsonic"
-config SYS_SOC
- string
- default "kirkwood"
-
config SYS_CONFIG_NAME
string
default "ib62x0"
if TARGET_ALT
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "alt"
string
default "renesas"
-config SYS_SOC
- string
- default "rmobile"
-
config SYS_CONFIG_NAME
string
default "alt"
if TARGET_KOELSCH
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "koelsch"
string
default "renesas"
-config SYS_SOC
- string
- default "rmobile"
-
config SYS_CONFIG_NAME
string
default "koelsch"
if TARGET_LAGER
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "lager"
string
default "renesas"
-config SYS_SOC
- string
- default "rmobile"
-
config SYS_CONFIG_NAME
string
default "lager"
if TARGET_ARNDALE
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "arndale"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "arndale"
return 0;
}
#endif
+
+#ifdef CONFIG_S5P_PA_SYSRAM
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ writel(addr, CONFIG_S5P_PA_SYSRAM);
+
+ /* make sure this write is really executed */
+ __asm__ volatile ("dsb\n");
+}
+#endif
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
if TARGET_ORIGEN
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "origen"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "origen"
if TARGET_SMDK5250
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "smdk5250"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "smdk5250"
if TARGET_SNOW
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "smdk5250"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "snow"
if TARGET_PEACH_PIT
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "smdk5420"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "peach-pit"
if TARGET_SMDK5420
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "smdk5420"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "smdk5420"
if TARGET_SMDKV310
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "smdkv310"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "smdkv310"
if TARGET_TRATS
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "trats"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "trats"
if TARGET_TRATS2
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "trats2"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "trats2"
if TARGET_S5PC210_UNIVERSAL
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "universal_c210"
string
default "samsung"
-config SYS_SOC
- string
- default "exynos"
-
config SYS_CONFIG_NAME
string
default "s5pc210_universal"
-if TARGET_NHK8815
-
-config SYS_CPU
- string
- default "arm926ejs"
+if NOMADIK_NHK8815
config SYS_BOARD
string
string
default "st"
-config SYS_SOC
- string
- default "nomadik"
-
config SYS_CONFIG_NAME
string
default "nhk8815"
if TARGET_TAO3530
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "tao3530"
string
default "technexion"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "tao3530"
if TARGET_TWISTER
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "twister"
string
default "technexion"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "twister"
if TARGET_MT_VENTOUX
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "mt_ventoux"
string
default "teejet"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "mt_ventoux"
if TARGET_AM3517_CRANE
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "am3517crane"
string
default "ti"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "am3517_crane"
if TARGET_OMAP3_BEAGLE
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "beagle"
string
default "ti"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_beagle"
if TARGET_DRA7XX_EVM
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "dra7xx"
string
default "ti"
-config SYS_SOC
- string
- default "omap5"
-
config SYS_CONFIG_NAME
string
default "dra7xx_evm"
if TARGET_OMAP3_EVM
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "evm"
string
default "ti"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_evm"
if TARGET_OMAP3_EVM_QUICK_MMC
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "evm"
string
default "ti"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_evm_quick_mmc"
if TARGET_OMAP3_EVM_QUICK_NAND
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "evm"
string
default "ti"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_evm_quick_nand"
if TARGET_K2E_EVM
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "ks2_evm"
string
default "ti"
-config SYS_SOC
- string
- default "keystone"
-
config SYS_CONFIG_NAME
string
default "k2e_evm"
if TARGET_K2HK_EVM
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "ks2_evm"
string
default "ti"
-config SYS_SOC
- string
- default "keystone"
-
config SYS_CONFIG_NAME
string
default "k2hk_evm"
if TARGET_OMAP5_UEVM
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "omap5_uevm"
string
default "ti"
-config SYS_SOC
- string
- default "omap5"
-
config SYS_CONFIG_NAME
string
default "omap5_uevm"
if TARGET_OMAP4_PANDA
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "panda"
string
default "ti"
-config SYS_SOC
- string
- default "omap4"
-
config SYS_CONFIG_NAME
string
default "omap4_panda"
if TARGET_OMAP3_SDP3430
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "sdp3430"
string
default "ti"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "omap3_sdp3430"
if TARGET_OMAP4_SDP4430
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "sdp4430"
string
default "ti"
-config SYS_SOC
- string
- default "omap4"
-
config SYS_CONFIG_NAME
string
default "omap4_sdp4430"
if TARGET_DEVKIT8000
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
string
default "devkit8000"
string
default "timll"
-config SYS_SOC
- string
- default "omap3"
-
config SYS_CONFIG_NAME
string
default "devkit8000"
if TARGET_COLIBRI_T20_IRIS
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "colibri_t20_iris"
string
default "toradex"
-config SYS_SOC
- string
- default "tegra20"
-
config SYS_CONFIG_NAME
string
default "colibri_t20_iris"
if TARGET_COLIBRI_T30
-config SYS_CPU
- string
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
config SYS_BOARD
string
default "colibri_t30"
string
default "toradex"
-config SYS_SOC
- string
- default "tegra30"
-
config SYS_CONFIG_NAME
string
default "colibri_t30"
. = CONFIG_SPL_TEXT_BASE;
.text.0 :
{
+ *(.vectors)
arch/arm/cpu/pxa/start.o (.text*)
arch/arm/lib/built-in.o (.text*)
board/vpac270/built-in.o (.text*)
+++ /dev/null
-if TARGET_ZYNQ_MICROZED
-
-config SYS_CPU
- string
- default "armv7"
-
-config SYS_BOARD
- string
- default "zynq"
-
-config SYS_VENDOR
- string
- default "xilinx"
-
-config SYS_SOC
- string
- default "zynq"
-
-config SYS_CONFIG_NAME
- string
- default "zynq_microzed"
-
-endif
-
-if TARGET_ZYNQ_ZC70X
-
-config SYS_CPU
- string
- default "armv7"
-
-config SYS_BOARD
- string
- default "zynq"
-
-config SYS_VENDOR
- string
- default "xilinx"
-
-config SYS_SOC
- string
- default "zynq"
-
-config SYS_CONFIG_NAME
- string
- default "zynq_zc70x"
-
-endif
-
-if TARGET_ZYNQ_ZC770
-
-config SYS_CPU
- string
- default "armv7"
-
-config SYS_BOARD
- string
- default "zynq"
-
-config SYS_VENDOR
- string
- default "xilinx"
-
-config SYS_SOC
- string
- default "zynq"
-
-config SYS_CONFIG_NAME
- string
- default "zynq_zc770"
-
-endif
-
-if TARGET_ZYNQ_ZED
-
-config SYS_CPU
- string
- default "armv7"
-
-config SYS_BOARD
- string
- default "zynq"
-
-config SYS_VENDOR
- string
- default "xilinx"
-
-config SYS_SOC
- string
- default "zynq"
-
-config SYS_CONFIG_NAME
- string
- default "zynq_zed"
-
-endif
M: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
S: Maintained
F: board/xilinx/zynq/
-F: include/configs/zynq_microzed.h
-F: configs/zynq_microzed_defconfig
-F: include/configs/zynq_zc70x.h
-F: configs/zynq_zc70x_defconfig
-F: include/configs/zynq_zc770.h
-F: configs/zynq_zc770_xm010_defconfig
-F: configs/zynq_zc770_xm012_defconfig
-F: configs/zynq_zc770_xm013_defconfig
-F: include/configs/zynq_zed.h
-F: configs/zynq_zed_defconfig
+F: include/configs/zynq*.h
+F: configs/zynq_*_defconfig
"boot Linux zImage image from memory", bootz_help_text
);
#endif /* CONFIG_CMD_BOOTZ */
+
+#ifdef CONFIG_CMD_BOOTI
+/* See Documentation/arm64/booting.txt in the Linux kernel */
+struct Image_header {
+ uint32_t code0; /* Executable code */
+ uint32_t code1; /* Executable code */
+ uint64_t text_offset; /* Image load offset, LE */
+ uint64_t image_size; /* Effective Image size, LE */
+ uint64_t res1; /* reserved */
+ uint64_t res2; /* reserved */
+ uint64_t res3; /* reserved */
+ uint64_t res4; /* reserved */
+ uint32_t magic; /* Magic number */
+ uint32_t res5;
+};
+
+#define LINUX_ARM64_IMAGE_MAGIC 0x644d5241
+
+static int booti_setup(bootm_headers_t *images)
+{
+ struct Image_header *ih;
+ uint64_t dst;
+
+ ih = (struct Image_header *)map_sysmem(images->ep, 0);
+
+ if (ih->magic != le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC)) {
+ puts("Bad Linux ARM64 Image magic!\n");
+ return 1;
+ }
+
+ if (ih->image_size == 0) {
+ puts("Image lacks image_size field, assuming 16MiB\n");
+ ih->image_size = (16 << 20);
+ }
+
+ /*
+ * If we are not at the correct run-time location, set the new
+ * correct location and then move the image there.
+ */
+ dst = gd->bd->bi_dram[0].start + le32_to_cpu(ih->text_offset);
+ if (images->ep != dst) {
+ void *src;
+
+ debug("Moving Image from 0x%lx to 0x%llx\n", images->ep, dst);
+
+ src = (void *)images->ep;
+ images->ep = dst;
+ memmove((void *)dst, src, le32_to_cpu(ih->image_size));
+ }
+
+ return 0;
+}
+
+/*
+ * Image booting support
+ */
+static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[], bootm_headers_t *images)
+{
+ int ret;
+ struct Image_header *ih;
+
+ ret = do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START,
+ images, 1);
+
+ /* Setup Linux kernel Image entry point */
+ if (!argc) {
+ images->ep = load_addr;
+ debug("* kernel: default image load address = 0x%08lx\n",
+ load_addr);
+ } else {
+ images->ep = simple_strtoul(argv[0], NULL, 16);
+ debug("* kernel: cmdline image address = 0x%08lx\n",
+ images->ep);
+ }
+
+ ret = booti_setup(images);
+ if (ret != 0)
+ return 1;
+
+ ih = (struct Image_header *)map_sysmem(images->ep, 0);
+
+ lmb_reserve(&images->lmb, images->ep, le32_to_cpu(ih->image_size));
+
+ /*
+ * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
+ * have a header that provide this informaiton.
+ */
+ if (bootm_find_ramdisk_fdt(flag, argc, argv))
+ return 1;
+
+ return 0;
+}
+
+int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+
+ /* Consume 'booti' */
+ argc--; argv++;
+
+ if (booti_start(cmdtp, flag, argc, argv, &images))
+ return 1;
+
+ /*
+ * We are doing the BOOTM_STATE_LOADOS state ourselves, so must
+ * disable interrupts ourselves
+ */
+ bootm_disable_interrupts();
+
+ images.os.os = IH_OS_LINUX;
+ ret = do_bootm_states(cmdtp, flag, argc, argv,
+ BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
+ BOOTM_STATE_OS_GO,
+ &images, 1);
+
+ return ret;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char booti_help_text[] =
+ "[addr [initrd[:size]] [fdt]]\n"
+ " - boot Linux Image stored in memory\n"
+ "\tThe argument 'initrd' is optional and specifies the address\n"
+ "\tof the initrd in memory. The optional argument ':size' allows\n"
+ "\tspecifying the size of RAW initrd.\n"
+#if defined(CONFIG_OF_LIBFDT)
+ "\tSince booting a Linux kernelrequires a flat device-tree\n"
+ "\ta third argument is required which is the address of the\n"
+ "\tdevice-tree blob. To boot that kernel without an initrd image,\n"
+ "\tuse a '-' for the second argument.\n"
+#endif
+ "";
+#endif
+
+U_BOOT_CMD(
+ booti, CONFIG_SYS_MAXARGS, 1, do_booti,
+ "boot arm64 Linux Image image from memory", booti_help_text
+);
+#endif /* CONFIG_CMD_BOOTI */
CONFIG_ARM=y
++S:CONFIG_RMOBILE=y
CONFIG_TARGET_ALT=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_AM3517_CRANE=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_AM3517_EVM=y
CONFIG_ARM=y
++S:CONFIG_RMOBILE=y
CONFIG_TARGET_ARMADILLO_800EVA=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_ARNDALE=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
+CONFIG_ARM=y
+CONFIG_TARGET_BCM28155_AP=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCM958300K=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCM958622HR=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_BEAVER=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_DAVINCI=y
+S:CONFIG_TARGET_CAM_ENC_4XX=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_CARDHU=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_CM_T35=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
+S:CONFIG_TARGET_CM_T54=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_COLIBRI_T20_IRIS=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_COLIBRI_T30=y
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA830EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_DAVINCI=y
+S:CONFIG_TARGET_DA850EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_DAVINCI=y
+S:CONFIG_TARGET_DA850EVM=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA114=y
+S:CONFIG_TARGET_DALMORE=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM355EVM=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM355LEOPARD=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM365EVM=y
CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000"
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM6467EVM=y
CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000"
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM6467EVM=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DVEVM=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SCHMOOGIE=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SFFSDR=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SONATA=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_DEVKIT8000=y
CONFIG_ARM=y
+CONFIG_OMAP34XX=y
CONFIG_TARGET_DIG297=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_DNS325=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_DOCKSTAR=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
+S:CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
+S:CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
+S:CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_DREAMPLUG=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP44XX=y
+S:CONFIG_TARGET_DUOVERO=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_EA20=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_ECO5PK=y
CONFIG_ARM=y
+CONFIG_ORION5X=y
CONFIG_TARGET_EDMINIV2=y
CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_ENBW_CMC=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_GURUPLUG=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_HARMONY=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_DAVINCI=y
+S:CONFIG_TARGET_HAWKBOARD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="UART_U_BOOT"
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_DAVINCI=y
+S:CONFIG_TARGET_HAWKBOARD=y
CONFIG_ARM=y
-CONFIG_TARGET_HIGHBANK=y
+CONFIG_ARCH_HIGHBANK=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_ICONNECT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_DAVINCI=y
+S:CONFIG_TARGET_IPAM390=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA124=y
+S:CONFIG_TARGET_JETSON_TK1=y
CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2E_EVM=y
CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2HK_EVM=y
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
++S:CONFIG_RMOBILE=y
CONFIG_TARGET_KOELSCH=y
CONFIG_ARM=y
++S:CONFIG_RMOBILE=y
CONFIG_TARGET_KZM9G=y
CONFIG_ARM=y
++S:CONFIG_RMOBILE=y
CONFIG_TARGET_LAGER=y
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_MCX=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_MEDCOM_WIDE=y
CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_MT_VENTOUX=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_MV88F6281GTW_GE=y
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
-CONFIG_TARGET_NHK8815=y
+CONFIG_ARCH_NOMADIK=y
+CONFIG_NOMADIK_NHK8815=y
CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND"
CONFIG_ARM=y
-CONFIG_TARGET_NHK8815=y
+CONFIG_ARCH_NOMADIK=y
+CONFIG_NOMADIK_NHK8815=y
CONFIG_ARM=y
+CONFIG_OMAP34XX=y
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_EVM=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_TAO3530=y
CONFIG_ARM=y
+CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
CONFIG_ARM=y
+CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_MVBLX=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_ARM=y
+CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_PANDORA=y
CONFIG_ARM=y
+CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_SDP3430=y
CONFIG_ARM=y
+CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_ZOOM1=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP44XX=y
+S:CONFIG_TARGET_OMAP4_PANDA=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP44XX=y
+S:CONFIG_TARGET_OMAP4_SDP4430=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
+S:CONFIG_TARGET_OMAP5_UEVM=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_ORIGEN=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_PAZ00=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_PEACH_PIT=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_PLUTUX=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_POGO_E02=y
CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_RD6281A=y
CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_S5PC210_UNIVERSAL=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_SEABOARD=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SMDK5250=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SMDK5420=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SMDKV310=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SNOW=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_TAO3530=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_TEC_NG=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_TEC=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_TK71=y
CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS2=y
CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_TRICORDER=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_TRICORDER=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_TRIMSLICE=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
+S:CONFIG_TARGET_TWISTER=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA124=y
+S:CONFIG_TARGET_VENICE2=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_VENTANA=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB"
CONFIG_ARM=y
-CONFIG_TARGET_VERSATILEAB=y
+CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB"
CONFIG_ARM=y
-CONFIG_TARGET_VERSATILEPB=y
+CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB"
CONFIG_ARM=y
-CONFIG_TARGET_VERSATILEQEMU=y
+CONFIG_ARCH_VERSATILE=y
-CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_WHISTLER=y
CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
CONFIG_TARGET_WIRELESS_SPACE=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC70X=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZED=y
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
-
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
unsigned int drvsel;
unsigned int smplsel;
/* Disable SDMMC clock. */
- clrbits_le32(&clock_manager_base->per_pll_en,
+ clrbits_le32(&clock_manager_base->per_pll.en,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
/* Configures drv_sel and smpl_sel */
readl(&system_manager_base->sdmmcgrp_ctrl));
/* Enable SDMMC clock */
- setbits_le32(&clock_manager_base->per_pll_en,
+ setbits_le32(&clock_manager_base->per_pll.en,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
}
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
- struct dwmci_host *host = NULL;
+ struct dwmci_host *host;
+
+ /* calloc for zero init */
host = calloc(sizeof(struct dwmci_host), 1);
if (!host) {
printf("dwmci_host calloc fail!\n");
return -1;
}
- host->name = SOCFPGA_NAME;
+ host->name = "SOCFPGA DWMMC";
host->ioaddr = (void *)regbase;
host->buswidth = bus_width;
host->clksel = socfpga_dwmci_clksel;
int board_nand_init(struct nand_chip *nand)
{
nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
+#if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+#endif
#if defined(CONFIG_NAND_ECC_BCH)
nand->ecc.mode = NAND_ECC_SOFT_BCH;
#else
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
+obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
+obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CS8900) += cs8900.o
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifdef BCM_GMAC_DEBUG
+#ifndef DEBUG
+#define DEBUG
+#endif
+#endif
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <phy.h>
+
+#include "bcm-sf2-eth.h"
+#include "bcm-sf2-eth-gmac.h"
+
+#define SPINWAIT(exp, us) { \
+ uint countdown = (us) + 9; \
+ while ((exp) && (countdown >= 10)) {\
+ udelay(10); \
+ countdown -= 10; \
+ } \
+}
+
+static int gmac_disable_dma(struct eth_dma *dma, int dir);
+static int gmac_enable_dma(struct eth_dma *dma, int dir);
+
+/* DMA Descriptor */
+typedef struct {
+ /* misc control bits */
+ uint32_t ctrl1;
+ /* buffer count and address extension */
+ uint32_t ctrl2;
+ /* memory address of the date buffer, bits 31:0 */
+ uint32_t addrlow;
+ /* memory address of the date buffer, bits 63:32 */
+ uint32_t addrhigh;
+} dma64dd_t;
+
+uint32_t g_dmactrlflags;
+
+static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags)
+{
+ debug("%s enter\n", __func__);
+
+ g_dmactrlflags &= ~mask;
+ g_dmactrlflags |= flags;
+
+ /* If trying to enable parity, check if parity is actually supported */
+ if (g_dmactrlflags & DMA_CTRL_PEN) {
+ uint32_t control;
+
+ control = readl(GMAC0_DMA_TX_CTRL_ADDR);
+ writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR);
+ if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) {
+ /*
+ * We *can* disable it, therefore it is supported;
+ * restore control register
+ */
+ writel(control, GMAC0_DMA_TX_CTRL_ADDR);
+ } else {
+ /* Not supported, don't allow it to be enabled */
+ g_dmactrlflags &= ~DMA_CTRL_PEN;
+ }
+ }
+
+ return g_dmactrlflags;
+}
+
+static inline void reg32_clear_bits(uint32_t reg, uint32_t value)
+{
+ uint32_t v = readl(reg);
+ v &= ~(value);
+ writel(v, reg);
+}
+
+static inline void reg32_set_bits(uint32_t reg, uint32_t value)
+{
+ uint32_t v = readl(reg);
+ v |= value;
+ writel(v, reg);
+}
+
+#ifdef BCM_GMAC_DEBUG
+static void dma_tx_dump(struct eth_dma *dma)
+{
+ dma64dd_t *descp = NULL;
+ uint8_t *bufp;
+ int i;
+
+ printf("TX DMA Register:\n");
+ printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
+ readl(GMAC0_DMA_TX_CTRL_ADDR),
+ readl(GMAC0_DMA_TX_PTR_ADDR),
+ readl(GMAC0_DMA_TX_ADDR_LOW_ADDR),
+ readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR),
+ readl(GMAC0_DMA_TX_STATUS0_ADDR),
+ readl(GMAC0_DMA_TX_STATUS1_ADDR));
+
+ printf("TX Descriptors:\n");
+ for (i = 0; i < TX_BUF_NUM; i++) {
+ descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
+ printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
+ descp->ctrl1, descp->ctrl2,
+ descp->addrhigh, descp->addrlow);
+ }
+
+ printf("TX Buffers:\n");
+ /* Initialize TX DMA descriptor table */
+ for (i = 0; i < TX_BUF_NUM; i++) {
+ bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE);
+ printf("buf%d:0x%x; ", i, (uint32_t)bufp);
+ }
+ printf("\n");
+}
+
+static void dma_rx_dump(struct eth_dma *dma)
+{
+ dma64dd_t *descp = NULL;
+ uint8_t *bufp;
+ int i;
+
+ printf("RX DMA Register:\n");
+ printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
+ readl(GMAC0_DMA_RX_CTRL_ADDR),
+ readl(GMAC0_DMA_RX_PTR_ADDR),
+ readl(GMAC0_DMA_RX_ADDR_LOW_ADDR),
+ readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR),
+ readl(GMAC0_DMA_RX_STATUS0_ADDR),
+ readl(GMAC0_DMA_RX_STATUS1_ADDR));
+
+ printf("RX Descriptors:\n");
+ for (i = 0; i < RX_BUF_NUM; i++) {
+ descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
+ printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
+ descp->ctrl1, descp->ctrl2,
+ descp->addrhigh, descp->addrlow);
+ }
+
+ printf("RX Buffers:\n");
+ for (i = 0; i < RX_BUF_NUM; i++) {
+ bufp = dma->rx_buf + i * RX_BUF_SIZE;
+ printf("buf%d:0x%x; ", i, (uint32_t)bufp);
+ }
+ printf("\n");
+}
+#endif
+
+static int dma_tx_init(struct eth_dma *dma)
+{
+ dma64dd_t *descp = NULL;
+ uint8_t *bufp;
+ int i;
+ uint32_t ctrl;
+
+ debug("%s enter\n", __func__);
+
+ /* clear descriptor memory */
+ memset((void *)(dma->tx_desc_aligned), 0,
+ TX_BUF_NUM * sizeof(dma64dd_t));
+ memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE);
+
+ /* Initialize TX DMA descriptor table */
+ for (i = 0; i < TX_BUF_NUM; i++) {
+ descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
+ bufp = dma->tx_buf + i * TX_BUF_SIZE;
+ /* clear buffer memory */
+ memset((void *)bufp, 0, TX_BUF_SIZE);
+
+ ctrl = 0;
+ /* if last descr set endOfTable */
+ if (i == (TX_BUF_NUM-1))
+ ctrl = D64_CTRL1_EOT;
+ descp->ctrl1 = ctrl;
+ descp->ctrl2 = 0;
+ descp->addrlow = (uint32_t)bufp;
+ descp->addrhigh = 0;
+ }
+
+ /* flush descriptor and buffer */
+ descp = dma->tx_desc_aligned;
+ bufp = dma->tx_buf;
+ flush_dcache_range((unsigned long)descp,
+ (unsigned long)(descp +
+ sizeof(dma64dd_t) * TX_BUF_NUM));
+ flush_dcache_range((unsigned long)(bufp),
+ (unsigned long)(bufp + TX_BUF_SIZE * TX_BUF_NUM));
+
+ /* initialize the DMA channel */
+ writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR);
+ writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
+
+ /* now update the dma last descriptor */
+ writel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK,
+ GMAC0_DMA_TX_PTR_ADDR);
+
+ return 0;
+}
+
+static int dma_rx_init(struct eth_dma *dma)
+{
+ uint32_t last_desc;
+ dma64dd_t *descp = NULL;
+ uint8_t *bufp;
+ uint32_t ctrl;
+ int i;
+
+ debug("%s enter\n", __func__);
+
+ /* clear descriptor memory */
+ memset((void *)(dma->rx_desc_aligned), 0,
+ RX_BUF_NUM * sizeof(dma64dd_t));
+ /* clear buffer memory */
+ memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE);
+
+ /* Initialize RX DMA descriptor table */
+ for (i = 0; i < RX_BUF_NUM; i++) {
+ descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
+ bufp = dma->rx_buf + i * RX_BUF_SIZE;
+ ctrl = 0;
+ /* if last descr set endOfTable */
+ if (i == (RX_BUF_NUM - 1))
+ ctrl = D64_CTRL1_EOT;
+ descp->ctrl1 = ctrl;
+ descp->ctrl2 = RX_BUF_SIZE;
+ descp->addrlow = (uint32_t)bufp;
+ descp->addrhigh = 0;
+
+ last_desc = ((uint32_t)(descp) & D64_XP_LD_MASK)
+ + sizeof(dma64dd_t);
+ }
+
+ descp = dma->rx_desc_aligned;
+ bufp = dma->rx_buf;
+ /* flush descriptor and buffer */
+ flush_dcache_range((unsigned long)descp,
+ (unsigned long)(descp +
+ sizeof(dma64dd_t) * RX_BUF_NUM));
+ flush_dcache_range((unsigned long)(bufp),
+ (unsigned long)(bufp + RX_BUF_SIZE * RX_BUF_NUM));
+
+ /* initailize the DMA channel */
+ writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR);
+ writel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR);
+
+ /* now update the dma last descriptor */
+ writel(last_desc, GMAC0_DMA_RX_PTR_ADDR);
+
+ return 0;
+}
+
+static int dma_init(struct eth_dma *dma)
+{
+ debug(" %s enter\n", __func__);
+
+ /*
+ * Default flags: For backwards compatibility both
+ * Rx Overflow Continue and Parity are DISABLED.
+ */
+ dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0);
+
+ debug("rx burst len 0x%x\n",
+ (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK)
+ >> D64_RC_BL_SHIFT);
+ debug("tx burst len 0x%x\n",
+ (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK)
+ >> D64_XC_BL_SHIFT);
+
+ dma_tx_init(dma);
+ dma_rx_init(dma);
+
+ /* From end of chip_init() */
+ /* enable the overflow continue feature and disable parity */
+ dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */,
+ DMA_CTRL_ROC /* value */);
+
+ return 0;
+}
+
+static int dma_deinit(struct eth_dma *dma)
+{
+ debug(" %s enter\n", __func__);
+
+ gmac_disable_dma(dma, MAC_DMA_RX);
+ gmac_disable_dma(dma, MAC_DMA_TX);
+
+ free(dma->tx_buf);
+ dma->tx_buf = NULL;
+ free(dma->tx_desc);
+ dma->tx_desc = NULL;
+ dma->tx_desc_aligned = NULL;
+
+ free(dma->rx_buf);
+ dma->rx_buf = NULL;
+ free(dma->rx_desc);
+ dma->rx_desc = NULL;
+ dma->rx_desc_aligned = NULL;
+
+ return 0;
+}
+
+int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
+{
+ uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE;
+
+ /* kick off the dma */
+ size_t len = length;
+ int txout = dma->cur_tx_index;
+ uint32_t flags;
+ dma64dd_t *descp = NULL;
+ uint32_t ctrl;
+ uint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) +
+ sizeof(dma64dd_t)) & D64_XP_LD_MASK;
+ size_t buflen;
+
+ debug("%s enter\n", __func__);
+
+ /* load the buffer */
+ memcpy(bufp, packet, len);
+
+ /* Add 4 bytes for Ethernet FCS/CRC */
+ buflen = len + 4;
+
+ ctrl = (buflen & D64_CTRL2_BC_MASK);
+
+ /* the transmit will only be one frame or set SOF, EOF */
+ /* also set int on completion */
+ flags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF;
+
+ /* txout points to the descriptor to uset */
+ /* if last descriptor then set EOT */
+ if (txout == (TX_BUF_NUM - 1)) {
+ flags |= D64_CTRL1_EOT;
+ last_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK;
+ }
+
+ /* write the descriptor */
+ descp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout;
+ descp->addrlow = (uint32_t)bufp;
+ descp->addrhigh = 0;
+ descp->ctrl1 = flags;
+ descp->ctrl2 = ctrl;
+
+ /* flush descriptor and buffer */
+ flush_dcache_range((unsigned long)descp,
+ (unsigned long)(descp + sizeof(dma64dd_t)));
+ flush_dcache_range((unsigned long)bufp,
+ (unsigned long)(bufp + TX_BUF_SIZE));
+
+ /* now update the dma last descriptor */
+ writel(last_desc, GMAC0_DMA_TX_PTR_ADDR);
+
+ /* tx dma should be enabled so packet should go out */
+
+ /* update txout */
+ dma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1);
+
+ return 0;
+}
+
+bool gmac_check_tx_done(struct eth_dma *dma)
+{
+ /* wait for tx to complete */
+ uint32_t intstatus;
+ bool xfrdone = false;
+
+ debug("%s enter\n", __func__);
+
+ intstatus = readl(GMAC0_INT_STATUS_ADDR);
+
+ debug("int(0x%x)\n", intstatus);
+ if (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) {
+ xfrdone = true;
+ /* clear the int bits */
+ intstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3);
+ writel(intstatus, GMAC0_INT_STATUS_ADDR);
+ } else {
+ debug("Tx int(0x%x)\n", intstatus);
+ }
+
+ return xfrdone;
+}
+
+int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
+{
+ void *bufp, *datap;
+ size_t rcvlen = 0, buflen = 0;
+ uint32_t stat0 = 0, stat1 = 0;
+ uint32_t control, offset;
+ uint8_t statbuf[HWRXOFF*2];
+
+ int index, curr, active;
+ dma64dd_t *descp = NULL;
+
+ /* udelay(50); */
+
+ /*
+ * this api will check if a packet has been received.
+ * If so it will return the address of the buffer and current
+ * descriptor index will be incremented to the
+ * next descriptor. Once done with the frame the buffer should be
+ * added back onto the descriptor and the lastdscr should be updated
+ * to this descriptor.
+ */
+ index = dma->cur_rx_index;
+ offset = (uint32_t)(dma->rx_desc_aligned);
+ stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK;
+ stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK;
+ curr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
+ active = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
+
+ /* check if any frame */
+ if (index == curr)
+ return -1;
+
+ debug("received packet\n");
+ debug("expect(0x%x) curr(0x%x) active(0x%x)\n", index, curr, active);
+ /* remove warning */
+ if (index == active)
+ ;
+
+ /* get the packet pointer that corresponds to the rx descriptor */
+ bufp = dma->rx_buf + index * RX_BUF_SIZE;
+
+ descp = (dma64dd_t *)(dma->rx_desc_aligned) + index;
+ /* flush descriptor and buffer */
+ flush_dcache_range((unsigned long)descp,
+ (unsigned long)(descp + sizeof(dma64dd_t)));
+ flush_dcache_range((unsigned long)bufp,
+ (unsigned long)(bufp + RX_BUF_SIZE));
+
+ buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK);
+
+ stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR);
+ stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR);
+
+ debug("bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\n",
+ (uint32_t)bufp, index, buflen, stat0, stat1);
+
+ dma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1);
+
+ /* get buffer offset */
+ control = readl(GMAC0_DMA_RX_CTRL_ADDR);
+ offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT;
+ rcvlen = *(uint16_t *)bufp;
+
+ debug("Received %d bytes\n", rcvlen);
+ /* copy status into temp buf then copy data from rx buffer */
+ memcpy(statbuf, bufp, offset);
+ datap = (void *)((uint32_t)bufp + offset);
+ memcpy(buf, datap, rcvlen);
+
+ /* update descriptor that is being added back on ring */
+ descp->ctrl2 = RX_BUF_SIZE;
+ descp->addrlow = (uint32_t)bufp;
+ descp->addrhigh = 0;
+ /* flush descriptor */
+ flush_dcache_range((unsigned long)descp,
+ (unsigned long)(descp + sizeof(dma64dd_t)));
+
+ /* set the lastdscr for the rx ring */
+ writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
+
+ return (int)rcvlen;
+}
+
+static int gmac_disable_dma(struct eth_dma *dma, int dir)
+{
+ int status;
+
+ debug("%s enter\n", __func__);
+
+ if (dir == MAC_DMA_TX) {
+ /* address PR8249/PR7577 issue */
+ /* suspend tx DMA first */
+ writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR);
+ SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
+ D64_XS0_XS_MASK)) !=
+ D64_XS0_XS_DISABLED) &&
+ (status != D64_XS0_XS_IDLE) &&
+ (status != D64_XS0_XS_STOPPED), 10000);
+
+ /*
+ * PR2414 WAR: DMA engines are not disabled until
+ * transfer finishes
+ */
+ writel(0, GMAC0_DMA_TX_CTRL_ADDR);
+ SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
+ D64_XS0_XS_MASK)) !=
+ D64_XS0_XS_DISABLED), 10000);
+
+ /* wait for the last transaction to complete */
+ udelay(2);
+
+ status = (status == D64_XS0_XS_DISABLED);
+ } else {
+ /*
+ * PR2414 WAR: DMA engines are not disabled until
+ * transfer finishes
+ */
+ writel(0, GMAC0_DMA_RX_CTRL_ADDR);
+ SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) &
+ D64_RS0_RS_MASK)) !=
+ D64_RS0_RS_DISABLED), 10000);
+
+ status = (status == D64_RS0_RS_DISABLED);
+ }
+
+ return status;
+}
+
+static int gmac_enable_dma(struct eth_dma *dma, int dir)
+{
+ uint32_t control;
+
+ debug("%s enter\n", __func__);
+
+ if (dir == MAC_DMA_TX) {
+ dma->cur_tx_index = 0;
+
+ /*
+ * These bits 20:18 (burstLen) of control register can be
+ * written but will take effect only if these bits are
+ * valid. So this will not affect previous versions
+ * of the DMA. They will continue to have those bits set to 0.
+ */
+ control = readl(GMAC0_DMA_TX_CTRL_ADDR);
+
+ control |= D64_XC_XE;
+ if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
+ control |= D64_XC_PD;
+
+ writel(control, GMAC0_DMA_TX_CTRL_ADDR);
+
+ /* initailize the DMA channel */
+ writel((uint32_t)(dma->tx_desc_aligned),
+ GMAC0_DMA_TX_ADDR_LOW_ADDR);
+ writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
+ } else {
+ dma->cur_rx_index = 0;
+
+ control = (readl(GMAC0_DMA_RX_CTRL_ADDR) &
+ D64_RC_AE) | D64_RC_RE;
+
+ if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
+ control |= D64_RC_PD;
+
+ if (g_dmactrlflags & DMA_CTRL_ROC)
+ control |= D64_RC_OC;
+
+ /*
+ * These bits 20:18 (burstLen) of control register can be
+ * written but will take effect only if these bits are
+ * valid. So this will not affect previous versions
+ * of the DMA. They will continue to have those bits set to 0.
+ */
+ control &= ~D64_RC_BL_MASK;
+ /* Keep default Rx burstlen */
+ control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK;
+ control |= HWRXOFF << D64_RC_RO_SHIFT;
+
+ writel(control, GMAC0_DMA_RX_CTRL_ADDR);
+
+ /*
+ * the rx descriptor ring should have
+ * the addresses set properly;
+ * set the lastdscr for the rx ring
+ */
+ writel(((uint32_t)(dma->rx_desc_aligned) +
+ (RX_BUF_NUM - 1) * RX_BUF_SIZE) &
+ D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
+ }
+
+ return 0;
+}
+
+bool gmac_mii_busywait(unsigned int timeout)
+{
+ uint32_t tmp = 0;
+
+ while (timeout > 10) {
+ tmp = readl(GMAC_MII_CTRL_ADDR);
+ if (tmp & (1 << GMAC_MII_BUSY_SHIFT)) {
+ udelay(10);
+ timeout -= 10;
+ } else {
+ break;
+ }
+ }
+ return tmp & (1 << GMAC_MII_BUSY_SHIFT);
+}
+
+int gmac_miiphy_read(const char *devname, unsigned char phyaddr,
+ unsigned char reg, unsigned short *value)
+{
+ uint32_t tmp = 0;
+
+ (void)devname;
+
+ /* Busy wait timeout is 1ms */
+ if (gmac_mii_busywait(1000)) {
+ error("%s: Prepare MII read: MII/MDIO busy\n", __func__);
+ return -1;
+ }
+
+ /* Read operation */
+ tmp = GMAC_MII_DATA_READ_CMD;
+ tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
+ (reg << GMAC_MII_PHY_REG_SHIFT);
+ debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg);
+ writel(tmp, GMAC_MII_DATA_ADDR);
+
+ if (gmac_mii_busywait(1000)) {
+ error("%s: MII read failure: MII/MDIO busy\n", __func__);
+ return -1;
+ }
+
+ *value = readl(GMAC_MII_DATA_ADDR) & 0xffff;
+ debug("MII read data 0x%x\n", *value);
+ return 0;
+}
+
+int gmac_miiphy_write(const char *devname, unsigned char phyaddr,
+ unsigned char reg, unsigned short value)
+{
+ uint32_t tmp = 0;
+
+ (void)devname;
+
+ /* Busy wait timeout is 1ms */
+ if (gmac_mii_busywait(1000)) {
+ error("%s: Prepare MII write: MII/MDIO busy\n", __func__);
+ return -1;
+ }
+
+ /* Write operation */
+ tmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff);
+ tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
+ (reg << GMAC_MII_PHY_REG_SHIFT));
+ debug("MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\n",
+ tmp, phyaddr, reg, value);
+ writel(tmp, GMAC_MII_DATA_ADDR);
+
+ if (gmac_mii_busywait(1000)) {
+ error("%s: MII write failure: MII/MDIO busy\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+void gmac_init_reset(void)
+{
+ debug("%s enter\n", __func__);
+
+ /* set command config reg CC_SR */
+ reg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
+ udelay(GMAC_RESET_DELAY);
+}
+
+void gmac_clear_reset(void)
+{
+ debug("%s enter\n", __func__);
+
+ /* clear command config reg CC_SR */
+ reg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
+ udelay(GMAC_RESET_DELAY);
+}
+
+static void gmac_enable_local(bool en)
+{
+ uint32_t cmdcfg;
+
+ debug("%s enter\n", __func__);
+
+ /* read command config reg */
+ cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
+
+ /* put mac in reset */
+ gmac_init_reset();
+
+ cmdcfg |= CC_SR;
+
+ /* first deassert rx_ena and tx_ena while in reset */
+ cmdcfg &= ~(CC_RE | CC_TE);
+ /* write command config reg */
+ writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
+
+ /* bring mac out of reset */
+ gmac_clear_reset();
+
+ /* if not enable exit now */
+ if (!en)
+ return;
+
+ /* enable the mac transmit and receive paths now */
+ udelay(2);
+ cmdcfg &= ~CC_SR;
+ cmdcfg |= (CC_RE | CC_TE);
+
+ /* assert rx_ena and tx_ena when out of reset to enable the mac */
+ writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
+
+ return;
+}
+
+int gmac_enable(void)
+{
+ gmac_enable_local(1);
+
+ /* clear interrupts */
+ writel(I_INTMASK, GMAC0_INT_STATUS_ADDR);
+ return 0;
+}
+
+int gmac_disable(void)
+{
+ gmac_enable_local(0);
+ return 0;
+}
+
+int gmac_set_speed(int speed, int duplex)
+{
+ uint32_t cmdcfg;
+ uint32_t hd_ena;
+ uint32_t speed_cfg;
+
+ hd_ena = duplex ? 0 : CC_HD;
+ if (speed == 1000) {
+ speed_cfg = 2;
+ } else if (speed == 100) {
+ speed_cfg = 1;
+ } else if (speed == 10) {
+ speed_cfg = 0;
+ } else {
+ error("%s: Invalid GMAC speed(%d)!\n", __func__, speed);
+ return -1;
+ }
+
+ cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
+ cmdcfg &= ~(CC_ES_MASK | CC_HD);
+ cmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena);
+
+ printf("Change GMAC speed to %dMB\n", speed);
+ debug("GMAC speed cfg 0x%x\n", cmdcfg);
+ writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
+
+ return 0;
+}
+
+int gmac_set_mac_addr(unsigned char *mac)
+{
+ /* set our local address */
+ debug("GMAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ writel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR);
+ writew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR);
+
+ return 0;
+}
+
+int gmac_mac_init(struct eth_device *dev)
+{
+ struct eth_info *eth = (struct eth_info *)(dev->priv);
+ struct eth_dma *dma = &(eth->dma);
+
+ uint32_t tmp;
+ uint32_t cmdcfg;
+ int chipid;
+
+ debug("%s enter\n", __func__);
+
+ /* Always use GMAC0 */
+ printf("Using GMAC%d\n", 0);
+
+ /* Reset AMAC0 core */
+ writel(0, AMAC0_IDM_RESET_ADDR);
+ tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR);
+ /* Set clock */
+ tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT);
+ tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT);
+ /* Set Tx clock */
+ tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT);
+ writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR);
+
+ /* reset gmac */
+ /*
+ * As AMAC is just reset, NO need?
+ * set eth_data into loopback mode to ensure no rx traffic
+ * gmac_loopback(eth_data, TRUE);
+ * ET_TRACE(("%s gmac loopback\n", __func__));
+ * udelay(1);
+ */
+
+ cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
+ cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML |
+ CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI |
+ CC_PAD_EN | CC_PF);
+ cmdcfg |= (CC_PROM | CC_NLC | CC_CFE);
+ /* put mac in reset */
+ gmac_init_reset();
+ writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
+ gmac_clear_reset();
+
+ /* enable clear MIB on read */
+ reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR);
+ /* PHY: set smi_master to drive mdc_clk */
+ reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE);
+
+ /* clear persistent sw intstatus */
+ writel(0, GMAC0_INT_STATUS_ADDR);
+
+ if (dma_init(dma) < 0) {
+ error("%s: GMAC dma_init failed\n", __func__);
+ goto err_exit;
+ }
+
+ chipid = CHIPID;
+ printf("%s: Chip ID: 0x%x\n", __func__, chipid);
+
+ /* set switch bypass mode */
+ tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR);
+ tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT);
+
+ /* Switch mode */
+ /* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */
+
+ writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR);
+
+ tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR);
+ tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT);
+ writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR);
+
+ /* Set MDIO to internal GPHY */
+ tmp = readl(GMAC_MII_CTRL_ADDR);
+ /* Select internal MDC/MDIO bus*/
+ tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT);
+ /* select MDC/MDIO connecting to on-chip internal PHYs */
+ tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT);
+ /*
+ * give bit[6:0](MDCDIV) with required divisor to set
+ * the MDC clock frequency, 66MHZ/0x1A=2.5MHZ
+ */
+ tmp |= 0x1A;
+
+ writel(tmp, GMAC_MII_CTRL_ADDR);
+
+ if (gmac_mii_busywait(1000)) {
+ error("%s: Configure MDIO: MII/MDIO busy\n", __func__);
+ goto err_exit;
+ }
+
+ /* Configure GMAC0 */
+ /* enable one rx interrupt per received frame */
+ writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR);
+
+ /* read command config reg */
+ cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
+ /* enable 802.3x tx flow control (honor received PAUSE frames) */
+ cmdcfg &= ~CC_RPI;
+ /* enable promiscuous mode */
+ cmdcfg |= CC_PROM;
+ /* Disable loopback mode */
+ cmdcfg &= ~CC_ML;
+ /* set the speed */
+ cmdcfg &= ~(CC_ES_MASK | CC_HD);
+ /* Set to 1Gbps and full duplex by default */
+ cmdcfg |= (2 << CC_ES_SHIFT);
+
+ /* put mac in reset */
+ gmac_init_reset();
+ /* write register */
+ writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
+ /* bring mac out of reset */
+ gmac_clear_reset();
+
+ /* set max frame lengths; account for possible vlan tag */
+ writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR);
+
+ return 0;
+
+err_exit:
+ dma_deinit(dma);
+ return -1;
+}
+
+int gmac_add(struct eth_device *dev)
+{
+ struct eth_info *eth = (struct eth_info *)(dev->priv);
+ struct eth_dma *dma = &(eth->dma);
+ void *tmp;
+
+ /*
+ * Desc has to be 16-byte aligned ?
+ * If it is 8-byte aligned by malloc, fail Tx
+ */
+ tmp = malloc(sizeof(dma64dd_t) * TX_BUF_NUM + 8);
+ if (tmp == NULL) {
+ printf("%s: Failed to allocate TX desc Buffer\n", __func__);
+ return -1;
+ }
+
+ dma->tx_desc = (void *)tmp;
+ dma->tx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
+ debug("TX Descriptor Buffer: %p; length: 0x%x\n",
+ dma->tx_desc_aligned, sizeof(dma64dd_t) * TX_BUF_NUM);
+
+ tmp = malloc(TX_BUF_SIZE * TX_BUF_NUM);
+ if (tmp == NULL) {
+ printf("%s: Failed to allocate TX Data Buffer\n", __func__);
+ free(dma->tx_desc);
+ return -1;
+ }
+ dma->tx_buf = (uint8_t *)tmp;
+ debug("TX Data Buffer: %p; length: 0x%x\n",
+ dma->tx_buf, TX_BUF_SIZE * TX_BUF_NUM);
+
+ /* Desc has to be 16-byte aligned ? */
+ tmp = malloc(sizeof(dma64dd_t) * RX_BUF_NUM + 8);
+ if (tmp == NULL) {
+ printf("%s: Failed to allocate RX Descriptor\n", __func__);
+ free(dma->tx_desc);
+ free(dma->tx_buf);
+ return -1;
+ }
+ dma->rx_desc = tmp;
+ dma->rx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
+ debug("RX Descriptor Buffer: %p, length: 0x%x\n",
+ dma->rx_desc_aligned, sizeof(dma64dd_t) * RX_BUF_NUM);
+
+ tmp = malloc(RX_BUF_SIZE * RX_BUF_NUM);
+ if (tmp == NULL) {
+ printf("%s: Failed to allocate RX Data Buffer\n", __func__);
+ free(dma->tx_desc);
+ free(dma->tx_buf);
+ free(dma->rx_desc);
+ return -1;
+ }
+ dma->rx_buf = tmp;
+ debug("RX Data Buffer: %p; length: 0x%x\n",
+ dma->rx_buf, RX_BUF_SIZE * RX_BUF_NUM);
+
+ g_dmactrlflags = 0;
+
+ eth->phy_interface = PHY_INTERFACE_MODE_GMII;
+
+ dma->tx_packet = gmac_tx_packet;
+ dma->check_tx_done = gmac_check_tx_done;
+
+ dma->check_rx_done = gmac_check_rx_done;
+
+ dma->enable_dma = gmac_enable_dma;
+ dma->disable_dma = gmac_disable_dma;
+
+ eth->miiphy_read = gmac_miiphy_read;
+ eth->miiphy_write = gmac_miiphy_write;
+
+ eth->mac_init = gmac_mac_init;
+ eth->disable_mac = gmac_disable;
+ eth->enable_mac = gmac_enable;
+ eth->set_mac_addr = gmac_set_mac_addr;
+ eth->set_mac_speed = gmac_set_speed;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BCM_SF2_ETH_GMAC_H_
+#define _BCM_SF2_ETH_GMAC_H_
+
+#define BCM_SF2_ETH_MAC_NAME "gmac"
+
+#ifndef ETHHW_PORT_INT
+#define ETHHW_PORT_INT 8
+#endif
+
+#define GMAC0_REG_BASE 0x18042000
+#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE
+#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
+#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
+#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
+
+
+#define GMAC_DMA_PTR_OFFSET 0x04
+#define GMAC_DMA_ADDR_LOW_OFFSET 0x08
+#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
+#define GMAC_DMA_STATUS0_OFFSET 0x10
+#define GMAC_DMA_STATUS1_OFFSET 0x14
+
+#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
+#define GMAC0_DMA_TX_PTR_ADDR \
+ (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
+#define GMAC0_DMA_TX_ADDR_LOW_ADDR \
+ (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
+#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \
+ (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
+#define GMAC0_DMA_TX_STATUS0_ADDR \
+ (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
+#define GMAC0_DMA_TX_STATUS1_ADDR \
+ (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
+
+#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220)
+#define GMAC0_DMA_RX_PTR_ADDR \
+ (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
+#define GMAC0_DMA_RX_ADDR_LOW_ADDR \
+ (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
+#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \
+ (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
+#define GMAC0_DMA_RX_STATUS0_ADDR \
+ (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
+#define GMAC0_DMA_RX_STATUS1_ADDR \
+ (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
+
+#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808)
+#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c)
+#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810)
+#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814)
+
+#define GMAC0_IRL_FRAMECOUNT_SHIFT 24
+
+/* transmit channel control */
+/* transmit enable */
+#define D64_XC_XE 0x00000001
+/* transmit suspend request */
+#define D64_XC_SE 0x00000002
+/* parity check disable */
+#define D64_XC_PD 0x00000800
+/* BurstLen bits */
+#define D64_XC_BL_MASK 0x001C0000
+#define D64_XC_BL_SHIFT 18
+
+/* transmit descriptor table pointer */
+/* last valid descriptor */
+#define D64_XP_LD_MASK 0x00001fff
+
+/* transmit channel status */
+/* transmit state */
+#define D64_XS0_XS_MASK 0xf0000000
+#define D64_XS0_XS_SHIFT 28
+#define D64_XS0_XS_DISABLED 0x00000000
+#define D64_XS0_XS_ACTIVE 0x10000000
+#define D64_XS0_XS_IDLE 0x20000000
+#define D64_XS0_XS_STOPPED 0x30000000
+#define D64_XS0_XS_SUSP 0x40000000
+
+/* receive channel control */
+/* receive enable */
+#define D64_RC_RE 0x00000001
+/* address extension bits */
+#define D64_RC_AE 0x00030000
+/* overflow continue */
+#define D64_RC_OC 0x00000400
+/* parity check disable */
+#define D64_RC_PD 0x00000800
+/* receive frame offset */
+#define D64_RC_RO_MASK 0x000000fe
+#define D64_RC_RO_SHIFT 1
+/* BurstLen bits */
+#define D64_RC_BL_MASK 0x001C0000
+#define D64_RC_BL_SHIFT 18
+
+/* flags for dma controller */
+/* partity enable */
+#define DMA_CTRL_PEN (1 << 0)
+/* rx overflow continue */
+#define DMA_CTRL_ROC (1 << 1)
+
+/* receive descriptor table pointer */
+/* last valid descriptor */
+#define D64_RP_LD_MASK 0x00001fff
+
+/* receive channel status */
+/* current descriptor pointer */
+#define D64_RS0_CD_MASK 0x00001fff
+/* receive state */
+#define D64_RS0_RS_MASK 0xf0000000
+#define D64_RS0_RS_SHIFT 28
+#define D64_RS0_RS_DISABLED 0x00000000
+#define D64_RS0_RS_ACTIVE 0x10000000
+#define D64_RS0_RS_IDLE 0x20000000
+#define D64_RS0_RS_STOPPED 0x30000000
+#define D64_RS0_RS_SUSP 0x40000000
+
+/* descriptor control flags 1 */
+/* core specific flags */
+#define D64_CTRL_COREFLAGS 0x0ff00000
+/* end of descriptor table */
+#define D64_CTRL1_EOT ((uint32_t)1 << 28)
+/* interrupt on completion */
+#define D64_CTRL1_IOC ((uint32_t)1 << 29)
+/* end of frame */
+#define D64_CTRL1_EOF ((uint32_t)1 << 30)
+/* start of frame */
+#define D64_CTRL1_SOF ((uint32_t)1 << 31)
+
+/* descriptor control flags 2 */
+/* buffer byte count. real data len must <= 16KB */
+#define D64_CTRL2_BC_MASK 0x00007fff
+/* address extension bits */
+#define D64_CTRL2_AE 0x00030000
+#define D64_CTRL2_AE_SHIFT 16
+/* parity bit */
+#define D64_CTRL2_PARITY 0x00040000
+/* control flags in the range [27:20] are core-specific and not defined here */
+#define D64_CTRL_CORE_MASK 0x0ff00000
+
+#define DC_MROR 0x00000010
+#define PC_MTE 0x00800000
+
+/* command config */
+#define CC_TE 0x00000001
+#define CC_RE 0x00000002
+#define CC_ES_MASK 0x0000000c
+#define CC_ES_SHIFT 2
+#define CC_PROM 0x00000010
+#define CC_PAD_EN 0x00000020
+#define CC_CF 0x00000040
+#define CC_PF 0x00000080
+#define CC_RPI 0x00000100
+#define CC_TAI 0x00000200
+#define CC_HD 0x00000400
+#define CC_HD_SHIFT 10
+#define CC_SR 0x00002000
+#define CC_ML 0x00008000
+#define CC_AE 0x00400000
+#define CC_CFE 0x00800000
+#define CC_NLC 0x01000000
+#define CC_RL 0x02000000
+#define CC_RED 0x04000000
+#define CC_PE 0x08000000
+#define CC_TPI 0x10000000
+#define CC_AT 0x20000000
+
+#define I_PDEE 0x00000400
+#define I_PDE 0x00000800
+#define I_DE 0x00001000
+#define I_RDU 0x00002000
+#define I_RFO 0x00004000
+#define I_XFU 0x00008000
+#define I_RI 0x00010000
+#define I_XI0 0x01000000
+#define I_XI1 0x02000000
+#define I_XI2 0x04000000
+#define I_XI3 0x08000000
+#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU)
+#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS)
+
+#define I_INTMASK 0x0f01fcff
+
+#define CHIP_DRU_BASE 0x0301d000
+#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc)
+#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194)
+
+#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0
+#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13
+
+#define AMAC0_IDM_RESET_ADDR 0x18110800
+#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408
+#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6
+#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5
+#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3
+
+#define CHIPA_CHIP_ID_ADDR 0x18000000
+#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)
+#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)
+#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)
+
+#define GMAC_MII_CTRL_ADDR 0x18002000
+#define GMAC_MII_CTRL_BYP_SHIFT 10
+#define GMAC_MII_CTRL_EXT_SHIFT 9
+#define GMAC_MII_DATA_ADDR 0x18002004
+#define GMAC_MII_DATA_READ_CMD 0x60020000
+#define GMAC_MII_DATA_WRITE_CMD 0x50020000
+#define GMAC_MII_BUSY_SHIFT 8
+#define GMAC_MII_PHY_ADDR_SHIFT 23
+#define GMAC_MII_PHY_REG_SHIFT 18
+
+#define GMAC_RESET_DELAY 2
+#define HWRXOFF 30
+#define MAXNAMEL 8
+#define NUMTXQ 4
+
+int gmac_add(struct eth_device *dev);
+
+#endif /* _BCM_SF2_ETH_GMAC_H_ */
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <config.h>
+
+#include <phy.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+#include <netdev.h>
+#include "bcm-sf2-eth.h"
+
+#if defined(CONFIG_BCM_SF2_ETH_GMAC)
+#include "bcm-sf2-eth-gmac.h"
+#else
+#error "bcm_sf2_eth: NEED to define a MAC!"
+#endif
+
+#define BCM_NET_MODULE_DESCRIPTION "Broadcom Starfighter2 Ethernet driver"
+#define BCM_NET_MODULE_VERSION "0.1"
+#define BCM_SF2_ETH_DEV_NAME "bcm_sf2"
+
+static const char banner[] =
+ BCM_NET_MODULE_DESCRIPTION " " BCM_NET_MODULE_VERSION "\n";
+
+static int bcm_sf2_eth_init(struct eth_device *dev)
+{
+ struct eth_info *eth = (struct eth_info *)(dev->priv);
+ struct eth_dma *dma = &(eth->dma);
+ struct phy_device *phydev;
+ int rc = 0;
+ int i;
+
+ rc = eth->mac_init(dev);
+ if (rc) {
+ error("%s: Couldn't cofigure MAC!\n", __func__);
+ return rc;
+ }
+
+ /* disable DMA */
+ dma->disable_dma(dma, MAC_DMA_RX);
+ dma->disable_dma(dma, MAC_DMA_TX);
+
+ eth->port_num = 0;
+ debug("Connecting PHY 0...\n");
+ phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
+ 0, dev, eth->phy_interface);
+ if (phydev != NULL) {
+ eth->port[0] = phydev;
+ eth->port_num += 1;
+ } else {
+ debug("No PHY found for port 0\n");
+ }
+
+ for (i = 0; i < eth->port_num; i++)
+ phy_config(eth->port[i]);
+
+ return rc;
+}
+
+/*
+ * u-boot net functions
+ */
+
+static int bcm_sf2_eth_send(struct eth_device *dev, void *packet, int length)
+{
+ struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);
+ uint8_t *buf = (uint8_t *)packet;
+ int rc = 0;
+ int i = 0;
+
+ debug("%s enter\n", __func__);
+
+ /* load buf and start transmit */
+ rc = dma->tx_packet(dma, buf, length);
+ if (rc) {
+ debug("ERROR - Tx failed\n");
+ return rc;
+ }
+
+ while (!(dma->check_tx_done(dma))) {
+ udelay(100);
+ debug(".");
+ i++;
+ if (i > 20) {
+ error("%s: Tx timeout: retried 20 times\n", __func__);
+ rc = -1;
+ break;
+ }
+ }
+
+ debug("%s exit rc(0x%x)\n", __func__, rc);
+ return rc;
+}
+
+static int bcm_sf2_eth_receive(struct eth_device *dev)
+{
+ struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);
+ uint8_t *buf = (uint8_t *)NetRxPackets[0];
+ int rcvlen;
+ int rc = 0;
+ int i = 0;
+
+ while (1) {
+ /* Poll Rx queue to get a packet */
+ rcvlen = dma->check_rx_done(dma, buf);
+ if (rcvlen < 0) {
+ /* No packet received */
+ rc = -1;
+ debug("\nNO More Rx\n");
+ break;
+ } else if ((rcvlen == 0) || (rcvlen > RX_BUF_SIZE)) {
+ error("%s: Wrong Ethernet packet size (%d B), skip!\n",
+ __func__, rcvlen);
+ break;
+ } else {
+ debug("recieved\n");
+
+ /* Forward received packet to uboot network handler */
+ NetReceive(buf, rcvlen);
+
+ if (++i >= PKTBUFSRX)
+ i = 0;
+ buf = NetRxPackets[i];
+ }
+ }
+
+ return rc;
+}
+
+static int bcm_sf2_eth_write_hwaddr(struct eth_device *dev)
+{
+ struct eth_info *eth = (struct eth_info *)(dev->priv);
+
+ printf(" ETH MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->enetaddr[0], dev->enetaddr[1], dev->enetaddr[2],
+ dev->enetaddr[3], dev->enetaddr[4], dev->enetaddr[5]);
+
+ return eth->set_mac_addr(dev->enetaddr);
+}
+
+static int bcm_sf2_eth_open(struct eth_device *dev, bd_t *bt)
+{
+ struct eth_info *eth = (struct eth_info *)(dev->priv);
+ struct eth_dma *dma = &(eth->dma);
+ int i;
+
+ debug("Enabling BCM SF2 Ethernet.\n");
+
+ /* Set MAC address from env */
+ if (bcm_sf2_eth_write_hwaddr(dev) != 0) {
+ error("%s: MAC set error when opening !\n", __func__);
+ return -1;
+ }
+
+ eth->enable_mac();
+
+ /* enable tx and rx DMA */
+ dma->enable_dma(dma, MAC_DMA_RX);
+ dma->enable_dma(dma, MAC_DMA_TX);
+
+ /*
+ * Need to start PHY here because link speed can change
+ * before each ethernet operation
+ */
+ for (i = 0; i < eth->port_num; i++) {
+ if (phy_startup(eth->port[i])) {
+ error("%s: PHY %d startup failed!\n", __func__, i);
+ if (i == CONFIG_BCM_SF2_ETH_DEFAULT_PORT) {
+ error("%s: No default port %d!\n", __func__, i);
+ return -1;
+ }
+ }
+ }
+
+ /* Set MAC speed using default port */
+ i = CONFIG_BCM_SF2_ETH_DEFAULT_PORT;
+ debug("PHY %d: speed:%d, duplex:%d, link:%d\n", i,
+ eth->port[i]->speed, eth->port[i]->duplex, eth->port[i]->link);
+ eth->set_mac_speed(eth->port[i]->speed, eth->port[i]->duplex);
+
+ debug("Enable Ethernet Done.\n");
+
+ return 0;
+}
+
+static void bcm_sf2_eth_close(struct eth_device *dev)
+{
+ struct eth_info *eth = (struct eth_info *)(dev->priv);
+ struct eth_dma *dma = &(eth->dma);
+
+ /* disable DMA */
+ dma->disable_dma(dma, MAC_DMA_RX);
+ dma->disable_dma(dma, MAC_DMA_TX);
+
+ eth->disable_mac();
+}
+
+int bcm_sf2_eth_register(bd_t *bis, u8 dev_num)
+{
+ struct eth_device *dev;
+ struct eth_info *eth;
+ int rc;
+
+ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ if (dev == NULL) {
+ error("%s: Not enough memory!\n", __func__);
+ return -1;
+ }
+
+ eth = (struct eth_info *)malloc(sizeof(struct eth_info));
+ if (eth == NULL) {
+ error("%s: Not enough memory!\n", __func__);
+ return -1;
+ }
+
+ printf(banner);
+
+ memset(dev, 0, sizeof(*dev));
+ sprintf(dev->name, "%s_%s-%hu", BCM_SF2_ETH_DEV_NAME,
+ BCM_SF2_ETH_MAC_NAME, dev_num);
+
+ dev->priv = (void *)eth;
+ dev->iobase = 0;
+
+ dev->init = bcm_sf2_eth_open;
+ dev->halt = bcm_sf2_eth_close;
+ dev->send = bcm_sf2_eth_send;
+ dev->recv = bcm_sf2_eth_receive;
+ dev->write_hwaddr = bcm_sf2_eth_write_hwaddr;
+
+#ifdef CONFIG_BCM_SF2_ETH_GMAC
+ if (gmac_add(dev)) {
+ free(eth);
+ free(dev);
+ error("%s: Adding GMAC failed!\n", __func__);
+ return -1;
+ }
+#else
+#error "bcm_sf2_eth: NEED to register a MAC!"
+#endif
+
+ eth_register(dev);
+
+#ifdef CONFIG_CMD_MII
+ miiphy_register(dev->name, eth->miiphy_read, eth->miiphy_write);
+#endif
+
+ /* Initialization */
+ debug("Ethernet initialization ...");
+
+ rc = bcm_sf2_eth_init(dev);
+ if (rc != 0) {
+ error("%s: configuration failed!\n", __func__);
+ return -1;
+ }
+
+ printf("Basic ethernet functionality initialized\n");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BCM_SF2_ETH_H_
+#define _BCM_SF2_ETH_H_
+
+#include <phy.h>
+
+#define RX_BUF_SIZE 2048
+/* RX_BUF_NUM must be power of 2 */
+#define RX_BUF_NUM 32
+
+#define TX_BUF_SIZE 2048
+/* TX_BUF_NUM must be power of 2 */
+#define TX_BUF_NUM 2
+
+/* Support 2 Ethernet ports now */
+#define BCM_ETH_MAX_PORT_NUM 2
+
+#define CONFIG_BCM_SF2_ETH_DEFAULT_PORT 0
+
+enum {
+ MAC_DMA_TX = 1,
+ MAC_DMA_RX = 2
+};
+
+struct eth_dma {
+ void *tx_desc_aligned;
+ void *rx_desc_aligned;
+ void *tx_desc;
+ void *rx_desc;
+
+ uint8_t *tx_buf;
+ uint8_t *rx_buf;
+
+ int cur_tx_index;
+ int cur_rx_index;
+
+ int (*tx_packet)(struct eth_dma *dma, void *packet, int length);
+ bool (*check_tx_done)(struct eth_dma *dma);
+
+ int (*check_rx_done)(struct eth_dma *dma, uint8_t *buf);
+
+ int (*enable_dma)(struct eth_dma *dma, int dir);
+ int (*disable_dma)(struct eth_dma *dma, int dir);
+};
+
+struct eth_info {
+ struct eth_dma dma;
+ phy_interface_t phy_interface;
+ struct phy_device *port[BCM_ETH_MAX_PORT_NUM];
+ int port_num;
+
+ int (*miiphy_read)(const char *devname, unsigned char phyaddr,
+ unsigned char reg, unsigned short *value);
+ int (*miiphy_write)(const char *devname, unsigned char phyaddr,
+ unsigned char reg, unsigned short value);
+
+ int (*mac_init)(struct eth_device *dev);
+ int (*enable_mac)(void);
+ int (*disable_mac)(void);
+ int (*set_mac_addr)(unsigned char *mac);
+ int (*set_mac_speed)(int speed, int duplex);
+
+};
+
+#endif /* _BCM_SF2_ETH_H_ */
ulong bootm_disable_interrupts(void);
-/* This is a special function used by bootz */
+/* This is a special function used by booti/bootz */
int bootm_find_ramdisk_fdt(int flag, int argc, char * const argv[]);
int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
#undef DEBUG
#define CONFIG_ARMV7
#define CONFIG_R8A7794
-#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Alt"
#define CONFIG_SH_GPIO_PFC
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
#define CONFIG_OMAP_COMMON
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
#define CONFIG_OMAP_COMMON
#undef DEBUG
#define CONFIG_ARMV7
#define CONFIG_R8A7740
-#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
#define CONFIG_SH_GPIO_PFC
/* Enable Time Command */
#define CONFIG_CMD_TIME
+#define CONFIG_S5P_PA_SYSRAM 0x02020000
+#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
+
+/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
+#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
+
+#define CONFIG_ARMV7_VIRT
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BCM_EP_BOARD_H
+#define __BCM_EP_BOARD_H
+
+#include <asm/arch/configs.h>
+
+/* Architecture, CPU, chip, etc */
+#define CONFIG_ARMV7
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * Memory configuration
+ * (these must be defined elsewhere)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#error CONFIG_SYS_TEXT_BASE must be defined!
+#endif
+#ifndef CONFIG_SYS_SDRAM_BASE
+#error CONFIG_SYS_SDRAM_BASE must be defined!
+#endif
+#ifndef CONFIG_SYS_SDRAM_SIZE
+#error CONFIG_SYS_SDRAM_SIZE must be defined!
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#define CONFIG_STACKSIZE (256 * 1024)
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+#undef CONFIG_CMD_MEMORY
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+#define CONFIG_DOS_PARTITION
+
+/* version string, parser, etc */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* Commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* SHA hashing */
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
+#define CONFIG_CMD_BOOTZ
+
+/* Misc utility code */
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CRC32_VERIFY
+
+#endif /* __BCM_EP_BOARD_H */
* High Level Configuration Options
*/
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
/* High Level Configuration Options */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
#define CONFIG_OMAP_GPIO
* High Level Configuration Options
*/
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_DOCKSTAR /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_MARVELL 1
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
-#define CONFIG_ORION5X 1 /* SOC Family Name */
#define CONFIG_88F5182 1 /* SOC Name */
#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_GOFLEXHOME /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_GURUPLUG /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High level configuration options
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High level configuration options
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
*/
#define CONFIG_MARVELL
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
#define CONFIG_HOSTNAME km_kirkwood_pci
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_FPGA_CONFIG
+#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
/* KM_KIRKWOOD_128M16 */
#elif defined(CONFIG_KM_KIRKWOOD_128M16)
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_FPGA_CONFIG
-
+#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#else
#error ("Board unsupported")
#endif
#undef DEBUG
#define CONFIG_ARMV7
#define CONFIG_R8A7791
-#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
#define CONFIG_SH_GPIO_PFC
#undef DEBUG
-#define CONFIG_RMOBILE
#define CONFIG_SH73A0
#define CONFIG_KZM_A9_GT
#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SoC Family Name */
/* SoC name */
#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
#define CONFIG_KW88F6192
#undef DEBUG
#define CONFIG_ARMV7
#define CONFIG_R8A7790
-#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Lager"
#define CONFIG_SH_GPIO_PFC
* General configuration options
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High Level Configuration Options
*/
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP3_MCX /* working with mcx */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#include <nomadik.h>
#define CONFIG_ARM926EJS
-#define CONFIG_NOMADIK
#define CONFIG_NOMADIK_8815 /* cpu variant */
-#define CONFIG_NOMADIK_NHK8815 /* board variant */
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
*/
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP3430 /* which is in a 3430 */
#define CONFIG_OMAP3_RX51 /* working with RX51 */
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
* High level configuration options
*/
#define CONFIG_OMAP /* This is TI OMAP core */
-#define CONFIG_OMAP34XX /* belonging to 34XX family */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
* High Level Configuration Options
*/
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
*/
#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
#define CONFIG_OMAP_GPIO
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_OMAP_COMMON
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_OPENRD_BASE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_RD6281A /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
* High level configuration
*/
/* Virtual target or real hardware */
-#define CONFIG_SOCFPGA_VIRTUAL_TARGET
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_ENV_IS_NOWHERE
/*
+ * network support
+ */
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_DESIGNWARE_ETH 1
+#endif
+
+#ifdef CONFIG_DESIGNWARE_ETH
+#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
+/* console support for network */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+/* designware */
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#define CONFIG_DW_AUTONEG
+#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+/* EMAC controller and PHY used */
+#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
+#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
+#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+#endif /* CONFIG_DESIGNWARE_ETH */
+
+/*
* L4 Watchdog
*/
#define CONFIG_HW_WATCHDOG
* High Level Configuration Options
*/
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
*/
#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#include <asm/arch/tegra.h> /* get chip and board defs */
#ifndef __CONFIG_TI_OMAP3_COMMON_H__
#define __CONFIG_TI_OMAP3_COMMON_H__
-#define CONFIG_OMAP34XX
#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP44XX 1 /* which is a 44XX */
#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_MISC_INIT_R
#define CONFIG_ARCH_CPU_INIT
#ifndef __CONFIG_TI_OMAP5_COMMON_H
#define __CONFIG_TI_OMAP5_COMMON_H
-#define CONFIG_OMAP54XX
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_NR_DRAM_BANKS 1
/* High Level Configuration Options */
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP_COMMON
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H
-#define DEBUG
-
#ifdef CONFIG_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000)
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
/* SMSC91C111 Ethernet Configuration */
#define CONFIG_SMC91111 1
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTI
+#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0x200000\0" \
- "initrd_addr_r=0xa00000\0" \
- "initrd_size=0x2000000\0" \
- "fdt_addr_r=0x100000\0" \
+ "kernel_addr_r=0x80000000\0" \
+ "initrd_addr_r=0x88000000\0" \
+ "fdt_addr_r=0x83000000\0" \
"fdt_high=0xa0000000\0"
#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#endif /* __VEXPRESS_AEMV8A_H */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SoC Family Name */
/* SoC name */
#define CONFIG_KW88F6281
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/* High Level configuration Options */
#define CONFIG_ARMV7
-#define CONFIG_ZYNQ
/* CPU clock */
#ifndef CONFIG_CPU_FREQ_HZ
int at91emac_register(bd_t *bis, unsigned long iobase);
int au1x00_enet_initialize(bd_t*);
int ax88180_initialize(bd_t *bis);
+int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
int bfin_EMAC_initialize(bd_t *bis);
int calxedaxgmac_initialize(u32 id, ulong base_addr);
int cs8900_initialize(u8 dev_num, int base_addr);
projects / platform / kernel / u-boot.git / commitdiff