* Rewrite of NAND code based on what is in 2.6.12 Linux kernel
Patch by Ladislav Michl, 29 Jun 2005
+* Enable PCI on hmi1001 board
+
+* Fix return values of the jffs2 commands ls/fsload/fsinfo,
+ so we can use them to, e.g., check the existence of a file with
+ "if ls foo; then this; else that; fi" in the hush shell
+ Patch by Andreas Engel, 16 August 2005
+
+* Coding style cleanup
+
+* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
+ Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
+
+* Check return value of malloc in 440gx_enet.c
+ Patch by Travis B. Sawyer, 18 Jul 2005
+
+* Add Sandburst Metrobox and Sandburst Karef board support packages.
+ Second serial port on 440GX now defined as a system device.
+ Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
+ Patch by Travis B. Sawyer, 12 Jul 2005
+
======================================================================
Changes for U-Boot 1.1.3:
======================================================================
+* Minor code cleanup
+
+* Add forgotten new fils from latest VoiceBlue update
+
+* Make bootretry feature work with hush shell.
+ Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too.
+ Patch by Andreas Engel, 19 Jul 2005
+
+* Update Hymod Board Database PHP code in "tools" directory
+ Patch by Murray Jensen, 01 Jul 2005
+
+* Make "tr" command use POSIX compliant; export HOSTOS make variable
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix Murray Jensen's mail address.
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Preserve PHY_BMCR during a soft reset.
+ Patch by Carl Riechers, 24 Jun 2005
+
+* VoiceBlue update: eeprom tool can also store firmware version now.
+ eeprom.bin is runable by jumping at load address.
+ Patch by Ladislav Michl, 23 May 2005
+
+* Move the AT91RM9200DK to the ARM Systems list.
+ Patch by Anders Larsen, 26 Apr 2005
+
+* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3
+ Patch by Anders Larsen, 26 Apr 2005
+
+* measure_gclk() is needed when DEBUG is enabled
+ Patch by Bryan O'Donoghue, 25 Apr 2005
+
+* Add UPD-Checksum code, fix problem in net.c (return instead of break)
+ Patch by Reinhard Arlt, 12 Aug 2005
+
+* esd PCI405 board updated
+ Patch by Matthias Fuchs, 28 Jul 2005
+
+* esd WUH405 and DU405 board updated
+ Patch by Matthias Fuchs, 27 Jul 2005
+
+* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I)
+ Patch by Matthias Fuchs, 4 May 2005
+
+* Update AMCC Yosemite to get a consistent setup for all AMCC eval
+ boards (baudrate, environment...). Flash driver fixed.
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Add NAND FLASH support for AMCC Bamboo 440EP eval board
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Add configuration for IFM AEV FIFO board.
+ Minor coding style cleanup.
+
+* Add configuration for IFM SPI eval board
+
+* Fix CompactFlash problem on HMI1001 board
+
+* Make new "mtdparts" code build with older compilers
+ Patch by Andrea Scian, 09 Aug 2005
+
+* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to
+ CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design
+ with the 405 defines and the linux kernel defines.
+ Patch by Stefan Roese, 08 Aug 2005
+
+* Fix compiler warnings with older GCC versions
+
+* Add common (with Linux) MTD partition scheme and "mtdparts" command
+
+ Old, obsolete and duplicated code was cleaned up and replace by the
+ new partitioning method. There are two possible approaches now:
+
+ The first one is to define a single, static partition:
+
+ #undef CONFIG_JFFS2_CMDLINE
+ #define CONFIG_JFFS2_DEV "nor0"
+ #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */
+ #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */
+ #define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+ The second method uses the mtdparts command line option and dynamic
+ partitioning:
+
+ /* mtdparts command line support */
+ #define CONFIG_JFFS2_CMDLINE
+ #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
+ #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+
+ Command line of course produces bigger images, and may be inappropriate
+ for some targets, so by default it's off.
+
+* Fix build problems for PM856 Board
+
+* Fix sign extension bug in 'fpga loadb' command;
+ make 'fpga loadb' always print the file header info
+ Patch by Andrew Dyer, 11 Jan 2005
+
+* Fix errors that occur when accessing SystemACE CF
+ Patch by Jeff Angielski, 09 Jan 2005
+
+* Document switching between U-Boot and PlanetCore on RPXlite
+ by Sam Song, 24 Dec 2004
+
+* Fix PowerQUICC II mask detection.
+ Patch by Eugene Surovegin, 20 Dec 2004
+
+* Add support for Altera NIOS DK1C20 board
+ Patch by Shlomo Kut, 13 Dec 2004
+
+* Add support for ep8248 board
+ Patch by Yuli Barcohen, 12 Dec 2004
+
+ Minor code cleanup.
+
+* Fix baudrate setting for KGDB on MPC8260
+ Patch by HoJin, 11 Dec 2004
+
+* Fix 'mii help' text formatting
+ Patch by Cory Tusar, 10 Dec 2004
+
+* Fix return code of NFS command
+ Patch by Hiroshi Ito, 11 Dec 2004
+
+* Fix typo
+
+* Fix compiler warnings in cpu/ppc4xx/usbdev.c
+ Patch by Steven Blakeslee, 04 Aug 2005
+
+* Add support for AMCC Bamboo PPC440EP eval board
+ Patch by Stefan Roese, 04 Aug 2005
+
+* Patch by Jon Loeliger
+ Fix style issues primarily in 85xx and 83xx boards.
+ - C++ comments
+ - Trailing white space
+ - Indentation not by TAB
+ - Excessive amount of empty lines
+ - Trailing empty lines
+
+* Patch by Ron Alder, 11 Jul 2005
+ Add Xianghua Xiao and Lunsheng Wang's support for the
+ GDA MPC8540 EVAL board.
+
+* Patch by Eran Liberty
+ Add support for the Freescale MPC8349ADS board.
+
+* Patch by Jon Loeliger, 25 Jul 2005
+ Move the TSEC driver out of cpu/mpc85xx as it will be shared
+ by the upcoming mpc83xx family as well.
+
+* Patch by Jon Loeliger, 05 May 2005
+ Implemented support for MPC8548CDS board.
+ Added DDR II support based on SPD values for MPC85xx boards.
+ This roll-up patch also includes bugfies for the previously
+ published patches:
+ DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
+
+* Patch by Jon Loeliger, 10 Feb 2005
+ Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
+
+* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
+ For MPC85xxCDS:
+ Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
+ for faster flash parts.
+ Add documentation for BR/OR for FLASH.
+
+* Patch by Jon Loeliger 08 Feb 2005
+ Determine L2 Cache size dynamically on 85XX boards.
+
+* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
+ - Convert the CPM2 based functionality to use new CONFIG_CPM2
+ option rather than a myriad of CONFIG_MPC8560-like variants.
+ Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
+ Eliminates the CONFIG_MPC8560 option entirely. Distributes the
+ new CONFIG_CPM2 option to each 8260 board.
+
+* Add support for MicroSys PM856 board
+ Patch by Josef Wagner, 03 Aug 2005
+
+* Minor fixes to PM854 board
+ Patch by Josef Wagner, 03 Aug 2005
+
+* Adjust configuration of XENIAX board
+ (chip select and GPIO required for USB operation)
+
+* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
+ routed to the Watchdog handler
+ Patch by Eugene Surovegin, 18 Jun 2005
+
+* (re)enabled scsi commands do_scsi() and do_scsiboot()
+ Patch by Denis Peter, 06 Dec 2004
+
+* Fix endianess problem in TFTP / NFS default filenames
+ Patch by Hiroshi Ito, 06 Dec 2004
+
+* Ignore broadcast status bit in received frames in 8260 FCC ethernet
+ loopback test code
+ Patch by Murray Jensen, 18 Jul 2005
+
+* Fix typo in mkconfig script (used == instead of =)
+ Patch by Murray Jensen, 18 Jul 2005
+
+* Cleanup build problems on 64 bit build hosts
+
+* Update MAINTAINERS file
+
+* Patch by Stefan Roese, 01 Aug 2005:
+ - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
+ (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
+ for details.
+ - Sycamore (PPC405GPr) eval board added (Walnut port is extended
+ to run on both 405GP and 405GPr eval boards).
+
+* Patch by Steven Blakeslee, 27 Jul 2005:
+ - Add support for AMCC PPC440EP/GR.
+ - Add support for AMCC Yosemite PPC440EP eval board.
+ - Add support for AMCC Yellowstone PPC440GR eval board.
+
+* Minor fixes for PPChameleon Board:
+ - fix alignment of NAND size
+ - make code do what the comment says
+
+* Implement h/w sector protection status synchronization at boot.
+ The code is provided for, and was tested on, the Yukon/Alaska
+ and PM520 boards only.
+
+ A bug in flash_real_protect() for the Yukon board was fixed by
+ adding a function that tells if two banks are on one flash chip.
+
+* Fix sysmon POST problem: check I2C error codes
+ This fixes a problem of displaying bogus voltages when the voltages
+ are so low that the I2C devices start failing while the rest of the
+ system keeps running.
+
+* Patch by Cedric Vincent, 6 Jul 2005:
+ Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c"
+
+* Patch by Jon Loeliger, 20 Jul 2005:
+ Add missing PCI IO port definitions.
+
+* Add CompactFlash support for HMI1001 board.
+
+* Adjust printed board ID for LWMON board.
+
+* Fix low-level OHCI transfers for ARM920t and MPC5xxx
+
+* Add new argument format for flash commands to allow for usage like
+ "erase $(addr) +$(filesize)", i. e. a size argument can be used and
+ U-Boot will automaticially find the end of the corresponding sector.
+
+* Patch by Stefan Roese, 5 Jul 2005:
+ Update uc100 board PHY setup
+
+* Patch by Stefan Roese, 1 Jul 2005:
+ Fix PHY address for CATcenter board (now correct!)
+
+* Patch by Stefan Roese, 30 Jun 2005:
+ Fix PHY addresses for PPChameleon and CATcenter boards
+ Change MAINTAINER for most esd boards
+
+* Patch by Detlev Zundel, 30 Jun 2005:
+ Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
+
+* Fix baudrate calculation problem on MPC5200 systems
+
+* Add EEPROM and RTC support for HMI1001 board
+
+* Patch by Detlev Zundel, 20 Jun 2005:
+ Fix initialization of low active GPIO pins on inka4x0 board
+
* Enable redundant environment, disable HW flash protection of
HMI1001 board
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA & NETPHONE board support, ARTOS support.
+D: Support for Silicon Turnkey eXpress XTc
N: Pierre Aubert
E: <p.aubert@staubli.com>
W: www.denx.de
N: Murray Jensen
-E: Murray.Jensen@cmst.csiro.au
+E: Murray.Jensen@csiro.au
D: Initial 8260 support; GDB support
D: Port to Cogent+Hymod boards; Hymod Board Database
-W: http://www.msa.cmst.csiro.au/ourstaff/MurrayJensen/mjj.html
N: Yoo. Jonghoon
E: yooth@ipone.co.kr
D: Support for DOS partitions
N: Dan Malek
-E: dan@netx4.com
+E: dan@embeddedalley.com
D: FADSROM, the grandfather of all of this
+D: Support for Silicon Turnkey eXpress XTc
N: Andrea "llandre" Marson
E: andrea.marson@dave-tech.it
Yuli Barcohen <yuli@arabellasw.com>
Adder MPC87x/MPC852T
+ ep8248 MPC8248
ISPAN MPC8260
MPC8260ADS MPC826x/MPC827x/MPC8280
Rattler MPC8248
sacsng MPC8260
-Rick Bronson <rick@efn.org>
-
- AT91RM9200DK at91rm9200
-
Oliver Brown <obrown@adventnetworks.com>
gw8260 MPC8260
AmigaOneG3SE MPC7xx
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+ ADCIOP IOP480 (PPC401)
+ APC405 PPC405GP
+ AR405 PPC405GP
+ ASH405 PPC405EP
+ CANBT PPC405CR
+ CPCI405 PPC405GP
+ CPCI4052 PPC405GP
+ CPCI405AB PPC405GP
+ CPCI405DT PPC405GP
+ CPCI440 PPC440GP
+ CPCIISER4 PPC405GP
+ DASA_SIM IOP480 (PPC401)
+ DP405 PPC405EP
+ DU405 PPC405GP
+ G2000 PPC405EP
+ HH405 PPC405EP
+ HUB405 PPC405EP
+ OCRTC PPC405GP
+ ORSG PPC405GP
+ PCI405 PPC405GP
+ PLU405 PPC405EP
+ PMC405 PPC405GP
+ VOH405 PPC405EP
+ VOM405 PPC405EP
+ WUH405 PPC405EP
+
Frank Gottschling <fgottschling@eltec.de>
MHPC MPC8xx
MVS1 MPC823
-Bill Hargen <Bill_Hargen@Jabil.com>
-
- BUBINGA405EP PPC405EP
-
Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
KUP4X MPC859
-Murray Jensen <Murray.Jensen@cmst.csiro.au>
+Murray Jensen <Murray.Jensen@csiro.au>
cogent_mpc8xx MPC8xx
debris MPC8245
-Nye Liu <nyet@zumanetworks.com>
-
- ZUMA MPC7xx_74xx
-
Thomas Lange <thomas@corelatus.se>
GTH MPC860
ELPT860 MPC860T
+Nye Liu <nyet@zumanetworks.com>
+
+ ZUMA MPC7xx_74xx
+
+Jon Loeliger <jdl@freescale.com>
+
+ MPC8540ADS MPC8540
+ MPC8560ADS MPC8560
+ MPC8541CDS MPC8541
+ MPC8555CDS MPC8555
+
+Dan Malek <dan@embeddededge.com>
+
+ STxGP3 MPC85xx
+ STxXTc MPC8xx
+
Eran Man <eran@nbase.co.il>
EVB64260_750CX MPC750CX
TOP860 MPC860T
TOP5200 MPC5200
-Scott McNutt <smcnutt@artesyncp.com>
-
- EBONY PPC440GP
-
Tolunay Orkun <torkun@nextio.com>
+
csb272 PPC405GP
csb472 PPC405GP
PIP405 PPC4xx
Daniel Poirot <dan.poirot@windriver.com>
+
sbc8240 MPC8240
sbc405 PPC405GP
-Stefan Roese <stefan.roese@esd-electronics.com>
+Stefan Roese <sr@denx.de>
- ADCIOP IOP480 (PPC401)
- APC405 PPC405GP
- AR405 PPC405GP
- ASH405 PPC405EP
- CANBT PPC405CR
- CPCI405 PPC405GP
- CPCI4052 PPC405GP
- CPCI405AB PPC405GP
- CPCI405DT PPC405GP
- CPCI440 PPC440GP
- CPCIISER4 PPC405GP
- DASA_SIM IOP480 (PPC401)
- DP405 PPC405EP
- DU405 PPC405GP
- G2000 PPC405EP
- HH405 PPC405EP
- HUB405 PPC405EP
- OCRTC PPC405GP
- ORSG PPC405GP
- PCI405 PPC405GP
- PLU405 PPC405EP
- PMC405 PPC405GP
- VOH405 PPC405EP
- VOM405 PPC405EP
- WUH405 PPC405EP
+ bamboo PPC440EP
+ bunbinga PPC405EP
+ ebony PPC440GP
+ ocotea PPC440GX
+ sycamore PPC405GPr
+ walnut PPC405GP
+ yellowstone PPC440GR
+ yosemite PPC440EP
+
+Yusdi Santoso <yusdi_santoso@adaptec.com>
+
+ HIDDEN_DRAGON MPC8241/MPC8245
Travis Sawyer (travis.sawyer@sandburst.com>
+ KAREF PPC440GX
+ METROBOX PPC440GX
XPEDITE1K PPC440GX
- OCOTEA PPC440GX
Peter De Schrijver <p2@mind.be>
svm_sc8xx MPC8xx
-Jon Loeliger <jdl@freescale.com>
-
- MPC8540ADS MPC8540
- MPC8560ADS MPC8560
-
-Dan Malek <dan@embeddededge.com>
-
- STxGP3 MPC85xx
-
-Yusdi Santoso <yusdi_santoso@adaptec.com>
-
- HIDDEN_DRAGON MPC8241/MPC8245
-
-------------------------------------------------------------------------
Unknown / orphaned boards:
CRAYL1 PPC4xx
ERIC PPC4xx
- WALNUT405 PPC4xx
MOUSSE MPC824x
# Board CPU #
#########################################################################
+Rishi Bhattacharya <rishi@ti.com>
+
+ omap5912osk ARM926EJS
+
+Rick Bronson <rick@efn.org>
+
+ AT91RM9200DK at91rm9200
+
George G. Davis <gdavis@mvista.com>
assabet SA1100
impa7 ARM720T (EP7211)
ep7312 ARM720T (EP7312)
+Kshitij Gupta <kshitij@ti.com>
+
+ omap1510inn ARM925T
+ omap1610inn ARM926EJS
+
Kyle Harris <kharris@nexus-tech.net>
lubbock xscale
smdk2400 ARM920T
trab ARM920T
-Prakash Kumar <prakash@embedx.com>
-
- cerf250 xscale
-
-Kshitij Gupta <kshitij@ti.com>
-
- omap1510inn ARM925T
- omap1610inn ARM926EJS
-
-Dave Peverley <dpeverley@mpc-data.co.uk>
- omap730p2 ARM926EJS
-
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
-Rishi Bhattacharya <rishi@ti.com>
-
- omap5912osk ARM926EJS
-
-Richard Woodruff <r-woodruff2@ti.com>
+Prakash Kumar <prakash@embedx.com>
- omap2420h4 ARM1136EJS
+ cerf250 xscale
David Müller <d.mueller@elsoft.ch>
shannon SA1100
+Dave Peverley <dpeverley@mpc-data.co.uk>
+
+ omap730p2 ARM926EJS
+
Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale
Andrea Scian <andrea.scian@dave-tech.it>
- B2 ARM7TDMI (S3C44B0X)
+ B2 ARM7TDMI (S3C44B0X)
Greg Ungerer <greg.ungerer@opengear.com>
cm4116 ks8695p
cm4148 ks8695p
+Richard Woodruff <r-woodruff2@ti.com>
+
+ omap2420h4 ARM1136EJS
+
Alex Züpke <azu@sysgo.de>
lart SA1100
# Board CPU #
#########################################################################
-Stefan Roese <stefan.roese@esd-electronics.com>
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
TASREG MCF5249
#########################################################################
LIST_4xx=" \
- ADCIOP AR405 ASH405 BUBINGA405EP \
+ ADCIOP AR405 ASH405 bubinga \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
- EBONY ERIC EXBITGEN HUB405 \
- JSE MIP405 MIP405T ML2 \
- ml300 OCOTEA OCRTC ORSG \
- PCI405 PIP405 PLU405 PMC405 \
- PPChameleonEVB VOH405 W7OLMC W7OLMG \
- WALNUT405 WUH405 XPEDITE1K \
+ ebony ERIC EXBITGEN HUB405 \
+ JSE KAREF METROBOX MIP405 \
+ MIP405T ML2 ml300 ocotea \
+ OCRTC ORSG PCI405 PIP405 \
+ PLU405 PMC405 PPChameleonEVB VOH405 \
+ W7OLMC W7OLMG walnut WUH405 \
+ XPEDITE1K yellowstone yosemite \
"
#########################################################################
debris eXalion HIDDEN_DRAGON MOUSSE \
MUSENKI MVBLUE OXC PN62 \
Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
- sbc8240 \
+ sbc8240 \
"
#########################################################################
LIST_8260=" \
atc cogent_mpc8260 CPU86 CPU87 \
- ep8260 gw8260 hymod IPHASE4539 \
- ISPAN MPC8260ADS MPC8266ADS MPC8272ADS \
- PM826 PM828 ppmc8260 Rattler8248 \
- RPXsuper rsdproto sacsng sbc8260 \
- SCM TQM8260_AC TQM8260_AD TQM8260_AE \
- ZPC1900 \
+ ep8248 ep8260 gw8260 hymod \
+ IPHASE4539 ISPAN MPC8260ADS MPC8266ADS \
+ MPC8272ADS PM826 PM828 ppmc8260 \
+ Rattler8248 RPXsuper rsdproto sacsng \
+ sbc8260 SCM TQM8260_AC TQM8260_AD \
+ TQM8260_AE ZPC1900 \
"
#########################################################################
+## MPC83xx Systems (includes 8349, etc.)
+#########################################################################
+
+LIST_83xx=" \
+ MPC8349ADS \
+"
+
+
+#########################################################################
## MPC85xx Systems (includes 8540, 8560 etc.)
#########################################################################
LIST_85xx=" \
- MPC8540ADS MPC8541CDS MPC8555CDS MPC8560ADS \
- PM854 sbc8540 sbc8560 stxgp3 \
- TQM8540 \
+ MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
+ MPC8555CDS MPC8560ADS PM854 PM856 \
+ sbc8540 sbc8560 stxgp3 TQM8540 \
"
#########################################################################
BAB7xx CPCI750 ELPPC \
"
-LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
- ${LIST_8xx} \
- ${LIST_824x} ${LIST_8260} \
- ${LIST_85xx} \
- ${LIST_4xx} \
+LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
+ ${LIST_8xx} \
+ ${LIST_8220} ${LIST_824x} ${LIST_8260} \
+ ${LIST_83xx} \
+ ${LIST_85xx} \
+ ${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
#########################################################################
#########################################################################
LIST_ARM9=" \
- at91rm9200dk cmc_pu2 integratorcp integratorap \
+ at91rm9200dk cmc_pu2 integratorcp integratorap \
lpd7a400 mx1ads mx1fs2 omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
"
#########################################################################
-## MIPS Systems
+## MIPS Systems (default = big endian)
#########################################################################
LIST_mips4kc="incaip"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
#########################################################################
+## MIPS Systems (little endian)
+#########################################################################
+
+LIST_mips4kc_el=""
+
+LIST_mips5kc_el=""
+
+LIST_au1xx0_el="dbau1550_el"
+
+LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}"
+
+#########################################################################
## i386 Systems
#########################################################################
for arg in $@
do
case "$arg" in
- ppc|5xx|5xxx|8xx|8220|824x|8260|85xx|4xx|7xx|74xx| \
+ ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
microblaze| \
- mips| \
+ mips|mips_el| \
nios|nios2| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
-e s/powerpc/ppc/ \
-e s/macppc/ppc/)
-HOSTOS := $(shell uname -s | tr A-Z a-z | \
+HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
sed -e 's/\(cygwin\).*/cygwin/')
-export HOSTARCH
+export HOSTARCH HOSTOS
# Deal with colliding definitions from tcsh etc.
VENDOR=
CROSS_COMPILE =
else
ifeq ($(ARCH),ppc)
-CROSS_COMPILE = ppc_8xx-
+CROSS_COMPILE = powerpc-linux-
endif
ifeq ($(ARCH),arm)
CROSS_COMPILE = arm-linux-
ifeq ($(CPU),ppc4xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
+ifeq ($(CPU),mpc83xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
## MPC5xxx Systems
#########################################################################
+aev_config: unconfig
+ @./mkconfig -a aev ppc mpc5xxx tqm5200
+
hmi1001_config: unconfig
@./mkconfig hmi1001 ppc mpc5xxx hmi1001
}
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
+spieval_config: unconfig
+ echo "#define CONFIG_CS_AUTOCONF">>include/config.h
+ echo "... with automatic CS configuration"
+ @./mkconfig -a spieval ppc mpc5xxx tqm5200
+
#########################################################################
## MPC8xx Systems
#########################################################################
SPD823TS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
+stxxtc_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8xx stxxtc
+
svm_sc8xx_config: unconfig
@ >include/config.h
@./mkconfig $(@:_config=) ppc mpc8xx svm_sc8xx
ASH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
-BUBINGA405EP_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx bubinga405ep
+bamboo_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc
+
+bubinga_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc
CANBT_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx canbt esd
DU405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
-EBONY_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ebony
+ebony_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx ebony amcc
ERIC_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx eric
JSE_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx jse
+KAREF_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx karef sandburst
+
+METROBOX_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst
+
MIP405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
ml300_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
-OCOTEA_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ocotea
+ocotea_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc
OCRTC_config \
ORSG_config: unconfig
sbc405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx sbc405
+sycamore_config: unconfig
+ @echo "Configuring for sycamore board as subset of walnut..."
+ @./mkconfig -a walnut ppc ppc4xx walnut amcc
+
VOH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
W7OLMG_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx w7o
-WALNUT405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx walnut405
+walnut_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx walnut amcc
WUH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
XPEDITE1K_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
+yosemite_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc
+
+yellowstone_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
+
#########################################################################
## MPC8220 Systems
#########################################################################
-Alaska8220_config: unconfig
+
+Alaska8220_config \
+Yukon8220_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8220 alaska
sorcery_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8220 sorcery
-Yukon8220_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8220 yukon
-
#########################################################################
## MPC824x Systems
#########################################################################
fi; \
echo "export CONFIG_BOOT_ROM" >> config.mk;
+ep8248_config \
+ep8248E_config : unconfig
+ @./mkconfig ep8248 ppc mpc8260 ep8248
+
ep8260_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 ep8260
@./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd
#########################################################################
+## MPC83xx Systems
+#########################################################################
+
+MPC8349ADS_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
+
+#########################################################################
## MPC85xx Systems
#########################################################################
MPC8540ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
+MPC8540EVAL_config \
+MPC8540EVAL_33_config \
+MPC8540EVAL_66_config \
+MPC8540EVAL_33_slave_config \
+MPC8540EVAL_66_slave_config: unconfig
+ @echo "" >include/config.h ; \
+ if [ "$(findstring _33_,$@)" ] ; then \
+ echo -n "... 33 MHz PCI" ; \
+ else \
+ echo "#define CONFIG_SYSCLK_66M" >>include/config.h ; \
+ echo -n "... 66 MHz PCI" ; \
+ fi ; \
+ if [ "$(findstring _slave_,$@)" ] ; then \
+ echo "#define CONFIG_PCI_SLAVE" >>include/config.h ; \
+ echo " slave" ; \
+ else \
+ echo " host" ; \
+ fi
+ @./mkconfig -a MPC8540EVAL ppc mpc85xx mpc8540eval
+
MPC8560ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
MPC8541CDS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds
+MPC8548CDS_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc85xx mpc8548cds cds
+
MPC8555CDS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
PM854_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx pm854
+PM856_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc85xx pm856
+
sbc8540_config \
sbc8540_33_config \
sbc8540_66_config: unconfig
dbau1550_el_config : unconfig
@ >include/config.h
@echo "#define CONFIG_DBAU1550 1" >>include/config.h
- @./mkconfig -a dbau1x00 mips mips dbau1x00 "" little
+ @./mkconfig -a dbau1x00 mips mips dbau1x00
#########################################################################
## MIPS64 5Kc
rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
rm -f tools/env/fw_printenv tools/env/fw_setenv
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
- rm -f board/trab/trab_fkt
+ rm -f board/trab/trab_fkt board/voiceblue/eeprom
clobber: clean
find . -type f \( -name .depend \
CONFIG_EBONY CONFIG_MOUSSE CONFIG_SXNI855T
CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM823L
CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM8260
- CONFIG_ep8260 CONFIG_MPC8560ADS CONFIG_TQM850L
- CONFIG_ERIC CONFIG_MUSENKI CONFIG_TQM855L
- CONFIG_ESTEEM192E CONFIG_MVS1 CONFIG_TQM860L
- CONFIG_ETX094 CONFIG_NETPHONE CONFIG_TTTech
- CONFIG_EVB64260 CONFIG_NETTA CONFIG_UTX8245
- CONFIG_FADS823 CONFIG_NETVIA CONFIG_V37
- CONFIG_FADS850SAR CONFIG_NX823 CONFIG_W7OLMC
- CONFIG_FADS860T CONFIG_OCRTC CONFIG_W7OLMG
- CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT405
- CONFIG_FPS850L CONFIG_OXC CONFIG_ZPC1900
- CONFIG_FPS860L CONFIG_ZUMA
+ CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM850L
+ CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM855L
+ CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TQM860L
+ CONFIG_ETX094 CONFIG_MVS1 CONFIG_TTTech
+ CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_UTX8245
+ CONFIG_FADS823 CONFIG_NETTA CONFIG_V37
+ CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMC
+ CONFIG_FADS860T CONFIG_NX823 CONFIG_W7OLMG
+ CONFIG_FLAGADM CONFIG_OCRTC CONFIG_WALNUT
+ CONFIG_FPS850L CONFIG_ORSG CONFIG_ZPC1900
+ CONFIG_FPS860L CONFIG_OXC CONFIG_ZUMA
ARM based boards:
-----------------
DUET_ADS_config MBX_config sbc8560_66_config
EBONY_config MPC8260ADS_config SM850_config
ELPT860_config MPC8540ADS_config SPD823TS_config
- ESTEEM192E_config MPC8560ADS_config stxgp3_config
- ETX094_config NETVIA_config SXNI855T_config
- FADS823_config omap1510inn_config TQM823L_config
- FADS850SAR_config omap1610h2_config TQM850L_config
- FADS860T_config omap1610inn_config TQM855L_config
- FPS850L_config omap5912osk_config TQM860L_config
- omap2420h4_config WALNUT405_config
- Yukon8220_config
+ ESTEEM192E_config MPC8540EVAL_config stxgp3_config
+ ETX094_config MPC8560ADS_config SXNI855T_config
+ FADS823_config NETVIA_config TQM823L_config
+ FADS850SAR_config omap1510inn_config TQM850L_config
+ FADS860T_config omap1610h2_config TQM855L_config
+ FPS850L_config omap1610inn_config TQM860L_config
+ omap5912osk_config walnut_config
+ omap2420h4_config Yukon8220_config
ZPC1900_config
Note: for some board special configuration names may exist; check if
CFG_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
- Walnut405.h should work for you. I'd set it to a value larger
+ walnut.h should work for you. I'd set it to a value larger
than your SDRAM module. If you have a 64MB SDRAM module, set
it above 400_0000. Just make sure your board has no resources
that are supposed to respond to that address! That code in
#define FLASH_CYCLE2 0x02aa
#define WR_BLOCK 0x20
-
/*-----------------------------------------------------------------------
* Functions
*/
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+static unsigned char same_chip_banks (int bank1, int bank2);
/*-----------------------------------------------------------------------
*/
break;
}
size += flash_info[i].size;
+
+ /* get the h/w and s/w protection status in sync */
+ flash_sync_real_protect(&flash_info[i]);
}
/* Protect monitor and environment sectors
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
- info->protect[i] = 0;
}
}
}
}
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ for (i = 0; i < info->sector_count; ++i) {
+ info->protect[i] = intel_sector_protected(info, i);
+ }
+ break;
+ case FLASH_AM040:
+ default:
+ /* no h/w protect support */
+ break;
+ }
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+ FPWV *addr;
+ FPWV *lock_conf_addr;
+ ulong start;
+ unsigned char ret;
+
+ /*
+ * first, wait for the WSM to be finished. The rationale for
+ * waiting for the WSM to become idle for at most
+ * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+ * because of: (1) erase, (2) program or (3) lock bit
+ * configuration. So we just wait for the longest timeout of
+ * the (1)-(3), i.e. the erase timeout.
+ */
+
+ /* wait at least 35ns (W12) before issuing Read Status Register */
+ udelay(1);
+ addr = (FPWV *) info->start[sector];
+ *addr = (FPW) INTEL_STATUS;
+
+ start = get_timer (0);
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ printf("WSM busy too long, can't get prot status\n");
+ return 1;
+ }
+ }
+
+ /* issue the Read Identifier Codes command */
+ *addr = (FPW) INTEL_READID;
+
+ /* wait at least 35ns (W12) before reading */
+ udelay(1);
+
+ /* Intel example code uses offset of 4 for 8-bit flash */
+ lock_conf_addr = (FPWV *) info->start[sector] + 4;
+ ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+ /* put flash back in read mode */
+ *addr = (FPW) INTEL_RESET;
+
+ return ret;
+}
+
+
+/*
+ * Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they
+ * are and 0 otherwise.
+ */
+static unsigned char same_chip_banks (int bank1, int bank2)
+{
+ unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = {
+ {1, 1, 0, 0},
+ {1, 1, 0, 0},
+ {0, 0, 1, 1},
+ {0, 0, 1, 1}
+ };
+ return same_chip[bank1][bank2];
+}
+
+
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
int flash_real_protect (flash_info_t * info, long sector, int prot)
{
ulong start;
- int i;
+ int i, j;
+ int curr_bank;
+ int bank;
int rc = 0;
FPWV *addr = (FPWV *) (info->start[sector]);
int flag = disable_interrupts ();
* we have to restore lock bits of protected sectors.
*/
if (!prot) {
- for (i = 0; i < info->sector_count; i++) {
- if (info->protect[i]) {
- start = get_timer (0);
- addr = (FPWV *) (info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- while ((*addr & INTEL_FINISHED) !=
- INTEL_FINISHED) {
- if (get_timer (start) >
- CFG_FLASH_UNLOCK_TOUT) {
- printf ("Flash lock bit operation timed out\n");
- rc = 1;
- break;
+ /*
+ * re-locking must be done for all banks that belong on one
+ * FLASH chip, as all the sectors on the chip were unlocked
+ * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
+ * that banks never span chips, in particular chips which
+ * support h/w protection differently).
+ */
+
+ /* find the current bank number */
+ curr_bank = CFG_MAX_FLASH_BANKS + 1;
+ for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) {
+ if (&flash_info[j] == info) {
+ curr_bank = j;
+ }
+ }
+ if (curr_bank == CFG_MAX_FLASH_BANKS + 1) {
+ printf("Error: can't determine bank number!\n");
+ }
+
+ for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
+ if (!same_chip_banks(curr_bank, bank)) {
+ continue;
+ }
+ info = &flash_info[bank];
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->protect[i]) {
+ start = get_timer (0);
+ addr = (FPWV *) (info->start[i]);
+ *addr = INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = INTEL_PROTECT; /* set */
+ while ((*addr & INTEL_FINISHED) !=
+ INTEL_FINISHED) {
+ if (get_timer (start) >
+ CFG_FLASH_UNLOCK_TOUT) {
+ printf ("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
}
}
}
}
+
+ /*
+ * get the s/w sector protection status in sync with the h/w,
+ * in case something went wrong during the re-locking.
+ */
+ flash_sync_real_protect(info); /* resets flash to read mode */
}
if (flag)
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
+ * CompactFlash/IDE:
+ * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*/
#include <common.h>
+#include <nios-io.h>
#if defined(CONFIG_SEVENSEG)
#include "../common/sevenseg.h"
#endif
{
return (0);
}
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+int ide_preinit (void)
+{
+ nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT;
+ nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER;
+ nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL;
+
+ /* setup data direction registers */
+ present->direction = NIOS_PIO_IN;
+ power->direction = NIOS_PIO_OUT;
+ atasel->direction = NIOS_PIO_OUT;
+
+ /* Check for presence of card */
+ if (present->data)
+ return 1;
+ printf ("Ok\n");
+
+ /* Finish setup */
+ power->data = 1; /* Turn on power FET */
+ atasel->data = 0; /* Put in ATA mode */
+
+ return 0;
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+OBJS += flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <ppc440.h>
+#include "bamboo.h"
+
+void ext_bus_cntlr_init(void);
+void configure_ppc440ep_pins(void);
+int is_nand_selected(void);
+
+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
+#if 0
+{ /* GPIO Alternate1 Alternate2 Alternate3 */
+ {
+ /* GPIO Core 0 */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
+ { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
+ },
+ {
+ /* GPIO Core 1 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
+ }
+};
+#endif
+
+/*----------------------------------------------------------------------------+
+ | EBC Devices Characteristics
+ | Peripheral Bank Access Parameters - EBC0_BnAP
+ | Peripheral Bank Configuration Register - EBC0_BnCR
+ +----------------------------------------------------------------------------*/
+/* Small Flash */
+#define EBC0_BNAP_SMALL_FLASH \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(6) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(3) | \
+ EBC0_BNAP_TH_ENCODE(1) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_WRITEONLY | \
+ EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_SMALL_FLASH_CS0 \
+ EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
+
+#define EBC0_BNCR_SMALL_FLASH_CS4 \
+ EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
+
+/* Large Flash or SRAM */
+#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(8) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(1) | \
+ EBC0_BNAP_TH_ENCODE(2) | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_RW | \
+ EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
+ EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
+ EBC0_BNCR_BS_8MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_16BIT
+
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
+ EBC0_BNCR_BAS_ENCODE(0x87800000) | \
+ EBC0_BNCR_BS_8MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_16BIT
+
+/* NVRAM - FPGA */
+#define EBC0_BNAP_NVRAM_FPGA \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(9) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(0) | \
+ EBC0_BNAP_TH_ENCODE(2) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_WRITEONLY | \
+ EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_NVRAM_FPGA_CS5 \
+ EBC0_BNCR_BAS_ENCODE(0x80000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
+
+/* Nand Flash */
+#define EBC0_BNAP_NAND_FLASH \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(3) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(0) | \
+ EBC0_BNAP_WBN_ENCODE(0) | \
+ EBC0_BNAP_WBF_ENCODE(0) | \
+ EBC0_BNAP_TH_ENCODE(1) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_NOT_DELAYED | \
+ EBC0_BNAP_BEM_RW | \
+ EBC0_BNAP_PEN_DISABLED
+
+
+#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
+
+/* NAND0 */
+#define EBC0_BNCR_NAND_FLASH_CS1 \
+ EBC0_BNCR_BAS_ENCODE(0x90000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+/* NAND1 - Bank2 */
+#define EBC0_BNCR_NAND_FLASH_CS2 \
+ EBC0_BNCR_BAS_ENCODE(0x94000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+
+/* NAND1 - Bank3 */
+#define EBC0_BNCR_NAND_FLASH_CS3 \
+ EBC0_BNCR_BAS_ENCODE(0x94000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+
+int board_early_init_f(void)
+{
+ ext_bus_cntlr_init();
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ out32(GPIO0_OSRL, 0x00000400);
+ out32(GPIO0_OSRH, 0x00000000);
+ out32(GPIO0_TSRL, 0x00000400);
+ out32(GPIO0_TSRH, 0x00000000);
+ out32(GPIO0_ISR1L, 0x00000000);
+ out32(GPIO0_ISR1H, 0x00000000);
+ out32(GPIO0_ISR2L, 0x00000000);
+ out32(GPIO0_ISR2H, 0x00000000);
+ out32(GPIO0_ISR3L, 0x00000000);
+ out32(GPIO0_ISR3H, 0x00000000);
+
+ out32(GPIO1_OSRL, 0x0C380000);
+ out32(GPIO1_OSRH, 0x00000000);
+ out32(GPIO1_TSRL, 0x0C380000);
+ out32(GPIO1_TSRH, 0x00000000);
+ out32(GPIO1_ISR1L, 0x0FC30000);
+ out32(GPIO1_ISR1H, 0x00000000);
+ out32(GPIO1_ISR2L, 0x0C010000);
+ out32(GPIO1_ISR2H, 0x00000000);
+ out32(GPIO1_ISR3L, 0x01400000);
+ out32(GPIO1_ISR3H, 0x00000000);
+
+ configure_ppc440ep_pins();
+
+ return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+/*----------------------------------------------------------------------------+
+ | nand_reset.
+ | Reset Nand flash
+ | This routine will abort previous cmd
+ +----------------------------------------------------------------------------*/
+int nand_reset(ulong addr)
+{
+ int wait=0, stat=0;
+
+ out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
+ out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
+
+ while ((stat != 0xc0) && (wait != 0xffff)) {
+ stat = in8(addr + NAND_DATA_REG);
+ wait++;
+ }
+
+ if (stat == 0xc0) {
+ return 0;
+ } else {
+ printf("NAND Reset timeout.\n");
+ return -1;
+ }
+}
+
+void board_nand_set_device(int cs, ulong addr)
+{
+ /* Set NandFlash Core Configuration Register */
+ out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
+
+ switch (cs) {
+ case 1:
+ /* -------
+ * NAND0
+ * -------
+ * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
+ * Set NDF1CR - Enable External CS1 in NAND FLASH controller
+ */
+ out32(addr + NAND_CR1_REG, 0x80002222);
+ break;
+
+ case 2:
+ /* -------
+ * NAND1
+ * -------
+ * K9K2G0B : 5 addr cyc, 2 col + 3 Row
+ * Set NDF2CR : Enable External CS2 in NAND FLASH controller
+ */
+ out32(addr + NAND_CR2_REG, 0xC0007777);
+ break;
+ }
+
+ /* Perform Reset Command */
+ if (nand_reset(addr) != 0)
+ return;
+}
+
+void nand_init(void)
+{
+ board_nand_set_device(1, CFG_NAND_ADDR);
+
+ nand_probe(CFG_NAND_ADDR);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+ print_size(nand_dev_desc[0].totlen, "\n");
+ }
+
+#if 0 /* NAND1 not supported yet */
+ board_nand_set_device(2, CFG_NAND2_ADDR);
+
+ nand_probe(CFG_NAND2_ADDR);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+ print_size(nand_dev_desc[0].totlen, "\n");
+ }
+#endif
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+
+int checkboard(void)
+{
+ sys_info_t sysinfo;
+ unsigned char *s = getenv("serial#");
+
+ get_sys_info(&sysinfo);
+
+ printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+ return (0);
+}
+
+/*************************************************************************
+ *
+ * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ * 13 row add bits, 10 column add bits (but 12 row used only).
+ * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ * 12 row add bits, 10 column add bits.
+ * Prepare a subset (only the used ones) of SPD data
+ *
+ * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ * the corresponding bank is divided by 2 due to number of Row addresses
+ * 12 in the ECC module
+ *
+ * Assumes: 64 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+void fixed_sdram_init(void)
+{
+ /*
+ * clear this first, if the DDR is enabled by a debugger
+ * then you can not make changes.
+ */
+ mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, 0x00082001);
+ mtsdram(mem_b1cr, 0x00000000);
+ mtsdram(mem_b2cr, 0x00000000);
+ mtsdram(mem_b3cr, 0x00000000);
+}
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+
+ /*
+ * First init bank0 (onboard sdram) and then configure the DIMM-slots
+ */
+ fixed_sdram_init();
+ dram_size = spd_sdram (0);
+
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ for (k = 0; k < CFG_KBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ return 0;
+}
+#endif
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long strap;
+ unsigned long addr;
+
+ /*--------------------------------------------------------------------------+
+ * Bamboo is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
+ printf("PCI: SDR0_STRP1[PAE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return 0;
+ }
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440 EP PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Bamboo is always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*----------------------------------------------------------------------------+
+ | is_powerpc440ep_pass1.
+ +----------------------------------------------------------------------------*/
+int is_powerpc440ep_pass1(void)
+{
+ unsigned long pvr;
+
+ pvr = get_pvr();
+
+ if (pvr == PVR_POWERPC_440EP_PASS1)
+ return TRUE;
+ else if (pvr == PVR_POWERPC_440EP_PASS2)
+ return FALSE;
+ else {
+ printf("brdutil error 3\n");
+ for (;;)
+ ;
+ }
+
+ return(FALSE);
+}
+
+/*----------------------------------------------------------------------------+
+ | is_nand_selected.
+ +----------------------------------------------------------------------------*/
+int is_nand_selected(void)
+{
+#ifdef CONFIG_BAMBOO_NAND
+ return TRUE;
+#else
+ return FALSE;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+ | config_on_ebc_cs4_is_small_flash => from EPLD
+ +----------------------------------------------------------------------------*/
+unsigned char config_on_ebc_cs4_is_small_flash(void)
+{
+ /* Not implemented yet => returns constant value */
+ return TRUE;
+}
+
+/*----------------------------------------------------------------------------+
+ | Ext_bus_cntlr_init.
+ | Initialize the external bus controller
+ +----------------------------------------------------------------------------*/
+void ext_bus_cntlr_init(void)
+{
+ unsigned long sdr0_pstrp0, sdr0_sdstp1;
+ unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+ unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
+ unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
+ unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
+ unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
+ unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
+
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 1 : Initialize EBC Bank 5
+ | ==============================
+ | Bank5 is always associated to the NVRAM/EPLD.
+ | It has to be initialized prior to other banks settings computation since
+ | some board registers values may be needed
+ |
+ +-------------------------------------------------------------------------*/
+ /* NVRAM - FPGA */
+ mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
+ mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 2 : Determine which boot device was selected
+ | =========================================
+ |
+ | Read Pin Strap Register in PPC440EP
+ | In case of boot from IIC, read Serial Device Strap Register1
+ |
+ | Result can either be :
+ | - Boot from EBC 8bits => SMALL FLASH
+ | - Boot from EBC 16bits => Large Flash or SRAM
+ | - Boot from NAND Flash
+ | - Boot from PCI
+ |
+ +-------------------------------------------------------------------------*/
+ /* Read Pin Strap Register in PPC440EP */
+ mfsdr(sdr_pstrp0, sdr0_pstrp0);
+ bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+ /*-------------------------------------------------------------------------+
+ | PPC440EP Pass1
+ +-------------------------------------------------------------------------*/
+ if (is_powerpc440ep_pass1() == TRUE) {
+ switch(bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
+ /* Boot from Nand Flash */
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+ /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+ /* Read Serial Device Strap Register1 in PPC440EP */
+ mfsdr(sdr_sdstp1, sdr0_sdstp1);
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+ }
+ break;
+ }
+ }
+
+ /*-------------------------------------------------------------------------+
+ | PPC440EP Pass2
+ +-------------------------------------------------------------------------*/
+ else {
+ switch(bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
+ /* Boot from Nand Flash */
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+ /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
+ /* Boot from Large Flash or SRAM */
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+ /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
+ /* Boot from Large Flash or SRAM */
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
+ /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+ /* Default Strap Settings 5-7 */
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+ /* Read Serial Device Strap Register1 in PPC440EP */
+ mfsdr(sdr_sdstp1, sdr0_sdstp1);
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+ }
+ break;
+ }
+ }
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 3 : Compute EBC settings depending on selected boot device
+ | ====== ======================================================
+ |
+ | Resulting EBC init will be among following configurations :
+ |
+ | - Boot from EBC 8bits => boot from SMALL FLASH selected
+ | EBC-CS0 = Small Flash
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Soft Config
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
+ | EBC-CS0 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Software Configuration
+ | EBC-CS4 = Small Flash
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from NAND Flash
+ | EBC-CS0 = NAND Flash0
+ | EBC-CS1,2,3 = NAND Flash1
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from PCI
+ | EBC-CS0 = ...
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Software Configuration
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM or
+ | Small Flash depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ +-------------------------------------------------------------------------*/
+
+ switch(computed_boot_device) {
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_SMALL_FLASH:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
+ if ((is_nand_selected()) == TRUE) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
+ if ((is_nand_selected()) == TRUE) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_NAND_FLASH0:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = 0;
+ ebc0_cs0_bncr_value = 0;
+
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+
+ /* Large Flash or SRAM */
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_PCI:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = 0;
+ ebc0_cs0_bncr_value = 0;
+
+ if ((is_nand_selected()) == TRUE) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+
+ if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
+ /* Small Flash */
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+ } else {
+ /* Large Flash or SRAM */
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+ }
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_DEVICE_UNKNOWN:
+ /*------------------------------------------------------------------------- */
+ /* Error */
+ break;
+
+ }
+
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------------*/
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
+ EBC0_CFG_PTD_ENABLED |
+ EBC0_CFG_RTC_2048PERCLK |
+ EBC0_CFG_EMPL_LOW |
+ EBC0_CFG_EMPH_LOW |
+ EBC0_CFG_CSTC_DRIVEN |
+ EBC0_CFG_BPF_ONEDW |
+ EBC0_CFG_EMS_8BIT |
+ EBC0_CFG_PME_DISABLED |
+ EBC0_CFG_PMT_ENCODE(0) );
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC Bank 0-4
+ +-------------------------------------------------------------------------*/
+ /* EBC Bank0 */
+ mtebc(pb0ap, ebc0_cs0_bnap_value);
+ mtebc(pb0cr, ebc0_cs0_bncr_value);
+ /* EBC Bank1 */
+ mtebc(pb1ap, ebc0_cs1_bnap_value);
+ mtebc(pb1cr, ebc0_cs1_bncr_value);
+ /* EBC Bank2 */
+ mtebc(pb2ap, ebc0_cs2_bnap_value);
+ mtebc(pb2cr, ebc0_cs2_bncr_value);
+ /* EBC Bank3 */
+ mtebc(pb3ap, ebc0_cs3_bnap_value);
+ mtebc(pb3cr, ebc0_cs3_bncr_value);
+ /* EBC Bank4 */
+ mtebc(pb4ap, ebc0_cs4_bnap_value);
+ mtebc(pb4cr, ebc0_cs4_bncr_value);
+
+ return;
+}
+
+
+/*----------------------------------------------------------------------------+
+ | get_uart_configuration.
+ +----------------------------------------------------------------------------*/
+uart_config_nb_t get_uart_configuration(void)
+{
+ return (L4);
+}
+
+/*----------------------------------------------------------------------------+
+ | set_phy_configuration_through_fpga => to EPLD
+ +----------------------------------------------------------------------------*/
+void set_phy_configuration_through_fpga(zmii_config_t config)
+{
+
+ unsigned long fpga_selection_reg;
+
+ fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
+
+ switch(config)
+ {
+ case ZMII_CONFIGURATION_IS_MII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
+ break;
+ case ZMII_CONFIGURATION_IS_RMII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
+ break;
+ case ZMII_CONFIGURATION_IS_SMII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
+ break;
+ case ZMII_CONFIGURATION_UNKNOWN:
+ default:
+ break;
+ }
+ out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
+
+}
+
+/*----------------------------------------------------------------------------+
+ | scp_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void scp_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | iic1_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void iic1_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_a_b_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_a_b_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_a_b_unselect_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_a_b_unselect_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_c_d_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_c_d_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_c_d_unselect_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_c_d_unselect_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_device_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_device_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_device_reset_through_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_device_reset_through_fpga(void)
+{
+ /* Perform soft Reset pulse */
+ unsigned long fpga_reset_reg;
+ int i;
+
+ fpga_reset_reg = in8(FPGA_RESET_REG);
+ out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
+ for (i=0; i<500; i++)
+ udelay(1000);
+ out8(FPGA_RESET_REG,fpga_reset_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_host_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_host_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | ndfc_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void ndfc_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
+ fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
+ fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | uart_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void uart_selection_in_fpga(uart_config_nb_t uart_config)
+{
+ /* FPGA register */
+ unsigned char fpga_selection_3_reg;
+
+ /* Read FPGA Reagister */
+ fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
+
+ switch (uart_config)
+ {
+ case L1:
+ /* ----------------------------------------------------------------------- */
+ /* L1 configuration: UART0 = 8 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ case L2:
+ /* ----------------------------------------------------------------------- */
+ /* L2 configuration: UART0 = 4 pins */
+ /* UART1 = 4 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ case L3:
+ /* ----------------------------------------------------------------------- */
+ /* L3 configuration: UART0 = 4 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+ break;
+
+ case L4:
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ default:
+ /* Unsupported UART configuration number */
+ for (;;)
+ ;
+ break;
+
+ }
+}
+
+
+/*----------------------------------------------------------------------------+
+ | init_default_gpio
+ +----------------------------------------------------------------------------*/
+void init_default_gpio(void)
+{
+ int i;
+
+ /* Init GPIO0 */
+ for(i=0; i<GPIO_MAX; i++)
+ {
+ gpio_tab[GPIO0][i].add = GPIO0_BASE;
+ gpio_tab[GPIO0][i].in_out = GPIO_DIS;
+ gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
+ }
+
+ /* Init GPIO1 */
+ for(i=0; i<GPIO_MAX; i++)
+ {
+ gpio_tab[GPIO1][i].add = GPIO1_BASE;
+ gpio_tab[GPIO1][i].in_out = GPIO_DIS;
+ gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
+ }
+
+ /* EBC_CS_N(5) - GPIO0_10 */
+ gpio_tab[GPIO0][10].in_out = GPIO_OUT;
+ gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
+
+ /* EBC_CS_N(4) - GPIO0_9 */
+ gpio_tab[GPIO0][9].in_out = GPIO_OUT;
+ gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uart_ios
+ +------------------------------------------------------------------------------
+ |
+ | Set UART Configuration in PowerPC440EP
+ |
+ | +---------------------------------------------------------------------+
+ | | Configuartion | Connector | Nb of pins | Pins | Associated |
+ | | Number | Port Name | available | naming | CORE |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L1 | Port_A | 8 | UART | UART core 0 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L2 | Port_A | 4 | UART1 | UART core 0 |
+ | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L3 | Port_A | 4 | UART1 | UART core 0 |
+ | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
+ | | | Port_C | 2 | UART3 | UART core 2 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | | Port_A | 2 | UART1 | UART core 0 |
+ | | L4 | Port_B | 2 | UART2 | UART core 1 |
+ | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
+ | | | Port_D | 2 | UART4 | UART core 3 |
+ | +-----------------+---------------+------------+--------+-------------+
+ |
+ | Involved GPIOs
+ |
+ | +------------------------------------------------------------------------------+
+ | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
+ | +---------+------------------+-----+-----------------+-----+-------------+-----+
+ | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
+ | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
+ | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
+ | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
+ | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
+ | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
+ | +------------------------------------------------------------------------------+
+ |
+ |
+ +----------------------------------------------------------------------------*/
+
+void update_uart_ios(uart_config_nb_t uart_config)
+{
+ switch (uart_config)
+ {
+ case L1:
+ /* ----------------------------------------------------------------------- */
+ /* L1 configuration: UART0 = 8 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
+
+ break;
+
+ case L2:
+ /* ----------------------------------------------------------------------- */
+ /* L2 configuration: UART0 = 4 pins */
+ /* UART1 = 4 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ case L3:
+ /* ----------------------------------------------------------------------- */
+ /* L3 configuration: UART0 = 4 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ case L4:
+ /* ----------------------------------------------------------------------- */
+ /* L4 configuration: UART0 = 2 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* UART3 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ default:
+ /* Unsupported UART configuration number */
+ printf("ERROR - Unsupported UART configuration number.\n\n");
+ for (;;)
+ ;
+ break;
+
+ }
+
+ /* Set input Selection Register on Alt_Receive for UART Input Core */
+ out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
+ out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
+ out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
+}
+
+/*----------------------------------------------------------------------------+
+ | update_ndfc_ios(void).
+ +----------------------------------------------------------------------------*/
+void update_ndfc_ios(void)
+{
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
+ gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
+
+#if 0
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+ | update_zii_ios(void).
+ +----------------------------------------------------------------------------*/
+void update_zii_ios(void)
+{
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
+ gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
+ gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
+ gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
+ gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
+ gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
+ gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
+ gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
+ gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
+ gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
+ gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
+ gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
+ gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
+ gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
+ gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_0_3_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_0_3_irq_ios(void)
+{
+ gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
+ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
+ gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
+ gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
+ gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_4_9_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_4_9_irq_ios(void)
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_a_b_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_a_b_ios(void)
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_c_d_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_c_d_ios(void)
+{
+ gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
+ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
+ gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
+ gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
+ gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
+ gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
+ gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_ebc_master_ios().
+ +----------------------------------------------------------------------------*/
+void update_ebc_master_ios(void)
+{
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_usb2_device_ios().
+ +----------------------------------------------------------------------------*/
+void update_usb2_device_ios(void)
+{
+ gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
+ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
+ gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
+ gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
+ gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_pci_patch_ios().
+ +----------------------------------------------------------------------------*/
+void update_pci_patch_ios(void)
+{
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | set_chip_gpio_configuration(unsigned char gpio_core)
+ | Put the core impacted by clock modification and sharing in reset.
+ | Config the select registers to resolve the sharing depending of the config.
+ | Configure the GPIO registers.
+ |
+ +----------------------------------------------------------------------------*/
+void set_chip_gpio_configuration(unsigned char gpio_core)
+{
+ unsigned char i=0, j=0, reg_offset = 0;
+ unsigned long gpio_reg, gpio_core_add;
+
+ /* GPIO config of the GPIOs 0 to 31 */
+ for (i=0; i<GPIO_MAX; i++, j++)
+ {
+ if (i == GPIO_MAX/2)
+ {
+ reg_offset = 4;
+ j = i-16;
+ }
+
+ gpio_core_add = gpio_tab[gpio_core][i].add;
+
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------+
+ | force_bup_core_selection.
+ +----------------------------------------------------------------------------*/
+void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
+{
+ /* Pointer invalid */
+ if (core_select_P == NULL)
+ {
+ printf("Configuration invalid pointer 1\n");
+ for (;;)
+ ;
+ }
+
+ /* L4 Selection */
+ *(core_select_P+UART_CORE0) = CORE_SELECTED;
+ *(core_select_P+UART_CORE1) = CORE_SELECTED;
+ *(core_select_P+UART_CORE2) = CORE_SELECTED;
+ *(core_select_P+UART_CORE3) = CORE_SELECTED;
+
+ /* RMII Selection */
+ *(core_select_P+RMII_SEL) = CORE_SELECTED;
+
+ /* External Interrupt 0-9 selection */
+ *(core_select_P+UIC_0_3) = CORE_SELECTED;
+ *(core_select_P+UIC_4_9) = CORE_SELECTED;
+
+ *(core_select_P+SCP_CORE) = CORE_SELECTED;
+ *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
+ *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
+ *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
+
+ if (is_nand_selected()) {
+ *(core_select_P+NAND_FLASH) = CORE_SELECTED;
+ }
+
+ *config_val_P = CONFIG_IS_VALID;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | configure_ppc440ep_pins.
+ +----------------------------------------------------------------------------*/
+void configure_ppc440ep_pins(void)
+{
+ uart_config_nb_t uart_configuration;
+ config_validity_t config_val = CONFIG_IS_INVALID;
+
+ /* Create Core Selection Table */
+ core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
+ {
+ CORE_NOT_SELECTED, /* IIC_CORE, */
+ CORE_NOT_SELECTED, /* SPC_CORE, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
+ CORE_NOT_SELECTED, /* UIC_4_9, */
+ CORE_NOT_SELECTED, /* USB2_HOST, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
+ CORE_NOT_SELECTED, /* USB2_DEVICE, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
+ CORE_NOT_SELECTED, /* USB1_DEVICE, */
+ CORE_NOT_SELECTED, /* EBC_MASTER, */
+ CORE_NOT_SELECTED, /* NAND_FLASH, */
+ CORE_NOT_SELECTED, /* UART_CORE0, */
+ CORE_NOT_SELECTED, /* UART_CORE1, */
+ CORE_NOT_SELECTED, /* UART_CORE2, */
+ CORE_NOT_SELECTED, /* UART_CORE3, */
+ CORE_NOT_SELECTED, /* MII_SEL, */
+ CORE_NOT_SELECTED, /* RMII_SEL, */
+ CORE_NOT_SELECTED, /* SMII_SEL, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
+ CORE_NOT_SELECTED, /* UIC_0_3 */
+ CORE_NOT_SELECTED, /* USB1_HOST */
+ CORE_NOT_SELECTED /* PCI_PATCH */
+ };
+
+
+ /* Table Default Initialisation + FPGA Access */
+ init_default_gpio();
+ set_chip_gpio_configuration(GPIO0);
+ set_chip_gpio_configuration(GPIO1);
+
+ /* Update Table */
+ force_bup_core_selection(ppc440ep_core_selection, &config_val);
+#if 0 /* test-only */
+ /* If we are running PIBS 1, force known configuration */
+ update_core_selection_table(ppc440ep_core_selection, &config_val);
+#endif
+
+ /*----------------------------------------------------------------------------+
+ | SDR + ios table update + fpga initialization
+ +----------------------------------------------------------------------------*/
+ unsigned long sdr0_pfc1 = 0;
+ unsigned long sdr0_usb0 = 0;
+ unsigned long sdr0_mfr = 0;
+
+ /* PCI Always selected */
+
+ /* I2C Selection */
+ if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+ iic1_selection_in_fpga();
+ }
+
+ /* SCP Selection */
+ if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+ scp_selection_in_fpga();
+ }
+
+ /* UIC 0:3 Selection */
+ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
+ {
+ update_uic_0_3_irq_ios();
+ dma_a_b_unselect_in_fpga();
+ }
+
+ /* UIC 4:9 Selection */
+ if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
+ update_uic_4_9_irq_ios();
+ }
+
+ /* DMA AB Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
+ update_dma_a_b_ios();
+ dma_a_b_selection_in_fpga();
+ }
+
+ /* DMA CD Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
+ {
+ update_dma_c_d_ios();
+ dma_c_d_selection_in_fpga();
+ }
+
+ /* EBC Master Selection */
+ if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_ebc_master_ios();
+ }
+
+ /* PCI Patch Enable */
+ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_pci_patch_ios();
+ }
+
+ /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
+ if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
+ {
+ /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
+ printf("Invalid configuration => USB2 Host selected\n");
+ for (;;)
+ ;
+ /*usb2_host_selection_in_fpga(); */
+ }
+
+ /* USB2.0 Device Selection */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ {
+ update_usb2_device_ios();
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
+
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
+ mtsdr(sdr_usb0, sdr0_usb0);
+
+ usb2_device_selection_in_fpga();
+ }
+
+ /* USB1.1 Device Selection */
+ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
+ {
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
+ mtsdr(sdr_usb0, sdr0_usb0);
+ }
+
+ /* USB1.1 Host Selection */
+ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
+ {
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
+ mtsdr(sdr_usb0, sdr0_usb0);
+ }
+
+ /* NAND Flash Selection */
+ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
+ {
+ update_ndfc_ios();
+
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ SDR0_CUST0_CHIPSELGAT_EN1 |
+ SDR0_CUST0_CHIPSELGAT_EN2);
+
+ ndfc_selection_in_fpga();
+ }
+ else
+ {
+ /* Set Mux on EMAC */
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
+ }
+
+ /* MII Selection */
+ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
+ }
+
+ /* RMII Selection */
+ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
+ }
+
+ /* SMII Selection */
+ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
+ }
+
+ /* UART Selection */
+ uart_configuration = get_uart_configuration();
+ switch (uart_configuration)
+ {
+ case L1: /* L1 Selection */
+ /* UART0 8 pins Only */
+ /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
+ break;
+ case L2: /* L2 Selection */
+ /* UART0 and UART1 4 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L3: /* L3 Selection */
+ /* UART0 4 pins, UART1 and UART2 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L4: /* L4 Selection */
+ /* UART0, UART1, UART2 and UART3 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ }
+ update_uart_ios(uart_configuration);
+
+ /* UART Selection in all cases */
+ uart_selection_in_fpga(uart_configuration);
+
+ /* Packet Reject Function Available */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
+ {
+ /* Set UPR Bit in SDR0_PFC1 Register */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
+ }
+
+ /* Packet Reject Function Enable */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
+ {
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
+ mtsdr(sdr_mfr, sdr0_mfr);
+ }
+
+ /* Perform effective access to hardware */
+ mtsdr(sdr_pfc1, sdr0_pfc1);
+ set_chip_gpio_configuration(GPIO0);
+ set_chip_gpio_configuration(GPIO1);
+
+ /* USB2.0 Device Reset must be done after GPIO setting */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ usb2_device_reset_through_fpga();
+
+}
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*----------------------------------------------------------------------------+
+ | FPGA registers and bit definitions
+ +----------------------------------------------------------------------------*/
+/*
+ * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
+ * TLB initialization makes it correspond to logical address 0x80001FF0.
+ * => Done init_chip.s in bootlib
+ */
+#define FPGA_BASE_ADDR 0x80002000
+
+/*----------------------------------------------------------------------------+
+ | Board Jumpers Setting Register
+ | Board Settings provided by jumpers
+ +----------------------------------------------------------------------------*/
+#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
+/* Boot from small flash */
+#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
+/* Operational Flash versus SRAM position in Memory Map */
+#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
+#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
+#define FPGA_SET_REG_SRAM_ABOVE 0x00
+/* Boot From NAND Flash */
+#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
+#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
+/* On Board PCI Arbiter Select */
+#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
+#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 1
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
+#define FPGA_SEL_1_REG_PHY_MASK 0xE0
+#define FPGA_SEL_1_REG_MII 0x80
+#define FPGA_SEL_1_REG_RMII 0x40
+#define FPGA_SEL_1_REG_SMII 0x20
+#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
+#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
+#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
+#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
+#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
+#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 2
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
+#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
+#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
+#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
+#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
+#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
+#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
+#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
+ /* 1 = TC - output from 440EP */
+#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
+ /* 1 = TC (output from 440EP) */
+#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
+#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
+#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 3
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
+#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
+#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
+#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
+#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
+
+/*----------------------------------------------------------------------------+
+ | Soft Reset Register
+ +----------------------------------------------------------------------------*/
+#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
+#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
+#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
+#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
+
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+/* Serial Device Strap Reg 0 */
+#define SDR0_SDSTP0 0x0020
+/* Serial Device Strap Reg 1 */
+#define SDR0_SDSTP1 0x0021
+/* Serial Device Strap Reg 2 */
+#define SDR0_SDSTP2 SDR0_STRP2
+/* Serial Device Strap Reg 3 */
+#define SDR0_SDSTP3 SDR0_STRP3
+
+#define sdr_pstrp0 0x0040
+
+#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
+#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
+#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
+#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
+
+#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
+#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
+#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
+#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0 0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
+
+/*----------------------------------------------------------------------------+
+| EBC Configuration Register - EBC0_CFG
++----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN 0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED 0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK 0x38000000
+#define EBC0_CFG_RTC_16PERCLK 0x00000000
+#define EBC0_CFG_RTC_32PERCLK 0x08000000
+#define EBC0_CFG_RTC_64PERCLK 0x10000000
+#define EBC0_CFG_RTC_128PERCLK 0x18000000
+#define EBC0_CFG_RTC_256PERCLK 0x20000000
+#define EBC0_CFG_RTC_512PERCLK 0x28000000
+#define EBC0_CFG_RTC_1024PERCLK 0x30000000
+#define EBC0_CFG_RTC_2048PERCLK 0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW 0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
+#define EBC0_CFG_EMPL_HIGH 0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW 0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
+#define EBC0_CFG_EMPH_HIGH 0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN 0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW 0x00000000
+#define EBC0_CFG_BPF_TWODW 0x00100000
+#define EBC0_CFG_BPF_FOURDW 0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT 0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED 0x00000000
+#define EBC0_CFG_PME_ENABLED 0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Configuration Register - EBC0_BnCR
++----------------------------------------------------------------------------*/
+/* BAS - Base Address Select */
+#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
+/* BS - Bank Size */
+#define EBC0_BNCR_BS_MASK 0x000E0000
+#define EBC0_BNCR_BS_1MB 0x00000000
+#define EBC0_BNCR_BS_2MB 0x00020000
+#define EBC0_BNCR_BS_4MB 0x00040000
+#define EBC0_BNCR_BS_8MB 0x00060000
+#define EBC0_BNCR_BS_16MB 0x00080000
+#define EBC0_BNCR_BS_32MB 0x000A0000
+#define EBC0_BNCR_BS_64MB 0x000C0000
+#define EBC0_BNCR_BS_128MB 0x000E0000
+/* BU - Bank Usage */
+#define EBC0_BNCR_BU_MASK 0x00018000
+#define EBC0_BNCR_BU_RO 0x00008000
+#define EBC0_BNCR_BU_WO 0x00010000
+#define EBC0_BNCR_BU_RW 0x00018000
+/* BW - Bus Width */
+#define EBC0_BNCR_BW_MASK 0x00006000
+#define EBC0_BNCR_BW_8BIT 0x00000000
+#define EBC0_BNCR_BW_16BIT 0x00002000
+#define EBC0_BNCR_BW_32BIT 0x00004000
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Access Parameters - EBC0_BnAP
++----------------------------------------------------------------------------*/
+/* Burst Mode Enable */
+#define EBC0_BNAP_BME_ENABLED 0x80000000
+#define EBC0_BNAP_BME_DISABLED 0x00000000
+/* Transfert Wait */
+#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
+/* Chip Select On Timing */
+#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
+/* Output Enable On Timing */
+#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
+/* Write Back Enable On Timing */
+#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
+/* Write Back Enable Off Timing */
+#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
+/* Transfert Hold */
+#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
+/* PerReady Enable */
+#define EBC0_BNAP_RE_ENABLED 0x00000100
+#define EBC0_BNAP_RE_DISABLED 0x00000000
+/* Sample On Ready */
+#define EBC0_BNAP_SOR_DELAYED 0x00000000
+#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
+/* Byte Enable Mode */
+#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
+#define EBC0_BNAP_BEM_RW 0x00000040
+/* Parity Enable */
+#define EBC0_BNAP_PEN_DISABLED 0x00000000
+#define EBC0_BNAP_PEN_ENABLED 0x00000020
+
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+/* */
+#define BOOT_FROM_SMALL_FLASH 0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
+#define BOOT_FROM_NAND_FLASH0 0x02
+#define BOOT_FROM_PCI 0x03
+#define BOOT_DEVICE_UNKNOWN 0x04
+
+
+#define PVR_POWERPC_440EP_PASS1 0x42221850
+#define PVR_POWERPC_440EP_PASS2 0x422218D3
+
+#define TRUE 1
+#define FALSE 0
+
+#define GPIO_GROUP_MAX 2
+#define GPIO_MAX 32
+#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
+#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+ /* For the other GPIO number, you must shift */
+
+#define GPIO0 0
+#define GPIO1 1
+
+
+/*#define MAX_SELECTION_NB CORE_NB */
+#define MAX_CORE_SELECT_NB 22
+
+/*----------------------------------------------------------------------------+
+ | PPC440EP GPIOs addresses.
+ +----------------------------------------------------------------------------*/
+#define GPIO0_BASE 0xEF600B00
+#define GPIO0_REAL 0xEF600B00
+
+#define GPIO1_BASE 0xEF600C00
+#define GPIO1_REAL 0xEF600C00
+
+/* Offsets */
+#define GPIOx_OR 0x00 /* GPIO Output Register */
+#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
+#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
+#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
+#define GPIOx_IR 0x1C /* GPIO Input Register */
+#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
+#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
+#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
+#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
+
+/* GPIO0 */
+#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
+#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
+#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
+#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
+#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
+#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
+
+/* GPIO1 */
+#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
+#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
+#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
+#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
+#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
+#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
+
+
+/*----------------------------------------------------------------------------+
+ | Declare Configuration values
+ +----------------------------------------------------------------------------*/
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct { unsigned long add; /* gpio core base address */
+ gpio_driver_t in_out; /* Driver Setting */
+ gpio_select_t alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+/*----------------------------------------------------------------------------+
+ | XX XX
+ |
+ | XXXXXX XXX XX XXX XXX
+ | XX XX X XX XX XX
+ | XX XX X XX XX XX
+ | XX XX XX XX XX
+ | XXXXXX XXX XXX XXXX XXXX
+ +----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+ | Defines
+ +----------------------------------------------------------------------------*/
+typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
+ ZMII_CONFIGURATION_IS_MII,
+ ZMII_CONFIGURATION_IS_RMII,
+ ZMII_CONFIGURATION_IS_SMII
+} zmii_config_t;
+
+/*----------------------------------------------------------------------------+
+ | Declare Configuration values
+ +----------------------------------------------------------------------------*/
+typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
+typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
+typedef enum config_list { IIC_CORE,
+ SCP_CORE,
+ DMA_CHANNEL_AB,
+ UIC_4_9,
+ USB2_HOST,
+ DMA_CHANNEL_CD,
+ USB2_DEVICE,
+ PACKET_REJ_FUNC_AVAIL,
+ USB1_DEVICE,
+ EBC_MASTER,
+ NAND_FLASH,
+ UART_CORE0,
+ UART_CORE1,
+ UART_CORE2,
+ UART_CORE3,
+ MII_SEL,
+ RMII_SEL,
+ SMII_SEL,
+ PACKET_REJ_FUNC_EN,
+ UIC_0_3,
+ USB1_HOST,
+ PCI_PATCH,
+ CORE_NB
+} core_list_t;
+
+typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
+ B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
+ B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
+ B3_V16, B3_VALUE_UNKNOWN
+} block3_value_t;
+
+typedef enum config_validity { CONFIG_IS_VALID,
+ CONFIG_IS_INVALID
+} config_validity_t;
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "bamboo.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+ {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
+ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+ {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
+ {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
+ {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+ unsigned long val;
+ unsigned long ebc_boot_size;
+ unsigned long boot_selection;
+
+ mfsdr(sdr_pstrp0, val);
+ index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
+
+ if ((index == 5) || (index == 7)) {
+ /*
+ * Boot Settings in IIC EEprom address 0xA8 or 0xA4
+ * Read Serial Device Strap Register1 in PPC440EP
+ */
+ mfsdr(sdr_sdstp1, val);
+ boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ index = 3;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ index = 0;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ index = 1;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ index = 2;
+ break;
+ }
+ } else if (index == 0) {
+ if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
+ index = 8; /* sram below op code flash -> new index 8 */
+ }
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
--- /dev/null
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_8M 0x00000060
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+ tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+ /* PCI */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+ /* USB 2.0 Device */
+ tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/bamboo/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+long int spd_sdram(void);
+
+#include <common.h>
+#include <asm/processor.h>
+
+int board_early_init_f(void)
+{
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000010);
+ mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
+ mtdcr(uictr, 0x00000010); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ unsigned char *s = getenv("serial#");
+
+ puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+ return;
+}
+
+/* -------------------------------------------------------------------------
+ initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ the necessary info for SDRAM controller configuration
+ ------------------------------------------------------------------------- */
+long int initdram(int board_type)
+{
+ long int ret;
+
+ ret = spd_sdram();
+ return ret;
+}
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("test: xxx MB - ok\n");
+
+ return (0);
+}
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ if (CFG_MAX_FLASH_BANKS == 1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ size_b1 = 0;
+ flash_info[0].size = size_b0;
+ }
+
+ /* 2 banks */
+ else {
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b1 = -size_b1;
+ pbcr = (pbcr & 0x0001ffff) | base_b1 |
+ (((size_b1 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb1cr = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr(ebccfga, pb1cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb1cr);
+ base_b0 = base_b1 - size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 |
+ (((size_b0 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb0cr = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets(base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b0 + size_b0 - CFG_MONITOR_LEN,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+ /* Also protect sector containing initial power-up instruction */
+ /* (flash_protect() checks address range - other call ignored) */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 =
+ flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets(base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b1 + size_b1 - CFG_MONITOR_LEN,
+ base_b1 + size_b1 - 1,
+ &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ (void)flash_protect(FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 - CFG_MONITOR_LEN,
+ base_b0 + size_b0 - 1,
+ &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+ } /* else 2 banks */
+ return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/bubinga405ep/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
--- /dev/null
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1) {
+ return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ int n;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ /* 1 x 16k boot sector */
+ base -= 16 << 10;
+ --i;
+ info->start[i] = base;
+ /* 2 x 8k boot sectors */
+ for (n=0; n<2; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ /* 1 x 32k boot sector */
+ base -= 32 << 10;
+ --i;
+ info->start[i] = base;
+
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
* MA 02111-1307 USA
*/
-
#include <common.h>
-#include "ebony.h"
#include <asm/processor.h>
#include <spd_sdram.h>
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
-long int fixed_sdram (void);
+long int fixed_sdram(void);
-int board_early_init_f (void)
+int board_early_init_f(void)
{
uint reg;
- unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+ unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char status;
-
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
- mtdcr (ebccfga, xbcfg);
- reg = mfdcr (ebccfgd);
- mtdcr (ebccfgd, reg | 0x04000000); /* Set ATC */
+ mtdcr(ebccfga, xbcfg);
+ reg = mfdcr(ebccfgd);
+ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
- mtebc (pb1ap, 0x02815480); /* NVRAM/RTC */
- mtebc (pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
- mtebc (pb7ap, 0x01015280); /* FPGA registers */
- mtebc (pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
+ mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
+ mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
+ mtebc(pb7ap, 0x01015280); /* FPGA registers */
+ mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
/* read FPGA_REG0 and set the bus controller */
status = *fpga_base;
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
- mtebc (pb0ap, 0x9b015480); /* FLASH/SRAM */
- mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
- mtebc (pb2ap, 0x9b015480); /* 4MB FLASH */
- mtebc (pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
+ mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
+ mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
+ mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
+ mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
} else {
- mtebc (pb0ap, 0x9b015480); /* 4MB FLASH */
- mtebc (pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
+ mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
+ mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
/* set CS2 if FLASH_ONBD_N == 0 */
if (!(status & FLASH_ONBD_N)) {
- mtebc (pb2ap, 0x9b015480); /* FLASH/SRAM */
- mtebc (pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
+ mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
+ mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
}
}
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
return 0;
}
-
-int checkboard (void)
+int checkboard(void)
{
sys_info_t sysinfo;
+ unsigned char *s = getenv("serial#");
- get_sys_info (&sysinfo);
+ get_sys_info(&sysinfo);
- printf ("Board: IBM 440GP Evaluation Board (Ebony)\n");
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+ printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
-
-long int initdram (int board_type)
+long int initdram(int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram (0);
+ dram_size = spd_sdram(0);
#else
- dram_size = fixed_sdram ();
+ dram_size = fixed_sdram();
#endif
return dram_size;
}
-
#if defined(CFG_DRAM_TEST)
-int testdram (void)
+int testdram(void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
+ printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
+ printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
* PLB @ 133 MHz
*
************************************************************************/
-long int fixed_sdram (void)
+long int fixed_sdram(void)
{
uint reg;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
- mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
- mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- udelay (400); /* Delay 200 usecs (min) */
+ mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
- mfsdram (mem_mcsts, reg);
+ mfsdram(mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
return (128 * 1024 * 1024); /* 128 MB */
}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
+#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
-int pci_pre_init(struct pci_controller * hose )
+int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
+ unsigned long strap;
/*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
- strap = mfdcr(cpc0_strp1);
- if( (strap & 0x00100000) == 0 ){
- printf("PCI: CPC0_STRP1[PAE] not set.\n");
- return 0;
- }
+ strap = mfdcr(cpc0_strp1);
+ if ((strap & 0x00100000) == 0) {
+ printf("PCI: CPC0_STRP1[PAE] not set.\n");
+ return 0;
+ }
- return 1;
+ return 1;
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
+void pci_target_init(struct pci_controller *hose)
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r(PCIX0_PIM0SA, 0); /* disable */
+ out32r(PCIX0_PIM1SA, 0); /* disable */
+ out32r(PCIX0_PIM2SA, 0); /* disable */
+ out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+ out32r(PCIX0_PIM0LAH, 0);
+ out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out32r( PCIX0_BAR0, 0 );
+ out32r(PCIX0_BAR0, 0);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+ out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
+ out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
- /* The ebony board is always configured as host. */
- return(1);
+ /* The ebony board is always configured as host. */
+ return (1);
}
-#endif /* defined(CONFIG_PCI) */
+#endif /* defined(CONFIG_PCI) */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
+ {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
+ {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
+ {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
+ {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ /* check the bitmap of switch status */
+ if (switch_status & BOOT_SMALL_FLASH) {
+ index += BOOT_SMALL_FLASH_VAL;
+ }
+ if (switch_status & FLASH_ONBD_N) {
+ index += FLASH_ONBD_N_VAL;
+ }
+ if (switch_status & FLASH_SRAM_SEL) {
+ index += FLASH_SRAM_SEL_VAL;
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *)
+ flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[2]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/ebony/init.o (.text)
+ board/amcc/ebony/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
--- /dev/null
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
+ {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
+ {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
+ {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
+ {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ /* check the bitmap of switch status */
+ if (switch_status & BOOT_SMALL_FLASH) {
+ index += BOOT_SMALL_FLASH_VAL;
+ }
+ if (switch_status & FLASH_ONBD_N) {
+ index += FLASH_ONBD_N_VAL;
+ }
+ if (switch_status & FLASH_SRAM_SEL) {
+ index += FLASH_SRAM_SEL_VAL;
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] =
+ flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf
+ ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[i]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
/*
* Copyright (C) 2004 PaulReynolds@lhsolutions.com
*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
int checkboard (void)
{
sys_info_t sysinfo;
+ unsigned char *s = getenv ("serial#");
get_sys_info (&sysinfo);
- printf ("Board: IBM 440GX Evaluation Board\n");
+ printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
+ if (s != NULL) {
+ puts (", serial# ");
+ puts (s);
+ }
+ putc ('\n');
+
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/ocotea/init.o (.text)
+ board/amcc/ocotea/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ if (CFG_MAX_FLASH_BANKS == 1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ size_b1 = 0;
+ flash_info[0].size = size_b0;
+ } else {
+ /* 2 banks */
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b1 = -size_b1;
+ pbcr =
+ (pbcr & 0x0001ffff) | base_b1 |
+ (((size_b1 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb1cr = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr(ebccfga, pb1cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb1cr);
+ base_b0 = base_b1 - size_b0;
+ pbcr =
+ (pbcr & 0x0001ffff) | base_b0 |
+ (((size_b0 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb0cr = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets(base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 =
+ flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets(base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b1 + size_b1 -
+ monitor_flash_len,
+ base_b1 + size_b1 - 1,
+ &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ (void)flash_protect(FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 -
+ monitor_flash_len,
+ base_b0 + size_b0 - 1,
+ &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+ } /* else 2 banks */
+ return (size_b0 + size_b1);
+}
+
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/walnut405/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the Walnut/Sycamore board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED
+ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+ | IRQ 27 (EXT IRQ 2) Not Used
+ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+ | Note for Walnut board:
+ | An interrupt taken for the FPGA (IRQ 25) indicates that either
+ | the Mouse, Keyboard, IRDA, or External Expansion caused the
+ | interrupt. The FPGA must be read to determine which device
+ | caused the interrupt. The default setting of the FPGA clears
+ |
+ +-------------------------------------------------------------------------*/
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
+ mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ /* set UART1 control to select CTS/RTS */
+#define FPGA_BRDC 0xF0300004
+ *(volatile char *)(FPGA_BRDC) |= 0x1;
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ unsigned char *s = getenv("serial#");
+ uint pvr = get_pvr();
+
+ if (pvr == PVR_405GPR_RB) {
+ puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
+ } else {
+ puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
+ }
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+ return;
+}
+
+/*
+ * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * the necessary info for SDRAM controller configuration
+ */
+long int initdram(int board_type)
+{
+ return spd_sdram(0);
+}
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("test: xxx MB - ok\n");
+
+ return (0);
+}
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+OBJS += flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
/*
- * (C) Copyright 2004-2005
+ * (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
+/*
+ * Ported to XPedite1000, 1/2 mb boot flash only
+ * Travis B. Sawyer, <travis.sawyer@sandburst.com>
+ */
+
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
-
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
-#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
-#define BOOT_SMALL_FLASH_VAL 4
-#define FLASH_ONBD_N_VAL 2
-#define FLASH_SRAM_SEL_VAL 1
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+unsigned long flash_addr_table[512][CFG_MAX_FLASH_BANKS] = {
+ {0xfe000000}
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
- {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
- {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
- {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
- {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
- {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
- {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
- {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
- {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
};
/*-----------------------------------------------------------------------
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-#ifdef CONFIG_OCOTEA
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
+#define ADDR0 0xaaaa
+#define ADDR1 0x5554
+#define FLASH_WORD_SIZE unsigned short
/*-----------------------------------------------------------------------
*/
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
- unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
- unsigned char switch_status;
unsigned short index = 0;
int i;
- /* read FPGA base register FPGA_REG0 */
- switch_status = *fpga_base;
-
- /* check the bitmap of switch status */
- if (switch_status & BOOT_SMALL_FLASH) {
- index += BOOT_SMALL_FLASH_VAL;
- }
- if (switch_status & FLASH_ONBD_N) {
- index += FLASH_ONBD_N_VAL;
- }
- if (switch_status & FLASH_SRAM_SEL) {
- index += FLASH_SRAM_SEL_VAL;
- }
-
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
}
/* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]);
+ size_b[i] = flash_get_size((vu_long *)
+ flash_addr_table[index][i],
+ &flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i] << 20);
+ printf
+ ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
total_b += flash_info[i].size;
}
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
- 0xffffffff,
- &flash_info[2]);
+ /* FLASH protect Monitor */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE, 0xFFFFFFFF, &flash_info[0]);
return total_b;
}
case FLASH_MAN_AMD:
printf("AMD ");
break;
- case FLASH_MAN_STM:
- printf("STM ");
- break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
case FLASH_AM040:
printf("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
- case FLASH_AMDLV033C:
- printf("AM29LV033C (32 Mbit, top boot sector)\n");
- break;
case FLASH_SST800A:
printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
- flash = (volatile unsigned long *) info->start[i];
+ flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) {
/*-----------------------------------------------------------------------
*/
+/*-----------------------------------------------------------------------
+ */
+
/*
* The following code cannot be run from FLASH!
*/
ulong base = (ulong) addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
- DEBUGF("FLASH ADDR: %08x\n", (unsigned) addr);
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
udelay(10000);
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x00AA;
udelay(1000);
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = (FLASH_WORD_SIZE) 0x0055;
udelay(1000);
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x0090;
udelay(1000);
value = addr2[0];
+
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
- return (0); /* no or unknown flash */
+ return (0); /* no or unknown flash */
}
- value = addr2[1]; /* device ID */
+#ifdef CONFIG_ADCIOP
+ value = addr2[0]; /* device ID */
+ debug("\ndev_code=%x\n", value);
+#else
+ value = addr2[1]; /* device ID */
+#endif
DEBUGF("\nFLASH DEVICEID: %x\n", value);
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) STM_ID_M29W040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_LV033C:
- info->flash_id += FLASH_AMDLV033C;
- info->sector_count = 64;
- info->size = 0x00400000;
- break; /* => 4 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
+ info->flash_id = 0;
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ info->size = 0x02000000;
/* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
-
- /* For AMD29033C flash we need to resend the command of *
- * reading flash protection for upper 8 Mb of flash */
- if ( i == 32 ) {
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
+ info->start[i] = (int)base + (i * 0x00020000);
+ info->protect[i] = 0;
}
- /* issue bank reset to return to read mode */
- addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- /* ? ? ? */
- }
+ *(FLASH_WORD_SIZE *) ((int)addr) = (FLASH_WORD_SIZE) 0x00F0; /* reset bank */
return (info->size);
}
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr =
- (FLASH_WORD_SIZE *) (info->start[sect]);
+ (FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
- int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+ printf("Erasing sector %p\n", addr2);
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
+ (FLASH_WORD_SIZE) 0x00AA;
+ asm("sync");
+ asm("isync");
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
+ (FLASH_WORD_SIZE) 0x0055;
+ asm("sync");
+ asm("isync");
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
+ (FLASH_WORD_SIZE) 0x0080;
+ asm("sync");
+ asm("isync");
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
+ (FLASH_WORD_SIZE) 0x00AA;
+ asm("sync");
+ asm("isync");
+ *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
+ (FLASH_WORD_SIZE) 0x0055;
+ asm("sync");
+ asm("isync");
+ addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ asm("sync");
+ asm("isync");
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
l_sect = sect;
/*
* Wait for each sector to complete, it's more
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
+#if 0
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+ wait_for_DQ7(info, l_sect);
+
+ DONE:
+#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
{
ulong cp, wp, data;
int i, l, rc;
+ ulong status_value = 0;
- wp = (addr & ~3); /* get lower word aligned address */
+ wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
+
+ /*print status if needed */
+ if ((wp >= (status_value + 0x20000))
+ && (status_value < 0xFFFE0000)) {
+ status_value = wp;
+ printf("writing to sector 0x%X\n", status_value);
+ }
+
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
*/
static int write_word(flash_info_t * info, ulong dest, ulong data)
{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+ vu_long *addr2 = (vu_long *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ if ((*((volatile FLASH_WORD_SIZE *)dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+ *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
+ (FLASH_WORD_SIZE) 0x00AA;
+ asm("sync");
+ asm("isync");
+ *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR1) =
+ (FLASH_WORD_SIZE) 0x0055;
+ asm("sync");
+ asm("isync");
+ *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
+ (FLASH_WORD_SIZE) 0x00A0;
+ asm("sync");
+ asm("isync");
dest2[i] = data2[i];
return (0);
}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_8M 0x00000060
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ /*
+ 0xf0000000 must be first, before relocation SA_I must be off to use the
+ dcache as stack. It is patched after relocation to enable SA_I
+ */
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+ /* PCI */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+ /* USB 2.0 Device */
+ tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/yellowstone/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+ register uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(ebccfga, xbcfg);
+ reg = mfdcr(ebccfgd);
+ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
+
+ mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
+ mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
+
+ mtebc(pb1ap, 0x00000000);
+ mtebc(pb1cr, 0x00000000);
+
+ mtebc(pb2ap, 0x04814500);
+ /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
+
+ mtebc(pb3ap, 0x00000000);
+ mtebc(pb3cr, 0x00000000);
+
+ mtebc(pb4ap, 0x00000000);
+ mtebc(pb4cr, 0x00000000);
+
+ mtebc(pb5ap, 0x00000000);
+ mtebc(pb5cr, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ /*CPLD cs */
+ /*setup Address lines for flash sizes larger than 16Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
+
+ /*setup emac */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+ out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+ /*UART1 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+ out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+ /*setup USB 2.0 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+ out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+
+ /*--------------------------------------------------------------------
+ * Setup other serial configuration
+ *-------------------------------------------------------------------*/
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
+ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
+
+ /*clear tmrclk divisor */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+ /*enable ethernet */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+
+ /*enable usb 1.1 fs device and remove usb 2.0 reset */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+
+ /*get rid of flash write protect */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+
+ printf("Board: AMCC YELLOWSTONE\n");
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
+ printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
+ return (0);
+}
+
+/*************************************************************************
+ * sdram_init -- doesn't use serial presence detect.
+ *
+ * Assumes: 256 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+void sdram_init(void)
+{
+ register uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_clktr, 0x40000000); /* ?? */
+ mtsdram(mem_wddctr, 0x40000000); /* ?? */
+
+ /*clear this first, if the DDR is enabled by a debugger
+ then you can not make changes. */
+ mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
+ mtsdram(mem_tr0, 0x410a4012); /* ?? */
+ mtsdram(mem_tr1, 0x8080080b); /* ?? */
+ mtsdram(mem_rtr, 0x04080000); /* ?? */
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram(mem_cfg0, 0x84000000); /* Enable */
+
+ for (;;) {
+ mfsdram(mem_mcsts, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+}
+
+/*************************************************************************
+ * long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+ sdram_init();
+ return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ for (k = 0; k < CFG_KBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ return 0;
+}
+#endif
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long strap;
+ unsigned long addr;
+
+ /*--------------------------------------------------------------------------+
+ * Bamboo is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
+ printf("PCI: SDR0_STRP1[PAE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return 0;
+ }
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440 EP PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Bamboo is always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+}
+#endif
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_8M 0x00000060
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+ /* PCI */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+ /* USB 2.0 Device */
+ tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/yosemite/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+int board_early_init_f(void)
+{
+ register uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(ebccfga, xbcfg);
+ reg = mfdcr(ebccfgd);
+ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
+
+ mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
+ mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
+
+ mtebc(pb1ap, 0x00000000);
+ mtebc(pb1cr, 0x00000000);
+
+ mtebc(pb2ap, 0x04814500);
+ /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
+
+ mtebc(pb3ap, 0x00000000);
+ mtebc(pb3cr, 0x00000000);
+
+ mtebc(pb4ap, 0x00000000);
+ mtebc(pb4cr, 0x00000000);
+
+ mtebc(pb5ap, 0x00000000);
+ mtebc(pb5cr, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ /*CPLD cs */
+ /*setup Address lines for flash sizes larger than 16Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
+
+ /*setup emac */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+ out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+ /*UART1 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+ out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+ /*setup USB 2.0 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+ out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+
+ /*--------------------------------------------------------------------
+ * Setup other serial configuration
+ *-------------------------------------------------------------------*/
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
+ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
+
+ /*clear tmrclk divisor */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+ /*enable ethernet */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+
+ /*enable usb 1.1 fs device and remove usb 2.0 reset */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+
+ /*get rid of flash write protect */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ uint pbcr;
+ int size_val = 0;
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+
+ printf("Board: AMCC YOSEMITE\n");
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
+ printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
+
+
+ return (0);
+}
+
+/*************************************************************************
+ * sdram_init -- doesn't use serial presence detect.
+ *
+ * Assumes: 256 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+void sdram_init(void)
+{
+ register uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_clktr, 0x40000000); /* ?? */
+ mtsdram(mem_wddctr, 0x40000000); /* ?? */
+
+ /*clear this first, if the DDR is enabled by a debugger
+ then you can not make changes. */
+ mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
+
+ mtsdram(mem_tr0, 0x410a4012); /* ?? */
+ mtsdram(mem_tr1, 0x8080080b); /* ?? */
+ mtsdram(mem_rtr, 0x04080000); /* ?? */
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram(mem_cfg0, 0x84000000); /* Enable */
+
+ for (;;) {
+ mfsdram(mem_mcsts, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+}
+
+/*************************************************************************
+ * long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+ sdram_init();
+ return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ for (k = 0; k < CFG_KBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ return 0;
+}
+#endif
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long strap;
+ unsigned long addr;
+
+ /*--------------------------------------------------------------------------+
+ * Bamboo is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
+ printf("PCI: SDR0_STRP1[PAE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return 0;
+ }
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440 EP PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Bamboo is always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
break;
default:
printf ("Unknown Chip Type\n");
- goto Done;
- break;
+ return;
}
printf (" Size: %ld MB in %d Sectors\n",
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
-
-Done: ;
}
/*-----------------------------------------------------------------------
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-long int spd_sdram (void);
-
-#include <common.h>
-#include <asm/processor.h>
-
-
-int board_early_init_f (void)
-{
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000010);
- mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
- mtdcr (uictr, 0x00000010); /* set int trigger levels */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
-
-#if 0
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
- /* CS1 */
- /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb1ap, 0x02815480);
- mtebc (pb1cr, 0xF0018000);
-
- p = (unsigned int*)0xEF600708;
- t = *p;
- t = t | 0x00000400;
- *p = t;
-
- /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb2ap, 0x04815A80);
- mtebc (pb2cr, 0xF0118000);
-
- /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb3ap, 0x01815280);
- mtebc (pb3cr, 0xF0218000);
-
- /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb7ap, 0x01815280);
- mtebc (pb7cr, 0xF0318000);
-
-
- /* set UART1 control to select CTS/RTS */
-#define FPGA_BRDC 0xF0300004
- *(volatile char *) (FPGA_BRDC) |= 0x1;
-
-#endif
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- unsigned char *s = getenv ("serial#");
-
- puts ("Board: IBM 405EP Eval Board");
-
- if (s != NULL) {
- puts (", serial# ");
- puts (s);
- }
- putc ('\n');
-
- return (0);
-}
-
-
-/* -------------------------------------------------------------------------
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
- ------------------------------------------------------------------------- */
-long int initdram (int board_type)
-{
- long int ret;
-
- ret = spd_sdram ();
- return ret;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: xxx MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-#ifdef CONFIG_ADCIOP
-#define ADDR0 0x0aa9
-#define ADDR1 0x0556
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_CPCI405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned short
-#endif
-
-#ifdef CONFIG_WALNUT405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_BUBINGA405EP
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Only one bank */
- if (CFG_MAX_FLASH_BANKS == 1) {
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM + CFG_MONITOR_LEN - 1,
- &flash_info[0]);
- /* Also protect sector containing initial power-up instruction */
- (void) flash_protect (FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
- size_b1 = 0;
- flash_info[0].size = size_b0;
- }
-
- /* 2 banks */
- else {
- size_b1 = flash_get_size ((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1) {
- mtdcr (ebccfga, pb0cr);
- pbcr = mfdcr (ebccfgd);
- mtdcr (ebccfga, pb0cr);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 |
- (((size_b1 / 1024 / 1024) - 1) << 17);
- mtdcr (ebccfgd, pbcr);
- /* printf("pb1cr = %x\n", pbcr); */
- }
-
- if (size_b0) {
- mtdcr (ebccfga, pb1cr);
- pbcr = mfdcr (ebccfgd);
- mtdcr (ebccfga, pb1cr);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 |
- (((size_b0 / 1024 / 1024) - 1) << 17);
- mtdcr (ebccfgd, pbcr);
- /* printf("pb0cr = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- base_b0 + size_b0 - CFG_MONITOR_LEN,
- base_b0 + size_b0 - 1, &flash_info[0]);
- /* Also protect sector containing initial power-up instruction */
- /* (flash_protect() checks address range - other call ignored) */
- (void) flash_protect (FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
- (void) flash_protect (FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- base_b1 + size_b1 - CFG_MONITOR_LEN,
- base_b1 + size_b1 - 1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void) flash_protect (FLAG_PROTECT_CLEAR,
- base_b0 + size_b0 - CFG_MONITOR_LEN,
- base_b0 + size_b0 - 1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- } /* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *) info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-#if 0 /* test-only */
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " "
-#else
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ", info->protect[i] ? "RO " : " "
-#endif
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
-
-#ifdef CONFIG_ADCIOP
- value = addr2[2];
-#else
- value = addr2[0];
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- /* printf("\ndev_code=%x\n", value); */
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (FLASH_WORD_SIZE) AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- case (FLASH_WORD_SIZE) SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- info->protect[i] = addr2[4] & 1;
-#else
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
-#endif
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile unsigned char *) info->start[0];
- addr2[ADDR0] = 0xAA;
- addr2[ADDR1] = 0x55;
- addr2[ADDR0] = 0xF0; /* reset bank */
-#else
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-#endif
-#else /* test-only */
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-#endif /* test-only */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7 (flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer (0);
- last = 0;
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
- printf ("Erasing sector %p\n", addr2); /* CLH */
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay (1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7 (info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7 (info, l_sect);
-
- DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*------------------------------------------------------------------------------+ */
-/* */
-/* This source code has been made available to you by IBM on an AS-IS */
-/* basis. Anyone receiving this source is licensed under IBM */
-/* copyrights to use it in any way he or she deems fit, including */
-/* copying it, modifying it, compiling it, and redistributing it either */
-/* with or without modifications. No license under IBM patents or */
-/* patent applications is to be implied by the copyright license. */
-/* */
-/* Any user of this software should understand that IBM cannot provide */
-/* technical support for this software and will not be responsible for */
-/* any consequences resulting from the use of this software. */
-/* */
-/* Any person who transfers this source code or any derivative work */
-/* must include the IBM copyright notice, this paragraph, and the */
-/* preceding two paragraphs in the transferred software. */
-/* */
-/* COPYRIGHT I B M CORPORATION 1995 */
-/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
-
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - NVRAM/RTC */
-/* Bank 2 - Keyboard/Mouse controller */
-/* Bank 3 - IR controller */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - FPGA registers */
-/*----------------------------------------------------------------------------- */
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
-/*----------------------------------------------------------------------------- */
-/* Function: sdram_init */
-/* Description: Dummy implementation here - done in C later */
-/*----------------------------------------------------------------------------- */
- .globl sdram_init
-sdram_init:
- blr
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-/*
- cpu/ppc4xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
-*/
- cpu/ppc4xx/start.o (.text)
- board/bubinga405ep/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-
- common/environment.o(.text)
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <ioports.h>
#include <spd.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
void sdram_init(void);
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
int board_early_init_f (void)
{
return 0;
#endif
dram_size = spd_sdram();
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o \
+ ../common/cadmus.o \
+ ../common/eeprom.o
+
+SOBJS := init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8548cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 1M Non-cacheable, guarded
+ * 0xf8000000 1M CADMUS registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long 6
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+ entry_end
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
+ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+
+ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+ printf (" PCI1: %d bit, %s MHz, %s\n",
+ (pci1_32) ? 32 : 64,
+ (pci1_speed == 33000000) ? "33" :
+ (pci1_speed == 66000000) ? "66" : "unknown",
+ pci1_clk_sel ? "sync" : "async");
+
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+
+ /*
+ * Hack TSEC 3 and 4 IO voltages.
+ */
+ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & 0x0f) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8548 uses "new" 15-16 style addressing.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ } },
+ { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+ pci_mpc85xx_init(&hose);
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/cds/mpc8548cds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/cds/mpc8548cds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <ioports.h>
#include <spd.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
void sdram_init(void);
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
int board_early_init_f (void)
{
return 0;
#endif
dram_size = spd_sdram();
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
If anyone finds anything wrong with the stuff above, I would appreciate
an email about it.
-Murray Jensen <Murray.Jensen@cmst.csiro.au>
+Murray Jensen <Murray.Jensen@csiro.au>
21-Aug-00
debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
totlen += nand_probe (CFG_NAND1_BASE);
- printf ("%4lu MB\n", totlen >>20);
+ printf ("%3lu MB\n", totlen >>20);
}
#endif
# MA 02111-1307 USA
#
+# Reserve 256 kB for Monitor
TEXT_BASE = 0xFFFC0000
+
+# Reserve 320 kB for Monitor
+#TEXT_BASE = 0xFFFB0000
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-#define BOOT_SMALL_FLASH_VAL 4
-#define FLASH_ONBD_N_VAL 2
-#define FLASH_SRAM_SEL_VAL 1
-
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
- {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
- {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
- {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
- {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
- {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
- {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
- {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
- {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t *info);
-#endif
-
-#ifdef CONFIG_ADCIOP
-#define ADDR0 0x0aa9
-#define ADDR1 0x0556
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_CPCI405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned short
-#endif
-
-#ifdef CONFIG_WALNUT405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_EBONY
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void) {
- unsigned long total_b = 0;
- unsigned long size_b[CFG_MAX_FLASH_BANKS];
- unsigned char * fpga_base = (unsigned char *)CFG_FPGA_BASE;
- unsigned char switch_status;
- unsigned short index = 0;
- int i;
-
-
- /* read FPGA base register FPGA_REG0 */
- switch_status = *fpga_base;
-
- /* check the bitmap of switch status */
- if (switch_status & BOOT_SMALL_FLASH) {
- index += BOOT_SMALL_FLASH_VAL;
- }
- if (switch_status & FLASH_ONBD_N) {
- index += FLASH_ONBD_N_VAL;
- }
- if (switch_status & FLASH_SRAM_SEL) {
- index += FLASH_SRAM_SEL_VAL;
- }
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0) {
- continue;
- }
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size(
- (vu_long *)flash_addr_table[index][i], &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i]<<20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040) ||
- (info->flash_id == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-#endif /* 0 */
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " "
- );
- }
- printf ("\n");
- return;
- }
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
- static ulong flash_get_size (vu_long *addr, flash_info_t *info)
- {
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
-
- /* Write auto select command: read Manufacturer ID */
- udelay(10000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- udelay(1000);
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- udelay(1000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
- udelay(1000);
-
-#ifdef CONFIG_ADCIOP
- value = addr2[2];
-#else
- value = addr2[0];
-#endif
-
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (FLASH_WORD_SIZE)STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- debug ("\ndev_code=%x\n", value);
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_F016D:
- info->flash_id += FLASH_AMD016;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
- case (FLASH_WORD_SIZE)STM_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- case (FLASH_WORD_SIZE)SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040) ||
- (info->flash_id == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr2[4] & 1;
-#else
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
-#endif
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile unsigned char *)info->start[0];
- addr2[ADDR0] = 0xAA;
- addr2[ADDR1] = 0x55;
- addr2[ADDR0] = 0xF0; /* reset bank */
-#else
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif
-#else /* test-only */
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif /* test-only */
- }
-
- return (info->size);
- }
-
- int wait_for_DQ7(flash_info_t *info, int sect)
- {
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
- }
-
-/*-----------------------------------------------------------------------
- */
-
- int flash_erase (flash_info_t *info, int s_first, int s_last)
- {
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7(info, l_sect);
-
- DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
- }
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
- int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
- {
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
- }
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
- static int write_word (flash_info_t * info, ulong dest, ulong data)
- {
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
- }
-
-/*-----------------------------------------------------------------------
- */
*/
#include <config.h>
+#include <asm/processor.h>
#include <74xx_7xx.h>
#include <mpc106.h>
#include <version.h>
#include <pci.h>
#include <mpc106.h>
+#include <asm/processor.h>
/* defines L2CR register for MPC750 */
*/
#include <config.h>
+#include <asm/processor.h>
#include <version.h>
#include <mpc106.h>
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EP82xx series boards by Embedded Planet
+#
+
+TEXT_BASE = 0xFFF00000
--- /dev/null
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP8248 boards.
+ * Tested on EP8248E.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
+ /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
+ /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
+ /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
+ /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
+ /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
+ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
+ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
+ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
+ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
+ /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
+ /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
+ /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
+ /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
+ /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
+ /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
+ /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
+ /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
+ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
+ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
+ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
+ /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
+ /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
+ /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
+ /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
+ },
+
+ /* Port B */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
+ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
+ /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */
+ /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */
+ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
+ /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */
+ /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
+ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
+ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+ /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
+ /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
+ /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
+ /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
+ /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
+ /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
+ /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
+ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
+ /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ }
+};
+
+int board_early_init_f (void)
+{
+ vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+ bcsr[4] |= 0x30; /* Turn the LEDs off */
+
+#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
+ bcsr[6] |= 0x10;
+#endif
+#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
+ bcsr[7] |= 0x10;
+#endif
+
+#if CFG_FCC1
+ bcsr[8] |= 0xC0;
+#endif /* CFG_FCC1 */
+#if CFG_FCC2
+ bcsr[8] |= 0x30;
+#endif /* CFG_FCC2 */
+
+ return 0;
+}
+
+long int initdram(int board_type)
+{
+ vu_char *bcsr = (vu_char *)CFG_BCSR;
+ long int msize = 16L << (bcsr[2] & 3);
+
+#ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+ uchar c = 0xFF;
+ uint psdmr = CFG_PSDMR;
+ int i;
+
+ immap->im_siu_conf.sc_ppc_acr = 0x02;
+ immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+ immap->im_siu_conf.sc_tescr1 = 0x00004000;
+
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ /* Initialise 60x bus SDRAM */
+ memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_or1 = CFG_SDRAM_OR;
+ memctl->memc_br1 = CFG_SDRAM_BR;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+ *ramaddr = c;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
+ *ramaddr = c;
+ memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
+ *ramaddr = c;
+#endif /* !CFG_RAMBOOT */
+
+ /* Return total 60x bus SDRAM size */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+ vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+ puts("Board: ");
+ switch (bcsr[0]) {
+ case 0x0C:
+ printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
+ break;
+ default:
+ printf("unknown: ID=%02X\n", bcsr[0]);
+ }
+
+ return 0;
+}
/*
- * (C) Copyright 2002
+ * (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*/
OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
.plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- ppc/vsprintf.o (.text)
- ppc/crc32.o (.text)
- ppc/extable.o (.text)
-
- common/environment.o(.text)
-
+ cpu/mpc8260/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
+ . = ALIGN(16);
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_FIXUP_TABLE_ = .;
*(.fixup)
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
_end = . ;
PROVIDE (end = .);
}
+ENTRY(_start)
}
+int misc_init_r (void)
+{
+ unsigned long cntrl0Reg;
+
+ /*
+ * Setup UART1 handshaking: use CTS instead of DSR
+ */
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
+ return (0);
+}
+
+
/*
* Check Board Identity:
*/
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
+ value = in32(GPIO0_IR) & 0x00100200; /* get config bits */
/*
* Restore GPIO settings
mtdcr(cntrl0, cntrl0Reg);
switch (value) {
- case 0x00180000:
- /* CS2==1 && CS3==1 -> version 1.0 and 1.1 */
+ case 0x00100200:
+ /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
return 1;
- case 0x00080000:
- /* CS2==0 && CS3==1 -> version 1.2 */
+ case 0x00000200:
+ /* CS2==0 && IRQ5==1 -> version 1.2 */
return 2;
+ case 0x00000000:
+ /* CS2==0 && IRQ5==0 -> version 1.3 */
+ return 3;
#if 0 /* not yet manufactured ! */
case 0x00100000:
- /* CS2==1 && CS3==0 -> version 1.3 */
- return 3;
- case 0x00000000:
- /* CS2==0 && CS3==0 -> version 1.4 */
+ /* CS2==1 && IRQ5==0 -> version 1.4 */
return 4;
#endif
default:
}
/* ------------------------------------------------------------------------- */
+int wpeeprom(int wp)
+{
+ int wp_state = wp;
+ volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
+
+ if (wp == 1) {
+ *uart1_mcr &= ~0x02;
+ } else if (wp == 0) {
+ *uart1_mcr |= 0x02;
+ } else {
+ if (*uart1_mcr & 0x02) {
+ wp_state = 0;
+ } else {
+ wp_state = 1;
+ }
+ }
+ return wp_state;
+}
+
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int wp = -1;
+ if (argc >= 2) {
+ if (argv[1][0] == '1') {
+ wp = 1;
+ } else if (argv[1][0] == '0') {
+ wp = 0;
+ }
+ }
+
+ wp = wpeeprom(wp);
+ printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
+ return 0;
+}
+
+U_BOOT_CMD(
+ wpeeprom, 2, 1, do_wpeeprom,
+ "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n",
+ "wpeeprom\n"
+ " - check I2C EEPROM write protection state\n"
+ "wpeeprom 1\n"
+ " - enable I2C EEPROM write protection\n"
+ "wpeeprom 0\n"
+ " - disable I2C EEPROM write protection\n"
+ );
- 0x1f,0x8b,0x08,0x08,0x72,0xdc,0x88,0x41,0x00,0x03,0x77,0x75,0x68,0x34,0x30,0x35,
- 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0xec,0xbd,0x7b,0x78,0x14,0xd7,
- 0x95,0x2f,0xba,0x7a,0x57,0x21,0x4a,0xdd,0x2d,0x75,0x59,0x40,0x46,0x31,0x36,0x94,
- 0x5a,0x82,0x34,0x72,0xab,0x69,0x1a,0x22,0xcb,0xb2,0xdc,0x2a,0x04,0x93,0x28,0x40,
- 0x82,0xc6,0xc9,0x9c,0xcf,0x33,0xc9,0x75,0xda,0x0e,0xc9,0x61,0x7c,0x70,0x8e,0xe2,
- 0xc9,0xbd,0x87,0x38,0x1e,0xa7,0xf4,0x30,0x88,0xc7,0x98,0x36,0x78,0x12,0x9c,0xf8,
- 0x66,0x8a,0x47,0x62,0xec,0x90,0x9c,0x06,0xd9,0x46,0x18,0xc6,0x2e,0xb0,0xe2,0x88,
- 0x87,0x41,0x71,0x3c,0x19,0x6c,0x13,0xd2,0x38,0xb2,0x2d,0x63,0x19,0xcb,0x98,0x38,
- 0x92,0x85,0xd1,0x5d,0x7b,0xd7,0xa3,0xab,0xaa,0xab,0x05,0x99,0xf9,0xee,0xfd,0xe6,
- 0xfb,0xee,0x68,0xfe,0x98,0x9d,0xaa,0x4d,0xb9,0xf6,0xea,0x5d,0x6b,0xfd,0xf6,0x6f,
- 0xfd,0xf6,0xda,0x50,0x1c,0x1a,0xd6,0xff,0x0f,0xc0,0x77,0x07,0x88,0xff,0xeb,0xff,
- 0x5c,0xb9,0x20,0xfe,0xe9,0xaf,0xce,0xfb,0x6a,0x3c,0x1e,0xfb,0xe6,0xd7,0x56,0xc0,
- 0x9d,0x10,0x48,0xfc,0xfd,0xa7,0xe3,0x5f,0xff,0xf6,0xb7,0xe6,0x2d,0x58,0x00,0x5f,
- 0xc3,0xff,0x15,0x8f,0x2f,0x98,0x3b,0x6f,0xde,0xdc,0xf8,0x7c,0x58,0x01,0xc5,0xf3,
- 0x16,0xd4,0x27,0x6a,0xeb,0xe7,0xc5,0xe1,0xeb,0xe0,0x9b,0xbf,0x73,0x1c,0xff,0x9e,
- 0x78,0xe4,0xaf,0xbf,0x11,0x07,0xc5,0x07,0x00,0x93,0xe3,0xbe,0x14,0xfd,0xff,0x81,
- 0xb8,0x4f,0xf2,0x81,0xd2,0x58,0x13,0x07,0x8d,0xfe,0x6f,0x30,0xee,0x17,0xc7,0x41,
- 0xb2,0xff,0x6f,0x5f,0x1c,0x64,0x68,0x01,0x79,0x23,0x94,0xc5,0xe1,0xca,0x7f,0x32,
- 0xaf,0x98,0xcd,0x3f,0xb3,0xff,0xf8,0x51,0xa5,0x60,0xaf,0xdc,0x5f,0xe3,0x05,0xd5,
- 0x6c,0x92,0xab,0x78,0xbe,0x4f,0x06,0xeb,0xf9,0xaf,0x5e,0xd5,0xf3,0x3f,0x34,0x9f,
- 0xff,0xe7,0xf6,0x87,0xb2,0xab,0xe8,0x0e,0xc0,0x5b,0xef,0x43,0xfb,0x13,0xc0,0xf7,
- 0x8b,0x80,0x1f,0x88,0x02,0xaa,0x57,0xa3,0xb1,0xd7,0xfc,0x87,0xda,0x03,0x97,0x61,
- 0x5c,0x49,0x0e,0x87,0x56,0x72,0xe7,0xe1,0x0f,0xd0,0xd8,0x55,0xaa,0x71,0xf1,0x78,
- 0x2f,0x24,0x5a,0x42,0x23,0xdc,0x05,0x72,0x5c,0xf9,0x74,0x3c,0x78,0x8a,0x8b,0x43,
- 0xab,0xd9,0xbf,0xfc,0x9b,0x70,0x40,0x89,0xf5,0x05,0x76,0x71,0x31,0x78,0x8f,0x24,
- 0xd4,0x60,0x4f,0x59,0x0c,0xc6,0x7a,0xab,0xb7,0x06,0x32,0xed,0xaf,0xf3,0xeb,0x94,
- 0xb0,0x22,0x6c,0x26,0x12,0x6f,0x5a,0xb1,0x6f,0xd2,0x46,0xa1,0x1b,0x56,0x69,0x01,
- 0x95,0x1c,0x87,0x6e,0x2e,0xd2,0x1b,0xf0,0x11,0x7c,0xdb,0xbf,0xac,0x6a,0x09,0x24,
- 0xc8,0x20,0x74,0xc1,0x6c,0x41,0x48,0xb7,0x13,0x90,0xcc,0xe7,0xf3,0xbb,0xe1,0x00,
- 0x94,0x1e,0x0a,0xec,0x6a,0x5f,0x85,0x8d,0xb0,0x56,0x9e,0xf9,0x4c,0x14,0x1b,0x31,
- 0x25,0x90,0xc1,0xfe,0xeb,0x00,0x9f,0x9f,0x26,0x71,0xde,0x7c,0x9f,0xbf,0x9a,0x36,
- 0x04,0x63,0x90,0xd4,0x96,0x47,0x38,0x6c,0xf0,0x37,0x2b,0x21,0x7c,0x7f,0x08,0xc2,
- 0x5f,0xc8,0x9b,0x32,0x8b,0x34,0x38,0xac,0xd4,0xca,0x41,0x89,0x13,0x17,0x9b,0xfd,
- 0x55,0xdf,0x41,0x18,0x87,0xc6,0x43,0x81,0x2c,0x77,0x10,0xde,0x83,0xef,0x2a,0xcb,
- 0x87,0x2b,0x87,0x84,0x71,0xc0,0x7f,0x38,0xcc,0x8d,0xc0,0x65,0xb5,0x51,0x0b,0x65,
- 0x03,0x83,0x90,0x32,0xfa,0xf7,0x8b,0xbb,0xd9,0xf3,0x43,0x3b,0x3b,0xa2,0x53,0xc7,
- 0xa0,0xfe,0x78,0xa9,0xc2,0x29,0xd0,0x27,0x24,0x52,0xbb,0x33,0xdc,0x80,0x82,0xb7,
- 0xe4,0xa0,0xca,0xc5,0x79,0xc9,0x1a,0x6f,0x94,0xc7,0xb7,0xd5,0x02,0x4f,0x90,0x98,
- 0xfc,0x9c,0x24,0x0d,0x0b,0xf5,0x24,0x0a,0xbf,0xc9,0xd6,0xb6,0x95,0x64,0xc8,0x10,
- 0x1c,0x90,0xa2,0x9a,0xa0,0x92,0xbd,0x38,0xfb,0xcd,0xf1,0x2e,0x83,0x6e,0x88,0x6a,
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+ 0x83,0x8b,0xf1,0x25,0xfe,0x3d,0xef,0x67,0xea,0xf8,0xbf,0x38,0x36,0xfc,0xb0,0x72,
+ 0x7b,0xf9,0xa5,0xe4,0x3e,0x61,0x7e,0xb3,0xfc,0xd2,0xe8,0xbe,0x89,0xb1,0x07,0xf3,
+ 0xb7,0x7b,0xde,0x4f,0xee,0x1b,0x1e,0x5b,0x17,0xe6,0x90,0x1a,0xcf,0xe0,0xdb,0xe3,
+ 0x3b,0x7f,0xfc,0xed,0xd3,0x27,0x5b,0xd2,0xdc,0x79,0xfa,0xc9,0xd6,0xe0,0xa7,0xc7,
+ 0x37,0xae,0xed,0x6c,0x6e,0x6f,0x0d,0x5e,0x3e,0xbe,0x23,0xcc,0x36,0xfc,0x07,0x7a,
+ 0xf5,0x46,0xf2,0xe0,0xf0,0x68,0x65,0x7e,0x7a,0x68,0xeb,0x4b,0xb7,0xb2,0x3b,0x95,
+ 0x7f,0xfc,0xe0,0xd5,0x9f,0x8f,0xbe,0xfd,0xd1,0x68,0xe5,0xfa,0xf6,0xd0,0xce,0x68,
+ 0xef,0x47,0xa3,0x4f,0xaf,0x6f,0xaa,0xfd,0x87,0x2e,0x8f,0x6f,0x5c,0xbb,0xb3,0xf9,
+ 0x64,0x6b,0xa8,0x1e,0xc6,0xf6,0x90,0x0c,0x6c,0xf3,0x13,0xec,0x3f,0xbe,0x21,0x23,
+ 0x54,0xfb,0x77,0x1f,0x28,0x6c,0xcc,0x7f,0x63,0xf3,0xea,0xd9,0x41,0xf1,0xc1,0x5f,
+ 0xe3,0x07,0xd1,0xfc,0xa5,0xed,0x4e,0xf9,0xc9,0x56,0xb7,0x2b,0xcd,0xdf,0xbe,0xbf,
+ 0x2b,0xa0,0xec,0x0c,0x5b,0xb2,0x7a,0x5b,0x93,0xb5,0xae,0x99,0xcc,0x12,0xbc,0x49,
+ 0x5b,0x56,0x40,0xb6,0xd0,0xe4,0x4a,0x0c,0x8d,0xdf,0x4b,0x89,0x3a,0x9e,0x38,0xff,
+ 0x05,0x1f,0xba,0x20,0xb0,0x50,0x80,0xa2,0x7d,0x57,0x24,0x6a,0x34,0x98,0xa8,0x4f,
+ 0xc8,0x16,0x43,0xed,0x1f,0x23,0x81,0xc8,0xcf,0x2e,0x34,0xf9,0x70,0x95,0x78,0x20,
+ 0x8d,0xe4,0xc3,0xa0,0x75,0x77,0x7e,0x46,0xe6,0x11,0x90,0x16,0x2b,0x21,0xb6,0xc9,
+ 0xfd,0xb0,0xc4,0x43,0x6c,0x73,0x11,0xe4,0xce,0x72,0xc1,0x6f,0x27,0xd4,0xfe,0x66,
+ 0xee,0x62,0x32,0xc5,0xb3,0x06,0xcc,0x4d,0xbf,0x0c,0x1d,0xe5,0x3d,0xe1,0xc4,0xe8,
+ 0xe0,0x47,0x9b,0xa6,0xc7,0x56,0xe3,0x01,0x08,0xea,0x7c,0x88,0xd4,0xe5,0x5a,0x2a,
+ 0x1f,0x2a,0x26,0x52,0x12,0xb1,0x10,0x97,0x55,0x20,0xd6,0x97,0xfc,0x5a,0xa3,0x55,
+ 0xa1,0xbd,0x04,0xf9,0x30,0xb0,0x16,0xe9,0x41,0x92,0xe4,0xc3,0xc5,0x5d,0xcf,0xac,
+ 0x0e,0xd1,0xb1,0xd2,0x97,0xab,0xf9,0x0f,0xec,0x3e,0x7a,0xba,0xdc,0x7a,0x93,0xfe,
+ 0xd2,0xee,0x82,0xb1,0x52,0x6b,0x35,0xf7,0x81,0xfd,0x75,0x2a,0xcd,0x9c,0xf2,0x76,
+ 0xdc,0xac,0xb5,0x40,0x1b,0x38,0x0f,0x8c,0x8a,0x24,0x1d,0xa7,0x06,0xbf,0x92,0xbb,
+ 0x8d,0x53,0x33,0xfc,0xc8,0xb0,0xe8,0x03,0x35,0x8a,0xc9,0x17,0x2f,0x60,0x02,0xde,
+ 0x01,0x59,0xec,0x31,0x1c,0xa4,0x00,0xeb,0x3c,0x6a,0x92,0xb0,0xcc,0xa5,0xc8,0x8c,
+ 0x7e,0x74,0x7e,0xf1,0xf8,0x8e,0x5b,0x1e,0x16,0xeb,0x22,0x71,0x58,0xf2,0x81,0x1b,
+ 0x35,0xc5,0x93,0xbb,0x39,0xab,0x8b,0x9a,0xa5,0x18,0x1e,0xda,0xd5,0xbf,0x3e,0xec,
+ 0x32,0xd1,0xbb,0x98,0xf1,0x6d,0x9e,0x68,0x80,0x09,0x0d,0x4d,0x3b,0x6f,0xf6,0xb7,
+ 0x08,0x8b,0x05,0xe2,0x8b,0x32,0x82,0xcc,0x84,0xc1,0xd1,0xbb,0x0f,0xd3,0xa2,0x45,
+ 0xfc,0xea,0xf1,0x34,0xdc,0x80,0x83,0x1e,0x89,0x9e,0x28,0xb0,0x3a,0x1f,0x66,0x0b,
+ 0xb8,0xdf,0x49,0x50,0x2c,0xe0,0xb6,0xe8,0xff,0x58,0x80,0x62,0x65,0xb5,0x47,0x1e,
+ 0x32,0x2b,0xb5,0xe6,0xef,0x43,0x32,0xf8,0x77,0x3e,0xe4,0xac,0x81,0x85,0x4d,0xd3,
+ 0xfc,0x7b,0x11,0x0c,0xd3,0xa3,0x2f,0x21,0xcd,0x9a,0xad,0x1b,0xf8,0x90,0xd6,0xcd,
+ 0x6a,0xd8,0x92,0xb2,0x6a,0x56,0x14,0x0f,0x13,0xfc,0xe6,0x8d,0xe0,0x4d,0x17,0x06,
+ 0x90,0xdf,0x7e,0x28,0x2e,0xd3,0x93,0xd7,0xcb,0xf0,0xd0,0x04,0xb5,0x79,0x14,0x0f,
+ 0xf9,0x2c,0x3e,0xf4,0x9f,0x69,0xa9,0x35,0x2b,0xda,0x22,0x19,0x0e,0xcf,0x2f,0x78,
+ 0x38,0x34,0xb6,0xb8,0xf0,0xba,0x11,0x2d,0xb8,0xbf,0x47,0xf3,0x53,0xc4,0x53,0x24,
+ 0x0e,0xe4,0xd1,0xd7,0x8d,0x8d,0x37,0xb5,0x6e,0x1a,0x87,0x86,0x9b,0xfb,0x69,0x01,
+ 0x07,0x3c,0xc3,0x9d,0xc0,0x70,0x89,0x58,0x17,0x56,0x40,0x85,0xc9,0x3c,0x63,0xa2,
+ 0xe9,0x53,0x00,0x31,0xf3,0x4d,0x9c,0x05,0x8e,0x88,0x96,0xd5,0x6b,0xa5,0x72,0xc3,
+ 0x84,0x2d,0xa0,0xc4,0x33,0x85,0x34,0x58,0x0e,0x3a,0x4f,0xb9,0x53,0x08,0x8a,0x7f,
+ 0x0a,0xd2,0xae,0xd1,0x00,0xc5,0x54,0x93,0x18,0x15,0x5e,0x25,0x82,0xdf,0x3a,0x82,
+ 0xa3,0x96,0xb3,0x26,0xcd,0x9b,0x56,0xfb,0x5a,0xe2,0xbb,0x04,0x5b,0x8a,0xce,0x3a,
+ 0x96,0x96,0x1d,0xec,0xe8,0xa9,0x43,0xca,0xf5,0x92,0x84,0x73,0x81,0x77,0x04,0xbd,
+ 0x2e,0x59,0x8b,0x5d,0xe0,0x4b,0x68,0x92,0x6b,0x20,0x4c,0x1b,0x9a,0xd8,0x85,0x92,
+ 0x68,0x51,0xf2,0x49,0x31,0x3f,0x22,0xe9,0xf1,0x0d,0xd7,0x8c,0xf8,0x90,0x0e,0x94,
+ 0xcf,0x04,0x6d,0xa7,0xd2,0x0f,0xc9,0x85,0x2b,0x02,0x1d,0xed,0xd5,0x66,0x3c,0x0c,
+ 0xa1,0x57,0xa6,0x1d,0xe4,0x73,0x34,0xa3,0x21,0x16,0xce,0xf0,0xdd,0x15,0xab,0x12,
+ 0x0f,0xce,0x64,0x4c,0x32,0x41,0x62,0x11,0x6e,0xa1,0xf9,0x4a,0x80,0x69,0xe7,0x1d,
+ 0x2a,0x5b,0xd0,0x84,0x87,0x5c,0x75,0x3f,0xcd,0x07,0x70,0x89,0xec,0x87,0xec,0x2c,
+ 0x3c,0x2a,0x1f,0x21,0x07,0x20,0xcb,0xed,0x47,0xf4,0x12,0x9a,0xa3,0x68,0x7a,0x2e,
+ 0x81,0x34,0x11,0x1f,0x32,0x32,0x01,0xde,0x32,0xf2,0x21,0xc6,0xc3,0x3d,0xde,0xee,
+ 0xc7,0x10,0x0b,0xf9,0xb4,0xc0,0xc2,0x02,0x99,0xe7,0x41,0x68,0xb8,0x12,0x0f,0xce,
+ 0xb7,0x9b,0x72,0xfe,0xfc,0xa4,0x8c,0x34,0x58,0xc5,0x32,0x6a,0xb6,0xdc,0xe0,0xc3,
+ 0xb2,0x98,0x6f,0x82,0x0f,0xd5,0xf5,0x45,0x20,0xe3,0xb4,0x86,0xf3,0xa7,0x64,0x79,
+ 0x79,0x13,0x59,0x8a,0xa1,0xc9,0xa1,0xa1,0xa1,0xc9,0x44,0x3c,0xc6,0x18,0x96,0x94,
+ 0xf7,0x1d,0xdf,0x30,0x61,0x2f,0xae,0x23,0xa7,0x4a,0x52,0x24,0xeb,0x15,0x6b,0xd8,
+ 0x82,0x06,0xea,0x86,0x91,0x28,0x1e,0x93,0xfa,0xb6,0xe4,0x43,0xce,0xba,0x30,0xdb,
+ 0xc4,0x91,0x0f,0x59,0x1d,0x0b,0x9b,0x06,0x94,0xf5,0x35,0xec,0xb5,0x96,0x78,0xd5,
+ 0x33,0x17,0x63,0x5d,0x48,0x83,0x58,0x62,0x0b,0x3e,0x9c,0x43,0x12,0xdb,0x3b,0x87,
+ 0x09,0xa3,0x22,0xf8,0x70,0x0e,0x94,0xf5,0xc5,0xae,0xca,0x24,0x83,0x39,0xb7,0xec,
+ 0x49,0x53,0xc2,0xfc,0x63,0xbb,0xf0,0x6d,0x62,0xf3,0x3f,0x04,0x16,0xa2,0x4e,0xac,
+ 0x9d,0x37,0xd7,0x17,0xf6,0xe7,0xd3,0xd0,0x0e,0x89,0x8c,0x59,0xe1,0x01,0xdc,0x88,
+ 0x63,0x46,0xae,0xc0,0x4c,0x1f,0xe6,0x9f,0x18,0xa9,0xac,0x61,0x8e,0x46,0x53,0x52,
+ 0xd7,0x57,0xc0,0x8e,0xc0,0x7e,0x88,0xcf,0xd6,0xaa,0xfc,0x08,0xd9,0x4f,0xb2,0xbc,
+ 0xf2,0x88,0x9e,0x6f,0x11,0x77,0x90,0x3f,0x9a,0x3e,0x92,0xdc,0x1f,0xc7,0x3b,0xc8,
+ 0x9b,0xe3,0x53,0xc4,0xf2,0xfb,0x9b,0xc1,0xfe,0x53,0xf1,0x05,0xf8,0x05,0xf8,0x2c,
+ 0x65,0xc5,0x29,0x7c,0x88,0xb9,0x53,0x9a,0x95,0x46,0x8b,0x7a,0xbf,0x28,0x0c,0xb0,
+ 0x96,0x62,0x7c,0xa2,0xb2,0xc0,0xfb,0x59,0x4b,0x26,0xee,0xc0,0x3d,0xda,0x5f,0x48,
+ 0x15,0x43,0xc3,0x52,0x13,0x71,0xc7,0x5a,0x25,0x56,0x33,0x9e,0x2c,0x0d,0x56,0x5c,
+ 0x7f,0xc4,0x85,0x1f,0x95,0x99,0x30,0xa6,0x7d,0x2d,0x6c,0x49,0xd9,0xd7,0x21,0x58,
+ 0x29,0x08,0xc3,0x2d,0x65,0x7c,0xa0,0x1b,0xb3,0xb4,0xfa,0xf2,0xe4,0xee,0x67,0xbc,
+ 0xd7,0x8a,0xd6,0x57,0xa1,0xc1,0x87,0x3c,0x77,0x4e,0x98,0x4e,0xeb,0x63,0xe4,0x43,
+ 0x4b,0x60,0xe1,0x22,0x9c,0xb3,0xcd,0x90,0x0f,0x9b,0xe3,0x99,0x67,0xb9,0xd7,0xed,
+ 0xb4,0x93,0xcf,0xf3,0x13,0xd3,0x45,0xdb,0x31,0xf2,0xc4,0x62,0x0c,0xd3,0x8e,0x81,
+ 0xf9,0x27,0x07,0xd8,0x42,0xf3,0x40,0xa2,0xf5,0x8e,0xf3,0x21,0xac,0x8c,0xbb,0x64,
+ 0xe6,0xb3,0x66,0x0d,0x39,0x37,0x41,0x14,0x31,0xc4,0xac,0xd7,0x0b,0x25,0x88,0x78,
+ 0x5e,0xf0,0x21,0x87,0x2a,0x43,0x1a,0xa4,0xb1,0x32,0x43,0x50,0xa4,0x2a,0x28,0x86,
+ 0x26,0xea,0xcd,0xf2,0xaf,0x91,0x49,0x46,0x1f,0x9c,0x7d,0xc5,0x6d,0x49,0xb4,0xb1,
+ 0xf5,0x07,0x9d,0x87,0x53,0x2d,0xf1,0x49,0x34,0x03,0x87,0x8d,0xd7,0xea,0x46,0xc9,
+ 0x3f,0x78,0xbd,0x3d,0x17,0x33,0x4b,0xc8,0x87,0xef,0xfe,0xbe,0x47,0xec,0xfe,0x7b,
+ 0xbc,0x74,0x2d,0x31,0x23,0x79,0xa0,0xbd,0x01,0x06,0x4a,0xfe,0x01,0xf8,0xda,0x5b,
+ 0x23,0x0f,0xdf,0xbd,0xbd,0xfc,0x9d,0x1b,0x2f,0xbe,0x35,0x26,0xf8,0xf0,0xfd,0x3a,
+ 0x1f,0x2e,0x47,0x7c,0xb8,0xeb,0x19,0xf7,0x50,0xc4,0x87,0xc7,0x05,0x1f,0xee,0xd4,
+ 0xf9,0xf0,0x69,0xc4,0x87,0xbb,0x78,0xec,0xf3,0xea,0xab,0x02,0x0b,0xff,0x5a,0xd9,
+ 0xd9,0x1e,0xda,0xaa,0x83,0x22,0x12,0xe3,0x73,0xf8,0x50,0xfe,0xf4,0xbf,0x6f,0x62,
+ 0xff,0x4f,0x1b,0xa0,0x78,0xf9,0x79,0x7c,0x38,0xd8,0xe0,0xc3,0xee,0x03,0xe3,0x1b,
+ 0xf3,0xfd,0x9b,0x4f,0x1e,0x0f,0x5d,0x7a,0xa6,0xff,0xe3,0x2f,0x1e,0xbd,0x0f,0x1e,
+ 0x11,0x2f,0x28,0x7c,0xc8,0xa6,0xbe,0xf8,0x59,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,
+ 0xb4,0xb4,0xb4,0xb4,0xfe,0xdf,0x25,0x6b,0x07,0xaa,0x6b,0x07,0x2d,0x2d,0x2d,0x2d,
+ 0x2d,0x2d,0x2d,0x2d,0x2d,0x2d,0xad,0xe7,0x4b,0xd6,0x0e,0x09,0x5d,0x3b,0x68,0x69,
+ 0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x3d,0x5f,0xb2,0x76,0x30,0x65,0xed,
+ 0xf0,0xbf,0x0e,0x45,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0xeb,0xbf,
+ 0x28,0x5f,0xfc,0xd1,0x24,0xf8,0xe7,0x79,0x1f,0xb8,0xf8,0xce,0x53,0xdc,0x07,0xf6,
+ 0xb9,0xdf,0x27,0xd4,0x3f,0x6b,0xf8,0x50,0x25,0xd1,0x39,0x1f,0x9f,0x7e,0xb6,0xdf,
+ 0xbf,0x00,0x34,0x34,0xbf,0x69,0xee,0x33,0x01,0x00,
#define CFG_DIRECT_FLASH_TFTP
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
-#define CFG_JFFS2_FIRST_SECTOR 4
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
+#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
+*/
+
#define CFG_JFFS2_SORT_FRAGMENTS
#endif /* CFG_CMD_JFFS2 */
*addr = FLASH_CMD_RESET;
return (0);
}
-
-/*-----------------------------------------------------------------------
- * Support for flash file system (JFFS2)
- *
- * We use custom partition info function because we have to fit the
- * file system image between first sector (containing hard reset
- * configuration word) and the sector containing U-Boot image. Standard
- * partition info function does not allow for last sector specification
- * and assumes that the file system occupies flash bank up to and
- * including bank's last sector.
- */
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
-#error TODO
-
-#ifndef CFG_JFFS2_FIRST_SECTOR
-#define CFG_JFFS2_FIRST_SECTOR 0
-#endif
-#ifndef CFG_JFFS2_FIRST_BANK
-#define CFG_JFFS2_FIRST_BANK 0
-#endif
-#ifndef CFG_JFFS2_NUM_BANKS
-#define CFG_JFFS2_NUM_BANKS 1
-#endif
-#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
-
-#include <jffs2/jffs2.h>
-
-static struct part_info partition;
-
-struct part_info *jffs2_part_info(int part_num)
-{
- int i;
-
- if (part_num == 0) {
- if (partition.usr_priv == 0) {
- partition.offset =
- (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
- for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
- partition.size += flash_info[i].size;
- partition.size -=
- flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
- flash_info[CFG_JFFS2_FIRST_BANK].start[0];
-#ifdef CFG_JFFS2_LAST_SECTOR
- i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
- partition.size -=
- flash_info[CFG_JFFS2_LAST_BANK].start[i] -
- flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
-#endif
-
- partition.usr_priv = (void *)1;
- }
- return &partition;
- }
- return 0;
-}
-
-#endif /* JFFS2 */
}
static unsigned long UPMATable[] = {
- 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, //Words 0 to 3
- 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, //Words 4 to 7
- 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 8 to 11
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 12 to 15
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 16 to 19
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
- 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, //Words 24 to 27
- 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 28 to 31
- 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, //Words 32 to 35
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 36 to 39
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
- 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 48 to 51
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
- 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 //Words 60 to 63
+ 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
+ 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
+ 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
+ 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
+ 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
+ 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
+ 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
+ 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
};
int board_early_init_f (void)
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
return 0;
}
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
+#define GPIO_WKUP_7 0x80000000UL
#define GPIO_PSC3_9 0x04000000UL
int misc_init_f (void)
/* Initialize GPIO output pins.
*/
- /* Configure GPT as GPIO output */
+ /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
*(vu_long *)MPC5XXX_GPT0_ENABLE =
*(vu_long *)MPC5XXX_GPT1_ENABLE =
*(vu_long *)MPC5XXX_GPT2_ENABLE =
*(vu_long *)MPC5XXX_GPT3_ENABLE =
*(vu_long *)MPC5XXX_GPT4_ENABLE =
- *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24;
+ *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
/* Configure GPT7 as PWM timer, 1kHz, no ints. */
*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
+ /* Set LR mirror bit because it is low-active */
+ *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7;
/*
* Reset Coral-P graphics controller
*/
#include <common.h>
#include <asm/arch/pxa-regs.h>
-#if defined CFG_JFFS_CUSTOM_PART
-#include <jffs2/jffs2.h>
-#endif
-
/* Debugging macros ------------------------------------------------------ */
#undef FLASH_DEBUG
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-#if defined CFG_JFFS_CUSTOM_PART
-
-/**
- * jffs2_part_info - get information about a JFFS2 partition
- *
- * @part_num: number of the partition you want to get info about
- * @return: struct part_info* in case of success, 0 if failure
- */
-
-static struct part_info part;
-static int current_part = -1;
-
-#ifdef CONFIG_MTD_INNOKOM_16MB
-#ifdef CONFIG_MTD_INNOKOM_64MB
-#error Please define only one CONFIG_MTD_INNOKOM_XXMB option.
-#endif
-struct part_info* jffs2_part_info(int part_num) {
- void *jffs2_priv_saved = part.jffs2_priv;
-
- PRINTK2("jffs2_part_info: part_num=%i\n",part_num);
-
- if (current_part == part_num)
- return ∂
-
- /* u-boot partition */
- if(part_num==0){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00000000;
- part.size=256*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* primary OS+firmware partition */
- if(part_num==1){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00040000;
- part.size=768*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* secondary OS+firmware partition */
- if(part_num==2){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00100000;
- part.size=8*1024*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* data partition */
- if(part_num==3){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00900000;
- part.size=7*1024*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- if (current_part == part_num) {
- part.usr_priv = ¤t_part;
- part.jffs2_priv = jffs2_priv_saved;
- return ∂
- }
-
- PRINTK("jffs2_part_info: end of partition table\n");
- return 0;
-}
-#endif /* CONFIG_MTD_INNOKOM_16MB */
-
-#ifdef CONFIG_MTD_INNOKOM_64MB
-#ifdef CONFIG_MTD_INNOKOM_16MB
-#error Please define only one CONFIG_MTD_INNOKOM_XXMB option.
-#endif
-struct part_info* jffs2_part_info(int part_num) {
- void *jffs2_priv_saved = part.jffs2_priv;
-
- PRINTK2("jffs2_part_info: part_num=%i\n",part_num);
-
- if (current_part == part_num)
- return ∂
-
- /* u-boot partition */
- if(part_num==0){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00000000;
- part.size=256*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* primary OS+firmware partition */
- if(part_num==1){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00040000;
- part.size=16*1024*1024-128*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* secondary OS+firmware partition */
- if(part_num==2){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x01020000;
- part.size=16*1024*1024-128*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* data partition */
- if(part_num==3){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x02000000;
- part.size=32*1024*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
- PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- if (current_part == part_num) {
- part.usr_priv = ¤t_part;
- part.jffs2_priv = jffs2_priv_saved;
- return ∂
- }
-
- PRINTK("jffs2_part_info: end of partition table\n");
- return 0;
-}
-#endif /* CONFIG_MTD_INNOKOM_64MB */
-#endif /* defined CFG_JFFS_CUSTOM_PART */
-
-
/**
* flash_init: - initialize data structures for flash chips
*
***********************************************************************/
int checkboard (void)
{
- puts ("Board: LICCON Konsole LCD2\n");
+ puts ("Board: LICCON Konsole LCD3\n");
return (0);
}
return rc;
}
-
-/*-----------------------------------------------------------------------
- * Support for flash file system (JFFS2)
- *
- * We use custom partition info function because we have to fit the
- * file system image between first sector (containing hard reset
- * configuration word) and the sector containing U-Boot image. Standard
- * partition info function does not allow for last sector specification
- * and assumes that the file system occupies flash bank up to and
- * including bank's last sector.
- */
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
-
-#ifndef CFG_JFFS2_FIRST_SECTOR
-#define CFG_JFFS2_FIRST_SECTOR 0
-#endif
-#ifndef CFG_JFFS2_FIRST_BANK
-#define CFG_JFFS2_FIRST_BANK 0
-#endif
-#ifndef CFG_JFFS2_NUM_BANKS
-#define CFG_JFFS2_NUM_BANKS 1
-#endif
-#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
-
-#include <jffs2/jffs2.h>
-
-static struct part_info partition;
-
-struct part_info *jffs2_part_info(int part_num)
-{
- int i;
-
- if (part_num == 0) {
- if (partition.usr_priv == 0) {
- partition.offset =
- (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
- for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
- partition.size += flash_info[i].size;
- partition.size -=
- flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
- flash_info[CFG_JFFS2_FIRST_BANK].start[0];
-#ifdef CFG_JFFS2_LAST_SECTOR
- i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
- partition.size -=
- flash_info[CFG_JFFS2_LAST_BANK].start[i] -
- flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
-#endif
-
- partition.usr_priv = (void *)1;
- }
- return &partition;
- }
- return 0;
-}
-
-#endif /* JFFS2 */
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC83xxADS
+#
+
+TEXT_BASE = 0xFE700000
--- /dev/null
+/*
+ * Copyright Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+ volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+
+ /* Enable flash write */
+ bcsr[1] &= ~0x01;
+
+ return 0;
+}
+
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram(NULL);
+#else
+ msize = fixed_sdram();
+#endif
+ /*
+ * Initialize SDRAM if it is on local bus.
+ */
+ sdram_init();
+ puts(" DDR RAM: ");
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CFG_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1);
+ ddr_size = ddr_size>>1, ddr_size_log2++) {
+ if (ddr_size & 1) {
+ return -1;
+ }
+ }
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+
+ im->ddr.csbnds[0].csbnds = 0x00100017;
+ im->ddr.csbnds[1].csbnds = 0x0018001f;
+ im->ddr.csbnds[2].csbnds = 0x00000007;
+ im->ddr.csbnds[3].csbnds = 0x0008000f;
+ im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[3] = CFG_DDR_CONFIG;
+ im->ddr.timing_cfg_1 =
+ 3 << TIMING_CFG1_PRETOACT_SHIFT |
+ 7 << TIMING_CFG1_ACTTOPRE_SHIFT |
+ 3 << TIMING_CFG1_ACTTORW_SHIFT |
+ 4 << TIMING_CFG1_CASLAT_SHIFT |
+ 3 << TIMING_CFG1_REFREC_SHIFT |
+ 3 << TIMING_CFG1_WRREC_SHIFT |
+ 2 << TIMING_CFG1_ACTTOACT_SHIFT |
+ 1 << TIMING_CFG1_WRTORD_SHIFT;
+ im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
+ im->ddr.sdram_cfg =
+ SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+ | SDRAM_CFG_2T_EN
+#endif
+ | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+ im->ddr.sdram_mode =
+ 0x2000 << SDRAM_MODE_ESD_SHIFT |
+ 0x0162 << SDRAM_MODE_SD_SHIFT;
+
+ im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
+ 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
+ udelay(200);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ return msize;
+}
+#endif/*!CFG_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+ puts("Board: Freescale MPC8349ADS\n");
+ return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxads_config_table[] = {
+ {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
+ } },
+ {}
+}
+#endif
+
+
+volatile static struct pci_controller hose[] = {
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxads_config_table,
+#endif
+ },
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxads_config_table,
+#endif
+ }
+};
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+
+ pci_mpc83xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+/*
+ * if MPC8349ADS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM) \
+ && defined(CFG_OR2_PRELIM) \
+ && defined(CFG_LBLAWBAR2_PRELIM) \
+ && defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile lbus8349_t *lbc= &immap->lbus;
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+ puts("\n SDRAM on Local Bus: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+ */
+
+ /*setup mtrpt, lsrt and lbcr for LB bus*/
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller Machine Mode Register.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
+
+ lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
+ asm("sync");
+ /*1 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*2 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*3 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*4 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*5 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*6 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*7 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*8 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ /* 0x58636733;mode register write operation */
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+}
+#else
+void
+sdram_init(void)
+{
+ put("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc83xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
#include <asm/immap_85xx.h>
#include <spd.h>
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
dram_size = fixed_sdram ();
#endif
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o flash.o
+#OBJS := $(BOARD).o flash.o $(BOARD)_slave.o
+SOBJS := init.o
+#SOBJS :=
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# gda8540 board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+#TEXT_BASE = 0x1000000
+TEXT_BASE = 0xfff80000
+
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- /dev/null
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+/*
+ * The variable should be in the flash info structure. Since it
+ * is only used in this board specific file it is declared here.
+ * In the future I think an endian flag should be part of the
+ * flash_info_t structure. (Ron Alder)
+ */
+static ulong big_endian = 0;
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt);
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(flash_info_t *info, vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* set the default sector offset */
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+ break;
+ case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+ break;
+ case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+ break;
+ case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+ /* only deal with 16 bit and 32 bit port width, 16bit chip */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value,va,vb,vc,vd;
+ ulong base = (ulong)addr;
+ ulong sector_offset;
+
+#ifdef DEBUG
+ printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+ udelay(20);
+ asm("sync");
+
+#ifndef CFG_FLASH_CFI
+ printf("Not define CFG_FLASH_CFI\n");
+ return (0);
+#else
+ value = addr[0];
+ va=(value & 0xFF000000)>>24;
+ vb=(value & 0x00FF0000)>>16;
+ vc=(value & 0x0000FF00)>>8;
+ vd=(value & 0x000000FF);
+ if ((va==0) && (vb==0)) {
+ printf("cannot identify Flash\n");
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+ else if ((va==0) && (vb!=0)) {
+ big_endian = 1;
+ info->chipwidth = FLASH_CFI_BY16;
+ if(vb == vd) info->portwidth = FLASH_CFI_32BIT;
+ else info->portwidth = FLASH_CFI_16BIT;
+ }
+ else if ((va!=0) && (vb==0)) {
+ big_endian = 0;
+ info->chipwidth = FLASH_CFI_BY16;
+ if(va == vc) info->portwidth = FLASH_CFI_32BIT;
+ else info->portwidth = FLASH_CFI_16BIT;
+ }
+ else if ((va!=0) && (vb!=0)) {
+ big_endian = 1; /* no meaning for 8bit chip */
+ info->chipwidth = FLASH_CFI_BY8;
+ if(va == vb) info->portwidth = FLASH_CFI_16BIT;
+ else info->portwidth = FLASH_CFI_8BIT;
+ }
+#ifdef DEBUG
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ printf("port width is 8 bit.\n");
+ break;
+ case FLASH_CFI_16BIT:
+ printf("port width is 16 bit, ");
+ break;
+ case FLASH_CFI_32BIT:
+ printf("port width is 32 bit, ");
+ break;
+ }
+ switch (info->chipwidth) {
+ case FLASH_CFI_BY16:
+ printf("chip width is 16 bit, ");
+ switch (big_endian) {
+ case 0:
+ printf("Little Endian.\n");
+ break;
+ case 1:
+ printf("Big Endian.\n");
+ break;
+ }
+ break;
+ }
+#endif
+#endif /*#ifdef CFG_FLASH_CFI*/
+
+ if (big_endian==0) value = (addr[0] & 0xFF000000) >>8;
+ else value = (addr[0] & 0x00FF0000);
+#ifdef DEBUG
+ printf("manufacturer=0x%x\n",(uint)(value>>16));
+#endif
+ switch (value) {
+ case MT_MANUFACT & 0xFFFF0000: /* SHARP, MT or => Intel */
+ case INTEL_ALT_MANU & 0xFFFF0000:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("unknown manufacturer: %x\n", (unsigned int)value);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ if (info->portwidth==FLASH_CFI_16BIT) {
+ switch (big_endian) {
+ case 0:
+ value = (addr[0] & 0x0000FF00)>>8;
+ break;
+ case 1:
+ value = (addr[0] & 0x000000FF);
+ break;
+ }
+ }
+ else if (info->portwidth == FLASH_CFI_32BIT) {
+ switch (big_endian) {
+ case 0:
+ value = (addr[1] & 0x0000FF00)>>8;
+ break;
+ case 1:
+ value = (addr[1] & 0x000000FF);
+ break;
+ }
+ }
+
+#ifdef DEBUG
+ printf("deviceID=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case (INTEL_ID_28F016S & 0x0000FFFF):
+ info->flash_id += FLASH_28F016SV;
+ info->sector_count = 32;
+ sector_offset = 0x10000;
+ break; /* => 2 MB */
+
+ case (INTEL_ID_28F160S3 & 0x0000FFFF):
+ info->flash_id += FLASH_28F160S3;
+ info->sector_count = 32;
+ sector_offset = 0x10000;
+ break; /* => 2 MB */
+
+ case (INTEL_ID_28F320S3 & 0x0000FFFF):
+ info->flash_id += FLASH_28F320S3;
+ info->sector_count = 64;
+ sector_offset = 0x10000;
+ break; /* => 4 MB */
+
+ case (INTEL_ID_28F640J3A & 0x0000FFFF):
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ sector_offset = 0x20000;
+ break; /* => 8 MB */
+
+ case SHARP_ID_28F016SCL & 0x0000FFFF:
+ case SHARP_ID_28F016SCZ & 0x0000FFFF:
+ info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+ info->sector_count = 32;
+ sector_offset = 0x10000;
+ break; /* => 2 MB */
+
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ sector_offset = sector_offset * (info->portwidth / info->chipwidth);
+ info->size = info->sector_count * sector_offset;
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += sector_offset;
+ /* don't know how to check sector protection */
+ info->protect[i] = 0;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ asm("sync");
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last, ready, erase_err_status;
+
+ if (big_endian == 1) {
+ ready = 0x0080;
+ erase_err_status = 0x00a0;
+ }
+ else {
+ ready = 0x8000;
+ erase_err_status = 0xa000;
+ }
+ if ((info->portwidth / info->chipwidth)==2) {
+ ready += (ready <<16);
+ erase_err_status += (erase_err_status <<16);
+ }
+
+#ifdef DEBUG
+ printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status);
+#endif
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+#ifdef DEBUG
+ printf("\nFlash Erase:\n");
+#endif
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
+ /* Start erase on unprotected sectors */
+#if defined(DEBUG)
+ printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_short *addr16 = (vu_short *)(info->start[sect]);
+ vu_long *addr = (vu_long *)(info->start[sect]);
+ printf(".");
+ switch (info->portwidth) {
+ case FLASH_CFI_16BIT:
+ asm("sync");
+ last = start = get_timer (0);
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+ /* Reset Array */
+ *addr16 = 0xffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr16 = 0x5050;
+ asm("sync");
+ /* Single Block Erase Command */
+ *addr16 = 0x2020;
+ asm("sync");
+ /* Confirm */
+ *addr16 = 0xD0D0;
+ asm("sync");
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr16 = 0xD0D0;
+ asm("sync");
+ }
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+ /* wait at least 80us - let's wait 1 ms */
+ *addr16 = 0x7070;
+ udelay (1000);
+ while ((*addr16 & ready) != ready) {
+ if((*addr16 & erase_err_status)== erase_err_status){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr16);
+ *addr16 = 0xFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr16 = 0xFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ /* reset to read mode */
+ *addr16 = 0xFFFF;
+ asm("sync");
+ break;
+ case FLASH_CFI_32BIT:
+ asm("sync");
+ last = start = get_timer (0);
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ asm("sync");
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+ }
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+ /* wait at least 80us - let's wait 1 ms */
+ *addr = 0x70707070;
+ udelay (1000);
+ while ((*addr & ready) != ready) {
+ if((*addr & erase_err_status)==erase_err_status){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+ break;
+ } /* end switch */
+ } /* end if */
+ } /* end for */
+
+ printf ("flash erase done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+#define FLASH_BLOCK_SIZE 32
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data, count, temp;
+/* ulong temp[FLASH_BLOCK_SIZE/4];*/
+ int i, l, rc;
+
+ count = cnt;
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ cp = wp;
+ /* handle unaligned block bytes , flash block size = 16bytes */
+ wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1);
+ if ((wp-cp)>=cnt) {
+ if ((rc = write_block(info,src,cp,wp-cp)) !=0)
+ return (rc);
+ src += wp-cp;
+ cnt -= wp-cp;
+ }
+ /* handle aligned block bytes */
+ temp = 0;
+ printf("\n");
+ while ( cnt >= FLASH_BLOCK_SIZE) {
+ if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) {
+ return (rc);
+ }
+ src += FLASH_BLOCK_SIZE;
+ cp += FLASH_BLOCK_SIZE;
+ cnt -= FLASH_BLOCK_SIZE;
+ if (((count-cnt)>>10)>temp) {
+ temp=(count-cnt)>>10;
+ printf("\r%d KB",temp);
+ }
+ }
+ printf("\n");
+ wp = cp;
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+#undef FLASH_BLOCK_SIZE
+
+/*-----------------------------------------------------------------------
+ * Write block to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * -1 Error
+ */
+static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt)
+{
+ vu_short *baddr, *addr = (vu_short *)dest;
+ ushort data;
+ ulong start, now, xsr,csr, ready;
+ int flag;
+
+ if (cnt==0) return 0;
+ else if(cnt != (cnt& ~1)) return -1;
+
+ /* Check if Flash is (sufficiently) erased */
+ data = * src;
+ data = (data<<8) | *(src+1);
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ if (big_endian == 1) {
+ ready = 0x0080;
+ }
+ else {
+ ready = 0x8000;
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ do {
+ /* Write Command */
+ *addr = 0xe8e8;
+ asm("sync");
+ xsr = *addr;
+ asm("sync");
+ } while (!(xsr & ready)); /*wait until read */
+ /*write count=BLOCK SIZE -1 */
+ data=(cnt>>1)-1;
+ data=(data<<8)|data;
+ *addr = data; /* word mode, cnt/2 */
+ asm("sync");
+ baddr = addr;
+ while(cnt) {
+ data = * src++;
+ data = (data<<8) | *src++;
+ asm("sync");
+ *baddr = data;
+ asm("sync");
+ ++baddr;
+ cnt = cnt -2;
+ }
+ *addr = 0xd0d0; /* confirm write */
+ start = get_timer(0);
+ asm("sync");
+ if (flag)
+ enable_interrupts();
+ /* data polling for D7 */
+ flag = 0;
+ while (((csr = *addr) & ready) != ready) {
+ if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x4040) {
+ printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+ /* Clear Status Registers Command */
+ *addr = 0x5050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFF;
+ asm("sync");
+ return (flag);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a short word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+ vu_short *addr = (vu_short *)dest;
+ ulong start, now, csr, ready;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x1010;
+ start = get_timer (0);
+ asm("sync");
+ /* Write Data */
+ *addr = data;
+ asm("sync");
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+ if (big_endian == 1) {
+ ready = 0x0080;
+ }
+ else {
+ ready = 0x8000;
+ }
+ /* data polling for D7 */
+ flag = 0;
+ while (((csr = *addr) & ready) != ready) {
+ if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x4040) {
+ printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+ /* Clear Status Registers Command */
+ *addr = 0x5050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFF;
+ asm("sync");
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr, ready;
+ int flag=0;
+
+ switch (info->portwidth) {
+ case FLASH_CFI_32BIT:
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ if (big_endian == 1) {
+ ready = 0x0080;
+ }
+ else {
+ ready = 0x8000;
+ }
+ if ((info->portwidth / info->chipwidth)==2) {
+ ready += (ready <<16);
+ }
+ else {
+ ready = ready << 16;
+ }
+ /* Write Command */
+ *addr = 0x10101010;
+ asm("sync");
+ /* Write Data */
+ *addr = data;
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+ while (((csr = *addr) & ready) != ready) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x40404040) {
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+ break;
+ case FLASH_CFI_16BIT:
+ flag = write_short (info, dest, (unsigned short) (data>>16));
+ if (flag == 0)
+ flag = write_short (info, dest+2, (unsigned short) (data));
+ break;
+ }
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(flash_info_t * info, vu_long * addr)
+{
+ ulong start, now, ready;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+
+ *addr = 0x60606060;
+ asm("sync");
+ *addr = 0xd0d0d0d0;
+ asm("sync");
+
+
+ if (big_endian == 1) {
+ ready = 0x0080;
+ }
+ else {
+ ready = 0x8000;
+ }
+ if ((info->portwidth / info->chipwidth)==2) {
+ ready += (ready <<16);
+ }
+ else {
+ ready = ready << 16;
+ }
+#ifdef DEBUG
+ printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready);
+#endif
+ *addr = 0x70707070; /* read status */
+ start = get_timer (0);
+ while((*addr & ready) != ready){
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
--- /dev/null
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+/* TLB1 entries configuration: */
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ .long 0x0a /* the following data table uses a few of 16 TLB entries */
+
+ .long TLB1_MAS0(1,1,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if defined(CFG_FLASH_PORT_WIDTH_16)
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ #if !defined(CONFIG_SPD_EEPROM)
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ .long TLB1_MAS0(1,6,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ #if defined(CONFIG_RAM_AS_FLASH)
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ #else
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,7,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ #ifdef CONFIG_L2_INIT_RAM
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+ #else
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,8,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,9,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+ entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ * f800_0000-fbff_ffff: LBC SDRAM(64M)
+ * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ * fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ * fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ * Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x03
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+ entry_end
--- /dev/null
+/*
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+extern long int spd_sdram (void);
+
+long int fixed_sdram (void);
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+ pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+ return 0;
+}
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info (&sysinfo);
+
+ printf ("Board: Freescale MPC8540EVAL Board\n");
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+ printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+ if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+ || (CFG_LBC_LCRR & 0x0f) == 8) {
+ printf ("\tLBC: %lu MHz\n",
+ sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
+ } else {
+ printf("\tLBC: unknown\n");
+ }
+ printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+ return (0);
+}
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+ volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ sys_info_t sysinfo;
+ uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+
+#if defined(CONFIG_DDR_DLL)
+ uint temp_ddrdll = 0;
+
+ /* Work around to stabilize DDR DLL */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CFG_RAMBOOT)
+ return dram_size;
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
+ get_sys_info(&sysinfo);
+ /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+ if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+ lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+ } else {
+ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+ udelay(200);
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+ lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+ {
+ /* Initialize all of memory for ECC, then
+ * enable errors */
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ dma_init();
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+ *p = (unsigned int)0xdeadbeef;
+ if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+ }
+
+ /* 8K */
+ dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+ /* 16K */
+ dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+ /* 32K */
+ dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+ /* 64K */
+ dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+ /* 128k */
+ dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+ /* 256k */
+ dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+ /* 512k */
+ dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+ /* 1M */
+ dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+ /* 2M */
+ dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+ /* 4M */
+ dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+ }
+
+ /* Enable errors for ECC */
+ ddr->err_disable = 0x00000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+#ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+#endif
+ asm("sync;isync;msync");
+ udelay(500);
+#if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+#else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+#endif
+ asm("sync; isync; msync");
+ udelay(500);
+#endif
+ return (CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
--- /dev/null
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Assumes that the size of u-boot is less than 512K and the
+ * start address is aligned on a 512K block.
+ * Boot page and reset vector is put at that end of the 512K block. */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/mpc8540eval/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+
+ . = (. & 0xFFF80000) + 0x0007F000;
+ .bootpg :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/mpc8540eval/init.o (.bootpg)
+ } = 0xffff
+
+ . = (. & 0xFFF80000) + 0x0007FFFC;
+ .resetvec :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+}
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
#include <spd.h>
#include <miiphy.h>
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
dram_size = fixed_sdram ();
#endif
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
cpu/mpc85xx/ether_fcc.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
+ * Part of this code has been derived from linux:
+ * Universal Host Controller Interface driver for USB (take II).
+ *
+ * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
+ * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
+ * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
+ * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
+ * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support
+ * from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
+ * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c)
+ *
+ * HW-initalization based on material of
+ *
+ * (C) Copyright 1999 Linus Torvalds
+ * (C) Copyright 1999 Johannes Erdfelt
+ * (C) Copyright 1999 Randy Dunlap
+ * (C) Copyright 1999 Gregory P. Smith
+ *
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
- * Note: Part of this code has been derived from linux
*
*/
#include <common.h>
-#if defined CFG_JFFS_CUSTOM_PART
-#include <jffs2/jffs2.h>
-#endif
-
#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE
static void flash_sync_real_protect(flash_info_t * info);
#endif
-#if defined CFG_JFFS_CUSTOM_PART
-
-/**
- * jffs2_part_info - get information about a JFFS2 partition
- *
- * @part_num: number of the partition you want to get info about
- * @return: struct part_info* in case of success, 0 if failure
- */
-
-static struct part_info part;
-static int current_part = -1;
-
-struct part_info *
-jffs2_part_info(int part_num)
-{
- void *jffs2_priv_saved = part.jffs2_priv;
-
- printf("jffs2_part_info: part_num=%i\n", part_num);
-
- if (current_part == part_num)
- return ∂
-
- /* rootfs */
- if (part_num == 0) {
- memset(&part, 0, sizeof (part));
-
- part.offset = (char *) MX1FS2_JFFS2_PART0_START;
- part.size = MX1FS2_JFFS2_PART0_SIZE;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
- printf("part.size = 0x%08x\n", (unsigned int) part.size);
- }
-
- /* userfs */
- if (part_num == 1) {
- memset(&part, 0, sizeof (part));
-
- part.offset = (char *) MX1FS2_JFFS2_PART1_START;
- part.size = MX1FS2_JFFS2_PART1_SIZE;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
- printf("part.size = 0x%08x\n", (unsigned int) part.size);
- }
-
- if (current_part == part_num) {
- part.usr_priv = ¤t_part;
- part.jffs2_priv = jffs2_priv_saved;
- return ∂
- }
-
- printf("jffs2_part_info: end of partition table\n");
- return 0;
-}
-#endif /* CFG_JFFS_CUSTOM_PART */
-
/*-----------------------------------------------------------------------
* flash_init()
*
static int write_data (flash_info_t *info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t *info);
void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
/*-----------------------------------------------------------------------
*/
break;
}
size += flash_info[i].size;
+
+ /* get the h/w and s/w protection status in sync */
+ flash_sync_real_protect(&flash_info[i]);
}
/* Protect monitor and environment sectors
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
}
}
}
}
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+
+ case FLASH_28F128J3A:
+ case FLASH_28F640J3A:
+ case FLASH_28F320J3A:
+ for (i = 0; i < info->sector_count; ++i) {
+ info->protect[i] = intel_sector_protected(info, i);
+ }
+ break;
+ default:
+ /* no h/w protect support */
+ break;
+ }
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+ FPWV *addr;
+ FPWV *lock_conf_addr;
+ ulong start;
+ unsigned char ret;
+
+ /*
+ * first, wait for the WSM to be finished. The rationale for
+ * waiting for the WSM to become idle for at most
+ * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+ * because of: (1) erase, (2) program or (3) lock bit
+ * configuration. So we just wait for the longest timeout of
+ * the (1)-(3), i.e. the erase timeout.
+ */
+
+ /* wait at least 35ns (W12) before issuing Read Status Register */
+ udelay(1);
+ addr = (FPWV *) info->start[sector];
+ *addr = (FPW) INTEL_STATUS;
+
+ start = get_timer (0);
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ printf("WSM busy too long, can't get prot status\n");
+ return 1;
+ }
+ }
+
+ /* issue the Read Identifier Codes command */
+ *addr = (FPW) INTEL_READID;
+
+ /* wait at least 35ns (W12) before reading */
+ udelay(1);
+
+ /* Intel example code uses offset of 2 for 16 bit flash */
+ lock_conf_addr = (FPWV *) info->start[sector] + 2;
+ ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+ /* put flash back in read mode */
+ *addr = (FPW) INTEL_RESET;
+
+ return ret;
+}
+
/*-----------------------------------------------------------------------
*/
* 0 - OK
* 1 - Error (timeout, voltage problems, etc.)
*/
-int flash_real_protect(flash_info_t *info, long sector, int prot)
+int flash_real_protect (flash_info_t *info, long sector, int prot)
{
ulong start;
int i;
/*
* Clear lock bit command clears all sectors lock bits, so
* we have to restore lock bits of protected sectors.
+ * WARNING: code below re-locks sectors only for one bank (info).
+ * This causes problems on boards where several banks share
+ * the same chip, as sectors in othere banks will be unlocked
+ * but not re-locked. It works fine on pm520 though, as there
+ * is only one chip and one bank.
*/
if (!prot)
{
}
}
}
+ /*
+ * get the s/w sector protection status in sync with the h/w,
+ * in case something went wrong during the re-locking.
+ */
+ flash_sync_real_protect(info); /* resets flash to read mode */
}
if (flag)
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+OBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
+++ /dev/null
-/*
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao,(X.Xiao@motorola.com)
- *
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if !defined(CFG_NO_FLASH)
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CFG_ENV_IS_IN_FLASH)
-# ifndef CFG_ENV_ADDR
-# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
-# endif
-# ifndef CFG_ENV_SIZE
-# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
-# endif
-# ifndef CFG_ENV_SECT_SIZE
-# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
-# endif
-#endif
-
-#undef DEBUG
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(vu_long * addr);
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
-
- /* Init: enable write,
- * or we cannot even write flash commands
- */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* set the default sector offset */
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-
-#ifdef CFG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
- break;
- case FLASH_28F128J3A: printf ("28F128J3A (128 Mbit, 128 x 128K)\n");
- break;
-
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
- ulong sector_offset;
-
-#ifdef DEBUG
- printf("Check flash at 0x%08x\n",(uint)addr);
-#endif
- /* Write "Intelligent Identifier" command: read Manufacturer ID */
- *addr = 0x90909090;
- udelay(20);
- asm("sync");
-
- value = addr[0] & 0x00FF00FF;
-
-#ifdef DEBUG
- printf("manufacturer=0x%x\n",(uint)value);
-#endif
- switch (value) {
- case MT_MANUFACT: /* SHARP, MT or => Intel */
- case INTEL_ALT_MANU:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- printf("unknown manufacturer: %x\n", (unsigned int)value);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1] & 0x00FF00FF; /* device ID */
-
-#ifdef DEBUG
- printf("deviceID=0x%x\n",(uint)value);
-#endif
- switch (value) {
- case (INTEL_ID_28F016S):
- info->flash_id += FLASH_28F016SV;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F160S3):
- info->flash_id += FLASH_28F160S3;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F320S3):
- info->flash_id += FLASH_28F320S3;
- info->sector_count = 64;
- info->size = 0x00800000;
- sector_offset = 0x20000;
- break; /* => 2x4 MB */
-
- case (INTEL_ID_28F640J3A):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x01000000;
- sector_offset = 0x40000;
- break; /* => 2x8 MB */
-
- case (INTEL_ID_28F128J3A):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x02000000;
- sector_offset = 0x40000;
- break; /* => 2x16 MB */
-
-
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- info->sector_count = 32;
- info->size = 0x00800000;
- sector_offset = 0x40000;
- break; /* => 4x2 MB */
-
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += sector_offset;
- /* don't know how to check sector protection */
- info->protect[i] = 0;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_long *)info->start[0];
- *addr = 0xFFFFFF; /* reset bank to read array mode */
- asm("sync");
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-#ifdef DEBUG
- printf("\nFlash Erase:\n");
-#endif
- /* Make Sure Block Lock Bit is not set. */
- if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
- return 1;
- }
-
- /* Start erase on unprotected sectors */
-#if defined(DEBUG)
- printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
-#endif
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
- asm("sync");
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
- /* Single Block Erase Command */
- *addr = 0x20202020;
- asm("sync");
- /* Confirm */
- *addr = 0xD0D0D0D0;
- asm("sync");
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = 0xD0D0D0D0;
- asm("sync");
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
- while ((*addr & 0x00800080) != 0x00800080) {
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- /* reset to read mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
- }
- }
-
- printf ("flash erase done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start, csr;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = 0x10101010;
- asm("sync");
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
-
- while (((csr = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x40404040) {
- printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
- flag = 1;
- }
-
- /* Clear Status Registers Command */
- *addr = 0x50505050;
- asm("sync");
- /* Reset to read array mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
-
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
- */
-
-static int clear_block_lock_bit(vu_long * addr)
-{
- ulong start, now;
-
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
-
- *addr = 0x60606060;
- asm("sync");
- *addr = 0xd0d0d0d0;
- asm("sync");
-
- start = get_timer (0);
- while((*addr & 0x00800080) != 0x00800080){
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout on clearing Block Lock Bit\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- }
- return 0;
-}
-
-#endif /* !CFG_NO_FLASH */
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+SOBJS := init.o
+#SOBJS :=
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PM856 board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 64M FLASH (8,16,32 or 64 MB)
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+ /*
+ * TLB 7: 256M DDR
+ * 0x00000000 256M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+#endif
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff BCSR 1M
+ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x05
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4
+ entry_end
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+long int fixed_sdram(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+void reset_phy (void)
+{
+}
+
+
+int checkboard (void)
+{
+ puts("Board: MicroSys PM856\n");
+
+#ifdef CONFIG_PCI
+ printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf(" PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init();
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+ int i,x;
+
+ x = 10;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay (200);
+ while (gur->ddrdllcr != 0x81000100)
+ {
+ gur->devdisr = gur->devdisr | 0x00010000;
+ asm("sync;isync;msync");
+ for (i=0; i<x; i++)
+ ;
+ gur->devdisr = gur->devdisr & 0xfff7ffff;
+ asm("sync;isync;msync");
+ x++;
+ }
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+ } else {
+ /*
+ * On REV1 boards, need to change CLKDIV before enable DLL.
+ * Default CLKDIV is 8, change it to 4 temporarily.
+ */
+ uint pvr = get_pvr();
+ uint temp_lbcdll = 0;
+
+ if (pvr == PVR_85xx_REV1) {
+ /* FIXME: Justify the high bit here. */
+ lbc->lcrr = 0x10000004;
+ }
+
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ } },
+ { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
--- /dev/null
+/*
+ * (C) Copyright 2005 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/pm856/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/pm856/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Ported from Ebony flash support
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0xfff80000} /* Boot Flash */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size(
+ (vu_long *)flash_addr_table[index][i], &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i]<<20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " "
+ );
+ }
+ printf ("\n");
+ return;
+ }
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ FLASH_WORD_SIZE value;
+ ulong base = (ulong)addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+ /* Write auto select command: read Manufacturer ID */
+ udelay(10000);
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ udelay(1000);
+ addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ udelay(1000);
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00080000; /* => 512 kb */
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (info->flash_id == FLASH_AM040) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* reset to return to reading data */
+ addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+ ulong start, now, last;
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+ start = get_timer (0);
+ last = start;
+ while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+ DEBUGF("Erasing sector %p\n", addr2);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
--- /dev/null
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation.
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#if defined(CONFIG_440)
+# include <440_i2c.h>
+#else
+# include <405gp_i2c.h>
+#endif
+#include <i2c.h>
+#include <440_i2c.h>
+#include <command.h>
+#include "ppc440gx_i2c.h"
+
+#ifdef CONFIG_I2C_BUS1
+
+#define IIC_OK 0
+#define IIC_NOK 1
+#define IIC_NOK_LA 2 /* Lost arbitration */
+#define IIC_NOK_ICT 3 /* Incomplete transfer */
+#define IIC_NOK_XFRA 4 /* Transfer aborted */
+#define IIC_NOK_DATA 5 /* No data in buffer */
+#define IIC_NOK_TOUT 6 /* Transfer timeout */
+
+#define IIC_TIMEOUT 1 /* 1 second */
+#if defined(CFG_I2C_NOPROBES)
+static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
+#endif
+
+static void _i2c_bus1_reset (void)
+{
+ int i, status;
+
+ /* Reset status register */
+ /* write 1 in SCMP and IRQA to clear these fields */
+ out8 (IIC_STS1, 0x0A);
+
+ /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
+ out8 (IIC_EXTSTS1, 0x8F);
+ __asm__ volatile ("eieio");
+
+ /*
+ * Get current state, reset bus
+ * only if no transfers are pending.
+ */
+ i = 10;
+ do {
+ /* Get status */
+ status = in8 (IIC_STS1);
+ udelay (500); /* 500us */
+ i--;
+ } while ((status & IIC_STS_PT) && (i > 0));
+ /* Soft reset controller */
+ status = in8 (IIC_XTCNTLSS1);
+ out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
+ __asm__ volatile ("eieio");
+
+ /* make sure where in initial state, data hi, clock hi */
+ out8 (IIC_DIRECTCNTL1, 0xC);
+ for (i = 0; i < 10; i++) {
+ if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
+ /* clock until we get to known state */
+ out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
+ udelay (100); /* 100us */
+ out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
+ udelay (100); /* 100us */
+ } else {
+ break;
+ }
+ }
+ /* send start condition */
+ out8 (IIC_DIRECTCNTL1, 0x4);
+ udelay (1000); /* 1ms */
+ /* send stop condition */
+ out8 (IIC_DIRECTCNTL1, 0xC);
+ udelay (1000); /* 1ms */
+ /* Unreset controller */
+ out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
+ udelay (1000); /* 1ms */
+}
+
+void i2c1_init (int speed, int slaveadd)
+{
+ sys_info_t sysInfo;
+ unsigned long freqOPB;
+ int val, divisor;
+
+#ifdef CFG_I2C_INIT_BOARD
+ /* call board specific i2c bus reset routine before accessing the */
+ /* environment, which might be in a chip on that bus. For details */
+ /* about this problem see doc/I2C_Edge_Conditions. */
+ i2c_init_board();
+#endif
+
+ /* Handle possible failed I2C state */
+ /* FIXME: put this into i2c_init_board()? */
+ _i2c_bus1_reset ();
+
+ /* clear lo master address */
+ out8 (IIC_LMADR1, 0);
+
+ /* clear hi master address */
+ out8 (IIC_HMADR1, 0);
+
+ /* clear lo slave address */
+ out8 (IIC_LSADR1, 0);
+
+ /* clear hi slave address */
+ out8 (IIC_HSADR1, 0);
+
+ /* Clock divide Register */
+ /* get OPB frequency */
+ get_sys_info (&sysInfo);
+ freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
+ /* set divisor according to freqOPB */
+ divisor = (freqOPB - 1) / 10000000;
+ if (divisor == 0)
+ divisor = 1;
+ out8 (IIC_CLKDIV1, divisor);
+
+ /* no interrupts */
+ out8 (IIC_INTRMSK1, 0);
+
+ /* clear transfer count */
+ out8 (IIC_XFRCNT1, 0);
+
+ /* clear extended control & stat */
+ /* write 1 in SRC SRS SWC SWS to clear these fields */
+ out8 (IIC_XTCNTLSS1, 0xF0);
+
+ /* Mode Control Register
+ Flush Slave/Master data buffer */
+ out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
+ __asm__ volatile ("eieio");
+
+
+ val = in8(IIC_MDCNTL1);
+ __asm__ volatile ("eieio");
+
+ /* Ignore General Call, slave transfers are ignored,
+ disable interrupts, exit unknown bus state, enable hold
+ SCL
+ 100kHz normaly or FastMode for 400kHz and above
+ */
+
+ val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+ if( speed >= 400000 ){
+ val |= IIC_MDCNTL_FSM;
+ }
+ out8 (IIC_MDCNTL1, val);
+
+ /* clear control reg */
+ out8 (IIC_CNTL1, 0x00);
+ __asm__ volatile ("eieio");
+
+}
+
+/*
+ This code tries to use the features of the 405GP i2c
+ controller. It will transfer up to 4 bytes in one pass
+ on the loop. It only does out8(lbz) to the buffer when it
+ is possible to do out16(lhz) transfers.
+
+ cmd_type is 0 for write 1 for read.
+
+ addr_len can take any value from 0-255, it is only limited
+ by the char, we could make it larger if needed. If it is
+ 0 we skip the address write cycle.
+
+ Typical case is a Write of an addr followd by a Read. The
+ IBM FAQ does not cover this. On the last byte of the write
+ we don't set the creg CHT bit, and on the first bytes of the
+ read we set the RPST bit.
+
+ It does not support address only transfers, there must be
+ a data part. If you want to write the address yourself, put
+ it in the data pointer.
+
+ It does not support transfer to/from address 0.
+
+ It does not check XFRCNT.
+*/
+static
+int i2c_transfer1(unsigned char cmd_type,
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char addr_len,
+ unsigned char data[],
+ unsigned short data_len )
+{
+ unsigned char* ptr;
+ int reading;
+ int tran,cnt;
+ int result;
+ int status;
+ int i;
+ uchar creg;
+
+ if( data == 0 || data_len == 0 ){
+ /*Don't support data transfer of no length or to address 0*/
+ printf( "i2c_transfer: bad call\n" );
+ return IIC_NOK;
+ }
+ if( addr && addr_len ){
+ ptr = addr;
+ cnt = addr_len;
+ reading = 0;
+ }else{
+ ptr = data;
+ cnt = data_len;
+ reading = cmd_type;
+ }
+
+ /*Clear Stop Complete Bit*/
+ out8(IIC_STS1,IIC_STS_SCMP);
+ /* Check init */
+ i=10;
+ do {
+ /* Get status */
+ status = in8(IIC_STS1);
+ __asm__ volatile("eieio");
+ i--;
+ } while ((status & IIC_STS_PT) && (i>0));
+
+ if (status & IIC_STS_PT) {
+ result = IIC_NOK_TOUT;
+ return(result);
+ }
+ /*flush the Master/Slave Databuffers*/
+ out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+ /*need to wait 4 OPB clocks? code below should take that long*/
+
+ /* 7-bit adressing */
+ out8(IIC_HMADR1,0);
+ out8(IIC_LMADR1, chip);
+ __asm__ volatile("eieio");
+
+ tran = 0;
+ result = IIC_OK;
+ creg = 0;
+
+ while ( tran != cnt && (result == IIC_OK)) {
+ int bc,j;
+
+ /* Control register =
+ Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
+ Transfer is a sequence of transfers
+ */
+ creg |= IIC_CNTL_PT;
+
+ bc = (cnt - tran) > 4 ? 4 :
+ cnt - tran;
+ creg |= (bc-1)<<4;
+ /* if the real cmd type is write continue trans*/
+ if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
+ creg |= IIC_CNTL_CHT;
+
+ if (reading)
+ creg |= IIC_CNTL_READ;
+ else {
+ for(j=0; j<bc; j++) {
+ /* Set buffer */
+ out8(IIC_MDBUF1,ptr[tran+j]);
+ __asm__ volatile("eieio");
+ }
+ }
+ out8(IIC_CNTL1, creg );
+ __asm__ volatile("eieio");
+
+ /* Transfer is in progress
+ we have to wait for upto 5 bytes of data
+ 1 byte chip address+r/w bit then bc bytes
+ of data.
+ udelay(10) is 1 bit time at 100khz
+ Doubled for slop. 20 is too small.
+ */
+ i=2*5*8;
+ do {
+ /* Get status */
+ status = in8(IIC_STS1);
+ __asm__ volatile("eieio");
+ udelay (10);
+ i--;
+ } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
+ && (i>0));
+
+ if (status & IIC_STS_ERR) {
+ result = IIC_NOK;
+ status = in8 (IIC_EXTSTS1);
+ /* Lost arbitration? */
+ if (status & IIC_EXTSTS_LA)
+ result = IIC_NOK_LA;
+ /* Incomplete transfer? */
+ if (status & IIC_EXTSTS_ICT)
+ result = IIC_NOK_ICT;
+ /* Transfer aborted? */
+ if (status & IIC_EXTSTS_XFRA)
+ result = IIC_NOK_XFRA;
+ } else if ( status & IIC_STS_PT) {
+ result = IIC_NOK_TOUT;
+ }
+ /* Command is reading => get buffer */
+ if ((reading) && (result == IIC_OK)) {
+ /* Are there data in buffer */
+ if (status & IIC_STS_MDBS) {
+ /*
+ even if we have data we have to wait 4OPB clocks
+ for it to hit the front of the FIFO, after that
+ we can just read. We should check XFCNT here and
+ if the FIFO is full there is no need to wait.
+ */
+ udelay (1);
+ for(j=0;j<bc;j++) {
+ ptr[tran+j] = in8(IIC_MDBUF1);
+ __asm__ volatile("eieio");
+ }
+ } else
+ result = IIC_NOK_DATA;
+ }
+ creg = 0;
+ tran+=bc;
+ if( ptr == addr && tran == cnt ) {
+ ptr = data;
+ cnt = data_len;
+ tran = 0;
+ reading = cmd_type;
+ if( reading )
+ creg = IIC_CNTL_RPST;
+ }
+ }
+ return (result);
+}
+
+int i2c_probe1 (uchar chip)
+{
+ uchar buf[1];
+
+ buf[0] = 0;
+
+ /*
+ * What is needed is to send the chip address and verify that the
+ * address was <ACK>ed (i.e. there was a chip at that address which
+ * drove the data line low).
+ */
+ return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
+}
+
+
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+ uchar xaddr[4];
+ int ret;
+
+ if ( alen > 4 ) {
+ printf ("I2C read: addr len %d not supported\n", alen);
+ return 1;
+ }
+
+ if ( alen > 0 ) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
+
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ if( alen > 0 )
+ chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+ if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+ printf( "I2c read: failed %d\n", ret);
+ return 1;
+ }
+ return 0;
+}
+
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+ uchar xaddr[4];
+
+ if ( alen > 4 ) {
+ printf ("I2C write: addr len %d not supported\n", alen);
+ return 1;
+
+ }
+ if ( alen > 0 ) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ if( alen > 0 )
+ chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+
+ return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
+{
+ char buf;
+
+ i2c_read1(i2c_addr, reg, 1, &buf, 1);
+
+ return(buf);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
+{
+ i2c_write1(i2c_addr, reg, 1, &val, 1);
+}
+
+
+int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int j;
+#if defined(CFG_I2C_NOPROBES)
+ int k, skip;
+#endif
+
+ puts ("Valid chip addresses:");
+ for(j = 0; j < 128; j++) {
+#if defined(CFG_I2C_NOPROBES)
+ skip = 0;
+ for (k = 0; k < sizeof(i2c_no_probes); k++){
+ if (j == i2c_no_probes[k]){
+ skip = 1;
+ break;
+ }
+ }
+ if (skip)
+ continue;
+#endif
+ if(i2c_probe1(j) == 0) {
+ printf(" %02X", j);
+ }
+ }
+ putc ('\n');
+
+#if defined(CFG_I2C_NOPROBES)
+ puts ("Excluded chip addresses:");
+ for( k = 0; k < sizeof(i2c_no_probes); k++ )
+ printf(" %02X", i2c_no_probes[k] );
+ putc ('\n');
+#endif
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ iprobe1, 1, 1, do_i2c1_probe,
+ "iprobe1 - probe to discover valid I2C chip addresses\n",
+ "\n -discover valid I2C chip addresses\n"
+);
+
+#endif /* CONFIG_I2C_BUS1 */
--- /dev/null
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from i2c driver for ppc4xx by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#if defined(CONFIG_440)
+# include <440_i2c.h>
+#else
+# include <405gp_i2c.h>
+#endif
+#include <i2c.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500)
+#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
+#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF)
+#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF)
+#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR)
+#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR)
+#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL)
+#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL)
+#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS)
+#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
+#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
+#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
+#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV)
+#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
+#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
+#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
+#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL)
+
+void i2c1_init (int speed, int slaveadd);
+int i2c_probe1 (uchar chip);
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg);
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val);
+
+#endif /* CONFIG_HARD_I2C */
--- /dev/null
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+#include "sb_common.h"
+
+long int fixed_sdram (void);
+
+/*************************************************************************
+ * metrobox_get_master
+ *
+ * PRI_N - active low signal. If the GPIO pin is low we are the master
+ *
+ ************************************************************************/
+int sbcommon_get_master(void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+
+ if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
+ return 0;
+ }
+ else {
+ return 1;
+ }
+}
+
+/*************************************************************************
+ * metrobox_secondary_present
+ *
+ * Figure out if secondary/slave board is present
+ *
+ ************************************************************************/
+int sbcommon_secondary_present(void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+
+ if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
+ return 0;
+ else
+ return 1;
+}
+
+/*************************************************************************
+ * sbcommon_get_serial_number
+ *
+ * Retrieve the board serial number via the mac address in eeprom
+ *
+ ************************************************************************/
+unsigned short sbcommon_get_serial_number(void)
+{
+ unsigned char buff[0x100];
+ unsigned short sernum;
+
+ /* Get the board serial number from eeprom */
+ /* Initialize I2C */
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ /* Read 256 bytes in EEPROM */
+ i2c_read (0x50, 0, 1, buff, 0x100);
+
+ memcpy(&sernum, &buff[0xF4], 2);
+ sernum /= 32;
+
+ return (sernum);
+}
+
+/*************************************************************************
+ * sbcommon_fans
+ *
+ * Spin up fans 2 & 3 to get some air moving. OS will take care
+ * of the rest. This is mostly a precaution...
+ *
+ * Assumes i2c bus 1 is ready.
+ *
+ ************************************************************************/
+void sbcommon_fans(void)
+{
+ /*
+ * Attempt to turn on 2 of the fans...
+ * Need to go through the bridge
+ */
+ puts ("FANS: ");
+
+ /* select fan4 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x08); /* val = bus 4 */
+
+ /* Turn on FAN 4 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 4 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ /* select fan3 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x04); /* val = bus 3 */
+
+ /* Turn on FAN 3 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 3 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ /* select fan2 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x02); /* val = bus 4 */
+
+ /* Turn on FAN 2 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 2 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ /* select fan1 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x01); /* val = bus 0 */
+
+ /* Turn on FAN 1 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 1 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ puts ("on\n");
+
+ return;
+
+}
+
+/*************************************************************************
+ * initdram
+ *
+ * Initialize sdram
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram (0);
+#else
+ dram_size = fixed_sdram ();
+#endif
+ return dram_size;
+}
+
+
+/*************************************************************************
+ * testdram
+ *
+ *
+ ************************************************************************/
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing SDRAM: ");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("OK\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay (400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ for (;;) {
+ mfsdram (mem_mcsts, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+
+ return (128 * 1024 * 1024); /* 128 MB */
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+ unsigned long strap;
+
+ /*--------------------------------------------------------------------------+
+ * The metrobox is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*--------------------------------------------------------------------------+
+ * Disable everything
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0SA, 0 ); /* disable */
+ out32r( PCIX0_PIM1SA, 0 ); /* disable */
+ out32r( PCIX0_PIM2SA, 0 ); /* disable */
+ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+ /*--------------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAH, 0 );
+ out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+ out32r( PCIX0_BAR0, 0 );
+
+ /*--------------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *--------------------------------------------------------------------------*/
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+ out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ * is_pci_host
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* The metrobox is always configured as host. */
+ return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * board_get_enetaddr
+ *
+ * Get the ethernet MAC address for the management ethernet from the
+ * strap EEPROM. Note that is the BASE address for the range of
+ * external ethernet MACs on the board. The base + 31 is the actual
+ * mgmt mac address.
+ *
+ ************************************************************************/
+static int macaddr_idx = 0;
+
+void board_get_enetaddr (uchar * enet)
+{
+ int i;
+ unsigned short tmp;
+ unsigned char buff[0x100], *cp;
+
+ if (0 == macaddr_idx) {
+
+ /* Initialize I2C */
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ /* Read 256 bytes in EEPROM */
+ i2c_read (0x50, 0, 1, buff, 0x100);
+
+ cp = &buff[0xF0];
+
+ for (i = 0; i < 6; i++,cp++)
+ enet[i] = *cp;
+
+ memcpy(&tmp, &enet[4], 2);
+ tmp += 31;
+ memcpy(&enet[4], &tmp, 2);
+
+ macaddr_idx++;
+ } else {
+ enet[0] = 0x02;
+ enet[1] = 0x00;
+ enet[2] = 0x00;
+ enet[3] = 0x00;
+ enet[4] = 0x00;
+ if (1 == sbcommon_get_master() ) {
+ /* Master/Primary card */
+ enet[5] = 0x01;
+ } else {
+ /* Slave/Secondary card */
+ enet [5] = 0x02;
+ }
+ }
+
+ return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+ return (ctrlc());
+}
+#endif
--- /dev/null
+#ifndef __SBCOMMON_H__
+#define __SBCOMMON_H__
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+
+/*
+ * GPIO Settings
+ */
+/* Chassis settings */
+#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
+#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
+
+/* Debug LEDs */
+#define SBCOMMON_GPIO_DBGLED_0 0x00000400
+#define SBCOMMON_GPIO_DBGLED_1 0x00000200
+#define SBCOMMON_GPIO_DBGLED_2 0x00100000
+#define SBCOMMON_GPIO_DBGLED_3 0x00000100
+
+#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
+ SBCOMMON_GPIO_DBGLED_1 | \
+ SBCOMMON_GPIO_DBGLED_2 | \
+ SBCOMMON_GPIO_DBGLED_3)
+
+#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
+#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
+#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
+
+#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
+
+#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
+ SBCOMMON_GPIO_DBGLED_1 | \
+ SBCOMMON_GPIO_DBGLED_2 | \
+ SBCOMMON_GPIO_DBGLED_3 | \
+ SBCOMMON_GPIO_SYS_STATUS)
+
+typedef struct ppc440_gpio_regs {
+ volatile unsigned long out;
+ volatile unsigned long tri_state;
+ volatile unsigned long dummy[4];
+ volatile unsigned long open_drain;
+ volatile unsigned long in;
+} __attribute__((packed)) ppc440_gpio_regs_t;
+
+int sbcommon_get_master(void);
+int sbcommon_secondary_present(void);
+unsigned short sbcommon_get_serial_number(void);
+void sbcommon_fans(void);
+
+#endif /* __SBCOMMON_H__ */
--- /dev/null
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+# Travis B. Sawyer
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+ ../common/sb_common.o
+
+SOBJS = init.o
+
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandburst Corporation Metrobox Reference Design
+# Travis B. Sawyer
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_of
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_OF_AUTO_H
+#define HAL_KA_OF_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'ofem'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define OFEM_BLOCK_ADDR_BIT_L 6
+#define OFEM_BLOCK_ADDR_BIT_H 9
+#define OFEM_BLOCK_ADDR_WIDTH 4
+
+#define OFEM_ADDR 0x0
+
+/* ---- Reg addressing (within block) */
+#define OFEM_REG_ADDR_BIT_L 2
+#define OFEM_REG_ADDR_BIT_H 5
+#define OFEM_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000
+#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31
+#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004
+#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31
+#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018
+#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31
+#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c
+#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
+
+#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
--- /dev/null
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_sc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_SC_AUTO_H
+#define HAL_KA_SC_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'scan'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define SCAN_BLOCK_ADDR_BIT_L 7
+#define SCAN_BLOCK_ADDR_BIT_H 9
+#define SCAN_BLOCK_ADDR_WIDTH 3
+
+#define SCAN_ADDR 0x0
+
+/* ---- Reg addressing (within block) */
+#define SCAN_REG_ADDR_BIT_L 2
+#define SCAN_REG_ADDR_BIT_H 6
+#define SCAN_REG_ADDR_WIDTH 5
+
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000
+#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31
+#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004
+#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31
+#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008
+#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31
+#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c
+#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31
+#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038
+#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c
+#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040
+#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044
+#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054
+#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31
+#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
+
+#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
--- /dev/null
+/*
+* Copyright (C) 2005 Sandburst Corporation
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+/*
+ * Ported from Ebony init.S by Travis B. Sawyer
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbtab_end
--- /dev/null
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "karef.h"
+#include "karef_version.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/sb_common.h"
+#include "../common/ppc440gx_i2c.h"
+
+void fpga_init (void);
+
+KAREF_BOARD_ID_ST board_id_as[] =
+{
+ {"Undefined"}, /* Not specified */
+ {"Kamino Reference Design"},
+ {"Reserved"}, /* Reserved for future use */
+ {"Reserved"}, /* Reserved for future use */
+};
+
+KAREF_BOARD_ID_ST ofem_board_id_as[] =
+{
+ {"Undefined"},
+ {"1x10 + 10x2"},
+ {"Reserved"},
+ {"Reserved"},
+};
+
+/*************************************************************************
+ * board_early_init_f
+ *
+ * Setup chip selects, initialize the Opto-FPGA, initialize
+ * interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ /* Enable GPIO interrupts */
+ mtsdr(sdr_pfc0, 0x00103E00);
+
+ /* Setup access for LEDs, and system topology info */
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+ gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+ gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
+
+ /* Turn on all the leds for now */
+ gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+ /*--------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------*/
+ mtebc(xbcfg,
+ EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
+ EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+ EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+ EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
+ EBC_CFG_PR_32);
+
+ /*--------------------------------------------------------------------+
+ | 1/2 MB FLASH. Initialize bank 0 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb0ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+ /*--------------------------------------------------------------------+
+ | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb1ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb2ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | KaRef Scan FPGA. Initialize bank 3 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb5ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | MAC A & B for Kamino. OFEM FPGA decodes the addresses
+ | Initialize bank 4 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb4ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+ EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | OFEM FPGA Initialize bank 5 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb3ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+
+ mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb6ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | BME-32. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb7ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ * Setup the interrupt controller polarities, triggers, etc.
+ +-------------------------------------------------------------------*/
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non- critical */
+ mtdcr (uic0pr, 0xfffffe03); /* polarity */
+ mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
+ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+ mtdcr (uic1er, 0x00000000); /* disable all */
+ mtdcr (uic1cr, 0x00000000); /* all non-critical */
+ mtdcr (uic1pr, 0xffffc8ff); /* polarity */
+ mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+ mtdcr (uic2er, 0x00000000); /* disable all */
+ mtdcr (uic2cr, 0x00000000); /* all non-critical */
+ mtdcr (uic2pr, 0xffff83ff); /* polarity */
+ mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr (uicb0sr, 0xfc000000); /* clear all */
+ mtdcr (uicb0er, 0x00000000); /* disable all */
+ mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+ mtdcr (uicb0pr, 0xfc000000);
+ mtdcr (uicb0tr, 0x00000000);
+ mtdcr (uicb0vr, 0x00000001);
+
+ fpga_init();
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * checkboard
+ *
+ * Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+ unsigned char brd_rev, brd_id;
+ unsigned short sernum;
+ unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
+ unsigned char ofem_brd_rev, ofem_brd_id;
+ KAREF_FPGA_REGS_ST *karef_ps;
+ OFEM_FPGA_REGS_ST *ofem_ps;
+
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+
+ scan_id = (unsigned char)((karef_ps->revision_ul &
+ SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
+ >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
+
+ scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
+ >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
+
+ brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
+
+ brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
+
+ ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+
+ ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
+
+ if (0xF != ofem_brd_id) {
+ ofem_id = (unsigned char)((ofem_ps->revision_ul &
+ SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
+ >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
+
+ ofem_rev = (unsigned char)((ofem_ps->revision_ul &
+ SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
+ >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
+ }
+
+ get_sys_info (&sysinfo);
+
+ sernum = sbcommon_get_serial_number();
+
+ printf ("Board: Sandburst Corporation Kamino Reference Design "
+ "Serial Number: %d\n", sernum);
+ printf ("%s\n", KAREF_U_BOOT_REL_STR);
+
+ printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+ if (sbcommon_get_master()) {
+ printf("Slot 0 - Master\nSlave board");
+ if (sbcommon_secondary_present())
+ printf(" present\n");
+ else
+ printf(" not detected\n");
+ } else {
+ printf("Slot 1 - Slave\n\n");
+ }
+
+ printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
+ printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
+ if(0xF != ofem_brd_id) {
+ printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
+ printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
+ }
+
+ printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+ /* Fix the ack in the bme 32 */
+ udelay(5000);
+ out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+ asm("eieio");
+
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_f
+ *
+ * Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+ /* Turn on i2c bus 1 */
+ puts ("I2C1: ");
+ i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ puts ("ready\n");
+
+ /* Turn on fans 3 & 4 */
+ sbcommon_fans();
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_r
+ *
+ * Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+ unsigned short sernum;
+ char envstr[255];
+ KAREF_FPGA_REGS_ST *karef_ps;
+ OFEM_FPGA_REGS_ST *ofem_ps;
+ unsigned char ofem_id;
+
+ if(NULL != getenv("secondserial")) {
+ puts("secondserial is set, switching to second serial port\n");
+ setenv("stderr", "serial1");
+ setenv("stdout", "serial1");
+ setenv("stdin", "serial1");
+ }
+
+ setenv("ubrelver", KAREF_U_BOOT_REL_STR);
+
+ memset(envstr, 0, 255);
+ sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+ setenv("bldstr", envstr);
+ saveenv();
+
+ if( getenv("autorecover")) {
+ setenv("autorecover", NULL);
+ saveenv();
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for automatic filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+ sernum, sernum);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type allow the system to continue to boot\n");
+ }
+
+ if( getenv("fakeled")) {
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+ ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
+ karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
+ setenv("bootdelay", "-1");
+ saveenv();
+ printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+ }
+
+ return (0);
+}
+
+/*************************************************************************
+ * ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+ KAREF_FPGA_REGS_ST *karef_ps;
+ /* TODO: ide reset */
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+
+ if (on) {
+ karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+ } else {
+ karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ * fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+ KAREF_FPGA_REGS_ST *karef_ps;
+ OFEM_FPGA_REGS_ST *ofem_ps;
+ unsigned char ofem_id;
+ unsigned long tmp;
+
+ /* Ensure we have power all around */
+ udelay(500);
+
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ tmp =
+ SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
+
+ karef_ps->reset_ul = tmp;
+
+ /*
+ * Wait a bit to allow the ofem fpga to get its brains
+ */
+ udelay(5000);
+
+ /*
+ * Check to see if the ofem is there
+ */
+ ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+ if(0xF != ofem_id) {
+ tmp =
+ SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
+ SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
+ SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
+
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+ ofem_ps->reset_ul = tmp;
+
+ ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
+ }
+
+ karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
+
+ asm("eieio");
+
+ return;
+}
+
+int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ memset(envstr, 0, 255);
+ /*
+ * Setup our ip address
+ */
+ sprintf(envstr, "10.100.70.%d", sernum);
+
+ setenv("ipaddr", envstr);
+ /*
+ * Setup the host ip address
+ */
+ setenv("serverip", "10.100.17.10");
+
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+ "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
+ "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
+ "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
+ sernum, sernum, sernum);
+
+ setenv("bootargs_nfs", envstr);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup CF bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+ "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+ sernum, sernum);
+
+ setenv("bootargs_cf", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
+ setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
+
+ /*
+ * Setup compact flash boot command
+ */
+ setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
+
+ saveenv();
+
+ return(1);
+}
+
+int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
+ sernum, sernum);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+
+ setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
+ " please type fsrecover.sh<cr>\n");
+
+ return(1);
+}
+
+U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
+ "kasetup - Set environment to factory defaults\n", NULL);
+
+U_BOOT_CMD(karecover, 1, 1, karefRecover,
+ "karecover - Set environment to allow for fs recovery\n", NULL);
--- /dev/null
+#ifndef __KAREF_H__
+#define __KAREF_H__
+/*
+ * (C) Copyright 2005
+ * Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Ka Reference Design OFEM FPGA Registers & definitions */
+#include "hal_ka_sc_auto.h"
+#include "hal_ka_of_auto.h"
+
+typedef struct karef_board_id_s {
+ const char name[40];
+} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
+
+/* SCAN FPGA */
+typedef struct karef_fpga_regs_s
+{
+ volatile unsigned long revision_ul; /* Read Only */
+ volatile unsigned long reset_ul; /* Read/Write */
+ volatile unsigned long interrupt_ul; /* Read Only */
+ volatile unsigned long mask_ul; /* Read/Write */
+ volatile unsigned long scratch_ul; /* Read/Write */
+ volatile unsigned long scrmask_ul; /* Read/Write */
+ volatile unsigned long status_ul; /* Read Only */
+ volatile unsigned long control_ul; /* Read/Write */
+ volatile unsigned long boardinfo_ul; /* Read Only */
+ volatile unsigned long scan_from0_ul; /* Read Only */
+ volatile unsigned long scan_from1_ul; /* Read Only */
+ volatile unsigned long scan_to0_ul; /* Read/Write */
+ volatile unsigned long scan_to1_ul; /* Read/Write */
+ volatile unsigned long scan_control_ul; /* Read/Write */
+ volatile unsigned long pll_control_ul; /* Read/Write */
+ volatile unsigned long core_clock_cnt_ul; /* Read/Write */
+ volatile unsigned long dr_clock_cnt_ul; /* Read/Write */
+ volatile unsigned long spi_clock_cnt_ul; /* Read/Write */
+ volatile unsigned long brdout_data_ul; /* Read/Write */
+ volatile unsigned long brdout_enable_ul; /* Read/Write */
+ volatile unsigned long brdin_data_ul; /* Read Only */
+ volatile unsigned long misc_ul; /* Read/Write */
+} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST;
+
+/* OFEM FPGA */
+typedef struct ofem_fpga_regs_s
+{
+ volatile unsigned long revision_ul; /* Read Only */
+ volatile unsigned long reset_ul; /* Read/Write */
+ volatile unsigned long interrupt_ul; /* Read Only */
+ volatile unsigned long mask_ul; /* Read/Write */
+ volatile unsigned long scratch_ul; /* Read/Write */
+ volatile unsigned long scrmask_ul; /* Read/Write */
+ volatile unsigned long control_ul; /* Read/Write */
+ volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
+} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST;
+
+
+#endif /* __KAREF_H__ */
--- /dev/null
+#ifndef _KAREF_VERSION_H_
+#define _KAREF_VERSION_H_
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/sandburst/karef/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
/*
- * (C) Copyright 2002-2004
+ * (C) Copyright 2002-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
*
* See file CREDITS for list of people who contributed to this
* project.
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
+ .rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
+ .rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/ocotea/init.o (.text)
+ board/sandburst/karef/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
--- /dev/null
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+ ../common/sb_common.o
+SOBJS = init.o
+
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/* ****************************************************************
+ * Common defs for reg spec for chip xc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_XC_AUTO_H
+#define HAL_XC_AUTO_H
+
+/* ----------------------------------------------------------------
+ * For block: 'xcvr_cntl'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
+#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
+#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
+
+#define XCVR_CNTL_ADDR 0x0
+
+/* ---- Reg addressing (within block) */
+#define XCVR_CNTL_REG_ADDR_BIT_L 2
+#define XCVR_CNTL_REG_ADDR_BIT_H 5
+#define XCVR_CNTL_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000
+#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004
+#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008
+#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c
+#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020
+#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024
+#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
+
+#endif /* matches #ifndef HAL_XC_AUTO_H */
--- /dev/null
+/*
+* Copyright (C) 2005
+* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbtab_end
--- /dev/null
+/*
+ * Copyright (c) 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "metrobox.h"
+#include "metrobox_version.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/ppc440gx_i2c.h"
+#include "../common/sb_common.h"
+
+void fpga_init (void);
+
+METROBOX_BOARD_ID_ST board_id_as[] =
+{ {"Undefined"}, /* Not specified */
+ {"2x10Gb"}, /* 2 ports, 10 GbE */
+ {"20x1Gb"}, /* 20 ports, 1 GbE */
+ {"Reserved"}, /* Reserved for future use */
+};
+
+/*************************************************************************
+ * board_early_init_f
+ *
+ * Setup chip selects, initialize the Opto-FPGA, initialize
+ * interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ /* Enable GPIO interrupts */
+ mtsdr(sdr_pfc0, 0x00103E00);
+
+ /* Setup access for LEDs, and system topology info */
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+ gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+ gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
+
+ /* Turn on all the leds for now */
+ gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+ /*--------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------*/
+ mtebc(xbcfg,
+ EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
+ EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+ EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+ EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
+ EBC_CFG_PR_32);
+
+ /*--------------------------------------------------------------------+
+ | 1/2 MB FLASH. Initialize bank 0 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb0ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+ /*--------------------------------------------------------------------+
+ | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb1ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb2ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | OPTO & OFEM FPGA. Initialize bank 3 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb3ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | MAC A for metrobox
+ | MAC A & B for Kamino. OFEM FPGA decodes the addresses
+ | Initialize bank 4 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb4ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | Metrobox MAC B Initialize bank 5 with default values.
+ | KA REF FPGA Initialize bank 5 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb5ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb6ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | BME-32. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb7ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ * Setup the interrupt controller polarities, triggers, etc.
+ +-------------------------------------------------------------------*/
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non- critical */
+ mtdcr (uic0pr, 0xfffffe03); /* polarity */
+ mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
+ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+ mtdcr (uic1er, 0x00000000); /* disable all */
+ mtdcr (uic1cr, 0x00000000); /* all non-critical */
+ mtdcr (uic1pr, 0xffffc8ff); /* polarity */
+ mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+ mtdcr (uic2er, 0x00000000); /* disable all */
+ mtdcr (uic2cr, 0x00000000); /* all non-critical */
+ mtdcr (uic2pr, 0xffff83ff); /* polarity */
+ mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr (uicb0sr, 0xfc000000); /* clear all */
+ mtdcr (uicb0er, 0x00000000); /* disable all */
+ mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+ mtdcr (uicb0pr, 0xfc000000);
+ mtdcr (uicb0tr, 0x00000000);
+ mtdcr (uicb0vr, 0x00000001);
+
+ fpga_init();
+
+ return 0;
+}
+
+/*************************************************************************
+ * checkboard
+ *
+ * Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+ unsigned char brd_rev, brd_id;
+ unsigned short sernum;
+ unsigned char opto_rev, opto_id;
+ OPTO_FPGA_REGS_ST *opto_ps;
+
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ opto_rev = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+ opto_id = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
+
+ brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
+ SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
+
+ brd_id = (unsigned char)((opto_ps->boardinfo_ul &
+ SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
+
+ get_sys_info (&sysinfo);
+
+ sernum = sbcommon_get_serial_number();
+ printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
+ printf ("%s\n", METROBOX_U_BOOT_REL_STR);
+
+ printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+ if (sbcommon_get_master()) {
+ printf("Slot 0 - Master\nSlave board");
+ if (sbcommon_secondary_present())
+ printf(" present\n");
+ else
+ printf(" not detected\n");
+ } else {
+ printf("Slot 1 - Slave\n\n");
+ }
+
+ printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
+ printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
+
+ printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+
+ /* Fix the ack in the bme 32 */
+ udelay(5000);
+ out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+ asm("eieio");
+
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_f
+ *
+ * Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+ /* Turn on i2c bus 1 */
+ puts ("I2C1: ");
+ i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ puts ("ready\n");
+
+ /* Turn on fans */
+ sbcommon_fans();
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_r
+ *
+ * Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+ unsigned short sernum;
+ char envstr[255];
+ unsigned char opto_rev;
+ OPTO_FPGA_REGS_ST *opto_ps;
+
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ if(NULL != getenv("secondserial")) {
+ puts("secondserial is set, switching to second serial port\n");
+ setenv("stderr", "serial1");
+ setenv("stdout", "serial1");
+ setenv("stdin", "serial1");
+ }
+
+ setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
+
+ memset(envstr, 0, 255);
+ sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+ setenv("bldstr", envstr);
+ saveenv();
+
+ if( getenv("autorecover")) {
+ setenv("autorecover", NULL);
+ saveenv();
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for automatic filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+ sernum, sernum);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type allow the system to continue to boot\n");
+ }
+
+ if( getenv("fakeled")) {
+ setenv("bootdelay", "-1");
+ saveenv();
+ printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+ opto_rev = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+ if(0x12 <= opto_rev) {
+ opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
+ }
+ }
+
+ return (0);
+}
+
+/*************************************************************************
+ * ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+ OPTO_FPGA_REGS_ST *opto_ps;
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ if (on) { /* assert RESET */
+ opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+ } else { /* release RESET */
+ opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ * fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+ OPTO_FPGA_REGS_ST *opto_ps;
+ unsigned char opto_rev;
+ unsigned long tmp;
+
+ /* Ensure we have power all around */
+ udelay(500);
+
+ /*
+ * Take appropriate hw bits out of reset
+ */
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ tmp =
+ SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
+ opto_ps->reset_ul = tmp;
+ /*
+ * Turn on the 'Slow Blink' for the System Error Led.
+ * Ensure FPGA rev is up to at least rev 0x12
+ */
+ opto_rev = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+ if(0x12 <= opto_rev) {
+ opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
+ }
+
+ asm("eieio");
+
+ return;
+}
+
+int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ memset(envstr, 0, 255);
+ /*
+ * Setup our ip address
+ */
+ sprintf(envstr, "10.100.60.%d", sernum);
+
+ setenv("ipaddr", envstr);
+ /*
+ * Setup the host ip address
+ */
+ setenv("serverip", "10.100.17.10");
+
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+ "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
+ "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
+ ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
+ sernum, sernum, sernum);
+
+ setenv("bootargs_nfs", envstr);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup CF bootargs
+ */
+ memset(envstr, 0, 255);
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+ "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+ sernum, sernum);
+
+ setenv("bootargs_cf", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
+ setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
+
+ /*
+ * Setup compact flash boot command
+ */
+ setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
+
+ saveenv();
+
+
+ return(1);
+}
+
+int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
+ sernum, sernum);
+
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
+ " please type fsrecover.sh<cr>\n");
+
+ return(1);
+}
+
+U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
+ "mbsetup - Set environment to factory defaults\n", NULL);
+
+U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
+ "mbrecover - Set environment to allow for fs recovery\n", NULL);
--- /dev/null
+#ifndef __METROBOX_H__
+#define __METROBOX_H__
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef struct metrobox_board_id_s {
+ const char name[40];
+} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
+
+
+/* Metrobox Opto-FPGA registers and definitions */
+#include "hal_xc_auto.h"
+typedef struct opto_fpga_regs_s {
+ volatile unsigned long revision_ul; /* Read Only */
+ volatile unsigned long reset_ul; /* Read/Write */
+ volatile unsigned long status_ul; /* Read Only */
+ volatile unsigned long interrupt_ul; /* Read Only */
+ volatile unsigned long mask_ul; /* Read/Write */
+ volatile unsigned long scratch_ul; /* Read/Write */
+ volatile unsigned long scrmask_ul; /* Read/Write */
+ volatile unsigned long control_ul; /* Read/Write */
+ volatile unsigned long boardinfo_ul; /* Read Only */
+} OPTO_FPGA_REGS_ST __attribute__ ((packed)), *OPTO_FPGA_REGS_PST;
+
+#endif /* __METROBOX_H__ */
--- /dev/null
+#ifndef _METROBOX_VERSION_H_
+#define _METROBOX_VERSION_H_
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/sandburst/metrobox/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/sandburst/metrobox/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* common/environment.o(.text) */
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
TEXT_BASE = 0xfffc0000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
return (size_sdram);
}
-
-#ifdef CFG_JFFS_CUSTOM_PART
-
-static struct part_info part;
-
-#define jffs2_block(i) \
- ((struct jffs2_unknown_node*)(CFG_JFFS2_BASE + (i) * 65536))
-
-struct part_info* jffs2_part_info(int part_num)
-{
- DECLARE_GLOBAL_DATA_PTR;
- bd_t *bd = gd->bd;
- char* s;
- int i;
- int bootnor = 0; /* assume booting from NAND flash */
-
- if (part_num != 0)
- return 0; /* only support one partition */
-
- if (part.usr_priv == (void*)1)
- return ∂ /* already have part info */
-
- memset(&part, 0, sizeof(part));
-
- if (nand_dev_desc[0].ChipID == NAND_ChipID_UNKNOWN)
- bootnor = 1;
- else if (bd->bi_flashsize < 0x800000)
- bootnor = 0;
- else for (i = 0; !bootnor && i < 4; ++i) {
- /* boot from NOR if JFFS2 info in any of
- * first 4 erase blocks
- */
-
- if (jffs2_block(i)->magic == JFFS2_MAGIC_BITMASK)
- bootnor = 1;
- }
-
- if (bootnor) {
- /* no NAND flash or boot in NOR, use NOR flash */
- part.offset = (unsigned char *)CFG_JFFS2_BASE;
- part.size = CFG_JFFS2_SIZE;
- }
- else {
- char readcmd[60];
-
- /* boot info in NAND flash, get and use copy in RAM */
-
- /* override info from environment if present */
- s = getenv("fsaddr");
- part.offset = s ? (void *)simple_strtoul(s, NULL, 16)
- : (void *)CFG_JFFS2_RAMBASE;
- s = getenv("fssize");
- part.size = s ? simple_strtoul(s, NULL, 16)
- : CFG_JFFS2_RAMSIZE;
-
- /* read from nand flash */
- sprintf(readcmd, "nand read.jffs2 %x 0 %x",
- (uint32_t)part.offset, part.size);
- run_command(readcmd, 0);
- }
-
- part.erasesize = 0; /* unused */
- part.usr_priv=(void*)1; /* ready */
-
- return ∂
-}
-#endif /* ifdef CFG_JFFS_CUSTOM_PART */
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
cpu/mpc85xx/ether_fcc.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# STx XTc
+#
+
+TEXT_BASE = 0x40F00000
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2005
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * U-Boot port on STx XTc board
+ * Mostly copied from Netta
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b) (1U << (31-(_b)))
+#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b) (1U << (15-(_b)))
+#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b) (1U << (7-(_b)))
+#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b) _BD(_b)
+#define _BR(_l, _h) _BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+ printf ("Silicon Turnkey eXpress XTc\n");
+ return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000 0x00000000
+#define CS_0001 0x10000000
+#define CS_0010 0x20000000
+#define CS_0011 0x30000000
+#define CS_0100 0x40000000
+#define CS_0101 0x50000000
+#define CS_0110 0x60000000
+#define CS_0111 0x70000000
+#define CS_1000 0x80000000
+#define CS_1001 0x90000000
+#define CS_1010 0xA0000000
+#define CS_1011 0xB0000000
+#define CS_1100 0xC0000000
+#define CS_1101 0xD0000000
+#define CS_1110 0xE0000000
+#define CS_1111 0xF0000000
+
+#define BS_0000 0x00000000
+#define BS_0001 0x01000000
+#define BS_0010 0x02000000
+#define BS_0011 0x03000000
+#define BS_0100 0x04000000
+#define BS_0101 0x05000000
+#define BS_0110 0x06000000
+#define BS_0111 0x07000000
+#define BS_1000 0x08000000
+#define BS_1001 0x09000000
+#define BS_1010 0x0A000000
+#define BS_1011 0x0B000000
+#define BS_1100 0x0C000000
+#define BS_1101 0x0D000000
+#define BS_1110 0x0E000000
+#define BS_1111 0x0F000000
+
+#define GPL0_AAAA 0x00000000
+#define GPL0_AAA0 0x00200000
+#define GPL0_AAA1 0x00300000
+#define GPL0_000A 0x00800000
+#define GPL0_0000 0x00A00000
+#define GPL0_0001 0x00B00000
+#define GPL0_111A 0x00C00000
+#define GPL0_1110 0x00E00000
+#define GPL0_1111 0x00F00000
+
+#define GPL1_0000 0x00000000
+#define GPL1_0001 0x00040000
+#define GPL1_1110 0x00080000
+#define GPL1_1111 0x000C0000
+
+#define GPL2_0000 0x00000000
+#define GPL2_0001 0x00010000
+#define GPL2_1110 0x00020000
+#define GPL2_1111 0x00030000
+
+#define GPL3_0000 0x00000000
+#define GPL3_0001 0x00004000
+#define GPL3_1110 0x00008000
+#define GPL3_1111 0x0000C000
+
+#define GPL4_0000 0x00000000
+#define GPL4_0001 0x00001000
+#define GPL4_1110 0x00002000
+#define GPL4_1111 0x00003000
+
+#define GPL5_0000 0x00000000
+#define GPL5_0001 0x00000400
+#define GPL5_1110 0x00000800
+#define GPL5_1111 0x00000C00
+#define LOOP 0x00000080
+
+#define EXEN 0x00000040
+
+#define AMX_COL 0x00000000
+#define AMX_ROW 0x00000020
+#define AMX_MAR 0x00000030
+
+#define NA 0x00000008
+
+#define UTA 0x00000004
+
+#define TODT 0x00000002
+
+#define LAST 0x00000001
+
+#define A10_AAAA GPL0_AAAA
+#define A10_AAA0 GPL0_AAA0
+#define A10_AAA1 GPL0_AAA1
+#define A10_000A GPL0_000A
+#define A10_0000 GPL0_0000
+#define A10_0001 GPL0_0001
+#define A10_111A GPL0_111A
+#define A10_1110 GPL0_1110
+#define A10_1111 GPL0_1111
+
+#define RAS_0000 GPL1_0000
+#define RAS_0001 GPL1_0001
+#define RAS_1110 GPL1_1110
+#define RAS_1111 GPL1_1111
+
+#define CAS_0000 GPL2_0000
+#define CAS_0001 GPL2_0001
+#define CAS_1110 GPL2_1110
+#define CAS_1111 GPL2_1111
+
+#define WE_0000 GPL3_0000
+#define WE_0001 GPL3_0001
+#define WE_1110 GPL3_1110
+#define WE_1111 GPL3_1111
+
+/* #define CAS_LATENCY 3 */
+#define CAS_LATENCY 2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+ /* RSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_,
+
+ /* RBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+ /* RSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+
+ /* RBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WSS */
+ CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
+ CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_,
+
+ /* WBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
+ CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+
+#endif
+
+ /* UPT */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+
+ /* EXC */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+ _NOT_USED_,
+
+ /* REG */
+ CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+ CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+static const uint nandcs_table[0x40] = {
+ /* RSS */
+ CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_0000 | GPL5_1111,
+ CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+ CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
+
+ /* RBS */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WSS */
+ CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_1111,
+ CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+ /* WBS */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* UPT */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* EXC */
+ CS_0001 | LAST,
+ _NOT_USED_,
+
+ /* REG */
+ CS_1110 ,
+ CS_0001 | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 9 */
+#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+ unsigned int i, j, v, vv;
+ volatile unsigned int *p;
+ unsigned int pv;
+
+ p = (unsigned int *)addr;
+ pv = (unsigned int)p;
+ for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+ *p++ = pv;
+
+ p = (unsigned int *)addr;
+ for (i = 0; i < size / sizeof(unsigned int); i++) {
+ v = (unsigned int)p;
+ vv = *p;
+ if (vv != v) {
+ printf("%p: read %08x instead of %08x\n", p, vv, v);
+ hang();
+ }
+ p++;
+ }
+
+ for (j = 0; j < 5; j++) {
+ switch (j) {
+ case 0: v = 0x00000000; break;
+ case 1: v = 0xffffffff; break;
+ case 2: v = 0x55555555; break;
+ case 3: v = 0xaaaaaaaa; break;
+ default:v = 0xdeadbeef; break;
+ }
+ p = (unsigned int *)addr;
+ for (i = 0; i < size / sizeof(unsigned int); i++) {
+ *p = v;
+ vv = *p;
+ if (vv != v) {
+ printf("%p: read %08x instead of %08x\n", p, vv, v);
+ hang();
+ }
+ *p = ~v;
+ p++;
+ }
+ }
+}
+
+#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
+
+long int initdram(int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size;
+ u32 d1, d2;
+
+ upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+ /*
+ * Preliminary prescaler for refresh
+ */
+ memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+ memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or4 = CFG_OR4_PRELIM;
+ memctl->memc_br4 = CFG_BR4_PRELIM;
+
+ memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
+
+ udelay(200);
+
+ /* perform SDRAM initialisation sequence */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
+ udelay(1);
+
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
+ udelay(1);
+
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
+ udelay(1);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay(10000);
+
+
+ d1 = 0xAA55AA55;
+ *(volatile u32 *)0 = d1;
+ d2 = *(volatile u32 *)0;
+ if (d1 != d2) {
+ printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+ DO_LOOP;
+ }
+
+ d1 = 0x55AA55AA;
+ *(volatile u32 *)0 = d1;
+ d2 = *(volatile u32 *)0;
+ if (d1 != d2) {
+ printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+ DO_LOOP;
+ }
+
+ d1 = 0x12345678;
+ *(volatile u32 *)0 = d1;
+ d2 = *(volatile u32 *)0;
+ if (d1 != d2) {
+ printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+ DO_LOOP;
+ }
+
+ size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+ return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+ int phyno;
+ unsigned short v;
+
+ udelay(10000);
+ /* reset the damn phys */
+ mii_init();
+
+ for (phyno = 0; phyno < 32; ++phyno) {
+ miiphy_read(phyno, PHY_PHYIDR1, &v);
+ if (v == 0xFFFF)
+ continue;
+ miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+ udelay(10000);
+ miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ udelay(10000);
+ }
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK _BW(6)
+#define PA_GP_OUTMASK (_BW(7))
+#define PA_SP_MASK 0
+#define PA_ODR_VAL 0
+#define PA_GP_OUTVAL (_BW(7))
+#define PA_SP_DIRVAL 0
+
+#define PB_GP_INMASK 0
+#define PB_GP_OUTMASK (_B(23))
+#define PB_SP_MASK 0
+#define PB_ODR_VAL 0
+#define PB_GP_OUTVAL (_B(23))
+#define PB_SP_DIRVAL 0
+
+#define PC_GP_INMASK 0
+#define PC_GP_OUTMASK (_BW(15))
+
+#define PC_SP_MASK 0
+#define PC_SOVAL 0
+#define PC_INTVAL 0
+#define PC_GP_OUTVAL 0
+#define PC_SP_DIRVAL 0
+
+#define PE_GP_INMASK 0
+#define PE_GP_OUTMASK 0
+#define PE_GP_OUTVAL 0
+
+#define PE_SP_MASK 0
+#define PE_ODR_VAL 0
+#define PE_SP_DIRVAL 0
+
+int board_early_init_f(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile iop8xx_t *ioport = &immap->im_ioport;
+ volatile cpm8xx_t *cpm = &immap->im_cpm;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ (void)ioport;
+ (void)cpm;
+#if 1
+ /* NAND chip select */
+ upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+ memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+ memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
+ memctl->memc_mbmr = 0; /* all clear */
+#endif
+
+ memctl->memc_br5 &= ~BR_V;
+ memctl->memc_br6 &= ~BR_V;
+ memctl->memc_br7 &= ~BR_V;
+
+#if 1
+ ioport->iop_padat = PA_GP_OUTVAL;
+ ioport->iop_paodr = PA_ODR_VAL;
+ ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
+ ioport->iop_papar = PA_SP_MASK;
+
+ cpm->cp_pbdat = PB_GP_OUTVAL;
+ cpm->cp_pbodr = PB_ODR_VAL;
+ cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
+ cpm->cp_pbpar = PB_SP_MASK;
+
+ ioport->iop_pcdat = PC_GP_OUTVAL;
+ ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
+ ioport->iop_pcso = PC_SOVAL;
+ ioport->iop_pcint = PC_INTVAL;
+ ioport->iop_pcpar = PC_SP_MASK;
+
+ cpm->cp_pedat = PE_GP_OUTVAL;
+ cpm->cp_peodr = PE_ODR_VAL;
+ cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
+ cpm->cp_pepar = PE_SP_MASK;
+#endif
+
+ return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+ unsigned long totlen;
+
+ totlen = nand_probe(CFG_NAND_BASE);
+ printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+ /* XXX add here the really funky stuff */
+}
+
+#endif
+
+#ifdef CONFIG_SHOW_ACTIVITY
+
+/* called from timer interrupt every 1/CFG_HZ sec */
+void board_show_activity(ulong timestamp)
+{
+}
+
+/* called when looping */
+void show_activity(int arg)
+{
+}
+
+#endif
+
+#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+ /* printf("overwrite_console called\n"); */
+ return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ reset_phys();
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ common/dlmalloc.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ . = env_offset;
common/environment.o(.text)
*(.text)
int checkboard (void)
{
+#if defined (CONFIG_AEVFIFO)
+ puts ("Board: AEVFIFO\n");
+ return 0;
+#endif
#if defined (CONFIG_TQM5200_AA)
puts ("Board: TQM5200-AA (TQ-Components GmbH)\n");
#elif defined (CONFIG_TQM5200_AB)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
#include <common.h>
#include <mpc8xx.h>
#include <i2c.h>
+#include <miiphy.h>
/*********************************************************************/
val |= 0x80;
i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);
+ /*
+ * Configure PHY to setup LED's correctly and use 100MBit, FD
+ */
+ mii_init();
+
+ miiphy_write(0, PHY_BMCR, 0x2100); /* disable auto-negotiation, 100mbit, full-duplex */
+ miiphy_write(0, PHY_FCSCR, 0x4122); /* set LED's to Link, Transmit, Receive */
+
return 0;
}
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
all: $(LIB) eeprom.srec eeprom.bin
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
-eeprom.srec: eeprom.o
- $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \
+eeprom.srec: eeprom.o eeprom_start.o
+ $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+ -o $(<:.o=) -e $(<:.o=) $^ \
-L../../examples -lstubs \
-L../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
eeprom.bin: eeprom.srec
- $(OBJCOPY) -O binary $< $@ 2>/dev/null
+ $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
clean:
rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-static int verify_macaddr(char *);
-static int set_mac(char *);
-
-int eeprom(int argc, char *argv[])
-{
- app_startup(argv);
- if (get_version() != XF_VERSION) {
- printf("Wrong XF_VERSION.\n");
- printf("Application expects ABI version %d\n", XF_VERSION);
- printf("Actual U-Boot ABI version %d\n", (int)get_version());
- return 1;
- }
-
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
- printf("SMSC91111 not found.\n");
- return 2;
- }
-
- if (argc != 2) {
- printf("VoiceBlue EEPROM writer\n");
- printf("Built: %s at %s\n", __DATE__ , __TIME__ );
- printf("Usage:\n\t<mac_address>");
- return 3;
- }
-
- set_mac(argv[1]);
- if (verify_macaddr(argv[1])) {
- printf("*** ERROR ***\n");
- return 4;
- }
-
- return 0;
-}
-
static u16 read_eeprom_reg(u16 reg)
{
int timeout;
return 1;
}
+static int write_data(u16 *buf, int len)
+{
+ u16 reg = 0x23;
+
+ while (len--)
+ write_eeprom_reg(*buf++, reg++);
+
+ return 0;
+}
+
static int verify_macaddr(char *s)
{
u16 reg;
int i, err = 0;
- printf("Verifying MAC Address: ");
+ printf("MAC Address: ");
err = i = 0;
for (i = 0; i < 3; i++) {
reg = read_eeprom_reg(0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
- err |= reg != ((u16 *)s)[i];
+ if (s)
+ err |= reg != ((u16 *)s)[i];
}
return err ? 0 : 1;
return 0;
}
+
+static int parse_element(char *s, unsigned char *buf, int len)
+{
+ int cnt;
+ char *p, num[3];
+ unsigned char id;
+
+ id = simple_strtoul(s, &p, 16);
+ if (*p++ != ':')
+ return -1;
+ cnt = 2;
+ num[2] = 0;
+ for (; *p; p += 2) {
+ if (p[1] == 0)
+ return -2;
+ if (cnt + 3 > len)
+ return -3;
+ num[0] = p[0];
+ num[1] = p[1];
+ buf[cnt++] = simple_strtoul(num, NULL, 16);
+ }
+ buf[0] = id;
+ buf[1] = cnt - 2;
+
+ return cnt;
+}
+
+int eeprom(int argc, char *argv[])
+{
+ int i, len, ret;
+ unsigned char buf[58], *p;
+
+ app_startup(argv);
+ if (get_version() != XF_VERSION) {
+ printf("Wrong XF_VERSION.\n");
+ printf("Application expects ABI version %d\n", XF_VERSION);
+ printf("Actual U-Boot ABI version %d\n", (int)get_version());
+ return 1;
+ }
+
+ if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ printf("SMSC91111 not found.\n");
+ return 2;
+ }
+
+ /* Called without parameters - print MAC address */
+ if (argc < 2) {
+ verify_macaddr(NULL);
+ return 0;
+ }
+
+ /* Print help message */
+ if (argv[1][1] == 'h') {
+ printf("VoiceBlue EEPROM writer\n");
+ printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+ printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+ return 0;
+ }
+
+ /* Try to parse information elements */
+ len = sizeof(buf);
+ p = buf;
+ for (i = 2; i < argc; i++) {
+ ret = parse_element(argv[i], p, len);
+ switch (ret) {
+ case -1:
+ printf("Element %d: malformed\n", i - 1);
+ return 3;
+ case -2:
+ printf("Element %d: odd character count\n", i - 1);
+ return 3;
+ case -3:
+ printf("Out of EEPROM memory\n");
+ return 3;
+ default:
+ p += ret;
+ len -= ret;
+ }
+ }
+
+ /* First argument (MAC) is mandatory */
+ set_mac(argv[1]);
+ if (verify_macaddr(argv[1])) {
+ printf("*** MAC address does not match! ***\n");
+ return 4;
+ }
+
+ while (len--)
+ *p++ = 0;
+
+ write_data((u16 *)buf, sizeof(buf) >> 1);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = ALIGN(4);
+ .text :
+ {
+ eeprom_start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+/*
+ * Copyright (c) 2005 2N Telekomunikace
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+.globl _start
+_start: b eeprom
return 0;
}
-#ifndef VOICEBLUE_SMALL_FLASH
-
-#include <jffs2/jffs2.h>
-
-extern flash_info_t flash_info[];
-static struct part_info partinfo;
-static int current_part = -1;
-
-/* Partition table (Linux MTD see it this way)
- *
- * 0 - U-Boot
- * 1 - env
- * 2 - redundant env
- * 3 - data1 (jffs2)
- * 4 - data2 (jffs2)
- */
-
-static struct {
- ulong offset;
- ulong size;
-} part[5];
-
-static void partition_flash(flash_info_t *info)
-{
- char mtdparts[128];
- int i, n, size, psize;
- const ulong plen[3] = { CFG_MONITOR_LEN, CFG_ENV_SIZE, CFG_ENV_SIZE };
-
- size = n = 0;
- for (i = 0; i < 4; i++) {
- part[i].offset = info->start[n];
- psize = i < 3 ? plen[i] : (info->size - size) / 2;
- while (part[i].size < psize) {
- if (++n > info->sector_count) {
- printf("Partitioning error. System halted.\n");
- while (1) ;
- }
- part[i].size += info->start[n] - info->start[n - 1];
- }
- size += part[i].size;
- }
- part[4].offset = info->start[n];
- part[4].size = info->start[info->sector_count - 1] - info->start[n];
-
- sprintf(mtdparts, "omapflash.0:"
- "%dk(U-Boot)ro,%dk(env),%dk(r_env),%dk(data1),-(data2)",
- part[0].size >> 10, part[1].size >> 10,
- part[2].size >> 10, part[3].size >> 10);
- setenv ("mtdparts", mtdparts);
-}
-
-struct part_info* jffs2_part_info(int part_num)
-{
- void *jffs2_priv_saved = partinfo.jffs2_priv;
-
- if (part_num != 3 && part_num != 4)
- return NULL;
-
- if (current_part != part_num) {
- memset(&partinfo, 0, sizeof(partinfo));
- current_part = part_num;
- partinfo.offset = (char*) part[part_num].offset;
- partinfo.size = part[part_num].size;
- partinfo.usr_priv = ¤t_part;
- partinfo.jffs2_priv = jffs2_priv_saved;
- }
-
- return &partinfo;
-}
-
-#endif
-
int misc_init_r(void)
{
*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55;
-#ifndef VOICEBLUE_SMALL_FLASH
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("Unknown flash. System halted.\n");
- while (1) ;
- }
- partition_flash(&flash_info[0]);
-#endif
-
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-#ifdef CONFIG_ADCIOP
-#define ADDR0 0x0aa9
-#define ADDR1 0x0556
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_CPCI405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned short
-#endif
-
-#ifdef CONFIG_WALNUT405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Only one bank */
- if (CFG_MAX_FLASH_BANKS == 1)
- {
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM+monitor_flash_len-1,
- &flash_info[0]);
- size_b1 = 0 ;
- flash_info[0].size = size_b0;
- }
-
- /* 2 banks */
- else
- {
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1)
- {
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb0cr);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
- mtdcr(ebccfgd, pbcr);
- /* printf("pb1cr = %x\n", pbcr); */
- }
-
- if (size_b0)
- {
- mtdcr(ebccfga, pb1cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb1cr);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(ebccfgd, pbcr);
- /* printf("pb0cr = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b0+size_b0-monitor_flash_len,
- base_b0+size_b0-1,
- &flash_info[0]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b1+size_b1-monitor_flash_len,
- base_b1+size_b1-1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void)flash_protect(FLAG_PROTECT_CLEAR,
- base_b0+size_b0-monitor_flash_len,
- base_b0+size_b0-1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- }/* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)){
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-#if 0 /* test-only */
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
-#else
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " "
-#endif
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
-
-#ifdef CONFIG_ADCIOP
- value = addr2[2];
-#else
- value = addr2[0];
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- /* printf("\ndev_code=%x\n", value); */
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- case (FLASH_WORD_SIZE)SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)){
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr2[4] & 1;
-#else
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
-#endif
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile unsigned char *)info->start[0];
- addr2[ADDR0] = 0xAA;
- addr2[ADDR1] = 0x55;
- addr2[ADDR0] = 0xF0; /* reset bank */
-#else
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif
-#else /* test-only */
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif /* test-only */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7(flash_info_t *info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2); /* CLH */
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7(info, l_sect);
-
-DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*------------------------------------------------------------------------------+ */
-/* */
-/* This source code has been made available to you by IBM on an AS-IS */
-/* basis. Anyone receiving this source is licensed under IBM */
-/* copyrights to use it in any way he or she deems fit, including */
-/* copying it, modifying it, compiling it, and redistributing it either */
-/* with or without modifications. No license under IBM patents or */
-/* patent applications is to be implied by the copyright license. */
-/* */
-/* Any user of this software should understand that IBM cannot provide */
-/* technical support for this software and will not be responsible for */
-/* any consequences resulting from the use of this software. */
-/* */
-/* Any person who transfers this source code or any derivative work */
-/* must include the IBM copyright notice, this paragraph, and the */
-/* preceding two paragraphs in the transferred software. */
-/* */
-/* COPYRIGHT I B M CORPORATION 1995 */
-/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
-
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - NVRAM/RTC */
-/* Bank 2 - Keyboard/Mouse controller */
-/* Bank 3 - IR controller */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - FPGA registers */
-/*----------------------------------------------------------------------------- */
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
- /* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 0 (Flash and SRAM) initialization */
- /*----------------------------------------------------------------------- */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9B01
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr ebccfgd,r4
-
- blr
-
-
-/*----------------------------------------------------------------------------- */
-/* Function: sdram_init */
-/* Description: Dummy implementation here - done in C later */
-/*----------------------------------------------------------------------------- */
- .globl sdram_init
-sdram_init:
- blr
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include "walnut405.h"
-#include <asm/processor.h>
-#include <spd_sdram.h>
-
-int board_early_init_f (void)
-{
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the Walnut board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
- | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
- | IRQ 27 (EXT IRQ 2) Not Used
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for Walnut board:
- | An interrupt taken for the FPGA (IRQ 25) indicates that either
- | the Mouse, Keyboard, IRDA, or External Expansion caused the
- | interrupt. The FPGA must be read to determine which device
- | caused the interrupt. The default setting of the FPGA clears
- |
- +-------------------------------------------------------------------------*/
-
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
- mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
- mtdcr (uictr, 0x10000000); /* set int trigger levels */
- mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
-
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
- /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb1ap, 0x02815480);
- mtebc (pb1cr, 0xF0018000);
-
- /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb2ap, 0x04815A80);
- mtebc (pb2cr, 0xF0118000);
-
- /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb3ap, 0x01815280);
- mtebc (pb3cr, 0xF0218000);
-
- /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb7ap, 0x01815280);
- mtebc (pb7cr, 0xF0318000);
-
- /* set UART1 control to select CTS/RTS */
-#define FPGA_BRDC 0xF0300004
- *(volatile char *) (FPGA_BRDC) |= 0x1;
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
-
- puts ("Board: ");
-
- if (!s || strncmp (s, "WALNUT405", 9)) {
- puts ("### No HW ID - assuming WALNUT405");
- } else {
- for (e = s; *e; ++e) {
- if (*e == ' ')
- break;
- }
- for (; s < e; ++s) {
- putc (*s);
- }
- }
- putc ('\n');
-
- return (0);
-}
-
-
-/* -------------------------------------------------------------------------
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
- ------------------------------------------------------------------------- */
-long int initdram (int board_type)
-{
- return spd_sdram (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: xxx MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
#include <common.h>
#include <linux/byteorder/swab.h>
-#if defined CFG_JFFS_CUSTOM_PART
-#include <jffs2/jffs2.h>
-#endif
-
#define SWAP(x) __swab32(x)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
-#if defined CFG_JFFS_CUSTOM_PART
-
-/*
- * jffs2_part_info - get information about a JFFS2 partition
- *
- * @part_num: number of the partition you want to get info about
- * @return: struct part_info* in case of success, 0 if failure
- */
-
-static struct part_info part;
-static int current_part = -1;
-
-struct part_info* jffs2_part_info(int part_num) {
- void *jffs2_priv_saved = part.jffs2_priv;
-
- printf("jffs2_part_info: part_num=%i\n",part_num);
-
- if (current_part == part_num)
- return ∂
-
- /* u-boot partition */
- if(part_num==0){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00000000;
- part.size=256*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
- printf("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* primary OS+firmware partition */
- if(part_num==1){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00040000;
- part.size=1024*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
- printf("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- /* secondary OS+firmware partition */
- if(part_num==2){
- memset(&part, 0, sizeof(part));
-
- part.offset=(char*)0x00140000;
- part.size=8*1024*1024;
-
- /* Mark the struct as ready */
- current_part = part_num;
-
- printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
- printf("part.size = 0x%08x\n",(unsigned int)part.size);
- }
-
- if (current_part == part_num) {
- part.usr_priv = ¤t_part;
- part.jffs2_priv = jffs2_priv_saved;
- return ∂
- }
-
- printf("jffs2_part_info: end of partition table\n");
- return 0;
-}
-#endif
-
-
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
* available to cmd_fat.c:get_dev and filling in a block device
* description that has all the bits needed for FAT support to
* read sectors.
+ *
+ * According to Xilinx technical support, before accessing the
+ * SystemACE CF you need to set the following control bits:
+ * FORCECFGMODE : 1
+ * CFGMODE : 0
+ * CFGSTART : 0
*/
# include <common.h>
int retry = 10;
/* CONTROLREG = LOCKREG */
- ace_writew(0x0002, 0x18);
+ unsigned val=ace_readw(0x18);
+ val|=0x0002;
+ ace_writew((val&0xffff), 0x18);
/* Wait for MPULOCK in STATUSREG[15:0] */
while (! (ace_readw(0x04) & 0x0002)) {
static void release_cf_lock(void)
{
- /* CONTROLREG = none */
- ace_writew(0x0000, 0x18);
+ unsigned val=ace_readw(0x18);
+ val&=~(0x0002);
+ ace_writew((val&0xffff), 0x18);
}
block_dev_desc_t * systemace_get_dev(int dev)
systemace_dev.blksz = 512;
systemace_dev.removable = 1;
systemace_dev.block_read = systemace_read;
+
+ init_part(&systemace_dev);
+
}
return &systemace_dev;
int retry;
unsigned blk_countdown;
unsigned char*dp = (unsigned char*)buffer;
+ unsigned val;
if (get_cf_lock() < 0) {
unsigned status = ace_readw(0x04);
retry = 2000;
for (;;) {
- unsigned val = ace_readw(0x04);
+ val = ace_readw(0x04);
/* If CFDETECT is false, card is missing. */
if (! (val & 0x0010)) {
/* Write sector count | ReadMemCardData. */
ace_writew((trans&0xff) | 0x0300, 0x14);
+ /* Reset the configruation controller */
+ val = ace_readw(0x18);
+ val|=0x0080;
+ ace_writew(val, 0x18);
+
retry = trans * 16;
while (retry > 0) {
int idx;
retry -= 1;
}
+ /* Clear the configruation controller reset */
+ val = ace_readw(0x18);
+ val&=~0x0080;
+ ace_writew(val, 0x18);
+
/* Count the blocks we transfer this time. */
start += trans;
blk_countdown -= trans;
#endif
print_num ("bootflags", bd->bi_bootflags );
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300)
+ defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
-#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300 */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
+#if defined(CONFIG_CPM2)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
print_str ("brgfreq", strmhz(buf, bd->bi_brgfreq));
#endif
print_str ("intfreq", strmhz(buf, bd->bi_intfreq));
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
-#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300 */
+#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_MPC8220)
print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq));
print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq));
kbd->bi_flbfreq /= 1000000L;
kbd->bi_vcofreq /= 1000000L;
#endif
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
kbd->bi_cpmfreq /= 1000000L;
kbd->bi_brgfreq /= 1000000L;
kbd->bi_sccfreq /= 1000000L;
kbd->bi_vco /= 1000000L;
-#endif /* CONFIG_8260 */
+#endif
#if defined(CONFIG_MPC5xxx)
kbd->bi_ipbfreq /= 1000000L;
kbd->bi_pcifreq /= 1000000L;
#include <config.h>
#include <command.h>
-#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR)
+#if defined(CONFIG_4xx) && (CONFIG_COMMANDS & CFG_CMD_SETGETDCR)
/* ======================================================================
* Interpreter command to retrieve an IBM PPC 4xx Device Control Register
* ====================================================================== */
int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
-#if defined(CONFIG_WALNUT405) || \
+#if defined(CONFIG_WALNUT) || \
defined(CFG_VXWORKS_MAC_PTR)
DECLARE_GLOBAL_DATA_PTR;
#endif
* This will vary from board to board
*/
-#if defined(CONFIG_WALNUT405)
+#if defined(CONFIG_WALNUT)
tmp = (char *) CFG_NVRAM_BASE_ADDR + 0x500;
memcpy ((char *) tmp, (char *) &gd->bd->bi_enetaddr[3], 3);
#elif defined(CFG_VXWORKS_MAC_PTR)
#include <common.h>
#include <command.h>
-
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
#endif
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+#include <jffs2/jffs2.h>
+
+/* parition handling routines */
+int mtdparts_init(void);
+int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
+int find_dev_and_part(const char *id, struct mtd_device **dev,
+ u8 *part_num, struct part_info **part);
+#endif
+
extern flash_info_t flash_info[]; /* info for FLASH chips */
/*
return 1;
}
+/*
+ * This function computes the start and end addresses for both
+ * erase and protect commands. The range of the addresses on which
+ * either of the commands is to operate can be given in two forms:
+ * 1. <cmd> start end - operate on <'start', 'end')
+ * 2. <cmd> start +length - operate on <'start', start + length)
+ * If the second form is used and the end address doesn't fall on the
+ * sector boundary, than it will be adjusted to the next sector boundary.
+ * If it isn't in the flash, the function will fail (return -1).
+ * Input:
+ * arg1, arg2: address specification (i.e. both command arguments)
+ * Output:
+ * addr_first, addr_last: computed address range
+ * Return:
+ * 1: success
+ * -1: failure (bad format, bad address).
+*/
+static int
+addr_spec(char *arg1, char *arg2, ulong *addr_first, ulong *addr_last)
+{
+ char len_used = 0; /* indicates if the "start +length" form used */
+ char *ep;
+
+ *addr_first = simple_strtoul(arg1, &ep, 16);
+ if (ep == arg1 || *ep != '\0')
+ return -1;
+
+ if (arg2 && *arg2 == '+'){
+ len_used = 1;
+ ++arg2;
+ }
+
+ *addr_last = simple_strtoul(arg2, &ep, 16);
+ if (ep == arg2 || *ep != '\0')
+ return -1;
+
+ if (len_used){
+ char found = 0;
+ ulong bank;
+
+ /*
+ * *addr_last has the length, compute correct *addr_last
+ * XXX watch out for the integer overflow! Right now it is
+ * checked for in both the callers.
+ */
+ *addr_last = *addr_first + *addr_last - 1;
+
+ /*
+ * It may happen that *addr_last doesn't fall on the sector
+ * boundary. We want to round such an address to the next
+ * sector boundary, so that the commands don't fail later on.
+ */
+
+ /* find the end addr of the sector where the *addr_last is */
+ for (bank = 0; bank < CFG_MAX_FLASH_BANKS && !found; ++bank){
+ int i;
+ flash_info_t *info = &flash_info[bank];
+ for (i = 0; i < info->sector_count && !found; ++i){
+ /* get the end address of the sector */
+ ulong sector_end_addr;
+ if (i == info->sector_count - 1){
+ sector_end_addr =
+ info->start[0] + info->size - 1;
+ } else {
+ sector_end_addr =
+ info->start[i+1] - 1;
+ }
+ if (*addr_last <= sector_end_addr &&
+ *addr_last >= info->start[i]){
+ /* sector found */
+ found = 1;
+ /* adjust *addr_last if necessary */
+ if (*addr_last < sector_end_addr){
+ *addr_last = sector_end_addr;
+ }
+ }
+ } /* sector */
+ } /* bank */
+ if (!found){
+ /* error, addres not in flash */
+ printf("Error: end address (0x%08lx) not in flash!\n",
+ *addr_last);
+ return -1;
+ }
+ } /* "start +length" from used */
+
+ return 1;
+}
+
static int
flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
int *s_first, int *s_last,
flash_print_info (&flash_info[bank-1]);
return 0;
}
+
int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
flash_info_t *info;
ulong bank, addr_first, addr_last;
int n, sect_first, sect_last;
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 dev_type, dev_num, pnum;
+#endif
int rcode = 0;
if (argc < 2) {
return rcode;
}
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+ /* erase <part-id> - erase partition */
+ if ((argc == 2) && (id_parse(argv[1], NULL, &dev_type, &dev_num) == 0)) {
+ mtdparts_init();
+ if (find_dev_and_part(argv[1], &dev, &pnum, &part) == 0) {
+ if (dev->id->type == MTD_DEV_TYPE_NOR) {
+ bank = dev->id->num;
+ info = &flash_info[bank];
+ addr_first = part->offset + info->start[0];
+ addr_last = addr_first + part->size - 1;
+
+ printf ("Erase Flash Parition %s, "
+ "bank %d, 0x%08lx - 0x%08lx ",
+ argv[1], bank, addr_first,
+ addr_last);
+
+ rcode = flash_sect_erase(addr_first, addr_last);
+ return rcode;
+ }
+
+ printf("cannot erase, not a NOR device\n");
+ return 1;
+ }
+ }
+#endif
+
if (argc != 3) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
return rcode;
}
- addr_first = simple_strtoul(argv[1], NULL, 16);
- addr_last = simple_strtoul(argv[2], NULL, 16);
+ if (addr_spec(argv[1], argv[2], &addr_first, &addr_last) < 0){
+ printf ("Bad address format\n");
+ return 1;
+ }
if (addr_first >= addr_last) {
printf ("Usage:\n%s\n", cmdtp->usage);
flash_info_t *info;
ulong bank, addr_first, addr_last;
int i, p, n, sect_first, sect_last;
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 dev_type, dev_num, pnum;
+#endif
int rcode = 0;
#ifdef CONFIG_HAS_DATAFLASH
int status;
return rcode;
}
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+ /* protect on/off <part-id> */
+ if ((argc == 3) && (id_parse(argv[2], NULL, &dev_type, &dev_num) == 0)) {
+ mtdparts_init();
+ if (find_dev_and_part(argv[2], &dev, &pnum, &part) == 0) {
+ if (dev->id->type == MTD_DEV_TYPE_NOR) {
+ bank = dev->id->num;
+ info = &flash_info[bank];
+ addr_first = part->offset + info->start[0];
+ addr_last = addr_first + part->size - 1;
+
+ printf ("%sProtect Flash Parition %s, "
+ "bank %d, 0x%08lx - 0x%08lx\n",
+ p ? "" : "Un", argv[1],
+ bank, addr_first, addr_last);
+
+ rcode = flash_sect_protect (p, addr_first, addr_last);
+ return rcode;
+ }
+
+ printf("cannot %sprotect, not a NOR device\n",
+ p ? "" : "un");
+ return 1;
+ }
+ }
+#endif
+
if (argc != 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
return rcode;
}
- addr_first = simple_strtoul(argv[2], NULL, 16);
- addr_last = simple_strtoul(argv[3], NULL, 16);
+ if (addr_spec(argv[2], argv[3], &addr_first, &addr_last) < 0){
+ printf("Bad address format\n");
+ return 1;
+ }
if (addr_first >= addr_last) {
printf ("Usage:\n%s\n", cmdtp->usage);
/**************************************************/
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+# define TMP_ERASE "erase <part-id>\n - erase partition\n"
+# define TMP_PROT_ON "protect on <part-id>\n - protect partition\n"
+# define TMP_PROT_OFF "protect off <part-id>\n - make partition writable\n"
+#else
+# define TMP_ERASE /* empty */
+# define TMP_PROT_ON /* empty */
+# define TMP_PROT_OFF /* empty */
+#endif
U_BOOT_CMD(
flinfo, 2, 1, do_flinfo,
"erase - erase FLASH memory\n",
"start end\n"
" - erase FLASH from addr 'start' to addr 'end'\n"
+ "erase start +len\n"
+ " - erase FLASH from addr 'start' to the end of sect "
+ "w/addr 'start'+'len'-1\n"
"erase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n"
"erase bank N\n - erase FLASH bank # N\n"
+ TMP_ERASE
"erase all\n - erase all FLASH banks\n"
);
"protect - enable or disable FLASH write protection\n",
"on start end\n"
" - protect FLASH from addr 'start' to addr 'end'\n"
+ "protect on start +len\n"
+ " - protect FLASH from addr 'start' to end of sect "
+ "w/addr 'start'+'len'-1\n"
"protect on N:SF[-SL]\n"
" - protect sectors SF-SL in FLASH bank # N\n"
"protect on bank N\n - protect FLASH bank # N\n"
+ TMP_PROT_ON
"protect on all\n - protect all FLASH banks\n"
"protect off start end\n"
" - make FLASH from addr 'start' to addr 'end' writable\n"
+ "protect off start +len\n"
+ " - make FLASH from addr 'start' to end of sect "
+ "w/addr 'start'+'len'-1 wrtable\n"
"protect off N:SF[-SL]\n"
" - make sectors SF-SL writable in FLASH bank # N\n"
"protect off bank N\n - make FLASH bank # N writable\n"
+ TMP_PROT_OFF
"protect off all\n - make all FLASH banks writable\n"
);
+#undef TMP_ERASE
+#undef TMP_PROT_ON
+#undef TMP_PROT_OFF
+
#endif /* CFG_CMD_FLASH */
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
- int length;
- char* swapdata;
- int swapsize;
+ unsigned int length;
+ unsigned char* swapdata;
+ unsigned int swapsize;
char buffer[80];
- char *ptr;
- char *dataptr;
- int data;
- int i;
+ unsigned char *ptr;
+ unsigned char *dataptr;
+ unsigned char data;
+ unsigned int i;
int rc;
dataptr = fpgadata;
#if CFG_FPGA_XILINX
- /* skip the first 13 bytes of the bitsteam, their meaning is unknown */
- dataptr+=13;
+ /* skip the first bytes of the bitsteam, their meaning is unknown */
+ length = (*dataptr << 8) + *(dataptr+1);
+ dataptr+=2;
+ dataptr+=length;
/* get design name (identifier, length, string) */
+ length = (*dataptr << 8) + *(dataptr+1);
+ dataptr+=2;
if (*dataptr++ != 0x61) {
- PRINTF("fpga_loadbitstream: Design name identifier not recognized in bitstream.\n");
+ PRINTF ("%s: Design name identifier not recognized in bitstream\n",
+ __FUNCTION__ );
return FPGA_FAIL;
}
for(i=0;i<length;i++)
buffer[i]=*dataptr++;
- buffer[length-5]='\0'; /* remove filename extension */
- PRINTF("fpga_loadbitstream: design name = \"%s\".\n",buffer);
+ printf(" design filename = \"%s\"\n", buffer);
/* get part number (identifier, length, string) */
if (*dataptr++ != 0x62) {
- printf("fpga_loadbitstream: Part number identifier not recognized in bitstream.\n");
+ printf("%s: Part number identifier not recognized in bitstream\n",
+ __FUNCTION__ );
return FPGA_FAIL;
}
- length = (*dataptr << 8) + *(dataptr+1); dataptr+=2;
+ length = (*dataptr << 8) + *(dataptr+1);
+ dataptr+=2;
for(i=0;i<length;i++)
buffer[i]=*dataptr++;
- PRINTF("fpga_loadbitstream: part number = \"%s\".\n",buffer);
+ printf(" part number = \"%s\"\n", buffer);
/* get date (identifier, length, string) */
if (*dataptr++ != 0x63) {
- printf("fpga_loadbitstream: Date identifier not recognized in bitstream.\n");
+ printf("%s: Date identifier not recognized in bitstream\n",
+ __FUNCTION__);
return FPGA_FAIL;
}
- length = (*dataptr << 8) + *(dataptr+1); dataptr+=2;
+ length = (*dataptr << 8) + *(dataptr+1);
+ dataptr+=2;
for(i=0;i<length;i++)
buffer[i]=*dataptr++;
- PRINTF("fpga_loadbitstream: date = \"%s\".\n",buffer);
+ printf(" date = \"%s\"\n", buffer);
/* get time (identifier, length, string) */
if (*dataptr++ != 0x64) {
- printf("fpga_loadbitstream: Time identifier not recognized in bitstream.\n");
+ printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
return FPGA_FAIL;
}
- length = (*dataptr << 8) + *(dataptr+1); dataptr+=2;
+ length = (*dataptr << 8) + *(dataptr+1);
+ dataptr+=2;
for(i=0;i<length;i++)
buffer[i]=*dataptr++;
- PRINTF("fpga_loadbitstream: time = \"%s\".\n",buffer);
+ printf(" time = \"%s\"\n", buffer);
/* get fpga data length (identifier, length) */
if (*dataptr++ != 0x65) {
- printf("fpga_loadbitstream: Data length identifier not recognized in bitstream.\n");
+ printf("%s: Data length identifier not recognized in bitstream\n",
+ __FUNCTION__);
return FPGA_FAIL;
}
- swapsize = ((long)*dataptr<<24) + ((long)*(dataptr+1)<<16) + ((long)*(dataptr+2)<<8) + (long)*(dataptr+3);
+ swapsize = ((unsigned int) *dataptr <<24) +
+ ((unsigned int) *(dataptr+1) <<16) +
+ ((unsigned int) *(dataptr+2) <<8 ) +
+ ((unsigned int) *(dataptr+3) ) ;
dataptr+=4;
- PRINTF("fpga_loadbitstream: bytes in bitstream = %d.\n",swapsize);
+ printf(" bytes in bitstream = %d\n", swapsize);
/* check consistency of length obtained */
if (swapsize >= size) {
- printf("fpga_loadbitstream: Could not find right length of data in bitstream.\n");
+ printf("%s: Could not find right length of data in bitstream\n",
+ __FUNCTION__);
return FPGA_FAIL;
}
/* allocate memory */
- swapdata = (char *)malloc(swapsize);
+ swapdata = (unsigned char *)malloc(swapsize);
if (swapdata == NULL) {
- printf("fpga_loadbitstream: Could not allocate %d bytes memory !\n",swapsize);
+ printf("%s: Could not allocate %d bytes memory !\n",
+ __FUNCTION__, swapsize);
return FPGA_FAIL;
}
free(swapdata);
return rc;
#else
- printf("Bitstream support only for Xilinx devices.\n");
+ printf("Bitstream support only for Xilinx devices\n");
return FPGA_FAIL;
#endif
}
data_size = simple_strtoul (argv[4], NULL, 16);
case 4: /* fpga <op> <dev> <data> */
fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
- PRINTF ("do_fpga: fpga_data = 0x%x\n",
- (uint) fpga_data);
+ PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
case 3: /* fpga <op> <dev | data addr> */
dev = (int) simple_strtoul (argv[2], NULL, 16);
- PRINTF ("do_fpga: device = %d\n", dev);
+ PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
/* FIXME - this is a really weak test */
if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
- PRINTF ("do_fpga: Assuming buffer pointer in arg 3\n");
+ PRINTF ("%s: Assuming buffer pointer in arg 3\n",
+ __FUNCTION__);
fpga_data = (void *) dev;
- PRINTF ("do_fpga: fpga_data = 0x%x\n",
- (uint) fpga_data);
+ PRINTF ("%s: fpga_data = 0x%x\n",
+ __FUNCTION__, (uint) fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}
case 2: /* fpga <op> */
op = (int) fpga_get_op (argv[1]);
break;
default:
- PRINTF ("do_fpga: Too many or too few args (%d)\n",
- argc);
+ PRINTF ("%s: Too many or too few args (%d)\n",
+ __FUNCTION__, argc);
op = FPGA_NONE; /* force usage display */
break;
}
break;
default:
- printf ("Unknown operation.\n");
+ printf ("Unknown operation\n");
fpga_usage (cmdtp);
break;
}
"fpga - loadable FPGA image support\n",
"fpga [operation type] [device number] [image address] [image size]\n"
"fpga operations:\n"
- "\tinfo\tlist known device information.\n"
- "\tload\tLoad device from memory buffer.\n"
- "\tloadb\tLoad device from bitstream buffer (Xilinx devices only).\n"
- "\tdump\tLoad device to memory buffer.\n");
+ "\tinfo\tlist known device information\n"
+ "\tload\tLoad device from memory buffer\n"
+ "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
+ "\tdump\tLoad device to memory buffer\n");
#endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
* (C) Copyright 2002
* Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
* (C) Copyright 2003
* Kai-Uwe Bloem, Auerswald GmbH & Co KG, <linux-development@auerswald.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Added support for reading flash partition table from environment.
+ * Parsing routines are based on driver/mtd/cmdline.c from the linux 2.4
+ * kernel tree.
+ *
+ * $Id: cmdlinepart.c,v 1.17 2004/11/26 11:18:47 lavinen Exp $
+ * Copyright 2002 SYSGO Real-Time Solutions GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Three environment variables are used by the parsing routines:
+ *
+ * 'partition' - keeps current partition identifier
+ *
+ * partition := <part-id>
+ * <part-id> := <dev-id>,part_num
+ *
+ *
+ * 'mtdids' - linux kernel mtd device id <-> u-boot device id mapping
+ *
+ * mtdids=<idmap>[,<idmap>,...]
+ *
+ * <idmap> := <dev-id>=<mtd-id>
+ * <dev-id> := 'nand'|'nor'<dev-num>
+ * <dev-num> := mtd device number, 0...
+ * <mtd-id> := unique device tag used by linux kernel to find mtd device (mtd->name)
+ *
+ *
+ * 'mtdparts' - partition list
+ *
+ * mtdparts=mtdparts=<mtd-def>[;<mtd-def>...]
+ *
+ * <mtd-def> := <mtd-id>:<part-def>[,<part-def>...]
+ * <mtd-id> := unique device tag used by linux kernel to find mtd device (mtd->name)
+ * <part-def> := <size>[@<offset>][<name>][<ro-flag>]
+ * <size> := standard linux memsize OR '-' to denote all remaining space
+ * <offset> := partition start offset within the device
+ * <name> := '(' NAME ')'
+ * <ro-flag> := when set to 'ro' makes partition read-only (not used, passed to kernel)
+ *
+ * Notes:
+ * - each <mtd-id> used in mtdparts must albo exist in 'mtddis' mapping
+ * - if the above variables are not set defaults for a given target are used
+ *
+ * Examples:
+ *
+ * 1 NOR Flash, with 1 single writable partition:
+ * mtdids=nor0=edb7312-nor
+ * mtdparts=mtdparts=edb7312-nor:-
+ *
+ * 1 NOR Flash with 2 partitions, 1 NAND with one
+ * mtdids=nor0=edb7312-nor,nand0=edb7312-nand
+ * mtdparts=mtdparts=edb7312-nor:256k(ARMboot)ro,-(root);edb7312-nand:-(home)
+ *
+ */
+
+/*
+ * JFFS2/CRAMFS support
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <jffs2/jffs2.h>
+#include <linux/mtd/nand.h>
+#include <linux/list.h>
+#include <linux/ctype.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+
+#include <cramfs/cramfs_fs.h>
+
+/* enable/disable debugging messages */
+#define DEBUG
+#undef DEBUG
+
+#ifdef DEBUG
+# define DEBUGF(fmt, args...) printf(fmt ,##args)
+#else
+# define DEBUGF(fmt, args...)
+#endif
+
+/* special size referring to all the remaining space in a partition */
+#define SIZE_REMAINING 0xFFFFFFFF
+
+/* special offset value, it is used when not provided by user
+ *
+ * this value is used temporarily during parsing, later such offests
+ * are recalculated */
+#define OFFSET_NOT_SPECIFIED 0xFFFFFFFF
+
+/* minimum partition size */
+#define MIN_PART_SIZE 4096
+
+/* this flag needs to be set in part_info struct mask_flags
+ * field for read-only partitions */
+#define MTD_WRITEABLE 1
+
+#ifdef CONFIG_JFFS2_CMDLINE
+/* default values for mtdids and mtdparts variables */
+#if defined(MTDIDS_DEFAULT)
+static const char *const mtdids_default = MTDIDS_DEFAULT;
+#else
+#warning "MTDIDS_DEFAULT not defined!"
+static const char *const mtdids_default = NULL;
+#endif
+
+#if defined(MTDPARTS_DEFAULT)
+static const char *const mtdparts_default = MTDPARTS_DEFAULT;
+#else
+#warning "MTDPARTS_DEFAULT not defined!"
+static const char *const mtdparts_default = NULL;
+#endif
+
+/* copies of last seen 'mtdids', 'mtdparts' and 'partition' env variables */
+#define MTDIDS_MAXLEN 128
+#define MTDPARTS_MAXLEN 512
+#define PARTITION_MAXLEN 16
+static char last_ids[MTDIDS_MAXLEN];
+static char last_parts[MTDPARTS_MAXLEN];
+static char last_partition[PARTITION_MAXLEN];
+
+/* low level jffs2 cache cleaning routine */
+extern void jffs2_free_cache(struct part_info *part);
+
+/* mtdids mapping list, filled by parse_ids() */
+struct list_head mtdids;
+
+/* device/partition list, parse_cmdline() parses into here */
+struct list_head devices;
+#endif /* #ifdef CONFIG_JFFS2_CMDLINE */
+
+/* current active device and partition number */
+static struct mtd_device *current_dev = NULL;
+static u8 current_partnum = 0;
+
+extern int cramfs_check (struct part_info *info);
+extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename);
+extern int cramfs_ls (struct part_info *info, char *filename);
+extern int cramfs_info (struct part_info *info);
+
+static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num);
+
+/* command line only routines */
+#ifdef CONFIG_JFFS2_CMDLINE
+
+static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len);
+static int device_del(struct mtd_device *dev);
+
+/**
+ * Parses a string into a number. The number stored at ptr is
+ * potentially suffixed with K (for kilobytes, or 1024 bytes),
+ * M (for megabytes, or 1048576 bytes), or G (for gigabytes, or
+ * 1073741824). If the number is suffixed with K, M, or G, then
+ * the return value is the number multiplied by one kilobyte, one
+ * megabyte, or one gigabyte, respectively.
+ *
+ * @param ptr where parse begins
+ * @param retptr output pointer to next char after parse completes (output)
+ * @return resulting unsigned int
+ */
+static unsigned long memsize_parse (const char *const ptr, const char **retptr)
+{
+ unsigned long ret = simple_strtoul(ptr, (char **)retptr, 0);
+
+ switch (**retptr) {
+ case 'G':
+ case 'g':
+ ret <<= 10;
+ case 'M':
+ case 'm':
+ ret <<= 10;
+ case 'K':
+ case 'k':
+ ret <<= 10;
+ (*retptr)++;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * Format string describing supplied size. This routine does the opposite job
+ * to memsize_parse(). Size in bytes is converted to string and if possible
+ * shortened by using k (kilobytes), m (megabytes) or g (gigabytes) suffix.
+ *
+ * Note, that this routine does not check for buffer overflow, it's the caller
+ * who must assure enough space.
+ *
+ * @param buf output buffer
+ * @param size size to be converted to string
+ */
+static void memsize_format(char *buf, u32 size)
+{
+#define SIZE_GB ((u32)1024*1024*1024)
+#define SIZE_MB ((u32)1024*1024)
+#define SIZE_KB ((u32)1024)
+
+ if ((size % SIZE_GB) == 0)
+ sprintf(buf, "%lug", size/SIZE_GB);
+ else if ((size % SIZE_MB) == 0)
+ sprintf(buf, "%lum", size/SIZE_MB);
+ else if (size % SIZE_KB == 0)
+ sprintf(buf, "%luk", size/SIZE_KB);
+ else
+ sprintf(buf, "%lu", size);
+}
+
+/**
+ * Save current device and partition in environment variable 'partition'.
+ */
+static void current_save(void)
+{
+ char buf[16];
+
+ DEBUGF("--- current_save ---\n");
+
+ if (current_dev) {
+ sprintf(buf, "%s%d,%d", MTD_DEV_TYPE(current_dev->id->type),
+ current_dev->id->num, current_partnum);
+
+ setenv("partition", buf);
+ strncpy(last_partition, buf, 16);
+
+ DEBUGF("=> partition %s\n", buf);
+ } else {
+ setenv("partition", NULL);
+ last_partition[0] = '\0';
+
+ DEBUGF("=> partition NULL\n");
+ }
+}
+
+/**
+ * Performs sanity check for supplied NOR flash partition. Table of existing
+ * NOR flash devices is searched and partition device is located. Alignment
+ * with the granularity of NOR flash sectors is verified.
+ *
+ * @param id of the parent device
+ * @param part partition to validate
+ * @return 0 if partition is valid, 1 otherwise
+ */
+static int part_validate_nor(struct mtdids *id, struct part_info *part)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+ /* info for FLASH chips */
+ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ flash_info_t *flash;
+ int offset_aligned;
+ u32 end_offset;
+ int i;
+
+ flash = &flash_info[id->num];
+
+ offset_aligned = 0;
+ for (i = 0; i < flash->sector_count; i++) {
+ if ((flash->start[i] - flash->start[0]) == part->offset) {
+ offset_aligned = 1;
+ break;
+ }
+ }
+ if (offset_aligned == 0) {
+ printf("%s%d: partition (%s) start offset alignment incorrect\n",
+ MTD_DEV_TYPE(id->type), id->num, part->name);
+ return 1;
+ }
+
+ end_offset = part->offset + part->size;
+ for (i = 0; i < flash->sector_count; i++) {
+ if ((flash->start[i] - flash->start[0]) == end_offset)
+ return 0;
+ }
+
+ if (flash->size == end_offset)
+ return 0;
+
+ printf("%s%d: partition (%s) size alignment incorrect\n",
+ MTD_DEV_TYPE(id->type), id->num, part->name);
+#endif
+ return 1;
+}
+
+/**
+ * Performs sanity check for supplied NAND flash partition. Table of existing
+ * NAND flash devices is searched and partition device is located. Alignment
+ * with the granularity of nand erasesize is verified.
+ *
+ * @param id of the parent device
+ * @param part partition to validate
+ * @return 0 if partition is valid, 1 otherwise
+ */
+static int part_validate_nand(struct mtdids *id, struct part_info *part)
+{
+#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
+ /* info for NAND chips */
+ extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+ struct nand_chip *nand;
+
+ nand = &nand_dev_desc[id->num];
+
+ if ((unsigned long)(part->offset) % nand->erasesize) {
+ printf("%s%d: partition (%s) start offset alignment incorrect\n",
+ MTD_DEV_TYPE(id->type), id->num, part->name);
+ return 1;
+ }
+
+ if (part->size % nand->erasesize) {
+ printf("%s%d: partition (%s) size alignment incorrect\n",
+ MTD_DEV_TYPE(id->type), id->num, part->name);
+ return 1;
+ }
+
+ return 0;
+#else
+ return 1;
+#endif
+}
+
+/**
+ * Performs sanity check for supplied partition. Offset and size are verified
+ * to be within valid range. Partition type is checked and either
+ * parts_validate_nor() or parts_validate_nand() is called with the argument
+ * of part.
+ *
+ * @param id of the parent device
+ * @param part partition to validate
+ * @return 0 if partition is valid, 1 otherwise
+ */
+static int part_validate(struct mtdids *id, struct part_info *part)
+{
+ if (part->size == SIZE_REMAINING)
+ part->size = id->size - part->offset;
+
+ if (part->offset > id->size) {
+ printf("%s: offset %08lx beyond flash size %08lx\n",
+ id->mtd_id, part->offset, id->size);
+ return 1;
+ }
+
+ if ((part->offset + part->size) <= part->offset) {
+ printf("%s%d: partition (%s) size too big\n",
+ MTD_DEV_TYPE(id->type), id->num, part->name);
+ return 1;
+ }
+
+ if (part->offset + part->size > id->size) {
+ printf("%s: partitioning exceeds flash size\n", id->mtd_id);
+ return 1;
+ }
+
+ if (id->type == MTD_DEV_TYPE_NAND)
+ return part_validate_nand(id, part);
+ else if (id->type == MTD_DEV_TYPE_NOR)
+ return part_validate_nor(id, part);
+ else
+ DEBUGF("part_validate: invalid dev type\n");
+
+ return 1;
+}
+
+/**
+ * Delete selected partition from the partion list of the specified device.
+ *
+ * @param dev device to delete partition from
+ * @param part partition to delete
+ * @return 0 on success, 1 otherwise
+ */
+static int part_del(struct mtd_device *dev, struct part_info *part)
+{
+ /* if there is only one partition, remove whole device */
+ if (dev->num_parts == 1)
+ return device_del(dev);
+
+ /* otherwise just delete this partition */
+
+ if (dev == current_dev) {
+ /* we are modyfing partitions for the current device,
+ * update current */
+ struct part_info *curr_pi;
+ curr_pi = jffs2_part_info(current_dev, current_partnum);
+
+ if (curr_pi) {
+ if (curr_pi == part) {
+ printf("current partition deleted, resetting current to 0\n");
+ current_partnum = 0;
+ current_save();
+ } else if (part->offset <= curr_pi->offset) {
+ current_partnum--;
+ current_save();
+ }
+ }
+ }
+
+
+ jffs2_free_cache(part);
+ list_del(&part->link);
+ free(part);
+ dev->num_parts--;
+
+ return 0;
+}
+
+/**
+ * Delete all partitions from parts head list, free memory.
+ *
+ * @param head list of partitions to delete
+ */
+static void part_delall(struct list_head *head)
+{
+ struct list_head *entry, *n;
+ struct part_info *part_tmp;
+
+ /* clean tmp_list and free allocated memory */
+ list_for_each_safe(entry, n, head) {
+ part_tmp = list_entry(entry, struct part_info, link);
+
+ jffs2_free_cache(part_tmp);
+ list_del(entry);
+ free(part_tmp);
+ }
+}
+
+/**
+ * Add new partition to the supplied partition list. Make sure partitions are
+ * sorted by offset in ascending order.
+ *
+ * @param head list this partition is to be added to
+ * @param new partition to be added
+ */
+static int part_sort_add(struct mtd_device *dev, struct part_info *part)
+{
+ struct list_head *entry;
+ struct part_info *new_pi, *curr_pi;
+
+ /* link partition to parrent dev */
+ part->dev = dev;
+
+ if (list_empty(&dev->parts)) {
+ DEBUGF("part_sort_add: list empty\n");
+ list_add(&part->link, &dev->parts);
+ return 0;
+ }
+
+ new_pi = list_entry(&part->link, struct part_info, link);
+
+ /* get current partition info if we are updating current device */
+ curr_pi = NULL;
+ if (dev == current_dev)
+ curr_pi = jffs2_part_info(current_dev, current_partnum);
+
+ list_for_each(entry, &dev->parts) {
+ struct part_info *pi;
+
+ pi = list_entry(entry, struct part_info, link);
+
+ /* be compliant with kernel cmdline, allow only one partition at offset zero */
+ if ((new_pi->offset == pi->offset) && (pi->offset == 0)) {
+ printf("cannot add second partition at offset 0\n");
+ return 1;
+ }
+
+ if (new_pi->offset <= pi->offset) {
+ list_add_tail(&part->link, entry);
+
+ if (curr_pi && (pi->offset <= curr_pi->offset)) {
+ /* we are modyfing partitions for the current
+ * device, update current */
+ current_partnum++;
+ current_save();
+ }
+
+ return 0;
+ }
+ }
+ list_add_tail(&part->link, &dev->parts);
+ return 0;
+}
+
+/**
+ * Add provided partition to the partition list of a given device.
+ *
+ * @param dev device to which partition is added
+ * @param part partition to be added
+ * @return 0 on success, 1 otherwise
+ */
+static int part_add(struct mtd_device *dev, struct part_info *part)
+{
+ /* verify alignment and size */
+ if (part_validate(dev->id, part) != 0)
+ return 1;
+
+ /* partition is ok, add it to the list */
+ if (part_sort_add(dev, part) != 0)
+ return 1;
+
+ dev->num_parts++;
+ return 0;
+}
+
+/**
+ * Parse one partition definition, allocate memory and return pointer to this
+ * location in retpart.
+ *
+ * @param partdef pointer to the partition definition string i.e. <part-def>
+ * @param ret output pointer to next char after parse completes (output)
+ * @param retpart pointer to the allocated partition (output)
+ * @return 0 on success, 1 otherwise
+ */
+static int part_parse(const char *const partdef, const char **ret, struct part_info **retpart)
+{
+ struct part_info *part;
+ unsigned long size;
+ unsigned long offset;
+ const char *name;
+ int name_len;
+ unsigned int mask_flags;
+ const char *p;
+
+ p = partdef;
+ *retpart = NULL;
+ *ret = NULL;
+
+ /* fetch the partition size */
+ if (*p == '-') {
+ /* assign all remaining space to this partition */
+ DEBUGF("'-': remaining size assigned\n");
+ size = SIZE_REMAINING;
+ p++;
+ } else {
+ size = memsize_parse(p, &p);
+ if (size < MIN_PART_SIZE) {
+ printf("partition size too small (%lx)\n", size);
+ return 1;
+ }
+ }
+
+ /* check for offset */
+ offset = OFFSET_NOT_SPECIFIED;
+ if (*p == '@') {
+ p++;
+ offset = memsize_parse(p, &p);
+ }
+
+ /* now look for the name */
+ if (*p == '(') {
+ name = ++p;
+ if ((p = strchr(name, ')')) == NULL) {
+ printf("no closing ) found in partition name\n");
+ return 1;
+ }
+ name_len = p - name + 1;
+ if ((name_len - 1) == 0) {
+ printf("empty partition name\n");
+ return 1;
+ }
+ p++;
+ } else {
+ /* 0x00000000@0x00000000 */
+ name_len = 22;
+ name = NULL;
+ }
+
+ /* test for options */
+ mask_flags = 0;
+ if (strncmp(p, "ro", 2) == 0) {
+ mask_flags |= MTD_WRITEABLE;
+ p += 2;
+ }
+
+ /* check for next partition definition */
+ if (*p == ',') {
+ if (size == SIZE_REMAINING) {
+ *ret = NULL;
+ printf("no partitions allowed after a fill-up partition\n");
+ return 1;
+ }
+ *ret = ++p;
+ } else if ((*p == ';') || (*p == '\0')) {
+ *ret = p;
+ } else {
+ printf("unexpected character '%c' at the end of partition\n", *p);
+ *ret = NULL;
+ return 1;
+ }
+
+ /* allocate memory */
+ part = (struct part_info *)malloc(sizeof(struct part_info) + name_len);
+ if (!part) {
+ printf("out of memory\n");
+ return 1;
+ }
+ memset(part, 0, sizeof(struct part_info) + name_len);
+ part->size = size;
+ part->offset = offset;
+ part->mask_flags = mask_flags;
+ part->name = (char *)(part + 1);
+
+ if (name) {
+ /* copy user provided name */
+ strncpy(part->name, name, name_len - 1);
+ part->auto_name = 0;
+ } else {
+ /* auto generated name in form of size@offset */
+ sprintf(part->name, "0x%08lx@0x%08lx", size, offset);
+ part->auto_name = 1;
+ }
+
+ part->name[name_len - 1] = '\0';
+ INIT_LIST_HEAD(&part->link);
+
+ DEBUGF("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n",
+ part->name, part->size,
+ part->offset, part->mask_flags);
+
+ *retpart = part;
+ return 0;
+}
+#endif/* #ifdef CONFIG_JFFS2_CMDLINE */
+
+/**
+ * Check device number to be within valid range for given device type.
+ *
+ * @param dev device to validate
+ * @return 0 if device is valid, 1 otherwise
+ */
+static int device_validate(u8 type, u8 num, u32 *size)
+{
+ if (type == MTD_DEV_TYPE_NOR) {
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+ if (num < CFG_MAX_FLASH_BANKS) {
+ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ *size = flash_info[num].size;
+ return 0;
+ }
+
+ printf("no such FLASH device: %s%d (valid range 0 ... %d\n",
+ MTD_DEV_TYPE(type), num, CFG_MAX_FLASH_BANKS - 1);
+#else
+ printf("support for FLASH devices not present\n");
+#endif
+ } else if (type == MTD_DEV_TYPE_NAND) {
+#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
+ if (num < CFG_MAX_NAND_DEVICE) {
+ extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+ *size = nand_dev_desc[num].totlen;
+ return 0;
+ }
+
+ printf("no such NAND device: %s%d (valid range 0 ... %d)\n",
+ MTD_DEV_TYPE(type), num, CFG_MAX_NAND_DEVICE - 1);
+#else
+ printf("support for NAND devices not present\n");
+#endif
+ }
+
+ return 1;
+}
+
+#ifdef CONFIG_JFFS2_CMDLINE
+/**
+ * Delete all mtd devices from a supplied devices list, free memory allocated for
+ * each device and delete all device partitions.
+ *
+ * @return 0 on success, 1 otherwise
+ */
+static int device_delall(struct list_head *head)
+{
+ struct list_head *entry, *n;
+ struct mtd_device *dev_tmp;
+
+ /* clean devices list */
+ list_for_each_safe(entry, n, head) {
+ dev_tmp = list_entry(entry, struct mtd_device, link);
+ list_del(entry);
+ part_delall(&dev_tmp->parts);
+ free(dev_tmp);
+ }
+ INIT_LIST_HEAD(&devices);
+
+ return 0;
+}
+
+/**
+ * If provided device exists it's partitions are deleted, device is removed
+ * from device list and device memory is freed.
+ *
+ * @param dev device to be deleted
+ * @return 0 on success, 1 otherwise
+ */
+static int device_del(struct mtd_device *dev)
+{
+ part_delall(&dev->parts);
+ list_del(&dev->link);
+ free(dev);
+
+ if (dev == current_dev) {
+ /* we just deleted current device */
+ if (list_empty(&devices)) {
+ current_dev = NULL;
+ } else {
+ /* reset first partition from first dev from the
+ * devices list as current */
+ current_dev = list_entry(devices.next, struct mtd_device, link);
+ current_partnum = 0;
+ }
+ current_save();
+ }
+
+
+ return 0;
+}
+
+/**
+ * Search global device list and return pointer to the device of type and num
+ * specified.
+ *
+ * @param type device type
+ * @param num device number
+ * @return NULL if requested device does not exist
+ */
+static struct mtd_device* device_find(u8 type, u8 num)
+{
+ struct list_head *entry;
+ struct mtd_device *dev_tmp;
+
+ list_for_each(entry, &devices) {
+ dev_tmp = list_entry(entry, struct mtd_device, link);
+
+ if ((dev_tmp->id->type == type) && (dev_tmp->id->num == num))
+ return dev_tmp;
+ }
+
+ return NULL;
+}
+
+/**
+ * Add specified device to the global device list.
+ *
+ * @param dev device to be added
+ */
+static void device_add(struct mtd_device *dev)
+{
+ if (list_empty(&devices)) {
+ current_dev = dev;
+ current_partnum = 0;
+ current_save();
+ }
+
+ list_add_tail(&dev->link, &devices);
+}
+
+/**
+ * Parse device type, name and mtd-id. If syntax is ok allocate memory and
+ * return pointer to the device structure.
+ *
+ * @param mtd_dev pointer to the device definition string i.e. <mtd-dev>
+ * @param ret output pointer to next char after parse completes (output)
+ * @param retdev pointer to the allocated device (output)
+ * @return 0 on success, 1 otherwise
+ */
+static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_device **retdev)
+{
+ struct mtd_device *dev;
+ struct part_info *part;
+ struct mtdids *id;
+ const char *mtd_id;
+ unsigned int mtd_id_len;
+ const char *p, *pend;
+ LIST_HEAD(tmp_list);
+ struct list_head *entry, *n;
+ u16 num_parts;
+ u32 offset;
+ int err = 1;
+
+ p = mtd_dev;
+ *retdev = NULL;
+ *ret = NULL;
+
+ DEBUGF("===device_parse===\n");
+
+ /* fetch <mtd-id> */
+ mtd_id = p;
+ if (!(p = strchr(mtd_id, ':'))) {
+ printf("no <mtd-id> identifier\n");
+ return 1;
+ }
+ mtd_id_len = p - mtd_id + 1;
+ p++;
+
+ /* verify if we have a valid device specified */
+ if ((id = id_find_by_mtd_id(mtd_id, mtd_id_len - 1)) == NULL) {
+ printf("invalid mtd device '%.*s'\n", mtd_id_len - 1, mtd_id);
+ return 1;
+ }
+
+ DEBUGF("dev type = %d (%s), dev num = %d, mtd-id = %s\n",
+ id->type, MTD_DEV_TYPE(id->type),
+ id->num, id->mtd_id);
+ pend = strchr(p, ';');
+ DEBUGF("parsing partitions %.*s\n", (pend ? pend - p : strlen(p)), p);
+
+
+ /* parse partitions */
+ num_parts = 0;
+
+ offset = 0;
+ if ((dev = device_find(id->type, id->num)) != NULL) {
+ /* if device already exists start at the end of the last partition */
+ part = list_entry(dev->parts.prev, struct part_info, link);
+ offset = part->offset + part->size;
+ }
+
+ while (p && (*p != '\0') && (*p != ';')) {
+ err = 1;
+ if ((part_parse(p, &p, &part) != 0) || (!part))
+ break;
+
+ /* calculate offset when not specified */
+ if (part->offset == OFFSET_NOT_SPECIFIED)
+ part->offset = offset;
+ else
+ offset = part->offset;
+
+ /* verify alignment and size */
+ if (part_validate(id, part) != 0)
+ break;
+
+ offset += part->size;
+
+ /* partition is ok, add it to the list */
+ list_add_tail(&part->link, &tmp_list);
+ num_parts++;
+ err = 0;
+ }
+ if (err == 1) {
+ part_delall(&tmp_list);
+ return 1;
+ }
+
+ if (num_parts == 0) {
+ printf("no partitions for device %s%d (%s)\n",
+ MTD_DEV_TYPE(id->type), id->num, id->mtd_id);
+ return 1;
+ }
+
+ DEBUGF("\ntotal partitions: %d\n", num_parts);
+
+ /* check for next device presence */
+ if (p) {
+ if (*p == ';') {
+ *ret = ++p;
+ } else if (*p == '\0') {
+ *ret = p;
+ } else {
+ printf("unexpected character '%c' at the end of device\n", *p);
+ *ret = NULL;
+ return 1;
+ }
+ }
+
+ /* allocate memory for mtd_device structure */
+ if ((dev = (struct mtd_device *)malloc(sizeof(struct mtd_device))) == NULL) {
+ printf("out of memory\n");
+ return 1;
+ }
+ memset(dev, 0, sizeof(struct mtd_device));
+ dev->id = id;
+ dev->num_parts = num_parts;
+ INIT_LIST_HEAD(&dev->parts);
+ INIT_LIST_HEAD(&dev->link);
+
+ /* move partitions from tmp_list to dev->parts */
+ list_for_each_safe(entry, n, &tmp_list) {
+ part = list_entry(entry, struct part_info, link);
+ list_del(entry);
+ if (part_sort_add(dev, part) != 0) {
+ device_del(dev);
+ return 1;
+ }
+ }
+
+ *retdev = dev;
+
+ DEBUGF("===\n\n");
+ return 0;
+}
+
+/**
+ * Initialize global device list.
+ *
+ * @return 0 on success, 1 otherwise
+ */
+static int devices_init(void)
+{
+ last_parts[0] = '\0';
+ current_dev = NULL;
+ current_save();
+
+ return device_delall(&devices);
+}
+
+/*
+ * Search global mtdids list and find id of requested type and number.
+ *
+ * @return pointer to the id if it exists, NULL otherwise
+ */
+static struct mtdids* id_find(u8 type, u8 num)
+{
+ struct list_head *entry;
+ struct mtdids *id;
+
+ list_for_each(entry, &mtdids) {
+ id = list_entry(entry, struct mtdids, link);
+
+ if ((id->type == type) && (id->num == num))
+ return id;
+ }
+
+ return NULL;
+}
+
+/**
+ * Search global mtdids list and find id of a requested mtd_id.
+ *
+ * Note: first argument is not null terminated.
+ *
+ * @param mtd_id string containing requested mtd_id
+ * @param mtd_id_len length of supplied mtd_id
+ * @return pointer to the id if it exists, NULL otherwise
+ */
+static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len)
+{
+ struct list_head *entry;
+ struct mtdids *id;
+
+ DEBUGF("--- id_find_by_mtd_id: '%.*s' (len = %d)\n",
+ mtd_id_len, mtd_id, mtd_id_len);
+
+ list_for_each(entry, &mtdids) {
+ id = list_entry(entry, struct mtdids, link);
+
+ DEBUGF("entry: '%s' (len = %d)\n",
+ id->mtd_id, strlen(id->mtd_id));
+
+ if (mtd_id_len != strlen(id->mtd_id))
+ continue;
+ if (strncmp(id->mtd_id, mtd_id, mtd_id_len) == 0)
+ return id;
+ }
+
+ return NULL;
+}
+#endif /* #ifdef CONFIG_JFFS2_CMDLINE */
+
+/**
+ * Parse device id string <dev-id> := 'nand'|'nor'<dev-num>, return device
+ * type and number.
+ *
+ * @param id string describing device id
+ * @param ret_id output pointer to next char after parse completes (output)
+ * @param dev_type parsed device type (output)
+ * @param dev_num parsed device number (output)
+ * @return 0 on success, 1 otherwise
+ */
+int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num)
+{
+ const char *p = id;
+
+ *dev_type = 0;
+ if (strncmp(p, "nand", 4) == 0) {
+ *dev_type = MTD_DEV_TYPE_NAND;
+ p += 4;
+ } else if (strncmp(p, "nor", 3) == 0) {
+ *dev_type = MTD_DEV_TYPE_NOR;
+ p += 3;
+ } else {
+ printf("incorrect device type in %s\n", id);
+ return 1;
+ }
+
+ if (!isdigit(*p)) {
+ printf("incorrect device number in %s\n", id);
+ return 1;
+ }
+
+ *dev_num = simple_strtoul(p, (char **)&p, 0);
+ if (ret_id)
+ *ret_id = p;
+ return 0;
+}
+
+#ifdef CONFIG_JFFS2_CMDLINE
+/**
+ * Process all devices and generate corresponding mtdparts string describing
+ * all partitions on all devices.
+ *
+ * @param buf output buffer holding generated mtdparts string (output)
+ * @param buflen buffer size
+ * @return 0 on success, 1 otherwise
+ */
+static int generate_mtdparts(char *buf, u32 buflen)
+{
+ struct list_head *pentry, *dentry;
+ struct mtd_device *dev;
+ struct part_info *part, *prev_part;
+ char *p = buf;
+ char tmpbuf[32];
+ u32 size, offset, len, part_cnt;
+ u32 maxlen = buflen - 1;
+
+ DEBUGF("--- generate_mtdparts ---\n");
+
+ if (list_empty(&devices)) {
+ buf[0] = '\0';
+ return 0;
+ }
+
+ sprintf(p, "mtdparts=");
+ p += 9;
+
+ list_for_each(dentry, &devices) {
+ dev = list_entry(dentry, struct mtd_device, link);
+
+ /* copy mtd_id */
+ len = strlen(dev->id->mtd_id) + 1;
+ if (len > maxlen)
+ goto cleanup;
+ memcpy(p, dev->id->mtd_id, len - 1);
+ p += len - 1;
+ *(p++) = ':';
+ maxlen -= len;
+
+ /* format partitions */
+ prev_part = NULL;
+ part_cnt = 0;
+ list_for_each(pentry, &dev->parts) {
+ part = list_entry(pentry, struct part_info, link);
+ size = part->size;
+ offset = part->offset;
+ part_cnt++;
+
+ /* partition size */
+ memsize_format(tmpbuf, size);
+ len = strlen(tmpbuf);
+ if (len > maxlen)
+ goto cleanup;
+ memcpy(p, tmpbuf, len);
+ p += len;
+ maxlen -= len;
+
+
+ /* add offset only when there is a gap between
+ * partitions */
+ if ((!prev_part && (offset != 0)) ||
+ (prev_part && ((prev_part->offset + prev_part->size) != part->offset))) {
+
+ memsize_format(tmpbuf, offset);
+ len = strlen(tmpbuf) + 1;
+ if (len > maxlen)
+ goto cleanup;
+ *(p++) = '@';
+ memcpy(p, tmpbuf, len - 1);
+ p += len - 1;
+ maxlen -= len;
+ }
+
+ /* copy name only if user supplied */
+ if(!part->auto_name) {
+ len = strlen(part->name) + 2;
+ if (len > maxlen)
+ goto cleanup;
+
+ *(p++) = '(';
+ memcpy(p, part->name, len - 2);
+ p += len - 2;
+ *(p++) = ')';
+ maxlen -= len;
+ }
+
+ /* ro mask flag */
+ if (part->mask_flags && MTD_WRITEABLE) {
+ len = 2;
+ if (len > maxlen)
+ goto cleanup;
+ *(p++) = 'r';
+ *(p++) = 'o';
+ maxlen -= 2;
+ }
+
+ /* print ',' separator if there are other partitions
+ * following */
+ if (dev->num_parts > part_cnt) {
+ if (1 > maxlen)
+ goto cleanup;
+ *(p++) = ',';
+ maxlen--;
+ }
+ prev_part = part;
+ }
+ /* print ';' separator if there are other devices following */
+ if (dentry->next != &devices) {
+ if (1 > maxlen)
+ goto cleanup;
+ *(p++) = ';';
+ maxlen--;
+ }
+ }
+
+ /* we still have at least one char left, as we decremented maxlen at
+ * the begining */
+ *p = '\0';
+
+ return 0;
+
+cleanup:
+ last_parts[0] = '\0';
+ return 1;
+}
+
+/**
+ * Call generate_mtdparts to process all devices and generate corresponding
+ * mtdparts string, save it in mtdparts environment variable.
+ *
+ * @param buf output buffer holding generated mtdparts string (output)
+ * @param buflen buffer size
+ * @return 0 on success, 1 otherwise
+ */
+static int generate_mtdparts_save(char *buf, u32 buflen)
+{
+ int ret;
+
+ ret = generate_mtdparts(buf, buflen);
+
+ if ((buf[0] != '\0') && (ret == 0))
+ setenv("mtdparts", buf);
+ else
+ setenv("mtdparts", NULL);
+
+ return ret;
+}
+
+/**
+ * Format and print out a partition list for each device from global device
+ * list.
+ */
+static void list_partitions(void)
+{
+ struct list_head *dentry, *pentry;
+ struct part_info *part;
+ struct mtd_device *dev;
+ int part_num;
+
+ DEBUGF("\n---list_partitions---\n");
+ list_for_each(dentry, &devices) {
+ dev = list_entry(dentry, struct mtd_device, link);
+ printf("\ndevice %s%d <%s>, # parts = %d\n",
+ MTD_DEV_TYPE(dev->id->type), dev->id->num,
+ dev->id->mtd_id, dev->num_parts);
+ printf(" #: name\t\t\tsize\t\toffset\t\tmask_flags\n");
+
+ /* list partitions for given device */
+ part_num = 0;
+ list_for_each(pentry, &dev->parts) {
+ part = list_entry(pentry, struct part_info, link);
+ printf(" %d: %-22s\t0x%08x\t0x%08x\t%d\n",
+ part_num, part->name, part->size,
+ part->offset, part->mask_flags);
+
+ part_num++;
+ }
+ }
+ if (list_empty(&devices))
+ printf("no partitions defined\n");
+
+ /* current_dev is not NULL only when we have non empty device list */
+ if (current_dev) {
+ part = jffs2_part_info(current_dev, current_partnum);
+ if (part) {
+ printf("\nactive partition: %s%d,%d - (%s) 0x%08lx @ 0x%08lx\n",
+ MTD_DEV_TYPE(current_dev->id->type),
+ current_dev->id->num, current_partnum,
+ part->name, part->size, part->offset);
+ } else {
+ printf("could not get current partition info\n\n");
+ }
+ }
+
+ printf("\ndefaults:\n");
+ printf("mtdids : %s\n", mtdids_default);
+ printf("mtdparts: %s\n", mtdparts_default);
+}
+
+/**
+ * Given partition identifier in form of <dev_type><dev_num>,<part_num> find
+ * corresponding device and verify partition number.
+ *
+ * @param id string describing device and partition
+ * @param dev pointer to the requested device (output)
+ * @param part_num verified partition number (output)
+ * @param part pointer to requested partition (output)
+ * @return 0 on success, 1 otherwise
+ */
+int find_dev_and_part(const char *id, struct mtd_device **dev,
+ u8 *part_num, struct part_info **part)
+{
+ u8 type, dnum, pnum;
+ const char *p;
+
+ DEBUGF("--- find_dev_and_part ---\nid = %s\n", id);
+
+ p = id;
+ *dev = NULL;
+ *part = NULL;
+ *part_num = 0;
+
+ if (id_parse(p, &p, &type, &dnum) != 0)
+ return 1;
+
+ if ((*p++ != ',') || (*p == '\0')) {
+ printf("no partition number specified\n");
+ return 1;
+ }
+ pnum = simple_strtoul(p, (char **)&p, 0);
+ if (*p != '\0') {
+ printf("unexpected trailing character '%c'\n", *p);
+ return 1;
+ }
+
+ if ((*dev = device_find(type, dnum)) == NULL) {
+ printf("no such device %s%d\n", MTD_DEV_TYPE(type), dnum);
+ return 1;
+ }
+
+ if ((*part = jffs2_part_info(*dev, pnum)) == NULL) {
+ printf("no such partition\n");
+ *dev = NULL;
+ return 1;
+ }
+
+ *part_num = pnum;
+
+ return 0;
+}
+
+/**
+ * Find and delete partition. For partition id format see find_dev_and_part().
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * @param id string describing device and partition
+ * @return 0 on success, 1 otherwise
+ */
+static int delete_partition(const char *id)
+{
+ u8 pnum;
+ struct mtd_device *dev;
+ struct part_info *part;
+
+ if (find_dev_and_part(id, &dev, &pnum, &part) == 0) {
+
+ DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08lx@0x%08lx\n",
+ MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum,
+ part->name, part->size, part->offset);
+
+ if (part_del(dev, part) != 0)
+ return 1;
+
+ if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) {
+ printf("generated mtdparts too long, reseting to null\n");
+ return 1;
+ }
+ return 0;
+ }
+
+ printf("partition %s not found\n", id);
+ return 1;
+}
+
+/**
+ * Accept character string describing mtd partitions and call device_parse()
+ * for each entry. Add created devices to the global devices list.
*
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * @param mtdparts string specifing mtd partitions
+ * @return 0 on success, 1 otherwise
+ */
+static int parse_mtdparts(const char *const mtdparts)
+{
+ const char *p = mtdparts;
+ struct mtd_device *dev;
+ int err = 1;
+
+ DEBUGF("\n---parse_mtdparts---\nmtdparts = %s\n\n", p);
+
+ /* delete all devices and partitions */
+ if (devices_init() != 0) {
+ printf("could not initialise device list\n");
+ return err;
+ }
+
+ /* re-read 'mtdparts' variable, devices_init may be updating env */
+ p = getenv("mtdparts");
+
+ if (strncmp(p, "mtdparts=", 9) != 0) {
+ printf("mtdparts variable doesn't start with 'mtdparts='\n");
+ return err;
+ }
+ p += 9;
+
+ while (p && (*p != '\0')) {
+ err = 1;
+ if ((device_parse(p, &p, &dev) != 0) || (!dev))
+ break;
+
+ DEBUGF("+ device: %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
+ dev->id->num, dev->id->mtd_id);
+
+ /* check if parsed device is already on the list */
+ if (device_find(dev->id->type, dev->id->num) != NULL) {
+ printf("device %s%d redefined, please correct mtdparts variable\n",
+ MTD_DEV_TYPE(dev->id->type), dev->id->num);
+ break;
+ }
+
+ list_add_tail(&dev->link, &devices);
+ err = 0;
+ }
+ if (err == 1) {
+ device_delall(&devices);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * Parse provided string describing mtdids mapping (see file header for mtdids
+ * variable format). Allocate memory for each entry and add all found entries
+ * to the global mtdids list.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * @param ids mapping string
+ * @return 0 on success, 1 otherwise
*/
+static int parse_mtdids(const char *const ids)
+{
+ const char *p = ids;
+ const char *mtd_id;
+ int mtd_id_len;
+ struct mtdids *id;
+ struct list_head *entry, *n;
+ struct mtdids *id_tmp;
+ u8 type, num;
+ u32 size;
+ int ret = 1;
-/*
- * Boot support
+ DEBUGF("\n---parse_mtdids---\nmtdids = %s\n\n", ids);
+
+ /* clean global mtdids list */
+ list_for_each_safe(entry, n, &mtdids) {
+ id_tmp = list_entry(entry, struct mtdids, link);
+ DEBUGF("mtdids del: %d %d\n", id_tmp->type, id_tmp->num);
+ list_del(entry);
+ free(id_tmp);
+ }
+ last_ids[0] = '\0';
+ INIT_LIST_HEAD(&mtdids);
+
+ while(p && (*p != '\0')) {
+
+ ret = 1;
+ /* parse 'nor'|'nand'<dev-num> */
+ if (id_parse(p, &p, &type, &num) != 0)
+ break;
+
+ if (*p != '=') {
+ printf("mtdids: incorrect <dev-num>\n");
+ break;
+ }
+ p++;
+
+ /* check if requested device exists */
+ if (device_validate(type, num, &size) != 0)
+ return 1;
+
+ /* locate <mtd-id> */
+ mtd_id = p;
+ if ((p = strchr(mtd_id, ',')) != NULL) {
+ mtd_id_len = p - mtd_id + 1;
+ p++;
+ } else {
+ mtd_id_len = strlen(mtd_id) + 1;
+ }
+ if (mtd_id_len == 0) {
+ printf("mtdids: no <mtd-id> identifier\n");
+ break;
+ }
+
+ /* check if this id is already on the list */
+ int double_entry = 0;
+ list_for_each(entry, &mtdids) {
+ id_tmp = list_entry(entry, struct mtdids, link);
+ if ((id_tmp->type == type) && (id_tmp->num == num)) {
+ double_entry = 1;
+ break;
+ }
+ }
+ if (double_entry) {
+ printf("device id %s%d redefined, please correct mtdids variable\n",
+ MTD_DEV_TYPE(type), num);
+ break;
+ }
+
+ /* allocate mtdids structure */
+ if (!(id = (struct mtdids *)malloc(sizeof(struct mtdids) + mtd_id_len))) {
+ printf("out of memory\n");
+ break;
+ }
+ memset(id, 0, sizeof(struct mtdids) + mtd_id_len);
+ id->num = num;
+ id->type = type;
+ id->size = size;
+ id->mtd_id = (char *)(id + 1);
+ strncpy(id->mtd_id, mtd_id, mtd_id_len - 1);
+ id->mtd_id[mtd_id_len - 1] = '\0';
+ INIT_LIST_HEAD(&id->link);
+
+ DEBUGF("+ id %s%d\t%16d bytes\t%s\n",
+ MTD_DEV_TYPE(id->type), id->num,
+ id->size, id->mtd_id);
+
+ list_add_tail(&id->link, &mtdids);
+ ret = 0;
+ }
+ if (ret == 1) {
+ /* clean mtdids list and free allocated memory */
+ list_for_each_safe(entry, n, &mtdids) {
+ id_tmp = list_entry(entry, struct mtdids, link);
+ list_del(entry);
+ free(id_tmp);
+ }
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * Parse and initialize global mtdids mapping and create global
+ * device/partition list.
+ *
+ * @return 0 on success, 1 otherwise
*/
-#include <common.h>
-#include <command.h>
-#include <s_record.h>
-#include <jffs2/load_kernel.h>
-#include <net.h>
+int mtdparts_init(void)
+{
+ static int initialized = 0;
+ const char *ids, *parts;
+ const char *current_partition;
+ int ids_changed;
+ char tmp_ep[PARTITION_MAXLEN];
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+ DEBUGF("\n---mtdparts_init---\n");
+ if (!initialized) {
+ INIT_LIST_HEAD(&mtdids);
+ INIT_LIST_HEAD(&devices);
+ memset(last_ids, 0, MTDIDS_MAXLEN);
+ memset(last_parts, 0, MTDPARTS_MAXLEN);
+ memset(last_partition, 0, PARTITION_MAXLEN);
+ initialized = 1;
+ }
-#include <cramfs/cramfs_fs.h>
+ /* get variables */
+ ids = getenv("mtdids");
+ parts = getenv("mtdparts");
+ current_partition = getenv("partition");
-extern int cramfs_check (struct part_info *info);
-extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename);
-extern int cramfs_ls (struct part_info *info, char *filename);
-extern int cramfs_info (struct part_info *info);
+ /* save it for later parsing, cannot rely on current partition pointer
+ * as 'partition' variable may be updated during init */
+ tmp_ep[0] = '\0';
+ if (current_partition)
+ strncpy(tmp_ep, current_partition, PARTITION_MAXLEN);
+
+ DEBUGF("last_ids : %s\n", last_ids);
+ DEBUGF("env_ids : %s\n", ids);
+ DEBUGF("last_parts: %s\n", last_parts);
+ DEBUGF("env_parts : %s\n\n", parts);
+
+ DEBUGF("last_partition : %s\n", last_partition);
+ DEBUGF("env_partition : %s\n", current_partition);
+
+ /* if mtdids varible is empty try to use defaults */
+ if (!ids) {
+ if (mtdids_default) {
+ DEBUGF("mtdids variable not defined, using default\n");
+ ids = mtdids_default;
+ setenv("mtdids", (char *)ids);
+ } else {
+ printf("mtdids not defined, no default present\n");
+ return 1;
+ }
+ }
+ if (strlen(ids) > MTDIDS_MAXLEN - 1) {
+ printf("mtdids too long (> %d)\n", MTDIDS_MAXLEN);
+ return 1;
+ }
+
+ /* do no try to use defaults when mtdparts variable is not defined,
+ * just check the length */
+ if (!parts)
+ printf("mtdparts variable not set, see 'help mtdparts'\n");
+
+ if (parts && (strlen(parts) > MTDPARTS_MAXLEN - 1)) {
+ printf("mtdparts too long (> %d)\n", MTDPARTS_MAXLEN);
+ return 1;
+ }
+
+ /* check if we have already parsed those mtdids */
+ if ((last_ids[0] != '\0') && (strcmp(last_ids, ids) == 0)) {
+ ids_changed = 0;
+ } else {
+ ids_changed = 1;
+
+ if (parse_mtdids(ids) != 0) {
+ device_delall(&devices);
+ return 1;
+ }
+
+ /* ok it's good, save new ids */
+ strncpy(last_ids, ids, MTDIDS_MAXLEN);
+ }
+
+ /* parse partitions if either mtdparts or mtdids were updated */
+ if (parts && ((last_parts[0] == '\0') || ((strcmp(last_parts, parts) != 0)) || ids_changed)) {
+ if (parse_mtdparts(parts) != 0)
+ return 1;
+
+ if (list_empty(&devices)) {
+ printf("mtdparts_init: no valid partitions\n");
+ return 1;
+ }
+
+ /* ok it's good, save new parts */
+ strncpy(last_parts, parts, MTDPARTS_MAXLEN);
+
+ /* reset first partition from first dev from the list as current */
+ current_dev = list_entry(devices.next, struct mtd_device, link);
+ current_partnum = 0;
+ current_save();
-static int part_num=0;
+ DEBUGF("mtdparts_init: current_dev = %s%d, current_partnum = %d\n",
+ MTD_DEV_TYPE(current_dev->id->type),
+ current_dev->id->num, current_partnum);
+ }
+
+ /* mtdparts variable was reset to NULL, delete all devices/partitions */
+ if (!parts && (last_parts[0] != '\0'))
+ return devices_init();
+
+ /* do not process current partition if mtdparts variable is null */
+ if (!parts)
+ return 0;
-#ifndef CFG_JFFS_CUSTOM_PART
+ /* is current partition set in environment? if so, use it */
+ if ((tmp_ep[0] != '\0') && (strcmp(tmp_ep, last_partition) != 0)) {
+ struct part_info *p;
+ struct mtd_device *cdev;
+ u8 pnum;
-#define CFG_JFFS_SINGLE_PART 1
+ DEBUGF("--- getting current partition: %s\n", tmp_ep);
-static struct part_info part;
+ if (find_dev_and_part(tmp_ep, &cdev, &pnum, &p) == 0) {
+ current_dev = cdev;
+ current_partnum = pnum;
+ current_save();
+ }
+ } else if (getenv("partition") == NULL) {
+ DEBUGF("no partition variable set, setting...\n");
+ current_save();
+ }
-#ifndef CONFIG_JFFS2_NAND
+ return 0;
+}
+#else /* #ifdef CONFIG_JFFS2_CMDLINE */
+/*
+ * 'Static' version of command line mtdparts_init() routine. Single partition on
+ * a single device configuration.
+ */
-struct part_info*
-jffs2_part_info(int part_num)
+/**
+ * Parse and initialize global mtdids mapping and create global
+ * device/partition list.
+ *
+ * @return 0 on success, 1 otherwise
+ */
+int mtdparts_init(void)
{
- extern flash_info_t flash_info[]; /* info for FLASH chips */
- int i;
+ static int initialized = 0;
+ u32 size;
+ char *dev_name;
+
+ DEBUGF("\n---mtdparts_init---\n");
+ if (!initialized) {
+ struct mtdids *id;
+ struct part_info *part;
- if(part_num==0){
+ initialized = 1;
+ current_dev = (struct mtd_device *)
+ malloc(sizeof(struct mtd_device) +
+ sizeof(struct part_info) +
+ sizeof(struct mtdids));
+ if (!current_dev) {
+ printf("out of memory\n");
+ return 1;
+ }
+ memset(current_dev, 0, sizeof(struct mtd_device) +
+ sizeof(struct part_info) + sizeof(struct mtdids));
- if(part.usr_priv==(void*)1)
- return ∂
+ id = (struct mtdids *)(current_dev + 1);
+ part = (struct part_info *)(id + 1);
- memset(&part, 0, sizeof(part));
+ /* id */
+ id->mtd_id = "single part";
-#if defined(CFG_JFFS2_FIRST_SECTOR)
- part.offset = (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
+#if defined(CONFIG_JFFS2_DEV)
+ dev_name = CONFIG_JFFS2_DEV;
#else
- part.offset = (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+ dev_name = "nor0";
#endif
- /* Figure out flash partition size */
- for (i = CFG_JFFS2_FIRST_BANK; i < CFG_JFFS2_NUM_BANKS+CFG_JFFS2_FIRST_BANK; i++)
- part.size += flash_info[i].size;
+ if ((id_parse(dev_name, NULL, &id->type, &id->num) != 0) ||
+ (device_validate(id->type, id->num, &size) != 0)) {
+ printf("incorrect device: %s%d\n", MTD_DEV_TYPE(id->type), id->num);
+ free(current_dev);
+ return 1;
+ }
+ id->size = size;
+ INIT_LIST_HEAD(&id->link);
+
+ DEBUGF("dev id: type = %d, num = %d, size = 0x%08lx, mtd_id = %s\n",
+ id->type, id->num, id->size, id->mtd_id);
+
+ /* partition */
+ part->name = "static";
+ part->auto_name = 0;
+
+#if defined(CONFIG_JFFS2_PART_SIZE)
+ part->size = CONFIG_JFFS2_PART_SIZE;
+#else
+ part->size = SIZE_REMAINING;
+#endif
-#if defined(CFG_JFFS2_FIRST_SECTOR) && (CFG_JFFS2_FIRST_SECTOR > 0)
- part.size -=
- flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
- flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#if defined(CONFIG_JFFS2_PART_OFFSET)
+ part->offset = CONFIG_JFFS2_PART_OFFSET;
+#else
+ part->offset = 0x00000000;
#endif
- /* Mark the struct as ready */
- part.usr_priv=(void*)1;
+ part->dev = current_dev;
+ INIT_LIST_HEAD(&part->link);
+
+ /* recalculate size if needed */
+ if (part->size == SIZE_REMAINING)
+ part->size = id->size - part->offset;
+
+ DEBUGF("part : name = %s, size = 0x%08lx, offset = 0x%08lx\n",
+ part->name, part->size, part->offset);
- return ∂
+ /* device */
+ current_dev->id = id;
+ INIT_LIST_HEAD(¤t_dev->link);
+ current_dev->num_parts = 1;
+ INIT_LIST_HEAD(¤t_dev->parts);
+ list_add(&part->link, ¤t_dev->parts);
}
+
return 0;
}
+#endif /* #ifdef CONFIG_JFFS2_CMDLINE */
-#else /* CONFIG_JFFS2_NAND */
-
-struct part_info*
-jffs2_part_info(int part_num)
+/**
+ * Return pointer to the partition of a requested number from a requested
+ * device.
+ *
+ * @param dev device that is to be searched for a partition
+ * @param part_num requested partition number
+ * @return pointer to the part_info, NULL otherwise
+ */
+static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num)
{
- if(part_num==0){
+ struct list_head *entry;
+ struct part_info *part;
+ int num;
+
+ if (!dev)
+ return NULL;
- if(part.usr_priv==(void*)1)
- return ∂
+ DEBUGF("\n--- jffs2_part_info: partition number %d for device %s%d (%s)\n",
+ part_num, MTD_DEV_TYPE(dev->id->type),
+ dev->id->num, dev->id->mtd_id);
- memset(&part, 0, sizeof(part));
+ if (part_num >= dev->num_parts) {
+ printf("invalid partition number %d for device %s%d (%s)\n",
+ part_num, MTD_DEV_TYPE(dev->id->type),
+ dev->id->num, dev->id->mtd_id);
+ return NULL;
+ }
- part.offset = (char *)CONFIG_JFFS2_NAND_OFF;
- part.size = CONFIG_JFFS2_NAND_SIZE; /* the bigger size the slower jffs2 */
+ /* locate partition number, return it */
+ num = 0;
+ list_for_each(entry, &dev->parts) {
+ part = list_entry(entry, struct part_info, link);
-#ifndef CONFIG_JFFS2_NAND_DEV
-#define CONFIG_JFFS2_NAND_DEV 0
-#endif
- /* nand device with the JFFS2 parition plus 1 */
- part.usr_priv = (void*)(CONFIG_JFFS2_NAND_DEV+1);
- return ∂
+ if (part_num == num++) {
+ return part;
+ }
}
- return 0;
+
+ return NULL;
}
-#endif /* CONFIG_JFFS2_NAND */
-#endif /* ifndef CFG_JFFS_CUSTOM_PART */
+/***************************************************/
+/* U-boot commands */
+/***************************************************/
-int
-do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/**
+ * Routine implementing fsload u-boot command. This routine tries to load
+ * a requested file from jffs2/cramfs filesystem on a current partition.
+ *
+ * @param cmdtp command internal data
+ * @param flag command flag
+ * @param argc number of arguments supplied to the command
+ * @param argv arguments list
+ * @return 0 on success, 1 otherwise
+ */
+int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- struct part_info* jffs2_part_info(int);
- int jffs2_1pass_load(char *, struct part_info *,const char *);
char *fsname;
char *filename;
int size;
filename = argv[2];
}
- if (0 != (part=jffs2_part_info(part_num))){
+ /* make sure we are in sync with env variables */
+ if (mtdparts_init() !=0)
+ return 1;
+
+ if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
return !(size > 0);
}
- puts ("Active partition not valid\n");
- return 0;
+ return 1;
}
-int
-do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/**
+ * Routine implementing u-boot ls command which lists content of a given
+ * directory on a current partition.
+ *
+ * @param cmdtp command internal data
+ * @param flag command flag
+ * @param argc number of arguments supplied to the command
+ * @param argv arguments list
+ * @return 0 on success, 1 otherwise
+ */
+int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- struct part_info* jffs2_part_info(int);
- int jffs2_1pass_ls(struct part_info *,char *);
char *filename = "/";
int ret;
struct part_info *part;
if (argc == 2)
filename = argv[1];
- if (0 != (part=jffs2_part_info(part_num))){
+ /* make sure we are in sync with env variables */
+ if (mtdparts_init() !=0)
+ return 1;
+
+ if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
if (cramfs_check(part)) {
ret = jffs2_1pass_ls(part, filename);
}
- return (ret == 1);
+ return ret ? 0 : 1;
}
- puts ("Active partition not valid\n");
- return 0;
+ return 1;
}
-int
-do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/**
+ * Routine implementing u-boot fsinfo command. This routine prints out
+ * miscellaneous filesystem informations/statistics.
+ *
+ * @param cmdtp command internal data
+ * @param flag command flag
+ * @param argc number of arguments supplied to the command
+ * @param argv arguments list
+ * @return 0 on success, 1 otherwise
+ */
+int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- struct part_info* jffs2_part_info(int);
- int jffs2_1pass_info(struct part_info *);
struct part_info *part;
char *fsname;
int ret;
- if ((part=jffs2_part_info(part_num))){
+ /* make sure we are in sync with env variables */
+ if (mtdparts_init() !=0)
+ return 1;
+
+ if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
ret = jffs2_1pass_info(part);
}
- return (ret == 1);
+ return ret ? 0 : 1;
}
- puts ("Active partition not valid\n");
+ return 1;
+}
+
+/* command line only */
+#ifdef CONFIG_JFFS2_CMDLINE
+/**
+ * Routine implementing u-boot chpart command. Sets new current partition based
+ * on the user supplied partition id. For partition id format see find_dev_and_part().
+ *
+ * @param cmdtp command internal data
+ * @param flag command flag
+ * @param argc number of arguments supplied to the command
+ * @param argv arguments list
+ * @return 0 on success, 1 otherwise
+ */
+int do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+/* command line only */
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 pnum;
+
+ if (mtdparts_init() !=0)
+ return 1;
+
+ if (argc < 2) {
+ printf("no partition id specified\n");
+ return 1;
+ }
+
+ if (find_dev_and_part(argv[1], &dev, &pnum, &part) != 0)
+ return 1;
+
+ current_dev = dev;
+ current_partnum = pnum;
+ current_save();
+
+ printf("partition changed to %s%d,%d\n",
+ MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum);
+
return 0;
}
-#ifndef CFG_JFFS_SINGLE_PART
-int
-do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/**
+ * Routine implementing u-boot mtdparts command. Initialize/update default global
+ * partition list and process user partition request (list, add, del).
+ *
+ * @param cmdtp command internal data
+ * @param flag command flag
+ * @param argc number of arguments supplied to the command
+ * @param argv arguments list
+ * @return 0 on success, 1 otherwise
+ */
+int do_jffs2_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- int tmp_part;
- char str_part_num[3];
- struct part_info* jffs2_part_info(int);
+ if (argc == 2) {
+ if (strcmp(argv[1], "default") == 0) {
+ setenv("mtdids", (char *)mtdids_default);
+ setenv("mtdparts", (char *)mtdparts_default);
+ setenv("partition", NULL);
- if (argc >= 2) {
- tmp_part = simple_strtoul(argv[1], NULL, 16);
- } else {
- puts ("Need partition number in argument list\n");
- return 0;
+ mtdparts_init();
+ return 0;
+ } else if (strcmp(argv[1], "delall") == 0) {
+ /* this may be the first run, initialize lists if needed */
+ mtdparts_init();
+ setenv("mtdparts", NULL);
+
+ /* devices_init() calls current_save() */
+ return devices_init();
+ }
}
- if (jffs2_part_info(tmp_part)){
- printf("Partition changed to %d\n",tmp_part);
- part_num=tmp_part;
- sprintf(str_part_num, "%d", part_num);
- setenv("partition", str_part_num);
+ /* make sure we are in sync with env variables */
+ if (mtdparts_init() != 0)
+ return 1;
+
+ if (argc == 1) {
+ list_partitions();
return 0;
}
- printf("Partition %d is not valid partiton\n",tmp_part);
- return 0;
+ /* mtdparts add <mtd-dev> <size>[@<offset>] <name> [ro] */
+ if (((argc == 5) || (argc == 6)) && (strcmp(argv[1], "add") == 0)) {
+#define PART_ADD_DESC_MAXLEN 64
+ char tmpbuf[PART_ADD_DESC_MAXLEN];
+ u8 type, num, len;
+ struct mtd_device *dev;
+ struct mtd_device *dev_tmp;
+ struct mtdids *id;
+ struct part_info *p;
-}
+ if (id_parse(argv[2], NULL, &type, &num) != 0)
+ return 1;
-U_BOOT_CMD(
- chpart, 2, 0, do_jffs2_chpart,
- "chpart\t- change active partition\n",
- " - change active partition\n"
-);
-#endif /* CFG_JFFS_SINGLE_PART */
+ if ((id = id_find(type, num)) == NULL) {
+ printf("no such device %s defined in mtdids variable\n", argv[2]);
+ return 1;
+ }
-/***************************************************/
+ len = strlen(id->mtd_id) + 1; /* 'mtd_id:' */
+ len += strlen(argv[3]); /* size@offset */
+ len += strlen(argv[4]) + 2; /* '(' name ')' */
+ if (argv[5] && (strlen(argv[5]) == 2))
+ len += 2; /* 'ro' */
+
+ if (len >= PART_ADD_DESC_MAXLEN) {
+ printf("too long partition description\n");
+ return 1;
+ }
+ sprintf(tmpbuf, "%s:%s(%s)%s",
+ id->mtd_id, argv[3], argv[4], argv[5] ? argv[5] : "");
+ DEBUGF("add tmpbuf: %s\n", tmpbuf);
+
+ if ((device_parse(tmpbuf, NULL, &dev) != 0) || (!dev))
+ return 1;
+ DEBUGF("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
+ dev->id->num, dev->id->mtd_id);
+
+ if ((dev_tmp = device_find(dev->id->type, dev->id->num)) == NULL) {
+ device_add(dev);
+ } else {
+ /* merge new partition with existing ones*/
+ p = list_entry(dev->parts.next, struct part_info, link);
+ if (part_add(dev_tmp, p) != 0) {
+ device_del(dev);
+ return 1;
+ }
+ }
+
+ if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) {
+ printf("generated mtdparts too long, reseting to null\n");
+ return 1;
+ }
+
+ return 0;
+ }
+
+ /* mtdparts del part-id */
+ if ((argc == 3) && (strcmp(argv[1], "del") == 0)) {
+ DEBUGF("del: part-id = %s\n", argv[2]);
+
+ return delete_partition(argv[2]);
+ }
+
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+}
+#endif /* #ifdef CONFIG_JFFS2_CMDLINE */
+
+/***************************************************/
U_BOOT_CMD(
fsload, 3, 0, do_jffs2_fsload,
"fsload\t- load binary file from a filesystem image\n",
" - load binary file from flash bank\n"
" with offset 'off'\n"
);
+U_BOOT_CMD(
+ ls, 2, 1, do_jffs2_ls,
+ "ls\t- list files in a directory (default /)\n",
+ "[ directory ]\n"
+ " - list files in a directory.\n"
+);
U_BOOT_CMD(
fsinfo, 1, 1, do_jffs2_fsinfo,
" - print information about filesystems\n"
);
+#ifdef CONFIG_JFFS2_CMDLINE
U_BOOT_CMD(
- ls, 2, 1, do_jffs2_ls,
- "ls\t- list files in a directory (default /)\n",
- "[ directory ]\n"
- " - list files in a directory.\n"
+ chpart, 2, 0, do_jffs2_chpart,
+ "chpart\t- change active partition\n",
+ "part-id\n"
+ " - change active partition (e.g. part-id = nand0,1)\n"
+);
+
+U_BOOT_CMD(
+ mtdparts, 6, 0, do_jffs2_mtdparts,
+ "mtdparts- define flash/nand partitions\n",
+ "\n"
+ " - list partition table\n"
+ "mtdparts delall\n"
+ " - delete all partitions\n"
+ "mtdparts del part-id\n"
+ " - delete partition (e.g. part-id = nand0,1)\n"
+ "mtdparts add <mtd-dev> <size>[@<offset>] [<name>] [ro]\n"
+ " - add partition\n"
+ "mtdparts default\n"
+ " - reset partition table to defaults\n\n"
+ "-----\n\n"
+ "this command uses three environment variables:\n\n"
+ "'partition' - keeps current partition identifier\n\n"
+ "partition := <part-id>\n"
+ "<part-id> := <dev-id>,part_num\n\n"
+ "'mtdids' - linux kernel mtd device id <-> u-boot device id mapping\n\n"
+ "mtdids=<idmap>[,<idmap>,...]\n\n"
+ "<idmap> := <dev-id>=<mtd-id>\n"
+ "<dev-id> := 'nand'|'nor'<dev-num>\n"
+ "<dev-num> := mtd device number, 0...\n"
+ "<mtd-id> := unique device tag used by linux kernel to find mtd device (mtd->name)\n\n"
+ "'mtdparts' - partition list\n\n"
+ "mtdparts=mtdparts=<mtd-def>[;<mtd-def>...]\n\n"
+ "<mtd-def> := <mtd-id>:<part-def>[,<part-def>...]\n"
+ "<mtd-id> := unique device tag used by linux kernel to find mtd device (mtd->name)\n"
+ "<part-def> := <size>[@<offset>][<name>][<ro-flag>]\n"
+ "<size> := standard linux memsize OR '-' to denote all remaining space\n"
+ "<offset> := partition start offset within the device\n"
+ "<name> := '(' NAME ')'\n"
+ "<ro-flag> := when set to 'ro' makes partition read-only (not used, passed to kernel)\n"
);
+#endif /* #ifdef CONFIG_JFFS2_CMDLINE */
+
+/***************************************************/
#endif /* CFG_CMD_JFFS2 */
U_BOOT_CMD(
mii, 5, 1, do_mii,
"mii - MII utility commands\n",
- "info <addr> - display MII PHY info\n"
+ "info <addr> - display MII PHY info\n"
"mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
"mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
"mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
}
+
+U_BOOT_CMD(
+ scsi, 5, 1, do_scsi,
+ "scsi - SCSI sub-system\n",
+ "reset - reset SCSI controller\n"
+ "scsi info - show available SCSI devices\n"
+ "scsi scan - (re-)scan SCSI bus\n"
+ "scsi device [dev] - show or set current device\n"
+ "scsi part [dev] - print partition table of one or all SCSI devices\n"
+ "scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
+ " to memory address `addr'\n"
+);
+
+U_BOOT_CMD(
+ scsiboot, 3, 1, do_scsiboot,
+ "scsiboot- boot from SCSI device\n",
+ "loadAddr dev:part\n"
+);
+
#endif /* #if (CONFIG_COMMANDS & CFG_CMD_SCSI) */
block_dev_desc_t *stor_dev;
#endif
- if ((strncmp(argv[1],"reset",5) == 0) ||
- (strncmp(argv[1],"start",5) == 0)){
+ if ((strncmp(argv[1], "reset", 5) == 0) ||
+ (strncmp(argv[1], "start", 5) == 0)){
usb_stop();
printf("(Re)start USB...\n");
- usb_init();
+ i = usb_init();
+#ifdef CONFIG_USB_STORAGE
+ /* try to recognize storage devices immediately */
+ if (i >= 0)
+ usb_stor_curr_dev = usb_stor_scan(1);
+#endif
return 0;
}
if (strncmp(argv[1],"stop",4) == 0) {
return 0;
}
#ifdef CONFIG_USB_STORAGE
- if (strncmp(argv[1],"scan",4) == 0) {
- printf("Scan for storage device:\n");
- usb_stor_curr_dev=usb_stor_scan(1);
- if (usb_stor_curr_dev==-1) {
- printf("No device found. Not initialized?\n");
- return 1;
- }
+ if (strncmp(argv[1], "scan", 4) == 0) {
+ printf(" NOTE: this command is obsolete and will be phased out\n");
+ printf(" please use 'usb storage' for USB storage devices information\n\n");
+ usb_stor_info();
return 0;
}
+
+ if (strncmp(argv[1], "stor", 4) == 0) {
+ usb_stor_info();
+ return 0;
+ }
+
if (strncmp(argv[1],"part",4) == 0) {
int devno, ok;
for (ok=0, devno=0; devno<USB_MAX_STOR_DEV; ++devno) {
return 1;
}
}
- if (strcmp(argv[1],"dev") == 0) {
- if (argc==3) {
+ if (strncmp(argv[1], "dev", 3) == 0) {
+ if (argc == 3) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
printf ("\nUSB device %d: ", dev);
if (dev >= USB_MAX_STOR_DEV) {
"usb stop [f] - stop USB [f]=force stop\n"
"usb tree - show USB device tree\n"
"usb info [dev] - show available USB devices\n"
- "usb scan - (re-)scan USB bus for storage devices\n"
- "usb device [dev] - show or set current USB storage device\n"
+ "usb storage - show details of USB storage devices\n"
+ "usb dev [dev] - show or set current USB storage device\n"
"usb part [dev] - print partition table of one or all USB storage devices\n"
"usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
" to memory address `addr'\n"
* MA 02111-1307 USA
*/
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__ /* Dirty trick to get only #defines */
+#endif
+#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
#include <config.h>
+#undef __ASSEMBLY__
#include <environment.h>
/*
int n;
static char the_command[CFG_CBSIZE];
+#ifdef CONFIG_BOOT_RETRY_TIME
+# ifdef CONFIG_RESET_TO_RETRY
+ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+# else
+# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
+# endif
+ reset_cmd_timeout();
+#endif
i->__promptme = 1;
if (i->promptmode == 1) {
n = readline(CFG_PROMPT);
} else {
n = readline(CFG_PROMPT_HUSH_PS2);
}
+#ifdef CONFIG_BOOT_RETRY_TIME
+ if (n == -2) {
+ puts("\nTimeout waiting for command\n");
+# ifdef CONFIG_RESET_TO_RETRY
+ do_reset(NULL, 0, 0, NULL);
+# else
+# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
+# endif
+ }
+#endif
if (n == -1 ) {
flag_repeat = 0;
i->__promptme = 0;
/************************************************************************/
#include <video_font.h> /* Get font data, width and height */
+/************************************************************************/
+/* ** LOGO DATA */
+/************************************************************************/
+#ifdef CONFIG_LCD_LOGO
+# include <bmp_logo.h> /* Get logo data, width and height */
+# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
+# error Default Color Map overlaps with Logo Color Map
+# endif
+#endif
ulong lcd_setmem (ulong addr);
static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
{
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen (s));
#else
lcd_drawchars (x, y, s, strlen (s));
static inline void lcd_putc_xy (ushort x, ushort y, uchar c)
{
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
lcd_drawchars (x, y+BMP_LOGO_HEIGHT, &c, 1);
#else
lcd_drawchars (x, y, &c, 1);
/* Initialize the console */
console_col = 0;
-#ifdef LCD_INFO_BELOW_LOGO
+#ifdef CONFIG_LCD_INFO_BELOW_LOGO
console_row = 7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT;
#else
console_row = 1; /* leave 1 blank line below logo */
static void *lcd_logo (void)
{
-#ifdef LCD_INFO
+#ifdef CONFIG_LCD_INFO
DECLARE_GLOBAL_DATA_PTR;
char info[80];
char temp[32];
-#endif /* LCD_INFO */
+#endif /* CONFIG_LCD_INFO */
#ifdef CONFIG_SPLASH_SCREEN
char *s;
#endif /* CONFIG_LCD_LOGO */
#ifdef CONFIG_MPC823
-#ifdef LCD_INFO
+# ifdef CONFIG_LCD_INFO
sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, info, strlen(info));
sprintf (info, " Wolfgang DENK, wd@denx.de");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info, strlen(info));
-#ifdef LCD_INFO_BELOW_LOGO
+# ifdef CONFIG_LCD_INFO_BELOW_LOGO
sprintf (info, "MPC823 CPU at %s MHz",
strmhz(temp, gd->cpu_clk));
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3,
gd->bd->bi_flashsize >> 20 );
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
info, strlen(info));
-#else
+# else
/* leave one blank line */
sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash",
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
info, strlen(info));
+# endif /* CONFIG_LCD_INFO_BELOW_LOGO */
+# endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_MPC823 */
-#endif /* LCD_INFO_BELOW_LOGO */
-#endif /* LCD_INFO */
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length));
#else
return ((void *)lcd_base);
-#endif /* CONFIG_LCD_LOGO */
+#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */
}
/************************************************************************/
#if defined(CONFIG_LYNXKDI)
#include <lynxkdi.h>
-#if defined(CONFIG_MPC8260)
+#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
void lynxkdi_boot ( image_header_t *hdr )
{
void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep;
* Utility to send the preamble, address, and register (common to read
* and write).
*/
-static void miiphy_pre(char read,
- unsigned char addr,
- unsigned char reg)
+static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
- int j; /* counter */
- volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
-
- /*
- * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
- * The IEEE spec says this is a PHY optional requirement. The AMD
- * 79C874 requires one after power up and one after a MII communications
- * error. This means that we are doing more preambles than we need,
- * but it is safer and will be much more robust.
- */
-
- MDIO_ACTIVE;
- MDIO(1);
- for(j = 0; j < 32; j++)
- {
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- }
-
- /* send the start bit (01) and the read opcode (10) or write (10) */
- MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(read); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(!read); MIIDELAY; MDC(1); MIIDELAY;
-
- /* send the PHY address */
- for(j = 0; j < 5; j++)
- {
- MDC(0);
- if((addr & 0x10) == 0)
- {
- MDIO(0);
- }
- else
- {
- MDIO(1);
- }
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- addr <<= 1;
- }
-
- /* send the register address */
- for(j = 0; j < 5; j++)
- {
- MDC(0);
- if((reg & 0x10) == 0)
- {
- MDIO(0);
- }
- else
- {
- MDIO(1);
- }
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- reg <<= 1;
- }
+ int j; /* counter */
+#ifndef CONFIG_EP8248
+ volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
+
+ /*
+ * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
+ * The IEEE spec says this is a PHY optional requirement. The AMD
+ * 79C874 requires one after power up and one after a MII communications
+ * error. This means that we are doing more preambles than we need,
+ * but it is safer and will be much more robust.
+ */
+
+ MDIO_ACTIVE;
+ MDIO (1);
+ for (j = 0; j < 32; j++) {
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ }
+
+ /* send the start bit (01) and the read opcode (10) or write (10) */
+ MDC (0);
+ MDIO (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (1);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (read);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (!read);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ /* send the PHY address */
+ for (j = 0; j < 5; j++) {
+ MDC (0);
+ if ((addr & 0x10) == 0) {
+ MDIO (0);
+ } else {
+ MDIO (1);
+ }
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ addr <<= 1;
+ }
+
+ /* send the register address */
+ for (j = 0; j < 5; j++) {
+ MDC (0);
+ if ((reg & 0x10) == 0) {
+ MDIO (0);
+ } else {
+ MDIO (1);
+ }
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ reg <<= 1;
+ }
}
* Returns:
* 0 on success
*/
-int miiphy_read(unsigned char addr,
- unsigned char reg,
- unsigned short *value)
+int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
{
- short rdreg; /* register working value */
- int j; /* counter */
- volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
-
- miiphy_pre(1, addr, reg);
-
- /* tri-state our MDIO I/O pin so we can read */
- MDC(0);
- MDIO_TRISTATE;
- MIIDELAY;
- MDC(1);
- MIIDELAY;
-
- /* check the turnaround bit: the PHY should be driving it to zero */
- if(MDIO_READ != 0)
- {
- /* puts ("PHY didn't drive TA low\n"); */
- for(j = 0; j < 32; j++)
- {
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- }
- return(-1);
- }
-
- MDC(0);
- MIIDELAY;
-
- /* read 16 bits of register data, MSB first */
- rdreg = 0;
- for(j = 0; j < 16; j++)
- {
- MDC(1);
- MIIDELAY;
- rdreg <<= 1;
- rdreg |= MDIO_READ;
- MDC(0);
- MIIDELAY;
- }
-
- MDC(1);
- MIIDELAY;
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
-
- *value = rdreg;
+ short rdreg; /* register working value */
+ int j; /* counter */
+#ifndef CONFIG_EP8248
+ volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
+
+ miiphy_pre (1, addr, reg);
+
+ /* tri-state our MDIO I/O pin so we can read */
+ MDC (0);
+ MDIO_TRISTATE;
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ /* check the turnaround bit: the PHY should be driving it to zero */
+ if (MDIO_READ != 0) {
+ /* puts ("PHY didn't drive TA low\n"); */
+ for (j = 0; j < 32; j++) {
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ }
+ return (-1);
+ }
+
+ MDC (0);
+ MIIDELAY;
+
+ /* read 16 bits of register data, MSB first */
+ rdreg = 0;
+ for (j = 0; j < 16; j++) {
+ MDC (1);
+ MIIDELAY;
+ rdreg <<= 1;
+ rdreg |= MDIO_READ;
+ MDC (0);
+ MIIDELAY;
+ }
+
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ *value = rdreg;
#ifdef DEBUG
- printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
+ printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
#endif
- return 0;
+ return 0;
}
* Returns:
* 0 on success
*/
-int miiphy_write(unsigned char addr,
- unsigned char reg,
- unsigned short value)
+int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
{
- int j; /* counter */
- volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
-
- miiphy_pre(0, addr, reg);
-
- /* send the turnaround (10) */
- MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
-
- /* write 16 bits of register data, MSB first */
- for(j = 0; j < 16; j++)
- {
- MDC(0);
- if((value & 0x00008000) == 0)
- {
- MDIO(0);
- }
- else
- {
- MDIO(1);
- }
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- value <<= 1;
- }
-
- /*
- * Tri-state the MDIO line.
- */
- MDIO_TRISTATE;
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
-
- return 0;
+ int j; /* counter */
+#ifndef CONFIG_EP8248
+ volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
+
+ miiphy_pre (0, addr, reg);
+
+ /* send the turnaround (10) */
+ MDC (0);
+ MDIO (1);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ /* write 16 bits of register data, MSB first */
+ for (j = 0; j < 16; j++) {
+ MDC (0);
+ if ((value & 0x00008000) == 0) {
+ MDIO (0);
+ } else {
+ MDIO (1);
+ }
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ value <<= 1;
+ }
+
+ /*
+ * Tri-state the MDIO line.
+ */
+ MDIO_TRISTATE;
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ return 0;
}
#endif /* CONFIG_BITBANGMII */
unsigned short reg;
int loop_cnt;
- if (miiphy_write (addr, PHY_BMCR, 0x8000) != 0) {
+ if (miiphy_read (addr, PHY_BMCR, ®) != 0) {
+#ifdef DEBUG
+ printf ("PHY status read failed\n");
+#endif
+ return (-1);
+ }
+ if (miiphy_write (addr, PHY_BMCR, reg | 0x8000) != 0) {
#ifdef DEBUG
puts ("PHY reset failed\n");
#endif
/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
*
* Most of this source has been derived from the Linux USB
- * project.
+ * project:
+ * (C) Copyright Linus Torvalds 1999
+ * (C) Copyright Johannes Erdfelt 1999-2001
+ * (C) Copyright Andreas Gal 1999
+ * (C) Copyright Gregory P. Smith 1999
+ * (C) Copyright Deti Fliegl 1999 (new USB architecture)
+ * (C) Copyright Randy Dunlap 2000
+ * (C) Copyright David Brownell 2000 (kernel hotplug, usb_device_id)
+ * (C) Copyright Yggdrasil Computing, Inc. 2000
+ * (usb_device_id matching changes by Adam J. Richter)
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
#include <command.h>
#include <asm/processor.h>
+#include <linux/ctype.h>
#if (CONFIG_COMMANDS & CFG_CMD_USB)
#include <405gp_pci.h>
#endif
-
-/* #define USB_DEBUG */
+#undef USB_DEBUG
#ifdef USB_DEBUG
#define USB_PRINTF(fmt,args...) printf (fmt ,##args)
int usb_hub_probe(struct usb_device *dev, int ifnum);
void usb_hub_reset(void);
+
/***********************************************************************
* wait_ms
*/
{
if((timeout==0)&&(!asynch_allowed)) /* request for a asynch control pipe is not allowed */
return -1;
+
/* set setup command */
setup_packet.requesttype = requesttype;
setup_packet.request = request;
int usb_clear_halt(struct usb_device *dev, int pipe)
{
int result;
- unsigned short status;
- int endp=usb_pipeendpoint(pipe)|(usb_pipein(pipe)<<7);
+ int endp = usb_pipeendpoint(pipe)|(usb_pipein(pipe)<<7);
result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, endp, NULL, 0, USB_CNTL_TIMEOUT * 3);
/* don't clear if failed */
if (result < 0)
return result;
- result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
- USB_REQ_GET_STATUS, USB_DIR_IN | USB_RECIP_ENDPOINT, 0, endp,
- &status, sizeof(status), USB_CNTL_TIMEOUT * 3);
- if (result < 0)
- return result;
- USB_PRINTF("usb_clear_halt: status 0x%x\n",status);
- if (status & 1)
- return -1; /* still halted */
+
+ /*
+ * NOTE: we do not get status and verify reset was successful
+ * as some devices are reported to lock up upon this check..
+ */
+
usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+
/* toggle is reset on clear */
usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0);
return 0;
struct usb_interface_descriptor *if_face = NULL;
int ret, i;
- for (i=0; i<dev->config.bNumInterfaces; i++) {
+ for (i = 0; i < dev->config.bNumInterfaces; i++) {
if (dev->config.if_desc[i].bInterfaceNumber == interface) {
if_face = &dev->config.if_desc[i];
break;
interface, NULL, 0, USB_CNTL_TIMEOUT * 5)) < 0)
return ret;
- if_face->act_altsetting = (unsigned char)alternate;
- usb_set_maxpacket(dev);
return 0;
}
*/
int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char index, void *buf, int size)
{
- return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
- USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
- (USB_DT_STRING << 8) + index, langid, buf, size, USB_CNTL_TIMEOUT);
+ int i;
+ int result;
+
+ for (i = 0; i < 3; ++i) {
+ /* some devices are flaky */
+ result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+ USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
+ (USB_DT_STRING << 8) + index, langid, buf, size,
+ USB_CNTL_TIMEOUT);
+
+ if (result > 0)
+ break;
+ }
+
+ return result;
+}
+
+
+static void usb_try_string_workarounds(unsigned char *buf, int *length)
+{
+ int newlength, oldlength = *length;
+
+ for (newlength = 2; newlength + 1 < oldlength; newlength += 2)
+ if (!isprint(buf[newlength]) || buf[newlength + 1])
+ break;
+
+ if (newlength > 2) {
+ buf[0] = newlength;
+ *length = newlength;
+ }
}
+
+static int usb_string_sub(struct usb_device *dev, unsigned int langid,
+ unsigned int index, unsigned char *buf)
+{
+ int rc;
+
+ /* Try to read the string descriptor by asking for the maximum
+ * possible number of bytes */
+ rc = usb_get_string(dev, langid, index, buf, 255);
+
+ /* If that failed try to read the descriptor length, then
+ * ask for just that many bytes */
+ if (rc < 2) {
+ rc = usb_get_string(dev, langid, index, buf, 2);
+ if (rc == 2)
+ rc = usb_get_string(dev, langid, index, buf, buf[0]);
+ }
+
+ if (rc >= 2) {
+ if (!buf[0] && !buf[1])
+ usb_try_string_workarounds(buf, &rc);
+
+ /* There might be extra junk at the end of the descriptor */
+ if (buf[0] < rc)
+ rc = buf[0];
+
+ rc = rc - (rc & 1); /* force a multiple of two */
+ }
+
+ if (rc < 2)
+ rc = -1;
+
+ return rc;
+}
+
+
/********************************************************************
* usb_string:
* Get string index and translate it to ascii.
/* get langid for strings if it's not yet known */
if (!dev->have_langid) {
- err = usb_get_string(dev, 0, 0, tbuf, 4);
+ err = usb_string_sub(dev, 0, 0, tbuf);
if (err < 0) {
USB_PRINTF("error getting string descriptor 0 (error=%x)\n",dev->status);
return -1;
dev->devnum, dev->string_langid);
}
}
- /* Just ask for a maximum length string and then take the length
- * that was returned. */
- err = usb_get_string(dev, dev->string_langid, index, tbuf, 4);
- if (err < 0)
- return err;
- u=tbuf[0];
- USB_PRINTF("Strn Len %d, index %d\n",u,index);
-
- if (u > USB_BUFSIZ) {
- USB_PRINTF("usb_string: failed to get string - too long: %d\n", u);
- return -1;
- }
- err = usb_get_string(dev, dev->string_langid, index, tbuf, u);
+ err = usb_string_sub(dev, dev->string_langid, index, tbuf);
if (err < 0)
return err;
+
size--; /* leave room for trailing NULL char in output buffer */
for (idx = 0, u = 2; u < err; u += 2) {
if (idx >= size)
/* We still haven't set the Address yet */
addr = dev->devnum;
dev->devnum = 0;
+
+#undef NEW_INIT_SEQ
+#ifdef NEW_INIT_SEQ
+ /* this is a Windows scheme of initialization sequence, with double
+ * reset of the device. Some equipment is said to work only with such
+ * init sequence; this patch is based on the work by Alan Stern:
+ * http://sourceforge.net/mailarchive/forum.php?thread_id=5729457&forum_id=5398
+ */
+ int j;
+ struct usb_device_descriptor *desc;
+ int port = -1;
+ struct usb_device *parent = dev->parent;
+ unsigned short portstatus;
+
+ /* send 64-byte GET-DEVICE-DESCRIPTOR request. Since the descriptor is
+ * only 18 bytes long, this will terminate with a short packet. But if
+ * the maxpacket size is 8 or 16 the device may be waiting to transmit
+ * some more. */
+
+ desc = (struct usb_device_descriptor *)tmpbuf;
+ desc->bMaxPacketSize0 = 0;
+ for (j = 0; j < 3; ++j) {
+ err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
+ if (err < 0) {
+ USB_PRINTF("usb_new_device: 64 byte descr\n");
+ break;
+ }
+ }
+ dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0;
+
+ /* find the port number we're at */
+ if (parent) {
+
+ for (j = 0; j < parent->maxchild; j++) {
+ if (parent->children[j] == dev) {
+ port = j;
+ break;
+ }
+ }
+ if (port < 0) {
+ printf("usb_new_device: cannot locate device's port..\n");
+ return 1;
+ }
+
+ /* reset the port for the second time */
+ err = hub_port_reset(dev->parent, port, &portstatus);
+ if (err < 0) {
+ printf("\n Couldn't reset port %i\n", port);
+ return 1;
+ }
+ }
+#else
+ /* and this is the old and known way of initializing devices */
err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8);
if (err < 8) {
printf("\n USB device not responding, giving up (status=%lX)\n",dev->status);
return 1;
}
+#endif
+
dev->epmaxpacketin [0] = dev->descriptor.bMaxPacketSize0;
dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0;
switch (dev->descriptor.bMaxPacketSize0) {
/* device 0 is always present (root hub, so let it analyze) */
dev=usb_alloc_new_device();
usb_new_device(dev);
- printf("%d USB Devices found\n",dev_index);
+ printf("%d USB Device(s) found\n",dev_index);
/* insert "driver" if possible */
#ifdef CONFIG_USB_KEYBOARD
drv_usb_kbd_init();
#define MAX_TRIES 5
-void usb_hub_port_connect_change(struct usb_device *dev, int port)
+static int hub_port_reset(struct usb_device *dev, int port,
+ unsigned short *portstat)
{
- struct usb_device *usb;
+ int tries;
struct usb_port_status portsts;
unsigned short portstatus, portchange;
- int tries;
- /* Check status */
- if (usb_get_port_status(dev, port + 1, &portsts)<0) {
- USB_HUB_PRINTF("get_port_status failed\n");
- return;
- }
-
- portstatus = swap_16(portsts.wPortStatus);
- portchange = swap_16(portsts.wPortChange);
- USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus, portchange,
- portstatus&(1<<USB_PORT_FEAT_LOWSPEED) ? "Low Speed" : "High Speed");
-
- /* Clear the connection change status */
- usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION);
-
- /* Disconnect any existing devices under this port */
- if (((!(portstatus & USB_PORT_STAT_CONNECTION)) &&
- (!(portstatus & USB_PORT_STAT_ENABLE)))|| (dev->children[port])) {
- USB_HUB_PRINTF("usb_disconnect(&hub->children[port]);\n");
- /* Return now if nothing is connected */
- if (!(portstatus & USB_PORT_STAT_CONNECTION))
- return;
- }
- wait_ms(200);
-
- /* Reset the port */
+ USB_HUB_PRINTF("hub_port_reset: resetting port %d...\n", port);
for(tries=0;tries<MAX_TRIES;tries++) {
usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET);
if (usb_get_port_status(dev, port + 1, &portsts)<0) {
USB_HUB_PRINTF("get_port_status failed status %lX\n",dev->status);
- return;
+ return -1;
}
portstatus = swap_16(portsts.wPortStatus);
portchange = swap_16(portsts.wPortChange);
(portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0);
if ((portchange & USB_PORT_STAT_C_CONNECTION) ||
!(portstatus & USB_PORT_STAT_CONNECTION))
- return;
+ return -1;
+
+ if (portstatus & USB_PORT_STAT_ENABLE) {
- if (portstatus & USB_PORT_STAT_ENABLE)
break;
+ }
wait_ms(200);
}
if (tries==MAX_TRIES) {
USB_HUB_PRINTF("Cannot enable port %i after %i retries, disabling port.\n", port+1, MAX_TRIES);
USB_HUB_PRINTF("Maybe the USB cable is bad?\n");
- return;
+ return -1;
}
usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_RESET);
+ *portstat = portstatus;
+ return 0;
+
+}
+
+
+void usb_hub_port_connect_change(struct usb_device *dev, int port)
+{
+ struct usb_device *usb;
+ struct usb_port_status portsts;
+ unsigned short portstatus, portchange;
+
+ /* Check status */
+ if (usb_get_port_status(dev, port + 1, &portsts)<0) {
+ USB_HUB_PRINTF("get_port_status failed\n");
+ return;
+ }
+
+ portstatus = swap_16(portsts.wPortStatus);
+ portchange = swap_16(portsts.wPortChange);
+ USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus, portchange,
+ portstatus&(1<<USB_PORT_FEAT_LOWSPEED) ? "Low Speed" : "High Speed");
+
+ /* Clear the connection change status */
+ usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION);
+
+ /* Disconnect any existing devices under this port */
+ if (((!(portstatus & USB_PORT_STAT_CONNECTION)) &&
+ (!(portstatus & USB_PORT_STAT_ENABLE)))|| (dev->children[port])) {
+ USB_HUB_PRINTF("usb_disconnect(&hub->children[port]);\n");
+ /* Return now if nothing is connected */
+ if (!(portstatus & USB_PORT_STAT_CONNECTION))
+ return;
+ }
+ wait_ms(200);
+
+ /* Reset the port */
+ if (hub_port_reset(dev, port, &portstatus) < 0) {
+ printf("cannot reset port %i!?\n", port + 1);
+ return;
+ }
+
wait_ms(200);
/* Allocate a new device struct for it */
/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
+ * Most of this source has been derived from the Linux USB
+ * project:
+ * (c) 1999-2002 Matthew Dharm (mdharm-usb@one-eyed-alien.net)
+ * (c) 2000 David L. Brown, Jr. (usb-storage@davidb.org)
+ * (c) 1999 Michael Gee (michael@linuxspecific.com)
+ * (c) 2000 Yggdrasil Computing, Inc.
+ *
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
*
* For BBB support (C) Copyright 2003
* Gary Jennejohn, DENX Software Engineering <gj@denx.de>
*
- * Most of this source has been derived from the Linux USB
- * project. BBB support based on /sys/dev/usb/umass.c from
+ * BBB support based on /sys/dev/usb/umass.c from
* FreeBSD.
*
* See file CREDITS for list of people who contributed to this
#define UMASS_BBB_CSW_SIZE 13
#define USB_MAX_STOR_DEV 5
-static int usb_max_devs; /* number of highest available usb device */
+static int usb_max_devs = 0; /* number of highest available usb device */
static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV];
}
/*********************************************************************************
- * (re)-scan the usb and reports device info
+ * show info on storage devices; 'usb start/init' must be invoked earlier
+ * as we only retrieve structures populated during devices initialization
+ */
+void usb_stor_info(void)
+{
+ int i;
+
+ if (usb_max_devs > 0)
+ for (i = 0; i < usb_max_devs; i++) {
+ printf (" Device %d: ", i);
+ dev_print(&usb_dev_desc[i]);
+ }
+ else
+ printf("No storage devices, perhaps not 'usb start'ed..?\n");
+}
+
+/*********************************************************************************
+ * scan the usb and reports device info
* to the user if mode = 1
* returns current device or -1 if no
*/
memset(usb_stor_buf, 0, sizeof(usb_stor_buf));
if(mode==1) {
- printf(" scanning bus for storage devices...\n");
+ printf(" scanning bus for storage devices... ");
}
usb_disable_asynch(1); /* asynch transfer not allowed */
usb_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
usb_dev_desc[i].block_read=usb_stor_read;
}
+
usb_max_devs=0;
for(i=0;i<USB_MAX_DEVICE;i++) {
dev=usb_get_dev_index(i); /* get device */
}
if(usb_storage_probe(dev,0,&usb_stor[usb_max_devs])) { /* ok, it is a storage devices */
/* get info and fill it in */
-
- if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs])) {
- if(mode==1) {
- printf (" Device %d: ", usb_max_devs);
- dev_print(&usb_dev_desc[usb_max_devs]);
- } /* if mode */
+ if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs]))
usb_max_devs++;
- } /* if get info ok */
} /* if storage device */
if(usb_max_devs==USB_MAX_STOR_DEV) {
printf("max USB Storage Device reached: %d stopping\n",usb_max_devs);
break;
}
} /* for */
+
usb_disable_asynch(0); /* asynch transfer allowed */
+ printf("%d Storage Device(s) found\n", usb_max_devs);
if(usb_max_devs>0)
return 0;
else
result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0),
US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT*5);
+
if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED))
{
USB_STOR_PRINTF("RESET:stall\n");
return -1;
}
+
/* long wait for reset */
wait_ms(150);
USB_STOR_PRINTF("BBB_reset result %d: status %X reset\n",result,us->pusb_dev->status);
retry = 0;
again:
USB_STOR_PRINTF("STATUS phase\n");
- result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE, &actlen, USB_CNTL_TIMEOUT*5);
+ result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE,
+ &actlen, USB_CNTL_TIMEOUT*5);
+
/* special handling of STALL in STATUS phase */
if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED)) {
USB_STOR_PRINTF("STATUS:stall\n");
static int usb_inquiry(ccb *srb,struct us_data *ss)
{
int retry,i;
- retry=3;
+ retry=5;
do {
memset(&srb->cmd[0],0,12);
srb->cmd[0]=SCSI_INQUIRY;
static int usb_test_unit_ready(ccb *srb,struct us_data *ss)
{
- int retries=10;
+ int retries = 10;
do {
memset(&srb->cmd[0],0,12);
static int usb_read_capacity(ccb *srb,struct us_data *ss)
{
int retry;
- retry=2; /* retries */
+ retry = 3; /* retries */
do {
memset(&srb->cmd[0],0,12);
srb->cmd[0]=SCSI_RD_CAPAC;
int protocol = 0;
int subclass = 0;
-
- memset(ss, 0, sizeof(struct us_data));
-
/* let's examine the device now */
iface = &dev->config.if_desc[ifnum];
return 0;
}
+ memset(ss, 0, sizeof(struct us_data));
+
/* At this point, we know we've got a live one */
USB_STOR_PRINTF("\n\nUSB Mass Storage device detected\n");
unsigned char perq,modi;
unsigned long cap[2];
unsigned long *capacity,*blksz;
- ccb *pccb=&usb_ccb;
-
- /* For some mysterious reason the 256MB flash disk of Ours Technology, Inc
- * doesn't survive this reset */
- if (dev->descriptor.idVendor != 0xea0 || dev->descriptor.idProduct != 0x6828)
+ ccb *pccb = &usb_ccb;
+
+ /* for some reasons a couple of devices would not survive this reset */
+ if (
+ /* Sony USM256E */
+ (dev->descriptor.idVendor == 0x054c &&
+ dev->descriptor.idProduct == 0x019e)
+
+ ||
+ /* USB007 Mini-USB2 Flash Drive */
+ (dev->descriptor.idVendor == 0x066f &&
+ dev->descriptor.idProduct == 0x2010)
+ )
+ USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n");
+ else
ss->transport_reset(ss);
- pccb->pdata=usb_stor_buf;
- dev_desc->target=dev->devnum;
- pccb->lun=dev_desc->lun;
+ pccb->pdata = usb_stor_buf;
+
+ dev_desc->target = dev->devnum;
+ pccb->lun = dev_desc->lun;
USB_STOR_PRINTF(" address %d\n",dev_desc->target);
if(usb_inquiry(pccb,ss))
return -1;
- perq=usb_stor_buf[0];
- modi=usb_stor_buf[1];
- if((perq & 0x1f)==0x1f) {
+
+ perq = usb_stor_buf[0];
+ modi = usb_stor_buf[1];
+ if((perq & 0x1f) == 0x1f) {
return 0; /* skip unknown devices */
}
- if((modi&0x80)==0x80) {/* drive is removable */
- dev_desc->removable=1;
+ if((modi&0x80) == 0x80) {/* drive is removable */
+ dev_desc->removable = 1;
}
memcpy(&dev_desc->vendor[0], &usb_stor_buf[8], 8);
memcpy(&dev_desc->product[0], &usb_stor_buf[16], 16);
memcpy(&dev_desc->revision[0], &usb_stor_buf[32], 4);
- dev_desc->vendor[8]=0;
- dev_desc->product[16]=0;
- dev_desc->revision[4]=0;
+ dev_desc->vendor[8] = 0;
+ dev_desc->product[16] = 0;
+ dev_desc->revision[4] = 0;
USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]);
if(usb_test_unit_ready(pccb,ss)) {
printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n",pccb->sense_buf[2],pccb->sense_buf[12],pccb->sense_buf[13]);
- if(dev_desc->removable==1) {
- dev_desc->type=perq;
+ if(dev_desc->removable == 1) {
+ dev_desc->type = perq;
return 1;
}
else
return 0;
}
- pccb->pdata=(unsigned char *)&cap[0];
+ pccb->pdata = (unsigned char *)&cap[0];
memset(pccb->pdata,0,8);
- if(usb_read_capacity(pccb,ss)!=0) {
+ if(usb_read_capacity(pccb,ss) != 0) {
printf("READ_CAP ERROR\n");
- cap[0]=2880;
- cap[1]=0x200;
+ cap[0] = 2880;
+ cap[1] = 0x200;
}
USB_STOR_PRINTF("Read Capacity returns: 0x%lx, 0x%lx\n",cap[0],cap[1]);
#if 0
(((unsigned long)(cap[1]) & (unsigned long)0xff000000UL) >> 24) ));
#endif
/* this assumes bigendian! */
- cap[0]+=1;
- capacity=&cap[0];
- blksz=&cap[1];
+ cap[0] += 1;
+ capacity = &cap[0];
+ blksz = &cap[1];
USB_STOR_PRINTF("Capacity = 0x%lx, blocksz = 0x%lx\n",*capacity,*blksz);
- dev_desc->lba=*capacity;
- dev_desc->blksz=*blksz;
- dev_desc->type=perq;
+ dev_desc->lba = *capacity;
+ dev_desc->blksz = *blksz;
+ dev_desc->type = perq;
USB_STOR_PRINTF(" address %d\n",dev_desc->target);
USB_STOR_PRINTF("partype: %d\n",dev_desc->part_type);
endif
endif
+ifeq ($(PCI_CLOCK),PCI_66M)
+CFLAGS := $(CFLAGS) -DPCI_66M
+endif
+
#########################################################################
export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \
if ((baudrate = gd->baudrate) <= 0)
baudrate = CONFIG_BAUDRATE;
/* MASTER_CLOCK/(16 * baudrate) */
- us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
+ us->US_BRGR = (AT91C_MASTER_CLOCK >> 4) / (unsigned)baudrate;
}
int serial_init (void)
int got_rhsc;
/* device which was disconnected */
struct usb_device *devgone;
+/* flag guarding URB transation */
+int urb_finished = 0;
/*-------------------------------------------------------------------------*/
return -1;
}
+ /* if we have an unfinished URB from previous transaction let's
+ * fail and scream as quickly as possible so as not to corrupt
+ * further communication */
+ if (!urb_finished) {
+ err("sohci_submit_job: URB NOT FINISHED");
+ return -1;
+ }
+ /* we're about to begin a new transaction here so mark the URB unfinished */
+ urb_finished = 0;
+
/* every endpoint has a ed, locate and fill it */
if (!(ed = ep_add_ed (dev, pipe))) {
err("sohci_submit_job: ENOMEM");
else
td->hwBE = 0;
td->hwNextTD = m32_swap (td_pt);
- td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
td_rev = td_list;
td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
}
+
return td_list;
}
stat = cc_to_error[cc];
}
+ /* see if this done list makes for all TD's of current URB,
+ * and mark the URB finished if so */
+ if (++(lurb_priv->td_cnt) == lurb_priv->length) {
+ if ((ed->state & (ED_OPER | ED_UNLINK)))
+ urb_finished = 1;
+ else
+ dbg("dl_done_list: strange.., ED state %x, ed->state\n");
+ } else
+ dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
+ lurb_priv->length);
+
if (ed->state != ED_NEW) {
edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
edTailP = m32_swap (ed->hwTailP);
for (;;) {
/* check whether the controller is done */
stat = hc_interrupt();
+
if (stat < 0) {
stat = USB_ST_CRC_ERR;
break;
}
- if (stat >= 0 && stat != 0xff) {
+
+ /* NOTE: since we are not interrupt driven in U-Boot and always
+ * handle only one URB at a time, we cannot assume the
+ * transaction finished on the first successful return from
+ * hc_interrupt().. unless the flag for current URB is set,
+ * meaning that all TD's to/from device got actually
+ * transferred and processed. If the current URB is not
+ * finished we need to re-iterate this loop so as
+ * hc_interrupt() gets called again as there needs to be some
+ * more TD's to process still */
+ if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
/* 0xff is returned for an SF-interrupt */
break;
}
+
if (--timeout) {
wait_ms(1);
+ if (!urb_finished)
+ dbg("\%");
+
} else {
err("CTL:TIMEOUT ");
+ dbg("submit_common_msg: TO status %x\n", stat);
stat = USB_ST_CRC_ERR;
+ urb_finished = 1;
break;
}
}
+
+#if 0
/* we got an Root Hub Status Change interrupt */
if (got_rhsc) {
#ifdef DEBUG
devgone = dev;
}
}
+#endif
dev->status = stat;
dev->act_len = transfer_len;
int ints;
int stat = -1;
- if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+ if ((ohci->hcca->done_head != 0) &&
+ !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+
ints = OHCI_INTR_WDH;
- } else {
- ints = readl (®s->intrstatus);
+
+ } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) {
+ ohci->disabled++;
+ err ("%s device removed!", ohci->slot_name);
+ return -1;
+
+ } else if ((ints &= readl (®s->intrenable)) == 0) {
+ dbg("hc_interrupt: returning..\n");
+ return 0xff;
}
/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
if (ints & OHCI_INTR_RHSC) {
got_rhsc = 1;
+ stat = 0xff;
}
if (ints & OHCI_INTR_UE) {
if (ints & OHCI_INTR_WDH) {
wait_ms(1);
+
writel (OHCI_INTR_WDH, ®s->intrdisable);
stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
writel (OHCI_INTR_WDH, ®s->intrenable);
wait_ms(1);
#endif
ohci_inited = 1;
+ urb_finished = 1;
+
return 0;
}
};
/* ED States */
-
#define ED_NEW 0x00
#define ED_UNLINK 0x01
#define ED_OPER 0x02
__u32 hwNextTD; /* Next TD Pointer */
__u32 hwBE; /* Memory Buffer End Pointer */
- __u16 hwPSW[MAXPSW];
__u8 unused;
__u8 index;
struct ed *ed;
mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
MIPSFLAGS=$(shell \
if [ "$v" -lt "14" ]; then \
- echo "-mcpu=4kc -EB -mabicalls"; \
+ echo "-mcpu=4kc"; \
else \
- echo "-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined -EB -mabicalls"; \
+ echo "-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined"; \
fi)
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS = -EL
+else
+ENDIANNESS = -EB
+endif
+
+MIPSFLAGS += $(ENDIANNESS) -mabicalls
+
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
#if defined(CONFIG_MGT5100)
baseclk = CFG_MPC5XXX_CLKIN / 32;
#elif defined(CONFIG_MPC5200)
- baseclk = gd->ipb_clk / 32;
+ baseclk = (gd->ipb_clk + 16) / 32;
#endif
/* set up UART divisor */
- div = baseclk / gd->baudrate;
+ div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
psc->ctur = div >> 8;
psc->ctlr = div & 0xff;
}
int got_rhsc;
/* device which was disconnected */
struct usb_device *devgone;
+/* flag guarding URB transation */
+int urb_finished = 0;
/*-------------------------------------------------------------------------*/
return -1;
}
+ /* if we have an unfinished URB from previous transaction let's
+ * fail and scream as quickly as possible so as not to corrupt
+ * further communication */
+ if (!urb_finished) {
+ err("sohci_submit_job: URB NOT FINISHED");
+ return -1;
+ }
+ /* we're about to begin a new transaction here so mark the URB unfinished */
+ urb_finished = 0;
+
/* every endpoint has a ed, locate and fill it */
if (!(ed = ep_add_ed (dev, pipe))) {
err("sohci_submit_job: ENOMEM");
else
td->hwBE = 0;
td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
- td->hwPSW [0] = ohci_cpu_to_le16 (((__u32)data & 0x0FFF) | 0xE000);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
/*-------------------------------------------------------------------------*/
/* prepare all TDs of a transfer */
-
static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
{
td_t *td_list_next = NULL;
ed_t *ed;
int cc = 0;
- int stat = 0xff;
+ int stat = 0;
/* urb_t *urb; */
urb_priv_t *lurb_priv;
__u32 tdINFO, edHeadP, edTailP;
&& (lurb_priv->state != URB_DEL)) {
dbg("ConditionCode %#x", cc);
stat = cc_to_error[cc];
+ urb_finished = 1;
}
}
stat = USB_ST_CRC_ERR;
break;
}
- if (stat >= 0 && stat < 0xff) {
+
+ /* NOTE: since we are not interrupt driven in U-Boot and always
+ * handle only one URB at a time, we cannot assume the
+ * transaction finished on the first successful return from
+ * hc_interrupt().. unless the flag for current URB is set,
+ * meaning that all TD's to/from device got actually
+ * transferred and processed. If the current URB is not
+ * finished we need to re-iterate this loop so as
+ * hc_interrupt() gets called again as there needs to be some
+ * more TD's to process still */
+ if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
/* 0xff is returned for an SF-interrupt */
break;
}
+
if (--timeout) {
wait_ms(1);
+ if (!urb_finished)
+ dbg("\%");
+
} else {
err("CTL:TIMEOUT ");
+ dbg("submit_common_msg: TO status %x\n", stat);
stat = USB_ST_CRC_ERR;
+ urb_finished = 1;
break;
}
}
+#if 0
/* we got an Root Hub Status Change interrupt */
if (got_rhsc) {
#ifdef DEBUG
devgone = dev;
}
}
+#endif
dev->status = stat;
dev->act_len = transfer_len;
int ints;
int stat = -1;
- if ((ohci->hcca->done_head != 0) && !(ohci_cpu_to_le32 (ohci->hcca->done_head) & 0x01)) {
- ints = OHCI_INTR_WDH;
- } else {
- ints = readl (®s->intrstatus);
+ if ((ohci->hcca->done_head != 0) &&
+ !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
+
+ ints = OHCI_INTR_WDH;
+
+ } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) {
+ ohci->disabled++;
+ err ("%s device removed!", ohci->slot_name);
+ return -1;
+
+ } else if ((ints &= readl (®s->intrenable)) == 0) {
+ dbg("hc_interrupt: returning..\n");
+ return 0xff;
}
/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
if (ints & OHCI_INTR_RHSC) {
got_rhsc = 1;
+ stat = 0xff;
}
if (ints & OHCI_INTR_UE) {
/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
if (ints & OHCI_INTR_SF) {
unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
+ wait_ms(1);
writel (OHCI_INTR_SF, ®s->intrdisable);
if (ohci->ed_rm_list[frame] != NULL)
writel (OHCI_INTR_SF, ®s->intrenable);
ohci_dump (&gohci, 1);
#endif
ohci_inited = 1;
+ urb_finished = 1;
+
return 0;
}
__u32 hwNextTD; /* Next TD Pointer */
__u32 hwBE; /* Memory Buffer End Pointer */
- __u16 hwPSW[MAXPSW];
__u8 unused;
__u8 index;
struct ed *ed;
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_8260 -ffixed-r2 -ffixed-r29 \
+PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
puts ("0.0 0K50M");
break;
case 0x0C10:
- puts ("1.0 0K50M");
+ puts ("1.0 1K50M");
break;
case 0x0D00:
puts ("0.0 0K50M");
break;
case 0x0D10:
- puts ("1.0 0K50M");
+ puts ("1.0 1K50M");
break;
default:
printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
}
+/* broadcast is not an error - we send them like that */
+#define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC)
+
void
eth_loopback_test (void)
{
ecp->rxeacc._f++;
}
- if (sc & BD_ENET_RX_STATS) {
+ if (sc & BD_ENET_RX_ERRS) {
ulong n;
/*
ecp->rxeacc.cl++;
bdp->cbd_sc &= \
- ~BD_ENET_RX_STATS;
+ ~BD_ENET_RX_ERRS;
}
else {
ushort datlen = bdp->cbd_datlen;
/* Set up the baud rate generator.
*/
#if defined(CONFIG_KGDB_USE_EXTC)
- m8260_cpm_extcbrg(KGDB_SMC_INDEX, speed,
+ m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
#else
- m8260_cpm_setbrg(KGDB_SMC_INDEX, speed);
+ m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
#endif
/* Make the first buffer the only buffer.
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o \
+ resetvec.o
+
+COBJS = traps.o \
+ cpu.o \
+ cpu_init.o \
+ speed.o \
+ interrupts.o \
+ pci.o \
+ i2c.o \
+ spd_sdram.o
+
+OBJS = $(COBJS)
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
+ -ffixed-r2 -ffixed-r29 -msoft-float
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+/*
+ * CPU specific code for the MPC83xx family.
+ *
+ * Derived from the MPC8260 and MPC85xx.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc83xx.h>
+#include <asm/processor.h>
+
+
+int checkcpu(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ ulong clock = gd->cpu_clk;
+ u32 pvr = get_pvr();
+ char buf[32];
+
+ if ((pvr & 0xFFFF0000) != PVR_83xx) {
+ puts("Not MPC83xx Family!!!\n");
+ return -1;
+ }
+
+ puts("CPU: MPC83xx, ");
+ switch(pvr) {
+ case PVR_8349_REV10:
+ break;
+ case PVR_8349_REV11:
+ break;
+ default:
+ puts("Rev: Unknown\n");
+ return -1; /* Not sure what this is */
+ }
+ printf("Rev: %02x at %s MHz\n",pvr & 0x0000FFFF, strmhz(buf, clock));
+ return 0;
+}
+
+
+void upmconfig (uint upm, uint *table, uint size)
+{
+ hang(); /* FIXME: upconfig() needed? */
+}
+
+
+int
+do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ ulong msr;
+#ifndef MPC83xx_RESET
+ ulong addr;
+#endif
+
+ volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+
+#ifdef MPC83xx_RESET
+ /* Interrupts and MMU off */
+ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+ msr &= ~( MSR_EE | MSR_IR | MSR_DR);
+ __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+
+ /* enable Reset Control Reg */
+ immap->reset.rpr = 0x52535445;
+
+ /* confirm Reset Control Reg is enabled */
+ while(!((immap->reset.rcer) & RCER_CRE));
+
+ printf("Resetting the board.");
+ printf("\n");
+
+ udelay(200);
+
+ /* perform reset, only one bit */
+ immap->reset.rcr = RCR_SWHR;
+
+#else /* ! MPC83xx_RESET */
+
+ immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
+
+ /* Interrupts and MMU off */
+ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+ msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
+ __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+
+ /*
+ * Trying to execute the next instruction at a non-existing address
+ * should cause a machine check, resulting in reset
+ */
+ addr = CFG_RESET_ADDRESS;
+
+ printf("resetting the board.");
+ printf("\n");
+ ((void (*)(void)) addr) ();
+#endif /* MPC83xx_RESET */
+
+ return 1;
+}
+
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ */
+
+unsigned long get_tbclk(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ ulong tbclk;
+
+ tbclk = (gd->bus_clk + 3L) / 4L;
+
+ return tbclk;
+}
+
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset (void)
+{
+ hang(); /* FIXME: implement watchdog_reset()? */
+}
+#endif /* CONFIG_WATCHDOG */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <ioports.h>
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f (volatile immap_t * im)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset ((void *) gd, 0, sizeof (gd_t));
+
+ /* RSR - Reset Status Register - clear all status (4.6.1.3) */
+ gd->reset_status = im->reset.rsr;
+ im->reset.rsr = ~(RSR_RES);
+
+ /*
+ * RMR - Reset Mode Register
+ * contains checkstop reset enable (4.6.1.4)
+ */
+ im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
+
+ /* LCRR - Clock Ratio Register (10.3.1.16) */
+ im->lbus.lcrr = CFG_LCRR;
+
+ /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
+ im->sysconf.spcr |= SPCR_TBEN;
+
+ /* System General Purpose Register */
+ im->sysconf.sicrh = SICRH_TSOBI1;
+ im->sysconf.sicrl = SICRL_LDP_A;
+
+ /*
+ * Memory Controller:
+ */
+
+ /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+ * addresses - these have to be modified later when FLASH size
+ * has been determined
+ */
+
+#if defined(CFG_BR0_PRELIM) \
+ && defined(CFG_OR0_PRELIM) \
+ && defined(CFG_LBLAWBAR0_PRELIM) \
+ && defined(CFG_LBLAWAR0_PRELIM)
+ im->lbus.bank[0].br = CFG_BR0_PRELIM;
+ im->lbus.bank[0].or = CFG_OR0_PRELIM;
+ im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
+ im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
+#else
+#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
+#endif
+
+#if defined(CFG_BR1_PRELIM) \
+ && defined(CFG_OR1_PRELIM) \
+ && defined(CFG_LBLAWBAR1_PRELIM) \
+ && defined(CFG_LBLAWAR1_PRELIM)
+ im->lbus.bank[1].br = CFG_BR1_PRELIM;
+ im->lbus.bank[1].or = CFG_OR1_PRELIM;
+ im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
+ im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
+#endif
+#if defined(CFG_BR2_PRELIM) \
+ && defined(CFG_OR2_PRELIM) \
+ && defined(CFG_LBLAWBAR2_PRELIM) \
+ && defined(CFG_LBLAWAR2_PRELIM)
+ im->lbus.bank[2].br = CFG_BR2_PRELIM;
+ im->lbus.bank[2].or = CFG_OR2_PRELIM;
+ im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
+ im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
+#endif
+#if defined(CFG_BR3_PRELIM) \
+ && defined(CFG_OR3_PRELIM) \
+ && defined(CFG_LBLAWBAR3_PRELIM) \
+ && defined(CFG_LBLAWAR3_PRELIM)
+ im->lbus.bank[3].br = CFG_BR3_PRELIM;
+ im->lbus.bank[3].or = CFG_OR3_PRELIM;
+ im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
+ im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
+#endif
+#if defined(CFG_BR4_PRELIM) \
+ && defined(CFG_OR4_PRELIM) \
+ && defined(CFG_LBLAWBAR4_PRELIM) \
+ && defined(CFG_LBLAWAR4_PRELIM)
+ im->lbus.bank[4].br = CFG_BR4_PRELIM;
+ im->lbus.bank[4].or = CFG_OR4_PRELIM;
+ im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
+ im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
+#endif
+#if defined(CFG_BR5_PRELIM) \
+ && defined(CFG_OR5_PRELIM) \
+ && defined(CFG_LBLAWBAR5_PRELIM) \
+ && defined(CFG_LBLAWAR5_PRELIM)
+ im->lbus.bank[5].br = CFG_BR5_PRELIM;
+ im->lbus.bank[5].or = CFG_OR5_PRELIM;
+ im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
+ im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
+#endif
+#if defined(CFG_BR6_PRELIM) \
+ && defined(CFG_OR6_PRELIM) \
+ && defined(CFG_LBLAWBAR6_PRELIM) \
+ && defined(CFG_LBLAWAR6_PRELIM)
+ im->lbus.bank[6].br = CFG_BR6_PRELIM;
+ im->lbus.bank[6].or = CFG_OR6_PRELIM;
+ im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
+ im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
+#endif
+#if defined(CFG_BR7_PRELIM) \
+ && defined(CFG_OR7_PRELIM) \
+ && defined(CFG_LBLAWBAR7_PRELIM) \
+ && defined(CFG_LBLAWAR7_PRELIM)
+ im->lbus.bank[7].br = CFG_BR7_PRELIM;
+ im->lbus.bank[7].or = CFG_OR7_PRELIM;
+ im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
+ im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
+#endif
+}
+
+
+/*
+ * Initialize higher level parts of CPU like time base and timers.
+ */
+
+int cpu_init_r (void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao <x.xiao@motorola.com>
+ * Adapted for Motorola 85xx chip.
+ *
+ * (C) Copyright 2003
+ * Gleb Natapov <gnatapov@mrv.com>
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
+ *
+ * Hardware I2C driver for MPC107 PCI bridge.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_HARD_I2C
+#include <i2c.h>
+#include <asm/i2c.h>
+
+#ifdef CONFIG_MPC8349ADS
+i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
+#endif
+
+void
+i2c_init(int speed, int slaveadd)
+{
+ /* stop I2C controller */
+ writeb(0x00 , &I2C->cr);
+
+ /* set clock */
+ writeb(0x3f, &I2C->fdr);
+
+ /* set default filter */
+ writeb(0x10,&I2C->dfsrr);
+
+ /* write slave address */
+ writeb(slaveadd, &I2C->adr);
+
+ /* clear status register */
+ writeb(0x00, &I2C->sr);
+
+ /* start I2C controller */
+ writeb(I2C_CR_MEN, &I2C->cr);
+}
+
+static __inline__ int
+i2c_wait4bus (void)
+{
+ ulong timeval = get_timer (0);
+ while (readb(&I2C->sr) & I2C_SR_MBB) {
+ if (get_timer (timeval) > I2C_TIMEOUT) {
+ return -1;
+ }
+ }
+ return 0;
+}
+
+static __inline__ int
+i2c_wait (int write)
+{
+ u32 csr;
+ ulong timeval = get_timer(0);
+ do {
+ csr = readb(&I2C->sr);
+
+ if (!(csr & I2C_SR_MIF))
+ continue;
+
+ writeb(0x0, &I2C->sr);
+
+ if (csr & I2C_SR_MAL) {
+ debug("i2c_wait: MAL\n");
+ return -1;
+ }
+
+ if (!(csr & I2C_SR_MCF)) {
+ debug("i2c_wait: unfinished\n");
+ return -1;
+ }
+
+ if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
+ debug("i2c_wait: No RXACK\n");
+ return -1;
+ }
+
+ return 0;
+ } while (get_timer (timeval) < I2C_TIMEOUT);
+ debug("i2c_wait: timed out\n");
+}
+
+static __inline__ int
+i2c_write_addr (u8 dev, u8 dir, int rsta)
+{
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
+ (rsta?I2C_CR_RSTA:0),
+ &I2C->cr);
+
+ writeb((dev << 1) | dir, &I2C->dr);
+
+ if (i2c_wait (I2C_WRITE) < 0)
+ return 0;
+ return 1;
+}
+
+static __inline__ int
+__i2c_write (u8 *data, int length)
+{
+ int i;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
+ &I2C->cr);
+
+ for (i=0; i < length; i++) {
+ writeb(data[i], &I2C->dr);
+
+ if (i2c_wait (I2C_WRITE) < 0)
+ break;
+ }
+ return i;
+}
+
+static __inline__ int
+__i2c_read (u8 *data, int length)
+{
+ int i;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA |
+ ((length == 1) ? I2C_CR_TXAK : 0),
+ &I2C->cr);
+
+ /* dummy read */
+ readb(&I2C->dr);
+
+ for (i=0; i < length; i++) {
+ if (i2c_wait (I2C_READ) < 0)
+ break;
+
+ /* Generate ack on last next to last byte */
+ if (i == length - 2)
+ writeb(I2C_CR_MEN | I2C_CR_MSTA |
+ I2C_CR_TXAK,
+ &I2C->cr);
+
+ /* Generate stop on last byte */
+ if (i == length - 1)
+ writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
+
+ data[i] = readb(&I2C->dr);
+ }
+ return i;
+}
+
+int
+i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus () < 0)
+ goto exit;
+
+ if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+ goto exit;
+
+ if (__i2c_write (&a[4 - alen], alen) != alen)
+ goto exit;
+
+ if (i2c_write_addr (dev, I2C_READ, 1) == 0)
+ goto exit;
+
+ i = __i2c_read (data, length);
+
+ exit:
+ writeb(I2C_CR_MEN, &I2C->cr);
+ return !(i == length);
+}
+
+int
+i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus () < 0)
+ goto exit;
+
+ if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+ goto exit;
+
+ if (__i2c_write (&a[4 - alen], alen) != alen)
+ goto exit;
+
+ i = __i2c_write (data, length);
+
+ exit:
+ writeb(I2C_CR_MEN, &I2C->cr);
+ return !(i == length);
+}
+
+int i2c_probe (uchar chip)
+{
+ int tmp;
+
+ /*
+ * Try to read the first location of the chip. The underlying
+ * driver doesn't appear to support sending just the chip address
+ * and looking for an <ACK> back.
+ */
+ udelay(10000);
+ return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+}
+
+uchar i2c_reg_read (uchar i2c_addr, uchar reg)
+{
+ char buf[1];
+
+ i2c_read (i2c_addr, reg, 1, buf, 1);
+
+ return (buf[0]);
+}
+
+void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
+{
+ i2c_write (i2c_addr, reg, 1, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc83xx.h>
+#include <asm/processor.h>
+
+struct irq_action {
+ interrupt_handler_t *handler;
+ void *arg;
+ ulong count;
+};
+
+int interrupt_init_cpu (unsigned *decrementer_count)
+{
+ return 0;
+}
+
+
+/*
+ * Handle external interrupts
+ */
+
+void external_interrupt (struct pt_regs *regs)
+{
+}
+
+
+/*
+ * Install and free an interrupt handler.
+ */
+
+void
+irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
+{
+}
+
+
+void irq_free_handler (int irq)
+{
+}
+
+
+void timer_interrupt_cpu (struct pt_regs *regs)
+{
+ /* nothing to do here */
+ return;
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
+
+/* ripped this out of ppc4xx/interrupts.c */
+
+/*
+ * irqinfo - print information about PCI devices
+ */
+
+void
+do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+/*
+ * PCI Configuration space access support for MPC85xx PCI Bridge
+ */
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_MPC8349ADS
+#include <asm/i2c.h>
+#endif
+
+#if defined(CONFIG_PCI)
+
+void
+pci_mpc83xx_init(volatile struct pci_controller *hose)
+{
+ volatile immap_t * immr;
+ volatile clk8349_t * clk;
+ volatile law8349_t * pci_law;
+ volatile pot8349_t * pci_pot;
+ volatile pcictrl8349_t * pci_ctrl;
+ volatile pciconf8349_t * pci_conf;
+
+ u8 val8,tmp8,ret;
+ u16 reg16,tmp16;
+ u32 val32,tmp32;
+
+ immr = (immap_t *)CFG_IMMRBAR;
+ clk = (clk8349_t *)&immr->clk;
+ pci_law = immr->sysconf.pcilaw;
+ pci_pot = immr->ios.pot;
+ pci_ctrl = immr->pci_ctrl;
+ pci_conf = immr->pci_conf;
+
+ /*
+ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+ */
+ val32 = clk->occr;
+ udelay(2000);
+ clk->occr = 0xff000000;
+ udelay(2000);
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
+
+ /* mapped to PCI1 IO space 0x0 to local 0xe2000000 */
+ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
+
+ pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
+
+ /* mapped to PCI2 IO space 0x0 to local 0xe3000000 */
+ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
+
+ pci_ctrl[1].pitar1 = 0x0;
+ pci_ctrl[1].pibar1 = 0x0;
+ pci_ctrl[1].piebar1 = 0x0;
+ pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
+ /*
+ * Assign PIB PMC slot to desired PCI bus
+ */
+#ifdef CONFIG_MPC8349ADS
+ mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
+ i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
+#endif
+ val8 = 0;
+ ret = i2c_write(0x23,0x6,1,&val8,1);
+ ret = i2c_write(0x23,0x7,1,&val8,1);
+ val8 = 0xff;
+ ret = i2c_write(0x23,0x2,1,&val8,1);
+ ret = i2c_write(0x23,0x3,1,&val8,1);
+
+ val8 = 0;
+ ret = i2c_write(0x26,0x6,1,&val8,1);
+ val8 = 0x34;
+ ret = i2c_write(0x26,0x7,1,&val8,1);
+#if defined(PCI_64BIT)
+ val8 = 0xf4; /* PMC2<->PCI1 64bit */
+#elif defined(PCI_ALL_PCI1)
+ val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
+#elif defined(PCI_ONE_PCI1)
+ val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
+#elif defined(PCI_TWO_PCI1)
+ val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
+#else
+ val8 = 0xf5;
+#endif
+ ret = i2c_write(0x26,0x2,1,&val8,1);
+ val8 = 0xff;
+ ret = i2c_write(0x26,0x3,1,&val8,1);
+ val8 = 0;
+ ret = i2c_write(0x27,0x6,1,&val8,1);
+ ret = i2c_write(0x27,0x7,1,&val8,1);
+ val8 = 0xff;
+ ret = i2c_write(0x27,0x2,1,&val8,1);
+ val8 = 0xef;
+ ret = i2c_write(0x27,0x3,1,&val8,1);
+ asm("eieio");
+
+ /*
+ * Release PCI RST Output signal
+ */
+ udelay(2000);
+ pci_ctrl[0].gcr = 1;
+#ifndef PCI_64BIT
+ pci_ctrl[1].gcr = 1;
+#endif
+ udelay(2000);
+
+ hose[0].first_busno = 0;
+ hose[0].last_busno = 0xff;
+
+ pci_set_region(hose[0].regions + 0,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ pci_set_region(hose[0].regions + 1,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose[0].region_count = 2;
+
+ pci_setup_indirect(&hose[0],
+ (CFG_IMMRBAR+0x8300),
+ (CFG_IMMRBAR+0x8304));
+#define PCI_CLASS_BRIDGE 0x06
+ reg16 = 0xff;
+ tmp32 = 0xffff;
+ pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
+
+ pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+#ifndef PCI_64BIT
+ hose[1].first_busno = 0;
+ hose[1].last_busno = 0xff;
+
+ pci_set_region(hose[1].regions + 0,
+ CFG_PCI2_MEM_BASE,
+ CFG_PCI2_MEM_PHYS,
+ CFG_PCI2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ pci_set_region(hose[1].regions + 1,
+ CFG_PCI2_IO_BASE,
+ CFG_PCI2_IO_PHYS,
+ CFG_PCI2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose[1].region_count = 2;
+
+ pci_setup_indirect(&hose[1],
+ (CFG_IMMRBAR+0x8380),
+ (CFG_IMMRBAR+0x8384));
+
+ pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
+ pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+#endif
+
+#if defined(PCI_64BIT)
+ printf("PCI1 64bit on PMC2\n");
+#elif defined(PCI_ALL_PCI1)
+ printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
+#elif defined(PCI_ONE_PCI1)
+ printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
+#else
+ printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
+#endif
+
+#if 1
+ /*
+ * Hose scan.
+ */
+ pci_register_hose(hose);
+ hose->last_busno = pci_hose_scan(hose);
+#endif
+}
+
+#endif /* CONFIG_PCI */
--- /dev/null
+ .section .resetvec,"ax"
+#ifndef FIXME
+#if 0
+ b _start_e500
+#endif
+#endif
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <spd.h>
+#include <asm/mmu.h>
+#include <spd_sdram.h>
+
+#ifdef CONFIG_SPD_EEPROM
+
+#if defined(CONFIG_DDR_ECC)
+extern void dma_init(void);
+extern uint dma_check(void);
+extern int dma_xfer(void *dest, uint count, void *src);
+#endif
+
+#ifndef CFG_READ_SPD
+#define CFG_READ_SPD i2c_read
+#endif
+
+/*
+ * Convert picoseconds into clock cycles (rounding up if needed).
+ */
+
+int
+picos_to_clk(int picos)
+{
+ int clks;
+
+ clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
+ if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+ clks++;
+ }
+
+ return clks;
+}
+
+unsigned int
+banksize(unsigned char row_dens)
+{
+ return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+}
+
+long int spd_sdram(int(read_spd)(uint addr))
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile ddr8349_t *ddr = &immap->ddr;
+ volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
+ spd_eeprom_t spd;
+ unsigned tmp, tmp1;
+ unsigned int memsize;
+ unsigned int law_size;
+ unsigned char caslat;
+ unsigned int trfc, trfc_clk, trfc_low;
+
+#warning Current spd_sdram does not fit its usage... adjust implementation or API...
+
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+
+ if (spd.nrows > 2) {
+ puts("DDR:Only two chip selects are supported on ADS.\n");
+ return 0;
+ }
+
+ if (spd.nrow_addr < 12
+ || spd.nrow_addr > 14
+ || spd.ncol_addr < 8
+ || spd.ncol_addr > 11) {
+ puts("DDR:Row or Col number unsupported.\n");
+ return 0;
+ }
+
+ ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
+ ddr->cs_config[2] = ( 1 << 31
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+ debug("\n");
+ debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
+ debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
+
+ if (spd.nrows == 2) {
+ ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
+ | ((banksize(spd.row_dens) >> 23) - 1) );
+ ddr->cs_config[3] = ( 1<<31
+ | (spd.nrow_addr-12) << 8
+ | (spd.ncol_addr-8) );
+ debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
+ debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
+ }
+
+ if (spd.mem_type != 0x07) {
+ puts("No DDR module found!\n");
+ return 0;
+ }
+
+ /*
+ * Figure out memory size in Megabytes.
+ */
+ memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
+
+ /*
+ * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
+ */
+ law_size = 19 + __ilog2(memsize);
+
+ /*
+ * Set up LAWBAR for all of DDR.
+ */
+ ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
+ debug("DDR:bar=0x%08x\n", ecm->bar);
+ debug("DDR:ar=0x%08x\n", ecm->ar);
+
+ /*
+ * find the largest CAS
+ */
+ if(spd.cas_lat & 0x40) {
+ caslat = 7;
+ } else if (spd.cas_lat & 0x20) {
+ caslat = 6;
+ } else if (spd.cas_lat & 0x10) {
+ caslat = 5;
+ } else if (spd.cas_lat & 0x08) {
+ caslat = 4;
+ } else if (spd.cas_lat & 0x04) {
+ caslat = 3;
+ } else if (spd.cas_lat & 0x02) {
+ caslat = 2;
+ } else if (spd.cas_lat & 0x01) {
+ caslat = 1;
+ } else {
+ puts("DDR:no valid CAS Latency information.\n");
+ return 0;
+ }
+
+ tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+ + (spd.clk_cycle & 0x0f));
+ debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
+
+ tmp1 = get_bus_freq(0) / 1000000;
+ if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
+ /* 90~230 range, treated as DDR 200 */
+ if (spd.clk_cycle3 == 0xa0)
+ caslat -= 2;
+ else if(spd.clk_cycle2 == 0xa0)
+ caslat--;
+ } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
+ /* 230-280 range, treated as DDR 266 */
+ if (spd.clk_cycle3 == 0x75)
+ caslat -= 2;
+ else if (spd.clk_cycle2 == 0x75)
+ caslat--;
+ } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
+ /* 280~350 range, treated as DDR 333 */
+ if (spd.clk_cycle3 == 0x60)
+ caslat -= 2;
+ else if (spd.clk_cycle2 == 0x60)
+ caslat--;
+ } else if (tmp1 < 90 || tmp1 >= 350) {
+ /* DDR rate out-of-range */
+ puts("DDR:platform frequency is not fit for DDR rate\n");
+ return 0;
+ }
+
+ /*
+ * note: caslat must also be programmed into ddr->sdram_mode
+ * register.
+ *
+ * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+ * use conservative value here.
+ */
+ trfc = spd.trfc * 1000; /* up to ps */
+ trfc_clk = picos_to_clk(trfc);
+ trfc_low = (trfc_clk - 8) & 0xf;
+
+ ddr->timing_cfg_1 =
+ (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
+ ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
+ ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
+ ((caslat & 0x07) << 16 ) |
+ (trfc_low << 12 ) |
+ ( 0x300 ) |
+ ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
+
+ ddr->timing_cfg_2 = 0x00000800;
+
+ debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
+ debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
+
+ /*
+ * Only DDR I is supported
+ * DDR I and II have different mode-register-set definition
+ */
+
+ /* burst length is always 4 */
+ switch(caslat) {
+ case 2:
+ ddr->sdram_mode = 0x52; /* 1.5 */
+ break;
+ case 3:
+ ddr->sdram_mode = 0x22; /* 2.0 */
+ break;
+ case 4:
+ ddr->sdram_mode = 0x62; /* 2.5 */
+ break;
+ case 5:
+ ddr->sdram_mode = 0x32; /* 3.0 */
+ break;
+ default:
+ puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
+ return 0;
+ }
+ debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
+
+ switch(spd.refresh) {
+ case 0x00:
+ case 0x80:
+ tmp = picos_to_clk(15625000);
+ break;
+ case 0x01:
+ case 0x81:
+ tmp = picos_to_clk(3900000);
+ break;
+ case 0x02:
+ case 0x82:
+ tmp = picos_to_clk(7800000);
+ break;
+ case 0x03:
+ case 0x83:
+ tmp = picos_to_clk(31300000);
+ break;
+ case 0x04:
+ case 0x84:
+ tmp = picos_to_clk(62500000);
+ break;
+ case 0x05:
+ case 0x85:
+ tmp = picos_to_clk(125000000);
+ break;
+ default:
+ tmp = 0x512;
+ break;
+ }
+
+ /*
+ * Set BSTOPRE to 0x100 for page mode
+ * If auto-charge is used, set BSTOPRE = 0
+ */
+ ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
+ debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
+
+ /*
+ * Is this an ECC DDR chip?
+ */
+#if defined(CONFIG_DDR_ECC)
+ if (spd.config == 0x02) {
+ ddr->err_disable = 0x0000000d;
+ ddr->err_sbe = 0x00ff0000;
+ }
+ debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
+ debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+ /*
+ * SS_EN=1,
+ * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
+ * clock cycle after address/command
+ */
+ ddr->sdram_clk_cntl = 0x82000000;
+
+ /*
+ * Figure out the settings for the sdram_cfg register. Build up
+ * the entire register in 'tmp' before writing since the write into
+ * the register will actually enable the memory controller, and all
+ * settings must be done before enabling.
+ *
+ * sdram_cfg[0] = 1 (ddr sdram logic enable)
+ * sdram_cfg[1] = 1 (self-refresh-enable)
+ * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+ */
+ tmp = 0xc2000000;
+
+ /*
+ * sdram_cfg[3] = RD_EN - registered DIMM enable
+ * A value of 0x26 indicates micron registered DIMMS (micron.com)
+ */
+ if (spd.mod_attr == 0x26) {
+ tmp |= 0x10000000;
+ }
+
+#if defined(CONFIG_DDR_ECC)
+ /*
+ * If the user wanted ECC (enabled via sdram_cfg[2])
+ */
+ if (spd.config == 0x02) {
+ tmp |= 0x20000000;
+ }
+#endif
+
+#if defined(CONFIG_DDR_2T_TIMING)
+ /*
+ * Enable 2T timing by setting sdram_cfg[16].
+ */
+ tmp |= SDRAM_CFG_2T_EN;
+#endif
+
+ ddr->sdram_cfg = tmp;
+ asm("sync;isync");
+ udelay(500);
+
+ debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
+
+ return memsize;/*in MBytes*/
+}
+#endif /* CONFIG_SPD_EEPROM */
+
+
+#if defined(CONFIG_DDR_ECC)
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+#ifndef FIXME
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+ dma_init();
+
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) {
+ ppcDcbz((unsigned long) p);
+ }
+ *p = (unsigned int)0xdeadbeef;
+ if (((unsigned int)p & 0x1c) == 0x1c) {
+ ppcDcbf((unsigned long) p);
+ }
+ }
+
+ /* 8K */
+ dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
+ /* 16K */
+ dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
+ /* 32K */
+ dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
+ /* 64K */
+ dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
+ /* 128k */
+ dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
+ /* 256k */
+ dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
+ /* 512k */
+ dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
+ /* 1M */
+ dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
+ /* 2M */
+ dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
+ /* 4M */
+ dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
+ }
+
+ /*
+ * Enable errors for ECC.
+ */
+ ddr->err_disable = 0x00000000;
+ asm("sync;isync");
+#endif
+}
+
+#endif /* CONFIG_DDR_ECC */
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <asm/processor.h>
+
+/* ----------------------------------------------------------------- */
+
+typedef enum {
+ _unk,
+ _off,
+ _byp,
+ _x8,
+ _x4,
+ _x2,
+ _x1,
+ _1x,
+ _1_5x,
+ _2x,
+ _2_5x,
+ _3x
+} mult_t;
+
+typedef struct {
+ mult_t core_csb_ratio;
+ mult_t vco_divider;
+} corecnf_t;
+
+corecnf_t corecnf_tab[] = {
+ { _byp, _byp}, /* 0x00 */
+ { _byp, _byp}, /* 0x01 */
+ { _byp, _byp}, /* 0x02 */
+ { _byp, _byp}, /* 0x03 */
+ { _byp, _byp}, /* 0x04 */
+ { _byp, _byp}, /* 0x05 */
+ { _byp, _byp}, /* 0x06 */
+ { _byp, _byp}, /* 0x07 */
+ { _1x, _x2}, /* 0x08 */
+ { _1x, _x4}, /* 0x09 */
+ { _1x, _x8}, /* 0x0A */
+ { _1x, _x8}, /* 0x0B */
+ {_1_5x, _x2}, /* 0x0C */
+ {_1_5x, _x4}, /* 0x0D */
+ {_1_5x, _x8}, /* 0x0E */
+ {_1_5x, _x8}, /* 0x0F */
+ { _2x, _x2}, /* 0x10 */
+ { _2x, _x4}, /* 0x11 */
+ { _2x, _x8}, /* 0x12 */
+ { _2x, _x8}, /* 0x13 */
+ {_2_5x, _x2}, /* 0x14 */
+ {_2_5x, _x4}, /* 0x15 */
+ {_2_5x, _x8}, /* 0x16 */
+ {_2_5x, _x8}, /* 0x17 */
+ { _3x, _x2}, /* 0x18 */
+ { _3x, _x4}, /* 0x19 */
+ { _3x, _x8}, /* 0x1A */
+ { _3x, _x8}, /* 0x1B */
+};
+
+/* ----------------------------------------------------------------- */
+
+/*
+ *
+ */
+int get_clocks (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+ u32 pci_sync_in;
+ u8 spmf;
+ u8 clkin_div;
+ u32 sccr;
+ u32 corecnf_tab_index;
+ u8 corepll;
+ u32 lcrr;
+
+ u32 csb_clk;
+ u32 tsec1_clk;
+ u32 tsec2_clk;
+ u32 core_clk;
+ u32 usbmph_clk;
+ u32 usbdr_clk;
+ u32 i2c_clk;
+ u32 enc_clk;
+ u32 lbiu_clk;
+ u32 lclk_clk;
+ u32 ddr_clk;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+#ifndef CFG_HRCW_HIGH
+# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
+#endif /* CFG_HCWD_HIGH */
+
+#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
+# ifndef CONFIG_83XX_CLKIN
+# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
+# endif /* CONFIG_83XX_CLKIN */
+# ifdef CONFIG_83XX_PCICLK
+# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
+# endif /* CONFIG_83XX_PCICLK */
+/* PCI Host Mode */
+ if (!(im->reset.rcwh & RCWH_PCIHOST)) {
+ /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
+ /* FIXME: findout if there is a way to issue some warning */
+ return -2;
+ }
+ if (im->clk.spmr & SPMR_CKID) {
+ pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
+ }
+ else {
+ pci_sync_in = CONFIG_83XX_CLKIN;
+ }
+#else
+# ifdef CONFIG_83XX_CLKIN
+# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
+# endif /* CONFIG_83XX_CLKIN */
+# ifndef CONFIG_83XX_PCICLK
+# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
+# endif /* CONFIG_83XX_PCICLK */
+/* PCI Agent Mode */
+ if (im->reset.rcwh & RCWH_PCIHOST) {
+ /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
+ return -3;
+ }
+ pci_sync_in = CONFIG_83XX_PCICLK;
+#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
+
+ /* we have up to date pci_sync_in */
+ spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
+ clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
+
+ if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
+ csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
+ }
+ else {
+ csb_clk = pci_sync_in * spmf * (1 + clkin_div);
+ }
+
+ sccr = im->clk.sccr;
+ switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
+ case 0:
+ tsec1_clk = 0;
+ break;
+ case 1:
+ tsec1_clk = csb_clk;
+ break;
+ case 2:
+ tsec1_clk = csb_clk / 2;
+ break;
+ case 3:
+ tsec1_clk = csb_clk / 3;
+ break;
+ default:
+ /* unkown SCCR_TSEC1CM value */
+ return -4;
+ }
+
+ switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
+ case 0:
+ tsec2_clk = 0;
+ break;
+ case 1:
+ tsec2_clk = csb_clk;
+ break;
+ case 2:
+ tsec2_clk = csb_clk / 2;
+ break;
+ case 3:
+ tsec2_clk = csb_clk / 3;
+ break;
+ default:
+ /* unkown SCCR_TSEC2CM value */
+ return -5;
+ }
+ i2c_clk = tsec2_clk;
+
+ switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
+ case 0:
+ enc_clk = 0;
+ break;
+ case 1:
+ enc_clk = csb_clk;
+ break;
+ case 2:
+ enc_clk = csb_clk / 2;
+ break;
+ case 3:
+ enc_clk = csb_clk / 3;
+ break;
+ default:
+ /* unkown SCCR_ENCCM value */
+ return -6;
+ }
+
+ switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
+ case 0:
+ usbmph_clk = 0;
+ break;
+ case 1:
+ usbmph_clk = csb_clk;
+ break;
+ case 2:
+ usbmph_clk = csb_clk / 2;
+ break;
+ case 3:
+ usbmph_clk = csb_clk / 3;
+ break;
+ default:
+ /* unkown SCCR_USBMPHCM value */
+ return -7;
+ }
+
+ switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
+ case 0:
+ usbdr_clk = 0;
+ break;
+ case 1:
+ usbdr_clk = csb_clk;
+ break;
+ case 2:
+ usbdr_clk = csb_clk / 2;
+ break;
+ case 3:
+ usbdr_clk = csb_clk / 3;
+ break;
+ default:
+ /* unkown SCCR_USBDRCM value */
+ return -8;
+ }
+
+ if (usbmph_clk != 0
+ && usbdr_clk != 0
+ && usbmph_clk != usbdr_clk ) {
+ /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
+ return -9;
+ }
+
+ lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
+ lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+ switch (lcrr) {
+ case 2:
+ case 4:
+ case 8:
+ lclk_clk = lbiu_clk / lcrr;
+ break;
+ default:
+ /* unknown lcrr */
+ return -10;
+ }
+
+ ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
+
+ corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
+ corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
+ if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
+ /* corecnf_tab_index is too high, possibly worng value */
+ return -11;
+ }
+ switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
+ case _byp:
+ case _x1:
+ case _1x:
+ core_clk = csb_clk;
+ break;
+ case _1_5x:
+ core_clk = (3 * csb_clk) / 2;
+ break;
+ case _2x:
+ core_clk = 2 * csb_clk;
+ break;
+ case _2_5x:
+ core_clk = ( 5 * csb_clk) / 2;
+ break;
+ case _3x:
+ core_clk = 3 * csb_clk;
+ break;
+ default:
+ /* unkown core to csb ratio */
+ return -12;
+ }
+
+ gd->csb_clk = csb_clk ;
+ gd->tsec1_clk = tsec1_clk ;
+ gd->tsec2_clk = tsec2_clk ;
+ gd->core_clk = core_clk ;
+ gd->usbmph_clk = usbmph_clk;
+ gd->usbdr_clk = usbdr_clk ;
+ gd->i2c_clk = i2c_clk ;
+ gd->enc_clk = enc_clk ;
+ gd->lbiu_clk = lbiu_clk ;
+ gd->lclk_clk = lclk_clk ;
+ gd->ddr_clk = ddr_clk ;
+
+ gd->cpu_clk = gd->core_clk;
+ gd->bus_clk = gd->lbiu_clk;
+ return 0;
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ return gd->csb_clk;
+}
+
+int print_clock_conf (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ printf("Clock configuration:\n");
+ printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
+ printf(" Core: %4d MHz\n",gd->core_clk/1000000);
+ printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
+ printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
+ printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
+ printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
+ printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
+ printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
+ printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
+ printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
+
+#if 0
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ ulong sccr, dfbrg;
+ ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
+ corecnf_t *cp;
+
+ sccr = immap->im_clkrst.car_sccr;
+ dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
+
+ scmr = immap->im_clkrst.car_scmr;
+ corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
+ busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
+ cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
+ plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
+ pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
+
+ cp = &corecnf_tab[corecnf];
+
+ puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
+
+ switch (cp->b2c_mult) {
+ case _byp:
+ puts ("BYPASS");
+ break;
+
+ case _off:
+ puts ("OFF");
+ break;
+
+ case _unk:
+ puts ("UNKNOWN");
+ break;
+
+ default:
+ printf ("%d%sx",
+ cp->b2c_mult / 2,
+ (cp->b2c_mult % 2) ? ".5" : "");
+ break;
+ }
+
+ printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
+ cp->vco_div, cp->freq_60x, cp->freq_core);
+
+ printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
+ "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
+ pllmf);
+
+ printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
+ gd->vco_out, gd->scc_clk, gd->brg_clk);
+
+ printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
+ gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
+
+ if (sccr & SCCR_PCI_MODE) {
+ uint pci_div;
+
+ pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+ ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+
+ printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
+ }
+ putc ('\n');
+#endif
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
+ */
+
+#include <config.h>
+#include <mpc83xx.h>
+#include <version.h>
+
+#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
+#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING "MPC83XX"
+#endif
+
+/* We don't want the MMU yet.
+ */
+#undef MSR_KERNEL
+
+/*
+ * Floating Point enable, Machine Check and Recoverable Interr.
+ */
+#ifdef DEBUG
+#define MSR_KERNEL (MSR_FP|MSR_RI)
+#else
+#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
+#endif
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+ START_GOT
+ GOT_ENTRY(_GOT2_TABLE_)
+ GOT_ENTRY(_FIXUP_TABLE_)
+
+ GOT_ENTRY(_start)
+ GOT_ENTRY(_start_of_vectors)
+ GOT_ENTRY(_end_of_vectors)
+ GOT_ENTRY(transfer_to_handler)
+
+ GOT_ENTRY(__init_end)
+ GOT_ENTRY(_end)
+ GOT_ENTRY(__bss_start)
+ END_GOT
+
+/*
+ * Version string - must be in data segment because MPC83xx uses the
+ * first 256 bytes for the Hard Reset Configuration Word table (see
+ * below). Similarly, can't have the U-Boot Magic Number as the first
+ * thing in the image - don't know how this will affect the image tools,
+ * but I guess I'll find out soon.
+ */
+ .data
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " ", CONFIG_IDENT_STRING, "\0"
+
+ .text
+#define _HRCW_TABLE_ENTRY(w) \
+ .fill 8,1,(((w)>>24)&0xff); \
+ .fill 8,1,(((w)>>16)&0xff); \
+ .fill 8,1,(((w)>> 8)&0xff); \
+ .fill 8,1,(((w) )&0xff)
+
+ _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
+ _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
+
+
+#ifndef CONFIG_DEFAULT_IMMR
+#error CONFIG_DEFAULT_IMMR must be defined
+#endif /* CFG_DEFAULT_IMMR */
+#ifndef CFG_IMMRBAR
+#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR
+#endif /* CFG_IMMRBAR */
+
+/*
+ * After configuration, a system reset exception is executed using the
+ * vector at offset 0x100 relative to the base set by MSR[IP]. If
+ * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
+ * base address is 0xfff00000. In the case of a Power On Reset or Hard
+ * Reset, the value of MSR[IP] is determined by the CIP field in the
+ * HRCW.
+ *
+ * Other bits in the HRCW set up the Base Address and Port Size in BR0.
+ * This determines the location of the boot ROM (flash or EPROM) in the
+ * processor's address space at boot time. As long as the HRCW is set up
+ * so that we eventually end up executing the code below when the
+ * processor executes the reset exception, the actual values used should
+ * not matter.
+ *
+ * Once we have got here, the address mask in OR0 is cleared so that the
+ * bottom 32K of the boot ROM is effectively repeated all throughout the
+ * processor's address space, after which we can jump to the absolute
+ * address at which the boot ROM was linked at compile time, and proceed
+ * to initialise the memory controller without worrying if the rug will
+ * be pulled out from under us, so to speak (it will be fine as long as
+ * we configure BR0 with the same boot ROM link address).
+ */
+ . = EXC_OFF_SYS_RESET
+
+ .globl _start
+_start: /* time t 0 */
+ li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
+ nop
+ b boot_cold
+
+ . = EXC_OFF_SYS_RESET + 0x10
+
+ .globl _start_warm
+_start_warm:
+ li r21, BOOTFLAG_WARM /* Software reboot */
+ b boot_warm
+
+
+boot_cold: /* time t 3 */
+ lis r4, CONFIG_DEFAULT_IMMR@h
+ nop
+boot_warm: /* time t 5 */
+ mfmsr r5 /* save msr contents */
+ lis r3, CFG_IMMRBAR@h
+ ori r3, r3, CFG_IMMRBAR@l
+ stw r3, IMMRBAR(r4)
+
+ /* Initialise the E300 processor core */
+ /*------------------------------------------*/
+
+ bl init_e300_core
+
+#ifndef CFG_RAMBOOT
+
+ /* Inflate flash location so it appears everywhere, calculate */
+ /* the absolute address in final location of the FLASH, jump */
+ /* there and deflate the flash size back to minimal size */
+ /*------------------------------------------------------------*/
+ bl map_flash_by_law1
+ lis r4, (CFG_MONITOR_BASE)@h
+ ori r4, r4, (CFG_MONITOR_BASE)@l
+ addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
+ mtlr r5
+ blr
+in_flash:
+#if 1 /* Remapping flash with LAW0. */
+ bl remap_flash_by_law0
+#endif
+#endif /* CFG_RAMBOOT */
+
+ bl setup_stack_in_data_cache_on_r1
+
+ /* let the C-code set up the rest */
+ /* */
+ /* Be careful to keep code relocatable & stack humble */
+ /*------------------------------------------------------*/
+
+ GET_GOT /* initialize GOT access */
+
+ /* r3: IMMR */
+ lis r3, CFG_IMMRBAR@h
+ /* run low-level CPU init code (in Flash)*/
+ bl cpu_init_f
+
+ /* r3: BOOTFLAG */
+ mr r3, r21
+ /* run 1st part of board init code (in Flash)*/
+ bl board_init_f
+
+/*
+ * Vector Table
+ */
+
+ .globl _start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+ STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+ STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+ STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+#ifndef FIXME
+ STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+#endif
+
+/* Alignment exception. */
+ . = 0x600
+Alignment:
+ EXCEPTION_PROLOG
+ mfspr r4,DAR
+ stw r4,_DAR(r21)
+ mfspr r5,DSISR
+ stw r5,_DSISR(r21)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_Alignment:
+ .long AlignmentException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+/* Program check exception */
+ . = 0x700
+ProgramCheck:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_ProgramCheck:
+ .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+ STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+ /* I guess we could implement decrementer, and may have
+ * to someday for timekeeping.
+ */
+ STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+
+ STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+ STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+ STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+ STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+ STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+ STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+ STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
+#ifdef DEBUG
+ . = 0x1300
+ /*
+ * This exception occurs when the program counter matches the
+ * Instruction Address Breakpoint Register (IABR).
+ *
+ * I want the cpu to halt if this occurs so I can hunt around
+ * with the debugger and look at things.
+ *
+ * When DEBUG is defined, both machine check enable (in the MSR)
+ * and checkstop reset enable (in the reset mode register) are
+ * turned off and so a checkstop condition will result in the cpu
+ * halting.
+ *
+ * I force the cpu into a checkstop condition by putting an illegal
+ * instruction here (at least this is the theory).
+ *
+ * well - that didnt work, so just do an infinite loop!
+ */
+1: b 1b
+#else
+ STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
+#endif
+ STD_EXCEPTION(0x1400, SMI, UnknownException)
+
+ STD_EXCEPTION(0x1500, Trap_15, UnknownException)
+ STD_EXCEPTION(0x1600, Trap_16, UnknownException)
+ STD_EXCEPTION(0x1700, Trap_17, UnknownException)
+ STD_EXCEPTION(0x1800, Trap_18, UnknownException)
+ STD_EXCEPTION(0x1900, Trap_19, UnknownException)
+ STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
+ STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
+ STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
+ STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
+ STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
+ STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
+ STD_EXCEPTION(0x2000, Trap_20, UnknownException)
+ STD_EXCEPTION(0x2100, Trap_21, UnknownException)
+ STD_EXCEPTION(0x2200, Trap_22, UnknownException)
+ STD_EXCEPTION(0x2300, Trap_23, UnknownException)
+ STD_EXCEPTION(0x2400, Trap_24, UnknownException)
+ STD_EXCEPTION(0x2500, Trap_25, UnknownException)
+ STD_EXCEPTION(0x2600, Trap_26, UnknownException)
+ STD_EXCEPTION(0x2700, Trap_27, UnknownException)
+ STD_EXCEPTION(0x2800, Trap_28, UnknownException)
+ STD_EXCEPTION(0x2900, Trap_29, UnknownException)
+ STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
+ STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
+ STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
+ STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
+ STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
+ STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
+
+
+ .globl _end_of_vectors
+_end_of_vectors:
+
+ . = 0x3000
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+ .globl transfer_to_handler
+transfer_to_handler:
+ stw r22,_NIP(r21)
+ lis r22,MSR_POW@h
+ andc r23,r23,r22
+ stw r23,_MSR(r21)
+ SAVE_GPR(7, r21)
+ SAVE_4GPRS(8, r21)
+ SAVE_8GPRS(12, r21)
+ SAVE_8GPRS(24, r21)
+ mflr r23
+ andi. r24,r23,0x3f00 /* get vector offset */
+ stw r24,TRAP(r21)
+ li r22,0
+ stw r22,RESULT(r21)
+ lwz r24,0(r23) /* virtual address of handler */
+ lwz r23,4(r23) /* where to go when done */
+ mtspr SRR0,r24
+ mtspr SRR1,r20
+ mtlr r23
+ SYNC
+ rfi /* jump to handler, enable MMU */
+
+int_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SRR0,r2
+ mtspr SRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfi
+
+/*
+ * This code initialises the E300 processor core
+ * (conforms to PowerPC 603e spec)
+ * Note: expects original MSR contents to be in r5.
+ */
+ .globl init_e300_core
+init_e300_core: /* time t 10 */
+ /* Initialize machine status; enable machine check interrupt */
+ /*-----------------------------------------------------------*/
+
+ li r3, MSR_KERNEL /* Set ME and RI flags */
+ rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
+#ifdef DEBUG
+ rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
+#endif
+ SYNC /* Some chip revs need this... */
+ mtmsr r3
+ SYNC
+ mtspr SRR1, r3 /* Make SRR1 match MSR */
+
+
+ lis r3, CFG_IMMRBAR@h
+#if defined(CONFIG_WATCHDOG)
+ /* Initialise the Wathcdog values and reset it (if req) */
+ /*------------------------------------------------------*/
+ lis r4, CFG_WATCHDOG_VALUE
+ ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+ stw r4, SWCRR(r3)
+
+ /* and reset it */
+
+ li r4, 0x556C
+ sth r4, SWSRR@l(r3)
+ li r4, 0xAA39
+ sth r4, SWSRR@l(r3)
+#else
+ /* Disable Wathcdog */
+ /*-------------------*/
+ xor r4, r4, r4
+ stw r4, SWCRR(r3)
+#endif /* CONFIG_WATCHDOG */
+
+ /* Initialize the Hardware Implementation-dependent Registers */
+ /* HID0 also contains cache control */
+ /*------------------------------------------------------*/
+
+ lis r3, CFG_HID0_INIT@h
+ ori r3, r3, CFG_HID0_INIT@l
+ SYNC
+ mtspr HID0, r3
+
+ lis r3, CFG_HID0_FINAL@h
+ ori r3, r3, CFG_HID0_FINAL@l
+ SYNC
+ mtspr HID0, r3
+
+ lis r3, CFG_HID2@h
+ ori r3, r3, CFG_HID2@l
+ SYNC
+ mtspr HID2, r3
+
+ /* clear all BAT's */
+ /*----------------------------------*/
+
+ xor r0, r0, r0
+ mtspr DBAT0U, r0
+ mtspr DBAT0L, r0
+ mtspr DBAT1U, r0
+ mtspr DBAT1L, r0
+ mtspr DBAT2U, r0
+ mtspr DBAT2L, r0
+ mtspr DBAT3U, r0
+ mtspr DBAT3L, r0
+ mtspr IBAT0U, r0
+ mtspr IBAT0L, r0
+ mtspr IBAT1U, r0
+ mtspr IBAT1L, r0
+ mtspr IBAT2U, r0
+ mtspr IBAT2L, r0
+ mtspr IBAT3U, r0
+ mtspr IBAT3L, r0
+ SYNC
+
+ /* invalidate all tlb's
+ *
+ * From the 603e User Manual: "The 603e provides the ability to
+ * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
+ * instruction invalidates the TLB entry indexed by the EA, and
+ * operates on both the instruction and data TLBs simultaneously
+ * invalidating four TLB entries (both sets in each TLB). The
+ * index corresponds to bits 15-19 of the EA. To invalidate all
+ * entries within both TLBs, 32 tlbie instructions should be
+ * issued, incrementing this field by one each time."
+ *
+ * "Note that the tlbia instruction is not implemented on the
+ * 603e."
+ *
+ * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
+ * incrementing by 0x1000 each time. The code below is sort of
+ * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
+ *
+ */
+
+ li r3, 32
+ mtctr r3
+ li r3, 0
+1: tlbie r3
+ addi r3, r3, 0x1000
+ bdnz 1b
+ SYNC
+
+ /* Done! */
+ /*------------------------------*/
+ blr
+
+/* Cache functions.
+ *
+ * Note: requires that all cache bits in
+ * HID0 are in the low half word.
+ */
+ .globl icache_enable
+icache_enable:
+ mfspr r3, HID0
+ ori r3, r3, HID0_ICE
+ lis r4, 0
+ ori r4, r4, HID0_ILOCK
+ andc r3, r3, r4
+ ori r4, r3, HID0_ICFI
+ isync
+ mtspr HID0, r4 /* sets enable and invalidate, clears lock */
+ isync
+ mtspr HID0, r3 /* clears invalidate */
+ blr
+
+ .globl icache_disable
+icache_disable:
+ mfspr r3, HID0
+ lis r4, 0
+ ori r4, r4, HID0_ICE|HID0_ILOCK
+ andc r3, r3, r4
+ ori r4, r3, HID0_ICFI
+ isync
+ mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
+ isync
+ mtspr HID0, r3 /* clears invalidate */
+ blr
+
+ .globl icache_status
+icache_status:
+ mfspr r3, HID0
+ rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31
+ blr
+
+ .globl dcache_enable
+dcache_enable:
+ mfspr r3, HID0
+ ori r3, r3, HID0_ENABLE_DATA_CACHE
+ lis r4, 0
+ ori r4, r4, HID0_LOCK_DATA_CACHE
+ andc r3, r3, r4
+ ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE
+ sync
+ mtspr HID0, r4 /* sets enable and invalidate, clears lock */
+ sync
+ mtspr HID0, r3 /* clears invalidate */
+ blr
+
+ .globl dcache_disable
+dcache_disable:
+ mfspr r3, HID0
+ lis r4, 0
+ ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE
+ andc r3, r3, r4
+ ori r4, r3, HID0_INVALIDATE_DATA_CACHE
+ sync
+ mtspr HID0, r4 /* sets invalidate, clears enable and lock */
+ sync
+ mtspr HID0, r3 /* clears invalidate */
+ blr
+
+ .globl dcache_status
+dcache_status:
+ mfspr r3, HID0
+ rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31
+ blr
+
+ .globl get_pvr
+get_pvr:
+ mfspr r3, PVR
+ blr
+
+/*-------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+ mr r1, r3 /* Set new stack pointer */
+ mr r9, r4 /* Save copy of Global Data pointer */
+ mr r10, r5 /* Save copy of Destination Address */
+
+ mr r3, r5 /* Destination Address */
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r5, GOT(__init_end)
+ sub r5, r5, r4
+ li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
+ * + Destination Address
+ *
+ * Offset:
+ */
+ sub r15, r10, r4
+
+ /* First our own GOT */
+ add r14, r14, r15
+ /* then the one used by the C code */
+ add r30, r30, r15
+
+ /*
+ * Now relocate code
+ */
+
+ cmplw cr1,r3,r4
+ addi r0,r5,3
+ srwi. r0,r0,2
+ beq cr1,4f /* In place copy is not necessary */
+ beq 7f /* Protect against 0 count */
+ mtctr r0
+ bge cr1,2f
+ la r8,-4(r4)
+ la r7,-4(r3)
+
+ /* copy */
+1: lwzu r0,4(r8)
+ stwu r0,4(r7)
+ bdnz 1b
+
+ addi r0,r5,3
+ srwi. r0,r0,2
+ mtctr r0
+ la r8,-4(r4)
+ la r7,-4(r3)
+
+ /* and compare */
+20: lwzu r20,4(r8)
+ lwzu r21,4(r7)
+ xor. r22, r20, r21
+ bne 30f
+ bdnz 20b
+ b 4f
+
+ /* compare failed */
+30: li r3, 0
+ blr
+
+2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
+ add r8,r4,r0
+ add r7,r3,r0
+3: lwzu r0,-4(r8)
+ stwu r0,-4(r7)
+ bdnz 3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:
+ bl un_setup_stack_in_data_cache
+ mr r7, r3
+ mr r8, r4
+ bl dcache_disable
+ mr r3, r7
+ mr r4, r8
+
+ cmpwi r6,0
+ add r5,r3,r5
+ beq 7f /* Always flush prefetch queue in any case */
+ subi r0,r6,1
+ andc r3,r3,r0
+ mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/
+ rlwinm r7,r7,HID0_DCE_SHIFT,31,31
+ cmpwi r7,0
+ beq 9f
+ mr r4,r3
+5: dcbst 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 5b
+ sync /* Wait for all dcbst to complete on bus */
+9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
+ rlwinm r7,r7,HID0_DCE_SHIFT,31,31
+ cmpwi r7,0
+ beq 7f
+ mr r4,r3
+6: icbi 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 6b
+7: sync /* Wait for all icbi to complete on bus */
+ isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+ mtlr r0
+ blr
+
+in_ram:
+
+ /*
+ * Relocation Function, r14 point to got2+0x8000
+ *
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
+ */
+ li r0,__got2_entries@sectoff@l
+ la r3,GOT(_GOT2_TABLE_)
+ lwz r11,GOT(_GOT2_TABLE_)
+ mtctr r0
+ sub r11,r3,r11
+ addi r3,r3,-4
+1: lwzu r0,4(r3)
+ add r0,r0,r11
+ stw r0,0(r3)
+ bdnz 1b
+
+ /*
+ * Now adjust the fixups and the pointers to the fixups
+ * in case we need to move ourselves again.
+ */
+2: li r0,__fixup_entries@sectoff@l
+ lwz r3,GOT(_FIXUP_TABLE_)
+ cmpwi r0,0
+ mtctr r0
+ addi r3,r3,-4
+ beq 4f
+3: lwzu r4,4(r3)
+ lwzux r0,r4,r11
+ add r0,r0,r11
+ stw r10,0(r3)
+ stw r0,0(r4)
+ bdnz 3b
+4:
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ lwz r3,GOT(__bss_start)
+#if defined(CONFIG_HYMOD)
+ /*
+ * For HYMOD - the environment is the very last item in flash.
+ * The real .bss stops just before environment starts, so only
+ * clear up to that point.
+ *
+ * taken from mods for FADS board
+ */
+ lwz r4,GOT(environment)
+#else
+ lwz r4,GOT(_end)
+#endif
+
+ cmplw 0, r3, r4
+ beq 6f
+
+ li r0, 0
+5:
+ stw r0, 0(r3)
+ addi r3, r3, 4
+ cmplw 0, r3, r4
+ bne 5b
+6:
+
+ mr r3, r9 /* Global Data pointer */
+ mr r4, r10 /* Destination Address */
+ bl board_init_r
+
+ /*
+ * Copy exception vector code to low memory
+ *
+ * r3: dest_addr
+ * r7: source address, r8: end address, r9: target address
+ */
+ .globl trap_init
+trap_init:
+ lwz r7, GOT(_start)
+ lwz r8, GOT(_end_of_vectors)
+
+ li r9, 0x100 /* reset vector always at 0x100 */
+
+ cmplw 0, r7, r8
+ bgelr /* return if r7>=r8 - just in case */
+
+ mflr r4 /* save link register */
+1:
+ lwz r0, 0(r7)
+ stw r0, 0(r9)
+ addi r7, r7, 4
+ addi r9, r9, 4
+ cmplw 0, r7, r8
+ bne 1b
+
+ /*
+ * relocate `hdlr' and `int_return' entries
+ */
+ li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+ li r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 2b
+
+ li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+ li r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 3b
+
+ li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+ li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 4b
+
+ mfmsr r3 /* now that the vectors have */
+ lis r7, MSR_IP@h /* relocated into low memory */
+ ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
+ andc r3, r3, r7 /* (if it was on) */
+ SYNC /* Some chip revs need this... */
+ mtmsr r3
+ SYNC
+
+ mtlr r4 /* restore link register */
+ blr
+
+ /*
+ * Function: relocate entries for one exception vector
+ */
+trap_reloc:
+ lwz r0, 0(r7) /* hdlr ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 0(r7)
+
+ lwz r0, 4(r7) /* int_return ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 4(r7)
+
+ blr
+
+#ifdef CFG_INIT_RAM_LOCK
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+ /* invalidate the INIT_RAM section */
+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+ li r2,512
+ mtctr r2
+1: icbi r0, r3
+ dcbi r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+ sync /* Wait for all icbi to complete on bus */
+ isync
+ blr
+#endif
+
+map_flash_by_law1:
+ /* When booting from ROM (Flash or EPROM), clear the */
+ /* Address Mask in OR0 so ROM appears everywhere */
+ /*----------------------------------------------------*/
+ lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */
+ lwz r4, OR0@l(r3)
+ li r5, 0x7fff /* r5 <= 0x00007FFFF */
+ and r4, r4, r5
+ stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
+
+ /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
+ * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
+ * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
+ * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
+ * 0xFF800. From the hard resetting to here, the processor fetched and
+ * executed the instructions one by one. There is not absolutely
+ * jumping happened. Laterly, the u-boot code has to do an absolutely
+ * jumping to tell the CPU instruction fetching component what the
+ * u-boot TEXT base address is. Because the TEXT base resides in the
+ * boot ROM memory space, to garantee the code can run smoothly after
+ * that jumping, we must map in the entire boot ROM by Local Access
+ * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
+ * address for boot ROM, such as 0xFE000000. In this case, the default
+ * LBIU Local Access Widow 0 will not cover this memory space. So, we
+ * need another window to map in it.
+ */
+ lis r4, (CFG_FLASH_BASE)@h
+ ori r4, r4, (CFG_FLASH_BASE)@l
+ stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
+ lis r4, (0x80000016)@h
+ ori r4, r4, (0x80000016)@l
+ stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
+ blr
+
+ /* Though all the LBIU Local Access Windows and LBC Banks will be
+ * initialized in the C code, we'd better configure boot ROM's
+ * window 0 and bank 0 correctly at here.
+ */
+remap_flash_by_law0:
+ /* Initialize the BR0 with the boot ROM starting address. */
+ lwz r4, BR0(r3)
+ li r5, 0x7FFF
+ and r4, r4, r5
+ lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
+ ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
+ or r5, r5, r4
+ stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+
+ lwz r4, OR0(r3)
+ lis r5, 0xFF80 /* 8M */
+ or r4, r4, r5
+ stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */
+
+ lis r4, (CFG_FLASH_BASE)@h
+ ori r4, r4, (CFG_FLASH_BASE)@l
+ stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
+
+ lis r4, (0x80000016)@h
+ ori r4, r4, (0x80000016)@l
+ stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */
+
+ xor r4, r4, r4
+ stw r4, LBLAWBAR1(r3)
+ stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
+ blr
+
+setup_stack_in_data_cache_on_r1:
+ lis r3, (CFG_IMMRBAR)@h
+
+ /* setup D-BAT for the D-Cache (with out real memory backup) */
+
+ lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
+ mtspr DBAT0U, r4
+ ori r4, r4, 0x0002
+ mtspr DBAT0L, r4
+ isync
+
+#if 0
+ /* Enable MMU */
+ mfmsr r4
+ ori r4, r4, (MSR_DR | MSR_IR)@l
+ mtmsr r4
+#endif
+
+ /* Enable and invalidate data cache. */
+ mfspr r4, HID0
+ mr r5, r4
+ ori r4, r4, HID0_DCE | HID0_DCI
+ ori r5, r5, HID0_DCE
+ sync
+ mtspr HID0, r4
+ mtspr HID0, r5
+ sync
+
+ /* Allocate Initial RAM in data cache.*/
+ li r0, 0
+ lis r4, (CFG_INIT_RAM_ADDR)@h
+ ori r4, r4, (CFG_INIT_RAM_ADDR)@l
+ li r5, 128*8 /* 128*8*32=32Kb */
+ mtctr r5
+1:
+ dcbz r0, r4
+ addi r4, r4, 32
+ bdnz 1b
+ isync
+
+ /* Lock all the D-cache, basically leaving the reset of the program without dcache */
+ mfspr r4, HID0
+ ori r4, r4, (HID0_DLOCK)@l
+ sync
+ mtspr HID0 , r4
+
+ /* setup the stack pointer in r1 */
+ lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+ li r0, 0 /* Make room for stack frame header and */
+
+ stwu r0, -4(r1) /* clear final stack frame so that */
+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+
+ blr
+
+un_setup_stack_in_data_cache:
+ blr
+ mr r14, r4
+ mr r15, r5
+
+
+ lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
+ mtspr DBAT0U, r4
+ ori r4, r4, 0x0002
+ mtspr DBAT0L, r4
+ isync
+
+ /* un lock all the D-cache */
+ mfspr r4, HID0
+ lis r5, (~(HID0_DLOCK))@h
+ ori r5, r5, (~(HID0_DLOCK))@l
+ and r4, r4, r5
+ sync
+ mtspr HID0 , r4
+
+ /* Re - Allocate Initial RAM in data cache.*/
+ li r0, 0
+ lis r4, (CFG_INIT_RAM_ADDR)@h
+ ori r4, r4, (CFG_INIT_RAM_ADDR)@l
+ li r5, 128*8 /* 128*8*32=32Kb */
+ mtctr r5
+1:
+ dcbz r0, r4
+ addi r4, r4, 32
+ bdnz 1b
+ isync
+
+ mflr r16
+ bl dcache_disable
+ mtlr r16
+
+ blr
+
+#if 0
+#define GREEN_LIGHT 0x2B0D4046
+#define RED_LIGHT 0x250D4046
+#define LIB_CNT 0x4FFF
+
+/*
+ * Lib Light
+ */
+
+ .globl liblight
+liblight:
+ lis r3, CFG_IMMRBAR@h
+ ori r3, r3, CFG_IMMRBAR@l
+ li r4, 0x3002
+ mtmsr r4
+ xor r4, r4, r4
+ mtspr HID0, r4
+ mtspr HID2, r4
+ lis r4, 0xF8000000@h
+ ori r4, r4, 0xF8000000@l
+ stw r4, LBLAWBAR1(r3)
+ lis r4, 0x8000000E@h
+ ori r4, r4, 0x8000000E@l
+ stw r4, LBLAWAR1(r3)
+ lis r4, 0xF8000801@h
+ ori r4, r4, 0xF8000801@l
+ stw r4, BR1(r3)
+ lis r4, 0xFFFFE8f0@h
+ ori r4, r4, 0xFFFFE8f0@l
+ stw r4, OR1(r3)
+
+ lis r4, 0xF8000000@h
+ ori r4, r4, 0xF8000000@l
+ lis r5, GREEN_LIGHT@h
+ ori r5, r5, GREEN_LIGHT@l
+ lis r6, RED_LIGHT@h
+ ori r6, r6, RED_LIGHT@l
+ lis r7, LIB_CNT@h
+ ori r7, r7, LIB_CNT@l
+
+1:
+ stw r5, 0(r4)
+ mtctr r7
+2: bdnz 2b
+ stw r6, 0(r4)
+ mtctr r7
+3: bdnz 3b
+ b 1b
+
+#endif
--- /dev/null
+/*
+ * linux/arch/ppc/kernel/traps.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ *
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ * Initial file creating (porting from 85XX & 8260)
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware
+ * exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mpc8349_pci.h>
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern unsigned long search_exception_table(unsigned long);
+
+#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+
+/*
+ * Trap & Exception support
+ */
+
+void
+print_backtrace(unsigned long *sp)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int cnt = 0;
+ unsigned long i;
+
+ puts ("Call backtrace: ");
+ while (sp) {
+ if ((uint)sp > END_OF_MEM)
+ break;
+
+ i = sp[1];
+ if (cnt++ % 7 == 0)
+ putc ('\n');
+ printf("%08lX ", i);
+ if (cnt > 32) break;
+ sp = (unsigned long *)*sp;
+ }
+ putc ('\n');
+}
+
+void show_regs(struct pt_regs * regs)
+{
+ int i;
+
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+ regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+ printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+ regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+ regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+ regs->msr&MSR_IR ? 1 : 0,
+ regs->msr&MSR_DR ? 1 : 0);
+
+ putc ('\n');
+ for (i = 0; i < 32; i++) {
+ if ((i % 8) == 0) {
+ printf("GPR%02d: ", i);
+ }
+
+ printf("%08lX ", regs->gpr[i]);
+ if ((i % 8) == 7) {
+ putc ('\n');
+ }
+ }
+}
+
+
+void
+_exception(int signr, struct pt_regs *regs)
+{
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+}
+
+#ifdef CONFIG_PCI
+void dump_pci (void)
+{
+/*
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ printf ("PCI: err status %x err mask %x err ctrl %x\n",
+ le32_to_cpu (immap->im_pci.pci_esr),
+ le32_to_cpu (immap->im_pci.pci_emr),
+ le32_to_cpu (immap->im_pci.pci_ecr));
+ printf (" error address %x error data %x ctrl %x\n",
+ le32_to_cpu (immap->im_pci.pci_eacr),
+ le32_to_cpu (immap->im_pci.pci_edcr),
+ le32_to_cpu (immap->im_pci.pci_eccr));
+*/
+}
+#endif
+
+void
+MachineCheckException(struct pt_regs *regs)
+{
+ unsigned long fixup;
+
+ /* Probing PCI using config cycles cause this exception
+ * when a device is not present. Catch it and return to
+ * the PCI exception handler.
+ */
+#ifdef CONFIG_PCI
+#if 0
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#ifdef DEBUG
+ dump_pci();
+#endif
+ /* clear the error in the error status register */
+ if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
+ immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP);
+ return;
+ }
+#endif
+#endif /* CONFIG_PCI */
+ if ((fixup = search_exception_table(regs->nip)) != 0) {
+ regs->nip = fixup;
+ return;
+ }
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ puts ("Machine check in kernel mode.\n"
+ "Caused by (from msr): ");
+ printf("regs %p ",regs);
+ switch( regs->msr & 0x000F0000) {
+ case (0x80000000>>12):
+ puts ("Machine check signal - probably due to mm fault\n"
+ "with mmu off\n");
+ break;
+ case (0x80000000>>13):
+ puts ("Transfer error ack signal\n");
+ break;
+ case (0x80000000>>14):
+ puts ("Data parity signal\n");
+ break;
+ case (0x80000000>>15):
+ puts ("Address parity signal\n");
+ break;
+ default:
+ puts ("Unknown values in msr\n");
+ }
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+#ifdef CONFIG_PCI
+ dump_pci();
+#endif
+ panic("machine check");
+}
+
+void
+AlignmentException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Alignment Exception");
+}
+
+void
+ProgramCheckException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Program Check Exception");
+}
+
+void
+SoftEmuException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Software Emulation Exception");
+}
+
+
+void
+UnknownException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ regs->nip, regs->msr, regs->trap);
+ _exception(0, regs);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+void
+DebugException(struct pt_regs *regs)
+{
+ printf("Debugger trap at @ %lx\n", regs->nip );
+ show_regs(regs);
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+ do_bedbug_breakpoint( regs );
+#endif
+}
+
+/* Probe an address by reading. If not present, return -1, otherwise
+ * return 0.
+ */
+int
+addr_probe(uint *addr)
+{
+#if 0
+ int retval;
+
+ __asm__ __volatile__( \
+ "1: lwz %0,0(%1)\n" \
+ " eieio\n" \
+ " li %0,0\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: li %0,-1\n" \
+ " b 2b\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .align 2\n" \
+ " .long 1b,3b\n" \
+ ".text" \
+ : "=r" (retval) : "r"(addr));
+
+ return (retval);
+#endif
+ return 0;
+}
LIB = lib$(CPU).a
START = start.o resetvec.o
-COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tsec.o \
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o
OBJS = $(COBJS)
#include <common.h>
#include <asm/cpm_85xx.h>
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
/*
* because we have stack and init data in dual port ram
* we must reduce the size
#endif /* CONFIG_POST */
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
uint pvr, svr;
+ uint fam;
uint ver;
uint major, minor;
case SVR_8560:
puts("8560");
break;
+ case SVR_8548:
+ puts("8548");
+ break;
+ case SVR_8548_E:
+ puts("8548_E");
+ break;
default:
puts("Unknown");
break;
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
+ fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
- switch (ver) {
- case PVR_VER(PVR_85xx):
+ switch (fam) {
+ case PVR_FAM(PVR_85xx):
puts("E500");
break;
default:
get_sys_info(&sysinfo);
- puts("Clocks Configuration:\n");
+ puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+#ifdef CONFIG_MPC8548
+ /*
+ * Yes, the entire PQ38 family use the same
+ * bit-representation for twice the clock divider values.
+ */
+ clkdiv *= 2;
+#endif
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);
} else {
#include <ioports.h>
#include <asm/io.h>
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_CPM2
static void config_8560_ioports (volatile immap_t * immr)
{
int portnum;
memset ((void *) gd, 0, sizeof (gd_t));
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_CPM2
config_8560_ioports(immap);
#endif
memctl->br7 = CFG_BR7_PRELIM;
#endif
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
m8560_cpm_reset();
#endif
}
+
/*
- * We initialize L2 as cache here.
+ * Initialize L2 as cache.
+ *
+ * The newer 8548, etc, parts have twice as much cache, but
+ * use the same bit-encoding as the older 8555, etc, parts.
+ *
+ * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
*/
-int cpu_init_r (void)
+
+int cpu_init_r(void)
{
#if defined(CONFIG_L2_CACHE)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
- volatile uint temp;
+ volatile uint cache_ctl;
+ uint svr, ver;
+
+ svr = get_svr();
+ ver = SVR_VER(svr);
+
+ asm("msync;isync");
+ cache_ctl = l2cache->l2ctl;
+
+ switch (cache_ctl & 0x30000000) {
+ case 0x20000000:
+ if (ver == SVR_8548 || ver == SVR_8548_E) {
+ printf ("L2 cache 512KB:");
+ } else {
+ printf ("L2 cache 256KB:");
+ }
+ break;
+ case 0x00000000:
+ case 0x10000000:
+ case 0x30000000:
+ default:
+ printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
+ return -1;
+ }
asm("msync;isync");
l2cache->l2ctl = 0x68000000; /* invalidate */
- temp = l2cache->l2ctl;
+ cache_ctl = l2cache->l2ctl;
asm("msync;isync");
+
l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
- temp = l2cache->l2ctl;
+ cache_ctl = l2cache->l2ctl;
asm("msync;isync");
- printf("L2: 256 kB enabled\n");
+ printf(" enabled\n");
#else
- printf("L2: disabled.\n");
+ printf("L2 cache: disabled\n");
#endif
return 0;
#include <config.h>
#include <net.h>
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
#include <common.h>
#include <asm/cpm_85xx.h>
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
#if defined(CONFIG_CONS_ON_SCC)
#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
#endif /* CONFIG_CONS_ON_SCC */
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
#include <spd.h>
#include <asm/mmu.h>
-#if defined(CONFIG_DDR_ECC)
-extern void dma_init (void);
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void dma_init(void);
extern uint dma_check(void);
-extern int dma_xfer (void *dest, uint count, void *src);
+extern int dma_xfer(void *dest, uint count, void *src);
#endif
#ifdef CONFIG_SPD_EEPROM
#define CFG_READ_SPD i2c_read
#endif
+static unsigned int setup_laws_and_tlbs(unsigned int memsize);
+
+
/*
* Convert picoseconds into clock cycles (rounding up if needed).
*/
return clks;
}
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Study these table from Byte 31 of JEDEC SPD Spec.
+ *
+ * DDR I DDR II
+ * Bit Size Size
+ * --- ----- ------
+ * 7 high 512MB 512MB
+ * 6 256MB 256MB
+ * 5 128MB 128MB
+ * 4 64MB 16GB
+ * 3 32MB 8GB
+ * 2 16MB 4GB
+ * 1 2GB 2GB
+ * 0 low 1GB 1GB
+ *
+ * Reorder Table to be linear by stripping the bottom
+ * 2 or 5 bits off and shifting them up to the top.
+ */
+
+unsigned int
+compute_banksize(unsigned int mem_type, unsigned char row_dens)
+{
+ unsigned int bsize;
+
+ if (mem_type == SPD_MEMTYPE_DDR) {
+ /* Bottom 2 bits up to the top. */
+ bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+ debug("DDR: DDR I rank density = 0x%08x\n", bsize);
+ } else {
+ /* Bottom 5 bits up to the top. */
+ bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
+ debug("DDR: DDR II rank density = 0x%08x\n", bsize);
+ }
+ return bsize;
+}
+
+
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II. No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+
unsigned int
-banksize(unsigned char row_dens)
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
{
- return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+ /*
+ * Table look up the lower nibble, allow DDR I & II.
+ */
+ unsigned int tenths_ps[16] = {
+ 0,
+ 100,
+ 200,
+ 300,
+ 400,
+ 500,
+ 600,
+ 700,
+ 800,
+ 900,
+ 250,
+ 330, /* FIXME: Is 333 better/valid? */
+ 660, /* FIXME: Is 667 better/valid? */
+ 750,
+ 0, /* undefined */
+ 0 /* undefined */
+ };
+
+ unsigned int whole_ns = (spd_val & 0xF0) >> 4;
+ unsigned int tenth_ns = spd_val & 0x0F;
+ unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
+
+ return ps;
}
+
long int
spd_sdram(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
spd_eeprom_t spd;
- unsigned tmp, tmp1;
+ unsigned int n_ranks;
+ unsigned int rank_density;
+ unsigned int odt_rd_cfg, odt_wr_cfg;
+ unsigned int odt_cfg, mode_odt_enable;
+ unsigned int dqs_cfg;
+ unsigned char twr_clk, twtr_clk, twr_auto_clk;
+ unsigned int tCKmin_ps, tCKmax_ps;
+ unsigned int max_data_rate, effective_data_rate;
+ unsigned int busfreq;
+ unsigned sdram_cfg;
unsigned int memsize;
- unsigned int tlb_size;
- unsigned int law_size;
- unsigned char caslat;
- unsigned int ram_tlb_index;
- unsigned int ram_tlb_address;
+ unsigned char caslat, caslat_ctrl;
+ unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+ unsigned int trcd_clk;
+ unsigned int trtp_clk;
+ unsigned char cke_min_clk;
+ unsigned char add_lat;
+ unsigned char wr_lat;
+ unsigned char wr_data_delay;
+ unsigned char four_act;
+ unsigned char cpo;
+ unsigned char burst_len;
+ unsigned int mode_caslat;
+ unsigned char sdram_type;
+ unsigned char d_init;
- CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+ /*
+ * Read SPD information.
+ */
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
- if (spd.nrows > 2) {
- puts("DDR:Only two chip selects are supported on ADS.\n");
+ /*
+ * Check for supported memory module types.
+ */
+ if (spd.mem_type != SPD_MEMTYPE_DDR &&
+ spd.mem_type != SPD_MEMTYPE_DDR2) {
+ printf("Unable to locate DDR I or DDR II module.\n"
+ " Fundamental memory type is 0x%0x\n",
+ spd.mem_type);
return 0;
}
- if (spd.nrow_addr < 12
- || spd.nrow_addr > 14
- || spd.ncol_addr < 8
- || spd.ncol_addr > 11) {
- puts("DDR:Row or Col number unsupported.\n");
+ /*
+ * These test gloss over DDR I and II differences in interpretation
+ * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
+ * are not supported on DDR I; and not encoded on DDR II.
+ *
+ * Also note that the 8548 controller can support:
+ * 12 <= nrow <= 16
+ * and
+ * 8 <= ncol <= 11 (still, for DDR)
+ * 6 <= ncol <= 9 (for FCRAM)
+ */
+ if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+ printf("DDR: Unsupported number of Row Addr lines: %d.\n",
+ spd.nrow_addr);
+ return 0;
+ }
+ if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+ printf("DDR: Unsupported number of Column Addr lines: %d.\n",
+ spd.ncol_addr);
return 0;
}
- ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1;
- ddr->cs0_config = ( 1 << 31
- | (spd.nrow_addr - 12) << 8
- | (spd.ncol_addr - 8) );
- debug("\n");
- debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
- debug("cs0_config = 0x%08x\n",ddr->cs0_config);
-
- if (spd.nrows == 2) {
- ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8)
- | ((banksize(spd.row_dens) >> 23) - 1) );
- ddr->cs1_config = ( 1<<31
- | (spd.nrow_addr-12) << 8
- | (spd.ncol_addr-8) );
- debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
- debug("cs1_config = 0x%08x\n",ddr->cs1_config);
+ /*
+ * Determine the number of physical banks controlled by
+ * different Chip Select signals. This is not quite the
+ * same as the number of DIMM modules on the board. Feh.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ n_ranks = spd.nrows;
+ } else {
+ n_ranks = (spd.nrows & 0x7) + 1;
}
- if (spd.mem_type != 0x07) {
- puts("No DDR module found!\n");
+ debug("DDR: number of ranks = %d\n", n_ranks);
+
+ if (n_ranks > 2) {
+ printf("DDR: Only 2 chip selects are supported: %d\n",
+ n_ranks);
return 0;
}
/*
- * Figure out memory size in Megabytes.
+ * Adjust DDR II IO voltage biasing. It just makes it work.
*/
- memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ gur->ddrioovcr = (0
+ | 0x80000000 /* Enable */
+ | 0x10000000 /* VSEL to 1.8V */
+ );
+ }
/*
- * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
+ * Determine the size of each Rank in bytes.
*/
- law_size = 19 + __ilog2(memsize);
+ rank_density = compute_banksize(spd.mem_type, spd.row_dens);
+
/*
- * Determine size of each TLB1 entry.
+ * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
*/
- switch (memsize) {
- case 16:
- case 32:
- tlb_size = BOOKE_PAGESZ_16M;
- break;
- case 64:
- case 128:
- tlb_size = BOOKE_PAGESZ_64M;
- break;
- case 256:
- case 512:
- case 1024:
- case 2048:
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- default:
- puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n");
- return 0;
- break;
- }
+ ddr->cs0_bnds = (rank_density >> 24) - 1;
/*
- * Configure DDR TLB1 entries.
- * Starting at TLB1 8, use no more than 8 TLB1 entries.
+ * ODT configuration recommendation from DDR Controller Chapter.
*/
- ram_tlb_index = 8;
- ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
- while (ram_tlb_address < (memsize * 1024 * 1024)
- && ram_tlb_index < 16) {
- mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
- mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
- mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 0, 0, 0));
- mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
- asm volatile("isync;msync;tlbwe;isync");
+ odt_rd_cfg = 0; /* Never assert ODT */
+ odt_wr_cfg = 0; /* Never assert ODT */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
+#if 0
+ /* FIXME: How to determine the number of dimm modules? */
+ if (n_dimm_modules == 2) {
+ odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */
+ }
+#endif
+ }
- debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
- debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
- debug("DDR:MAS2=0x%08x\n",
- TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 0, 0, 0));
- debug("DDR:MAS3=0x%08x\n",
- TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+ ddr->cs0_config = ( 1 << 31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+ debug("\n");
+ debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
+ debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
- ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
- ram_tlb_index++;
+ if (n_ranks == 2) {
+ /*
+ * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
+ */
+ ddr->cs1_bnds = ( (rank_density >> 8)
+ | ((rank_density >> (24 - 1)) - 1) );
+ ddr->cs1_config = ( 1<<31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+ debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
+ debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
}
+
/*
- * Set up LAWBAR for all of DDR.
+ * Find the largest CAS by locating the highest 1 bit
+ * in the spd.cas_lat field. Translate it to a DDR
+ * controller field value:
+ *
+ * CAS Lat DDR I DDR II Ctrl
+ * Clocks SPD Bit SPD Bit Value
+ * ------- ------- ------- -----
+ * 1.0 0 0001
+ * 1.5 1 0010
+ * 2.0 2 2 0011
+ * 2.5 3 0100
+ * 3.0 4 3 0101
+ * 3.5 5 0110
+ * 4.0 4 0111
+ * 4.5 1000
+ * 5.0 5 1001
*/
- ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
- ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
- debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1);
- debug("DDR:LARAR1=0x%08x\n", ecm->lawar1);
-
- /*
- * find the largest CAS
- */
- if(spd.cas_lat & 0x40) {
- caslat = 7;
- } else if (spd.cas_lat & 0x20) {
- caslat = 6;
- } else if (spd.cas_lat & 0x10) {
- caslat = 5;
- } else if (spd.cas_lat & 0x08) {
- caslat = 4;
- } else if (spd.cas_lat & 0x04) {
- caslat = 3;
- } else if (spd.cas_lat & 0x02) {
- caslat = 2;
- } else if (spd.cas_lat & 0x01) {
- caslat = 1;
- } else {
- puts("DDR:no valid CAS Latency information.\n");
+ caslat = __ilog2(spd.cas_lat);
+ if ((spd.mem_type == SPD_MEMTYPE_DDR)
+ && (caslat > 5)) {
+ printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+ return 0;
+
+ } else if (spd.mem_type == SPD_MEMTYPE_DDR2
+ && (caslat < 2 || caslat > 5)) {
+ printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+ spd.cas_lat);
return 0;
}
+ debug("DDR: caslat SPD bit is %d\n", caslat);
+
+ /*
+ * Calculate the Maximum Data Rate based on the Minimum Cycle time.
+ * The SPD clk_cycle field (tCKmin) is measured in tenths of
+ * nanoseconds and represented as BCD.
+ */
+ tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
+ debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
+
+ /*
+ * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
+ */
+ max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
+ debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
+
- tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
- + (spd.clk_cycle & 0x0f));
- debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
+ /*
+ * Adjust the CAS Latency to allow for bus speeds that
+ * are slower than the DDR module.
+ */
+ busfreq = get_bus_freq(0) / 1000000; /* MHz */
- tmp1 = get_bus_freq(0) / 1000000;
- if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
- /* 90~230 range, treated as DDR 200 */
- if (spd.clk_cycle3 == 0xa0)
+ effective_data_rate = max_data_rate;
+ if (busfreq < 90) {
+ /* DDR rate out-of-range */
+ puts("DDR: platform frequency is not fit for DDR rate\n");
+ return 0;
+
+ } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
+ /*
+ * busfreq 90~230 range, treated as DDR 200.
+ */
+ effective_data_rate = 200;
+ if (spd.clk_cycle3 == 0xa0) /* 10 ns */
caslat -= 2;
- else if(spd.clk_cycle2 == 0xa0)
+ else if (spd.clk_cycle2 == 0xa0)
caslat--;
- } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
- /* 230-280 range, treated as DDR 266 */
- if (spd.clk_cycle3 == 0x75)
+
+ } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
+ /*
+ * busfreq 230~280 range, treated as DDR 266.
+ */
+ effective_data_rate = 266;
+ if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
caslat -= 2;
else if (spd.clk_cycle2 == 0x75)
caslat--;
- } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
- /* 280~350 range, treated as DDR 333 */
- if (spd.clk_cycle3 == 0x60)
+
+ } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
+ /*
+ * busfreq 280~350 range, treated as DDR 333.
+ */
+ effective_data_rate = 333;
+ if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
caslat -= 2;
else if (spd.clk_cycle2 == 0x60)
caslat--;
- } else if (tmp1 < 90 || tmp1 >= 350) {
- /* DDR rate out-of-range */
- puts("DDR:platform frequency is not fit for DDR rate\n");
+
+ } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
+ /*
+ * busfreq 350~460 range, treated as DDR 400.
+ */
+ effective_data_rate = 400;
+ if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
+ caslat -= 2;
+ else if (spd.clk_cycle2 == 0x50)
+ caslat--;
+
+ } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
+ /*
+ * busfreq 460~560 range, treated as DDR 533.
+ */
+ effective_data_rate = 533;
+ if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
+ caslat -= 2;
+ else if (spd.clk_cycle2 == 0x3D)
+ caslat--;
+
+ } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
+ /*
+ * busfreq 560~700 range, treated as DDR 667.
+ */
+ effective_data_rate = 667;
+ if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
+ caslat -= 2;
+ else if (spd.clk_cycle2 == 0x30)
+ caslat--;
+
+ } else if (700 <= busfreq) {
+ /*
+ * DDR rate out-of-range
+ */
+ printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
+ busfreq, max_data_rate);
return 0;
}
+
/*
- * note: caslat must also be programmed into ddr->sdram_mode
- * register.
- *
- * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
- * use conservative value here.
+ * Convert caslat clocks to DDR controller value.
+ * Force caslat_ctrl to be DDR Controller field-sized.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ caslat_ctrl = (caslat + 1) & 0x07;
+ } else {
+ caslat_ctrl = (2 * caslat - 1) & 0x0f;
+ }
+
+ debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
+ debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+ caslat, caslat_ctrl);
+
+ /*
+ * Timing Config 0.
+ * Avoid writing for DDR I. The new PQ38 DDR controller
+ * dreams up non-zero default values to be backwards compatible.
*/
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ unsigned char taxpd_clk = 8; /* By the book. */
+ unsigned char tmrd_clk = 2; /* By the book. */
+ unsigned char act_pd_exit = 2; /* Empirical? */
+ unsigned char pre_pd_exit = 6; /* Empirical? */
+
+ ddr->timing_cfg_0 = (0
+ | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
+ | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
+ | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
+ | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
+ );
+#if 0
+ ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
+#endif
+ debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+
+ } else {
+#if 0
+ /*
+ * Force extra cycles with 0xaa bits.
+ * Incidentally supply the dreamt-up backwards compat value!
+ */
+ ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */
+ ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
+ debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+#endif
+ }
+
+
+ /*
+ * Some Timing Config 1 values now.
+ * Sneak Extended Refresh Recovery in here too.
+ */
+
+ /*
+ * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+ * use conservative value.
+ * For DDR II, they are bytes 36 and 37, in quarter nanos.
+ */
+
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ twr_clk = 3; /* Clocks */
+ twtr_clk = 1; /* Clocks */
+ } else {
+ twr_clk = picos_to_clk(spd.twr * 250);
+ twtr_clk = picos_to_clk(spd.twtr * 250);
+ }
+
+ /*
+ * Calculate Trfc, in picos.
+ * DDR I: Byte 42 straight up in ns.
+ * DDR II: Byte 40 and 42 swizzled some, in ns.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ trfc = spd.trfc * 1000; /* up to ps */
+ } else {
+ unsigned int byte40_table_ps[8] = {
+ 0,
+ 250,
+ 330,
+ 500,
+ 660,
+ 750,
+ 0,
+ 0
+ };
+
+ trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+ + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+ }
+ trfc_clk = picos_to_clk(trfc);
+
+ /*
+ * Trcd, Byte 29, from quarter nanos to ps and clocks.
+ */
+ trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+ /*
+ * Convert trfc_clk to DDR controller fields. DDR I should
+ * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+ * 8548 controller has an extended REFREC field of three bits.
+ * The controller automatically adds 8 clocks to this value,
+ * so preadjust it down 8 first before splitting it up.
+ */
+ trfc_low = (trfc_clk - 8) & 0xf;
+ trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
+
+ /*
+ * Sneak in some Extended Refresh Recovery.
+ */
+ ddr->ext_refrec = (trfc_high << 16);
+ debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+
ddr->timing_cfg_1 =
- (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
- ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
- ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
- ((caslat & 0x07) << 16 ) |
- (((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) |
- ( 0x300 ) |
- ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
+ (0
+ | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
+ | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
+ | (trcd_clk << 20) /* ACTTORW */
+ | (caslat_ctrl << 16) /* CASLAT */
+ | (trfc_low << 12) /* REFEC */
+ | ((twr_clk & 0x07) << 8) /* WRRREC */
+ | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
+ | ((twtr_clk & 0x07) << 0) /* WRTORD */
+ );
- ddr->timing_cfg_2 = 0x00000800;
+ debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
- debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
- debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
/*
- * Only DDR I is supported
- * DDR I and II have different mode-register-set definition
+ * Timing_Config_2
+ * Was: 0x00000800;
*/
- /* burst length is always 4 */
- switch(caslat) {
- case 2:
- ddr->sdram_mode = 0x52; /* 1.5 */
- break;
- case 3:
- ddr->sdram_mode = 0x22; /* 2.0 */
- break;
- case 4:
- ddr->sdram_mode = 0x62; /* 2.5 */
- break;
- case 5:
- ddr->sdram_mode = 0x32; /* 3.0 */
- break;
- default:
- puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
- return 0;
+ /*
+ * Additive Latency
+ * For DDR I, 0.
+ * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+ * which comes from Trcd, and also note that:
+ * add_lat + caslat must be >= 4
+ */
+ add_lat = 0;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2
+ && (odt_wr_cfg || odt_rd_cfg)
+ && (caslat < 4)) {
+ add_lat = 4 - caslat;
+ if (add_lat > trcd_clk) {
+ add_lat = trcd_clk - 1;
+ }
}
- debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
- switch(spd.refresh) {
- case 0x00:
- case 0x80:
- tmp = picos_to_clk(15625000);
- break;
- case 0x01:
- case 0x81:
- tmp = picos_to_clk(3900000);
- break;
- case 0x02:
- case 0x82:
- tmp = picos_to_clk(7800000);
- break;
- case 0x03:
- case 0x83:
- tmp = picos_to_clk(31300000);
- break;
- case 0x04:
- case 0x84:
- tmp = picos_to_clk(62500000);
- break;
- case 0x05:
- case 0x85:
- tmp = picos_to_clk(125000000);
- break;
- default:
- tmp = 0x512;
- break;
+ /*
+ * Write Data Delay
+ * Historically 0x2 == 4/8 clock delay.
+ * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+ */
+ wr_data_delay = 3;
+
+ /*
+ * Write Latency
+ * Read to Precharge
+ * Minimum CKE Pulse Width.
+ * Four Activate Window
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ /*
+ * This is a lie. It should really be 1, but if it is
+ * set to 1, bits overlap into the old controller's
+ * otherwise unused ACSM field. If we leave it 0, then
+ * the HW will magically treat it as 1 for DDR 1. Oh Yea.
+ */
+ wr_lat = 0;
+
+ trtp_clk = 2; /* By the book. */
+ cke_min_clk = 1; /* By the book. */
+ four_act = 1; /* By the book. */
+
+ } else {
+ wr_lat = caslat - 1;
+
+ /* Convert SPD value from quarter nanos to picos. */
+ trtp_clk = picos_to_clk(spd.trtp * 250);
+
+ cke_min_clk = 3; /* By the book. */
+ four_act = picos_to_clk(37500); /* By the book. 1k pages? */
+ }
+
+ /*
+ * Empirically set ~MCAS-to-preamble override for DDR 2.
+ * Your milage will vary.
+ */
+ cpo = 0;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ if (effective_data_rate == 266 || effective_data_rate == 333) {
+ cpo = 0x7; /* READ_LAT + 5/4 */
+ } else if (effective_data_rate == 400) {
+ cpo = 0x9; /* READ_LAT + 7/4 */
+ } else {
+ /* Pure speculation */
+ cpo = 0xb;
+ }
+ }
+
+ ddr->timing_cfg_2 = (0
+ | ((add_lat & 0x7) << 28) /* ADD_LAT */
+ | ((cpo & 0x1f) << 23) /* CPO */
+ | ((wr_lat & 0x7) << 19) /* WR_LAT */
+ | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
+ | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
+ | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
+ | ((four_act & 0x1f) << 0) /* FOUR_ACT */
+ );
+
+ debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
+
+
+ /*
+ * Determine the Mode Register Set.
+ *
+ * This is nominally part specific, but it appears to be
+ * consistent for all DDR I devices, and for all DDR II devices.
+ *
+ * caslat must be programmed
+ * burst length is always 4
+ * burst type is sequential
+ *
+ * For DDR I:
+ * operating mode is "normal"
+ *
+ * For DDR II:
+ * other stuff
+ */
+
+ mode_caslat = 0;
+
+ /*
+ * Table lookup from DDR I or II Device Operation Specs.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ if (1 <= caslat && caslat <= 4) {
+ unsigned char mode_caslat_table[4] = {
+ 0x5, /* 1.5 clocks */
+ 0x2, /* 2.0 clocks */
+ 0x6, /* 2.5 clocks */
+ 0x3 /* 3.0 clocks */
+ };
+ mode_caslat = mode_caslat_table[caslat - 1];
+ } else {
+ puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
+ "2.5 and 3.0 clocks are supported.\n");
+ return 0;
+ }
+
+ } else {
+ if (2 <= caslat && caslat <= 5) {
+ mode_caslat = caslat;
+ } else {
+ puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
+ "4.0 and 5.0 clocks are supported.\n");
+ return 0;
+ }
+ }
+
+ /*
+ * Encoded Burst Lenght of 4.
+ */
+ burst_len = 2; /* Fiat. */
+
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ twr_auto_clk = 0; /* Historical */
+ } else {
+ /*
+ * Determine tCK max in picos. Grab tWR and convert to picos.
+ * Auto-precharge write recovery is:
+ * WR = roundup(tWR_ns/tCKmax_ns).
+ *
+ * Ponder: Is twr_auto_clk different than twr_clk?
+ */
+ tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
+ twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
+ }
+
+
+ /*
+ * Mode Reg in bits 16 ~ 31,
+ * Extended Mode Reg 1 in bits 0 ~ 15.
+ */
+ mode_odt_enable = 0x0; /* Default disabled */
+ if (odt_wr_cfg || odt_rd_cfg) {
+ /*
+ * Bits 6 and 2 in Extended MRS(1)
+ * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+ * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+ */
+ mode_odt_enable = 0x40; /* 150 Ohm */
}
+ ddr->sdram_mode =
+ (0
+ | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
+ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
+ | (twr_auto_clk << 9) /* Write Recovery Autopre */
+ | (mode_caslat << 4) /* caslat */
+ | (burst_len << 0) /* Burst length */
+ );
+
+ debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode);
+
+
+ /*
+ * Clear EMRS2 and EMRS3.
+ */
+ ddr->sdram_mode_2 = 0;
+ debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
+
+
/*
- * Set BSTOPRE to 0x100 for page mode
- * If auto-charge is used, set BSTOPRE = 0
+ * Determine Refresh Rate. Ignore self refresh bit on DDR I.
+ * Table from SPD Spec, Byte 12, converted to picoseconds and
+ * filled in with "default" normal values.
*/
- ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
- debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
+ {
+ unsigned int refresh_clk;
+ unsigned int refresh_time_ns[8] = {
+ 15625000, /* 0 Normal 1.00x */
+ 3900000, /* 1 Reduced .25x */
+ 7800000, /* 2 Extended .50x */
+ 31300000, /* 3 Extended 2.00x */
+ 62500000, /* 4 Extended 4.00x */
+ 125000000, /* 5 Extended 8.00x */
+ 15625000, /* 6 Normal 1.00x filler */
+ 15625000, /* 7 Normal 1.00x filler */
+ };
+
+ refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
+
+ /*
+ * Set BSTOPRE to 0x100 for page mode
+ * If auto-charge is used, set BSTOPRE = 0
+ */
+ ddr->sdram_interval =
+ (0
+ | (refresh_clk & 0x3fff) << 16
+ | 0x100
+ );
+ debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
+ }
/*
* Is this an ECC DDR chip?
+ * But don't mess with it if the DDR controller will init mem.
*/
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
if (spd.config == 0x02) {
ddr->err_disable = 0x0000000d;
ddr->err_sbe = 0x00ff0000;
}
- debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
- debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
+ debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
+ debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
#endif
- asm("sync;isync;msync");
+ asm("sync;isync;msync");
udelay(500);
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
- /* Setup the clock control (8555 and later)
- * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
- * SDRAM_CLK_CNTL[5-7] = Clock Adjust == 3 (3/4 cycle late)
+ /*
+ * SDRAM Cfg 2
+ */
+
+ /*
+ * When ODT is enabled, Chap 9 suggests asserting ODT to
+ * internal IOs only during reads.
+ */
+ odt_cfg = 0;
+ if (odt_rd_cfg | odt_wr_cfg) {
+ odt_cfg = 0x2; /* ODT to IOs during reads */
+ }
+
+ /*
+ * Try to use differential DQS with DDR II.
*/
- ddr->sdram_clk_cntl = 0x83000000;
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ dqs_cfg = 0; /* No Differential DQS for DDR I */
+ } else {
+ dqs_cfg = 0x1; /* Differential DQS for DDR II */
+ }
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Use the DDR controller to auto initialize memory.
+ */
+ d_init = 1;
+ ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
+ debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
+#else
+ /*
+ * Memory will be initialized via DMA, or not at all.
+ */
+ d_init = 0;
+#endif
+
+ ddr->sdram_cfg_2 = (0
+ | (dqs_cfg << 26) /* Differential DQS */
+ | (odt_cfg << 21) /* ODT */
+ | (d_init << 4) /* D_INIT auto init DDR */
+ );
+
+ debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
+
+
+#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
+ {
+ unsigned char clk_adjust;
+
+ /*
+ * Setup the clock control.
+ * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+ * SDRAM_CLK_CNTL[5-7] = Clock Adjust
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ clk_adjust = 0x6;
+ } else {
+ clk_adjust = 0x7;
+ }
+
+ ddr->sdram_clk_cntl = (0
+ | 0x80000000
+ | (clk_adjust << 23)
+ );
+ debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
+ }
#endif
/*
- * Figure out the settings for the sdram_cfg register. Build up
- * the entire register in 'tmp' before writing since the write into
- * the register will actually enable the memory controller, and all
- * settings must be done before enabling.
+ * Figure out the settings for the sdram_cfg register.
+ * Build up the entire register in 'sdram_cfg' before writing
+ * since the write into the register will actually enable the
+ * memory controller; all settings must be done before enabling.
*
* sdram_cfg[0] = 1 (ddr sdram logic enable)
* sdram_cfg[1] = 1 (self-refresh-enable)
- * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+ * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+ * 010 DDR 1 SDRAM
+ * 011 DDR 2 SDRAM
*/
- tmp = 0xc2000000;
+ sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
+ sdram_cfg = (0
+ | (1 << 31) /* Enable */
+ | (1 << 30) /* Self refresh */
+ | (sdram_type << 24) /* SDRAM type */
+ );
/*
* sdram_cfg[3] = RD_EN - registered DIMM enable
* A value of 0x26 indicates micron registered DIMMS (micron.com)
*/
- if (spd.mod_attr == 0x26) {
- tmp |= 0x10000000;
+ if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
+ sdram_cfg |= 0x10000000; /* RD_EN */
}
#if defined(CONFIG_DDR_ECC)
* If the user wanted ECC (enabled via sdram_cfg[2])
*/
if (spd.config == 0x02) {
- tmp |= 0x20000000;
+ sdram_cfg |= 0x20000000; /* ECC_EN */
}
#endif
/*
* Enable 2T timing by setting sdram_cfg[16].
*/
- tmp |= 0x8000;
+ sdram_cfg |= 0x8000; /* 2T_EN */
#endif
}
}
- ddr->sdram_cfg = tmp;
+ /*
+ * 200 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ */
+ udelay(200);
+
+ /*
+ * Go!
+ */
+ ddr->sdram_cfg = sdram_cfg;
asm("sync;isync;msync");
udelay(500);
- debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
+ debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg);
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+#endif
+
+
+ /*
+ * Figure out memory size in Megabytes.
+ */
+ memsize = n_ranks * rank_density / 0x100000;
+
+ /*
+ * Establish Local Access Window and TLB mappings for DDR memory.
+ */
+ memsize = setup_laws_and_tlbs(memsize);
+ if (memsize == 0) {
+ return 0;
+ }
return memsize * 1024 * 1024;
}
+
+
+/*
+ * Setup Local Access Window and TLB1 mappings for the requested
+ * amount of memory. Returns the amount of memory actually mapped
+ * (usually the original request size), or 0 on error.
+ */
+
+static unsigned int
+setup_laws_and_tlbs(unsigned int memsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ unsigned int tlb_size;
+ unsigned int law_size;
+ unsigned int ram_tlb_index;
+ unsigned int ram_tlb_address;
+
+ /*
+ * Determine size of each TLB1 entry.
+ */
+ switch (memsize) {
+ case 16:
+ case 32:
+ tlb_size = BOOKE_PAGESZ_16M;
+ break;
+ case 64:
+ case 128:
+ tlb_size = BOOKE_PAGESZ_64M;
+ break;
+ case 256:
+ case 512:
+ case 1024:
+ case 2048:
+ tlb_size = BOOKE_PAGESZ_256M;
+ break;
+ default:
+ puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
+
+ /*
+ * The memory was not able to be mapped.
+ */
+ return 0;
+ break;
+ }
+
+ /*
+ * Configure DDR TLB1 entries.
+ * Starting at TLB1 8, use no more than 8 TLB1 entries.
+ */
+ ram_tlb_index = 8;
+ ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+ while (ram_tlb_address < (memsize * 1024 * 1024)
+ && ram_tlb_index < 16) {
+ mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
+ mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
+ mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
+ 0, 0, 0, 0, 0, 0, 0, 0));
+ mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
+ 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+ asm volatile("isync;msync;tlbwe;isync");
+
+ debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
+ debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
+ debug("DDR: MAS2=0x%08x\n",
+ TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
+ 0, 0, 0, 0, 0, 0, 0, 0));
+ debug("DDR: MAS3=0x%08x\n",
+ TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
+ 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+
+ ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
+ ram_tlb_index++;
+ }
+
+
+ /*
+ * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
+ */
+ law_size = 19 + __ilog2(memsize);
+
+ /*
+ * Set up LAWBAR for all of DDR.
+ */
+ ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+ ecm->lawar1 = (LAWAR_EN
+ | LAWAR_TRGT_IF_DDR
+ | (LAWAR_SIZE & law_size));
+ debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
+ debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
+
+ /*
+ * Confirm that the requested amount of memory was mapped.
+ */
+ return memsize;
+}
+
#endif /* CONFIG_SPD_EEPROM */
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+
/*
* Initialize all of memory for ECC, then enable errors.
*/
+
void
ddr_enable_ecc(unsigned int dram_size)
{
if (((unsigned int)p & 0x1f) == 0) {
ppcDcbz((unsigned long) p);
}
- *p = (unsigned int)0xdeadbeef;
+ *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
if (((unsigned int)p & 0x1c) == 0x1c) {
ppcDcbf((unsigned long) p);
}
/*
* Enable errors for ECC.
*/
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
}
-#endif /* CONFIG_DDR_ECC */
+
+#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
{
DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
uint sccr, dfbrg;
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
gd->scc_clk = gd->vco_out / 4;
mtspr MCSR,r0
mtspr DEAR,r0
- mtspr DBCR0,r0
+ /* not needed and conflicts with some debuggers */
+ /* mtspr DBCR0,r0 */
mtspr DBCR1,r0
mtspr DBCR2,r0
- mtspr IAC1,r0
- mtspr IAC2,r0
+ /* not needed and conflicts with some debuggers */
+ /* mtspr IAC1,r0 */
+ /* mtspr IAC2,r0 */
mtspr DAC1,r0
mtspr DAC2,r0
mtspr BUCSR,r0 /* disable branch prediction */
mtspr MAS4,r0
mtspr MAS6,r0
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+ mtspr MAS7,r0
+#endif
isync
/* Setup interrupt vectors */
li r1,0x0b00
mtspr IVOR11,r1 /* 11: Interval timer */
li r1,0x0c00
- mtspr IVOR12,r1 /* 11: Watchdog timer */
- li r10,0x0d00
+ mtspr IVOR12,r1 /* 12: Watchdog timer */
+ li r1,0x0d00
mtspr IVOR13,r1 /* 13: Data TLB error */
li r1,0x0e00
mtspr IVOR14,r1 /* 14: Instruction TLB error */
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
ori r0,r0,0x4000 /* time base is processor clock */
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+ ori r0,r0,0x0080 /* enable MAS7 updates */
+#endif
mtspr HID0,r0
#if defined(CONFIG_ADDR_STREAMING)
/************************************************************************/
/* ** CONFIG STUFF -- should be moved to board config file */
/************************************************************************/
-#define CONFIG_LCD_LOGO
-#define LCD_INFO /* Display Logo, (C) and system info */
+#ifndef CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
+#endif
#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
#undef CONFIG_LCD_LOGO
-#undef LCD_INFO
+#undef CONFIG_LCD_INFO
#endif
/*----------------------------------------------------------------------*/
3, 0, 0, 1, 1, 15, 4, 0, 3
/* wbl, vpw, lcdac, wbf */
};
-#define LCD_INFO_BELOW_LOGO
+#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ057Q3DC02 */
/*----------------------------------------------------------------------*/
3, 0, 0, 1, 1, 248, 4, 0, 35
/* wbl, vpw, lcdac, wbf */
};
-#define LCD_INFO_BELOW_LOGO
+#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ065T9DR51U */
#ifdef CONFIG_SHARP_LQ084V1DG21
#include <mpc8xx.h>
#include <asm/processor.h>
-#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK)
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
#define PITC_SHIFT 16
#define PITR_SHIFT 16
failsafe--;
if (failsafe == 0)
break;
-
}
/* EMAC RESET */
#endif
/* MAL RESET */
- mtdcr (malmcr, MAL_CR_MMSR);
- /* wait for reset */
- while (mfdcr (malmcr) & MAL_CR_MMSR) {
- };
-#if defined(CONFIG_440)
- /* set RMII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+ mtdcr (malmcr, MAL_CR_MMSR);
+ /* wait for reset */
+ while (mfdcr (malmcr) & MAL_CR_MMSR) {
+ };
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ out32 (ZMII_FER, 0);
+ udelay(100);
+ /* set RII mode */
+ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+#elif defined(CONFIG_440)
+ /* set RMII mode */
+ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#endif /* CONFIG_440 */
/* MAL Channel RESET */
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
-#if defined(CONFIG_440)
- /* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if( get_pvr() == PVR_440GP_RB)
- mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- else
-#else
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
-#endif
+ /* Errata 1.12: MAL_1 -- Disable MAL bursting */
+ if (get_pvr() == PVR_440GP_RB) {
+ mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
+ }
/* Free "old" buffers */
if (hw_p->alloc_tx_buf)
reg |= dev->enetaddr[5];
out32 (EMAC_IAL + hw_p->hw_addr, reg);
+
switch (devnum) {
#if defined(CONFIG_NET_MULTI)
case 1:
out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
else
out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ mfsdr(sdr_mfr, reg);
+ /* set speed */
+ if (speed == _100BASET) {
+ out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
+ reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
+ } else {
+ reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+ out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
+ }
+ mtsdr(sdr_mfr, reg);
+#endif
#endif
/* Enable broadcast and indvidual address */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif
-
/* Frame gap set */
out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/*
* Connect interrupt service routines
*/
-#if !defined(CONFIG_405EP)
- /* 405EP has one EWU interrupt */
- irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
- (interrupt_handler_t *) enetInt, dev);
-#endif
irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
}
mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
mtdcr (malier, mal_ier);
-#if defined(CONFIG_405EP)
- /* 405EP has one EWU interrupt */
- irq_install_handler (VECNUM_EWU0,
- (interrupt_handler_t *) enetInt,
- dev);
-#endif
/* install MAL interrupt handler */
irq_install_handler (VECNUM_MS,
(interrupt_handler_t *) enetInt,
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_sdstp1,strap);
if ( (strap & 0x00010000) == 0 ){
printf("PCI: SDR0_STRP1[PISE] not set.\n");
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
-#else
+#elif defined(PCIX0_BRDGOPT1)
out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
#endif
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+#endif
hose->last_busno = pci_hose_scan(hose);
}
}
/* EMAC RESET */
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+ hw_p->print_speed = 1; /* print speed message again next time */
+
return;
}
extern int phy_setup_aneg (unsigned char addr);
extern int miiphy_reset (unsigned char addr);
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long pfc1;
static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
{
- int i;
+ int i, j;
unsigned long reg;
unsigned long msr;
unsigned long speed;
unsigned short devnum;
unsigned short reg_short;
sys_info_t sysinfo;
+#if defined(CONFIG_440GX)
int ethgroup;
+#endif
EMAC_440GX_HW_PST hw_p = dev->priv;
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
-
msr = mfmsr ();
mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
/* MAL Channel RESET */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
+#else
mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
+#endif
+
mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
/* wait for reset */
out32 (ZMII_FER, 0);
udelay (100);
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+#elif defined(CONFIG_440GX)
ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
#else
if ((devnum == 0) || (devnum == 1)) {
out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
(RGMII_FER_RGMII << RGMII_FER_V (3))));
}
-
#endif
+
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
__asm__ volatile ("eieio");
failsafe--;
}
+#if defined(CONFIG_440GX)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-
+#endif /* defined(CONFIG_440GX) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
case 1:
reg = CONFIG_PHY1_ADDR;
break;
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
case 2:
reg = CONFIG_PHY2_ADDR;
break;
bis->bi_phynum[devnum] = reg;
+#ifndef CONFIG_NO_PHY_RESET
/*
* Reset the phy, only if its the first time through
* otherwise, just check the speeds & feeds
if (hw_p->first_init == 0) {
miiphy_reset (reg);
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#if defined(CONFIG_CIS8201_PHY)
- /*
- * Cicada 8201 PHY needs to have an extended register whacked
- * for RGMII mode.
- */
- if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
- miiphy_write (reg, 23, 0x1200);
/*
- * Vitesse VSC8201/Cicada CIS8201 errata:
- * Interoperability problem with Intel 82547EI phys
- * This work around (provided by Vitesse) changes
- * the default timer convergence from 8ms to 12ms
+ * Cicada 8201 PHY needs to have an extended register whacked
+ * for RGMII mode.
*/
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0200);
- miiphy_write (reg, 0x1f, 0x52b5);
- miiphy_write (reg, 0x02, 0x0004);
- miiphy_write (reg, 0x01, 0x0671);
- miiphy_write (reg, 0x00, 0x8fae);
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0000);
- miiphy_write (reg, 0x1f, 0x0000);
- /* end Vitesse/Cicada errata */
- }
+ if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
+#if defined(CONFIG_CIS8201_SHORT_ETCH)
+ miiphy_write (reg, 23, 0x1300);
+#else
+ miiphy_write (reg, 23, 0x1000);
+#endif
+ /*
+ * Vitesse VSC8201/Cicada CIS8201 errata:
+ * Interoperability problem with Intel 82547EI phys
+ * This work around (provided by Vitesse) changes
+ * the default timer convergence from 8ms to 12ms
+ */
+ miiphy_write (reg, 0x1f, 0x2a30);
+ miiphy_write (reg, 0x08, 0x0200);
+ miiphy_write (reg, 0x1f, 0x52b5);
+ miiphy_write (reg, 0x02, 0x0004);
+ miiphy_write (reg, 0x01, 0x0671);
+ miiphy_write (reg, 0x00, 0x8fae);
+ miiphy_write (reg, 0x1f, 0x2a30);
+ miiphy_write (reg, 0x08, 0x0000);
+ miiphy_write (reg, 0x1f, 0x0000);
+ /* end Vitesse/Cicada errata */
+ }
#endif
#endif
/* Start/Restart autonegotiation */
phy_setup_aneg (reg);
udelay (1000);
}
+#endif /* CONFIG_NO_PHY_RESET */
miiphy_read (reg, PHY_BMSR, ®_short);
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ mfsdr(sdr_mfr, reg);
+ if (speed == 100) {
+ reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
+ } else {
+ reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+ }
+ mtsdr(sdr_mfr, reg);
+#endif
+
/* Set ZMII/RGMII speed according to the phy link speed */
reg = in32 (ZMII_SSR);
if ( (speed == 100) || (speed == 1000) )
out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
else
- out32 (ZMII_SSR,
- reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+ out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
if ((devnum == 2) || (devnum == 3)) {
if (speed == 1000)
}
/* set the Mal configuration reg */
+#if defined(CONFIG_440GX)
+ mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
+ MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
+#else
+ mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
/* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if (get_pvr () == PVR_440GP_RB)
- mtdcr (malmcr,
- MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- else
- mtdcr (malmcr,
- MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
- MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
+ if (get_pvr() == PVR_440GP_RB) {
+ mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
+ }
+#endif
/* Free "old" buffers */
if (hw_p->alloc_tx_buf)
hw_p->alloc_tx_buf =
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
+ if (NULL == hw_p->alloc_tx_buf)
+ return -1;
if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
hw_p->tx =
(mal_desc_t *) ((int) hw_p->alloc_tx_buf +
hw_p->alloc_rx_buf =
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
+ if (NULL == hw_p->alloc_rx_buf) {
+ free(hw_p->alloc_tx_buf);
+ hw_p->alloc_tx_buf = NULL;
+ return -1;
+ }
+
if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
hw_p->rx =
(mal_desc_t *) ((int) hw_p->alloc_rx_buf +
for (i = 0; i < NUM_TX_BUFF; i++) {
hw_p->tx[i].ctrl = 0;
hw_p->tx[i].data_len = 0;
- if (hw_p->first_init == 0)
+ if (hw_p->first_init == 0) {
hw_p->txbuf_ptr =
(char *) malloc (ENET_MAX_MTU_ALIGNED);
+ if (NULL == hw_p->txbuf_ptr) {
+ free(hw_p->alloc_rx_buf);
+ free(hw_p->alloc_tx_buf);
+ hw_p->alloc_rx_buf = NULL;
+ hw_p->alloc_tx_buf = NULL;
+ for(j = 0; j < i; j++) {
+ free(hw_p->tx[i].data_ptr);
+ hw_p->tx[i].data_ptr = NULL;
+ }
+ }
+ }
hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
if ((NUM_TX_BUFF - 1) == i)
hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
- mtdcr (maltxbattr, 0x0);
+#if defined (CONFIG_440EP) || defined (CONFIG_440GR)
+ mtdcr (maltxctp2r, hw_p->tx);
+#else
mtdcr (maltxctp1r, hw_p->tx);
+#endif
+ mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
mtdcr (malrxctp1r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
break;
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
case 2:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
/* set RX buffer size */
mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
break;
-#endif /*CONFIG_440_GX */
+#endif /* CONFIG_440GX */
case 0:
default:
/* setup MAL tx & rx channel pointers */
}
/* Enable MAL transmit and receive channels */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
+#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
+#endif
mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
/* set transmit enable & receive enable */
unsigned long mal_rx_eob;
unsigned long my_uic0msr, my_uic1msr;
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
unsigned long my_uic2msr;
#endif
EMAC_440GX_HW_PST hw_p;
my_uic0msr = mfdcr (uic0msr);
my_uic1msr = mfdcr (uic1msr);
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
my_uic2msr = mfdcr (uic2msr);
#endif
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
/* not for us */
return (rc);
}
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
&& !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
/* not for us */
return (rc); /* we had errors so get out */
}
}
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
if (hw_p->devnum == 2) {
if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
return (rc); /* we had errors so get out */
}
}
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/* handle MAX TX EOB interrupt from a tx */
if (my_uic0msr & UIC_MTE) {
mal_rx_eob = mfdcr (maltxeobisr);
case 1:
mtdcr (uic1sr, UIC_ETH1);
break;
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
case 2:
mtdcr (uic2sr, UIC_ETH2);
break;
case 3:
mtdcr (uic2sr, UIC_ETH3);
break;
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
default:
break;
}
int ppc_440x_eth_initialize (bd_t * bis)
{
static int virgin = 0;
- unsigned long pfc1;
struct eth_device *dev;
int eth_num = 0;
-
EMAC_440GX_HW_PST hw = NULL;
+#if defined(CONFIG_440GX)
+ unsigned long pfc1;
+
mfsdr (sdr_pfc1, pfc1);
pfc1 &= ~(0x01e00000);
pfc1 |= 0x01200000;
mtsdr (sdr_pfc1, pfc1);
+#endif
/* set phy num and mode */
bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+#if defined(CONFIG_PHY1_ADDR)
bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+#endif
+#if defined(CONFIG_440GX)
bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[0] = 0;
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
ppc_440x_eth_setup_bridge(0, bis);
#endif
+#endif
for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
}
hw->devnum = eth_num;
+ hw->print_speed = 1;
sprintf (dev->name, "ppc_440x_eth%d", eth_num);
dev->priv = (void *) hw;
bedbug_405.o commproc.o \
cpu.o cpu_init.o i2c.o interrupts.o \
miiphy.o miiphy_440.o sdram.o serial.o \
- spd_sdram.o speed.o traps.o
+ spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o
OBJS = $(AOBJS) $(COBJS)
get_sys_info(&sys_info);
#ifdef CONFIG_405GP
- puts ("IBM PowerPC 405GP");
+ puts ("AMCC PowerPC 405GP");
if (pvr == PVR_405GPR_RB) {
putc('r');
}
puts (" Rev. ");
#endif
#ifdef CONFIG_405CR
- puts ("IBM PowerPC 405CR Rev. ");
+ puts ("AMCC PowerPC 405CR Rev. ");
#endif
#ifdef CONFIG_405EP
- puts ("IBM PowerPC 405EP Rev. ");
+ puts ("AMCC PowerPC 405EP Rev. ");
#endif
switch (pvr) {
case PVR_405GP_RB:
#endif
#if defined(CONFIG_440)
- puts ("IBM PowerPC 440 G");
+ puts ("AMCC PowerPC 440");
switch(pvr) {
case PVR_440GP_RB:
- puts("P Rev. B");
+ puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
}
break;
case PVR_440GP_RC:
- puts("P Rev. C");
+ puts("GP Rev. C");
break;
case PVR_440GX_RA:
- puts("X Rev. A");
+ puts("GX Rev. A");
break;
case PVR_440GX_RB:
- puts("X Rev. B");
+ puts("GX Rev. B");
break;
case PVR_440GX_RC:
- puts("X Rev. C");
+ puts("GX Rev. C");
break;
+#if defined(CONFIG_440GR)
+ case PVR_440EP_RA:
+ puts("GR Rev. A");
+ break;
+ case PVR_440EP_RB:
+ puts("GR Rev. B");
+ break;
+#else
+ case PVR_440EP_RA:
+ puts("EP Rev. A");
+ break;
+ case PVR_440EP_RB:
+ puts("EP Rev. B");
+ break;
+#endif
+
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
+#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
+ /*give reset to BCSR*/
+ *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
+
+#else
+
/*
* Initiate system reset in debug control register DBCR
*/
#else
__asm__ __volatile__("mtspr 0x3f2, 3");
#endif
+
+#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
return 1;
}
unsigned long val;
val = mfspr(tcr);
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ val |= 0xb8000000; /* generate system reset after 1.34 seconds */
+#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
+#endif
mtspr(tcr, val);
val = mfspr(tsr);
void uic1_interrupt( void * parms); /* UIC1 handler */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
static struct irq_action irq_vecs2[32]; /* For UIC2 */
void uic0_interrupt( void * parms); /* UIC0 handler */
void uic2_interrupt( void * parms); /* UIC2 handler */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
irq_vecs2[vec].handler = NULL;
irq_vecs2[vec].arg = NULL;
irq_vecs2[vec].count = 0;
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#endif
}
set_evpr(0x00000000);
#if defined(CONFIG_440)
-#if !defined(CONFIG_440_GX)
+#if !defined(CONFIG_440GX)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
#endif
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
/* Take the GX out of compatibility mode
* Travis Sawyer, 9 Mar 2004
* NOTE: 440gx user manual inconsistency here
/*
* Handle external interrupts
*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
void external_interrupt(struct pt_regs *regs)
{
ulong uic_msr;
return;
-} /* external_interrupt CONFIG_440_GX */
+} /* external_interrupt CONFIG_440GX */
#else
}
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
/* Handler for UIC0 interrupt */
void uic0_interrupt( void * parms)
{
}
}
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#if defined(CONFIG_440)
/* Handler for UIC1 interrupt */
}
#endif /* defined(CONFIG_440) */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
/* Handler for UIC1 interrupt */
void uic2_interrupt( void * parms)
{
vec++;
}
}
-#endif /* defined(CONFIG_440_GX) */
+#endif /* defined(CONFIG_440GX) */
/****************************************************************************/
int i = vec;
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
i = vec - 32;
irqa = irq_vecs1;
i = vec - 64;
irqa = irq_vecs2;
}
-#else /* CONFIG_440_GX */
+#else /* CONFIG_440GX */
if (vec > 31) {
i = vec - 32;
irqa = irq_vecs1;
}
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
- if (irqa[i].handler != NULL) {
+ /*
+ * print warning when replacing with a different irq vector
+ */
+ if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) {
printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
vec, (uint) handler, (uint) irqa[i].handler);
}
irqa[i].arg = arg;
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
else
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else
int i = vec;
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
irqa = irq_vecs1;
i = vec - 32;
irqa = irq_vecs2;
i = vec - 64;
}
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
if (vec > 31) {
irqa = irq_vecs1;
i = vec - 32;
#endif
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
else
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else
printf("\n");
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
printf ("\nUIC 2\n");
printf ("Nr Routine Arg Count\n");
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_READ;
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
sta_reg = 0;
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_WRITE;
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
#if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
+#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
+#else
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
-#if defined(CONFIG_440_GX)
+#endif
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define CR0_MASK 0x3fff0000
#define CR0_EXTCLK_ENA 0x00600000
#define CR0_UDIV_POS 16
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#elif defined(CONFIG_405EP)
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#endif
#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
unsigned long tmp;
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
#endif
#else
reg = mfdcr(cntrl0) & ~CR0_MASK;
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
* Jun Gu, Artesyn Technology, jung@artesyncp.com
* Support for IBM 440 based on OpenBIOS draminit.c from IBM.
*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#define CFG_I2C_SLAVE 0xFE
#endif
-#ifndef CONFIG_440 /* for 405 WALNUT board */
+#define ONE_BILLION 1000000000
+
+#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
#define SDRAM0_CFG_DCE 0x80000000
#define SDRAM0_CFG_SRE 0x40000000
long int spd_sdram(int(read_spd)(uint addr))
{
- int bus_period,tmp,row,col;
+ int tmp,row,col;
int total_size,bank_size,bank_code;
int ecc_on;
int mode;
int t_rc;
int min_cas;
- if(read_spd == 0){
- read_spd=spd_read;
- /*
- * Make sure I2C controller is initialized
- * before continuing.
- */
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
- }
-
+ PPC405_SYS_INFO sys_info;
+ unsigned long bus_period_x_10;
/*
- * Calculate the bus period, we do it this
- * way to minimize stack utilization.
+ * get the board info
*/
-#ifndef CONFIG_405EP
- tmp = (mfdcr(pllmd) >> (31-6)) & 0xf; /* get FBDV bits */
- tmp = CONFIG_SYS_CLK_FREQ * tmp; /* get plb freq */
-#else
- {
- unsigned long freqCPU;
- unsigned long pllmr0;
- unsigned long pllmr1;
- unsigned long pllFbkDiv;
- unsigned long pllPlbDiv;
- unsigned long pllmr0_ccdv;
-
- /*
- * Read PLL Mode registers
- */
- pllmr0 = mfdcr (cpc0_pllmr0);
- pllmr1 = mfdcr (cpc0_pllmr1);
-
- pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
- if (pllFbkDiv == 0) {
- pllFbkDiv = 16;
- }
- pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
-
- /*
- * Determine CPU clock frequency
- */
- pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
- if (pllmr1 & PLLMR1_SSCS_MASK) {
- freqCPU = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / pllmr0_ccdv;
- } else {
- freqCPU = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
- }
+ get_sys_info(&sys_info);
+ bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
+ if (read_spd == 0){
+ read_spd=spd_read;
/*
- * Determine PLB clock frequency
+ * Make sure I2C controller is initialized
+ * before continuing.
*/
- tmp = freqCPU / pllPlbDiv;
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
}
-#endif
- bus_period = sdram_HZ_to_ns(tmp); /* get sdram speed */
/* Make shure we are using SDRAM */
- if (read_spd(2) != 0x04){
- SPD_ERR("SDRAM - non SDRAM memory module found\n");
- }
-
-/*------------------------------------------------------------------
- configure memory timing register
+ if (read_spd(2) != 0x04) {
+ SPD_ERR("SDRAM - non SDRAM memory module found\n");
+ }
- data from DIMM:
- 27 IN Row Precharge Time ( t RP)
- 29 MIN RAS to CAS Delay ( t RCD)
- 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
- -------------------------------------------------------------------*/
+ /* ------------------------------------------------------------------
+ * configure memory timing register
+ *
+ * data from DIMM:
+ * 27 IN Row Precharge Time ( t RP)
+ * 29 MIN RAS to CAS Delay ( t RCD)
+ * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
+ * -------------------------------------------------------------------*/
- /*
- * first figure out which cas latency mode to use
- * use the min supported mode
- */
+ /*
+ * first figure out which cas latency mode to use
+ * use the min supported mode
+ */
tmp = read_spd(127) & 0x6;
- if(tmp == 0x02){ /* only cas = 2 supported */
- min_cas = 2;
+ if (tmp == 0x02){ /* only cas = 2 supported */
+ min_cas = 2;
/* t_ck = read_spd(9); */
/* t_ac = read_spd(10); */
- }
- else if (tmp == 0x04){ /* only cas = 3 supported */
- min_cas = 3;
+ } else if (tmp == 0x04) { /* only cas = 3 supported */
+ min_cas = 3;
/* t_ck = read_spd(9); */
/* t_ac = read_spd(10); */
- }
- else if (tmp == 0x06){ /* 2,3 supported, so use 2 */
- min_cas = 2;
+ } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
+ min_cas = 2;
/* t_ck = read_spd(23); */
/* t_ac = read_spd(24); */
- }
- else {
- SPD_ERR("SDRAM - unsupported CAS latency \n");
+ } else {
+ SPD_ERR("SDRAM - unsupported CAS latency \n");
}
- /* get some timing values, t_rp,t_rcd,t_ras,t_rc
- */
- t_rp = read_spd(27);
- t_rcd = read_spd(29);
- t_ras = read_spd(30);
- t_rc = t_ras + t_rp;
-
- /* The following timing calcs subtract 1 before deviding.
- * this has effect of using ceiling instead of floor rounding,
- * and also subtracting 1 to convert number to reg value
- */
- /* set up CASL */
- sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
- /* set up PTA */
- sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
- /* set up CTP */
- tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
- if(tmp<1) tmp=1;
- sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
- /* set LDF = 2 cycles, reg value = 1 */
- sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
- /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
- tmp = ( (t_rc - 1) / bus_period)-3;
- if(tmp<0)tmp=0;
- if(tmp>6)tmp=6;
+ /* get some timing values, t_rp,t_rcd,t_ras,t_rc
+ */
+ t_rp = read_spd(27);
+ t_rcd = read_spd(29);
+ t_ras = read_spd(30);
+ t_rc = t_ras + t_rp;
+
+ /* The following timing calcs subtract 1 before deviding.
+ * this has effect of using ceiling instead of floor rounding,
+ * and also subtracting 1 to convert number to reg value
+ */
+ /* set up CASL */
+ sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
+ /* set up PTA */
+ sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
+ /* set up CTP */
+ tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
+ if (tmp < 1)
+ tmp = 1;
+ sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
+ /* set LDF = 2 cycles, reg value = 1 */
+ sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
+ /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
+ tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
+ if (tmp < 0)
+ tmp = 0;
+ if (tmp > 6)
+ tmp = 6;
sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
- /* set RCD = t_rcd/bus_period*/
- sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
+ /* set RCD = t_rcd/bus_period*/
+ sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
-/*------------------------------------------------------------------
- configure RTR register
- -------------------------------------------------------------------*/
- row = read_spd(3);
- col = read_spd(4);
- tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
- switch(tmp){
+ /*------------------------------------------------------------------
+ * configure RTR register
+ * -------------------------------------------------------------------*/
+ row = read_spd(3);
+ col = read_spd(4);
+ tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
+ switch (tmp) {
case 0x00:
- tmp=15625;
- break;
+ tmp = 15625;
+ break;
case 0x01:
- tmp=15625/4;
- break;
+ tmp = 15625 / 4;
+ break;
case 0x02:
- tmp=15625/2;
- break;
+ tmp = 15625 / 2;
+ break;
case 0x03:
- tmp=15625*2;
- break;
+ tmp = 15625 * 2;
+ break;
case 0x04:
- tmp=15625*4;
- break;
+ tmp = 15625 * 4;
+ break;
case 0x05:
- tmp=15625*8;
- break;
+ tmp = 15625 * 8;
+ break;
default:
- SPD_ERR("SDRAM - Bad refresh period \n");
+ SPD_ERR("SDRAM - Bad refresh period \n");
}
/* convert from nsec to bus cycles */
- tmp = tmp/bus_period;
- sdram0_rtr = (tmp & 0x3ff8)<< SDRAM0_RTR_SHIFT;
+ tmp = (tmp * 10) / bus_period_x_10;
+ sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
-/*------------------------------------------------------------------
- determine the number of banks used
- -------------------------------------------------------------------*/
+ /*------------------------------------------------------------------
+ * determine the number of banks used
+ * -------------------------------------------------------------------*/
/* byte 7:6 is module data width */
- if(read_spd(7) != 0)
- SPD_ERR("SDRAM - unsupported module width\n");
+ if (read_spd(7) != 0)
+ SPD_ERR("SDRAM - unsupported module width\n");
tmp = read_spd(6);
if (tmp < 32)
- SPD_ERR("SDRAM - unsupported module width\n");
+ SPD_ERR("SDRAM - unsupported module width\n");
else if (tmp < 64)
- bank_cnt=1; /* one bank per sdram side */
+ bank_cnt = 1; /* one bank per sdram side */
else if (tmp < 73)
- bank_cnt=2; /* need two banks per side */
+ bank_cnt = 2; /* need two banks per side */
else if (tmp < 161)
- bank_cnt=4; /* need four banks per side */
+ bank_cnt = 4; /* need four banks per side */
else
- SPD_ERR("SDRAM - unsupported module width\n");
+ SPD_ERR("SDRAM - unsupported module width\n");
/* byte 5 is the module row count (refered to as dimm "sides") */
tmp = read_spd(5);
- if(tmp==1);
- else if(tmp==2) bank_cnt *=2;
- else if(tmp==4) bank_cnt *=4;
- else bank_cnt = 8; /* 8 is an error code */
+ if (tmp == 1)
+ ;
+ else if (tmp==2)
+ bank_cnt *= 2;
+ else if (tmp==4)
+ bank_cnt *= 4;
+ else
+ bank_cnt = 8; /* 8 is an error code */
- if(bank_cnt > 4) /* we only have 4 banks to work with */
- SPD_ERR("SDRAM - unsupported module rows for this width\n");
+ if (bank_cnt > 4) /* we only have 4 banks to work with */
+ SPD_ERR("SDRAM - unsupported module rows for this width\n");
/* now check for ECC ability of module. We only support ECC
* on 32 bit wide devices with 8 bit ECC.
*/
- if ( (read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) ){
- sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
- ecc_on = 1;
- }
- else{
- sdram0_ecccfg=0;
- ecc_on = 0;
+ if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
+ sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
+ ecc_on = 1;
+ } else {
+ sdram0_ecccfg = 0;
+ ecc_on = 0;
}
-/*------------------------------------------------------------------
- calculate total size
- -------------------------------------------------------------------*/
+ /*------------------------------------------------------------------
+ * calculate total size
+ * -------------------------------------------------------------------*/
/* calculate total size and do sanity check */
tmp = read_spd(31);
- total_size=1<<22; /* total_size = 4MB */
+ total_size = 1 << 22; /* total_size = 4MB */
/* now multiply 4M by the smallest device row density */
/* note that we don't support asymetric rows */
- while (((tmp & 0x0001) == 0) && (tmp != 0)){
- total_size= total_size<<1;
- tmp = tmp>>1;
- }
+ while (((tmp & 0x0001) == 0) && (tmp != 0)) {
+ total_size = total_size << 1;
+ tmp = tmp >> 1;
+ }
total_size *= read_spd(5); /* mult by module rows (dimm sides) */
-/*------------------------------------------------------------------
- map rows * cols * banks to a mode
- -------------------------------------------------------------------*/
+ /*------------------------------------------------------------------
+ * map rows * cols * banks to a mode
+ * -------------------------------------------------------------------*/
- switch( row )
- {
+ switch (row) {
case 11:
- switch ( col )
- {
+ switch (col) {
case 8:
mode=4; /* mode 5 */
break;
mode=0; /* mode 1 */
break;
default:
- SPD_ERR("SDRAM - unsupported mode\n");
+ SPD_ERR("SDRAM - unsupported mode\n");
}
break;
case 12:
- switch ( col )
- {
+ switch (col) {
case 8:
mode=3; /* mode 4 */
break;
mode=1; /* mode 2 */
break;
default:
- SPD_ERR("SDRAM - unsupported mode\n");
+ SPD_ERR("SDRAM - unsupported mode\n");
}
break;
case 13:
- switch ( col )
- {
+ switch (col) {
case 8:
mode=5; /* mode 6 */
break;
case 9:
case 10:
- if (read_spd(17) ==2 )
- mode=6; /* mode 7 */
+ if (read_spd(17) == 2)
+ mode = 6; /* mode 7 */
else
- mode=2; /* mode 3 */
+ mode = 2; /* mode 3 */
break;
case 11:
- mode=2; /* mode 3 */
+ mode = 2; /* mode 3 */
break;
default:
- SPD_ERR("SDRAM - unsupported mode\n");
+ SPD_ERR("SDRAM - unsupported mode\n");
}
break;
default:
- SPD_ERR("SDRAM - unsupported mode\n");
+ SPD_ERR("SDRAM - unsupported mode\n");
}
-/*------------------------------------------------------------------
- using the calculated values, compute the bank
- config register values.
- -------------------------------------------------------------------*/
+ /*------------------------------------------------------------------
+ * using the calculated values, compute the bank
+ * config register values.
+ * -------------------------------------------------------------------*/
sdram0_b1cr = 0;
sdram0_b2cr = 0;
sdram0_b3cr = 0;
/* compute the size of each bank */
bank_size = total_size / bank_cnt;
/* convert bank size to bank size code for ppc4xx
- by takeing log2(bank_size) - 22 */
- tmp=bank_size; /* start with tmp = bank_size */
- bank_code=0; /* and bank_code = 0 */
- while (tmp>1){ /* this takes log2 of tmp */
+ by takeing log2(bank_size) - 22 */
+ tmp = bank_size; /* start with tmp = bank_size */
+ bank_code = 0; /* and bank_code = 0 */
+ while (tmp > 1) { /* this takes log2 of tmp */
bank_code++; /* and stores result in bank_code */
- tmp=tmp>>1;
- } /* bank_code is now log2(bank_size) */
- bank_code-=22; /* subtract 22 to get the code */
+ tmp = tmp >> 1;
+ } /* bank_code is now log2(bank_size) */
+ bank_code -= 22; /* subtract 22 to get the code */
tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
- sdram0_b0cr = (bank_size) * 0 | tmp;
+ sdram0_b0cr = (bank_size * 0) | tmp;
#ifndef CONFIG_405EP /* not on PPC405EP */
- if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
- if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
- if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
+ if (bank_cnt > 1)
+ sdram0_b2cr = (bank_size * 1) | tmp;
+ if (bank_cnt > 2)
+ sdram0_b1cr = (bank_size * 2) | tmp;
+ if (bank_cnt > 3)
+ sdram0_b3cr = (bank_size * 3) | tmp;
#else
/* PPC405EP chip only supports two SDRAM banks */
- if(bank_cnt>1) sdram0_b1cr = (bank_size) * 1 | tmp;
- if(bank_cnt>2) total_size -= (bank_size) * (bank_cnt - 2);
+ if (bank_cnt > 1)
+ sdram0_b1cr = (bank_size * 1) | tmp;
+ if (bank_cnt > 2)
+ total_size = 2 * bank_size;
#endif
-
/*
* enable sdram controller DCE=1
* enable burst read prefetch to 32 bytes BRPF=2
* leave other functions off
*/
-/*------------------------------------------------------------------
- now that we've done our calculations, we are ready to
- program all the registers.
- -------------------------------------------------------------------*/
-
+ /*------------------------------------------------------------------
+ * now that we've done our calculations, we are ready to
+ * program all the registers.
+ * -------------------------------------------------------------------*/
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
/* disable memcontroller so updates work */
- sdram0_cfg = 0;
- mtsdram0( mem_mcopt1, sdram0_cfg );
+ mtsdram0( mem_mcopt1, 0 );
#ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram0( mem_besra , sdram0_besr0 );
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
- if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
- mtsdram0( mem_mcopt1, sdram0_cfg );
-
+ if (ecc_on)
+ sdram0_cfg |= SDRAM0_CFG_MEMCHK;
+ mtsdram0(mem_mcopt1, sdram0_cfg);
- /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
-#ifdef MVISTA_MEM_BUG
- if (total_size > 128*1024*1024 )
- total_size=128*1024*1024;
-#endif
return (total_size);
}
#else /* CONFIG_440 */
/*-----------------------------------------------------------------------------
-| Memory Controller Options 0
-+-----------------------------------------------------------------------------*/
+ | Memory Controller Options 0
+ +-----------------------------------------------------------------------------*/
#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
/*-----------------------------------------------------------------------------
-| Memory Controller Options 1
-+-----------------------------------------------------------------------------*/
+ | Memory Controller Options 1
+ +-----------------------------------------------------------------------------*/
#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
/*-----------------------------------------------------------------------------+
-| SDRAM DEVPOT Options
-+-----------------------------------------------------------------------------*/
+ | SDRAM DEVPOT Options
+ +-----------------------------------------------------------------------------*/
#define SDRAM_DEVOPT_DLL 0x80000000
#define SDRAM_DEVOPT_DS 0x40000000
/*-----------------------------------------------------------------------------+
-| SDRAM MCSTS Options
-+-----------------------------------------------------------------------------*/
+ | SDRAM MCSTS Options
+ +-----------------------------------------------------------------------------*/
#define SDRAM_MCSTS_MRSC 0x80000000
#define SDRAM_MCSTS_SRMS 0x40000000
#define SDRAM_MCSTS_CIS 0x20000000
/*-----------------------------------------------------------------------------
-| SDRAM Refresh Timer Register
-+-----------------------------------------------------------------------------*/
+ | SDRAM Refresh Timer Register
+ +-----------------------------------------------------------------------------*/
#define SDRAM_RTR_RINT_MASK 0xFFFF0000
#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
/*-----------------------------------------------------------------------------+
-| SDRAM UABus Base Address Reg
-+-----------------------------------------------------------------------------*/
+ | SDRAM UABus Base Address Reg
+ +-----------------------------------------------------------------------------*/
#define SDRAM_UABBA_UBBA_MASK 0x0000000F
/*-----------------------------------------------------------------------------+
-| Memory Bank 0-7 configuration
-+-----------------------------------------------------------------------------*/
+ | Memory Bank 0-7 configuration
+ +-----------------------------------------------------------------------------*/
#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
/*-----------------------------------------------------------------------------+
-| SDRAM TR0 Options
-+-----------------------------------------------------------------------------*/
+ | SDRAM TR0 Options
+ +-----------------------------------------------------------------------------*/
#define SDRAM_TR0_SDWR_MASK 0x80000000
#define SDRAM_TR0_SDWR_2_CLK 0x00000000
#define SDRAM_TR0_SDWR_3_CLK 0x80000000
#define SDRAM_TR0_SDRD_4_CLK 0x00000003
/*-----------------------------------------------------------------------------+
-| SDRAM TR1 Options
-+-----------------------------------------------------------------------------*/
+ | SDRAM TR1 Options
+ +-----------------------------------------------------------------------------*/
#define SDRAM_TR1_RDSS_MASK 0xC0000000
#define SDRAM_TR1_RDSS_TR0 0x00000000
#define SDRAM_TR1_RDSS_TR1 0x40000000
#define SDRAM_TR1_RDCT_MAX 0x000001FF
/*-----------------------------------------------------------------------------+
-| SDRAM WDDCTR Options
-+-----------------------------------------------------------------------------*/
+ | SDRAM WDDCTR Options
+ +-----------------------------------------------------------------------------*/
#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
-| SDRAM CLKTR Options
-+-----------------------------------------------------------------------------*/
+ | SDRAM CLKTR Options
+ +-----------------------------------------------------------------------------*/
#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
-| SDRAM DLYCAL Options
-+-----------------------------------------------------------------------------*/
+ | SDRAM DLYCAL Options
+ +-----------------------------------------------------------------------------*/
#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
/*-----------------------------------------------------------------------------+
-| General Definition
-+-----------------------------------------------------------------------------*/
+ | General Definition
+ +-----------------------------------------------------------------------------*/
#define DEFAULT_SPD_ADDR1 0x53
#define DEFAULT_SPD_ADDR2 0x52
-#define ONE_BILLION 1000000000
#define MAXBANKS 4 /* at most 4 dimm banks */
#define MAX_SPD_BYTES 256
#define NUMHALFCYCLES 4
#define FALSE 0
const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
- {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF},
- {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000},
- {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555},
- {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA},
- {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A},
- {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5},
- {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA},
- {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55}
+ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF},
+ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000},
+ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555},
+ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA},
+ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A},
+ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5},
+ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA},
+ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55}
};
unsigned long num_dimm_banks);
void check_mem_type
- (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+(unsigned long* dimm_populated,
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void check_volt_type
- (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+(unsigned long* dimm_populated,
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void program_cfg0(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
*/
long int spd_sdram(void) {
- unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
- unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
- unsigned long total_size;
- unsigned long cfg0;
- unsigned long mcsts;
- unsigned long num_dimm_banks; /* on board dimm banks */
+ unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
+ unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
+ unsigned long total_size;
+ unsigned long cfg0;
+ unsigned long mcsts;
+ unsigned long num_dimm_banks; /* on board dimm banks */
- num_dimm_banks = sizeof(iic0_dimm_addr);
+ num_dimm_banks = sizeof(iic0_dimm_addr);
/*
* Make sure I2C controller is initialized
*/
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
- /*
- * Read the SPD information using I2C interface. Check to see if the
- * DIMM slots are populated.
- */
- get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * Check the memory type for the dimms plugged.
- */
- check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * Check the voltage type for the dimms plugged.
- */
- check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
-#if defined(CONFIG_440_GX)
- /*
- * Soft-reset SDRAM controller.
- */
- mtsdr(sdr_srst, SDR0_SRST_DMC);
- mtsdr(sdr_srst, 0x00000000);
+ /*
+ * Read the SPD information using I2C interface. Check to see if the
+ * DIMM slots are populated.
+ */
+ get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+ /*
+ * Check the memory type for the dimms plugged.
+ */
+ check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+ /*
+ * Check the voltage type for the dimms plugged.
+ */
+ check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+#if defined(CONFIG_440GX)
+ /*
+ * Soft-reset SDRAM controller.
+ */
+ mtsdr(sdr_srst, SDR0_SRST_DMC);
+ mtsdr(sdr_srst, 0x00000000);
#endif
- /*
- * program 440GP SDRAM controller options (SDRAM0_CFG0)
- */
- program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program 440GP SDRAM controller options (SDRAM0_CFG1)
- */
- program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program SDRAM refresh register (SDRAM0_RTR)
- */
- program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program SDRAM Timing Register 0 (SDRAM0_TR0)
- */
- program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program the BxCR registers to find out total sdram installed
- */
- total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
- num_dimm_banks);
-
- /*
- * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
- */
- mtsdram(mem_clktr, 0x40000000);
-
- /*
- * delay to ensure 200 usec has elapsed
- */
- udelay(400);
-
- /*
- * enable the memory controller
- */
- mfsdram(mem_cfg0, cfg0);
- mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
-
- /*
- * wait for SDRAM_CFG0_DC_EN to complete
- */
- while(1) {
- mfsdram(mem_mcsts, mcsts);
- if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
- break;
+ /*
+ * program 440GP SDRAM controller options (SDRAM0_CFG0)
+ */
+ program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+ /*
+ * program 440GP SDRAM controller options (SDRAM0_CFG1)
+ */
+ program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+ /*
+ * program SDRAM refresh register (SDRAM0_RTR)
+ */
+ program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+ /*
+ * program SDRAM Timing Register 0 (SDRAM0_TR0)
+ */
+ program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+ /*
+ * program the BxCR registers to find out total sdram installed
+ */
+ total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
+ num_dimm_banks);
+
+ /*
+ * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
+ */
+ mtsdram(mem_clktr, 0x40000000);
+
+ /*
+ * delay to ensure 200 usec has elapsed
+ */
+ udelay(400);
+
+ /*
+ * enable the memory controller
+ */
+ mfsdram(mem_cfg0, cfg0);
+ mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
+
+ /*
+ * wait for SDRAM_CFG0_DC_EN to complete
+ */
+ while (1) {
+ mfsdram(mem_mcsts, mcsts);
+ if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
+ break;
+ }
}
- }
- /*
- * program SDRAM Timing Register 1, adding some delays
- */
- program_tr1();
+ /*
+ * program SDRAM Timing Register 1, adding some delays
+ */
+ program_tr1();
- /*
- * if ECC is enabled, initialize parity bits
- */
+ /*
+ * if ECC is enabled, initialize parity bits
+ */
return total_size;
}
unsigned char spd_read(uchar chip, uint addr) {
unsigned char data[2];
- if (i2c_read(chip, addr, 1, data, 1) == 0)
- return data[0];
- else
- return 0;
+ if (i2c_probe(chip) == 0) {
+ if (i2c_read(chip, addr, 1, data, 1) == 0) {
+ return data[0];
+ }
+ }
+
+ return 0;
}
void get_spd_info(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long dimm_num;
- unsigned long dimm_found;
- unsigned char num_of_bytes;
- unsigned char total_size;
-
- dimm_found = FALSE;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- num_of_bytes = 0;
- total_size = 0;
-
- num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
- total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
-
- if ((num_of_bytes != 0) && (total_size != 0)) {
- dimm_populated[dimm_num] = TRUE;
- dimm_found = TRUE;
+ unsigned long dimm_num;
+ unsigned long dimm_found;
+ unsigned char num_of_bytes;
+ unsigned char total_size;
+
+ dimm_found = FALSE;
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ num_of_bytes = 0;
+ total_size = 0;
+
+ num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
+ total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
+
+ if ((num_of_bytes != 0) && (total_size != 0)) {
+ dimm_populated[dimm_num] = TRUE;
+ dimm_found = TRUE;
#if 0
- printf("DIMM slot %lu: populated\n", dimm_num);
+ printf("DIMM slot %lu: populated\n", dimm_num);
#endif
- }
- else {
- dimm_populated[dimm_num] = FALSE;
+ } else {
+ dimm_populated[dimm_num] = FALSE;
#if 0
- printf("DIMM slot %lu: Not populated\n", dimm_num);
+ printf("DIMM slot %lu: Not populated\n", dimm_num);
#endif
+ }
}
- }
- if (dimm_found == FALSE) {
- printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- hang();
- }
+ if (dimm_found == FALSE) {
+ printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
+ hang();
+ }
}
void check_mem_type(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long dimm_num;
- unsigned char dimm_type;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
- switch (dimm_type) {
- case 7:
+ unsigned long dimm_num;
+ unsigned char dimm_type;
+
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_populated[dimm_num] == TRUE) {
+ dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
+ switch (dimm_type) {
+ case 7:
#if 0
- printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
+ printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
#endif
- break;
- default:
- printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
- dimm_num);
- printf("Only DDR SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
- break;
- }
+ break;
+ default:
+ printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
+ dimm_num);
+ printf("Only DDR SDRAM DIMMs are supported.\n");
+ printf("Replace the DIMM module with a supported DIMM.\n\n");
+ hang();
+ break;
+ }
+ }
}
- }
}
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long dimm_num;
- unsigned long voltage_type;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
- if (voltage_type != 0x04) {
- printf("ERROR: DIMM %lu with unsupported voltage level.\n",
- dimm_num);
- hang();
- }
- else {
+ unsigned long dimm_num;
+ unsigned long voltage_type;
+
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_populated[dimm_num] == TRUE) {
+ voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
+ if (voltage_type != 0x04) {
+ printf("ERROR: DIMM %lu with unsupported voltage level.\n",
+ dimm_num);
+ hang();
+ } else {
#if 0
- printf("DIMM %lu voltage level supported.\n", dimm_num);
+ printf("DIMM %lu voltage level supported.\n", dimm_num);
#endif
- }
- break;
+ }
+ break;
+ }
}
- }
}
void program_cfg0(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long dimm_num;
- unsigned long cfg0;
- unsigned long ecc_enabled;
- unsigned char ecc;
- unsigned char attributes;
- unsigned long data_width;
- unsigned long dimm_32bit;
- unsigned long dimm_64bit;
-
- /*
- * get Memory Controller Options 0 data
- */
- mfsdram(mem_cfg0, cfg0);
-
- /*
- * clear bits
- */
- cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
- SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
- SDRAM_CFG0_DMWD_MASK |
- SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
-
-
- /*
- * FIXME: assume the DDR SDRAMs in both banks are the same
- */
- ecc_enabled = TRUE;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
- if (ecc != 0x02) {
- ecc_enabled = FALSE;
- }
-
- /*
- * program Registered DIMM Enable
- */
- attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
- if ((attributes & 0x02) != 0x00) {
- cfg0 |= SDRAM_CFG0_RDEN;
- }
-
- /*
- * program DDR SDRAM Data Width
- */
- data_width =
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
- (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
- if (data_width == 64 || data_width == 72) {
- dimm_64bit = TRUE;
- cfg0 |= SDRAM_CFG0_DMWD_64;
- }
- else if (data_width == 32 || data_width == 40) {
- dimm_32bit = TRUE;
- cfg0 |= SDRAM_CFG0_DMWD_32;
- }
- else {
- printf("WARNING: DIMM with datawidth of %lu bits.\n",
- data_width);
- printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
- hang();
- }
- break;
+ unsigned long dimm_num;
+ unsigned long cfg0;
+ unsigned long ecc_enabled;
+ unsigned char ecc;
+ unsigned char attributes;
+ unsigned long data_width;
+ unsigned long dimm_32bit;
+ unsigned long dimm_64bit;
+
+ /*
+ * get Memory Controller Options 0 data
+ */
+ mfsdram(mem_cfg0, cfg0);
+
+ /*
+ * clear bits
+ */
+ cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
+ SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
+ SDRAM_CFG0_DMWD_MASK |
+ SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
+
+
+ /*
+ * FIXME: assume the DDR SDRAMs in both banks are the same
+ */
+ ecc_enabled = TRUE;
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_populated[dimm_num] == TRUE) {
+ ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
+ if (ecc != 0x02) {
+ ecc_enabled = FALSE;
+ }
+
+ /*
+ * program Registered DIMM Enable
+ */
+ attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
+ if ((attributes & 0x02) != 0x00) {
+ cfg0 |= SDRAM_CFG0_RDEN;
+ }
+
+ /*
+ * program DDR SDRAM Data Width
+ */
+ data_width =
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
+ (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
+ if (data_width == 64 || data_width == 72) {
+ dimm_64bit = TRUE;
+ cfg0 |= SDRAM_CFG0_DMWD_64;
+ } else if (data_width == 32 || data_width == 40) {
+ dimm_32bit = TRUE;
+ cfg0 |= SDRAM_CFG0_DMWD_32;
+ } else {
+ printf("WARNING: DIMM with datawidth of %lu bits.\n",
+ data_width);
+ printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
+ hang();
+ }
+ break;
+ }
}
- }
-
- /*
- * program Memory Data Error Checking
- */
- if (ecc_enabled == TRUE) {
- cfg0 |= SDRAM_CFG0_MCHK_GEN;
- }
- else {
- cfg0 |= SDRAM_CFG0_MCHK_NON;
- }
-
- /*
- * program Page Management Unit
- */
- cfg0 |= SDRAM_CFG0_PMUD;
-
- /*
- * program Memory Controller Options 0
- * Note: DCEN must be enabled after all DDR SDRAM controller
- * configuration registers get initialized.
- */
- mtsdram(mem_cfg0, cfg0);
+
+ /*
+ * program Memory Data Error Checking
+ */
+ if (ecc_enabled == TRUE) {
+ cfg0 |= SDRAM_CFG0_MCHK_GEN;
+ } else {
+ cfg0 |= SDRAM_CFG0_MCHK_NON;
+ }
+
+ /*
+ * program Page Management Unit
+ */
+ cfg0 |= SDRAM_CFG0_PMUD;
+
+ /*
+ * program Memory Controller Options 0
+ * Note: DCEN must be enabled after all DDR SDRAM controller
+ * configuration registers get initialized.
+ */
+ mtsdram(mem_cfg0, cfg0);
}
void program_cfg1(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long cfg1;
- mfsdram(mem_cfg1, cfg1);
-
- /*
- * Self-refresh exit, disable PM
- */
- cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
-
- /*
- * program Memory Controller Options 1
- */
- mtsdram(mem_cfg1, cfg1);
+ unsigned long cfg1;
+ mfsdram(mem_cfg1, cfg1);
+
+ /*
+ * Self-refresh exit, disable PM
+ */
+ cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
+
+ /*
+ * program Memory Controller Options 1
+ */
+ mtsdram(mem_cfg1, cfg1);
}
void program_rtr (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long dimm_num;
- unsigned long bus_period_x_10;
- unsigned long refresh_rate = 0;
- unsigned char refresh_rate_type;
- unsigned long refresh_interval;
- unsigned long sdram_rtr;
- PPC440_SYS_INFO sys_info;
-
- /*
- * get the board info
- */
- get_sys_info(&sys_info);
- bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
-
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
- switch (refresh_rate_type) {
- case 0x00:
- refresh_rate = 15625;
- break;
- case 0x01:
- refresh_rate = 15625/4;
- break;
- case 0x02:
- refresh_rate = 15625/2;
- break;
- case 0x03:
- refresh_rate = 15626*2;
- break;
- case 0x04:
- refresh_rate = 15625*4;
- break;
- case 0x05:
- refresh_rate = 15625*8;
- break;
- default:
- printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
- dimm_num);
- printf("Replace the DIMM module with a supported DIMM.\n");
- break;
- }
+ unsigned long dimm_num;
+ unsigned long bus_period_x_10;
+ unsigned long refresh_rate = 0;
+ unsigned char refresh_rate_type;
+ unsigned long refresh_interval;
+ unsigned long sdram_rtr;
+ PPC440_SYS_INFO sys_info;
- break;
+ /*
+ * get the board info
+ */
+ get_sys_info(&sys_info);
+ bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
+
+
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_populated[dimm_num] == TRUE) {
+ refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
+ switch (refresh_rate_type) {
+ case 0x00:
+ refresh_rate = 15625;
+ break;
+ case 0x01:
+ refresh_rate = 15625/4;
+ break;
+ case 0x02:
+ refresh_rate = 15625/2;
+ break;
+ case 0x03:
+ refresh_rate = 15626*2;
+ break;
+ case 0x04:
+ refresh_rate = 15625*4;
+ break;
+ case 0x05:
+ refresh_rate = 15625*8;
+ break;
+ default:
+ printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
+ dimm_num);
+ printf("Replace the DIMM module with a supported DIMM.\n");
+ break;
+ }
+
+ break;
+ }
}
- }
- refresh_interval = refresh_rate * 10 / bus_period_x_10;
- sdram_rtr = (refresh_interval & 0x3ff8) << 16;
+ refresh_interval = refresh_rate * 10 / bus_period_x_10;
+ sdram_rtr = (refresh_interval & 0x3ff8) << 16;
- /*
- * program Refresh Timer Register (SDRAM0_RTR)
- */
- mtsdram(mem_rtr, sdram_rtr);
+ /*
+ * program Refresh Timer Register (SDRAM0_RTR)
+ */
+ mtsdram(mem_rtr, sdram_rtr);
}
void program_tr0 (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long dimm_num;
- unsigned long tr0;
- unsigned char wcsbc;
- unsigned char t_rp_ns;
- unsigned char t_rcd_ns;
- unsigned char t_ras_ns;
- unsigned long t_rp_clk;
- unsigned long t_ras_rcd_clk;
- unsigned long t_rcd_clk;
- unsigned long t_rfc_clk;
- unsigned long plb_check;
- unsigned char cas_bit;
- unsigned long cas_index;
- unsigned char cas_2_0_available;
- unsigned char cas_2_5_available;
- unsigned char cas_3_0_available;
- unsigned long cycle_time_ns_x_10[3];
- unsigned long tcyc_3_0_ns_x_10;
- unsigned long tcyc_2_5_ns_x_10;
- unsigned long tcyc_2_0_ns_x_10;
- unsigned long tcyc_reg;
- unsigned long bus_period_x_10;
- PPC440_SYS_INFO sys_info;
- unsigned long residue;
-
- /*
- * get the board info
- */
- get_sys_info(&sys_info);
- bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
-
- /*
- * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
- */
- mfsdram(mem_tr0, tr0);
- tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
- SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
- SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
- SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
-
- /*
- * initialization
- */
- wcsbc = 0;
- t_rp_ns = 0;
- t_rcd_ns = 0;
- t_ras_ns = 0;
- cas_2_0_available = TRUE;
- cas_2_5_available = TRUE;
- cas_3_0_available = TRUE;
- tcyc_2_0_ns_x_10 = 0;
- tcyc_2_5_ns_x_10 = 0;
- tcyc_3_0_ns_x_10 = 0;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
- t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
- t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
- t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
- cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
-
- for (cas_index = 0; cas_index < 3; cas_index++) {
- switch (cas_index) {
- case 0:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
- break;
- case 1:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
- break;
- default:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
- break;
- }
+ unsigned long dimm_num;
+ unsigned long tr0;
+ unsigned char wcsbc;
+ unsigned char t_rp_ns;
+ unsigned char t_rcd_ns;
+ unsigned char t_ras_ns;
+ unsigned long t_rp_clk;
+ unsigned long t_ras_rcd_clk;
+ unsigned long t_rcd_clk;
+ unsigned long t_rfc_clk;
+ unsigned long plb_check;
+ unsigned char cas_bit;
+ unsigned long cas_index;
+ unsigned char cas_2_0_available;
+ unsigned char cas_2_5_available;
+ unsigned char cas_3_0_available;
+ unsigned long cycle_time_ns_x_10[3];
+ unsigned long tcyc_3_0_ns_x_10;
+ unsigned long tcyc_2_5_ns_x_10;
+ unsigned long tcyc_2_0_ns_x_10;
+ unsigned long tcyc_reg;
+ unsigned long bus_period_x_10;
+ PPC440_SYS_INFO sys_info;
+ unsigned long residue;
- if ((tcyc_reg & 0x0F) >= 10) {
- printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
- dimm_num);
- hang();
- }
+ /*
+ * get the board info
+ */
+ get_sys_info(&sys_info);
+ bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
- cycle_time_ns_x_10[cas_index] =
- (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
- }
-
- cas_index = 0;
-
- if ((cas_bit & 0x80) != 0) {
- cas_index += 3;
- }
- else if ((cas_bit & 0x40) != 0) {
- cas_index += 2;
- }
- else if ((cas_bit & 0x20) != 0) {
- cas_index += 1;
- }
-
- if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
- tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- }
- else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_3_0_available = FALSE;
- }
-
- if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
- tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- }
- else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_2_5_available = FALSE;
- }
-
- if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
- tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- }
- else {
- if (cas_index != 0) {
- cas_index++;
+ /*
+ * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
+ */
+ mfsdram(mem_tr0, tr0);
+ tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
+ SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
+ SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
+ SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
+
+ /*
+ * initialization
+ */
+ wcsbc = 0;
+ t_rp_ns = 0;
+ t_rcd_ns = 0;
+ t_ras_ns = 0;
+ cas_2_0_available = TRUE;
+ cas_2_5_available = TRUE;
+ cas_3_0_available = TRUE;
+ tcyc_2_0_ns_x_10 = 0;
+ tcyc_2_5_ns_x_10 = 0;
+ tcyc_3_0_ns_x_10 = 0;
+
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_populated[dimm_num] == TRUE) {
+ wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
+ t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
+ t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
+ t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
+ cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
+
+ for (cas_index = 0; cas_index < 3; cas_index++) {
+ switch (cas_index) {
+ case 0:
+ tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
+ break;
+ case 1:
+ tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
+ break;
+ default:
+ tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
+ break;
+ }
+
+ if ((tcyc_reg & 0x0F) >= 10) {
+ printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
+ dimm_num);
+ hang();
+ }
+
+ cycle_time_ns_x_10[cas_index] =
+ (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
+ }
+
+ cas_index = 0;
+
+ if ((cas_bit & 0x80) != 0) {
+ cas_index += 3;
+ } else if ((cas_bit & 0x40) != 0) {
+ cas_index += 2;
+ } else if ((cas_bit & 0x20) != 0) {
+ cas_index += 1;
+ }
+
+ if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
+ tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
+ cas_index++;
+ } else {
+ if (cas_index != 0) {
+ cas_index++;
+ }
+ cas_3_0_available = FALSE;
+ }
+
+ if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
+ tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
+ cas_index++;
+ } else {
+ if (cas_index != 0) {
+ cas_index++;
+ }
+ cas_2_5_available = FALSE;
+ }
+
+ if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
+ tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
+ cas_index++;
+ } else {
+ if (cas_index != 0) {
+ cas_index++;
+ }
+ cas_2_0_available = FALSE;
+ }
+
+ break;
}
- cas_2_0_available = FALSE;
- }
+ }
+
+ /*
+ * Program SD_WR and SD_WCSBC fields
+ */
+ tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
+ switch (wcsbc) {
+ case 0:
+ tr0 |= SDRAM_TR0_SDWD_0_CLK;
+ break;
+ default:
+ tr0 |= SDRAM_TR0_SDWD_1_CLK;
+ break;
+ }
+
+ /*
+ * Program SD_CASL field
+ */
+ if ((cas_2_0_available == TRUE) &&
+ (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
+ tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
+ } else if ((cas_2_5_available == TRUE) &&
+ (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
+ tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
+ } else if ((cas_3_0_available == TRUE) &&
+ (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
+ tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
+ } else {
+ printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
+ printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
+ printf("Make sure the PLB speed is within the supported range.\n");
+ hang();
+ }
+
+ /*
+ * Calculate Trp in clock cycles and round up if necessary
+ * Program SD_PTA field
+ */
+ t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
+ plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
+ if (sys_info.freqPLB != plb_check) {
+ t_rp_clk++;
+ }
+ switch ((unsigned long)t_rp_clk) {
+ case 0:
+ case 1:
+ case 2:
+ tr0 |= SDRAM_TR0_SDPA_2_CLK;
+ break;
+ case 3:
+ tr0 |= SDRAM_TR0_SDPA_3_CLK;
+ break;
+ default:
+ tr0 |= SDRAM_TR0_SDPA_4_CLK;
+ break;
+ }
+
+ /*
+ * Program SD_CTP field
+ */
+ t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
+ plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
+ if (sys_info.freqPLB != plb_check) {
+ t_ras_rcd_clk++;
+ }
+ switch (t_ras_rcd_clk) {
+ case 0:
+ case 1:
+ case 2:
+ tr0 |= SDRAM_TR0_SDCP_2_CLK;
+ break;
+ case 3:
+ tr0 |= SDRAM_TR0_SDCP_3_CLK;
+ break;
+ case 4:
+ tr0 |= SDRAM_TR0_SDCP_4_CLK;
+ break;
+ default:
+ tr0 |= SDRAM_TR0_SDCP_5_CLK;
+ break;
+ }
- break;
+ /*
+ * Program SD_LDF field
+ */
+ tr0 |= SDRAM_TR0_SDLD_2_CLK;
+
+ /*
+ * Program SD_RFTA field
+ * FIXME tRFC hardcoded as 75 nanoseconds
+ */
+ t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
+ residue = sys_info.freqPLB % (ONE_BILLION / 75);
+ if (residue >= (ONE_BILLION / 150)) {
+ t_rfc_clk++;
+ }
+ switch (t_rfc_clk) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ tr0 |= SDRAM_TR0_SDRA_6_CLK;
+ break;
+ case 7:
+ tr0 |= SDRAM_TR0_SDRA_7_CLK;
+ break;
+ case 8:
+ tr0 |= SDRAM_TR0_SDRA_8_CLK;
+ break;
+ case 9:
+ tr0 |= SDRAM_TR0_SDRA_9_CLK;
+ break;
+ case 10:
+ tr0 |= SDRAM_TR0_SDRA_10_CLK;
+ break;
+ case 11:
+ tr0 |= SDRAM_TR0_SDRA_11_CLK;
+ break;
+ case 12:
+ tr0 |= SDRAM_TR0_SDRA_12_CLK;
+ break;
+ default:
+ tr0 |= SDRAM_TR0_SDRA_13_CLK;
+ break;
+ }
+
+ /*
+ * Program SD_RCD field
+ */
+ t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
+ plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
+ if (sys_info.freqPLB != plb_check) {
+ t_rcd_clk++;
+ }
+ switch (t_rcd_clk) {
+ case 0:
+ case 1:
+ case 2:
+ tr0 |= SDRAM_TR0_SDRD_2_CLK;
+ break;
+ case 3:
+ tr0 |= SDRAM_TR0_SDRD_3_CLK;
+ break;
+ default:
+ tr0 |= SDRAM_TR0_SDRD_4_CLK;
+ break;
}
- }
-
- /*
- * Program SD_WR and SD_WCSBC fields
- */
- tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
- switch (wcsbc) {
- case 0:
- tr0 |= SDRAM_TR0_SDWD_0_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDWD_1_CLK;
- break;
- }
-
- /*
- * Program SD_CASL field
- */
- if ((cas_2_0_available == TRUE) &&
- (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
- }
- else if((cas_2_5_available == TRUE) &&
- (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
- }
- else if((cas_3_0_available == TRUE) &&
- (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
- }
- else {
- printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
- printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
- printf("Make sure the PLB speed is within the supported range.\n");
- hang();
- }
-
- /*
- * Calculate Trp in clock cycles and round up if necessary
- * Program SD_PTA field
- */
- t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
- plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
- if (sys_info.freqPLB != plb_check) {
- t_rp_clk++;
- }
- switch ((unsigned long)t_rp_clk) {
- case 0:
- case 1:
- case 2:
- tr0 |= SDRAM_TR0_SDPA_2_CLK;
- break;
- case 3:
- tr0 |= SDRAM_TR0_SDPA_3_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDPA_4_CLK;
- break;
- }
-
- /*
- * Program SD_CTP field
- */
- t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
- plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
- if (sys_info.freqPLB != plb_check) {
- t_ras_rcd_clk++;
- }
- switch (t_ras_rcd_clk) {
- case 0:
- case 1:
- case 2:
- tr0 |= SDRAM_TR0_SDCP_2_CLK;
- break;
- case 3:
- tr0 |= SDRAM_TR0_SDCP_3_CLK;
- break;
- case 4:
- tr0 |= SDRAM_TR0_SDCP_4_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDCP_5_CLK;
- break;
- }
-
- /*
- * Program SD_LDF field
- */
- tr0 |= SDRAM_TR0_SDLD_2_CLK;
-
- /*
- * Program SD_RFTA field
- * FIXME tRFC hardcoded as 75 nanoseconds
- */
- t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
- residue = sys_info.freqPLB % (ONE_BILLION / 75);
- if (residue >= (ONE_BILLION / 150)) {
- t_rfc_clk++;
- }
- switch (t_rfc_clk) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- tr0 |= SDRAM_TR0_SDRA_6_CLK;
- break;
- case 7:
- tr0 |= SDRAM_TR0_SDRA_7_CLK;
- break;
- case 8:
- tr0 |= SDRAM_TR0_SDRA_8_CLK;
- break;
- case 9:
- tr0 |= SDRAM_TR0_SDRA_9_CLK;
- break;
- case 10:
- tr0 |= SDRAM_TR0_SDRA_10_CLK;
- break;
- case 11:
- tr0 |= SDRAM_TR0_SDRA_11_CLK;
- break;
- case 12:
- tr0 |= SDRAM_TR0_SDRA_12_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDRA_13_CLK;
- break;
- }
-
- /*
- * Program SD_RCD field
- */
- t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
- plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
- if (sys_info.freqPLB != plb_check) {
- t_rcd_clk++;
- }
- switch (t_rcd_clk) {
- case 0:
- case 1:
- case 2:
- tr0 |= SDRAM_TR0_SDRD_2_CLK;
- break;
- case 3:
- tr0 |= SDRAM_TR0_SDRD_3_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDRD_4_CLK;
- break;
- }
#if 0
- printf("tr0: %x\n", tr0);
+ printf("tr0: %x\n", tr0);
#endif
- mtsdram(mem_tr0, tr0);
+ mtsdram(mem_tr0, tr0);
}
void program_tr1 (void)
{
- unsigned long tr0;
- unsigned long tr1;
- unsigned long cfg0;
- unsigned long ecc_temp;
- unsigned long dlycal;
- unsigned long dly_val;
- unsigned long i, j, k;
- unsigned long bxcr_num;
- unsigned long max_pass_length;
- unsigned long current_pass_length;
- unsigned long current_fail_length;
- unsigned long current_start;
- unsigned long rdclt;
- unsigned long rdclt_offset;
- long max_start;
- long max_end;
- long rdclt_average;
- unsigned char window_found;
- unsigned char fail_found;
- unsigned char pass_found;
- unsigned long * membase;
- PPC440_SYS_INFO sys_info;
-
- /*
- * get the board info
- */
- get_sys_info(&sys_info);
-
- /*
- * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
- */
- mfsdram(mem_tr1, tr1);
- tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
- SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
-
- mfsdram(mem_tr0, tr0);
- if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
- (sys_info.freqPLB > 100000000)) {
- tr1 |= SDRAM_TR1_RDSS_TR2;
- tr1 |= SDRAM_TR1_RDSL_STAGE3;
- tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
- }
- else {
- tr1 |= SDRAM_TR1_RDSS_TR1;
- tr1 |= SDRAM_TR1_RDSL_STAGE2;
- tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
- }
-
- /*
- * save CFG0 ECC setting to a temporary variable and turn ECC off
- */
- mfsdram(mem_cfg0, cfg0);
- ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
-
- /*
- * get the delay line calibration register value
- */
- mfsdram(mem_dlycal, dlycal);
- dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
-
- max_pass_length = 0;
- max_start = 0;
- max_end = 0;
- current_pass_length = 0;
- current_fail_length = 0;
- current_start = 0;
- rdclt_offset = 0;
- window_found = FALSE;
- fail_found = FALSE;
- pass_found = FALSE;
+ unsigned long tr0;
+ unsigned long tr1;
+ unsigned long cfg0;
+ unsigned long ecc_temp;
+ unsigned long dlycal;
+ unsigned long dly_val;
+ unsigned long i, j, k;
+ unsigned long bxcr_num;
+ unsigned long max_pass_length;
+ unsigned long current_pass_length;
+ unsigned long current_fail_length;
+ unsigned long current_start;
+ unsigned long rdclt;
+ unsigned long rdclt_offset;
+ long max_start;
+ long max_end;
+ long rdclt_average;
+ unsigned char window_found;
+ unsigned char fail_found;
+ unsigned char pass_found;
+ unsigned long * membase;
+ PPC440_SYS_INFO sys_info;
+
+ /*
+ * get the board info
+ */
+ get_sys_info(&sys_info);
+
+ /*
+ * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
+ */
+ mfsdram(mem_tr1, tr1);
+ tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
+ SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
+
+ mfsdram(mem_tr0, tr0);
+ if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
+ (sys_info.freqPLB > 100000000)) {
+ tr1 |= SDRAM_TR1_RDSS_TR2;
+ tr1 |= SDRAM_TR1_RDSL_STAGE3;
+ tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
+ } else {
+ tr1 |= SDRAM_TR1_RDSS_TR1;
+ tr1 |= SDRAM_TR1_RDSL_STAGE2;
+ tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
+ }
+
+ /*
+ * save CFG0 ECC setting to a temporary variable and turn ECC off
+ */
+ mfsdram(mem_cfg0, cfg0);
+ ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
+ mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
+
+ /*
+ * get the delay line calibration register value
+ */
+ mfsdram(mem_dlycal, dlycal);
+ dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
+
+ max_pass_length = 0;
+ max_start = 0;
+ max_end = 0;
+ current_pass_length = 0;
+ current_fail_length = 0;
+ current_start = 0;
+ rdclt_offset = 0;
+ window_found = FALSE;
+ fail_found = FALSE;
+ pass_found = FALSE;
#ifdef DEBUG
- printf("Starting memory test ");
+ printf("Starting memory test ");
#endif
- for (k = 0; k < NUMHALFCYCLES; k++) {
- for (rdclt = 0; rdclt < dly_val; rdclt++) {
- /*
- * Set the timing reg for the test.
- */
- mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
-
- for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
- if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
- /* Bank is enabled */
- membase = (unsigned long*)
- (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
-
- /*
- * Run the short memory test
- */
- for (i = 0; i < NUMMEMTESTS; i++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- membase[j] = test[i][j];
- ppcDcbf((unsigned long)&(membase[j]));
+ for (k = 0; k < NUMHALFCYCLES; k++) {
+ for (rdclt = 0; rdclt < dly_val; rdclt++) {
+ /*
+ * Set the timing reg for the test.
+ */
+ mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
+
+ for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
+ mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
+ if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
+ /* Bank is enabled */
+ membase = (unsigned long*)
+ (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
+
+ /*
+ * Run the short memory test
+ */
+ for (i = 0; i < NUMMEMTESTS; i++) {
+ for (j = 0; j < NUMMEMWORDS; j++) {
+ membase[j] = test[i][j];
+ ppcDcbf((unsigned long)&(membase[j]));
+ }
+
+ for (j = 0; j < NUMMEMWORDS; j++) {
+ if (membase[j] != test[i][j]) {
+ ppcDcbf((unsigned long)&(membase[j]));
+ break;
+ }
+ ppcDcbf((unsigned long)&(membase[j]));
+ }
+
+ if (j < NUMMEMWORDS) {
+ break;
+ }
+ }
+
+ /*
+ * see if the rdclt value passed
+ */
+ if (i < NUMMEMTESTS) {
+ break;
+ }
+ }
}
- for (j = 0; j < NUMMEMWORDS; j++) {
- if (membase[j] != test[i][j]) {
- ppcDcbf((unsigned long)&(membase[j]));
- break;
- }
- ppcDcbf((unsigned long)&(membase[j]));
- }
-
- if (j < NUMMEMWORDS) {
- break;
+ if (bxcr_num == MAXBXCR) {
+ if (fail_found == TRUE) {
+ pass_found = TRUE;
+ if (current_pass_length == 0) {
+ current_start = rdclt_offset + rdclt;
+ }
+
+ current_fail_length = 0;
+ current_pass_length++;
+
+ if (current_pass_length > max_pass_length) {
+ max_pass_length = current_pass_length;
+ max_start = current_start;
+ max_end = rdclt_offset + rdclt;
+ }
+ }
+ } else {
+ current_pass_length = 0;
+ current_fail_length++;
+
+ if (current_fail_length >= (dly_val>>2)) {
+ if (fail_found == FALSE) {
+ fail_found = TRUE;
+ } else if (pass_found == TRUE) {
+ window_found = TRUE;
+ break;
+ }
+ }
}
- }
-
- /*
- * see if the rdclt value passed
- */
- if (i < NUMMEMTESTS) {
- break;
- }
- }
- }
-
- if (bxcr_num == MAXBXCR) {
- if (fail_found == TRUE) {
- pass_found = TRUE;
- if (current_pass_length == 0) {
- current_start = rdclt_offset + rdclt;
- }
-
- current_fail_length = 0;
- current_pass_length++;
-
- if (current_pass_length > max_pass_length) {
- max_pass_length = current_pass_length;
- max_start = current_start;
- max_end = rdclt_offset + rdclt;
- }
}
- }
- else {
- current_pass_length = 0;
- current_fail_length++;
-
- if (current_fail_length >= (dly_val>>2)) {
- if (fail_found == FALSE) {
- fail_found = TRUE;
- }
- else if (pass_found == TRUE) {
- window_found = TRUE;
+#ifdef DEBUG
+ printf(".");
+#endif
+ if (window_found == TRUE) {
break;
- }
}
- }
+
+ tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
+ rdclt_offset += dly_val;
}
#ifdef DEBUG
- printf(".");
+ printf("\n");
#endif
- if (window_found == TRUE) {
- break;
+
+ /*
+ * make sure we find the window
+ */
+ if (window_found == FALSE) {
+ printf("ERROR: Cannot determine a common read delay.\n");
+ hang();
}
- tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
- rdclt_offset += dly_val;
- }
-#ifdef DEBUG
- printf("\n");
-#endif
+ /*
+ * restore the orignal ECC setting
+ */
+ mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
- /*
- * make sure we find the window
- */
- if (window_found == FALSE) {
- printf("ERROR: Cannot determine a common read delay.\n");
- hang();
- }
-
- /*
- * restore the orignal ECC setting
- */
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
-
- /*
- * set the SDRAM TR1 RDCD value
- */
- tr1 &= ~SDRAM_TR1_RDCD_MASK;
- if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
- tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
- }
- else {
- tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
- }
-
- /*
- * set the SDRAM TR1 RDCLT value
- */
- tr1 &= ~SDRAM_TR1_RDCT_MASK;
- while (max_end >= (dly_val<<1)) {
- max_end -= (dly_val<<1);
- max_start -= (dly_val<<1);
- }
-
- rdclt_average = ((max_start + max_end) >> 1);
- if (rdclt_average >= 0x60)
- while(1);
-
- if (rdclt_average < 0) {
- rdclt_average = 0;
- }
-
- if (rdclt_average >= dly_val) {
- rdclt_average -= dly_val;
- tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
- }
- tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
+ /*
+ * set the SDRAM TR1 RDCD value
+ */
+ tr1 &= ~SDRAM_TR1_RDCD_MASK;
+ if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
+ tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
+ } else {
+ tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
+ }
+
+ /*
+ * set the SDRAM TR1 RDCLT value
+ */
+ tr1 &= ~SDRAM_TR1_RDCT_MASK;
+ while (max_end >= (dly_val << 1)) {
+ max_end -= (dly_val << 1);
+ max_start -= (dly_val << 1);
+ }
+
+ rdclt_average = ((max_start + max_end) >> 1);
+ if (rdclt_average >= 0x60)
+ while (1)
+ ;
+
+ if (rdclt_average < 0) {
+ rdclt_average = 0;
+ }
+
+ if (rdclt_average >= dly_val) {
+ rdclt_average -= dly_val;
+ tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
+ }
+ tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
#if 0
- printf("tr1: %x\n", tr1);
+ printf("tr1: %x\n", tr1);
#endif
- /*
- * program SDRAM Timing Register 1 TR1
- */
- mtsdram(mem_tr1, tr1);
+ /*
+ * program SDRAM Timing Register 1 TR1
+ */
+ mtsdram(mem_tr1, tr1);
}
unsigned long program_bxcr(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- unsigned long dimm_num;
- unsigned long bxcr_num;
- unsigned long bank_base_addr;
- unsigned long bank_size_bytes;
- unsigned long cr;
- unsigned long i;
- unsigned long temp;
- unsigned char num_row_addr;
- unsigned char num_col_addr;
- unsigned char num_banks;
- unsigned char bank_size_id;
-
-
- /*
- * Set the BxCR regs. First, wipe out the bank config registers.
- */
- for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
- mtdcr(memcfgd, 0x00000000);
- }
-
- /*
- * reset the bank_base address
- */
- bank_base_addr = CFG_SDRAM_BASE;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
- num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
- num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
- bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
-
- /*
- * Set the SDRAM0_BxCR regs
- */
- cr = 0;
- bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
- switch (bank_size_id) {
- case 0x02:
- cr |= SDRAM_BXCR_SDSZ_8;
- break;
- case 0x04:
- cr |= SDRAM_BXCR_SDSZ_16;
- break;
- case 0x08:
- cr |= SDRAM_BXCR_SDSZ_32;
- break;
- case 0x10:
- cr |= SDRAM_BXCR_SDSZ_64;
- break;
- case 0x20:
- cr |= SDRAM_BXCR_SDSZ_128;
- break;
- case 0x40:
- cr |= SDRAM_BXCR_SDSZ_256;
- break;
- case 0x80:
- cr |= SDRAM_BXCR_SDSZ_512;
- break;
- default:
- printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
- dimm_num);
- printf("ERROR: Unsupported value for the banksize: %d.\n",
- bank_size_id);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
- }
+ unsigned long dimm_num;
+ unsigned long bank_base_addr;
+ unsigned long bank_size_bytes;
+ unsigned long cr;
+ unsigned long i;
+ unsigned long temp;
+ unsigned char num_row_addr;
+ unsigned char num_col_addr;
+ unsigned char num_banks;
+ unsigned char bank_size_id;
+
+#ifndef CONFIG_BAMBOO
+ unsigned long bxcr_num;
- switch (num_col_addr) {
- case 0x08:
- cr |= SDRAM_BXCR_SDAM_1;
- break;
- case 0x09:
- cr |= SDRAM_BXCR_SDAM_2;
- break;
- case 0x0A:
- cr |= SDRAM_BXCR_SDAM_3;
- break;
- case 0x0B:
- cr |= SDRAM_BXCR_SDAM_4;
- break;
- default:
- printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
- dimm_num);
- printf("ERROR: Unsupported value for number of "
- "column addresses: %d.\n", num_col_addr);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
- }
-
- /*
- * enable the bank
- */
- cr |= SDRAM_BXCR_SDBE;
-
- /*------------------------------------------------------------------
- | This next section is hardware dependent and must be programmed
- | to match the hardware.
- +-----------------------------------------------------------------*/
- if (dimm_num == 0) {
- for (i = 0; i < num_banks; i++) {
- mtdcr(memcfga, mem_b0cr + (i << 2));
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
- }
- }
- else {
- for (i = 0; i < num_banks; i++) {
- mtdcr(memcfga, mem_b2cr + (i << 2));
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
+ /*
+ * Set the BxCR regs. First, wipe out the bank config registers.
+ */
+ for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
+ mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
+ mtdcr(memcfgd, 0x00000000);
+ }
+#endif
+
+ /*
+ * reset the bank_base address
+ */
+#ifndef CONFIG_BAMBOO
+ bank_base_addr = CFG_SDRAM_BASE;
+#else
+ bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
+#endif
+
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_populated[dimm_num] == TRUE) {
+ num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
+ num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
+ num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
+ bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
+
+ /*
+ * Set the SDRAM0_BxCR regs
+ */
+ cr = 0;
+ bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
+ switch (bank_size_id) {
+ case 0x02:
+ cr |= SDRAM_BXCR_SDSZ_8;
+ break;
+ case 0x04:
+ cr |= SDRAM_BXCR_SDSZ_16;
+ break;
+ case 0x08:
+ cr |= SDRAM_BXCR_SDSZ_32;
+ break;
+ case 0x10:
+ cr |= SDRAM_BXCR_SDSZ_64;
+ break;
+ case 0x20:
+ cr |= SDRAM_BXCR_SDSZ_128;
+ break;
+ case 0x40:
+ cr |= SDRAM_BXCR_SDSZ_256;
+ break;
+ case 0x80:
+ cr |= SDRAM_BXCR_SDSZ_512;
+ break;
+ default:
+ printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
+ dimm_num);
+ printf("ERROR: Unsupported value for the banksize: %d.\n",
+ bank_size_id);
+ printf("Replace the DIMM module with a supported DIMM.\n\n");
+ hang();
+ }
+
+ switch (num_col_addr) {
+ case 0x08:
+ cr |= SDRAM_BXCR_SDAM_1;
+ break;
+ case 0x09:
+ cr |= SDRAM_BXCR_SDAM_2;
+ break;
+ case 0x0A:
+ cr |= SDRAM_BXCR_SDAM_3;
+ break;
+ case 0x0B:
+ cr |= SDRAM_BXCR_SDAM_4;
+ break;
+ default:
+ printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
+ dimm_num);
+ printf("ERROR: Unsupported value for number of "
+ "column addresses: %d.\n", num_col_addr);
+ printf("Replace the DIMM module with a supported DIMM.\n\n");
+ hang();
+ }
+
+ /*
+ * enable the bank
+ */
+ cr |= SDRAM_BXCR_SDBE;
+
+ /*------------------------------------------------------------------
+ | This next section is hardware dependent and must be programmed
+ | to match the hardware.
+ +-----------------------------------------------------------------*/
+ if (dimm_num == 0) {
+ for (i = 0; i < num_banks; i++) {
+#ifndef CONFIG_BAMBOO
+ mtdcr(memcfga, mem_b0cr + (i << 2));
+#else
+ mtdcr(memcfga, mem_b1cr + (i << 2));
+#endif
+ temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
+ SDRAM_BXCR_SDSZ_MASK |
+ SDRAM_BXCR_SDAM_MASK |
+ SDRAM_BXCR_SDBE);
+ cr |= temp;
+ cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
+ mtdcr(memcfgd, cr);
+ bank_base_addr += bank_size_bytes;
+ }
+ } else {
+ for (i = 0; i < num_banks; i++) {
+#ifndef CONFIG_BAMBOO
+ mtdcr(memcfga, mem_b2cr + (i << 2));
+#else
+ mtdcr(memcfga, mem_b3cr + (i << 2));
+#endif
+ temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
+ SDRAM_BXCR_SDSZ_MASK |
+ SDRAM_BXCR_SDAM_MASK |
+ SDRAM_BXCR_SDBE);
+ cr |= temp;
+ cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
+ mtdcr(memcfgd, cr);
+ bank_base_addr += bank_size_bytes;
+ }
+ }
}
- }
}
- }
- return(bank_base_addr);
+ return(bank_base_addr);
}
void program_ecc (unsigned long num_bytes)
{
- unsigned long bank_base_addr;
- unsigned long current_address;
- unsigned long end_address;
- unsigned long address_increment;
- unsigned long cfg0;
-
- /*
- * get Memory Controller Options 0 data
- */
- mfsdram(mem_cfg0, cfg0);
-
- /*
- * reset the bank_base address
- */
- bank_base_addr = CFG_SDRAM_BASE;
-
- if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
- SDRAM_CFG0_MCHK_GEN);
-
- if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
- address_increment = 4;
- }
- else {
- address_increment = 8;
- }
+ unsigned long bank_base_addr;
+ unsigned long current_address;
+ unsigned long end_address;
+ unsigned long address_increment;
+ unsigned long cfg0;
+
+ /*
+ * get Memory Controller Options 0 data
+ */
+ mfsdram(mem_cfg0, cfg0);
- current_address = (unsigned long)(bank_base_addr);
- end_address = (unsigned long)(bank_base_addr) + num_bytes;
+ /*
+ * reset the bank_base address
+ */
+ bank_base_addr = CFG_SDRAM_BASE;
- while (current_address < end_address) {
- *((unsigned long*)current_address) = 0x00000000;
- current_address += address_increment;
- }
+ if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
+ mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
+ SDRAM_CFG0_MCHK_GEN);
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
- SDRAM_CFG0_MCHK_CHK);
- }
+ if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
+ address_increment = 4;
+ } else {
+ address_increment = 8;
+ }
+
+ current_address = (unsigned long)(bank_base_addr);
+ end_address = (unsigned long)(bank_base_addr) + num_bytes;
+
+ while (current_address < end_address) {
+ *((unsigned long*)current_address) = 0x00000000;
+ current_address += address_increment;
+ }
+
+ mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
+ SDRAM_CFG0_MCHK_CHK);
+ }
}
#endif /* CONFIG_440 */
#elif defined(CONFIG_440)
-#if !defined(CONFIG_440_GX)
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+void get_sys_info (sys_info_t *sysInfo)
+{
+ unsigned long temp;
+ unsigned long reg;
+ unsigned long lfdiv;
+ unsigned long m;
+ unsigned long prbdv0;
+ /*
+ WARNING: ASSUMES the following:
+ ENG=1
+ PRADV0=1
+ PRBDV0=1
+ */
+
+ /* Decode CPR0_PLLD0 for divisors */
+ mfclk(clk_plld, reg);
+ temp = (reg & PLLD_FWDVA_MASK) >> 16;
+ sysInfo->pllFwdDivA = temp ? temp : 16;
+ temp = (reg & PLLD_FWDVB_MASK) >> 8;
+ sysInfo->pllFwdDivB = temp ? temp: 8 ;
+ temp = (reg & PLLD_FBDV_MASK) >> 24;
+ sysInfo->pllFbkDiv = temp ? temp : 32;
+ lfdiv = reg & PLLD_LFBDV_MASK;
+
+ mfclk(clk_opbd, reg);
+ temp = (reg & OPBDDV_MASK) >> 24;
+ sysInfo->pllOpbDiv = temp ? temp : 4;
+
+ mfclk(clk_perd, reg);
+ temp = (reg & PERDV_MASK) >> 24;
+ sysInfo->pllExtBusDiv = temp ? temp : 8;
+
+ mfclk(clk_primbd, reg);
+ temp = (reg & PRBDV_MASK) >> 24;
+ prbdv0 = temp ? temp : 8;
+
+ mfclk(clk_spcid, reg);
+ temp = (reg & SPCID_MASK) >> 24;
+ sysInfo->pllPciDiv = temp ? temp : 4;
+
+ /* Calculate 'M' based on feedback source */
+ mfsdr(sdr_sdstp0, reg);
+ temp = (reg & PLLSYS0_SEL_MASK) >> 27;
+ if (temp == 0) { /* PLL output */
+ /* Figure which pll to use */
+ mfclk(clk_pllc, reg);
+ temp = (reg & PLLC_SRC_MASK) >> 29;
+ if (!temp) /* PLLOUTA */
+ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
+ else /* PLLOUTB */
+ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
+ }
+ else if (temp == 1) /* CPU output */
+ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
+ else /* PerClk */
+ m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
+
+ /* Now calculate the individual clocks */
+ sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+ sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
+ sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
+ sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
+ sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
+ sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
+
+ /* Figure which timer source to use */
+ if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
+ temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */
+ if (CONFIG_SYS_CLK_FREQ > temp)
+ sysInfo->freqTmrClk = temp;
+ else
+ sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ;
+ }
+ else /* Internal clock */
+ sysInfo->freqTmrClk = sysInfo->freqProcessor;
+}
+/********************************************
+ * get_PCI_freq
+ * return PCI bus freq in Hz
+ *********************************************/
+ulong get_PCI_freq (void)
+{
+ sys_info_t sys_info;
+ get_sys_info (&sys_info);
+ return sys_info.freqPCI;
+}
+
+#elif !defined(CONFIG_440GX)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
- if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
- sysInfo->freqPLB >>= 1;
+ if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
+ sysInfo->freqPLB >>= 1;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
/*----------------------------------------------------------------*/
- iccci r0,r0 /* NOTE: operands not used for 440 */
- dccci r0,r0 /* NOTE: operands not used for 440 */
+ iccci r0,r0 /* NOTE: operands not used for 440 */
+ dccci r0,r0 /* NOTE: operands not used for 440 */
sync
li r0,0
mtspr srr0,r0
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
-#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
- mtspr mcsrr0,r0
- mtspr mcsrr1,r0
- mfspr r1, mcsr
- mtspr mcsr,r1
+#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */
+ mtspr mcsrr0,r0
+ mtspr mcsrr1,r0
+ mfspr r1, mcsr
+ mtspr mcsr,r1
#endif
/*----------------------------------------------------------------*/
/* Initialize debug */
/* Setup interrupt vectors */
/*----------------------------------------------------------------*/
mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
- li r1,0x0100
+ li r1,0x0100
mtspr ivor0,r1 /* Critical input */
- li r1,0x0200
+ li r1,0x0200
mtspr ivor1,r1 /* Machine check */
- li r1,0x0300
+ li r1,0x0300
mtspr ivor2,r1 /* Data storage */
- li r1,0x0400
+ li r1,0x0400
mtspr ivor3,r1 /* Instruction storage */
li r1,0x0500
mtspr ivor4,r1 /* External interrupt */
mtspr tcr,r0 /* disable all */
mtspr esr,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
-#if !defined(CONFIG_440_GX)
+#if !defined(CONFIG_440GX)
lis r1,0x0002 /* set CE bit (Critical Exceptions) */
ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
mtmsr r1 /* change MSR */
-#else
+#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
bl __440gx_msr_set
b __440gx_msr_continue
__440gx_msr_set:
- lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
- ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
+ lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
+ ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
mtspr srr1,r1
mflr r1
mtspr srr0,r1
/* Setup the internal SRAM */
/*----------------------------------------------------------------*/
li r0,0
-#if defined (CONFIG_440_GX)
- mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ /* Clear Dcache to use as RAM */
+ addis r3,r0,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ addis r4,r0,CFG_INIT_RAM_END@h
+ ori r4,r4,CFG_INIT_RAM_END@l
+ rlwinm. r5,r4,0,27,31
+ rlwinm r5,r4,27,5,31
+ beq ..d_ran
+ addi r5,r5,0x0001
+..d_ran:
+ mtctr r5
+..d_ag:
+ dcbz r0,r3
+ addi r3,r3,32
+ bdnz ..d_ag
+#else
+#if defined (CONFIG_440GX)
+ mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
ori r1,r1,0x0980 /* first 64k */
- mtdcr isram0_sb0cr,r1
+ mtdcr isram0_sb0cr,r1
lis r1,0x8001
ori r1,r1,0x0980 /* second 64k */
- mtdcr isram0_sb1cr,r1
+ mtdcr isram0_sb1cr,r1
lis r1, 0x8002
ori r1,r1, 0x0980 /* third 64k */
- mtdcr isram0_sb2cr,r1
+ mtdcr isram0_sb2cr,r1
lis r1, 0x8003
ori r1,r1, 0x0980 /* fourth 64k */
- mtdcr isram0_sb3cr,r1
+ mtdcr isram0_sb3cr,r1
#else
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
#endif
+#endif
/*----------------------------------------------------------------*/
/* Setup the stack in internal SRAM */
/*----------------------------------------------------------------------- */
/* DMA Status, clear to come up clean */
/*----------------------------------------------------------------------- */
- addis r3,r0, 0xFFFF /* Clear all existing DMA status */
- ori r3,r3, 0xFFFF
- mtdcr dmasr, r3
+ addis r3,r0, 0xFFFF /* Clear all existing DMA status */
+ ori r3,r3, 0xFFFF
+ mtdcr dmasr, r3
- bl ppc405ep_init /* do ppc405ep specific init */
+ bl ppc405ep_init /* do ppc405ep specific init */
#endif /* CONFIG_405EP */
#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
/* Setup OCM */
lis r0, 0x7FFF
ori r0, r0, 0xFFFF
- mfdcr r3, ocmiscntl /* get instr-side IRAM config */
+ mfdcr r3, ocmiscntl /* get instr-side IRAM config */
mfdcr r4, ocmdscntl /* get data-side IRAM config */
and r3, r3, r0 /* disable data-side IRAM */
and r4, r4, r0 /* disable data-side IRAM */
/* set stack pointer and clear stack to known value */
lis r1,CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET@l
+ ori r1,r1,CFG_INIT_SP_OFFSET@l
li r4,2048 /* we store 2048 words to stack */
mtctr r4
lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
- ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
+ ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
lis r4,0xdead /* we store 0xdeaddead in the stack */
ori r4,r4,0xdead
#endif /* CFG_INIT_DCACHE_CS */
/*----------------------------------------------------------------------- */
- /* Initialize SDRAM Controller */
+ /* Initialize SDRAM Controller */
/*----------------------------------------------------------------------- */
bl sdram_init
ori r0, r0, RESET_VECTOR@l
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save return addr (underflow vect) */
-#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
+#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
GET_GOT /* initialize GOT access */
- bl cpu_init_f /* run low-level CPU init code (from Flash) */
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
/* NEVER RETURNS! */
bl board_init_f /* run first part of init code (from Flash) */
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
-#if defined(CONFIG_440_GX)
- lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
- ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
+ ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
#else
addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
#endif
mtdccr r10
/* do loop for # of congruence classes. */
-#if defined(CONFIG_440_GX)
- lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
- ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
- lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
- ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
+ ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+ lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
+ ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
#else
addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
#endif
mtctr r10
- addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
+ addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
..flush_dcache_loop:
lwz r3,0(r10) /* least recently used side */
*/
.globl relocate_code
relocate_code:
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ dccci 0,0 /* Invalidate data cache, now no longer our stack */
+ sync
+ addi r1,r0,0x0000 /* Tlb entry #0 */
+ tlbre r0,r1,0x0002 /* Read contents */
+ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
+ tlbwe r0,r1,0x0002 /* Save it out */
+ isync
+#endif
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Init Data pointer */
mr r10, r5 /* Save copy of Destination Address */
/**************************************************************************/
-/* PPC405EP specific stuff */
+/* PPC405EP specific stuff */
/**************************************************************************/
#ifdef CONFIG_405EP
ppc405ep_init:
-#ifdef CONFIG_BUBINGA405EP
+#ifdef CONFIG_BUBINGA
/*
* Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
* function) to support FPGA and NVRAM accesses below.
mtdcr ebccfgd,r3
#endif
- addi r3,0,CPC0_PCI_HOST_CFG_EN
-#ifdef CONFIG_BUBINGA405EP
+ addi r3,0,CPC0_PCI_HOST_CFG_EN
+#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Check FPGA for PCI internal/external arbitration
! If board is set to internal arbitration, update cpc0_pci
!-----------------------------------------------------------------------
*/
- addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
- ori r5,r5,FPGA_REG1@l
- lbz r5,0x0(r5) /* read to get PCI arb selection */
- andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
- beq ..pci_cfg_set /* if not set, then bypass reg write*/
+ addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
+ ori r5,r5,FPGA_REG1@l
+ lbz r5,0x0(r5) /* read to get PCI arb selection */
+ andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
+ beq ..pci_cfg_set /* if not set, then bypass reg write*/
#endif
- ori r3,r3,CPC0_PCI_ARBIT_EN
+ ori r3,r3,CPC0_PCI_ARBIT_EN
..pci_cfg_set:
- mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
+ mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
/*
!-----------------------------------------------------------------------
! Check to see if chip is in bypass mode.
! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
! CPU reset Otherwise, skip this step and keep going.
- ! Note: Running BIOS in bypass mode is not supported since PLB speed
- ! will not be fast enough for the SDRAM (min 66MHz)
+ ! Note: Running BIOS in bypass mode is not supported since PLB speed
+ ! will not be fast enough for the SDRAM (min 66MHz)
!-----------------------------------------------------------------------
*/
- mfdcr r5, CPC0_PLLMR1
- rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
- cmpi cr0,0,r4,0x1
+ mfdcr r5, CPC0_PLLMR1
+ rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
+ cmpi cr0,0,r4,0x1
- beq pll_done /* if SSCS =b'1' then PLL has */
+ beq pll_done /* if SSCS =b'1' then PLL has */
/* already been set */
/* and CPU has been reset */
/* so skip to next section */
-#ifdef CONFIG_BUBINGA405EP
+#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Read NVRAM to get value to write in PLLMR.
! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
!
! WARNING: This code assumes the first three words in the nvram_t
- ! structure in openbios.h. Changing the beginning of
- ! the structure will break this code.
+ ! structure in openbios.h. Changing the beginning of
+ ! the structure will break this code.
!
!-----------------------------------------------------------------------
*/
- addis r3,0,NVRAM_BASE@h
- addi r3,r3,NVRAM_BASE@l
-
- lwz r4, 0(r3)
- addis r5,0,NVRVFY1@h
- addi r5,r5,NVRVFY1@l
- cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
- bne ..no_pllset
- addi r3,r3,4
- lwz r4, 0(r3)
- addis r5,0,NVRVFY2@h
- addi r5,r5,NVRVFY2@l
- cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
- bne ..no_pllset
- addi r3,r3,8 /* Skip over conf_size */
- lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
- lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
- rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
- cmpi cr0,0,r5,1 /* See if PLL is locked */
- beq pll_write
+ addis r3,0,NVRAM_BASE@h
+ addi r3,r3,NVRAM_BASE@l
+
+ lwz r4, 0(r3)
+ addis r5,0,NVRVFY1@h
+ addi r5,r5,NVRVFY1@l
+ cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
+ bne ..no_pllset
+ addi r3,r3,4
+ lwz r4, 0(r3)
+ addis r5,0,NVRVFY2@h
+ addi r5,r5,NVRVFY2@l
+ cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
+ bne ..no_pllset
+ addi r3,r3,8 /* Skip over conf_size */
+ lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
+ lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
+ rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
+ cmpi cr0,0,r5,1 /* See if PLL is locked */
+ beq pll_write
..no_pllset:
-#endif /* CONFIG_BUBINGA405EP */
+#endif /* CONFIG_BUBINGA */
- addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
- ori r3,r3,PLLMR0_DEFAULT@l /* */
- addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
- ori r4,r4,PLLMR1_DEFAULT@l /* */
+ addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
+ ori r3,r3,PLLMR0_DEFAULT@l /* */
+ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
+ ori r4,r4,PLLMR1_DEFAULT@l /* */
- b pll_write /* Write the CPC0_PLLMR with new value */
+ b pll_write /* Write the CPC0_PLLMR with new value */
pll_done:
/*
! This is needed to enable PCI if not booting from serial EPROM
!-----------------------------------------------------------------------
*/
- addi r3, 0, 0x0
- mtdcr CPC0_SRR, r3
+ addi r3, 0, 0x0
+ mtdcr CPC0_SRR, r3
- addis r3,0,0x0010
- mtctr r3
+ addis r3,0,0x0010
+ mtctr r3
pci_wait:
- bdnz pci_wait
+ bdnz pci_wait
blr /* return to main code */
/*
!-----------------------------------------------------------------------------
-! Function: pll_write
-! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
-! That is:
-! 1. Pll is first disabled (de-activated by putting in bypass mode)
-! 2. PLL is reset
-! 3. Clock dividers are set while PLL is held in reset and bypassed
-! 4. PLL Reset is cleared
-! 5. Wait 100us for PLL to lock
-! 6. A core reset is performed
+! Function: pll_write
+! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
+! That is:
+! 1. Pll is first disabled (de-activated by putting in bypass mode)
+! 2. PLL is reset
+! 3. Clock dividers are set while PLL is held in reset and bypassed
+! 4. PLL Reset is cleared
+! 5. Wait 100us for PLL to lock
+! 6. A core reset is performed
! Input: r3 = Value to write to CPC0_PLLMR0
! Input: r4 = Value to write to CPC0_PLLMR1
! Output r3 = none
pll_write:
mfdcr r5, CPC0_UCR
andis. r5,r5,0xFFFF
- ori r5,r5,0x0101 /* Stop the UART clocks */
- mtdcr CPC0_UCR,r5 /* Before changing PLL */
+ ori r5,r5,0x0101 /* Stop the UART clocks */
+ mtdcr CPC0_UCR,r5 /* Before changing PLL */
mfdcr r5, CPC0_PLLMR1
- rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
- mtdcr CPC0_PLLMR1,r5
- oris r5,r5,0x4000 /* Set PLL Reset */
- mtdcr CPC0_PLLMR1,r5
-
- mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
- rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
- oris r5,r5,0x4000 /* Set PLL Reset */
- mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
- rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
- mtdcr CPC0_PLLMR1,r5
+ rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
+ mtdcr CPC0_PLLMR1,r5
+ oris r5,r5,0x4000 /* Set PLL Reset */
+ mtdcr CPC0_PLLMR1,r5
+
+ mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
+ rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
+ oris r5,r5,0x4000 /* Set PLL Reset */
+ mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
+ rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
+ mtdcr CPC0_PLLMR1,r5
/*
! Wait min of 100us for PLL to lock.
! See CMOS 27E databook for more info.
! At 200MHz, that means waiting 20,000 instructions
*/
- addi r3,0,20000 /* 2000 = 0x4e20 */
- mtctr r3
+ addi r3,0,20000 /* 2000 = 0x4e20 */
+ mtctr r3
pll_wait:
- bdnz pll_wait
+ bdnz pll_wait
- oris r5,r5,0x8000 /* Enable PLL */
- mtdcr CPC0_PLLMR1,r5 /* Engage */
+ oris r5,r5,0x8000 /* Enable PLL */
+ mtdcr CPC0_PLLMR1,r5 /* Engage */
/*
* Reset CPU to guarantee timings are OK
* Not sure if this is needed...
*/
addis r3,0,0x1000
- mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
+ mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
/* execution will continue from the poweron */
/* vector of 0xfffffffc */
#endif /* CONFIG_405EP */
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP.
+ *
+ * (C) Copyright 2003-2004
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
+ *
+ * Note: Much of this code has been derived from Linux 2.4
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - this driver is intended for use with USB Mass Storage Devices
+ * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_USB_OHCI
+
+#include <malloc.h>
+#include <usb.h>
+#include "usb_ohci.h"
+
+#include "usbdev.h"
+
+#define OHCI_USE_NPS /* force NoPowerSwitching mode */
+#undef OHCI_VERBOSE_DEBUG /* not always helpful */
+#undef DEBUG
+#undef SHOW_INFO
+#undef OHCI_FILL_TRACE
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+#define readl(a) (*((vu_long *)(a)))
+#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+
+#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#define m16_swap(x) swap_16(x)
+#define m32_swap(x) swap_32(x)
+
+#ifdef CONFIG_440EP
+#define ohci_cpu_to_le16(x) (x)
+#define ohci_cpu_to_le32(x) (x)
+#else
+#define ohci_cpu_to_le16(x) swap_16(x)
+#define ohci_cpu_to_le32(x) swap_32(x)
+#endif
+
+/* global ohci_t */
+static ohci_t gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* urb_priv */
+urb_priv_t urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+/* flag guarding URB transation */
+int urb_finished = 0;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect. AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+ u32 temp = readl (&hc->regs->roothub.register); \
+ if (hc->flags & OHCI_QUIRK_AMD756) \
+ while (temp & mask) \
+ temp = readl (&hc->regs->roothub.register); \
+ temp; })
+
+static u32 roothub_a (struct ohci *hc)
+ { return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_b (struct ohci *hc)
+ { return readl (&hc->regs->roothub.b); }
+static inline u32 roothub_status (struct ohci *hc)
+ { return readl (&hc->regs->roothub.status); }
+static u32 roothub_portstatus (struct ohci *hc, int i)
+ { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+
+/* forward declaration */
+static int hc_interrupt (void);
+static void
+td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv (urb_priv_t * urb)
+{
+ int i;
+ int last;
+ struct td * td;
+
+ last = urb->length - 1;
+ if (last >= 0) {
+ for (i = 0; i <= last; i++) {
+ td = urb->td[i];
+ if (td) {
+ td->usb_dev = NULL;
+ urb->td[i] = NULL;
+ }
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number (struct usb_device * dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, char * str, int small)
+{
+ urb_priv_t * purb = &urb_priv;
+
+ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+ str,
+ sohci_get_current_frame_number (dev),
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout (pipe)? 'O': 'I',
+ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+ (usb_pipecontrol (pipe)? "CTRL": "BULK"),
+ purb->actual_length,
+ transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol (pipe)) {
+ printf (__FILE__ ": cmd(8):");
+ for (i = 0; i < 8 ; i++)
+ printf (" %02x", ((__u8 *) setup) [i]);
+ printf ("\n");
+ }
+ if (transfer_len > 0 && buffer) {
+ printf (__FILE__ ": data(%d/%d):",
+ purb->actual_length,
+ transfer_len);
+ len = usb_pipeout (pipe)?
+ transfer_len: purb->actual_length;
+ for (i = 0; i < 16 && i < len; i++)
+ printf (" %02x", ((__u8 *) buffer) [i]);
+ printf ("%s\n", i < len? "...": "");
+ }
+ }
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
+void ep_print_int_eds (ohci_t *ohci, char * str) {
+ int i, j;
+ __u32 * ed_p;
+ for (i= 0; i < 32; i++) {
+ j = 5;
+ ed_p = &(ohci->hcca->int_table [i]);
+ if (*ed_p == 0)
+ continue;
+ printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ while (*ed_p != 0 && j--) {
+ ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
+ printf (" ed: %4x;", ed->hwINFO);
+ ed_p = &ed->hwNextED;
+ }
+ printf ("\n");
+ }
+}
+
+static void ohci_dump_intr_mask (char *label, __u32 mask)
+{
+ dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : ""
+ );
+}
+
+static void maybe_print_eds (char *label, __u32 value)
+{
+ ed_t *edp = (ed_t *)value;
+
+ if (value) {
+ dbg ("%s %08x", label, value);
+ dbg ("%08x", edp->hwINFO);
+ dbg ("%08x", edp->hwTailP);
+ dbg ("%08x", edp->hwHeadP);
+ dbg ("%08x", edp->hwNextED);
+ }
+}
+
+static char * hcfs2string (int state)
+{
+ switch (state) {
+ case OHCI_USB_RESET: return "reset";
+ case OHCI_USB_RESUME: return "resume";
+ case OHCI_USB_OPER: return "operational";
+ case OHCI_USB_SUSPEND: return "suspend";
+ }
+ return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status (ohci_t *controller)
+{
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
+
+ temp = readl (®s->revision) & 0xff;
+ if (temp != 0x10)
+ dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl (®s->control);
+ dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string (temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "",
+ temp & OHCI_CTRL_CBSR
+ );
+
+ temp = readl (®s->cmdstatus);
+ dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "",
+ (temp & OHCI_HCR) ? " HCR" : ""
+ );
+
+ ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
+ ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
+
+ maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
+
+ maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
+ maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
+
+ maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
+ maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
+
+ maybe_print_eds ("donehead", readl (®s->donehead));
+}
+
+static void ohci_dump_roothub (ohci_t *controller, int verbose)
+{
+ __u32 temp, ndp, i;
+
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+
+ if (verbose) {
+ dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "",
+ ndp
+ );
+ temp = roothub_b (controller);
+ dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp,
+ (temp & RH_B_PPCM) >> 16,
+ (temp & RH_B_DR)
+ );
+ temp = roothub_status (controller);
+ dbg ("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : ""
+ );
+ }
+
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : ""
+ );
+ }
+}
+
+static void ohci_dump (ohci_t *controller, int verbose)
+{
+ dbg ("OHCI controller usb-%s state", controller->slot_name);
+
+ /* dumps some of the state we know about */
+ ohci_dump_status (controller);
+ if (verbose)
+ ep_print_int_eds (controller, "hcca");
+ dbg ("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub (controller, 1);
+}
+
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ ohci_t *ohci;
+ ed_t * ed;
+ urb_priv_t *purb_priv;
+ int i, size = 0;
+
+ ohci = &gohci;
+
+ /* when controller's hung, permit only roothub cleanup attempts
+ * such as powering down ports */
+ if (ohci->disabled) {
+ err("sohci_submit_job: EPIPE");
+ return -1;
+ }
+
+ /* if we have an unfinished URB from previous transaction let's
+ * fail and scream as quickly as possible so as not to corrupt
+ * further communication */
+ if (!urb_finished) {
+ err("sohci_submit_job: URB NOT FINISHED");
+ return -1;
+ }
+ /* we're about to begin a new transaction here so mark the URB unfinished */
+ urb_finished = 0;
+
+ /* every endpoint has a ed, locate and fill it */
+ if (!(ed = ep_add_ed (dev, pipe))) {
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+
+ /* for the private part of the URB we need the number of TDs (size) */
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK: /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0)? 2:
+ (transfer_len - 1) / 4096 + 3;
+ break;
+ }
+
+ if (size >= (N_URB_TD - 1)) {
+ err("need %d TDs, only have %d", size, N_URB_TD);
+ return -1;
+ }
+ purb_priv = &urb_priv;
+ purb_priv->pipe = pipe;
+
+ /* fill the private part of the URB */
+ purb_priv->length = size;
+ purb_priv->ed = ed;
+ purb_priv->actual_length = 0;
+
+ /* allocate the TDs */
+ /* note that td[0] was allocated in ep_add_ed */
+ for (i = 0; i < size; i++) {
+ purb_priv->td[i] = td_alloc (dev);
+ if (!purb_priv->td[i]) {
+ purb_priv->length = i;
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+ }
+
+ if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: EINVAL");
+ return -1;
+ }
+
+ /* link the ed into a chain if is not already */
+ if (ed->state != ED_OPER)
+ ep_link (ohci, ed);
+
+ /* fill the TDs and link it to the ed */
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+{
+ ohci_t *ohci = &gohci;
+
+ return ohci_cpu_to_le16 (ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link (ohci_t *ohci, ed_t *edi)
+{
+ volatile ed_t *ed = edi;
+
+ ed->state = ED_OPER;
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ ed->hwNextED = 0;
+ if (ohci->ed_controltail == NULL) {
+ writel (ed, &ohci->regs->ed_controlhead);
+ } else {
+ ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
+ }
+ ed->ed_prev = ohci->ed_controltail;
+ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_controltail = edi;
+ break;
+
+ case PIPE_BULK:
+ ed->hwNextED = 0;
+ if (ohci->ed_bulktail == NULL) {
+ writel (ed, &ohci->regs->ed_bulkhead);
+ } else {
+ ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
+ }
+ ed->ed_prev = ohci->ed_bulktail;
+ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_bulktail = edi;
+ break;
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink (ohci_t *ohci, ed_t *edi)
+{
+ volatile ed_t *ed = edi;
+
+ ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_controltail == ed) {
+ ohci->ed_controltail = ed->ed_prev;
+ } else {
+ ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+
+ case PIPE_BULK:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_bulktail == ed) {
+ ohci->ed_bulktail = ed->ed_prev;
+ } else {
+ ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+ }
+ ed->state = ED_UNLINK;
+ return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
+ * but the USB stack is a little bit stateless so we do it at every transaction
+ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
+ * in all other cases the state is left unchanged
+ * the ed info fields are setted anyway even though most of them should not change */
+
+static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+{
+ td_t *td;
+ ed_t *ed_ret;
+ volatile ed_t *ed;
+
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
+ (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+
+ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+ err("ep_add_ed: pending delete");
+ /* pending delete request */
+ return NULL;
+ }
+
+ if (ed->state == ED_NEW) {
+ ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
+ /* dummy td; end of td list for ed */
+ td = td_alloc (usb_dev);
+ ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
+ ed->hwHeadP = ed->hwTailP;
+ ed->state = ED_UNLINK;
+ ed->type = usb_pipetype (pipe);
+ ohci_dev.ed_cnt++;
+ }
+
+ ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
+ | usb_pipeendpoint (pipe) << 7
+ | (usb_pipeisoc (pipe)? 0x8000: 0)
+ | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
+ | usb_pipeslow (pipe) << 13
+ | usb_maxpacket (usb_dev, pipe) << 16);
+
+ return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill (ohci_t *ohci, unsigned int info,
+ void *data, int len,
+ struct usb_device *dev, int index, urb_priv_t *urb_priv)
+{
+ volatile td_t *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+ int i;
+#endif
+
+ if (index > urb_priv->length) {
+ err("index > length");
+ return;
+ }
+ /* use this td as the next dummy */
+ td_pt = urb_priv->td [index];
+ td_pt->hwNextTD = 0;
+
+ /* fill the old dummy TD */
+ td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
+
+ td->ed = urb_priv->ed;
+ td->next_dl_td = NULL;
+ td->index = index;
+ td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+ if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+ for (i = 0; i < len; i++)
+ printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
+ printf("\n");
+ }
+#endif
+ if (!len)
+ data = 0;
+
+ td->hwINFO = ohci_cpu_to_le32 (info);
+ td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
+ if (data)
+ td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
+ else
+ td->hwBE = 0;
+ td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
+
+ /* append to queue */
+ td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+ ohci_t *ohci = &gohci;
+ int data_len = transfer_len;
+ void *data;
+ int cnt = 0;
+ __u32 info = 0;
+ unsigned int toggle = 0;
+
+ /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ toggle = TD_T_TOGGLE;
+ } else {
+ toggle = TD_T_DATA0;
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+ }
+ urb->td_cnt = 0;
+ if (data_len)
+ data = buffer;
+ else
+ data = 0;
+
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK:
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+ while(data_len > 4096) {
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
+ data += 4096; data_len -= 4096; cnt++;
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+ cnt++;
+
+ if (!ohci->sleeping)
+ writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+ break;
+
+ case PIPE_CONTROL:
+ info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+ td_fill (ohci, info, setup, 8, dev, cnt++, urb);
+ if (data_len > 0) {
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ /* NOTE: mishandles transfers >8K, some >4K */
+ td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill (ohci, info, data, 0, dev, cnt++, urb);
+ if (!ohci->sleeping)
+ writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+ break;
+ }
+ if (urb->length != cnt)
+ dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t * td)
+{
+ __u32 tdINFO, tdBE, tdCBP;
+ urb_priv_t *lurb_priv = &urb_priv;
+
+ tdINFO = ohci_cpu_to_le32 (td->hwINFO);
+ tdBE = ohci_cpu_to_le32 (td->hwBE);
+ tdCBP = ohci_cpu_to_le32 (td->hwCBP);
+
+
+ if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ if (tdBE != 0) {
+ if (td->hwCBP == 0)
+ lurb_priv->actual_length += tdBE - td->data + 1;
+ else
+ lurb_priv->actual_length += tdCBP - td->data;
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static td_t * dl_reverse_done_list (ohci_t *ohci)
+{
+ __u32 td_list_hc;
+ td_t *td_rev = NULL;
+ td_t *td_list = NULL;
+ urb_priv_t *lurb_priv = NULL;
+
+ td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
+ ohci->hcca->done_head = 0;
+
+ while (td_list_hc) {
+ td_list = (td_t *)td_list_hc;
+
+ if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
+ lurb_priv = &urb_priv;
+ dbg(" USB-error/status: %x : %p",
+ TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
+ if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+ td_list->ed->hwHeadP =
+ (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
+ (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
+ lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+ } else
+ td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
+ }
+#ifdef CONFIG_MPC5200
+ td_list->hwNextTD = 0;
+#endif
+ }
+
+ td_list->next_dl_td = td_rev;
+ td_rev = td_list;
+ td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
+ }
+ return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list (ohci_t *ohci, td_t *td_list)
+{
+ td_t *td_list_next = NULL;
+ ed_t *ed;
+ int cc = 0;
+ int stat = 0;
+ /* urb_t *urb; */
+ urb_priv_t *lurb_priv;
+ __u32 tdINFO, edHeadP, edTailP;
+
+ while (td_list) {
+ td_list_next = td_list->next_dl_td;
+
+ lurb_priv = &urb_priv;
+ tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
+
+ ed = td_list->ed;
+
+ dl_transfer_length(td_list);
+
+ /* error code of transfer */
+ cc = TD_CC_GET (tdINFO);
+ if (++(lurb_priv->td_cnt) == lurb_priv->length) {
+ if ((ed->state & (ED_OPER | ED_UNLINK))
+ && (lurb_priv->state != URB_DEL)) {
+ dbg("ConditionCode %#x", cc);
+ stat = cc_to_error[cc];
+ urb_finished = 1;
+ }
+ }
+
+ if (ed->state != ED_NEW) {
+ edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
+ edTailP = ohci_cpu_to_le32 (ed->hwTailP);
+
+ /* unlink eds if they are not busy */
+ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+ ep_unlink (ohci, ed);
+ }
+
+ td_list = td_list_next;
+ }
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x) len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#else
+#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+ __u32 temp, ndp, i;
+ int res;
+
+ res = -1;
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ /* check for a device disconnect */
+ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+ (RH_PS_PESC | RH_PS_CSC)) &&
+ ((temp & RH_PS_CCS) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *cmd)
+{
+ void * data = buffer;
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ __u32 datab[4];
+ __u8 *data_buf = (__u8 *)datab;
+ __u16 bmRType_bReq;
+ __u16 wValue;
+ __u16 wIndex;
+ __u16 wLength;
+
+#ifdef DEBUG
+urb_priv.actual_length = 0;
+pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#endif
+ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ info("Root-Hub submit IRQ: NOT implemented");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = m16_swap (cmd->value);
+ wIndex = m16_swap (cmd->index);
+ wLength = m16_swap (cmd->length);
+
+ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+ switch (bmRType_bReq) {
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
+
+ case RH_GET_STATUS:
+ *(__u16 *) data_buf = m16_swap (1); OK (2);
+ case RH_GET_STATUS | RH_INTERFACE:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_ENDPOINT:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (
+ RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK (4);
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ switch (wValue) {
+ case (RH_ENDPOINT_STALL): OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC); OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+ }
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PRS);
+ OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PES );
+ OK (0);
+ }
+ break;
+
+ case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+
+ case RH_GET_DESCRIPTOR:
+ switch ((wValue & 0xff00) >> 8) {
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_dev_des),
+ wLength));
+ data_buf = root_hub_dev_des; OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des; OK(len);
+ case (0x03): /* string descriptors */
+ if(wValue==0x0300) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if(wValue==0x0301) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
+ }
+ default:
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ {
+ __u32 temp = roothub_a (&gohci);
+
+ data_buf [0] = 9; /* min length; */
+ data_buf [1] = 0x29;
+ data_buf [2] = temp & RH_A_NDP;
+ data_buf [3] = 0;
+ if (temp & RH_A_PSM) /* per-port power switching? */
+ data_buf [3] |= 0x1;
+ if (temp & RH_A_NOCP) /* no overcurrent reporting? */
+ data_buf [3] |= 0x10;
+ else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
+ data_buf [3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab [1] = 0;
+ data_buf [5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b (&gohci);
+ data_buf [7] = temp & RH_B_DR;
+ if (data_buf [2] < 7) {
+ data_buf [8] = 0xff;
+ } else {
+ data_buf [0] += 2;
+ data_buf [8] = (temp & RH_B_DR) >> 8;
+ data_buf [10] = data_buf [9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf [0], wLength));
+ OK (len);
+ }
+
+ case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
+
+ case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
+
+ default:
+ dbg ("unsupported root hub command");
+ stat = USB_ST_STALLED;
+ }
+
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#endif
+
+ len = min_t(int, len, leni);
+ if (data != data_buf)
+ memcpy (data, data_buf, len);
+ dev->act_len = len;
+ dev->status = stat;
+
+#ifdef DEBUG
+ if (transfer_len)
+ urb_priv.actual_length = transfer_len;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#endif
+
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ int stat = 0;
+ int maxsize = usb_maxpacket(dev, pipe);
+ int timeout;
+
+ /* device pulled? Shortcut the action. */
+ if (devgone == dev) {
+ dev->status = USB_ST_CRC_ERR;
+ return 0;
+ }
+
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#endif
+ if (!maxsize) {
+ err("submit_common_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+
+ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+ err("sohci_submit_job failed");
+ return -1;
+ }
+
+ /* allow more time for a BULK device to react - some are slow */
+#define BULK_TO 5000 /* timeout in milliseconds */
+ if (usb_pipetype (pipe) == PIPE_BULK)
+ timeout = BULK_TO;
+ else
+ timeout = 100;
+
+ /* wait for it to complete */
+ for (;;) {
+ /* check whether the controller is done */
+ stat = hc_interrupt();
+ if (stat < 0) {
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+
+ /* NOTE: since we are not interrupt driven in U-Boot and always
+ * handle only one URB at a time, we cannot assume the
+ * transaction finished on the first successful return from
+ * hc_interrupt().. unless the flag for current URB is set,
+ * meaning that all TD's to/from device got actually
+ * transferred and processed. If the current URB is not
+ * finished we need to re-iterate this loop so as
+ * hc_interrupt() gets called again as there needs to be some
+ * more TD's to process still */
+ if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
+ /* 0xff is returned for an SF-interrupt */
+ break;
+ }
+
+ if (--timeout) {
+ wait_ms(1);
+ if (!urb_finished)
+ dbg("\%");
+
+ } else {
+ err("CTL:TIMEOUT ");
+ dbg("submit_common_msg: TO status %x\n", stat);
+ stat = USB_ST_CRC_ERR;
+ urb_finished = 1;
+ break;
+ }
+ }
+#if 0
+ /* we got an Root Hub Status Change interrupt */
+ if (got_rhsc) {
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#endif
+ got_rhsc = 0;
+ /* abuse timeout */
+ timeout = rh_check_port_status(&gohci);
+ if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here in case that changes */
+ /* the called routine adds 1 to the passed value */
+ usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+ /*
+ * XXX
+ * This is potentially dangerous because it assumes
+ * that only one device is ever plugged in!
+ */
+ devgone = dev;
+ }
+ }
+#endif
+
+ dev->status = stat;
+ dev->act_len = transfer_len;
+
+#ifdef DEBUG
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#endif
+
+ /* free TDs in urb_priv */
+ urb_free_priv (&urb_priv);
+ return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len)
+{
+ info("submit_bulk_msg");
+ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup)
+{
+ int maxsize = usb_maxpacket(dev, pipe);
+
+ info("submit_control_msg");
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#endif
+ if (!maxsize) {
+ err("submit_control_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+ gohci.rh.dev = dev;
+ /* root hub - redirect */
+ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+ setup);
+ }
+
+ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, int interval)
+{
+ info("submit_int_msg");
+ return -1;
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset (ohci_t *ohci)
+{
+ int timeout = 30;
+ int smm_timeout = 50; /* 0,5 sec */
+
+ if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
+ writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+ info("USB HC TakeOver from SMM");
+ while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
+ wait_ms (10);
+ if (--smm_timeout == 0) {
+ err("USB HC TakeOver failed!");
+ return -1;
+ }
+ }
+ }
+
+ /* Disable HC interrupts */
+ writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
+ ohci->slot_name,
+ readl (&ohci->regs->control));
+
+ /* Reset USB (needed by some controllers) */
+ ohci->hc_control = 0;
+ writel (ohci->hc_control, &ohci->regs->control);
+
+ /* HC Reset requires max 10 us delay */
+ writel (OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ if (--timeout == 0) {
+ err("USB HC reset timed out!");
+ return -1;
+ }
+ udelay (1);
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start (ohci_t * ohci)
+{
+ __u32 mask;
+ unsigned int fminterval;
+
+ ohci->disabled = 1;
+
+ /* Tell the controller where the control and bulk lists are
+ * The lists are empty now. */
+
+ writel (0, &ohci->regs->ed_controlhead);
+ writel (0, &ohci->regs->ed_bulkhead);
+
+ writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+
+ fminterval = 0x2edf;
+ writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+ writel (fminterval, &ohci->regs->fminterval);
+ writel (0x628, &ohci->regs->lsthresh);
+
+ /* start controller operations */
+ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ ohci->disabled = 0;
+ writel (ohci->hc_control, &ohci->regs->control);
+
+ /* disable all interrupts */
+ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel (mask, &ohci->regs->intrdisable);
+ /* clear all interrupts */
+ mask &= ~OHCI_INTR_MIE;
+ writel (mask, &ohci->regs->intrstatus);
+ /* Choose the interrupts we care about now - but w/o MIE */
+ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+ writel (mask, &ohci->regs->intrenable);
+
+#ifdef OHCI_USE_NPS
+ /* required for AMD-756 and some Mac platforms */
+ writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel (RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+
+#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
+ /* POTPGT delay is bits 24-31, in 2 ms units. */
+ mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+
+ /* connect the virtual root hub */
+ ohci->rh.devnum = 0;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static int
+hc_interrupt (void)
+{
+ ohci_t *ohci = &gohci;
+ struct ohci_regs *regs = ohci->regs;
+ int ints;
+ int stat = -1;
+
+ if ((ohci->hcca->done_head != 0) &&
+ !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
+
+ ints = OHCI_INTR_WDH;
+
+ } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) {
+ ohci->disabled++;
+ err ("%s device removed!", ohci->slot_name);
+ return -1;
+
+ } else if ((ints &= readl (®s->intrenable)) == 0) {
+ dbg("hc_interrupt: returning..\n");
+ return 0xff;
+ }
+
+ /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+
+ if (ints & OHCI_INTR_RHSC) {
+ got_rhsc = 1;
+ stat = 0xff;
+ }
+
+ if (ints & OHCI_INTR_UE) {
+ ohci->disabled++;
+ err ("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
+ /* e.g. due to PCI Master/Target Abort */
+
+#ifdef DEBUG
+ ohci_dump (ohci, 1);
+#endif
+ /* FIXME: be optimistic, hope that bug won't repeat often. */
+ /* Make some non-interrupt context restart the controller. */
+ /* Count and limit the retries though; either hardware or */
+ /* software errors can go forever... */
+ hc_reset (ohci);
+ return -1;
+ }
+
+ if (ints & OHCI_INTR_WDH) {
+ writel (OHCI_INTR_WDH, ®s->intrdisable);
+ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
+ writel (OHCI_INTR_WDH, ®s->intrenable);
+ }
+
+ if (ints & OHCI_INTR_SO) {
+ dbg("USB Schedule overrun\n");
+ writel (OHCI_INTR_SO, ®s->intrenable);
+ stat = -1;
+ }
+
+ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
+ if (ints & OHCI_INTR_SF) {
+ unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
+ wait_ms(1);
+ writel (OHCI_INTR_SF, ®s->intrdisable);
+ if (ohci->ed_rm_list[frame] != NULL)
+ writel (OHCI_INTR_SF, ®s->intrenable);
+ stat = 0xff;
+ }
+
+ writel (ints, ®s->intrstatus);
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci (ohci_t *ohci)
+{
+ dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+
+ if (!ohci->disabled)
+ hc_reset (ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(void)
+{
+ memset (&gohci, 0, sizeof (ohci_t));
+ memset (&urb_priv, 0, sizeof (urb_priv_t));
+
+ /* align the storage */
+ if ((__u32)&ghcca[0] & 0xff) {
+ err("HCCA not aligned!!");
+ return -1;
+ }
+ phcca = &ghcca[0];
+ info("aligned ghcca %p", phcca);
+ memset(&ohci_dev, 0, sizeof(struct ohci_device));
+ if ((__u32)&ohci_dev.ed[0] & 0x7) {
+ err("EDs not aligned!!");
+ return -1;
+ }
+ memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
+ if ((__u32)gtd & 0x7) {
+ err("TDs not aligned!!");
+ return -1;
+ }
+ ptd = gtd;
+ gohci.hcca = phcca;
+ memset (phcca, 0, sizeof (struct ohci_hcca));
+
+ gohci.disabled = 1;
+ gohci.sleeping = 0;
+ gohci.irq = -1;
+ gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+
+ gohci.flags = 0;
+ gohci.slot_name = "ppc440";
+
+ if (hc_reset (&gohci) < 0) {
+ hc_release_ohci (&gohci);
+ return -1;
+ }
+
+ if (hc_start (&gohci) < 0) {
+ err ("can't start usb-%s", gohci.slot_name);
+ hc_release_ohci (&gohci);
+ return -1;
+ }
+
+#ifdef DEBUG
+ ohci_dump (&gohci, 1);
+#endif
+ ohci_inited = 1;
+ urb_finished = 1;
+
+ /* init the device driver */
+ usb_dev_init();
+
+ return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+ /* this gets called really early - before the controller has */
+ /* even been initialized! */
+ if (!ohci_inited)
+ return 0;
+ /* TODO release any interrupts, etc. */
+ /* call hc_release_ohci() here ? */
+ hc_reset (&gohci);
+ return 0;
+}
+
+#endif /* CONFIG_USB_OHCI */
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
+};
+
+/* ED States */
+
+#define ED_NEW 0x00
+#define ED_UNLINK 0x01
+#define ED_OPER 0x02
+#define ED_DEL 0x04
+#define ED_URB_DEL 0x08
+
+/* usb_ohci_ed */
+struct ed {
+ __u32 hwINFO;
+ __u32 hwTailP;
+ __u32 hwHeadP;
+ __u32 hwNextED;
+
+ struct ed *ed_prev;
+ __u8 int_period;
+ __u8 int_branch;
+ __u8 int_load;
+ __u8 int_interval;
+ __u8 state;
+ __u8 type;
+ __u16 last_iso;
+ struct ed *ed_rm_list;
+
+ struct usb_device *usb_dev;
+ __u32 unused[3];
+} __attribute((aligned(16)));
+typedef struct ed ed_t;
+
+/* TD info field */
+#define TD_CC 0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC 0x0C000000
+#define TD_T 0x03000000
+#define TD_T_DATA0 0x02000000
+#define TD_T_DATA1 0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R 0x00040000
+#define TD_DI 0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP 0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN 0x00100000
+#define TD_DP_OUT 0x00080000
+
+#define TD_ISO 0x00010000
+#define TD_DEL 0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_DEVNOTRESP 0x05
+#define TD_PIDCHECKFAIL 0x06
+#define TD_UNEXPECTEDPID 0x07
+#define TD_DATAOVERRUN 0x08
+#define TD_DATAUNDERRUN 0x09
+#define TD_BUFFEROVERRUN 0x0C
+#define TD_BUFFERUNDERRUN 0x0D
+#define TD_NOTACCESSED 0x0F
+
+#define MAXPSW 1
+
+struct td {
+ __u32 hwINFO;
+ __u32 hwCBP; /* Current Buffer Pointer */
+ __u32 hwNextTD; /* Next TD Pointer */
+ __u32 hwBE; /* Memory Buffer End Pointer */
+
+ __u16 hwPSW[MAXPSW];
+ __u8 unused;
+ __u8 index;
+ struct ed *ed;
+ struct td *next_dl_td;
+ struct usb_device *usb_dev;
+ int transfer_len;
+ __u32 data;
+
+ __u32 unused2[2];
+} __attribute((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP (1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of. It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32 /* part of the OHCI standard */
+struct ohci_hcca {
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+#if defined(CONFIG_MPC5200)
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u16 frame_no; /* current frame number */
+#else
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+#endif
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute((aligned(256)));
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region. This is Memory Mapped I/O. You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+ /* control and status registers */
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
+ /* memory pointers */
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
+ /* frame counters */
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
+ /* Root hub ports */
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[MAX_ROOT_PORTS];
+ } roothub;
+} __attribute((aligned(32)));
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
+#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
+#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
+#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
+#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
+#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
+#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
+#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
+#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+# define OHCI_USB_RESET (0 << 6)
+# define OHCI_USB_RESUME (1 << 6)
+# define OHCI_USB_OPER (2 << 6)
+# define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR (1 << 0) /* host controller reset */
+#define OHCI_CLF (1 << 1) /* control list filled */
+#define OHCI_BLF (1 << 2) /* bulk list filled */
+#define OHCI_OCR (1 << 3) /* ownership change request */
+#define OHCI_SOC (3 << 16) /* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
+#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
+#define OHCI_INTR_SF (1 << 2) /* start frame */
+#define OHCI_INTR_RD (1 << 3) /* resume detect */
+#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
+#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
+#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
+#define OHCI_INTR_OC (1 << 30) /* ownership change */
+#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
+ void *int_addr;
+ int send;
+ int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status */
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct {
+ ed_t *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ int state;
+ unsigned long pipe;
+ int actual_length;
+ td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+typedef struct ohci {
+ struct ohci_hcca *hcca; /* hcca */
+ /*dma_addr_t hcca_dma; */
+
+ int irq;
+ int disabled; /* e.g. got a UE, we're hung */
+ int sleeping;
+ unsigned long flags; /* for HC bugs */
+
+ struct ohci_regs *regs; /* OHCI controller's memory */
+
+ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ ed_t *ed_bulktail; /* last endpoint of bulk list */
+ ed_t *ed_controltail; /* last endpoint of control list */
+ int intrstatus;
+ __u32 hc_control; /* copy of the hc control reg */
+ struct usb_device *dev[32];
+ struct virt_root_hub rh;
+
+ const char *slot_name;
+} ohci_t;
+
+#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+ ed_t ed[NUM_EDS];
+ int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD + 1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *td_alloc(struct usb_device *usb_dev)
+{
+ int i;
+ struct td *td;
+
+ td = NULL;
+ for (i = 0; i < NUM_TD; i++) {
+ if (ptd[i].usb_dev == NULL) {
+ td = &ptd[i];
+ td->usb_dev = usb_dev;
+ break;
+ }
+ }
+
+ return td;
+}
+
+static inline void ed_free(struct ed *ed)
+{
+ ed->usb_dev = NULL;
+}
--- /dev/null
+/*USB 1.1,2.0 device*/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifdef CONFIG_440EP
+
+#include <usb.h>
+#include "usbdev.h"
+#include "vecnum.h"
+
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIG 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+
+int set_value = -1;
+
+void process_endpoints(unsigned short usb2d0_intrin)
+{
+ /*will hold the packet received */
+ struct usb_device_descriptor usb_device_packet;
+ struct usb_config_descriptor usb_config_packet;
+ struct usb_string_descriptor usb_string_packet;
+ struct devrequest setup_packet;
+ unsigned int *setup_packet_pt;
+ unsigned char *packet_pt = NULL;
+ int temp, temp1;
+
+ int i;
+
+ /*printf("{USB device} - endpoint 0x%X \n", usb2d0_intrin); */
+
+ /*set usb address, seems to not work unless it is done in the next
+ interrupt, so that is why it is done this way */
+ if (set_value != -1)
+ *(unsigned char *)USB2D0_FADDR_8 = (unsigned char)set_value;
+
+ /*endpoint 1 */
+ if (usb2d0_intrin & 0x01) {
+ setup_packet_pt = (unsigned int *)&setup_packet;
+
+ /*copy packet */
+ setup_packet_pt[0] = *(unsigned int *)USB2D0_FIFO_0;
+ setup_packet_pt[1] = *(unsigned int *)USB2D0_FIFO_0;
+ temp = *(unsigned int *)USB2D0_FIFO_0;
+ temp1 = *(unsigned int *)USB2D0_FIFO_0;
+
+ /*do some swapping */
+ setup_packet.value = swap_16(setup_packet.value);
+ setup_packet.index = swap_16(setup_packet.index);
+ setup_packet.length = swap_16(setup_packet.length);
+
+ /*clear rx packet */
+ *(unsigned short *)USB2D0_INCSR0_8 = 0x48;
+
+ /*printf("0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", setup_packet.requesttype,
+ setup_packet.request, setup_packet.value,
+ setup_packet.index, setup_packet.length, temp, temp1 ); */
+
+ switch (setup_packet.request) {
+ case USB_REQ_GET_DESCRIPTOR:
+
+ switch (setup_packet.value >> 8) {
+ case USB_DT_DEVICE:
+ /*create packet */
+ usb_device_packet.bLength = 18;
+ usb_device_packet.bDescriptorType =
+ USB_DT_DEVICE;
+#ifdef USB_2_0_DEVICE
+ usb_device_packet.bcdUSB = swap_16(0x200);
+#else
+ usb_device_packet.bcdUSB = swap_16(0x110);
+#endif
+ usb_device_packet.bDeviceClass = 0xff;
+ usb_device_packet.bDeviceSubClass = 0;
+ usb_device_packet.bDeviceProtocol = 0;
+ usb_device_packet.bMaxPacketSize0 = 32;
+ usb_device_packet.idVendor = swap_16(1);
+ usb_device_packet.idProduct = swap_16(2);
+ usb_device_packet.bcdDevice = swap_16(0x300);
+ usb_device_packet.iManufacturer = 1;
+ usb_device_packet.iProduct = 1;
+ usb_device_packet.iSerialNumber = 1;
+ usb_device_packet.bNumConfigurations = 1;
+
+ /*put packet in fifo */
+ packet_pt = (unsigned char *)&usb_device_packet;
+ break;
+
+ case USB_DT_CONFIG:
+ /*create packet */
+ usb_config_packet.bLength = 9;
+ usb_config_packet.bDescriptorType =
+ USB_DT_CONFIG;
+ usb_config_packet.wTotalLength = swap_16(25);
+ usb_config_packet.bNumInterfaces = 1;
+ usb_config_packet.bConfigurationValue = 1;
+ usb_config_packet.iConfiguration = 0;
+ usb_config_packet.bmAttributes = 0x40;
+ usb_config_packet.MaxPower = 0;
+
+ /*put packet in fifo */
+ packet_pt = (unsigned char *)&usb_config_packet;
+ break;
+
+ case USB_DT_STRING:
+ /*create packet */
+ usb_string_packet.bLength = 2;
+ usb_string_packet.bDescriptorType =
+ USB_DT_STRING;
+ usb_string_packet.wData[0] = 0x0094;
+
+ /*put packet in fifo */
+ packet_pt = (unsigned char *)&usb_string_packet;
+ break;
+ }
+
+ /*put packet in fifo */
+ for (i = 0; i < (setup_packet.length); i++) {
+ *(unsigned char *)USB2D0_FIFO_0 = packet_pt[i];
+ }
+
+ /*give tx command */
+ *(unsigned short *)USB2D0_INCSR0_8 = 0x0a;
+
+ break;
+
+ case USB_REQ_SET_ADDRESS:
+
+ /*copy usb address */
+ set_value = setup_packet.value;
+
+ break;
+ }
+
+ }
+}
+
+void process_other(unsigned char usb2d0_intrusb)
+{
+
+ /*check for sof */
+ if (usb2d0_intrusb & 0x08) {
+ /*printf("{USB device} - sof detected\n"); */
+ }
+
+ /*check for reset */
+ if (usb2d0_intrusb & 0x04) {
+ /*printf("{USB device} - reset detected\n"); */
+
+ /*copy usb address of zero, need to do this when usb reset */
+ set_value = 0;
+ }
+
+ if (usb2d0_intrusb & 0x02) {
+ /*printf("{USB device} - resume detected\n"); */
+ }
+
+ if (usb2d0_intrusb & 0x01) {
+ /*printf("{USB device} - suspend detected\n"); */
+ }
+}
+
+int usbInt(void)
+{
+ /*Must read these 2 registers and use values to clear interrupts. If you
+ do not read them then the interrupt will not be cleared. If you do not
+ use the variable the optimizer will not do a read. */
+ volatile unsigned short usb2d0_intrin =
+ *(unsigned short *)USB2D0_INTRIN_16;
+ volatile unsigned char usb2d0_intrusb =
+ *(unsigned char *)USB2D0_INTRUSB_8;
+
+ /*check if there was an endpoint interrupt */
+ if (usb2d0_intrin != 0) {
+ process_endpoints(usb2d0_intrin);
+ }
+
+ /*check for other interrupts */
+ if (usb2d0_intrusb != 0) {
+ process_other(usb2d0_intrusb);
+ }
+
+ return 0;
+}
+
+void usb_dev_init()
+{
+#ifdef USB_2_0_DEVICE
+ printf("USB 2.0 Device init\n");
+ /*select 2.0 device */
+ mtsdr(sdr_usb0, 0x0); /* 2.0 */
+
+ /*usb dev init */
+ *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */
+#else
+ printf("USB 1.1 Device init\n");
+ /*select 1.1 device */
+ mtsdr(sdr_usb0, 0x2); /* 1.1 */
+
+ /*usb dev init */
+ *(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */
+#endif
+
+ /*enable interrupts */
+ *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f;
+
+ irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt,
+ NULL);
+}
+
+#endif /*CONFIG_440EP */
--- /dev/null
+#include <config.h>
+
+/*Common Registers*/
+#define USB2D0_INTRIN_16 (CFG_USB_DEVICE | 0x100)
+#define USB2D0_POWER_8 (CFG_USB_DEVICE | 0x102)
+#define USB2D0_FADDR_8 (CFG_USB_DEVICE | 0x103)
+#define USB2D0_INTRINE_16 (CFG_USB_DEVICE | 0x104)
+#define USB2D0_INTROUT_16 (CFG_USB_DEVICE | 0x106)
+#define USB2D0_INTRUSBE_8 (CFG_USB_DEVICE | 0x108)
+#define USB2D0_INTRUSB_8 (CFG_USB_DEVICE | 0x109)
+#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a)
+#define USB2D0_TSTMODE_8 (CFG_USB_DEVICE | 0x10c)
+#define USB2D0_INDEX_8 (CFG_USB_DEVICE | 0x10d)
+#define USB2D0_FRAME_16 (CFG_USB_DEVICE | 0x10e)
+
+/*Indexed Registers*/
+#define USB2D0_INCSR0_8 (CFG_USB_DEVICE | 0x110)
+#define USB2D0_INCSR_16 (CFG_USB_DEVICE | 0x110)
+#define USB2D0_INMAXP_16 (CFG_USB_DEVICE | 0x112)
+#define USB2D0_OUTCSR_16 (CFG_USB_DEVICE | 0x114)
+#define USB2D0_OUTMAXP_16 (CFG_USB_DEVICE | 0x116)
+#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a)
+#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a)
+
+/*FIFOs*/
+#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120)
+#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124)
+#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128)
+#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c)
+
+void usb_dev_init(void);
#define VECNUM_MS (32 + 0 ) /* MAL SERR */
#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
+#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
--- /dev/null
+---------------------------------------------------------------------
+Cleanup of AMCC eval boards (Walnut/Sycamore, Bubinga, Ebony, Ocotea)
+---------------------------------------------------------------------
+
+Changes to all AMCC eval boards:
+--------------------------------
+
+o Changed u-boot image size to 256 kBytes instead of 512 kBytes on most
+ boards.
+
+o Use 115200 baud as default console baudrate.
+
+o Added config option to use redundant environment in flash. This is also
+ the default setting. Option for environment in nvram is still available
+ for backward compatibility.
+
+o Merged board specific flash drivers to common flash driver:
+ board/amcc/common/flash.c
+
+
+Sycamore/Walnut (one port supporting both eval boards):
+-------------------------------------------------------
+
+o Cleanup to allow easier "cloning" for different (custom) boards:
+
+ o Moved EBC configuration from board specific asm-file "init.S"
+ using defines in board configuration file. No board specific
+ asm file needed anymore.
+
+
+August 01 2005, Stefan Roese <sr@denx.de>
--- /dev/null
+After several heart-struck failure, I got one workable way to program
+each other in FLASH between PlanetCore and U-Boot.
+
+Hardware Platform : RPXlite DW(EP 823 H1 DW)
+
+1. From U-Boot to PlanetCore
+
+Utilities : PlanetCore Boot Loader - PCL200.mot
+
+[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot
+PCL200.mot pcl200.bin
+
+[Target Operation]
+u-boot>t 100000 pcl200.bin
+u-boot>go 0x100000
+## Starting application at 0x00100000 ...
+
+MPC8xx PlanetCore Flash Burner v2.00
+Copyright 2001 Embedded Planet. All rights reserved.
+
+Construct Flash Device.....done.
+
+
+Program MPC8xx PlanetCore Boot Loader v2.00
+Built Sep 19, 2001 at 14:34:42
+Image located from FC000000 to FC01B5D1.
+(Skipping an image, only loading low boot image)
+
+Low boot board detected, skipping high boot image.
+Erasing, programming and verifying will start in 20
+seconds
+Press P to start immediately or ESC to cancel
+Press Space or Enter for more options.
+..............
+
+Erasing
+Programming
+FLASH programmed successfully!
+Press R to induce a hard reset
+
+MPC8xx PlanetCore Boot Loader v2.00
+Copyright 2001 Embedded Planet. All rights reserved.
+DRAM available size = 64 MB
+wvCV
+DRAM OK
+>
+
+2. From PlanetCore to U-Boot
+
+Utilities : PlanetCore FLASH Burner - PCB200.mot
+
+Use Flash Burner to finish the work:
+
+First, TFTP the U-Boot image file to RAM; For example,
+RPXlite_DW.bin to 0x400000
+Second, TFTP FLASH Burner to RAM; For example,
+0x100000
+Third, run the FLASH Burner and Program the U-Boot
+image into the correct location in FLASH.
+
+[Target Operation]
+MPC8xx PlanetCore Boot Loader v2.00
+Copyright 2001 Embedded Planet. All rights reserved.
+DRAM available size = 64 MB
+wvCV
+DRAM OK
+>t
+Load using tftp via Ethernet
+Enter server IP address <172.16.115.6> :
+Enter server filename <PCL200.mot> : RPXlite_DW.bin
+Enter (B)inary or (S)record input mode <S> : B
+Enter address offset : <00400000 hex> :
+
+Total bytes = 120096 in 232184 uSecs
+Loaded addresses 00400000 through 0041D51F.
+Start address = 00400000
+>t
+Load using tftp via Ethernet
+Enter server IP address <172.16.115.6> :
+Enter server filename <RPXlite_DW.bin> : PCB200.mot
+Enter (B)inary or (S)record input mode <B> : S
+Enter address offset : <00000000 hex> :
+.512.1024..2048....4096.....
+Total bytes = 326280 in 2570249 uSecs
+Loaded addresses 00100000 through 0011BB51.
+Start address = 00100000
+>go
+[Go 00100000]
+
+MPC8xx PlanetCore Flash Burner v2.00
+Copyright 2001 Embedded Planet. All rights reserved.
+
+Construct Flash Device.....done.
+
+Bad start address
+Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length =
+0xFFFFFFFF
+Forcing Menu Interface
+
+h[elp] Show commands.
+c[ode] Show information on code to be loaded.
+di[splay] Display all flash sections.
+du[mp] Dump memory. d ? for more info.
+e[rase] Erase flash sections.
+f[ill] Fill flash sections.
+im[age] Toggle load high, low, or both flash
+images.
+in[fo] Show flash information.
+ma[p] Show memory map.
+mo[dify] Modify memory. m ? for more info.
+p[rogram] Erase, program, and verify now.
+reset Restart the loader.
+s[how] Show flash sections to erase and program.
+t[est] Test flash sections.
+q[uit] Quit without programming.
+#program 400000 ff000000 1D51F
+doProgram( 400000 ff000000 1D51F )
+
+Start = 0x00400000, target = 0xFF000000, length =
+0x0001D51F
+Erasing sector 0xFF000000, length 0x008000.
+Erasing sector 0xFF008000, length 0x008000.
+Erasing sector 0xFF010000, length 0x008000.
+Erasing sector 0xFF018000, length 0x008000.
+Programming FF000000 through FF01D51E
+FLASH programmed successfully!
+Press R to induce a hard reset
+
+Forcing Hard Reset by MachineCheck and
+ResetOnCheckstop...
+
+U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
+
+CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB
+D-Cache
+Board: RPXlite_DW
+DRAM: 64 MB
+FLASH: 16 MB
+*** Warning - bad CRC, using default environment
+
+In: serial
+Out: serial
+Err: serial
+Net: SCC ETHERNET
+u-boot>
+
+-------------------------------------------------
+
+Well, sometimes network function of PlanetCore couldn't work when
+switching from U-Boot to PlanetCore. For example, you couldn't
+download a file from HOST PC via TFTP. Don't worry, just restart your
+HOST PC and everything would work as smooth as clockwork. I don't
+know the reason WHY:-)
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Merry Christmas and Happy New Year!
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+=====
+Best regards,
+
+Sam
--- /dev/null
+Freescale MPC83xx ADS Boards
+-----------------------------------------
+
+0. Toolchain / Building
+
+ $ PATH=$PATH:/usr/powerpc/bin
+ $ CROSS_COMPILE=powerpc-linux-
+ $ export PATH CROSS_COMPILE
+
+ $ powerpc-linux-gcc -v
+ Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs
+ Configured with: ../configure --prefix=/usr/powerpc
+ --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared
+ --disable-nls --disable-multilib --enable-languages=c,c++,ada,f77,objc
+ Thread model: posix
+ gcc version 3.4.3 (Debian)
+
+ $ powerpc-linux-as -v
+ GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15
+
+
+ $ make MPC8349ADS_config
+ Configuring for MPC8349ADS board...
+
+ $ make
+
+
+1. Board Switches and Jumpers
+
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x9fff_ffff PCI MEM 512M
+ 0xc000_0000 0xdfff_ffff Rapid IO 512M
+ 0xe000_0000 0xe00f_ffff CCSR 1M
+ 0xe200_0000 0xe2ff_ffff PCI IO 16M
+ 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ 0xf800_0000 0xf80f_ffff BCSR 1M
+ 0xfe00_0000 0xffff_ffff FLASH (boot bank) 16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8349ADS.h
+
+ CONFIG_MPC83xx MPC83xx family
+ CONFIG_MPC8349 MPC8349 specific
+ CONFIG_MPC8349ADS MPC8349ADS board specific
+ CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet
+
+
+4. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC8349ADS_config
+ make
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+ loadb
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp 10000 u-boot.bin
+ protect off fe000000 fe09ffff
+ erase fe000000 fe09ffff
+
+ cp.b 10000 fe000000 xxxx
+or
+ cp.b 10000 fe000000 a0000
+
+You might have to supply the correct byte count for 'xxxx' from
+the TFTP. Maybe a0000 will work too, that corresponds to the
+erased sectors.
+
+
+6. Notes
CONFIG_E500 BOOKE e500 family(Motorola)
CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
CONFIG_MPC8540 MPC8540 specific
- CONFIG_MPC8560 MPC8560 specific
CONFIG_MPC8540ADS MPC8540ADS board specific
CONFIG_MPC8560ADS MPC8560ADS board specific
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
CONFIG_DDR_ECC only for ECC DDR module
CONFIG_DDR_DLL DLL fix on some ADS boards needed for more
stability.
+ CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0.
Other than the above definitions, the rest in the config files are
straightforward.
4.4 Reflash U-boot Image using U-boot
- => tftp 10000 u-boot.bin
- => protect off fff80000 ffffffff
- => erase fff80000 ffffffff
- => cp.b 10000 fff80000 80000
+ tftp 10000 u-boot.bin
+ protect off fff80000 ffffffff
+ erase fff80000 ffffffff
+ cp.b 10000 fff80000 80000
4.5 Reflash U-Boot with a BDI-2000
SW4=10001000
-CPU Card Switches
------------------
+8555/41 CPU Card Switches
+-------------------------
Most switches on the CPU Card should not be changed. However, the
frequency can be changed by setting SW3:
SW4=11111110
+8548 CPU Card Switches
+----------------------
+And, just to be confusing, in this set of switches:
+
+ ON = 1
+ OFF = 0
+
+Default
+ SW1=11111101
+ SW2=10011111
+ SW3=11001000 (8X) (2:1)
+ SW4=11110011
+
+ SW3=X000XXXX == CORE:CCB 4:1
+ X001XXXX == CORE:CCB 9:2
+ X010XXXX == CORE:CCB 1:1
+ X011XXXX == CORE:CCB 3:2
+ X100XXXX == CORE:CCB 2:1
+ X101XXXX == CORE:CCB 5:2
+ X110XXXX == CORE:CCB 3:1
+ X111XXXX == CORE:CCB 7:2
+ XXXX0000 == CCB:SYSCLK 16:1
+ XXXX0001 == RESERVED
+ XXXX0010 == CCB:SYSCLK 2:1
+ XXXX0011 == CCB:SYSCLK 3:1
+ XXXX0100 == CCB:SYSCLK 4:1
+ XXXX0101 == CCB:SYSCLK 5:1
+ XXXX0110 == CCB:SYSCLK 6:1
+ XXXX0111 == RESERVED
+ XXXX1000 == CCB:SYSCLK 8:1
+ XXXX1001 == CCB:SYSCLK 9:1
+ XXXX1010 == CCB:SYSCLK 10:1
+ XXXX1011 == RESERVED
+ XXXX1100 == CCB:SYSCLK 12:1
+ XXXX1101 == CCB:SYSCLK 20:1
+ XXXX1110 == RESERVED
+ XXXX1111 == RESERVED
+
+
eDINK Info
----------
--- /dev/null
+
+
+First, some build notes on the Silicon Turnkey eXpress XTc.
+
+This board has both 87x/88x procesor options at various
+frequencies. The configuration file has some macros for setting
+the clock speed, not all have been tested. They all have
+a 10MHz input clock. Please do not check in a configuration
+file that selects a high speed not available on all processors.
+We chose the 66MHz core and bus speed, which should be OK on
+all boards. If you have a processor, lucky you! :-)
+Just build a new configuration with that speed, check
+the macro configuration to ensure it's correct. If the
+macro is updated, please check that in, but keep default
+processor speed.
+
+The board is likely to have more than 1Mbyte of NOR boot flash.
+It was also configured with a high boot vector (Dan's fault)
+so the standard 8xx mapping doesn't work well. We had to move
+the addresses around a little bit so one copy would work. The
+flash got fragmented, and we are working on a better solution.
+There is an "xtc.cfg" floating around for the BDI2000, use
+that for programming a new version of U-Boot. You can probably
+find it on the Silicon Turnkey eXpress (www.silicontkx.com),
+Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de)
+servers.
+
+The board will also have various SDRAM sizes, but the code
+should automatically determine the amount of memory.
+
+There are a couple of different board versions, visually
+they use different BGA or surface mount memory parts. However,
+they are logically the same board.
+
+Now, some operational notes.
+
+The board has the option of sporting two FEC Ethernet ports.
+The second port isn't configured to be automatically available
+because it would cause U-Boot to generate a board data structure
+(the bd_t) with multiple MAC addresses and be incompatible with
+standard 8xx kernel builds. You can use/test the second FEC
+in U-Boot by assigning an 'eth1addr' and selecting the second
+FEC as the port to use.
+
+Since this is just a development board and not a product, STx
+does not assign unique MAC addresses. We just pilfer the
+"default" ones used by Wolfgang on some other boards. Please
+ensure you assign unique MAC addresses when using these boards.
+
+The serial port baud rate is 38400, because that's the way
+I like it :-)
+
+Thanks to Pantelis for lots of the work on this board port.
+
+Have Fun!
+
+ -- Dan
+
+15 August 2005
serial_pl010.o serial_pl011.o serial_xuartlite.o \
sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
status_led.o sym53c8xx.o \
- ti_pci1410a.o tigon3.o \
+ ti_pci1410a.o tigon3.o tsec.o \
usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
videomodes.o w83c553f.o \
ks8695eth.o
i = buffered_size > cnt ? cnt : buffered_size;
if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
return rc;
- i -= (i % info->portwidth);
+ i -= i & (info->portwidth - 1);
wp += i;
src += i;
cnt -= i;
uchar *cp = (uchar *) cmdbuf;
for (i = 0; i < info->portwidth; i++)
- *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+ *cp++ = ((i + 1) & (info->chipwidth - 1)) ? '\0' : cmd;
#if defined(__LITTLE_ENDIAN)
switch (info->portwidth) {
case FLASH_CFI_8BIT:
-/*
- * (C) Copyright 2002
- * Denis Peter, MPL AG Switzerland
+/* ported from ctfb.c (linux kernel):
+ * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
+ *
+ * Ported to U-Boot:
+ * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-/*
- * ported from ctfb.c (linux kernel) for the U-Boot
- *
- */
-
-
#include <common.h>
#ifdef CONFIG_VIDEO
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
-#elif defined(CONFIG_440_GX)
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
-#ifndef CFG_FISRT_PCMCIA_BUS
-# define CFG_FISRT_PCMCIA_BUS 0
+#ifndef CFG_FIRST_PCMCIA_BUS
+# define CFG_FIRST_PCMCIA_BUS 0
#endif
int rcode = 0;
return 1;
}
if (strcmp(argv[1],"on") == 0) {
- rcode = pcmcia_on(CFG_FISRT_PCMCIA_BUS);
+ rcode = pcmcia_on(CFG_FIRST_PCMCIA_BUS);
} else if (strcmp(argv[1],"off") == 0) {
rcode = pcmcia_off();
} else {
*
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2003, Motorola, Inc.
- * maintained by Jon Loeliger (loeliger@freescale.com)
* author Andy Fleming
*
*/
struct tsec_info_struct {
unsigned int phyaddr;
- unsigned int gigabit;
+ u32 flags;
unsigned int phyregidx;
};
* phyaddr - The address of the PHY which is attached to
* the given device.
*
- * gigabit - This variable indicates whether the device
- * supports gigabit speed ethernet
+ * flags - This variable indicates whether the device
+ * supports gigabit speed ethernet, and whether it should be
+ * in reduced mode.
*
* phyregidx - This variable specifies which ethernet device
* controls the MII Management registers which are connected
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
-#ifdef CONFIG_MPC85XX_TSEC1
- {TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX},
+#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
+ {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#else
{ 0, 0, 0},
#endif
-#ifdef CONFIG_MPC85XX_TSEC2
- {TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX},
+#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
+ {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#else
{ 0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else
+# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
+ {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
+# else
{ 0, 0, 0},
+# endif
+# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
+ {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
+# else
+ { 0, 0, 0},
+# endif
#endif
};
-#define MAXCONTROLLERS 3
+#define MAXCONTROLLERS (4)
static int relocated = 0;
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
-int tsec_initialize(bd_t *bis, int index)
+int tsec_initialize(bd_t *bis, int index, char *devname)
{
struct eth_device* dev;
int i;
tsec_info[index].phyregidx*TSEC_SIZE);
priv->phyaddr = tsec_info[index].phyaddr;
- priv->gigabit = tsec_info[index].gigabit;
+ priv->flags = tsec_info[index].flags;
- sprintf(dev->name, "ENET%d", index);
+ sprintf(dev->name, devname);
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
regbase->miimadd = (phyid << 8) | regnum;
regbase->miimcon = value;
- asm("msync");
+ asm("sync");
timeout=1000000;
while((regbase->miimind & MIIMIND_BUSY) && timeout--);
/* Clear the command register, and wait */
regbase->miimcom = 0;
- asm("msync");
+ asm("sync");
/* Initiate a read command, and wait */
regbase->miimcom = MIIM_READ_COMMAND;
- asm("msync");
+ asm("sync");
/* Wait for the the indication that the read is done */
while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
regs->tbipa = TBIPA_VALUE;
regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
regs->tbipa = TBIPA_VALUE;
- asm("msync");
+ asm("sync");
}
/* Reset MII (due to new addresses) */
priv->phyregs->miimcfg = MIIMCFG_RESET;
- asm("msync");
+ asm("sync");
priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
- asm("msync");
+ asm("sync");
while(priv->phyregs->miimind & MIIMIND_BUSY);
if(0 == relocated)
/* For 10/100, the value is slightly different */
uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
{
- if(priv->gigabit)
+ if(priv->flags & TSEC_GIGABIT)
return MIIM_CONTROL_INIT;
else
return MIIM_CR_INIT;
for(phyid=0;phyid<4;phyid++) {
regbase->miimadd = (phyid << 8) | mii_reg;
regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
- asm("msync");
+ asm("sync");
timeout=1000000;
while((regbase->miimind & MIIMIND_BUSY) && timeout--);
return MIIM_CIS8204_SLEDCON_INIT;
}
+uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
+{
+ if (priv->flags & TSEC_REDUCED)
+ return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
+ else
+ return MIIM_CIS8204_EPHYCON_INIT;
+}
/* Initialized required registers to appropriate values, zeroing
* those we don't care about (unless zero is bad, in which case,
case 10:
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
| MACCFG2_MII);
+
+ /* If We're in reduced mode, we need
+ * to say whether we're 10 or 100 MB.
+ */
+ if ((priv->speed == 100)
+ && (priv->flags & TSEC_REDUCED))
+ regs->ecntrl |= ECNTRL_R100;
+ else
+ regs->ecntrl &= ~(ECNTRL_R100);
break;
default:
printf("%s: Speed was bad\n", dev->name);
/* Configure some basic stuff */
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
{MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
- {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL},
+ {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
#define __TSEC_H
#include <net.h>
-#include <mpc85xx.h>
+#include <config.h>
+
+#ifndef CFG_TSEC1_OFFSET
+ #define CFG_TSEC1_OFFSET (0x24000)
+#endif
-#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
#define TSEC_SIZE 0x01000
+/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
+#if defined(CONFIG_MPC85xx)
+ #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
+#elif defined(CONFIG_MPC83XX)
+ #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#endif
+
+
#define MAC_ADDR_LEN 6
/* #define TSEC_TIMEOUT 1000000 */
#define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020
+#define ECNTRL_R100 0x00000008
#define miim_end -2
#define miim_read -1
/* Cicada 8204 Extended PHY Control Register 1 */
#define MIIM_CIS8204_EPHY_CON 0x17
#define MIIM_CIS8204_EPHYCON_INIT 0x0006
+#define MIIM_CIS8204_EPHYCON_RGMII 0x1000
/* Cicada 8204 Serial LED Control Register */
#define MIIM_CIS8204_SLED_CON 0x1b
uint resc00[256];
} tsec_t;
+#define TSEC_GIGABIT (1)
+
+/* This flag currently only has
+ * meaning if we're using the eTSEC */
+#define TSEC_REDUCED (1 << 1)
+
struct tsec_private {
volatile tsec_t *regs;
volatile tsec_t *phyregs;
struct phy_info *phyinfo;
uint phyaddr;
- uint gigabit;
+ u32 flags;
uint link;
uint duplexity;
uint speed;
struct cramfs_super super;
+/* CPU address space offset calculation macro, struct part_info offset is
+ * device address space offset, so we need to shift it by a device start address. */
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
+
static int cramfs_read_super (struct part_info *info)
{
unsigned long root_offset;
/* Read the first block and get the superblock from it */
- memcpy (&super, (void *) info->offset, sizeof (super));
+ memcpy (&super, (void *) PART_OFFSET(info), sizeof (super));
/* Do sanity checks on the superblock */
if (super.magic != CRAMFS_32 (CRAMFS_MAGIC)) {
/* check at 512 byte offset */
- memcpy (&super, (void *) info->offset + 512, sizeof (super));
+ memcpy (&super, (void *) PART_OFFSET(info) + 512, sizeof (super));
if (super.magic != CRAMFS_32 (CRAMFS_MAGIC)) {
printf ("cramfs: wrong magic\n");
return -1;
return 0;
}
-static unsigned long cramfs_resolve (char *begin, unsigned long offset,
+static unsigned long cramfs_resolve (unsigned long begin, unsigned long offset,
unsigned long size, int raw,
char *filename)
{
return 0;
}
-static int cramfs_uncompress (char *begin, unsigned long offset,
+static int cramfs_uncompress (unsigned long begin, unsigned long offset,
unsigned long loadoffset)
{
struct cramfs_inode *inode = (struct cramfs_inode *) (begin + offset);
if (cramfs_read_super (info))
return -1;
- offset = cramfs_resolve (info->offset,
+ offset = cramfs_resolve (PART_OFFSET(info),
CRAMFS_GET_OFFSET (&(super.root)) << 2,
CRAMFS_24 (super.root.size), 0,
strtok (filename, "/"));
if (offset <= 0)
return offset;
- return cramfs_uncompress (info->offset, offset,
+ return cramfs_uncompress (PART_OFFSET(info), offset,
(unsigned long) loadoffset);
}
static int cramfs_list_inode (struct part_info *info, unsigned long offset)
{
struct cramfs_inode *inode = (struct cramfs_inode *)
- (info->offset + offset);
+ (PART_OFFSET(info) + offset);
char *name, str[20];
int namelen, nextoff;
unsigned long size = CRAMFS_24 (inode->size);
char *link = malloc (size);
- if (link != NULL && cramfs_uncompress (info->offset, offset,
+ if (link != NULL && cramfs_uncompress (PART_OFFSET(info), offset,
(unsigned long) link)
== size)
printf (" -> %*.*s\n", (int) size, (int) size, link);
size = CRAMFS_24 (super.root.size);
} else {
/* Resolve the path */
- offset = cramfs_resolve (info->offset,
+ offset = cramfs_resolve (PART_OFFSET(info),
CRAMFS_GET_OFFSET (&(super.root)) <<
2, CRAMFS_24 (super.root.size), 1,
strtok (filename, "/"));
return offset;
/* Resolving was successful. Examine the inode */
- inode = (struct cramfs_inode *) (info->offset + offset);
+ inode = (struct cramfs_inode *) (PART_OFFSET(info) + offset);
if (!S_ISDIR (CRAMFS_16 (inode->mode))) {
/* It's not a directory - list it, and that's that */
return (cramfs_list_inode (info, offset) > 0);
/* List the given directory */
while (inodeoffset < size) {
- inode = (struct cramfs_inode *) (info->offset + offset +
+ inode = (struct cramfs_inode *) (PART_OFFSET(info) + offset +
inodeoffset);
nextoffset = cramfs_list_inode (info, offset + inodeoffset);
int cramfs_check (struct part_info *info)
{
- struct cramfs_super *sb = (struct cramfs_super *) info->offset;
+ struct cramfs_super *sb;
+
+ if (info->dev->id->type != MTD_DEV_TYPE_NOR)
+ return 0;
+ sb = (struct cramfs_super *) PART_OFFSET(info);
if (sb->magic != CRAMFS_32 (CRAMFS_MAGIC)) {
/* check at 512 byte offset */
- sb = (struct cramfs_super *) (info->offset + 512);
- if (sb->magic != CRAMFS_32 (CRAMFS_MAGIC)) {
+ sb = (struct cramfs_super *) (PART_OFFSET(info) + 512);
+ if (sb->magic != CRAMFS_32 (CRAMFS_MAGIC))
return 0;
- }
}
return 1;
}
do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
int dols)
{
+#if CONFIG_NIOS /* NIOS CPU cannot access big automatic arrays */
+ static
+#endif
char fnamecopy[2048];
boot_sector bs;
volume_info volinfo;
# define DEBUGF(fmt,args...)
#endif
-#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
+/* keeps pointer to currentlu processed partition */
+static struct part_info *current_part;
+#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
/*
* Support for jffs2 on top of NAND-flash
*
static u8* nand_cache = NULL;
static u32 nand_cache_off = (u32)-1;
-static int nanddev = 0; /* nand device of current partition */
static int read_nand_cached(u32 off, u32 size, u_char *buf)
{
+ struct mtdids *id = current_part->dev->id;
u32 bytes_read = 0;
size_t retlen;
int cpy_bytes;
}
}
if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE,
- &retlen, nand_cache, nanddev) < 0 ||
- retlen != NAND_CACHE_SIZE) {
+ &retlen, nand_cache, id->num) < 0 ||
+ retlen != NAND_CACHE_SIZE) {
printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
- nand_cache_off, NAND_CACHE_SIZE);
+ nand_cache_off, NAND_CACHE_SIZE);
return -1;
}
}
return bytes_read;
}
-static void *get_fl_mem(u32 off, u32 size, void *ext_buf)
+static void *get_fl_mem_nand(u32 off, u32 size, void *ext_buf)
{
u_char *buf = ext_buf ? (u_char*)ext_buf : (u_char*)malloc(size);
if (NULL == buf) {
- printf("get_fl_mem: can't alloc %d bytes\n", size);
+ printf("get_fl_mem_nand: can't alloc %d bytes\n", size);
return NULL;
}
if (read_nand_cached(off, size, buf) < 0) {
return buf;
}
-static void *get_node_mem(u32 off)
+static void *get_node_mem_nand(u32 off)
{
struct jffs2_unknown_node node;
void *ret = NULL;
- if (NULL == get_fl_mem(off, sizeof(node), &node))
+ if (NULL == get_fl_mem_nand(off, sizeof(node), &node))
return NULL;
- if (!(ret = get_fl_mem(off, node.magic ==
+ if (!(ret = get_fl_mem_nand(off, node.magic ==
JFFS2_MAGIC_BITMASK ? node.totlen : sizeof(node),
NULL))) {
printf("off = %#x magic %#x type %#x node.totlen = %d\n",
return ret;
}
-static void put_fl_mem(void *buf)
+static void put_fl_mem_nand(void *buf)
{
free(buf);
}
+#endif /* #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+/*
+ * Support for jffs2 on top of NOR-flash
+ *
+ * NOR flash memory is mapped in processor's address space,
+ * just return address.
+ */
+static inline void *get_fl_mem_nor(u32 off)
+{
+ u32 addr = off;
+ struct mtdids *id = current_part->dev->id;
+
+ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ flash_info_t *flash = &flash_info[id->num];
+
+ addr += flash->start[0];
+ return (void*)addr;
+}
+
+static inline void *get_node_mem_nor(u32 off)
+{
+ return (void*)get_fl_mem_nor(off);
+}
+#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FLASH) */
-#else /* defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */
+/*
+ * Generic jffs2 raw memory and node read routines.
+ *
+ */
static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf)
{
+ struct mtdids *id = current_part->dev->id;
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+ if (id->type == MTD_DEV_TYPE_NOR)
+ return get_fl_mem_nor(off);
+#endif
+
+#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
+ if (id->type == MTD_DEV_TYPE_NAND)
+ return get_fl_mem_nand(off, size, ext_buf);
+#endif
+
+ printf("get_fl_mem: unknown device type, using raw offset!\n");
return (void*)off;
}
static inline void *get_node_mem(u32 off)
{
+ struct mtdids *id = current_part->dev->id;
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+ if (id->type == MTD_DEV_TYPE_NOR)
+ return get_node_mem_nor(off);
+#endif
+
+#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
+ if (id->type == MTD_DEV_TYPE_NAND)
+ return get_node_mem_nand(off);
+#endif
+
+ printf("get_node_mem: unknown device type, using raw offset!\n");
return (void*)off;
}
static inline void put_fl_mem(void *buf)
{
-}
-
-#endif /* defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */
+#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
+ struct mtdids *id = current_part->dev->id;
+ if (id->type == MTD_DEV_TYPE_NAND)
+ return put_fl_mem_nand(buf);
+#endif
+}
/* Compression names */
static char *compr_names[] = {
static u32
jffs2_scan_empty(u32 start_offset, struct part_info *part)
{
- char *max = part->offset + part->size - sizeof(struct jffs2_raw_inode);
- char *offset = part->offset + start_offset;
+ char *max = (char *)(part->offset + part->size - sizeof(struct jffs2_raw_inode));
+ char *offset = (char *)(part->offset + start_offset);
u32 off;
while (offset < max &&
if (((u32)offset & ((1 << SPIN_BLKSIZE)-1)) == 0) break;
}
- return offset - part->offset;
+ return (u32)offset - part->offset;
}
-static u32
-jffs_init_1pass_list(struct part_info *part)
+void
+jffs2_free_cache(struct part_info *part)
{
struct b_lists *pL;
free_nodes(&pL->dir);
free(pL);
}
+}
+
+static u32
+jffs_init_1pass_list(struct part_info *part)
+{
+ struct b_lists *pL;
+
+ jffs2_free_cache(part);
+
if (NULL != (part->jffs2_priv = malloc(sizeof(struct b_lists)))) {
pL = (struct b_lists *)part->jffs2_priv;
DEBUGF ("rescan: First time in use\n");
return 1;
}
+
/* if we have no list, we need to rescan */
if (pL->frag.listCount == 0) {
DEBUGF ("rescan: fraglist zero\n");
return 1;
}
- /* or if we are scanning a new partition */
- if (pL->partOffset != part->offset) {
- DEBUGF ("rescan: different partition\n");
- return 1;
- }
-
-#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
- if (nanddev != (int)part->usr_priv - 1) {
- DEBUGF ("rescan: nand device changed\n");
- return -1;
- }
-#endif /* defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
/* but suppose someone reflashed a partition at the same offset... */
b = pL->dir.listHead;
while (b) {
u32 counterF = 0;
u32 counterN = 0;
-#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
- nanddev = (int)part->usr_priv - 1;
-#endif /* defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
/* turn off the lcd. Refreshing the lcd adds 50% overhead to the */
/* jffs2 list building enterprise nope. in newer versions the overhead is */
/* only about 5 %. not enough to inconvenience people for. */
/* if we are building a list we need to refresh the cache. */
jffs_init_1pass_list(part);
pL = (struct b_lists *)part->jffs2_priv;
- pL->partOffset = part->offset;
offset = 0;
puts ("Scanning JFFS2 FS: ");
static struct b_lists *
jffs2_get_list(struct part_info * part, const char *who)
{
+ /* copy requested part_info struct pointer to global location */
+ current_part = part;
+
if (jffs2_1pass_rescan_needed(part)) {
if (!jffs2_1pass_build_lists(part)) {
printf("%s: Failed to scan JFFSv2 file structure\n", who);
jffs2_1pass_ls(struct part_info * part, const char *fname)
{
struct b_lists *pl;
- long ret = 0;
+ long ret = 1;
u32 inode;
if (! (pl = jffs2_get_list(part, "ls")))
{
struct b_lists *pl;
- long ret = 0;
+ long ret = 1;
u32 inode;
if (! (pl = jffs2_get_list(part, "load")))
};
struct b_lists {
- char *partOffset;
struct b_list dir;
struct b_list frag;
/*Register addresses */
#if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
+#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
+#endif
#define ZMII_FER (ZMII_BASE)
#define ZMII_SSR (ZMII_BASE + 4)
#define ZMII_SMIISR (ZMII_BASE + 8)
#endif /* CONFIG_440 */
#if defined(CONFIG_440)
-#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
+#else
+#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
+#endif
#else
#define EMAC_BASE 0xEF600800
#endif
#ifndef _440_i2c_h_
#define _440_i2c_h_
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
+#else
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
+#endif /*CONFIG_440EP CONFIG_440GR*/
#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
} EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST;
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#define EMAC_NUM_DEV 4
-#elif defined(CONFIG_440) && !defined(CONFIG_440_GX)
+#elif defined(CONFIG_440) && !defined(CONFIG_440GX)
#define EMAC_NUM_DEV 2
#else
#warning Bad configuration
/*ZMII Bridge Register addresses */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
+#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
+#endif
#define ZMII_FER (ZMII_BASE)
#define ZMII_SSR (ZMII_BASE + 4)
#define ZMII_SMIISR (ZMII_BASE + 8)
/*---------------------------------------------------------------------------+
| TCP/IP Acceleration Hardware (TAH) 440GX Only
+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50)
#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/* Ethernet MAC Regsiter Addresses */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
+#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
+#endif
#define EMAC_M0 (EMAC_BASE)
#define EMAC_M1 (EMAC_BASE + 4)
#define EMAC_M0_RXE (0x08000000)
#define EMAC_M0_WKE (0x04000000)
+/* on 440GX EMAC_MR1 has a different layout! */
+#if defined(CONFIG_440GX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
#define EMAC_M1_OBCI_83 (0x00000010)
#define EMAC_M1_OBCI_66 (0x00000008)
#define EMAC_M1_RSVD1 (0x00000007)
+#else /* defined(CONFIG_440GX) */
+/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
+#define EMAC_M1_FDE 0x80000000
+#define EMAC_M1_ILE 0x40000000
+#define EMAC_M1_VLE 0x20000000
+#define EMAC_M1_EIFC 0x10000000
+#define EMAC_M1_APP 0x08000000
+#define EMAC_M1_AEMI 0x02000000
+#define EMAC_M1_IST 0x01000000
+#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS 0x00400000
+#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K 0x00200000
+#define EMAC_M1_RFS_1K 0x00100000
+#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_1K 0x00040000
+#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
+#define EMAC_M1_TR0_MULTI 0x00008000
+#define EMAC_M1_TR1_DEPEND 0x00004000
+#define EMAC_M1_TR1_MULTI 0x00002000
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define EMAC_M1_JUMBO_ENABLE 0x00001000
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#endif /* defined(CONFIG_440GX) */
+
/* Transmit Mode Register 0 */
#define EMAC_TXM0_GNP0 (0x80000000)
#define EMAC_TXM0_GNP1 (0x40000000)
-/*FIXME: Implement this! */
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_NIOS_IO_H_
+#define __ASM_NIOS_IO_H_
+
+#define readb(addr)\
+ ({unsigned char val;\
+ asm volatile( " pfxio 0 \n"\
+ " ld %0, [%1] \n"\
+ " ext8d %0, %1 \n"\
+ :"=r"(val) : "r" (addr)); val;})
+
+#define readw(addr)\
+ ({unsigned short val;\
+ asm volatile( " pfxio 0 \n"\
+ " ld %0, [%1] \n"\
+ " ext16d %0, %1 \n"\
+ :"=r"(val) : "r" (addr)); val;})
+
+#define readl(addr)\
+ ({unsigned long val;\
+ asm volatile( " pfxio 0 \n"\
+ " ld %0, [%1] \n"\
+ :"=r"(val) : "r" (addr)); val;})
+
+#define writeb(addr,val)\
+ asm volatile ( " fill8 %%r0, %1 \n"\
+ " st8d [%0], %%r0 \n"\
+ : : "r" (addr), "r" (val) : "r0")
+
+#define writew(addr,val)\
+ asm volatile ( " fill16 %%r0, %1 \n"\
+ " st16d [%0], %%r0 \n"\
+ : : "r" (addr), "r" (val) : "r0")
+
+#define writel(addr,val)\
+ asm volatile ( " st [%0], %1 \n"\
+ : : "r" (addr), "r" (val))
+
+#define inb(addr) readb(addr)
+#define inw(addr) readw(addr)
+#define inl(addr) readl(addr)
+#define outb(val,addr) writeb(addr,val)
+#define outw(val,addr) writew(addr,val)
+#define outl(val,addr) writel(addr,val)
+
+static inline void insb (unsigned long port, void *dst, unsigned long count)
+{
+ unsigned char *p = dst;
+ while (count--) *p++ = inb (port);
+}
+static inline void insw (unsigned long port, void *dst, unsigned long count)
+{
+ unsigned short *p = dst;
+ while (count--) *p++ = inw (port);
+}
+static inline void insl (unsigned long port, void *dst, unsigned long count)
+{
+ unsigned long *p = dst;
+ while (count--) *p++ = inl (port);
+}
+
+static inline void outsb (unsigned long port, const void *src, unsigned long count)
+{
+ const unsigned char *p = src;
+ while (count--) outb (*p++, port);
+}
+
+static inline void outsw (unsigned long port, const void *src, unsigned long count)
+{
+ const unsigned short *p = src;
+ while (count--) outw (*p++, port);
+}
+static inline void outsl (unsigned long port, const void *src, unsigned long count)
+{
+ const unsigned long *p = src;
+ while (count--) outl (*p++, port);
+}
+
+#endif /* __ASM_NIOS_IO_H_ */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ * Liberty Eran (liberty@freescale.com)
+ */
+
+#ifndef __E300_H__
+#define __E300_H__
+
+/*
+ * e300 Processor Version & Revision Numbers
+ */
+#define PVR_83xx 0x80830000
+#define PVR_8349_REV10 (PVR_83xx | 0x0010)
+#define PVR_8349_REV11 (PVR_83xx | 0x0011)
+
+/*
+ * Hardware Implementation-Dependent Register 0 (HID0)
+ */
+
+/* #define HID0 1008 already defined in processor.h */
+#define HID0_MASK_MACHINE_CHECK 0x00000000
+#define HID0_ENABLE_MACHINE_CHECK 0x80000000
+
+#define HID0_DISABLE_CACHE_PARITY 0x00000000
+#define HID0_ENABLE_CACHE_PARITY 0x40000000
+
+#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
+
+#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY 0x10000000
+
+#define HID0_CORE_CLK_OUT 0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
+
+#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
+#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
+
+#define HID0_DISABLE_DOSE_MODE 0x00000000
+#define HID0_ENABLE_DOSE_MODE 0x00800000
+
+#define HID0_DISABLE_NAP_MODE 0x00000000
+#define HID0_ENABLE_NAP_MODE 0x00400000
+
+#define HID0_DISABLE_SLEEP_MODE 0x00000000
+#define HID0_ENABLE_SLEEP_MODE 0x00200000
+
+#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
+#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
+
+#define HID0_SOFT_RESET 0x00010000
+
+#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
+
+#define HID0_DISABLE_DATA_CACHE 0x00000000
+#define HID0_ENABLE_DATA_CACHE 0x00004000
+
+#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
+
+#define HID0_LOCK_DATA_CACHE 0x00001000
+
+#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
+
+#define HID0_INVALIDATE_DATA_CACHE 0x00000400
+
+#define HID0_DISABLE_M_BIT 0x00000000
+#define HID0_ENABLE_M_BIT 0x00000080
+
+#define HID0_FBIOB 0x00000010
+
+#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
+
+#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
+#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
+
+/*
+ * Hardware Implementation-Dependent Register 2 (HID2)
+ */
+#define HID2 1011
+
+#define HID2_LET 0x08000000
+#define HID2_HBE 0x00040000
+#define HID2_IWLCK_000 0x00000000 /* no ways locked */
+#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
+#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
+#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
+#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
+#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
+#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
+
+
+/* BAT (block address translation */
+#define BATU_BEPI_MSK 0xfffe0000
+#define BATU_BL_MSK 0x00001ffc
+
+#define BATU_BL_128K 0x00000000
+#define BATU_BL_256K 0x00000004
+#define BATU_BL_512K 0x0000000c
+#define BATU_BL_1M 0x0000001c
+#define BATU_BL_2M 0x0000003c
+#define BATU_BL_4M 0x0000007c
+#define BATU_BL_8M 0x000000fc
+#define BATU_BL_16M 0x000001fc
+#define BATU_BL_32M 0x000003fc
+#define BATU_BL_64M 0x000007fc
+#define BATU_BL_128M 0x00000ffc
+#define BATU_BL_256M 0x00001ffc
+
+#define BATU_VS 0x00000002
+#define BATU_VP 0x00000001
+
+#define BATL_BRPN_MSK 0xfffe0000
+#define BATL_WIMG_MSK 0x00000078
+
+#define BATL_WRITETHROUGH 0x00000040
+#define BATL_CACHEINHIBIT 0x00000020
+#define BATL_MEMCOHERENCE 0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+
+#define BATL_PP_MSK 0x00000003
+#define BATL_PP_00 0x00000000 /* No access */
+#define BATL_PP_01 0x00000001 /* Read-only */
+#define BATL_PP_10 0x00000002 /* Read-write */
+#define BATL_PP_11 0x00000003
+
+#endif /* __E300_H__ */
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+
+#include "asm/types.h"
+
/*
* The following data structure is placed in some memory wich is
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
/* There are many clocks on the MPC8260 - see page 9-5 */
unsigned long vco_out;
unsigned long cpm_clk;
unsigned long scc_clk;
unsigned long brg_clk;
#endif
+#if defined(CONFIG_MPC83XX)
+ /* There are other clocks in the MPC83XX */
+ u32 csb_clk;
+ u32 tsec1_clk;
+ u32 tsec2_clk;
+ u32 core_clk;
+ u32 usbmph_clk;
+ u32 usbdr_clk;
+ u32 i2c_clk;
+ u32 enc_clk;
+ u32 lbiu_clk;
+ u32 lclk_clk;
+ u32 ddr_clk;
+#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
-#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
--- /dev/null
+/*
+ * Freescale I2C Controller
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003, Motorola, Inc.
+ * author: Eran Liberty (liberty@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_I2C_H_
+#define _ASM_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct i2c
+{
+ u8 adr; /**< I2C slave address */
+#define I2C_ADR 0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES ~(I2C_ADR)
+ u8 res0[3];
+ u8 fdr; /**< I2C frequency divider register */
+#define IC2_FDR 0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES ~(IC2_FDR)
+ u8 res1[3];
+ u8 cr; /**< I2C control redister */
+#define I2C_CR_MEN 0x80
+#define I2C_CR_MIEN 0x40
+#define I2C_CR_MSTA 0x20
+#define I2C_CR_MTX 0x10
+#define I2C_CR_TXAK 0x08
+#define I2C_CR_RSTA 0x04
+#define I2C_CR_BCST 0x01
+ u8 res2[3];
+ u8 sr; /**< I2C status register */
+#define I2C_SR_MCF 0x80
+#define I2C_SR_MAAS 0x40
+#define I2C_SR_MBB 0x20
+#define I2C_SR_MAL 0x10
+#define I2C_SR_BCSTM 0x08
+#define I2C_SR_SRW 0x04
+#define I2C_SR_MIF 0x02
+#define I2C_SR_RXAK 0x01
+ u8 res3[3];
+ u8 dr; /**< I2C data register */
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+ u8 res4[3];
+ u8 dfsrr; /**< I2C digital filter sampling rate register */
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+ u8 res5[3];
+ u8 res6[0xE8];
+} i2c_t;
+
+#ifndef CFG_HZ
+#error CFG_HZ is not defined in /include/configs/${BOARD}.h
+#endif
+#define I2C_TIMEOUT (CFG_HZ/4)
+
+#ifndef CFG_IMMRBAR
+#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h
+#endif
+
+#ifndef CFG_I2C_OFFSET
+#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
+#endif
+
+#ifdef CONFIG_MPC8349ADS
+/*
+ * MPC8349 have two i2c bus
+ */
+extern i2c_t * mpc8349_i2c;
+#define I2C mpc8349_i2c
+#else
+#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
+#endif
+
+#define I2C_READ 1
+#define I2C_WRITE 0
+
+#endif /* _ASM_I2C_H_ */
--- /dev/null
+/*
+ * MPC8349 Internal Memory Map
+ * Copyright (c) 2004 Freescale Semiconductor.
+ * Eran Liberty (liberty@freescale.com)
+ *
+ * based on:
+ * - MPC8260 Internal Memory Map
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ * - MPC85xx Internal Memory Map
+ * Copyright(c) 2002,2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ */
+#ifndef __IMMAP_8349__
+#define __IMMAP_8349__
+
+#include <asm/types.h>
+#include <asm/i2c.h>
+
+/*
+ * Local Access Window.
+ */
+typedef struct law8349 {
+ u32 bar; /* LBIU local access window base address register */
+/* Identifies the 20 most-significant address bits of the base of local
+ * access window n. The specified base address should be aligned to the
+ * window size, as defined by LBLAWARn[SIZE].
+ */
+#define LAWBAR_BAR 0xFFFFF000
+#define LAWBAR_RES ~(LAWBAR_BAR)
+ u32 ar; /* LBIU local access window attribute register */
+/*
+ * This Macro were moved into mmu.h
+ */
+#if 0
+/* 0 The local bus local access window n is disabled. 1 The local bus
+ * local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
+ * combine to identify an address range for this window.
+ */
+#define LAWAR_EN 0x80000000
+/* Identifies the size of the window from the starting address. Window
+ * size is 2^(SIZE+1) bytes. 000000\96001010Reserved. Window is
+ * undefined.
+ */
+#define LAWAR_SIZE 0x0000003F
+#define LAWAR_SIZE_4K 0x0000000B
+#define LAWAR_SIZE_8K 0x0000000C
+#define LAWAR_SIZE_16K 0x0000000D
+#define LAWAR_SIZE_32K 0x0000000E
+#define LAWAR_SIZE_64K 0x0000000F
+#define LAWAR_SIZE_128K 0x00000010
+#define LAWAR_SIZE_256K 0x00000011
+#define LAWAR_SIZE_512K 0x00000012
+#define LAWAR_SIZE_1M 0x00000013
+#define LAWAR_SIZE_2M 0x00000014
+#define LAWAR_SIZE_4M 0x00000015
+#define LAWAR_SIZE_8M 0x00000016
+#define LAWAR_SIZE_16M 0x00000017
+#define LAWAR_SIZE_32M 0x00000018
+#define LAWAR_SIZE_64M 0x00000019
+#define LAWAR_SIZE_128M 0x0000001A
+#define LAWAR_SIZE_256M 0x0000001B
+#define LAWAR_SIZE_512M 0x0000001C
+#define LAWAR_SIZE_1G 0x0000001D
+#define LAWAR_SIZE_2G 0x0000001E
+#define LAWAR_RES ~(LAWAR_EN|LAWAR_SIZE)
+#endif
+
+} law8349_t;
+
+/*
+ * System configuration registers.
+ */
+typedef struct sysconf8349 {
+ u32 immrbar; /* Internal memory map base address register */
+ u8 res0[0x04];
+ u32 altcbar; /* Alternate configuration base address register */
+/* Identifies the12 most significant address bits of an alternate base
+ * address used for boot sequencer configuration accesses.
+ */
+#define ALTCBAR_BASE_ADDR 0xFFF00000
+#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
+ u8 res1[0x14];
+ law8349_t lblaw[4]; /* LBIU local access window */
+ u8 res2[0x20];
+ law8349_t pcilaw[2]; /* PCI local access window */
+ u8 res3[0x30];
+ law8349_t ddrlaw[2]; /* DDR local access window */
+ u8 res4[0x50];
+ u32 sgprl; /* System General Purpose Register Low */
+ u32 sgprh; /* System General Purpose Register High */
+ u32 spridr; /* System Part and Revision ID Register */
+#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */
+#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */
+ u8 res5[0x04];
+ u32 spcr; /* System Priority Configuration Register */
+#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */
+#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */
+#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */
+#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */
+#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */
+#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
+#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */
+#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
+#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
+#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
+#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
+ | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
+ | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
+ u32 sicrl; /* System General Purpose Register Low */
+#define SICRL_LDP_A 0x80000000
+#define SICRL_USB0 0x40000000
+#define SICRL_USB1 0x20000000
+#define SICRL_UART 0x0C000000
+#define SICRL_GPIO1_A 0x02000000
+#define SICRL_GPIO1_B 0x01000000
+#define SICRL_GPIO1_C 0x00800000
+#define SICRL_GPIO1_D 0x00400000
+#define SICRL_GPIO1_E 0x00200000
+#define SICRL_GPIO1_F 0x00180000
+#define SICRL_GPIO1_G 0x00040000
+#define SICRL_GPIO1_H 0x00020000
+#define SICRL_GPIO1_I 0x00010000
+#define SICRL_GPIO1_J 0x00008000
+#define SICRL_GPIO1_K 0x00004000
+#define SICRL_GPIO1_L 0x00003000
+#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
+ | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
+ | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
+ | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
+ | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
+ u32 sicrh; /* System General Purpose Register High */
+#define SICRH_DDR 0x80000000
+#define SICRH_TSEC1_A 0x10000000
+#define SICRH_TSEC1_B 0x08000000
+#define SICRH_TSEC1_C 0x04000000
+#define SICRH_TSEC1_D 0x02000000
+#define SICRH_TSEC1_E 0x01000000
+#define SICRH_TSEC1_F 0x00800000
+#define SICRH_TSEC2_A 0x00400000
+#define SICRH_TSEC2_B 0x00200000
+#define SICRH_TSEC2_C 0x00100000
+#define SICRH_TSEC2_D 0x00080000
+#define SICRH_TSEC2_E 0x00040000
+#define SICRH_TSEC2_F 0x00020000
+#define SICRH_TSEC2_G 0x00010000
+#define SICRH_TSEC2_H 0x00008000
+#define SICRH_GPIO2_A 0x00004000
+#define SICRH_GPIO2_B 0x00002000
+#define SICRH_GPIO2_C 0x00001000
+#define SICRH_GPIO2_D 0x00000800
+#define SICRH_GPIO2_E 0x00000400
+#define SICRH_GPIO2_F 0x00000200
+#define SICRH_GPIO2_G 0x00000180
+#define SICRH_GPIO2_H 0x00000060
+#define SICRH_TSOBI1 0x00000002
+#define SICRH_TSOBI2 0x00000001
+#define SICRh_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
+ | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
+ | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
+ | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
+ | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
+ | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
+ | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
+ | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
+ | SICRH_TSOBI2)
+ u8 res6[0xE4];
+} sysconf8349_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt8349 {
+ u8 res0[4];
+ u32 swcrr; /* System watchdog control register */
+ u32 swcnr; /* System watchdog count register */
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES ~(SWCNR_SWCN)
+ u8 res1[2];
+ u16 swsrr; /* System watchdog service register */
+ u8 res2[0xF0];
+} wdt8349_t;
+
+/*
+ * RTC/PIT Module Registers
+ */
+typedef struct rtclk8349 {
+ u32 cnr; /* control register */
+#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */
+#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */
+#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */
+#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */
+#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
+ u32 ldr; /* load register */
+ u32 psr; /* prescale register */
+ u32 ctr; /* register */
+ u32 evr; /* event register */
+#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
+#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
+#define RTEVR_RES ~(EVR_SIF | EVR_AIF)
+ u32 alr; /* alarm register */
+ u8 res0[0xE8];
+} rtclk8349_t;
+
+/*
+ * Global timper module
+ */
+
+typedef struct gtm8349 {
+ u8 cfr1; /* Timer1/2 Configuration */
+#define CFR1_PCAS 0x80 /* Pair Cascade mode */
+#define CFR1_BCM 0x40 /* Backward compatible mode */
+#define CFR1_STP2 0x20 /* Stop timer */
+#define CFR1_RST2 0x10 /* Reset timer */
+#define CFR1_GM2 0x08 /* Gate mode for pin 2 */
+#define CFR1_GM1 0x04 /* Gate mode for pin 1 */
+#define CFR1_STP1 0x02 /* Stop timer */
+#define CFR1_RST1 0x01 /* Reset timer */
+ u8 res0[3];
+ u8 cfr2; /* Timer3/4 Configuration */
+#define CFR2_PCAS 0x80 /* Pair Cascade mode */
+#define CFR2_SCAS 0x40 /* Super Cascade mode */
+#define CFR2_STP4 0x20 /* Stop timer */
+#define CFR2_RST4 0x10 /* Reset timer */
+#define CFR2_GM4 0x08 /* Gate mode for pin 4 */
+#define CFR2_GM3 0x04 /* Gate mode for pin 3 */
+#define CFR2_STP3 0x02 /* Stop timer */
+#define CFR2_RST3 0x01 /* Reset timer */
+ u8 res1[10];
+ u16 mdr1; /* Timer1 Mode Register */
+#define MDR_SPS 0xff00 /* Secondary Prescaler value */
+#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */
+#define MDR_OM 0x0020 /* Output mode */
+#define MDR_ORI 0x0010 /* Output reference interrupt enable */
+#define MDR_FRR 0x0008 /* Free run/restart */
+#define MDR_ICLK 0x0006 /* Input clock source for the timer */
+#define MDR_GE 0x0001 /* Gate enable */
+ u16 mdr2; /* Timer2 Mode Register */
+ u16 rfr1; /* Timer1 Reference Register */
+ u16 rfr2; /* Timer2 Reference Register */
+ u16 cpr1; /* Timer1 Capture Register */
+ u16 cpr2; /* Timer2 Capture Register */
+ u16 cnr1; /* Timer1 Counter Register */
+ u16 cnr2; /* Timer2 Counter Register */
+ u16 mdr3; /* Timer3 Mode Register */
+ u16 mdr4; /* Timer4 Mode Register */
+ u16 rfr3; /* Timer3 Reference Register */
+ u16 rfr4; /* Timer4 Reference Register */
+ u16 cpr3; /* Timer3 Capture Register */
+ u16 cpr4; /* Timer4 Capture Register */
+ u16 cnr3; /* Timer3 Counter Register */
+ u16 cnr4; /* Timer4 Counter Register */
+ u16 evr1; /* Timer1 Event Register */
+ u16 evr2; /* Timer2 Event Register */
+ u16 evr3; /* Timer3 Event Register */
+ u16 evr4; /* Timer4 Event Register */
+#define GTEVR_REF 0x0002 /* Output reference event */
+#define GTEVR_CAP 0x0001 /* Counter Capture event */
+#define GTEVR_RES ~(EVR_CAP|EVR_REF)
+ u16 psr1; /* Timer1 Prescaler Register */
+ u16 psr2; /* Timer2 Prescaler Register */
+ u16 psr3; /* Timer3 Prescaler Register */
+ u16 psr4; /* Timer4 Prescaler Register */
+ u8 res[0xC0];
+} gtm8349_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic8349 {
+ u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */
+#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
+#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
+#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */
+#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */
+#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */
+#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */
+#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
+ u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */
+#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */
+#define SICVR_IVEC 0x0000007f /* Interrupt vector */
+#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
+ u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */
+#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */
+#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */
+#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */
+#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */
+#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */
+#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */
+#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */
+#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */
+#define SIIH_UART1 0x00000080 /* UART1 interrupt */
+#define SIIH_UART2 0x00000040 /* UART2 interrupt */
+#define SIIH_SEC 0x00000020 /* SEC interrupt */
+#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
+#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */
+#define SIIH_SPI 0x00000001 /* SPI interrupt */
+#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
+ | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
+ | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
+ | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
+ | SIIH_I2C2 | SIIH_SPI)
+ u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */
+#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
+#define SIIL_PIT 0x40000000 /* PIT interrupt */
+#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */
+#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */
+#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */
+#define SIIL_MU 0x04000000 /* Message Unit interrupt */
+#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */
+#define SIIL_DMA 0x01000000 /* DMA interrupt */
+#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */
+#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */
+#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */
+#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */
+#define SIIL_DDR 0x00080000 /* DDR interrupt */
+#define SIIL_LBC 0x00040000 /* LBC interrupt */
+#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */
+#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */
+#define SIIL_PMC 0x00008000 /* PMC interrupt */
+#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */
+#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */
+#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
+#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
+#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
+#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
+ | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
+ | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
+ | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
+ | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
+ | SIIL_GTM5 |SIIL_DPTC )
+ u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */
+ u8 res0[8];
+ u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */
+ u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */
+ u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */
+ u8 res1[4];
+ u32 sepnr; /* System External Interrupt Pending Register (SEI) */
+ u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */
+ u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */
+#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
+#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
+#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
+#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
+#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
+#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
+#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
+#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
+#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
+ u32 semsr; /* System External Interrupt Mask Register (SEI) */
+#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */
+#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */
+#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */
+#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */
+#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */
+#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */
+#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */
+#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */
+#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */
+#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
+ | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
+ | SEI_SIRQ0)
+ u32 secnr; /* System External Interrupt Control Register (SECNR) */
+#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */
+#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */
+#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */
+#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */
+#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */
+#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */
+#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */
+#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */
+#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */
+#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */
+#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */
+#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */
+#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
+ | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
+ | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
+ | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
+ u32 sersr; /* System Error Status Register (SERR) */
+ u32 sermr; /* System Error Mask Register (SERR) */
+#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
+#define SERR_WDT 0x40000000 /* WDT MCP request */
+#define SERR_SBA 0x20000000 /* SBA MCP request */
+#define SERR_DDR 0x10000000 /* DDR MCP request */
+#define SERR_LBC 0x08000000 /* LBC MCP request */
+#define SERR_PCI1 0x04000000 /* PCI1 MCP request */
+#define SERR_PCI2 0x02000000 /* PCI2 MCP request */
+#define SERR_MU 0x01000000 /* MU MCP request */
+#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
+#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
+ |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
+ |SERR_RNC )
+ u32 sercr; /* System Error Control Register (SERCR) */
+#define SERCR_MCPR 0x00000001 /* MCP Route */
+#define SERCR_RES ~(SERCR_MCPR)
+ u8 res2[4];
+ u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */
+ u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */
+ u32 sefcr; /* System External Interrupt Force Register (SEI) */
+ u32 serfr; /* System Error Force Register (SERR) */
+ u8 res3[0xA0];
+} ipic8349_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter8349 {
+ u32 acr; /* Arbiter Configuration Register */
+#define ACR_COREDIS 0x10000000 /* Core disable. */
+#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
+#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
+#define ACR_RPTCNT 0x00000700 /* Repeat count. */
+#define ACR_APARK 0x00000030 /* Address parking. */
+#define ACR_PARKM 0x0000000F /* Parking master. */
+#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
+ u32 atr; /* Arbiter Timers Register */
+#define ATR_DTO 0x00FF0000 /* Data time out. */
+#define ATR_ATO 0x000000FF /* Address time out. */
+#define ATR_RES ~(ATR_DTO|ATR_ATO)
+ u8 res[4];
+ u32 aer; /* Arbiter Event Register (AE)*/
+ u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
+ u32 amr; /* Arbiter Mask Register (AE) */
+ u32 aeatr; /* Arbiter Event Attributes Register */
+#define AEATR_EVENT 0x07000000 /* Event type. */
+#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
+#define AEATR_TBST 0x00000800 /* Transfer burst. */
+#define AEATR_TSIZE 0x00000700 /* Transfer Size. */
+#define AEATR_TTYPE 0x0000001F /* Transfer Type. */
+#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
+ u32 aeadr; /* Arbiter Event Address Register */
+ u32 aerr; /* Arbiter Event Response Register (AE)*/
+#define AE_ETEA 0x00000020 /* Transfer error. */
+#define AE_RES_ 0x00000010 /* Reserved transfer type. */
+#define AE_ECW 0x00000008 /* External control word transfer type. */
+#define AE_AO 0x00000004 /* Address Only transfer type. */
+#define AE_DTO 0x00000002 /* Data time out. */
+#define AE_ATO 0x00000001 /* Address time out. */
+#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
+ u8 res1[0xDC];
+} arbiter8349_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset8349 {
+ u32 rcwl; /* RCWL Register */
+#define RCWL_LBIUCM 0x80000000 /* LBIUCM */
+#define RCWL_LBIUCM_SHIFT 31
+#define RCWL_DDRCM 0x40000000 /* DDRCM */
+#define RCWL_DDRCM_SHIFT 30
+#define RCWL_SVCOD 0x30000000 /* SVCOD */
+#define RCWL_SPMF 0x0f000000 /* SPMF */
+#define RCWL_SPMF_SHIFT 24
+#define RCWL_COREPLL 0x007F0000 /* COREPLL */
+#define RCWL_COREPLL_SHIFT 16
+#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
+#define RCWL_CEPDF 0x00000020 /* CEPDF */
+#define RCWL_CEPMF 0x0000001F /* CEPMF */
+#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
+ u32 rcwh; /* RCHL Register */
+#define RCWH_PCIHOST 0x80000000 /* PCIHOST */
+#define RCWH_PCIHOST_SHIFT 31
+#define RCWH_PCI64 0x40000000 /* PCI64 */
+#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */
+#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */
+#define RCWH_COREDIS 0x08000000 /* COREDIS */
+#define RCWH_BMS 0x04000000 /* BMS */
+#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */
+#define RCWH_SWEN 0x00800000 /* SWEN */
+#define RCWH_ROMLOC 0x00700000 /* ROMLOC */
+#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */
+#define RCWH_TSEC2M 0x00003000 /* TSEC2M */
+#define RCWH_TPR 0x00000100 /* TPR */
+#define RCWH_TLE 0x00000008 /* TLE */
+#define RCWH_LALE 0x00000004 /* LALE */
+#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
+ | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
+ | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
+ | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
+ | RCWH_TLE | RCWH_LALE)
+ u8 res0[8];
+ u32 rsr; /* Reset status Register */
+#define RSR_RSTSRC 0xE0000000 /* Reset source */
+#define RSR_RSTSRC_SHIFT 29
+#define RSR_BSF 0x00010000 /* Boot seq. fail */
+#define RSR_BSF_SHIFT 16
+#define RSR_SWSR 0x00002000 /* software soft reset */
+#define RSR_SWSR_SHIFT 13
+#define RSR_SWHR 0x00001000 /* software hard reset */
+#define RSR_SWHR_SHIFT 12
+#define RSR_JHRS 0x00000200 /* jtag hreset */
+#define RSR_JHRS_SHIFT 9
+#define RSR_JSRS 0x00000100 /* jtag sreset status */
+#define RSR_JSRS_SHIFT 8
+#define RSR_CSHR 0x00000010 /* checkstop reset status */
+#define RSR_CSHR_SHIFT 4
+#define RSR_SWRS 0x00000008 /* software watchdog reset status */
+#define RSR_SWRS_SHIFT 3
+#define RSR_BMRS 0x00000004 /* bus monitop reset status */
+#define RSR_BMRS_SHIFT 2
+#define RSR_SRS 0x00000002 /* soft reset status */
+#define RSR_SRS_SHIFT 1
+#define RSR_HRS 0x00000001 /* hard reset status */
+#define RSR_HRS_SHIFT 0
+#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
+ u32 rmr; /* Reset mode Register */
+#define RMR_CSRE 0x00000001 /* checkstop reset enable */
+#define RMR_CSRE_SHIFT 0
+#define RMR_RES ~(RMR_CSRE)
+ u32 rpr; /* Reset protection Register */
+ u32 rcr; /* Reset Control Register */
+#define RCR_SWHR 0x00000002 /* software hard reset */
+#define RCR_SWSR 0x00000001 /* software soft reset */
+#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
+ u32 rcer; /* Reset Control Enable Register */
+#define RCER_CRE 0x00000001 /* software hard reset */
+#define RCER_RES ~(RCER_CRE)
+ u8 res1[0xDC];
+} reset8349_t;
+
+typedef struct clk8349 {
+ u32 spmr; /* system PLL mode Register */
+#define SPMR_LBIUCM 0x80000000 /* LBIUCM */
+#define SPMR_DDRCM 0x40000000 /* DDRCM */
+#define SPMR_SVCOD 0x30000000 /* SVCOD */
+#define SPMR_SPMF 0x0F000000 /* SPMF */
+#define SPMR_CKID 0x00800000 /* CKID */
+#define SPMR_CKID_SHIFT 23
+#define SPMR_COREPLL 0x007F0000 /* COREPLL */
+#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
+#define SPMR_CEPDF 0x00000020 /* CEPDF */
+#define SPMR_CEPMF 0x0000001F /* CEPMF */
+#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
+ | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
+ | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
+ u32 occr; /* output clock control Register */
+#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
+#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
+#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */
+#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */
+#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */
+#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */
+#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */
+#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */
+#define OCCR_PCICD0 0x00800000 /* PCICD0 */
+#define OCCR_PCICD1 0x00400000 /* PCICD1 */
+#define OCCR_PCICD2 0x00200000 /* PCICD2 */
+#define OCCR_PCICD3 0x00100000 /* PCICD3 */
+#define OCCR_PCICD4 0x00080000 /* PCICD4 */
+#define OCCR_PCICD5 0x00040000 /* PCICD5 */
+#define OCCR_PCICD6 0x00020000 /* PCICD6 */
+#define OCCR_PCICD7 0x00010000 /* PCICD7 */
+#define OCCR_PCI1CR 0x00000002 /* PCI1CR */
+#define OCCR_PCI2CR 0x00000001 /* PCI2CR */
+#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
+ | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
+ | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
+ | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \
+ | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \
+ | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR )
+ u32 sccr; /* system clock control Register */
+#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */
+#define SCCR_TSEC2CM_SHIFT 28
+#define SCCR_ENCCM 0x03000000 /* ENCCM */
+#define SCCR_ENCCM_SHIFT 24
+#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */
+#define SCCR_USBMPHCM_SHIFT 22
+#define SCCR_USBDRCM 0x00300000 /* USBDRCM */
+#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_PCICM 0x00010000 /* PCICM */
+#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
+ | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
+ u8 res0[0xF4];
+} clk8349_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc8349 {
+ u32 pmccr; /* PMC Configuration Register */
+#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
+#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
+#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
+ u32 pmcer; /* PMC Event Register */
+#define PMCER_PMCI 0x00000001 /* PMC Interrupt */
+#define PMCER_RES ~(PMCER_PMCI)
+ u32 pmcmr; /* PMC Mask Register */
+#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
+#define PMCMR_RES ~(PMCMR_PMCIE)
+ u8 res0[0xF4];
+} pmc8349_t;
+
+
+/*
+ * general purpose I/O module
+ */
+typedef struct gpio8349 {
+ u32 dir; /* direction register */
+ u32 odr; /* open drain register */
+ u32 dat; /* data register */
+ u32 ier; /* interrupt event register */
+ u32 imr; /* interrupt mask register */
+ u32 icr; /* external interrupt control register */
+ u8 res0[0xE8];
+} gpio8349_t;
+
+/*
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr_cs_bnds{
+ u32 csbnds;
+#define CSBNDS_SA 0x00FF0000
+#define CSBNDS_SA_SHIFT 16
+#define CSBNDS_EA 0x000000FF
+#define CSBNDS_EA_SHIFT 0
+ u8 res0[4];
+} ddr_cs_bnds_t;
+
+typedef struct ddr8349{
+ ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */
+ u8 res0[0x60];
+ u32 cs_config[4]; /**< Chip Select x Configuration */
+#define CSCONFIG_EN 0x80000000
+#define CSCONFIG_AP 0x00800000
+#define CSCONFIG_ROW_BIT 0x00000700
+#define CSCONFIG_ROW_BIT_12 0x00000000
+#define CSCONFIG_ROW_BIT_13 0x00000100
+#define CSCONFIG_ROW_BIT_14 0x00000200
+#define CSCONFIG_COL_BIT 0x00000007
+#define CSCONFIG_COL_BIT_8 0x00000000
+#define CSCONFIG_COL_BIT_9 0x00000001
+#define CSCONFIG_COL_BIT_10 0x00000002
+#define CSCONFIG_COL_BIT_11 0x00000003
+ u8 res1[0x78];
+ u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */
+#define TIMING_CFG1_PRETOACT 0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT 28
+#define TIMING_CFG1_ACTTOPRE 0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT 24
+#define TIMING_CFG1_ACTTORW 0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT 20
+#define TIMING_CFG1_CASLAT 0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT 16
+#define TIMING_CFG1_REFREC 0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT 12
+#define TIMING_CFG1_WRREC 0x00000700
+#define TIMING_CFG1_WRREC_SHIFT 8
+#define TIMING_CFG1_ACTTOACT 0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT 4
+#define TIMING_CFG1_WRTORD 0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT 0
+
+ u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
+#define TIMING_CFG2_CPO 0x0F000000
+#define TIMING_CFG2_CPO_SHIFT 24
+#define TIMING_CFG2_ACSM 0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
+
+ u32 sdram_cfg; /**< SDRAM Control Configuration */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_32_BE 0x00080000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_NCAP 0x00020000
+#define SDRAM_CFG_2T_EN 0x00008000
+
+ u8 res2[4];
+ u32 sdram_mode; /**< SDRAM Mode Configuration */
+#define SDRAM_MODE_ESD 0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT 16
+#define SDRAM_MODE_SD 0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT 0
+
+ u8 res3[8];
+ u32 sdram_interval; /**< SDRAM Interval Configuration */
+#define SDRAM_INTERVAL_REFINT 0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT 16
+#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
+ u8 res9[8];
+ u32 sdram_clk_cntl;
+ u8 res4[0xCCC];
+ u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
+ u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
+ u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */
+ u8 res5[0x14];
+ u32 capture_data_hi; /**< Memory Data Path Read Capture High */
+ u32 capture_data_lo; /**< Memory Data Path Read Capture Low */
+ u32 capture_ecc; /**< Memory Data Path Read Capture ECC */
+ u8 res6[0x14];
+ u32 err_detect; /**< Memory Error Detect */
+ u32 err_disable; /**< Memory Error Disable */
+ u32 err_int_en; /**< Memory Error Interrupt Enable */
+ u32 capture_attributes; /**< Memory Error Attributes Capture */
+ u32 capture_address; /**< Memory Error Address Capture */
+ u32 capture_ext_address;/**< Memory Error Extended Address Capture */
+ u32 err_sbe; /**< Memory Single-Bit ECC Error Management */
+ u8 res7[0xA4];
+ u32 debug_reg;
+ u8 res8[0xFC];
+} ddr8349_t;
+
+/*
+ * I2C1 Controller
+ */
+
+
+/*
+ * DUART
+ */
+typedef struct duart8349{
+ u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
+ u8 uier_udmb; /**< combined register for UIER and UDMB */
+ u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
+ u8 ulcr; /**< line control register */
+ u8 umcr; /**< MODEM control register */
+ u8 ulsr; /**< line status register */
+ u8 umsr; /**< MODEM status register */
+ u8 uscr; /**< scratch register */
+ u8 res0[8];
+ u8 udsr; /**< DMA status register */
+ u8 res1[3];
+ u8 res2[0xEC];
+} duart8349_t;
+
+/*
+ * Local Bus Controller Registers
+ */
+typedef struct lbus_bank{
+ u32 br; /**< Base Register */
+ u32 or; /**< Base Register */
+} lbus_bank_t;
+
+typedef struct lbus8349 {
+ lbus_bank_t bank[8];
+ u8 res0[0x28];
+ u32 mar; /**< UPM Address Register */
+ u8 res1[0x4];
+ u32 mamr; /**< UPMA Mode Register */
+ u32 mbmr; /**< UPMB Mode Register */
+ u32 mcmr; /**< UPMC Mode Register */
+ u8 res2[0x8];
+ u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
+ u32 mdr; /**< UPM Data Register */
+ u8 res3[0x8];
+ u32 lsdmr; /**< SDRAM Mode Register */
+ u8 res4[0x8];
+ u32 lurt; /**< UPM Refresh Timer */
+ u32 lsrt; /**< SDRAM Refresh Timer */
+ u8 res5[0x8];
+ u32 ltesr; /**< Transfer Error Status Register */
+ u32 ltedr; /**< Transfer Error Disable Register */
+ u32 lteir; /**< Transfer Error Interrupt Register */
+ u32 lteatr; /**< Transfer Error Attributes Register */
+ u32 ltear; /**< Transfer Error Address Register */
+ u8 res6[0xC];
+ u32 lbcr; /**< Configuration Register */
+#define LBCR_LDIS 0x80000000
+#define LBCR_LDIS_SHIFT 31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT 22
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT 17
+#define LBCR_EPAR 0x00010000
+#define LBCR_EPAR_SHIFT 16
+#define LBCR_BMT 0x0000FF00
+#define LBCR_BMT_SHIFT 8
+ u32 lcrr; /**< Clock Ratio Register */
+#define LCRR_DBYP 0x80000000
+#define LCRR_DBYP_SHIFT 31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT 28
+#define LCRR_ECL 0x03000000
+#define LCRR_ECL_SHIFT 24
+#define LCRR_EADC 0x00030000
+#define LCRR_EADC_SHIFT 16
+#define LCRR_CLKDIV 0x0000000F
+#define LCRR_CLKDIV_SHIFT 0
+
+
+ u8 res7[0x28];
+ u8 res8[0xF00];
+} lbus8349_t;
+
+/*
+ * Serial Peripheral Interface
+ */
+typedef struct spi8349
+{
+ u32 mode; /**< mode register */
+ u32 event; /**< event register */
+ u32 mask; /**< mask register */
+ u32 com; /**< command register */
+ u8 res0[0x10];
+ u32 tx; /**< transmit register */
+ u32 rx; /**< receive register */
+ u8 res1[0xD8];
+} spi8349_t;
+
+typedef struct dma8349 {
+ u8 fixme[0x300];
+} dma8349_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf8349 {
+ u32 config_address;
+#define PCI_CONFIG_ADDRESS_EN 0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
+#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
+#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
+#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
+#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
+ u32 config_data;
+ u32 int_ack;
+ u8 res[116];
+} pciconf8349_t;
+
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+ u32 potar;
+ u8 res0[4];
+ u32 pobar;
+ u8 res1[4];
+ u32 pocmr;
+ u8 res2[4];
+} pot8349_t;
+/*
+ * Sequencer
+ */
+typedef struct ios8349 {
+ pot8349_t pot[6];
+#define POTAR_TA_MASK 0x000fffff
+#define POBAR_BA_MASK 0x000fffff
+#define POCMR_EN 0x80000000
+#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
+#define POCMR_SE 0x20000000 /* streaming enable */
+#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2*/
+#define POCMR_CM_MASK 0x000fffff
+#define POCMR_CM_4G 0x00000000
+#define POCMR_CM_2G 0x00080000
+#define POCMR_CM_1G 0x000C0000
+#define POCMR_CM_512M 0x000E0000
+#define POCMR_CM_256M 0x000F0000
+#define POCMR_CM_128M 0x000F8000
+#define POCMR_CM_64M 0x000FC000
+#define POCMR_CM_32M 0x000FE000
+#define POCMR_CM_16M 0x000FF000
+#define POCMR_CM_8M 0x000FF800
+#define POCMR_CM_4M 0x000FFC00
+#define POCMR_CM_2M 0x000FFE00
+#define POCMR_CM_1M 0x000FFF00
+#define POCMR_CM_512K 0x000FFF80
+#define POCMR_CM_256K 0x000FFFC0
+#define POCMR_CM_128K 0x000FFFE0
+#define POCMR_CM_64K 0x000FFFF0
+#define POCMR_CM_32K 0x000FFFF8
+#define POCMR_CM_16K 0x000FFFFC
+#define POCMR_CM_8K 0x000FFFFE
+#define POCMR_CM_4K 0x000FFFFF
+ u8 res0[0x60];
+ u32 pmcr;
+ u8 res1[4];
+ u32 dtcr;
+ u8 res2[4];
+} ios8349_t;
+
+/*
+ * PCI Controller Control and Status Registers
+ */
+typedef struct pcictrl8349 {
+ u32 esr;
+#define ESR_MERR 0x80000000
+#define ESR_APAR 0x00000400
+#define ESR_PCISERR 0x00000200
+#define ESR_MPERR 0x00000100
+#define ESR_TPERR 0x00000080
+#define ESR_NORSP 0x00000040
+#define ESR_TABT 0x00000020
+ u32 ecdr;
+#define ECDR_APAR 0x00000400
+#define ECDR_PCISERR 0x00000200
+#define ECDR_MPERR 0x00000100
+#define ECDR_TPERR 0x00000080
+#define ECDR_NORSP 0x00000040
+#define ECDR_TABT 0x00000020
+ u32 eer;
+#define EER_APAR 0x00000400
+#define EER_PCISERR 0x00000200
+#define EER_MPERR 0x00000100
+#define EER_TPERR 0x00000080
+#define EER_NORSP 0x00000040
+#define EER_TABT 0x00000020
+ u32 eatcr;
+#define EATCR_ERRTYPR_MASK 0x70000000
+#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */
+#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */
+#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */
+#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */
+#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */
+#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */
+#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */
+#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */
+#define EATCR_BN_MASK 0x0f000000 /* beat number */
+#define EATCR_BN_1st 0x00000000
+#define EATCR_BN_2ed 0x01000000
+#define EATCR_BN_3rd 0x02000000
+#define EATCR_BN_4th 0x03000000
+#define EATCR_BN_5th 0x0400000
+#define EATCR_BN_6th 0x05000000
+#define EATCR_BN_7th 0x06000000
+#define EATCR_BN_8th 0x07000000
+#define EATCR_BN_9th 0x08000000
+#define EATCR_TS_MASK 0x00300000 /* transaction size */
+#define EATCR_TS_4 0x00000000
+#define EATCR_TS_1 0x00100000
+#define EATCR_TS_2 0x00200000
+#define EATCR_TS_3 0x00300000
+#define EATCR_ES_MASK 0x000f0000 /* error source */
+#define EATCR_ES_EM 0x00000000 /* external master */
+#define EATCR_ES_DMA 0x00050000
+#define EATCR_CMD_MASK 0x0000f000
+#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/
+#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */
+#define EATCR_HPB 0x00000004 /* high parity bit */
+#define EATCR_PB 0x00000002 /* parity bit*/
+#define EATCR_VI 0x00000001 /* error information valid */
+ u32 eacr;
+ u32 eeacr;
+ u32 edlcr;
+ u32 edhcr;
+ u32 gcr;
+ u32 ecr;
+ u32 gsr;
+ u8 res0[12];
+ u32 pitar2;
+ u8 res1[4];
+ u32 pibar2;
+ u32 piebar2;
+ u32 piwar2;
+ u8 res2[4];
+ u32 pitar1;
+ u8 res3[4];
+ u32 pibar1;
+ u32 piebar1;
+ u32 piwar1;
+ u8 res4[4];
+ u32 pitar0;
+ u8 res5[4];
+ u32 pibar0;
+ u8 res6[4];
+ u32 piwar0;
+ u8 res7[132];
+#define PITAR_TA_MASK 0x000fffff
+#define PIBAR_MASK 0xffffffff
+#define PIEBAR_EBA_MASK 0x000fffff
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_RTT_MASK 0x000f0000
+#define PIWAR_RTT_NO_SNOOP 0x00040000
+#define PIWAR_RTT_SNOOP 0x00050000
+#define PIWAR_WTT_MASK 0x0000f000
+#define PIWAR_WTT_NO_SNOOP 0x00004000
+#define PIWAR_WTT_SNOOP 0x00005000
+#define PIWAR_IWS_MASK 0x0000003F
+#define PIWAR_IWS_4K 0x0000000B
+#define PIWAR_IWS_8K 0x0000000C
+#define PIWAR_IWS_16K 0x0000000D
+#define PIWAR_IWS_32K 0x0000000E
+#define PIWAR_IWS_64K 0x0000000F
+#define PIWAR_IWS_128K 0x00000010
+#define PIWAR_IWS_256K 0x00000011
+#define PIWAR_IWS_512K 0x00000012
+#define PIWAR_IWS_1M 0x00000013
+#define PIWAR_IWS_2M 0x00000014
+#define PIWAR_IWS_4M 0x00000015
+#define PIWAR_IWS_8M 0x00000016
+#define PIWAR_IWS_16M 0x00000017
+#define PIWAR_IWS_32M 0x00000018
+#define PIWAR_IWS_64M 0x00000019
+#define PIWAR_IWS_128M 0x0000001A
+#define PIWAR_IWS_256M 0x0000001B
+#define PIWAR_IWS_512M 0x0000001C
+#define PIWAR_IWS_1G 0x0000001D
+#define PIWAR_IWS_2G 0x0000001E
+} pcictrl8349_t;
+
+/*
+ * USB
+ */
+typedef struct usb8349 {
+ u8 fixme[0x2000];
+} usb8349_t;
+
+/*
+ * TSEC
+ */
+typedef struct tsec8349 {
+ u8 fixme[0x1000];
+} tsec8349_t;
+
+/*
+ * Security
+ */
+typedef struct security8349 {
+ u8 fixme[0x10000];
+} security8349_t;
+
+typedef struct immap {
+ sysconf8349_t sysconf; /* System configuration */
+ wdt8349_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk8349_t rtc; /* Real Time Clock Module Registers */
+ rtclk8349_t pit; /* Periodic Interval Timer */
+ gtm8349_t gtm[2]; /* Global Timers Module */
+ ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter8349_t arbiter; /* System Arbiter Registers */
+ reset8349_t reset; /* Reset Module */
+ clk8349_t clk; /* System Clock Module */
+ pmc8349_t pmc; /* Power Management Control Module */
+ gpio8349_t pgio[2]; /* general purpose I/O module */
+ u8 res0[0x200];
+ u8 DDL_DDR[0x100];
+ u8 DDL_LBIU[0x100];
+ u8 res1[0xE00];
+ ddr8349_t ddr; /* DDR Memory Controller Memory */
+ i2c_t i2c[2]; /* I2C1 Controller */
+ u8 res2[0x1300];
+ duart8349_t duart[2];/* DUART */
+ u8 res3[0x900];
+ lbus8349_t lbus; /* Local Bus Controller Registers */
+ u8 res4[0x1000];
+ spi8349_t spi; /* Serial Peripheral Interface */
+ u8 res5[0xF00];
+ dma8349_t dma; /* DMA */
+ pciconf8349_t pci_conf[2]; /* PCI Software Configuration Registers */
+ ios8349_t ios; /* Sequencer */
+ pcictrl8349_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
+ u8 res6[0x19900];
+ usb8349_t usb;
+ tsec8349_t tsec[2];
+ u8 res7[0xA000];
+ security8349_t security;
+} immap_t;
+
+#endif /* __IMMAP_8349__ */
#ifndef __IMMAP_85xx__
#define __IMMAP_85xx__
-
-/* Local-Access Registers and ECM Registers(0x0000-0x2000) */
-
+/*
+ * Local-Access Registers and ECM Registers(0x0000-0x2000)
+ */
typedef struct ccsr_local_ecm {
uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
char res1[4];
char res24[492];
} ccsr_local_ecm_t;
-
-/* DDR memory controller registers(0x2000-0x3000) */
-
+/*
+ * DDR memory controller registers(0x2000-0x3000)
+ */
typedef struct ccsr_ddr {
uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
char res1[4];
uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
- char res5[120];
+ char res5[112];
+ uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
- char res6[4];
+ uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
- char res7[8];
+ uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
+ uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
- char res7_5[8];
+ uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
+ char res6[4];
uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
- char res8[3276];
-#else
- char res8[3288];
-#endif
+ char res7[20];
+ uint init_address; /* 0x2148 - DDR training initialization address */
+ uint init_ext_address; /* 0x214C - DDR training initialization extended address */
+ char res8_1[2728];
+ uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
+ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
+ char res8_2[512];
uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
char res12[240];
} ccsr_ddr_t;
-
-/* I2C Registers(0x3000-0x4000) */
-
+/*
+ * I2C Registers(0x3000-0x4000)
+ */
typedef struct ccsr_i2c {
u_char i2cadr; /* 0x3000 - I2C Address Register */
#define MPC85xx_I2CADR_MASK 0xFE
#if defined(CONFIG_MPC8540) \
|| defined(CONFIG_MPC8541) \
+ || defined(CONFIG_MPC8548) \
|| defined(CONFIG_MPC8555)
/* DUART Registers(0x4000-0x5000) */
typedef struct ccsr_duart {
char res8[12072];
} ccsr_lbc_t;
-
-/* PCI Registers(0x8000-0x9000) */
-/* Omitting Reserved(0x9000-0x2_0000) */
-
+/*
+ * PCI Registers(0x8000-0x9000)
+ * Omitting Reserved(0x9000-0x2_0000)
+ */
typedef struct ccsr_pcix {
uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
char res11[94688];
} ccsr_pcix_t;
-
-/* L2 Cache Registers(0x2_0000-0x2_1000) */
-
+/*
+ * L2 Cache Registers(0x2_0000-0x2_1000)
+ */
typedef struct ccsr_l2cache {
uint l2ctl; /* 0x20000 - L2 configuration register 0 */
char res1[12];
char res15[420];
} ccsr_l2cache_t;
-
-/* DMA Registers(0x2_1000-0x2_2000) */
-
+/*
+ * DMA Registers(0x2_1000-0x2_2000)
+ */
typedef struct ccsr_dma {
char res1[256];
uint mr0; /* 0x21100 - DMA 0 Mode Register */
char res22[11516];
} ccsr_dma_t;
-/* tsec1 tsec2: 24000-26000 */
+/*
+ * tsec1 tsec2: 24000-26000
+ */
typedef struct ccsr_tsec {
char res1[16];
uint ievent; /* 0x24010 - Interrupt Event Register */
char res74[1024];
} ccsr_tsec_t;
-/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */
-
+/*
+ * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
+ */
typedef struct ccsr_pic {
char res0[106496]; /* 0x26000-0x40000 */
char res1[64];
char res150[130892];
} ccsr_pic_t;
-/* CPM Block(0x8_0000-0xc_0000) */
-#if defined(CONFIG_MPC8540) \
- || defined(CONFIG_MPC8541) \
- || defined(CONFIG_MPC8555)
+/*
+ * CPM Block(0x8_0000-0xc_0000)
+ */
+#ifndef CONFIG_CPM2
typedef struct ccsr_cpm {
char res[262144];
} ccsr_cpm_t;
#else
-/* 0x8000-0x8ffff:DPARM */
-
-/* 0x9000-0x90bff: General SIU */
+/*
+ * 0x8000-0x8ffff:DPARM
+ * 0x9000-0x90bff: General SIU
+ */
typedef struct ccsr_cpm_siu {
char res1[80];
uint smaer;
char res1[16*1024];
u_char im_dpram2[16*1024];
char res2[16*1024];
-
ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
ccsr_cpm_iram_t im_cpm_iram;
} ccsr_cpm_t;
#endif
-/* RapidIO Registers(0xc_0000-0xe_0000) */
+/*
+ * RapidIO Registers(0xc_0000-0xe_0000)
+ */
typedef struct ccsr_rio {
uint didcar; /* 0xc0000 - Device Identity Capability Register */
uint dicar; /* 0xc0004 - Device Information Capability Register */
char res58[60176];
} ccsr_rio_t;
-/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+/*
+ * Global Utilities Register Block(0xe_0000-0xf_ffff)
+ */
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
char res12[12];
uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
- char res13[61915];
+ char res13[248];
+ uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
+ uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
+ uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
+ uint res14; /* 0xe0f28 */
+ uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
+ char res15[61651];
} ccsr_gur_t;
typedef struct immap {
--- /dev/null
+#ifndef _PPC_KERNEL_MPC8349_PCI_H
+#define _PPC_KERNEL_MPC8349_PCI_H
+
+
+#define M8265_PCIBR0 0x101ac
+#define M8265_PCIBR1 0x101b0
+#define M8265_PCIMSK0 0x101c4
+#define M8265_PCIMSK1 0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE 0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
+#define PCIMSK_64KB 0xFFFF0000
+#define PCIMSK_128KB 0xFFFE0000
+#define PCIMSK_256KB 0xFFFC0000
+#define PCIMSK_512KB 0xFFF80000
+#define PCIMSK_1MB 0xFFF00000
+#define PCIMSK_2MB 0xFFE00000
+#define PCIMSK_4MB 0xFFC00000
+#define PCIMSK_8MB 0xFF800000
+#define PCIMSK_16MB 0xFF000000
+#define PCIMSK_32MB 0xFE000000
+#define PCIMSK_64MB 0xFC000000
+#define PCIMSK_128MB 0xF8000000
+#define PCIMSK_256MB 0xF0000000
+#define PCIMSK_512MB 0xE0000000
+#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus
+ * (local) addresses are translated to PCI addresses when the MPC826x is
+ * a PCI bus master (initiator).
+ */
+
+#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1 0x10818
+#define POTAR_REG2 0x10830
+
+#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
+#define POBAR_REG1 0x10820
+#define POBAR_REG2 0x10838
+
+#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1 0x10828
+#define POCMR_REG2 0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB 0x000FFFFF
+#define POCMR_MASK_8KB 0x000FFFFE
+#define POCMR_MASK_16KB 0x000FFFFC
+#define POCMR_MASK_32KB 0x000FFFF8
+#define POCMR_MASK_64KB 0x000FFFF0
+#define POCMR_MASK_128KB 0x000FFFE0
+#define POCMR_MASK_256KB 0x000FFFC0
+#define POCMR_MASK_512KB 0x000FFF80
+#define POCMR_MASK_1MB 0x000FFF00
+#define POCMR_MASK_2MB 0x000FFE00
+#define POCMR_MASK_4MB 0x000FFC00
+#define POCMR_MASK_8MB 0x000FF800
+#define POCMR_MASK_16MB 0x000FF000
+#define POCMR_MASK_32MB 0x000FE000
+#define POCMR_MASK_64MB 0x000FC000
+#define POCMR_MASK_128MB 0x000F8000
+#define POCMR_MASK_256MB 0x000F0000
+#define POCMR_MASK_512MB 0x000E0000
+#define POCMR_MASK_1GB 0x000C0000
+
+#define POCMR_ENABLE 0x80000000
+#define POCMR_PCI_IO 0x40000000
+#define POCMR_PREFETCH_EN 0x20000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG 0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN 0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI
+ * addresses are translated to 60x bus (local) addresses when the
+ * MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1 0x108D0
+#define PIBAR_REG1 0x108D8
+#define PICMR_REG1 0x108E0
+#define PITAR_REG0 0x108E8
+#define PIBAR_REG0 0x108F0
+#define PICMR_REG0 0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB 0x000FFFFF
+#define PICMR_MASK_8KB 0x000FFFFE
+#define PICMR_MASK_16KB 0x000FFFFC
+#define PICMR_MASK_32KB 0x000FFFF8
+#define PICMR_MASK_64KB 0x000FFFF0
+#define PICMR_MASK_128KB 0x000FFFE0
+#define PICMR_MASK_256KB 0x000FFFC0
+#define PICMR_MASK_512KB 0x000FFF80
+#define PICMR_MASK_1MB 0x000FFF00
+#define PICMR_MASK_2MB 0x000FFE00
+#define PICMR_MASK_4MB 0x000FFC00
+#define PICMR_MASK_8MB 0x000FF800
+#define PICMR_MASK_16MB 0x000FF000
+#define PICMR_MASK_32MB 0x000FE000
+#define PICMR_MASK_64MB 0x000FC000
+#define PICMR_MASK_128MB 0x000F8000
+#define PICMR_MASK_256MB 0x000F0000
+#define PICMR_MASK_512MB 0x000E0000
+#define PICMR_MASK_1GB 0x000C0000
+
+#define PICMR_ENABLE 0x80000000
+#define PICMR_NO_SNOOP_EN 0x40000000
+#define PICMR_PREFETCH_EN 0x20000000
+
+/* PCI error Registers */
+
+#define PCI_ERROR_STATUS_REG 0x10884
+#define PCI_ERROR_MASK_REG 0x10888
+#define PCI_ERROR_CONTROL_REG 0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
+
+/* PCI error Register bit defines */
+
+#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
+#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
+#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
+#define PCI_ERROR_PCI_NO_RSP 0x00000008
+#define PCI_ERROR_PCI_TAR_ABT 0x00000010
+#define PCI_ERROR_PCI_SERR 0x00000020
+#define PCI_ERROR_PCI_PERR_RD 0x00000040
+#define PCI_ERROR_PCI_PERR_WR 0x00000080
+#define PCI_ERROR_I2O_OFQO 0x00000100
+#define PCI_ERROR_I2O_IPQO 0x00000200
+#define PCI_ERROR_IRA 0x00000400
+#define PCI_ERROR_NMI 0x00000800
+#define PCI_ERROR_I2O_DBMC 0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG 0x10900
+#define PCI_CFG_DATA_REG 0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI 0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT 15
+#define HID0_DCE_SHIFT 14
+#define HID0_DLOCK_SHIFT 12
+
#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
#define HID0_NAP (1<<22)
#define HID0_SLEEP (1<<21)
#define HID0_DPM (1<<20)
-#define HID0_ICE (1<<15) /* Instruction Cache Enable */
-#define HID0_DCE (1<<14) /* Data Cache Enable */
+#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
+#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
-#define HID0_DLOCK (1<<12) /* Data Cache Lock */
+#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
#define HID0_DCI HID0_DCFI
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
+#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
#define MAS4 SPRN_MAS4
#define MAS5 SPRN_MAS5
#define MAS6 SPRN_MAS6
+#define MAS7 SPRN_MAS7
/* Device Control Registers */
#define PVR_405GPR_RB 0x50910951
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
+#define PVR_440EP_RA 0x42221850
+#define PVR_440EP_RB 0x422218D3
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892
#define SVR_8560 0x8070
#define SVR_8555 0x8079
#define SVR_8541 0x807A
+#define SVR_8548 0x8031
+#define SVR_8548_E 0x8039
/* I am just adding a single entry for 8260 boards. I think we may be
#if defined(CONFIG_MPC5xxx)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
+#if defined(CONFIG_MPC83XX)
+ unsigned long bi_immrbar;
+#endif
#if defined(CONFIG_MPC8220)
unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_inpfreq; /* Input Freq, In MHz */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
unsigned char bi_enet3addr[6];
#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ int bi_phynum[2]; /* Determines phy mapping */
+ int bi_phymode[2]; /* Determines phy mode */
+#endif
+#if defined(CONFIG_440GX)
int bi_phynum[4]; /* Determines phy mapping */
int bi_phymode[4]; /* Determines phy mode */
#endif
#include <mpc85xx.h>
#include <asm/immap_85xx.h>
#endif
+#ifdef CONFIG_MPC83XX
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
#ifdef CONFIG_4xx
#include <ppc4xx.h>
#endif
#endif
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \
- defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K)
+ defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \
+ defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
void board_get_enetaddr (uchar *addr);
#endif
int adjust_sdram_tbs_8xx (void);
#if defined(CONFIG_8260)
int prt_8260_clks (void);
-#endif
-#if defined(CONFIG_MPC5xxx)
+#elif defined(CONFIG_MPC83XX)
+int print_clock_conf(void);
+#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
#if defined(CONFIG_MPC8220)
#undef CFG_MEMTEST_END
#endif
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
#endif /* __CONFIG_H */
#undef CFG_ENV_IS_IN_FLASH
#endif
-#ifndef CFG_JFFS2_FIRST_SECTOR
-#define CFG_JFFS2_FIRST_SECTOR 0
-#endif
-#ifndef CFG_JFFS2_FIRST_BANK
-#define CFG_JFFS2_FIRST_BANK 0
-#endif
-#ifndef CFG_JFFS2_NUM_BANKS
-#define CFG_JFFS2_NUM_BANKS 1
-#endif
-#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
-
/*
* Memory map
*/
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+/*
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0x00400000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+*/
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=alaska-0"
+#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
+*/
+
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/processor.h>
-
#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=bab7xx-0"
+#define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)"
+*/
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */
+#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
+#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
#else
#define CONFIG_PHY_ADDR 2 /* PHY address */
#endif
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
#endif /* CONFIG_NO_SERIAL_EEPROM */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand"
+#define CONFIG_JFFS2_PART_SIZE 0x00200000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nand0=catcenter"
+#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
+*/
+
#endif /* __CONFIG_H */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
+
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition, use whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=cpci4052-0"
+#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)"
+*/
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=cpci405ab-0"
+#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)"
+*/
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC32) for environment
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=cpci405dt-0"
+#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)"
+*/
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/processor.h>
-
/* This define must be before the core.h include */
#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_CPU86 1 /* ...on a CPU86 board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/*
* select serial console configuration
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_CPU87 1 /* ...on a CPU87 board */
#define CONFIG_PCI
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/*
* select serial console configuration
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/processor.h>
-
/* This define must be before the core.h include */
#define CONFIG_DB64360 1 /* this is an DB64360 board */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor1"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
-/* Flash banks JFFS2 should use */
-#define CFG_JFFS2_FIRST_BANK 1
-#define CFG_JFFS2_NUM_BANKS 1
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor1=db64360-1"
+#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)"
+*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/processor.h>
-
/* This define must be before the core.h include */
#define CONFIG_DB64460 1 /* this is an DB64460 board */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor1"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
-/* Flash banks JFFS2 should use */
-#define CFG_JFFS2_FIRST_BANK 1
-#define CFG_JFFS2_NUM_BANKS 1
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor1=db64460-1"
+#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)"
+*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
* Scott McNutt <smcnutt@psyent.com>
* Stephan Linz <linz@li-pro.net>
*
+ * CompactFlash/IDE:
+ * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
- CFG_CMD_FAT | \
CFG_CMD_FDC | \
CFG_CMD_FDOS | \
CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
CFG_CMD_KGDB | \
#include <cmd_confdefs.h>
/*------------------------------------------------------------------------
+ * COMPACT FLASH
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CONFIG_IDE_PREINIT /* Implement id_preinit */
+#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0x00920a00 /* IDE/ATA base addr */
+#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
+#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
+#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */
+#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
+#define CFG_ATA_STRIDE 4 /* Width betwix addrs */
+#define CONFIG_DOS_PARTITION
+
+/* Board-specific cf regs */
+#define CFG_CF_PRESENT 0x009209b0 /* CF Present PIO base */
+#define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/
+#define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+
+/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef CFG_MEMTEST_END
#endif
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
#endif /* __CONFIG_H */
#undef CFG_MEMTEST_END
#endif
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
#endif /* __CONFIG_H */
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_IDENT_STRING " $Name: $"
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_DU405 1 /* ...on a DU405 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/processor.h>
-
#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 2 /* ! second bank contains U-Boot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
+#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
+*/
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/processor.h>
-
#ifndef __ASSEMBLY__
#include <galileo/core.h>
#endif
#define CONFIG_MPC8272_FAMILY 1
#define CONFIG_IDS8247 1
#define CPU_ID_STR "MPC8247"
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
/*-----------------------------------------------------------------------
* select serial console configuration
*
#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/*-----------------------------------------------------------------------
* Select serial console configuration
--- /dev/null
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
+ * design.
+ ***********************************************************************/
+
+/*
+ * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
+#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
+#undef CFG_DRAM_TEST /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
+#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000)
+#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
+#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
+
+/* Here for completeness */
+#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_BAUDRATE 9600
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C hardware support */
+#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
+
+#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
+#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
+#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
+#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
+#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
+#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
+#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
+#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
+#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
+
+
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DATE | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_PING | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_ELF | \
+ CFG_CMD_IDE | \
+ CFG_CMD_FAT)
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CFG_AUTO_COMPLETE 1
+#define CFG_ALT_MEMTEST 1 /* use real memory test */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+ /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of cmd args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0xF0000000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
+#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
+ to get to the correct offset */
+#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
+#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
+#define CFG_PCI_TARGET_INIT /* let board init pci target*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
+#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CFG_LOAD_ADDR 0x8000000 /* default load address */
+#define CFG_EXTBDINFO 1 /* use extended board_info */
+
+#define CFG_HZ 100 /* decr freq: 1 ms ticks */
+
+
+#endif /* __CONFIG_H */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * METROBOX.h - configuration Sandburst MetroBox
+ ***********************************************************************/
+
+/*
+ * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ *
+ * $Log: METROBOX.h,v $
+ * Revision 1.21 2005/06/03 15:05:25 tsawyer
+ * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
+ *
+ * Revision 1.20 2005/04/11 20:51:11 tsawyer
+ * fix ethernet
+ *
+ * Revision 1.19 2005/04/06 15:13:36 tsawyer
+ * Update appropriate files to coincide with u-boot 1.1.3
+ *
+ * Revision 1.18 2005/03/10 14:16:02 tsawyer
+ * add def'n for cis8201 short etch option.
+ *
+ * Revision 1.17 2005/03/09 19:49:51 tsawyer
+ * Remove KGDB to allow use of 2nd serial port
+ *
+ * Revision 1.16 2004/12/02 19:00:23 tsawyer
+ * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
+ *
+ * Revision 1.15 2004/09/15 18:04:12 tsawyer
+ * add multiple serial port support
+ *
+ * Revision 1.14 2004/09/03 15:27:51 tsawyer
+ * All metrobox boards are at 66.66 sys clock
+ *
+ * Revision 1.13 2004/08/05 20:27:46 tsawyer
+ * Remove system ace definitions, add net console support
+ *
+ * Revision 1.12 2004/07/29 20:00:13 tsawyer
+ * Add i2c bus 1
+ *
+ * Revision 1.11 2004/07/21 13:44:18 tsawyer
+ * SystemACE is out, CF direct to local bus is in
+ *
+ * Revision 1.10 2004/06/29 19:08:55 tsawyer
+ * Add CONFIG_MISC_INIT_R
+ *
+ * Revision 1.9 2004/06/28 21:30:53 tsawyer
+ * Fix default BOOTARGS
+ *
+ * Revision 1.8 2004/06/17 15:51:08 tsawyer
+ * auto complete
+ *
+ * Revision 1.7 2004/06/17 15:08:49 tsawyer
+ * Add autocomplete
+ *
+ * Revision 1.6 2004/06/15 12:33:57 tsawyer
+ * debugging checkpoint
+ *
+ * Revision 1.5 2004/06/12 19:48:28 tsawyer
+ * Debugging checkpoint
+ *
+ * Revision 1.4 2004/06/02 13:03:06 tsawyer
+ * Fix eth addrs
+ *
+ * Revision 1.3 2004/05/18 19:56:10 tsawyer
+ * Change default bootcommand to pImage.metrobox
+ *
+ * Revision 1.2 2004/05/18 14:13:44 tsawyer
+ * Add bringup values for bootargs and bootcommand.
+ * Remove definition of ipaddress and serverip addresses.
+ *
+ * Revision 1.1 2004/04/16 15:08:54 tsawyer
+ * Initial Revision
+ *
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_METROBOX 1 /* Board is Metrobox */
+#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
+#undef CFG_DRAM_TEST /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Metrobox"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
+#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
+#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_BAUDRATE 9600
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C hardware support */
+#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
+
+#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
+#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
+#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
+#define CONFIG_BOOTDELAY 5 /* disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
+#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
+#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
+#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
+#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
+#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
+#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
+#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
+
+
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DATE | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_PING | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_ELF | \
+ CFG_CMD_IDE | \
+ CFG_CMD_FAT)
+
+/* tbs 09-March-2005 Removed to be able to use 2nd serial */
+/* CFG_CMD_KGDB | \ */
+
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CFG_AUTO_COMPLETE 1
+#define CFG_ALT_MEMTEST 1 /* use real memory test */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+ /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of cmd args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0xF0000000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
+#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
+ to get to the correct offset */
+#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
+#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
+#define CFG_PCI_TARGET_INIT /* let board init pci target*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
+#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CFG_LOAD_ADDR 0x8000000 /* default load address */
+#define CFG_EXTBDINFO 1 /* use extended board_info */
+
+#define CFG_HZ 100 /* decr freq: 1 ms ticks */
+
+
+#endif /* __CONFIG_H */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* one flash only */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=mhpc-0"
+#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
+*/
/*
* For booting Linux, the board info and command line data
#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=mip405-0"
+#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
+*/
/*-----------------------------------------------------------------------
* Cache Configuration
#define CONFIG_ATAPI /* enable ATAPI Support */
/************************************************************
- * SCSI support (experimental) only SYM53C8xx supported
- ************************************************************/
-#undef CONFIG_SCSI_SYM53C8XX
-
-#ifdef CONFIG_SCSI_SYM53C8XX
-#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
-#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
-#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
-#define CFG_SCSI_SPIN_UP_TIME 2
-#endif /* CONFIG_SCSI_SYM53C8XX */
-/************************************************************
* DISK Partition support
************************************************************/
#define CONFIG_DOS_PARTITION
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-/* JFFS2 stuff */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00080000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=ml2-0"
+#define MTDPARTS_DEFAULT "mtdparts=ml2-0:-@512k(jffs2)"
+*/
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS 1
-#define CFG_JFFS2_FIRST_SECTOR 1
#endif /* __CONFIG_H */
#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
/*
* Figure out if we are booting low via flash HRCW or high via the BCSR.
*/
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-#define CFG_JFFS2_FIRST_SECTOR 1
-#define CFG_JFFS2_LAST_SECTOR 27
+/*
+ * JFFS2 partitions
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
+#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
#define CFG_JFFS2_SORT_FRAGMENTS
-#define CFG_JFFS_CUSTOM_PART
/* this is stuff came out of the Motorola docs */
#ifndef CFG_LOWBOOT
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8349ads board configuration file
+ *
+ * Please refer to doc/README.mpc83xxads for more info.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_MII
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83XX 1 /* MPC83XX family */
+#define CONFIG_MPC8349 1 /* MPC8349 specific */
+#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */
+
+/* FIXME: Real PCI support will come in a follow-up update. */
+#undef CONFIG_PCI
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#else
+#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ 66000000
+#else
+#define CONFIG_SYS_CLK_FREQ 33000000
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+#define CFG_IMMRBAR 0xE0000000
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000 /* memtest region */
+#define CFG_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#undef CONFIG_DDR_2T_TIMING
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+#else
+ /*
+ * Manually set up DDR parameters
+ */
+ #define CFG_DDR_SIZE 256 /* Mb */
+ #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+ #define CFG_DDR_TIMING_1 0x37344321
+ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
+ #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+ #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
+ #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CFG_FLASH_SIZE 8 /* FLASH size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP 0x7F000000
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BCSR 0xF8000000
+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
+#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ * LCRR: DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR 0x00000000
+
+#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
+#define CFG_LBLAWBAR2_PRELIM 0xF0000000
+#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM 0xfc006901
+
+#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
+#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
+ | CFG_LBC_LSDMR_BSMA1516 \
+ | CFG_LBC_LSDMR_RFCR8 \
+ | CFG_LBC_LSDMR_PRETOACT6 \
+ | CFG_LBC_LSDMR_ACTTORW3 \
+ | CFG_LBC_LSDMR_BL8 \
+ | CFG_LBC_LSDMR_WRC3 \
+ | CFG_LBC_LSDMR_CL3 \
+ )
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+
+/* IO Configuration */
+#define CFG_IO_CONF (\
+ IO_CONF_UART |\
+ IO_CONF_TSEC1 |\
+ IO_CONF_IRQ0 |\
+ IO_CONF_IRQ1 |\
+ IO_CONF_IRQ2 |\
+ IO_CONF_IRQ3 |\
+ IO_CONF_IRQ4 |\
+ IO_CONF_IRQ5 |\
+ IO_CONF_IRQ6 |\
+ IO_CONF_IRQ7 )
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#define CFG_PCI2_MEM_BASE 0xA0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe3000000
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#if defined(CONFIG_PCI)
+
+#define PCI_ALL_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_GMII 1 /* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1 1
+#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC83XX_TSEC2 1
+#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII \
+ )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_32_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#endif
+
+#define CFG_HID0_INIT 0x000000000
+
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+/* #define CFG_HID0_FINAL (\
+ HID0_ENABLE_INSTRUCTION_CACHE |\
+ HID0_ENABLE_M_BIT |\
+ HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+#define CFG_HID2 0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:04:9f:11:22:33
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01
+#endif
+
+#define CONFIG_IPADDR 192.168.1.253
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE your.uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=400000\0" \
+ "ramdiskfile=ramfs.83xx\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
+#ifndef CONFIG_HAS_FEC
+#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
+#endif
+
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
/*
* sysclk for MPC85xx
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+
+#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#endif
-#define CONFIG_ETHPRIME "MOTO ENET0"
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
--- /dev/null
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Modified by Lunsheng Wang, lunsheng@sohu.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8540eval board configuration file */
+/* please refer to doc/README.mpc85xxads for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
+#define CONFIG_MPC8540 1 /* MPC8540 specific */
+#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
+
+#undef CONFIG_PCI /* pci ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
+ * Not availabe for EVAL board
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+/* sysclk for MPC8540EVAL */
+#if defined(CONFIG_SYSCLK_66M)
+ /*
+ * the oscillator on board is 66Mhz
+ * can also get 66M clock from external PCI
+ */
+ #define CONFIG_SYS_CLK_FREQ 66000000
+#else
+ #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#undef CONFIG_BTB /* toggle branch predition */
+#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+
+#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
+#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
+#else
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#endif
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
+#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
+#else /* Boot from real Flash */
+#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
+#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
+#endif
+
+#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
+#define CFG_FLASH_CFI 1
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+/* Here some DDR setting should be added */
+
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
+#define CFG_OR2_PRELIM 0xfc006901
+#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
+#define CFG_LBC_LBCR 0x00000000
+#define CFG_LBC_LSRT 0x20000000
+#define CFG_LBC_MRTPR 0x20000000
+#define CFG_LBC_LSDMR_1 0x2861b723
+#define CFG_LBC_LSDMR_2 0x0861b723
+#define CFG_LBC_LSDMR_3 0x0861b723
+#define CFG_LBC_LSDMR_4 0x1861b723
+#define CFG_LBC_LSDMR_5 0x4061b723
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
+#else
+#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
+#endif
+#define CFG_OR4_PRELIM 0xffffe1f1
+#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+/* General PCI */
+#define CFG_PCI_MEM_BASE 0x80000000
+#define CFG_PCI_MEM_PHYS 0x80000000
+#define CFG_PCI_MEM_SIZE 0x20000000
+#define CFG_PCI_IO_BASE 0xe2000000
+
+#if defined(CONFIG_PCI)
+#define CONFIG_NET_MULTI
+#undef CONFIG_EEPRO100
+#define CONFIG_TULIP
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#if !defined(CONFIG_PCI_PNP)
+#define PCI_ENET0_IOADDR 0xe0000000
+#define PCI_ENET0_MEMADDR 0xe0000000
+#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
+#endif
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0008
+#elif defined(CONFIG_TSEC_ENET)
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
+#define TSEC1_PHY_ADDR 7
+#define TSEC2_PHY_ADDR 4
+#define FEC_PHY_ADDR 2
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define FEC_PHYIDX 0
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
+#define INTEL_LXT971_PHY 1
+#endif
+
+#undef DEBUG
+
+/* Environment */
+#ifndef CFG_RAMBOOT
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
+#define CFG_ENV_SIZE 0x2000
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#endif
+#define CFG_ENV_SIZE 0x2000
+#else
+/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */
+#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
+#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
+#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
+ | CFG_CMD_PCI | CFG_CMD_I2C ) & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
+ | CFG_CMD_I2C ) & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
+ | CFG_CMD_PING | CFG_CMD_I2C )
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*****************************/
+/* Environment Configuration */
+/*****************************/
+/* The mac addresses for all ethernet interface */
+/* NOTE: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE your.uImage
+
+#define CONFIG_SERVERIP 192.168.101.1
+#define CONFIG_IPADDR 192.168.101.11
+#define CONFIG_GATEWAYIP 192.168.101.0
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_HOSTNAME MPC8540EVAL
+
+#endif /* __CONFIG_H */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8541 1 /* MPC8541 specific */
#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
/*
* When initializing flash, if we cannot find the manufacturer ID,
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
/*
- * SDRAM on the Local Bus
+ * Local Bus Definitions
*/
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ * Port Size = 16 bits = BRx[19:20] = 10
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ *
+ * OR0, OR1:
+ * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ * Reserved ORx[17:18] = 11, confusion here?
+ * CSNT = ORx[20] = 1
+ * ACS = half cycle delay = ORx[21:22] = 11
+ * SCY = 6 = ORx[24:27] = 0110
+ * TRLX = use relaxed timing = ORx[29] = 1
+ * EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ */
+
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
-#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
-#define CFG_BR1_PRELIM 0xff001001 /* port size 16bit */
+#define CFG_BR0_PRELIM 0xff801001
+#define CFG_BR1_PRELIM 0xff001001
-#define CFG_OR0_PRELIM 0xff806e61 /* 8MB Flash */
-#define CFG_OR1_PRELIM 0xff806e61 /* 8MB Flash */
+#define CFG_OR0_PRELIM 0xff806e65
+#define CFG_OR1_PRELIM 0xff806e65
#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
-#undef CONFIG_CLOCKS_IN_MHZ
/*
- * Local Bus Definitions
+ * SDRAM on the Local Bus
*/
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
-#define CONFIG_ETHPRIME "MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8548cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548 1 /* MPC8548 specific */
+#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
+
+#undef CONFIG_PCI
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ * Port Size = 16 bits = BRx[19:20] = 10
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ *
+ * OR0, OR1:
+ * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ * Reserved ORx[17:18] = 11, confusion here?
+ * CSNT = ORx[20] = 1
+ * ACS = half cycle delay = ORx[21:22] = 11
+ * SCY = 6 = ORx[24:27] = 0110
+ * TRLX = use relaxed timing = ORx[29] = 1
+ * EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ */
+
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM 0xff801001
+#define CFG_BR1_PRELIM 0xff001001
+
+#define CFG_OR0_PRELIM 0xff806e65
+#define CFG_OR1_PRELIM 0xff806e65
+
+#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM 0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM 0xfc006901
+
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
+#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ * or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
+ | CFG_LBC_LSDMR_PRETOACT7 \
+ | CFG_LBC_LSDMR_ACTTORW7 \
+ | CFG_LBC_LSDMR_BL8 \
+ | CFG_LBC_LSDMR_WRC4 \
+ | CFG_LBC_LSDMR_CL3 \
+ | CFG_LBC_LSDMR_RFEN \
+ )
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ * port-size = 8-bits = BR[19:20] = 01
+ * no parity checking = BR[21:22] = 00
+ * GPMC for MSEL = BR[24:26] = 000
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
+ * disable buffer ctrl OR[19] = 0
+ * CSNT OR[20] = 1
+ * ACS OR[21:22] = 11
+ * XACS OR[23] = 1
+ * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
+ * SETA OR[28] = 0
+ * TRLX OR[29] = 1
+ * EHTR OR[30] = 1
+ * EAD extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CFG_BR3_PRELIM 0xf8000801
+#define CFG_OR3_PRELIM 0xfff00ff7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 2
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0xe3000000
+#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
+#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
+#define CONFIG_MPC85XX_TSEC3 1
+#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
+#define CONFIG_MPC85XX_TSEC4 1
+#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC3_PHY_ADDR 2
+#define TSEC4_PHY_ADDR 3
+#define FEC_PHY_ADDR 3
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define FEC_PHYIDX 0
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME "eTSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR 192.168.1.253
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE your.uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS1\0" \
+ "ramdiskaddr=400000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8555 1 /* MPC8555 specific */
#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
/*
* When initializing flash, if we cannot find the manufacturer ID,
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
/*
- * SDRAM on the Local Bus
+ * Local Bus Definitions
*/
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ * Port Size = 16 bits = BRx[19:20] = 10
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ *
+ * OR0, OR1:
+ * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ * Reserved ORx[17:18] = 11, confusion here?
+ * CSNT = ORx[20] = 1
+ * ACS = half cycle delay = ORx[21:22] = 11
+ * SCY = 6 = ORx[24:27] = 0110
+ * TRLX = use relaxed timing = ORx[29] = 1
+ * EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ */
+
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
-#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
-#define CFG_BR1_PRELIM 0xff001001 /* port size 16bit */
+#define CFG_BR0_PRELIM 0xff801001
+#define CFG_BR1_PRELIM 0xff001001
-#define CFG_OR0_PRELIM 0xff806e61 /* 8MB Flash */
-#define CFG_OR1_PRELIM 0xff806e61 /* 8MB Flash */
+#define CFG_OR0_PRELIM 0xff806e65
+#define CFG_OR1_PRELIM 0xff806e65
#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
-#undef CONFIG_CLOCKS_IN_MHZ
/*
- * Local Bus Definitions
+ * SDRAM on the Local Bus
*/
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
-#define CONFIG_ETHPRIME "MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
#define CONFIG_PCI
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
/*
* sysclk for MPC85xx
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define CONFIG_ETHPRIME "MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 4*1024*1024 /* size of jffs2 partition */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_SIZE 0x00400000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
+
+#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
+ "2560k(cramfs1),2560k(cramfs2)," \
+ "256k(u-boot),256k(env);" \
+ "nc650-nand:4m(nand1),28m(nand2)"
+*/
+
#endif /* __CONFIG_H */
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF (2 * 1024 * 1024) /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE (1*1024*1024) /* size of jffs2 partition */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_SIZE 0x00100000
+#define CONFIG_JFFS2_PART_OFFSET 0x00200000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nand0=netta-nand"
+#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)"
+*/
+
/*****************************************************************************/
#define CFG_DIRECT_FLASH_TFTP
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $"
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_PM826 1 /* ...on a PM8260 module */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_PM828 1 /* ...on a PM828 module */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
+
/*
* sysclk for MPC85xx
/*
* Determine DDR configuration from I2C interface.
*/
- #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
#else
/*
#undef CFG_RAMBOOT
#endif
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
/*
* Local Bus Definitions
*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 3
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_MPC85XX_FEC 1
-#define FEC_PHY_ADDR 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
+#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
-#define CONFIG_ETHPRIME "MOTO ENET0"
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_ETH2ADDR 00:40:42:01:00:02
#endif
-#define CONFIG_IPADDR 192.168.0.103
-#define CONFIG_HOSTNAME PM854
-#define CONFIG_ROOTPATH /opt/eldk30/ppc_82xx
-#define CONFIG_BOOTFILE uImage
+#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
+#define CONFIG_BOOTFILE pm854/uImage
-#define CONFIG_SERVERIP 192.168.0.54
+#define CONFIG_HOSTNAME pm854
+#define CONFIG_IPADDR 192.168.0.103
+#define CONFIG_SERVERIP 192.168.0.64
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_NETMASK 255.255.255.0
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=400000\0" \
- "ramdiskfile=uRamdisk\0"
+ "ramdiskfile=pm854/uRamdisk\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MicroSys PM856 board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
+#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_PM856 1 /* PM856 board specific */
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
+
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ * 33000000
+ * 66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz. In any event, this value
+ * must match the settings of some switches. Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 66000000
+#endif
+
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR parameters
+ */
+ #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
+ #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
+ #define CFG_DDR_CS0_CONFIG 0x80000102
+ #define CFG_DDR_TIMING_1 0x47444321
+ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
+ #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
+ #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
+ #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
+#endif
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
+
+#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
+#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
+
+#define CFG_OR0_PRELIM 0xfe006f67 /* 32MB Flash */
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
+
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else */
+#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x58
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR 0x51
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#undef CONFIG_MPC85XX_FEC
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+#endif /* CONFIG_TSEC_ENET */
+
+#define CONFIG_ETHPRIME "TSEC0"
+
+#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
+
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers
+ * - Full duplex
+ */
+#define CONFIG_ETHER_ON_FCC3
+#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE 0
+#define CFG_FCC_PSMR (FCC_PSMR_FDE)
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+ #else
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+ #endif
+#else
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_EEPROM \
+ | CFG_CMD_DATE \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C)
+ #else
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_EEPROM \
+ | CFG_CMD_DATE \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C)
+ #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x1000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_LOOPW
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR 00:40:42:01:00:00
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:40:42:01:00:01
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:40:42:01:00:02
+#endif
+
+
+#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
+#define CONFIG_BOOTFILE pm856/uImage
+
+#define CONFIG_HOSTNAME pm856
+#define CONFIG_IPADDR 192.168.0.103
+#define CONFIG_SERVERIP 192.168.0.64
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 9600
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=400000\0" \
+ "ramdiskfile=pm856/uRamdisk\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
+/*
+ * JFFS2 partitions - second bank contains u-boot
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=pmc405-0"
+#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)"
+*/
/*-----------------------------------------------------------------------
* Environment Variable setup
* CONFIG_PPCHAMELEON_CLK_33
*/
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_33
+#define CONFIG_PPCHAMELEON_CLK_25
#endif
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */
+#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
+#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
#else
#define CONFIG_PHY_ADDR 2 /* PHY address */
#endif
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
+
+/* Reserve 256 kB for Monitor */
#define CFG_FLASH_BASE 0xFFFC0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_LEN (256 * 1024)
+
+/* Reserve 320 kB for Monitor */
+/*
+#define CFG_FLASH_BASE 0xFFFB0000
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (320 * 1024)
+*/
+
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
/*
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
#endif /* CONFIG_NO_SERIAL_EEPROM */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 4*1024*1024 /* size of jffs2 partition */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_SIZE 0x00400000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
+*/
+
+/* 256 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+ "1792k(user),256k(u-boot);" \
+ "ppchameleonevb-nand:-(nand)"
+*/
+
+/* 320 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+ "1728k(user),320k(u-boot);" \
+ "ppchameleonevb-nand:-(nand)"
+*/
+
#endif /* __CONFIG_H */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* JFFS2 stuff */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS 1
-#define CFG_JFFS2_FIRST_SECTOR 24
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition
+ * use all the space starting at offset 3MB*/
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00300000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=r360-0"
+#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)"
+*/
/*
* Low Level Configuration Settings
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
+
#endif /* __CONFIG_H */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CPU_ID_STR "MPC8250"
#endif /* CONFIG_MPC8248 */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
#undef DEBUG
#define CFG_DIRECT_FLASH_TFTP
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
-#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
-#define CFG_JFFS2_FIRST_SECTOR 16
#define CFG_JFFS2_SORT_FRAGMENTS
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00100000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=rattler-0"
+#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
+*/
#endif /* CFG_CMD_JFFS2 */
#define CFG_MONITOR_BASE TEXT_BASE
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-#define CONFIG_MPC8560 1 /* MPC8560 (CPU) specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
- #define CONFIG_NET_MULTI 1
- #define CONFIG_PHY_BCM5421S /* GigaBit Ether PHY */
- #define CONFIG_MII 1 /* MII PHY management */
- #define CONFIG_PHY_ADDR 25 /* PHY address */
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MPC85xx_TSEC1
+# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
+# define CONFIG_MII 1 /* MII PHY management */
+# define TSEC1_PHY_ADDR 25
+# define TSEC1_PHYIDX 0
+/* Options are: TSEC0 */
+# define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-#define CONFIG_MPC8560 1 /* MPC8560 (CPU) specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
- #define CONFIG_NET_MULTI 1
- #define CONFIG_PHY_BCM5421S /* GigaBit Ether PHY */
- #define CONFIG_MII 1 /* MII PHY management */
- #define CONFIG_PHY_ADDR 25 /* PHY address */
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1 /* MII PHY management */
+# define CONFIG_MPC85xx_TSEC1
+# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
+# define TSEC1_PHY_ADDR 25
+# define TSEC1_PHYIDX 0
+/* Options are: TSEC0 */
+# define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
#define CONFIG_SCM 1 /* ...on a System Controller Module */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#if (CONFIG_TQM8260 <= 100)
# error "TQM8260 module revison not supported"
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CFG_JFFS_CUSTOM_PART
#define CFG_JFFS2_SORT_FRAGMENTS
-/* JFFS2 location when using NOR flash */
-#define CFG_JFFS2_BASE (CFG_FLASH_BASE + 0x80000)
-#define CFG_JFFS2_SIZE (0x780000)
-/* JFFS2 location (in RAM) when using NAND flash */
-#define CFG_JFFS2_RAMBASE 0x400000
-#define CFG_JFFS2_RAMSIZE 0x200000 /* NAND boot partition is 2MiB */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0x00780000
+#define CONFIG_JFFS2_PART_OFFSET 0x00080000
+*/
+
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_SIZE 0x00200000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand"
+#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
+*/
/* NAND flash support */
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
#endif
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 2
#define FEC_PHYIDX 0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
-#define CONFIG_ETHPRIME "ENET1"
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME "TSEC1"
#endif /* CONFIG_TSEC_ENET */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC2_PHY_ADDR 1
#define TSEC2_PHYIDX 0
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-#define CONFIG_ETHPRIME "ENET1"
+#define CONFIG_ETHPRIME "TSEC1"
/*
* Environment
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_NETMASK 255.255.255.0
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_IDENT_STRING " $Name: $"
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
-#define CONFIG_440_GX 1 /* 440 GX */
+#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8220 1
+#define CONFIG_YUKON8220 1 /* ... on Yukon board */
+
+/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
+ determine the CPU speed. */
+#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
+#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+
+/* Define this for PSC console
+#define CONFIG_PSC_CONSOLE 1
+*/
+
+#define CONFIG_EXTUART_CONSOLE 1
+
+#ifdef CONFIG_EXTUART_CONSOLE
+# define CONFIG_CONS_INDEX 1
+# define CFG_NS16550_SERIAL
+# define CFG_NS16550
+# define CFG_NS16550_REG_SIZE 1
+# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
+# define CFG_NS16550_CLK 18432000
+#endif
+
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
+
+#define CONFIG_NET_MULTI
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTARGS "root=/dev/ram rw"
+#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
+#define CONFIG_IPADDR 192.162.1.2
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_SERVERIP 192.162.1.1
+#define CONFIG_GATEWAYIP 192.162.1.1
+#define CONFIG_HOSTNAME yukon
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1
+#define CFG_I2C_MODULE 1
+
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+/*
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0
+#define CFG_ENV_SIZE 256
+*/
+
+/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+ else undefined it will boot from Intel Strata flash */
+#define CFG_AMD_BOOT 1
+
+/*
+ * Flexbus Chipselect configuration
+ */
+#if defined (CFG_AMD_BOOT)
+#define CFG_CS0_BASE 0xfff0
+#define CFG_CS0_MASK 0x00080000 /* 512 KB */
+#define CFG_CS0_CTRL 0x003f0d40
+
+#define CFG_CS1_BASE 0xfe00
+#define CFG_CS1_MASK 0x01000000 /* 16 MB */
+#define CFG_CS1_CTRL 0x003f1540
+#else
+#define CFG_CS0_BASE 0xff00
+#define CFG_CS0_MASK 0x01000000 /* 16 MB */
+#define CFG_CS0_CTRL 0x003f1540
+
+#define CFG_CS1_BASE 0xfe08
+#define CFG_CS1_MASK 0x00080000 /* 512 KB */
+#define CFG_CS1_CTRL 0x003f0d40
+#endif
+
+#define CFG_CS2_BASE 0xf100
+#define CFG_CS2_MASK 0x00040000
+#define CFG_CS2_CTRL 0x003f1140
+
+#define CFG_CS3_BASE 0xf200
+#define CFG_CS3_MASK 0x00040000
+#define CFG_CS3_CTRL 0x003f1100
+
+
+#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
+#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
+
+#if defined (CFG_AMD_BOOT)
+#define CFG_AMD_BASE CFG_FLASH0_BASE
+#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
+#define CFG_FLASH_BASE CFG_AMD_BASE
+#else
+#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
+#define CFG_AMD_BASE CFG_FLASH1_BASE
+#define CFG_FLASH_BASE CFG_INTEL_BASE
+#endif
+
+#define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
+#define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
+
+
+#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+
+#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
+#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
+
+#define CFG_FLASH_CHECKSUM
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#if defined (CFG_AMD_BOOT)
+#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
+#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
+#else
+#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
+#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
+#endif
+
+#define CONFIG_ENV_OVERWRITE 1
+
+#if defined CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK 0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS 1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
+#define CFG_SRAM_SIZE 0x8000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* SDRAM configuration */
+#define CFG_SDRAM_TOTAL_BANKS 2
+#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
+#define CFG_SDRAM_SPD_SIZE 0x40
+#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
+
+/* SDRAM drive strength register */
+#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
+ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+ (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
+ (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
+ (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC8220_FEC 1
+#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR 0x18
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+
+#endif /* __CONFIG_H */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
#define CPU_ID_STR "MPC8265"
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#undef DEBUG
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/processor.h>
-
#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
#define CONFIG_ETHER_PORT_MII /* use two MII ports */
#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */
CFG_CMD_MII | \
CFG_CMD_DATE)
-/* Flash banks JFFS2 should use */
-#define CFG_JFFS2_FIRST_BANK 1
-#define CFG_JFFS2_NUM_BANKS 2
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
+#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+*/
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
--- /dev/null
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
+#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
+#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
+#define CONFIG_AEVFIFO 1
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#ifdef CONFIG_AEVFIFO
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+/* #define CONFIG_PCI_SCAN_SHOW 1 */
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_EEPRO100 1
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CONFIG_NS8382X 1
+#endif /* CONFIG_AEVFIFO */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ ADD_BMP_CMD | \
+ CFG_CMD_PCI | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PING | \
+ CFG_CMD_POST_DIAG | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_TIMESTAMP /* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000) /* Boot low */
+# define CFG_LOWBOOT 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath) " \
+ "console=ttyS0,$(baudrate)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootfile=/tftpboot/tqm5200/uImage\0" \
+ "load=tftp 200000 $(u-boot)\0" \
+ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
+ "update=protect off FC000000 FC05FFFF;" \
+ "erase FC000000 FC05FFFF;" \
+ "cp.b 200000 FC000000 $(filesize);" \
+ "protect on FC000000 FC05FFFF\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
+#else
+#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else /* CFG_LOWBOOT */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
+#endif /* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
+ (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ * Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ * Use for REV200 STK52XX boards. Do not use with REV100 modules
+ * (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ * 000 -> All PSC2 pins are GIOPs
+ * 001 -> CAN1/2 on PSC2 pins
+ * Use for REV100 STK52xx boards
+ * use PSC6:
+ * on STK52xx:
+ * use as UART. Pins PSC6_0 to PSC6_3 are used.
+ * Bits 9:11 (mask: 0x00700000):
+ * 101 -> PSC6 : Extended POST test is not available
+ * on MINI-FAP and TQM5200_IB:
+ * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ * 000 -> PSC6 could not be used as UART, CODEC or IrDA
+ * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ * tests.
+ */
+#define CFG_GPS_PORT_CONFIG 0x81500014
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_CS_AUTOCONF
+#define CONFIG_LAST_STAGE_INIT
+#endif
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CFG_CS2_START 0xE5000000
+#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
+#define CFG_CS2_CFG 0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE 0xE0000000
+#define CFG_CS1_START (SM501_FB_BASE)
+#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
+#define CFG_CS1_CFG 0x8F48FF70
+#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+#endif /* __CONFIG_H */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ATC 1 /* ...on a ATC board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/*
* select serial console configuration
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * bamboo.h - configuration for BAMBOO board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
+#define CONFIG_440EP 1 /* Specific PPC440EP support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+
+/*
+ * Please note that, if NAND support is enabled, the 2nd ethernet port
+ * can't be used because of pin multiplexing. So, if you want to use the
+ * 2nd ethernet port you have to "undef" the following define.
+ */
+#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
+#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
+#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE 0x50000000
+#define CFG_NVRAM_BASE_ADDR 0x80000000
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_NAND_ADDR 0x90000000
+#define CFG_NAND2_ADDR 0x94000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
+#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
+ * The DS1558 code assumes this condition
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH related
+ *----------------------------------------------------------------------*/
+#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
+#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
+#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
+#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
+#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
+#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
+#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
+#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
+#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
+#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
+#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
+#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
+#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
+#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
+#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
+#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
+#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
+#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
+#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
+
+/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
+#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
+#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
+#define NAND0_CMD_READ2 0x50
+#define NAND0_CMD_READ_ID 0x90
+#define NAND0_CMD_READ_STATUS 0x70
+#define NAND0_CMD_RESET 0xFF
+#define NAND0_CMD_PAGE_PROG 0x80
+#define NAND0_CMD_PAGE_PROG_TRUE 0x10
+#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
+#define NAND0_CMD_BLOCK_ERASE 0x60
+#define NAND0_CMD_BLOCK_ERASE_END 0xD0
+
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
+#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
+#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
+#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
+
+/* not needed with 440EP NAND controller */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------------- */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x50,0x51} /* SPD i2c spd addresses */
+#define CFG_SDRAM_ONBOARD_SIZE (64 << 20) /* Bamboo has onboard and DIMM-slots!*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=bamboo\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/bamboo/uImage\0" \
+ "kernel_addr=fff00000\0" \
+ "ramdisk_addr=fff10000\0" \
+ "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
+ "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
+ "cp.b 100000 fff80000 80000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+
+#ifndef CONFIG_BAMBOO_NAND
+#define CONFIG_NET_MULTI 1 /* required for netconsole */
+#define CONFIG_PHY1_ADDR 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#endif /* CONFIG_BAMBOO_NAND */
+
+#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef CONFIG_BAMBOO_NAND
+#define _CFG_CMD_NAND CFG_CMD_NAND
+#else
+#define _CFG_CMD_NAND 0
+#endif /* CONFIG_BAMBOO_NAND */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_USB | \
+ _CFG_CMD_NAND | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI 1 /* support kdi files */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
/*
- * (C) Copyright 2000, 2001
+ * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#ifndef __CONFIG_H
#define __CONFIG_H
-/* Debug options */
-/*#define __DEBUG_START_FROM_SRAM__ */
-/*#define DEBUG 1*/
-
-
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_BUBINGA405EP 1 /* ...on a BUBINGA405EP board */
+#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/
/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM
/*
#endif
/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-
-/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
-#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#else
-#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
#if 1
-#define CONFIG_BOOTCOMMAND "" /* autoboot command */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#if 0
-#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
-#else
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#endif
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=bubinga\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/bubinga/uImage\0" \
+ "kernel_addr=fff80000\0" \
+ "ramdisk_addr=fff90000\0" \
+ "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run net_nfs"
#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
- "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
-#define CONFIG_BOOTARGS "root=/dev/hda1 " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
-
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
+#define CONFIG_BAUDRATE 115200
+
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
-/*
-#ifndef __DEBUG_START_FROM_SRAM__
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF )
-#endif
-*/
-
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
CFG_CMD_CACHE | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
- 0 )
+ CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#endif
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
* External peripheral base address
*-----------------------------------------------------------------------
*/
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
#define CFG_IR_REG_BASE_ADDR 0xF0200000
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CFG_SRAM_BASE 0xFFF80000
-#define CFG_FLASH_BASE 0xFFF00000
-#define CFG_MONITOR_BASE CFG_SRAM_BASE
-#else
#define CFG_SRAM_BASE 0xFFF00000
#define CFG_FLASH_BASE 0xFFF80000
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#endif
-
-
-/*#define CFG_MONITOR_LEN (200 * 1024) /XXX* Reserve 200 kB for Monitor */
-#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 200 kB for Monitor */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
/*
* For booting Linux, the board info and command line data
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-/* BEG ENVIRONNEMENT FLASH */
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
/*-----------------------------------------------------------------------
* NVRAM organization
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
-
/*
* Internal Definitions
*
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CFG_FLASH_RANGE_SIZE 0x01000000
#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=debris-0"
+#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
+*/
#define CFG_ENV_IS_IN_NVRAM 1
#define CONFIG_ENV_OVERWRITE 1
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#endif
+
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
+#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 9600
+#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_NVRAM */
+
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
-#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=ebony\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/ebony/uImage\0" \
+ "kernel_addr=ff800000\0" \
+ "ramdisk_addr=ff810000\0" \
+ "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
-#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
-#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-
-#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-
-#define CONFIG_BOOTARGS "root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#define CONFIG_BOOTDELAY -1 /* disable autoboot */
-#define CONFIG_BAUDRATE 9600
+#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
-
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
+ CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
/*-----------------------------------------------------------------------
* PCI stuff
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/*
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
-/* Flash banks JFFS2 should use */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_FIRST_SECTOR 2
-#define CFG_JFFS2_NUM_BANKS 1
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=ep7312-0"
+#define MTDPARTS_DEFAULT "mtdparts=ep7312-0:-(jffs2)"
+*/
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Embedded Planet EP8248 boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8248
+#define CPU_ID_STR "MPC8248"
+
+#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
+
+#undef DEBUG
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define CONFIG_CONS_ON_SMC /* Console is on SMC */
+#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
+#undef CONFIG_CONS_NONE /* It's not on external UART */
+#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
+
+#define CFG_BCSR 0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
+#undef CONFIG_ETHER_NONE /* No external Ethernet */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
+
+#if (CONFIG_ETHER_INDEX == 1)
+
+/* - Rx clock is CLK10
+ * - Tx clock is CLK11
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
+#define CFG_CPMFCR_RAMTYPE 0
+#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/* - Rx clock is CLK13
+ * - Tx clock is CLK14
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE 0
+#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT 0 /* Not used - implemented in BCSR */
+#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04)
+#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1)
+
+#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
+ else *(vu_char *)(CFG_BCSR + 8) &= 0xFE
+
+#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
+ else *(vu_char *)(CFG_BCSR + 8) &= 0xFD
+
+#define MIIDELAY udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN 66000000 /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_DHCP \
+ | CFG_CMD_ECHO \
+ | CFG_CMD_I2C \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_MII \
+ | CFG_CMD_PING \
+ )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
+#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE 0xFF800000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+
+#define CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR 0
+#define CFG_JFFS2_LAST_SECTOR 62
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C 1 /* To enable I2C support */
+#define CFG_I2C_SPEED 100000 /* I2C speed */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+#endif /* CFG_CMD_I2C */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
+
+#define CFG_ENV_IS_IN_FLASH
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+#define CFG_DEFAULT_IMMR 0x00010000
+
+#define CFG_IMMR 0xF0000000
+
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CFG_HID2 0
+
+#define CFG_SIUMCR 0x01240200
+#define CFG_SYPCR 0xFFFF0683
+#define CFG_BCR 0x00000000
+#define CFG_SCCR SCCR_DFBRG01
+
+#define CFG_RMR RMR_CSRE
+#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR 0
+
+#define CFG_MPTPR 0x1300
+#define CFG_PSDMR 0x82672522
+#define CFG_PSRT 0x4B
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841)
+#define CFG_SDRAM_OR 0xFF0030C0
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
+#define CFG_OR0_PRELIM 0xFF8008C2
+#define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801)
+#define CFG_OR2_PRELIM 0xFFF00864
+
+#define CFG_RESET_ADDRESS 0xC0000000
+
+#endif /* __CONFIG_H */
#define CFG_EP8260_H2 1
/* #undef CFG_EP8260_H2 */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
+
#endif /* __CONFIG_H */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_GW8260 1 /* on an GW8260 Board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
CFG_CMD_SNTP)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x58
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR 0x51
+
+/*
* Flash configuration
*/
#define CFG_FLASH_BASE 0xFF800000
#endif
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
#define CFG_GPS_PORT_CONFIG 0x01051004
/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
-
-/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
+
+#define CONFIG_IDE_PREINIT 1
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
+#define CONFIG_ATAPI 1
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
#endif /* __CONFIG_H */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_HYMOD 1 /* ...on a Hymod board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
+
#endif /* __CONFIG_H */
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-/* Flash banks JFFS2 should use */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_FIRST_SECTOR 8
-#define CFG_JFFS2_NUM_BANKS 2
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00020000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=impA7 NOR Flash Bank #0,nor1=impA7 NOR Flash Bank #1"
+#define MTDPARTS_DEFAULT "mtdparts=impA7 NOR Flash Bank #0:-(FileSystem1);impA7 NOR Flash Bank #1:-(FileSystem2)"
+*/
#endif /* __CONFIG_H */
#define CONFIG_NET_MULTI
#define CONFIG_INCA_IP_SWITCH_AMDIX
-#define CFG_JFFS2_FIRST_BANK 1
-#define CFG_JFFS2_NUM_BANKS 1
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, use all space on the device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor1"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0"
+#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \
+ "64k(env)," \
+ "768k(linux)," \
+ "1m@3m(rootfs)," \
+ "768k(linux2)," \
+ "3m@5m(rootfs2)"
+*/
/*-----------------------------------------------------------------------
* Cache Configuration
#define CFG_FLASH_BASE PHYS_FLASH_1
-
/*
- * JFFS2 Partitions
+ * JFFS2 partitions
+ *
*/
-#define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */
-#define CONFIG_MTD_INNOKOM_16MB 1 /* development flash */
-#undef CONFIG_MTD_INNOKOM_64MB /* production flash */
+/* development flash */
+#define CONFIG_MTD_INNOKOM_16MB 1
+#undef CONFIG_MTD_INNOKOM_64MB
+
+/* production flash */
+/*
+#define CONFIG_MTD_INNOKOM_64MB 1
+#undef CONFIG_MTD_INNOKOM_16MB
+*/
+
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=innokom-0"
+*/
+/* development flash */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
+*/
+
+/* production flash */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
+*/
/*
* GPIO settings
#define CONFIG_LCD 1 /* use LCD controller ... */
#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
+#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
+#define CONFIG_LCD_INFO 1 /* ... and some board info */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
#define CONFIG_SERIAL_MULTI 1
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* max size for environment */
-/* Flash banks JFFS2 should use */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_FIRST_SECTOR 8
-#define CFG_JFFS2_NUM_BANKS 2
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00080000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=modnet50-0"
+#define MTDPARTS_DEFAULT "mtdparts=modnet50-0:-@512k(jffs2)"
+*/
#endif /* __CONFIG_H */
#define CONFIG_INITRD_TAG 1 /* send initrd params */
#undef CONFIG_VFD /* do not send framebuffer setup */
-#define CFG_JFFS_CUSTOM_PART
/*
* Malloc pool need to host env + 128 Kb reserve for other allocations.
*/
#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/
#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
-#define MX1FS2_JFFS2_PART0_START 0x10200000
-#define MX1FS2_JFFS2_PART0_SIZE 0x00500000
-#define MX1FS2_JFFS2_PART1_START 0x10700000
-#define MX1FS2_JFFS2_PART1_SIZE 0x00900000
#else
#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
* footprint.
* NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
*/
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_FIRST_SECTOR 5
-#define CFG_JFFS2_NUM_BANKS 1
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+/*
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00050000
+*/
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=mx1fs2-0"
+
+#ifdef BUS32BIT_VERSION
+#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)"
+#endif
/*
* Environment setup. Definitions of monitor location and size with
/*
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_OCOTEA 1 /* Board is ebony */
-#define CONFIG_440_GX 1 /* Specifc GX support */
+#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#endif
+
+
+/*-----------------------------------------------------------------------
* NVRAM/RTC
*
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_NVRAM */
+
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=ocotea\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/ocotea/uImage\0" \
+ "kernel_addr=fff00000\0" \
+ "ramdisk_addr=fff10000\0" \
+ "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
-#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
-#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-#define CONFIG_ENV_OVERWRITE 1
-
-#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-
-#define CONFIG_BOOTARGS "root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#define CONFIG_BOOTDELAY -1 /* disable autoboot */
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_PHY3_ADDR 0x18
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.1.2.3
-#define CONFIG_ETHADDR 00:04:AC:E3:28:8A
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:04:AC:E3:28:8B
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:04:AC:E3:28:8C
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:04:AC:E3:28:8D
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SERVERIP 10.1.2.2
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
+ CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CFG_HZ 100 /* decrementer freq: 1 ms ticks */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
-#define CFG_PCI_TARGET_INIT /* let board init pci target */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CFG_FLASH_ERASE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Write */
-/* Flash banks JFFS2 should use */
-#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE)
#define CFG_JFFS2_MEM_NAND
-#define CFG_JFFS2_FIRST_BANK 1 /* use flash_info[1] */
-#define CFG_JFFS2_NUM_BANKS 1
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor1"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor1=omap2420-1"
+#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
+*/
#endif /* __CONFIG_H */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
#define CONFIG_SACSng 1 /* munged for the SACSng */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
/* XXX flagging this as something I might want to delete */
#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
- #define CONFIG_NET_MULTI 1
- #define CONFIG_PHY_BCM5421S 1 /* GigaBit Ether PHY */
- #define CONFIG_MII 1 /* MII PHY management */
- #define CONFIG_PHY_ADDR 25 /* PHY address */
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1 /* MII PHY management */
+# define CONFIG_MPC85xx_TSEC1
+# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
+# define TSEC1_PHY_ADDR 25
+# define TSEC1_PHYIDX 0
+/* Options are: TSEC0 */
+# define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */
#undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */
#define CONFIG_SPI_X 1
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* */
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=SC520CDP Flash Bank #0"
+#define MTDPARTS_DEFAULT "mtdparts=SC520CDP Flash Bank #0:-(jffs2)"
+*/
/*-----------------------------------------------------------------------
* Device drivers
#endif
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=sc520_spunk-0"
+#define MTDPARTS_DEFAULT "mtdparts=sc520_spunk-0:-(jffs2)"
+*/
/*-----------------------------------------------------------------------
* Device drivers
#define CFG_ATA_REG_OFFSET 0 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#define CFG_FISRT_PCMCIA_BUS 1
+#define CFG_FIRST_PCMCIA_BUS 1
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* reset for ide unsupported... */
--- /dev/null
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
+#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
+#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_STK52XX
+#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
+#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
+#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
+#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
+#define CONFIG_BOARD_EARLY_INIT_R
+#endif /* CONFIG_STK52XX */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#ifdef CONFIG_STK52XX
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+/* #define CONFIG_PCI_SCAN_SHOW 1 */
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_EEPRO100 1
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CONFIG_NS8382X 1
+#endif /* CONFIG_STK52XX */
+
+#ifdef CONFIG_PCI
+#define ADD_PCI_CMD CFG_CMD_PCI
+#else
+#define ADD_PCI_CMD 0
+#endif
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_VIDEO
+#define ADD_BMP_CMD CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD 0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#ifdef CONFIG_STK52XX
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD 0
+#endif
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* IDE */
+#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
+#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
+#else
+#define ADD_IDE_CMD 0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ ADD_BMP_CMD | \
+ ADD_IDE_CMD | \
+ ADD_PCI_CMD | \
+ ADD_USB_CMD | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PING | \
+ CFG_CMD_POST_DIAG | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_TIMESTAMP /* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000) /* Boot low */
+# define CFG_LOWBOOT 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#if defined (CONFIG_TQM5200_AA)
+# define CONFIG_U_BOOT_SUFFIX "-AA\0"
+#elif defined (CONFIG_TQM5200_AB)
+# define CONFIG_U_BOOT_SUFFIX "-AB\0"
+#elif defined (CONFIG_TQM5200_AC)
+# define CONFIG_U_BOOT_SUFFIX "-AC\0"
+#else
+# define CONFIG_U_BOOT_SUFFIX "\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootfile=/tftpboot/tqm5200/uImage\0" \
+ "load=tftp 200000 $(u-boot)\0" \
+ "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
+ "update=protect off FC000000 FC05FFFF;" \
+ "erase FC000000 FC05FFFF;" \
+ "cp.b 200000 FC000000 $(filesize);" \
+ "protect on FC000000 FC05FFFF\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
+#else
+#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * HW-Monitor configuration on Mini-FAP
+ */
+#if defined (CONFIG_MINIFAP)
+#define CFG_I2C_HWMON_ADDR 0x2C
+#endif
+
+/* List of I2C addresses to be verified by POST */
+#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
+#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
+ CFG_I2C_SLAVE }
+#elif defined (CONFIG_TQM5200_AC)
+#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
+#endif
+
+#if defined (CONFIG_MINIFAP)
+#undef I2C_ADDR_LIST
+#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
+ CFG_I2C_HWMON_ADDR, \
+ CFG_I2C_SLAVE }
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else /* CFG_LOWBOOT */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
+#endif /* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
+ (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ * Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ * Use for REV200 STK52XX boards. Do not use with REV100 modules
+ * (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ * 000 -> All PSC2 pins are GIOPs
+ * 001 -> CAN1/2 on PSC2 pins
+ * Use for REV100 STK52xx boards
+ * use PSC6:
+ * on STK52xx:
+ * use as UART. Pins PSC6_0 to PSC6_3 are used.
+ * Bits 9:11 (mask: 0x00700000):
+ * 101 -> PSC6 : Extended POST test is not available
+ * on MINI-FAP and TQM5200_IB:
+ * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ * 000 -> PSC6 could not be used as UART, CODEC or IrDA
+ * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ * tests.
+ */
+#if defined (CONFIG_MINIFAP)
+# define CFG_GPS_PORT_CONFIG 0x91000004
+#elif defined (CONFIG_STK52XX)
+# if defined (CONFIG_STK52XX_REV100)
+# define CFG_GPS_PORT_CONFIG 0x81500014
+# else /* STK52xx REV200 and above */
+# if defined (CONFIG_TQM5200_REV100)
+# error TQM5200 REV100 not supported on STK52XX REV200 or above
+# else/* TQM5200 REV200 and above */
+# define CFG_GPS_PORT_CONFIG 0x91500004
+# endif
+# endif
+#else /* TMQ5200 Inbetriebnahme-Board */
+# define CFG_GPS_PORT_CONFIG 0x81000004
+#endif
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_CS_AUTOCONF
+#define CONFIG_LAST_STAGE_INIT
+#endif
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
+#define CFG_CS2_START 0xE5000000
+#ifdef CONFIG_TQM5200_AB
+#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
+#else /* CONFIG_CS_AUTOCONF */
+#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
+#endif
+#define CFG_CS2_CFG 0x0004D930
+#endif
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
+ defined (CONFIG_CS_AUTOCONF)
+#define SM501_FB_BASE 0xE0000000
+#define CFG_CS1_START (SM501_FB_BASE)
+#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
+#define CFG_CS1_CFG 0x8F48FF70
+#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
+#endif
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
+#endif /* __CONFIG_H */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define CONFIG_ETHPRIME "MOTO ENET0"
+#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ * U-Boot port on STx XTc 8xx board
+ * Mostly copied from Panto's NETTA2 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
+#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
+
+#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
+
+/* Select one of few clock rates defined later in this file.
+*/
+/* #define MPC8XX_HZ 50000000 */
+#define MPC8XX_HZ 66666666
+
+#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootm"
+
+#define CONFIG_AUTOSCRIPT
+#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define FEC_ENET 1 /* eth.c needs it that way... */
+#undef CFG_DISCOVER_PHY
+#define CONFIG_MII 1
+#undef CONFIG_RMII
+
+#define CONFIG_ETHER_ON_FEC1 1
+#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
+#undef CONFIG_FEC1_PHY_NORXERR
+
+#define CONFIG_ETHER_ON_FEC2 1
+#define CONFIG_FEC2_PHY 3
+#undef CONFIG_FEC2_PHY_NORXERR
+
+#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_NAND | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS)
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "xtc> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#if defined(DEBUG)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#endif
+
+/* yes this is weird, I know :) */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000)
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+#define CFG_RESET_ADDRESS 0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE 0x10000
+
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
+#define CFG_ENV_OFFSET 0
+#define CFG_ENV_SIZE 0x4000
+
+#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000)
+#define CFG_ENV_OFFSET_REDUND 0
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 }
+
+#define CFG_FLASH_PROTECTION
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 50000000
+#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+ (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+ PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 66666666
+#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
+ (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+ PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+#else
+#error unsupported freq for XIN (must be 10MHz)
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+
+#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
+
+#define CFG_REMAP_OR_AM 0x80000000
+#define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH)
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock!)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider = 98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_MAMR_PTA 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define NAND_SIZE 0x00010000 /* 64K */
+#define NAND_BASE 0xF1000000
+
+/****************************************************************/
+
+/* NAND */
+#define CFG_NAND_BASE NAND_BASE
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
+
+#define CFG_MAX_NAND_DEVICE 1
+#undef NAND_NO_RB
+
+#define SECTORSIZE 512
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
+#define NAND_DISABLE_CE(nand) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
+ } while(0)
+
+#define NAND_ENABLE_CE(nand) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
+ } while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
+ } while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
+ } while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
+ } while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
+ } while(0)
+
+#ifndef NAND_NO_RB
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int _tries = 0; \
+ while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
+ if (++_tries > 100000) \
+ break; \
+ } while (0)
+#else
+#define NAND_WAIT_READY(nand) udelay(12)
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define WRITE_NAND(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define READ_NAND(adr) \
+ ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
+ * CxOE and CxRESET. We use the CxOE.
+ */
+#define STATUS_LED_BIT 0x00000080 /* bit 24 */
+
+#define STATUS_LED_PERIOD (CFG_HZ / 2)
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+ do { \
+ ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
+ } while(0)
+
+#define __led_set(_msk, _st) \
+ do { \
+ if ((_st)) \
+ ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
+ else \
+ ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
+ } while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/******************************************************************************/
+
+#define CFG_CONSOLE_IS_IN_ENV 1
+#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
+#define CFG_CONSOLE_ENV_OVERWRITE 1
+
+/******************************************************************************/
+
+/* use board specific hardware */
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SHOW_ACTIVITY
+
+/*****************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_CRC32_VERIFY 1
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
+
+/* Note: change below for your network setting!!!
+ * This was done just to facilitate manufacturing test and configuration.
+ */
+#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
+
+#define CONFIG_SERVERIP 192.168.08.1
+#define CONFIG_IPADDR 192.168.08.85
+#define CONFIG_GATEWAYIP 192.168.08.1
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_HOSTNAME stx_xtc
+#define CONFIG_ROOTPATH /xtcroot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_LOADADDR 0x1000000
+
+
+#endif /* __CONFIG_H */
CFG_CMD_JFFS2 | \
CFG_CMD_DATE )
-
-/* Flash banks JFFS2 should use */
-#define CFG_JFFS2_FIRST_BANK 1
-#define CFG_JFFS2_NUM_BANKS 1
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor1"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor1=v37-1"
+#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)"
+*/
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define VOICEBLUE_LED_REG 0x04030000
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00040000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=voiceblue-0"
+#define MTDPARTS_DEFAULT "mtdparts=voiceblue-0:128k(uboot),64k(env),64k(renv),-(jffs2)"
+*/
+
#endif /* __CONFIG_H */
/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2000-2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
+ /* ...and on a SYCAMORE board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=walnut\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/walnut/uImage\0" \
+ "kernel_addr=fff80000\0" \
+ "ramdisk_addr=fff80000\0" \
+ "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run net_nfs"
-/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
-#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#else
-#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
#if 0
-#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
- "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS "root=/dev/hda1 " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
-
-#endif
+#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
+ CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
-#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD 691200
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
/*-----------------------------------------------------------------------
- * PCI stuff
+ * I2C stuff
*-----------------------------------------------------------------------
*/
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
/*-----------------------------------------------------------------------
- * External peripheral base address
+ * PCI stuff
*-----------------------------------------------------------------------
*/
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CFG_KEY_REG_BASE_ADDR 0xF0100000
-#define CFG_IR_REG_BASE_ADDR 0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFF80000
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#endif
/*
* For booting Linux, the board info and command line data
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
/*-----------------------------------------------------------------------
* FLASH organization
*/
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-/* BEG ENVIRONNEMENT FLASH */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
/*-----------------------------------------------------------------------
* NVRAM organization
*/
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+ /* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
*/
-#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x9B015480
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB1AP 0x02815480
+#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
+#define CFG_EBC_PB2AP 0x04815A80
+#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB3AP 0x01815280
+#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB7AP 0x01815280
+#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#define CFG_KEY_REG_BASE_ADDR 0xF0100000
+#define CFG_IR_REG_BASE_ADDR 0xF0200000
+#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
+ * Definitions for initial stack pointer and data area
*/
-#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
+#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
-#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
*/
-#define SPD_EEPROM_ADDRESS 0x50
+#define SPD_EEPROM_ADDRESS 0x50
/*
* Internal Definitions
* GP30 == SDATA_OUT is 0
* GP81 == NSSPCLK is 0
*/
-#define CFG_GPCR0_VAL 0x40C31868
+#define CFG_GPCR0_VAL 0x40C31848
#define CFG_GPCR1_VAL 0x00000000
#define CFG_GPCR2_VAL 0x00020000
* [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
* [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
* [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
- * [03] 0 - 32 Bit bus width
+ * [03] 1 - 16 Bit bus width
* [02:00] 100 - variable latency I/O
*/
-#define CFG_MSC1_VAL 0x1224A264
+#define CFG_MSC1_VAL 0x1224A26C
/* This is the configuration for nCS4/5 -> LAN
* configuration for nCS5:
#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
#define CFG_FLASH_BASE PHYS_FLASH_1
-#define CFG_JFFS2_NUM_BANKS 1
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS_CUSTOM_PART 1
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=xsengine-0"
+#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
+*/
/* Environment settings */
#define CONFIG_ENV_OVERWRITE
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * yellowstone.h - configuration for YELLOWSTONE board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */
+#define CONFIG_440GR 1 /* Specific PPC440GR support */
+
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#undef CFG_DRAM_TEST /* disable - takes long time! */
+#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE 0x50000000
+#define CFG_NVRAM_BASE_ADDR 0x80000000
+#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
+#define CFG_INIT_RAM_END 0x2000
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
+#define CFG_SDRAM_BANKS (2)
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SERIAL_MULTI 1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
+ * The DS1558 code assumes this condition
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#define CFG_ENV_IS_IN_EEPROM 1
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x0
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
+#define CONFIG_BOOTDELAY 3 /* disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1 /* required for netconsole */
+#define CONFIG_PHY1_ADDR 3
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 10.0.4.251
+#define CONFIG_ETHADDR 00:10:EC:00:12:34
+#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SERVERIP 10.0.4.115
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG /* watchdog */
+#endif
+
+#ifdef CONFIG_440EP
+ /* Need to define POST */
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ /* CFG_CMD_EXT2 |*/ \
+ /* CFG_CMD_FAT |*/ \
+ CFG_CMD_I2C | \
+ /* CFG_CMD_IDE |*/ \
+ CFG_CMD_IRQ | \
+ /* CFG_CMD_KGDB |*/ \
+ CFG_CMD_MII | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_FLASH | \
+ /* CFG_CMD_SPI |*/ \
+ CFG_CMD_USB | \
+ 0 ) & ~CFG_CMD_IMLS)
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ /* CFG_CMD_EXT2 |*/ \
+ /* CFG_CMD_FAT |*/ \
+ CFG_CMD_I2C | \
+ /* CFG_CMD_IDE |*/ \
+ CFG_CMD_IRQ | \
+ /* CFG_CMD_KGDB |*/ \
+ CFG_CMD_MII | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_FLASH | \
+ /* CFG_CMD_SPI |*/ \
+ 0 ) & ~CFG_CMD_IMLS)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI 1 /* support kdi files */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * yosemite.h - configuration for YOSEMITE board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_YOSEMITE 1 /* Board is Yosemite */
+#define CONFIG_440EP 1 /* Specific PPC440EP support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
+#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE 0x50000000
+#define CFG_NVRAM_BASE_ADDR 0x80000000
+#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
+#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
+#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
+#define CFG_SDRAM_BANKS (2)
+
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=yosemite\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/yosemite/uImage\0" \
+ "kernel_addr=fc000000\0" \
+ "ramdisk_addr=fc100000\0" \
+ "load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \
+ "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
+ "cp.b 100000 fff80000 80000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1 /* required for netconsole */
+#define CONFIG_PHY1_ADDR 3
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG /* watchdog */
+#endif
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_USB )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI 1 /* support kdi files */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
* the internal memory map aligns the above structure on
* a 0x20 byte boundary
*/
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_MPC85xx
#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
#else
#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
*
*/
-/* this struct is very similar to mtd_info */
-struct part_info {
- u32 size; /* Total size of the Partition */
-
- /* "Major" erase size for the device. Naïve users may take this
- * to be the only erase size available, or may use the more detailed
- * information below if they desire
- */
- u32 erasesize;
+#include <linux/list.h>
- /* Where in memory does this partition start? */
- char *offset;
+/* mtd device types */
+#define MTD_DEV_TYPE_NOR 0x0001
+#define MTD_DEV_TYPE_NAND 0x0002
+#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : "nor")
- /* used by jffs2 set to NULL */
- void *jffs2_priv;
-
- /* private filed used by user */
- void *usr_priv;
+struct mtd_device {
+ struct list_head link;
+ struct mtdids *id; /* parent mtd id entry */
+ u16 num_parts; /* number of partitions on this device */
+ struct list_head parts; /* partitions */
};
-struct part_info*
-jffs2_part_info(int part_num);
-
-struct kernel_loader {
-
- /* Return true if there is a kernel contained at src */
- int (* check_magic)(struct part_info *part);
-
- /* load the kernel from the partition part to dst, return the number
- * of bytes copied if successful, zero if not */
- u32 (* load_kernel)(u32 *dst, struct part_info *part, const char *kernel_filename);
+struct part_info {
+ struct list_head link;
+ char *name; /* partition name */
+ u8 auto_name; /* set to 1 for generated name */
+ u32 size; /* total size of the partition */
+ u32 offset; /* offset within device */
+ void *jffs2_priv; /* used internaly by jffs2 */
+ u32 mask_flags; /* kernel MTD mask flags */
+ struct mtd_device *dev; /* parent device */
+};
- /* A brief description of the module (ie, "cramfs") */
- char *name;
+struct mtdids {
+ struct list_head link;
+ u8 type; /* device type */
+ u8 num; /* device number */
+ u32 size; /* device size */
+ char *mtd_id; /* linux kernel device id */
};
#define ldr_strlen strlen
# include <asm/byteorder.h>
#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */
-/************************************************************************/
-/* ** LOGO DATA */
-/************************************************************************/
-#ifdef CONFIG_LCD_LOGO
-# include <bmp_logo.h> /* Get logo data, width and height */
-#endif
-
/*
* Information about displays we are using. This is for configuring
* the LCD controller and memory allocation. Someone has to know what
#define LCD_COLOR16 4
/*----------------------------------------------------------------------*/
-#if defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
# define LCD_INFO_X 0
# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
#elif defined(CONFIG_LCD_LOGO)
#endif /* color definitions */
-#if defined(CONFIG_LCD_LOGO) && (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
-# error Default Color Map overlaps with Logo Color Map
-#endif
-
/************************************************************************/
#ifndef PAGE_SIZE
# define PAGE_SIZE 4096
/************************************************************************/
/* ** CONSOLE DEFINITIONS & FUNCTIONS */
/************************************************************************/
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \
/ VIDEO_FONT_HEIGHT)
#else
--- /dev/null
+#ifndef _LINUX_LIST_H
+#define _LINUX_LIST_H
+
+#ifndef ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCH
+static inline void prefetch(const void *x) {;}
+#endif
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+
+struct list_head {
+ struct list_head *next, *prev;
+};
+
+#define LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define LIST_HEAD(name) \
+ struct list_head name = LIST_HEAD_INIT(name)
+
+#define INIT_LIST_HEAD(ptr) do { \
+ (ptr)->next = (ptr); (ptr)->prev = (ptr); \
+} while (0)
+
+/*
+ * Insert a new entry between two known consecutive entries.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_add(struct list_head *new,
+ struct list_head *prev,
+ struct list_head *next)
+{
+ next->prev = new;
+ new->next = next;
+ new->prev = prev;
+ prev->next = new;
+}
+
+/**
+ * list_add - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it after
+ *
+ * Insert a new entry after the specified head.
+ * This is good for implementing stacks.
+ */
+static inline void list_add(struct list_head *new, struct list_head *head)
+{
+ __list_add(new, head, head->next);
+}
+
+/**
+ * list_add_tail - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it before
+ *
+ * Insert a new entry before the specified head.
+ * This is useful for implementing queues.
+ */
+static inline void list_add_tail(struct list_head *new, struct list_head *head)
+{
+ __list_add(new, head->prev, head);
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_del(struct list_head *prev, struct list_head *next)
+{
+ next->prev = prev;
+ prev->next = next;
+}
+
+/**
+ * list_del - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty on entry does not return true after this, the entry is in an undefined state.
+ */
+static inline void list_del(struct list_head *entry)
+{
+ __list_del(entry->prev, entry->next);
+ entry->next = (void *) 0;
+ entry->prev = (void *) 0;
+}
+
+/**
+ * list_del_init - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static inline void list_del_init(struct list_head *entry)
+{
+ __list_del(entry->prev, entry->next);
+ INIT_LIST_HEAD(entry);
+}
+
+/**
+ * list_move - delete from one list and add as another's head
+ * @list: the entry to move
+ * @head: the head that will precede our entry
+ */
+static inline void list_move(struct list_head *list, struct list_head *head)
+{
+ __list_del(list->prev, list->next);
+ list_add(list, head);
+}
+
+/**
+ * list_move_tail - delete from one list and add as another's tail
+ * @list: the entry to move
+ * @head: the head that will follow our entry
+ */
+static inline void list_move_tail(struct list_head *list,
+ struct list_head *head)
+{
+ __list_del(list->prev, list->next);
+ list_add_tail(list, head);
+}
+
+/**
+ * list_empty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static inline int list_empty(struct list_head *head)
+{
+ return head->next == head;
+}
+
+static inline void __list_splice(struct list_head *list,
+ struct list_head *head)
+{
+ struct list_head *first = list->next;
+ struct list_head *last = list->prev;
+ struct list_head *at = head->next;
+
+ first->prev = head;
+ head->next = first;
+
+ last->next = at;
+ at->prev = last;
+}
+
+/**
+ * list_splice - join two lists
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice(struct list_head *list, struct list_head *head)
+{
+ if (!list_empty(list))
+ __list_splice(list, head);
+}
+
+/**
+ * list_splice_init - join two lists and reinitialise the emptied list.
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_init(struct list_head *list,
+ struct list_head *head)
+{
+ if (!list_empty(list)) {
+ __list_splice(list, head);
+ INIT_LIST_HEAD(list);
+ }
+}
+
+/**
+ * list_entry - get the struct for this entry
+ * @ptr: the &struct list_head pointer.
+ * @type: the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_entry(ptr, type, member) \
+ ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member)))
+
+/**
+ * list_for_each - iterate over a list
+ * @pos: the &struct list_head to use as a loop counter.
+ * @head: the head for your list.
+ */
+#define list_for_each(pos, head) \
+ for (pos = (head)->next, prefetch(pos->next); pos != (head); \
+ pos = pos->next, prefetch(pos->next))
+/**
+ * list_for_each_prev - iterate over a list backwards
+ * @pos: the &struct list_head to use as a loop counter.
+ * @head: the head for your list.
+ */
+#define list_for_each_prev(pos, head) \
+ for (pos = (head)->prev, prefetch(pos->prev); pos != (head); \
+ pos = pos->prev, prefetch(pos->prev))
+
+/**
+ * list_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos: the &struct list_head to use as a loop counter.
+ * @n: another &struct list_head to use as temporary storage
+ * @head: the head for your list.
+ */
+#define list_for_each_safe(pos, n, head) \
+ for (pos = (head)->next, n = pos->next; pos != (head); \
+ pos = n, n = pos->next)
+
+/**
+ * list_for_each_entry - iterate over list of given type
+ * @pos: the type * to use as a loop counter.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_for_each_entry(pos, head, member) \
+ for (pos = list_entry((head)->next, typeof(*pos), member), \
+ prefetch(pos->member.next); \
+ &pos->member != (head); \
+ pos = list_entry(pos->member.next, typeof(*pos), member), \
+ prefetch(pos->member.next))
+
+/**
+ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos: the type * to use as a loop counter.
+ * @n: another type * to use as temporary storage
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_safe(pos, n, head, member) \
+ for (pos = list_entry((head)->next, typeof(*pos), member), \
+ n = list_entry(pos->member.next, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_continue - iterate over list of given type
+ * continuing after existing point
+ * @pos: the type * to use as a loop counter.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_continue(pos, head, member) \
+ for (pos = list_entry(pos->member.next, typeof(*pos), member), \
+ prefetch(pos->member.next); \
+ &pos->member != (head); \
+ pos = list_entry(pos->member.next, typeof(*pos), member), \
+ prefetch(pos->member.next))
+
+#endif
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc83xx.h
+ *
+ * MPC83xx specific definitions
+ */
+
+#ifndef __MPC83XX_H__
+#define __MPC83XX_H__
+
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/*
+ * MPC83xx cpu provide RCR register to do reset thing specially. easier
+ * to implement
+ */
+
+#define MPC83xx_RESET
+
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET 0x0100
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define CONFIG_DEFAULT_IMMR 0xFF400000
+
+/*
+ * Watchdog
+ */
+#define SWCRR 0x0204
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
+#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+#define SWCNR 0x0208
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES ~(SWCNR_SWCN)
+
+#define SWSRR 0x020E
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define IMMRBAR 0x0000
+#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
+#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define LBLAWBAR0 0x0020
+#define LBLAWAR0 0x0024
+#define LBLAWBAR1 0x0028
+#define LBLAWAR1 0x002C
+#define LBLAWBAR2 0x0030
+#define LBLAWAR2 0x0034
+#define LBLAWBAR3 0x0038
+#define LBLAWAR3 0x003C
+
+
+/*
+ * Base Registers & Option Registers
+ */
+#define BR0 0x5000
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_GPCM_AM 0xFFFF8000
+#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT 12
+#define OR_GPCM_CSNT 0x00000800
+#define OR_GPCM_CSNT_SHIFT 11
+#define OR_GPCM_ACS 0x00000600
+#define OR_GPCM_ACS_SHIFT 9
+#define OR_GPCM_XACS 0x00000100
+#define OR_GPCM_XACS_SHIFT 8
+#define OR_GPCM_SCY 0x000000F0
+#define OR_GPCM_SCY_SHIFT 4
+#define OR_GPCM_SETA 0x00000008
+#define OR_GPCM_SETA_SHIFT 3
+#define OR_GPCM_TRLX 0x00000004
+#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_EHTR 0x00000002
+#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EAD 0x00000001
+#define OR_GPCM_EAD_SHIFT 0
+
+#define OR_UPM_AM 0xFFFF8000
+#define OR_UPM_AM_SHIFT 15
+#define OR_UPM_XAM 0x00006000
+#define OR_UPM_XAM_SHIFT 13
+#define OR_UPM_BCTLD 0x00001000
+#define OR_UPM_BCTLD_SHIFT 12
+#define OR_UPM_BI 0x00000100
+#define OR_UPM_BI_SHIFT 8
+#define OR_UPM_TRLX 0x00000004
+#define OR_UPM_TRLX_SHIFT 2
+#define OR_UPM_EHTR 0x00000002
+#define OR_UPM_EHTR_SHIFT 1
+#define OR_UPM_EAD 0x00000001
+#define OR_UPM_EAD_SHIFT 0
+
+#define OR_SDRAM_AM 0xFFFF8000
+#define OR_SDRAM_AM_SHIFT 15
+#define OR_SDRAM_XAM 0x00006000
+#define OR_SDRAM_XAM_SHIFT 13
+#define OR_SDRAM_COLS 0x00001C00
+#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_ROWS 0x000001C0
+#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_PMSEL 0x00000020
+#define OR_SDRAM_PMSEL_SHIFT 5
+#define OR_SDRAM_EAD 0x00000001
+#define OR_SDRAM_EAD_SHIFT 0
+
+/*
+ * Hard Reset Configration Word - High
+ */
+#define HRCWH_PCI_AGENT 0x00000000
+#define HRCWH_PCI_HOST 0x80000000
+
+#define HRCWH_32_BIT_PCI 0x00000000
+#define HRCWH_64_BIT_PCI 0x40000000
+
+#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
+
+#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
+
+#define HRCWH_CORE_DISABLE 0x08000000
+#define HRCWH_CORE_ENABLE 0x00000000
+
+#define HRCWH_FROM_0X00000100 0x00000000
+#define HRCWH_FROM_0XFFF00100 0x04000000
+
+#define HRCWH_BOOTSEQ_DISABLE 0x00000000
+#define HRCWH_BOOTSEQ_NORMAL 0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
+
+#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
+
+#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
+#define HRCWH_ROM_LOC_PCI1 0x00100000
+#define HRCWH_ROM_LOC_PCI2 0x00200000
+#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
+
+#define HRCWH_TSEC1M_IN_RGMII 0x00000000
+#define HRCWH_TSEC1M_IN_RTBI 0x00004000
+#define HRCWH_TSEC1M_IN_GMII 0x00008000
+#define HRCWH_TSEC1M_IN_TBI 0x0000C000
+
+#define HRCWH_TSEC2M_IN_RGMII 0x00000000
+#define HRCWH_TSEC2M_IN_RTBI 0x00001000
+#define HRCWH_TSEC2M_IN_GMII 0x00002000
+#define HRCWH_TSEC2M_IN_TBI 0x00003000
+
+#define HRCWH_BIG_ENDIAN 0x00000000
+#define HRCWH_LITTLE_ENDIAN 0x00000008
+
+/*
+ * Hard Reset Configration Word - Low
+ */
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
+
+#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
+
+#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
+
+#define HRCWL_VCO_BYPASS 0x00000000
+#define HRCWL_VCO_1X2 0x00000000
+#define HRCWL_VCO_1X4 0x00200000
+#define HRCWL_VCO_1X8 0x00400000
+
+#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
+#define HRCWL_CORE_TO_CSB_1X1 0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
+#define HRCWL_CORE_TO_CSB_2X1 0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
+#define HRCWL_CORE_TO_CSB_3X1 0x00060000
+
+/*
+ * LCRR - Clock Ratio Register (10.3.1.16)
+ */
+#define LCRR_DBYP 0x80000000
+#define LCRR_DBYP_SHIFT 31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_1 0x10000000
+#define LCRR_BUFCMDC_2 0x20000000
+#define LCRR_BUFCMDC_3 0x30000000
+#define LCRR_BUFCMDC_4 0x00000000
+#define LCRR_BUFCMDC_SHIFT 28
+#define LCRR_ECL 0x03000000
+#define LCRR_ECL_4 0x00000000
+#define LCRR_ECL_5 0x01000000
+#define LCRR_ECL_6 0x02000000
+#define LCRR_ECL_7 0x03000000
+#define LCRR_ECL_SHIFT 24
+#define LCRR_EADC 0x00030000
+#define LCRR_EADC_1 0x00010000
+#define LCRR_EADC_2 0x00020000
+#define LCRR_EADC_3 0x00030000
+#define LCRR_EADC_4 0x00000000
+#define LCRR_EADC_SHIFT 16
+#define LCRR_CLKDIV 0x0000000F
+#define LCRR_CLKDIV_2 0x00000002
+#define LCRR_CLKDIV_4 0x00000004
+#define LCRR_CLKDIV_8 0x00000008
+#define LCRR_CLKDIV_SHIFT 0
+
+#endif /* __MPC83XX_H__ */
# endif
#endif /* CONFIG_MPC5xxx */
-#if !defined(CONFIG_NET_MULTI) && (defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_CPM2)
#include <config.h>
#if defined(CONFIG_ETHER_ON_FCC)
#if defined(CONFIG_ETHER_ON_SCC)
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
+/* From 440ep */
+#define PCI_ERREN 0x48 /* Error Enable */
+#define PCI_ERRSTS 0x49 /* Error Status */
+#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
+#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
+#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
+#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
+#define PCI_CAPID 0x58 /* Capability Identifier */
+#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
+#define PCI_PMC 0x5A /* Power Management Capabilities */
+#define PCI_PMCSR 0x5C /* Power Management Control Status */
+#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
+#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
+#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
+
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
#define icdbtrh 0x39f /* instruction cache debug tag register high */
#define mmucr 0x3b2 /* mmu control register */
#define ccr0 0x3b3 /* core configuration register 0 */
+#define ccr1 0x378 /* core configuration for 440x5 only */
#define icdbdr 0x3d3 /* instruction cache debug data register */
#define dbdr 0x3f3 /* debug data register */
#define clk_opbd 0x00c0
#define clk_perd 0x00e0
#define clk_mald 0x0100
+#define clk_spcid 0x0120
#define clk_icfg 0x0140
/* 440gx sdr register definations */
#define sdr_ebc 0x0100
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
+#define sdr_uart2 0x0122 /* UART2 Config */
+#define sdr_uart3 0x0123 /* UART3 Config */
#define sdr_cp440 0x0180
#define sdr_xcr 0x01c0
#define sdr_xpllc 0x01c1
#define sdr_xplld 0x01c2
#define sdr_srst 0x0200
#define sdr_slpipe 0x0220
-#define sdr_amp 0x0240
+#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
+#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
#define sdr_mirq0 0x0260
#define sdr_mirq1 0x0261
#define sdr_maltbl 0x0280
#define sdr_malrbl 0x02a0
#define sdr_maltbs 0x02c0
#define sdr_malrbs 0x02e0
+#define sdr_pci0 0x0300
+#define sdr_usb0 0x0320
#define sdr_cust0 0x4000
#define sdr_sdstp2 0x4001
#define sdr_cust1 0x4002
#define xbcfg 0x23 /* external bus configuration reg */
#define xbcid 0x23 /* external bus core id reg */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+/* PLB4 to PLB3 Bridge OUT */
+#define P4P3_DCR_BASE 0x020
+#define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
+#define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
+#define p4p3_eadr (P4P3_DCR_BASE+0x2)
+#define p4p3_euadr (P4P3_DCR_BASE+0x3)
+#define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
+#define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
+#define p4p3_confg (P4P3_DCR_BASE+0x6)
+#define p4p3_pic (P4P3_DCR_BASE+0x7)
+#define p4p3_peir (P4P3_DCR_BASE+0x8)
+#define p4p3_rev (P4P3_DCR_BASE+0xA)
+
+/* PLB3 to PLB4 Bridge IN */
+#define P3P4_DCR_BASE 0x030
+#define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
+#define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
+#define p3p4_eadr (P3P4_DCR_BASE+0x2)
+#define p3p4_euadr (P3P4_DCR_BASE+0x3)
+#define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
+#define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
+#define p3p4_confg (P3P4_DCR_BASE+0x6)
+#define p3p4_pic (P3P4_DCR_BASE+0x7)
+#define p3p4_peir (P3P4_DCR_BASE+0x8)
+#define p3p4_rev (P3P4_DCR_BASE+0xA)
+
+/* PLB3 Arbiter */
+#define PLB3_DCR_BASE 0x070
+#define plb3_revid (PLB3_DCR_BASE+0x2)
+#define plb3_besr (PLB3_DCR_BASE+0x3)
+#define plb3_bear (PLB3_DCR_BASE+0x6)
+#define plb3_acr (PLB3_DCR_BASE+0x7)
+
+/* PLB4 Arbiter - PowerPC440EP Pass1 */
+#define PLB4_DCR_BASE 0x080
+#define plb4_revid (PLB4_DCR_BASE+0x2)
+#define plb4_acr (PLB4_DCR_BASE+0x3)
+#define plb4_besr (PLB4_DCR_BASE+0x4)
+#define plb4_bearl (PLB4_DCR_BASE+0x6)
+#define plb4_bearh (PLB4_DCR_BASE+0x7)
+
+/* Nebula PLB4 Arbiter - PowerPC440EP */
+#define PLB_ARBITER_BASE 0x80
+
+#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
+#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
+#define plb0_acr_ppm_mask 0xF0000000
+#define plb0_acr_ppm_fixed 0x00000000
+#define plb0_acr_ppm_fair 0xD0000000
+#define plb0_acr_hbu_mask 0x08000000
+#define plb0_acr_hbu_disabled 0x00000000
+#define plb0_acr_hbu_enabled 0x08000000
+#define plb0_acr_rdp_mask 0x06000000
+#define plb0_acr_rdp_disabled 0x00000000
+#define plb0_acr_rdp_2deep 0x02000000
+#define plb0_acr_rdp_3deep 0x04000000
+#define plb0_acr_rdp_4deep 0x06000000
+#define plb0_acr_wrp_mask 0x01000000
+#define plb0_acr_wrp_disabled 0x00000000
+#define plb0_acr_wrp_2deep 0x01000000
+
+#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
+#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
+#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
+#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
+#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
+
+#define plb1_acr (PLB_ARBITER_BASE+ 0x09)
+#define plb1_acr_ppm_mask 0xF0000000
+#define plb1_acr_ppm_fixed 0x00000000
+#define plb1_acr_ppm_fair 0xD0000000
+#define plb1_acr_hbu_mask 0x08000000
+#define plb1_acr_hbu_disabled 0x00000000
+#define plb1_acr_hbu_enabled 0x08000000
+#define plb1_acr_rdp_mask 0x06000000
+#define plb1_acr_rdp_disabled 0x00000000
+#define plb1_acr_rdp_2deep 0x02000000
+#define plb1_acr_rdp_3deep 0x04000000
+#define plb1_acr_rdp_4deep 0x06000000
+#define plb1_acr_wrp_mask 0x01000000
+#define plb1_acr_wrp_disabled 0x00000000
+#define plb1_acr_wrp_2deep 0x01000000
+
+#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
+#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
+#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
+#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+
+/* USB Control Register */
+#define SDR0_USB0 0x0320
+#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
+#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
+#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
+#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
+#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
+#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
+
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0 0x4000
+#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
+
+#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
+
+#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
+
+#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+
+#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+
+#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
+
+#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
+
+#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
+#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
+
+#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
+
+/* CUST1 Customer Configuration Register1 */
+#define SDR0_CUST1 0x4002
+#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
+#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+
+/* Pin Function Control Register 0 */
+#define SDR0_PFC0 0x4100
+#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
+#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
+#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
+#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
+#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR 0x4300
+#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
+#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
+
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
+
+#else
+
/*-----------------------------------------------------------------------------
| Internal SRAM
+----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
+#endif /* !CONFIG_440EP !CONFIG_440GR*/
/*-----------------------------------------------------------------------------
| On-Chip Buses
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#define UIC2_DCR_BASE 0x210
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/* The following is for compatibility with 405 code */
#define uicsr uic0sr
#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
-#if defined(CONFIG_440_GX)
#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
-#endif /* CONFIG_440_GX */
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
/*---------------------------------------------------------------------------+
| Universal interrupt controller 2 interrupts (UIC2)
+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#define UIC_ETH2 0x80000000 /* Ethernet 2 */
#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
#define UIC_ETH3 0x20000000 /* Ethernet 3 */
#define UIC_RSVD29 0x00000004 /* Reserved */
#define UIC_RSVD30 0x00000002 /* Reserved */
#define UIC_RSVD31 0x00000001 /* Reserved */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller Base 0 interrupts (UICB0)
+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/*-----------------------------------------------------------------------------+
| External Bus Controller Bit Settings
#define EBC_BXCR_BW_MASK 0x00006000
#define EBC_BXCR_BW_8BIT 0x00000000
#define EBC_BXCR_BW_16BIT 0x00002000
-
+#define EBC_BXCR_BW_32BIT 0x00006000
#define EBC_BXAP_BME_ENABLED 0x80000000
#define EBC_BXAP_BME_DISABLED 0x00000000
#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
#define SDR0_MFR_ECS_MASK 0x10000000
#define SDR0_MFR_ECS_INTERNAL 0x10000000
+#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
+#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
+
#define SDR0_SRST_BGO 0x80000000
#define SDR0_SRST_PLB 0x40000000
#define SDR0_SRST_EBC 0x20000000
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440_GX)
+#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
-#else /* !CONFIG_440_GX */
+#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
+#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
+#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
+#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
+#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
+#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PRADV_MASK 0x07000000 /* Primary Divisor A */
+#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
+#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
+
#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+/* PCI Local Configuration Registers
+ --------------------------------- */
+#define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
+
+/* PCI Master Local Configuration Registers */
+#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
+#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
+#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
+#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
+#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
+#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
+#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
+#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
+#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
+#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
+#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
+#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
+
+/* PCI Target Local Configuration Registers */
+#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
+#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
+#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
+#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
+
+#else
+
#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
+#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
+
+/******************************************************************************
+ * GPIO macro register defines
+ ******************************************************************************/
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
+#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
+
+#define GPIO0_OR (GPIO_BASE0+0x0)
+#define GPIO0_TCR (GPIO_BASE0+0x4)
+#define GPIO0_OSRL (GPIO_BASE0+0x8)
+#define GPIO0_OSRH (GPIO_BASE0+0xC)
+#define GPIO0_TSRL (GPIO_BASE0+0x10)
+#define GPIO0_TSRH (GPIO_BASE0+0x14)
+#define GPIO0_ODR (GPIO_BASE0+0x18)
+#define GPIO0_IR (GPIO_BASE0+0x1C)
+#define GPIO0_RR1 (GPIO_BASE0+0x20)
+#define GPIO0_RR2 (GPIO_BASE0+0x24)
+#define GPIO0_RR3 (GPIO_BASE0+0x28)
+#define GPIO0_ISR1L (GPIO_BASE0+0x30)
+#define GPIO0_ISR1H (GPIO_BASE0+0x34)
+#define GPIO0_ISR2L (GPIO_BASE0+0x38)
+#define GPIO0_ISR2H (GPIO_BASE0+0x3C)
+#define GPIO0_ISR3L (GPIO_BASE0+0x40)
+#define GPIO0_ISR3H (GPIO_BASE0+0x44)
+
+#define GPIO1_OR (GPIO_BASE1+0x0)
+#define GPIO1_TCR (GPIO_BASE1+0x4)
+#define GPIO1_OSRL (GPIO_BASE1+0x8)
+#define GPIO1_OSRH (GPIO_BASE1+0xC)
+#define GPIO1_TSRL (GPIO_BASE1+0x10)
+#define GPIO1_TSRH (GPIO_BASE1+0x14)
+#define GPIO1_ODR (GPIO_BASE1+0x18)
+#define GPIO1_IR (GPIO_BASE1+0x1C)
+#define GPIO1_RR1 (GPIO_BASE1+0x20)
+#define GPIO1_RR2 (GPIO_BASE1+0x24)
+#define GPIO1_RR3 (GPIO_BASE1+0x28)
+#define GPIO1_ISR1L (GPIO_BASE1+0x30)
+#define GPIO1_ISR1H (GPIO_BASE1+0x34)
+#define GPIO1_ISR2L (GPIO_BASE1+0x38)
+#define GPIO1_ISR2H (GPIO_BASE1+0x3C)
+#define GPIO1_ISR3L (GPIO_BASE1+0x40)
+#define GPIO1_ISR3H (GPIO_BASE1+0x44)
+#endif
+
/*
* Macros for accessing the indirect EBC registers
*/
unsigned long pllFwdDivB;
unsigned long pllFbkDiv;
unsigned long pllOpbDiv;
+ unsigned long pllPciDiv;
unsigned long pllExtBusDiv;
unsigned long freqVCOMhz; /* in MHz */
unsigned long freqProcessor;
+ unsigned long freqTmrClk;
unsigned long freqPLB;
unsigned long freqOPB;
unsigned long freqEPB;
+ unsigned long freqPCI;
+ unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
+ unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
#endif /* _ASMLANGUAGE */
#define _SPD_H_
typedef struct spd_eeprom_s {
- unsigned char info_size; /* # of bytes written into serial memory */
- unsigned char chip_size; /* Total # of bytes of SPD memory device */
- unsigned char mem_type; /* Fundamental memory type (FPM, EDO, SDRAM...) */
- unsigned char nrow_addr; /* # of Row Addresses on this assembly */
- unsigned char ncol_addr; /* # of Column Addresses on this assembly */
- unsigned char nrows; /* # of Module Rows on this assembly */
- unsigned char dataw_lsb; /* Data Width of this assembly */
- unsigned char dataw_msb; /* ... Data Width continuation */
- unsigned char voltage; /* Voltage interface standard of this assembly */
- unsigned char clk_cycle; /* SDRAM Cycle time at CL=X */
- unsigned char clk_access; /* SDRAM Access from Clock at CL=X */
- unsigned char config; /* DIMM Configuration type (non-parity, ECC) */
- unsigned char refresh; /* Refresh Rate/Type */
- unsigned char primw; /* Primary SDRAM Width */
- unsigned char ecw; /* Error Checking SDRAM width */
- unsigned char min_delay; /* Min Clock Delay for Back to Back Random Address */
- unsigned char burstl; /* Burst Lengths Supported */
- unsigned char nbanks; /* # of Banks on Each SDRAM Device */
- unsigned char cas_lat; /* CAS# Latencies Supported */
- unsigned char cs_lat; /* CS# Latency */
- unsigned char write_lat; /* Write Latency (also called Write Recovery time) */
- unsigned char mod_attr; /* SDRAM Module Attributes */
- unsigned char dev_attr; /* SDRAM Device Attributes */
- unsigned char clk_cycle2; /* Min SDRAM Cycle time at CL=X-1 */
- unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1 */
- unsigned char clk_cycle3; /* Min SDRAM Cycle time at CL=X-2 */
- unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2 */
- unsigned char trp; /* Min Row Precharge Time (tRP) */
- unsigned char trrd; /* Min Row Active to Row Active (tRRD) */
- unsigned char trcd; /* Min RAS to CAS Delay (tRCD) */
- unsigned char tras; /* Minimum RAS Pulse Width (tRAS) */
- unsigned char row_dens; /* Density of each row on module */
- unsigned char ca_setup; /* Command and Address signal input setup time */
- unsigned char ca_hold; /* Command and Address signal input hold time */
- unsigned char data_setup; /* Data signal input setup time */
- unsigned char data_hold; /* Data signal input hold time */
- unsigned char sset[26]; /* Superset Information (may be used in future) */
- unsigned char spd_rev; /* SPD Data Revision Code */
- unsigned char cksum; /* Checksum for bytes 0-62 */
- unsigned char mid[8]; /* Manufacturer's JEDEC ID code per JEP-108E */
- unsigned char mloc; /* Manufacturing Location */
- unsigned char mpart[18]; /* Manufacturer's Part Number */
- unsigned char rev[2]; /* Revision Code */
- unsigned char mdate[2]; /* Manufacturing Date */
- unsigned char sernum[4]; /* Assembly Serial Number */
- unsigned char mspec[27]; /* Manufacturer Specific Data */
- unsigned char freq; /* Intel specification frequency */
- unsigned char intel_cas; /* Intel Specification CAS# Latency support */
+ unsigned char info_size; /* 0 # bytes written into serial memory */
+ unsigned char chip_size; /* 1 Total # bytes of SPD memory device */
+ unsigned char mem_type; /* 2 Fundamental memory type */
+ unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */
+ unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */
+ unsigned char nrows; /* 5 # of Module Rows on this assembly */
+ unsigned char dataw_lsb; /* 6 Data Width of this assembly */
+ unsigned char dataw_msb; /* 7 ... Data Width continuation */
+ unsigned char voltage; /* 8 Voltage intf std of this assembly */
+ unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */
+ unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */
+ unsigned char config; /* 11 DIMM Configuration type */
+ unsigned char refresh; /* 12 Refresh Rate/Type */
+ unsigned char primw; /* 13 Primary SDRAM Width */
+ unsigned char ecw; /* 14 Error Checking SDRAM width */
+ unsigned char min_delay; /* 15 for Back to Back Random Address */
+ unsigned char burstl; /* 16 Burst Lengths Supported */
+ unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */
+ unsigned char cas_lat; /* 18 CAS# Latencies Supported */
+ unsigned char cs_lat; /* 19 CS# Latency */
+ unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */
+ unsigned char mod_attr; /* 21 SDRAM Module Attributes */
+ unsigned char dev_attr; /* 22 SDRAM Device Attributes */
+ unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */
+ unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
+ unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */
+ unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
+ unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
+ unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
+ unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
+ unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
+ unsigned char row_dens; /* 31 Density of each row on module */
+ unsigned char ca_setup; /* 32 Cmd + Addr signal input setup time */
+ unsigned char ca_hold; /* 33 Cmd and Addr signal input hold time */
+ unsigned char data_setup; /* 34 Data signal input setup time */
+ unsigned char data_hold; /* 35 Data signal input hold time */
+ unsigned char twr; /* 36 Write Recovery time tWR */
+ unsigned char twtr; /* 37 Int write to read delay tWTR */
+ unsigned char trtp; /* 38 Int read to precharge delay tRTP */
+ unsigned char mem_probe; /* 39 Mem analysis probe characteristics */
+ unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+ unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
+ unsigned char trfc; /* 42 Min Auto to Active period tRFC */
+ unsigned char tckmax; /* 43 Max device cycle time tCKmax */
+ unsigned char tdqsq; /* 44 Max DQS to DQ skew */
+ unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */
+ unsigned char pll_relock; /* 46 PLL Relock time */
+ unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */
+ unsigned char spd_rev; /* 62 SPD Data Revision Code */
+ unsigned char cksum; /* 63 Checksum for bytes 0-62 */
+ unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-108E */
+ unsigned char mloc; /* 72 Manufacturing Location */
+ unsigned char mpart[18]; /* 73 Manufacturer's Part Number */
+ unsigned char rev[2]; /* 91 Revision Code */
+ unsigned char mdate[2]; /* 93 Manufacturing Date */
+ unsigned char sernum[4]; /* 95 Assembly Serial Number */
+ unsigned char mspec[27]; /* 99 Manufacturer Specific Data */
+
+ /*
+ * Open for Customer Use starting with byte 128.
+ */
+ unsigned char freq; /* 128 Intel spec: frequency */
+ unsigned char intel_cas; /* 129 Intel spec: CAS# Latency support */
} spd_eeprom_t;
+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM (0x01)
+#define SPD_MEMTYPE_EDO (0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
+#define SPD_MEMTYPE_SDRAM (0x04)
+#define SPD_MEMTYPE_ROM (0x05)
+#define SPD_MEMTYPE_SGRAM (0x06)
+#define SPD_MEMTYPE_DDR (0x07)
+#define SPD_MEMTYPE_DDR2 (0x08)
+
#endif /* _SPD_H_ */
/***** NetPhone ********************************************************/
#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* XXX empty just to avoid the error */
+/***** STx XTc ********************************************************/
+#elif defined(CONFIG_STXXTC)
+/* XXX empty just to avoid the error */
/***** sbc8240 ********************************************************/
#elif defined(CONFIG_WRSBC8240)
/* XXX empty just to avoid the error */
#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
-
/* String descriptor */
struct usb_string_descriptor {
unsigned char bLength;
#define USB_MAX_STOR_DEV 5
block_dev_desc_t *usb_stor_get_dev(int index);
int usb_stor_scan(int mode);
+void usb_stor_info(void);
#endif
#ifndef _USB_DEFS_H_
#define _USB_DEFS_H_
-
-/* Everything is aribtrary */
-#define USB_ALTSETTINGALLOC 4
-#define USB_MAXALTSETTING 128 /* Hard limit */
-
-#define USB_MAX_DEVICE 32
-#define USB_MAXCONFIG 8
-#define USB_MAXINTERFACES 8
-#define USB_MAXENDPOINTS 16
-#define USB_MAXCHILDREN 8 /* This is arbitrary */
-#define USB_MAX_HUB 16
-
-#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
-
/* USB constants */
/* Device and/or Interface Class codes */
#ifndef __VERSION_H__
#define __VERSION_H__
-#define U_BOOT_VERSION "U-Boot 1.1.3"
+#define U_BOOT_VERSION "U-Boot 1.1.4"
#endif /* __VERSION_H__ */
#include <net.h>
#include <serial.h>
#ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260)||defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
#include <commproc.h>
#endif
#endif
init_timebase,
#endif
#ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
dpram_init,
#endif
#endif
prt_8260_rsr,
prt_8260_clks,
#endif /* CONFIG_8260 */
+
+#if defined(CONFIG_MPC83XX)
+ print_clock_conf,
+#endif
+
checkcpu,
#if defined(CONFIG_MPC5xxx)
prt_mpc5xxx_clks,
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#endif
#if defined(CONFIG_MPC5xxx)
bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
#endif
+#if defined(CONFIG_MPC83XX)
+ bd->bi_immrbar = CFG_IMMRBAR;
+#endif
#if defined(CONFIG_MPC8220)
bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
bd->bi_inpfreq = gd->inp_clk;
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
bd->bi_cpmfreq = gd->cpm_clk;
bd->bi_brgfreq = gd->brg_clk;
bd->bi_sccfreq = gd->scc_clk;
bd->bi_vco = gd->vco_out;
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC5xxx)
bd->bi_ipbfreq = gd->ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
bd->bi_pci_busfreq = get_PCI_freq ();
bd->bi_opbfreq = get_OPB_freq ();
#elif defined(CONFIG_XILINX_ML300)
/* handle the 3rd ethernet address */
s = getenv ("eth2addr");
-#if defined(CONFIG_XPEDITE1K)
+#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
if (s == NULL)
board_get_enetaddr(bd->bi_enet2addr);
else
#ifdef CONFIG_HAS_ETH3
/* handle 4th ethernet address */
s = getenv("eth3addr");
-#if defined(CONFIG_XPEDITE1K)
+#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
if (s == NULL)
board_get_enetaddr(bd->bi_enet3addr);
else
ln -s asm-$2 asm
rm -f asm-$2/arch
-if [ -z "$6" -o "$6" == "NULL" ] ; then
+if [ -z "$6" -o "$6" = "NULL" ] ; then
ln -s arch-$3 asm-$2/arch
else
ln -s arch-$6 asm-$2/arch
extern int rtl8169_initialize(bd_t*);
extern int scc_initialize(bd_t*);
extern int skge_initialize(bd_t*);
-extern int tsec_initialize(bd_t*, int);
+extern int tsec_initialize(bd_t*, int, char *);
static struct eth_device *eth_devices, *eth_current;
skge_initialize(bis);
#endif
#if defined(CONFIG_MPC85XX_TSEC1)
- tsec_initialize(bis, 0);
+ tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME);
+#elif defined(CONFIG_MPC83XX_TSEC1)
+ tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME);
#endif
#if defined(CONFIG_MPC85XX_TSEC2)
- tsec_initialize(bis, 1);
+ tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME);
+#elif defined(CONFIG_MPC83XX_TSEC2)
+ tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME);
#endif
#if defined(CONFIG_MPC85XX_FEC)
- tsec_initialize(bis, 2);
+ tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
+#else
+# if defined(CONFIG_MPC85XX_TSEC3)
+ tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME);
+# elif defined(CONFIG_MPC83XX_TSEC3)
+ tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME);
+# endif
+# if defined(CONFIG_MPC85XX_TSEC4)
+ tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME);
+# elif defined(CONFIG_MPC83XX_TSEC4)
+ tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
+# endif
#endif
#if defined(CONFIG_AU1X00)
au1x00_enet_initialize(bis);
*
* DHCP:
*
- * Prerequisites: - own ethernet address
- * We want: - IP, Netmask, ServerIP, Gateway IP
- * - bootfilename, lease time
- * Next step: - TFTP
+ * Prerequisites: - own ethernet address
+ * We want: - IP, Netmask, ServerIP, Gateway IP
+ * - bootfilename, lease time
+ * Next step: - TFTP
*
* TFTP:
*
*
* SNTP:
*
- * Prerequisites: - own ethernet address
+ * Prerequisites: - own ethernet address
* - own IP address
* We want: - network time
* Next step: none
IPaddr_t NetArpWaitPacketIP;
IPaddr_t NetArpWaitReplyIP;
uchar *NetArpWaitPacketMAC; /* MAC address of waiting packet's destination */
-uchar *NetArpWaitTxPacket; /* THE transmit packet */
+uchar *NetArpWaitTxPacket; /* THE transmit packet */
int NetArpWaitTxPacketSize;
uchar NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
ulong NetArpWaitTimerStart;
arp->ar_pln = 4;
arp->ar_op = htons (ARPOP_REQUEST);
- memcpy (&arp->ar_data[0], NetOurEther, 6); /* source ET addr */
- NetWriteIP ((uchar *) & arp->ar_data[6], NetOurIP); /* source IP addr */
+ memcpy (&arp->ar_data[0], NetOurEther, 6); /* source ET addr */
+ NetWriteIP ((uchar *) & arp->ar_data[6], NetOurIP); /* source IP addr */
for (i = 10; i < 16; ++i) {
arp->ar_data[i] = 0; /* dest ET addr = 0 */
}
*/
NetOurIP = 0;
NetServerIP = getenv_IPaddr ("serverip");
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
- NetOurNativeVLAN = getenv_VLAN("nvlan");
- case CDP:
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
- NetOurNativeVLAN = getenv_VLAN("nvlan");
+ NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
+ NetOurNativeVLAN = getenv_VLAN("nvlan");
+ case CDP:
+ NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
+ NetOurNativeVLAN = getenv_VLAN("nvlan");
break;
default:
break;
puts (" ICMP Host Redirect to ");
print_IPaddr(icmph->un.gateway);
putc(' ');
- break;
+ return;
#if (CONFIG_COMMANDS & CFG_CMD_PING)
case ICMP_ECHO_REPLY:
/*
*/
/* XXX point to ip packet */
(*packetHandler)((uchar *)ip, 0, 0, 0);
- break;
+ return;
#endif
default:
return;
return;
}
+#ifdef CONFIG_UDP_CHECKSUM
+ if (ip->udp_xsum != 0) {
+ ulong xsum;
+ ushort *sumptr;
+ ushort sumlen;
+
+ xsum = ip->ip_p;
+ xsum += (ntohs(ip->udp_len));
+ xsum += (ntohl(ip->ip_src) >> 16) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_src) >> 0) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_dst) >> 16) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_dst) >> 0) & 0x0000ffff;
+
+ sumlen = ntohs(ip->udp_len);
+ sumptr = (ushort *) &(ip->udp_src);
+
+ while (sumlen > 1) {
+ ushort sumdata;
+
+ sumdata = *sumptr++;
+ xsum += ntohs(sumdata);
+ sumlen -= 2;
+ }
+ if (sumlen > 0) {
+ ushort sumdata;
+
+ sumdata = *(unsigned char *) sumptr;
+ sumdata = (sumdata << 8) & 0xff00;
+ xsum += sumdata;
+ }
+ while ((xsum >> 16) != 0) {
+ xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff);
+ }
+ if ((xsum != 0x00000000) && (xsum != 0x0000ffff)) {
+ printf(" UDP wrong checksum %08x %08x\n", xsum, ntohs(ip->udp_xsum));
+ return;
+ }
+ }
+#endif
+
#ifdef CONFIG_NETCONSOLE
nc_input_packet((uchar *)ip +IP_HDR_SIZE,
ntohs(ip->udp_dst),
return (1);
}
#if (CONFIG_COMMANDS & (CFG_CMD_PING | CFG_CMD_SNTP))
- common:
+ common:
#endif
if (NetOurIP == 0) {
static char dirfh[NFS_FHSIZE]; /* file handle of directory */
static char filefh[NFS_FHSIZE]; /* file handle of kernel image */
+static int NfsDownloadState;
static IPaddr_t NfsServerIP;
static int NfsSrvMountPort;
static int NfsSrvNfsPort;
static char *nfs_path;
static char nfs_path_buff[2048];
-static __inline__ void
+static __inline__ int
store_block (uchar * src, unsigned offset, unsigned len)
{
ulong newsize = offset + len;
rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len);
if (rc) {
flash_perror (rc);
- NetState = NETLOOP_FAIL;
- return;
+ return -1;
}
} else
#endif /* CFG_DIRECT_FLASH_NFS */
if (NetBootFileXferSize < (offset+len))
NetBootFileXferSize = newsize;
+ return 0;
}
static char*
}
rlen = ntohl(rpc_pkt.u.reply.data[18]);
- store_block ((uchar *)pkt+sizeof(rpc_pkt.u.reply), nfs_offset, rlen);
+ if ( store_block ((uchar *)pkt+sizeof(rpc_pkt.u.reply), nfs_offset, rlen) )
+ return -9999;
return rlen;
}
NetState = NETLOOP_FAIL;
} else {
puts ("\ndone\n");
- NetState = NETLOOP_SUCCESS;
+ NetState = NfsDownloadState;
}
break;
NfsState = STATE_READLINK_REQ;
NfsSend ();
} else {
+ if ( ! rlen ) NfsDownloadState = NETLOOP_SUCCESS;
NfsState = STATE_UMOUNT_REQ;
NfsSend ();
}
#ifdef NFS_DEBUG
printf ("%s\n", __FUNCTION__);
#endif
+ NfsDownloadState = NETLOOP_FAIL;
NfsServerIP = NetServerIP;
nfs_path = (char *)nfs_path_buff;
}
if (BootFile[0] == '\0') {
- IPaddr_t OurIP = ntohl (NetOurIP);
-
sprintf (default_filename, "/nfsroot/%02lX%02lX%02lX%02lX.img",
- OurIP & 0xFF,
- (OurIP >> 8) & 0xFF,
- (OurIP >> 16) & 0xFF,
- (OurIP >> 24) & 0xFF );
+ NetOurIP & 0xFF,
+ (NetOurIP >> 8) & 0xFF,
+ (NetOurIP >> 16) & 0xFF,
+ (NetOurIP >> 24) & 0xFF );
strcpy (nfs_path, default_filename);
printf ("*** Warning: no boot file name; using '%s'\n",
TftpStart (void)
{
if (BootFile[0] == '\0') {
- IPaddr_t OurIP = ntohl(NetOurIP);
-
sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",
- OurIP & 0xFF,
- (OurIP >> 8) & 0xFF,
- (OurIP >> 16) & 0xFF,
- (OurIP >> 24) & 0xFF );
+ NetOurIP & 0xFF,
+ (NetOurIP >> 8) & 0xFF,
+ (NetOurIP >> 16) & 0xFF,
+ (NetOurIP >> 24) & 0xFF );
tftp_filename = default_filename;
printf ("*** Warning: no boot file name; using '%s'\n",
char *p, sign;
int dec, frac;
+ if (val == -1) {
+ return "I/O ERROR";
+ }
+
if (unit_val < 0) {
sign = '-';
unit_val = -unit_val;
}
val = t->sysmon->read(t->sysmon, t->addr);
- t->val_valid = val >= t->val_min && val <= t->val_max;
- t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
+ if (val != -1) {
+ t->val_valid = val >= t->val_min && val <= t->val_max;
+ t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
+ } else {
+ t->val_valid = 0;
+ t->val_valid_alt = 0;
+ }
if (t->exec_after) {
t->exec_after(t);
Hymod Board Database
(C) Copyright 2001
-Murray Jensen <Murray.Jensen@cmst.csiro.au>
+Murray Jensen <Murray.Jensen@csiro.au>
CSIRO Manufacturing Science and Technology, Preston Lab
25-Jun-01
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
require("defs.php");
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// list page (hymod_bddb / boards)
pg_head("$bddb_label - Browse Board Log");
- if (!isset($serno) || $serno == 0)
- die("serial number not specified!");
+ $serno=intval($serno);
+ if ($serno == 0)
+ die("serial number not specified or invalid!");
function print_cell($str) {
if ($str == '')
<hr></hr>
<p></p>
<?php
- $limit=abs(isset($limit)?$limit:20);
- $offset=abs(isset($offset)?$offset:0);
+ $limit=abs(isset($_REQUEST['limit'])?$_REQUEST['limit']:20);
+ $offset=abs(isset($_REQUEST['offset'])?$_REQUEST['offset']:0);
$lr=mysql_query("select count(*) as n from log where serno=$serno");
$lrow=mysql_fetch_array($lr);
if($lrow['n']>$limit){
$preoffset=max(0,$offset-$limit);
$postoffset=$offset+$limit;
echo "<table width=\"100%\">\n<tr align=center>\n";
- printf("<td><%sa href=\"%s?serno=$serno&offset=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
- printf("<td><%sa href=\"%s?serno=$serno&offset=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
+ printf("<td><%sa href=\"%s?s
ubmit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
+ printf("<td><%sa href=\"%s?s
ubmit=Log&serno=$serno&offset=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
echo "</tr>\n</table>\n";
}
mysql_free_result($lr);
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// list page (hymod_bddb / boards)
require("defs.php");
- if (!isset($verbose))
- $verbose = 0;
+ $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
- if (!isset($serno))
- $serno = 0;
+ $verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0;
pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":""));
?>
<p></p>
<?php
- if ($serno == 0) {
- $limit=abs(isset($limit)?$limit:20);
- $offset=abs(isset($offset)?$offset:0);
+ $limit=isset($_REQUEST['limit'])?abs(intval($_REQUEST['limit'])):20;
+ $offset=isset($_REQUEST['offset'])?abs(intval($_REQUEST['offset'])):0;
+
+ if ($serno == '') {
+
$lr=mysql_query("select count(*) as n from boards");
$lrow=mysql_fetch_array($lr);
+
if($lrow['n']>$limit){
$preoffset=max(0,$offset-$limit);
$postoffset=$offset+$limit;
- echo "<table width=\"100%\">\n<tr align=center>\n";
- printf("<td><%sa href=\"%s?offset=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
- printf("<td><%sa href=\"%s?offset=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
+ echo "<table width=\"100%\">\n<tr>\n";
+ printf("<td align=left><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose);
+ printf("<td align=right><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset);
echo "</tr>\n</table>\n";
}
+
mysql_free_result($lr);
}
?>
?>
</tr>
<?php
- if ($serno == 0)
- $r=mysql_query("select * from boards order by serno limit $offset,$limit");
- else
- $r=mysql_query("select * from boards where serno=$serno");
+ $query = "select * from boards";
+ if ($serno != '') {
+ $pre = " where ";
+ foreach (preg_split("/[\s,]+/", $serno) as $s) {
+ if (preg_match('/^[0-9]+$/',$s))
+ $query .= $pre . "serno=" . $s;
+ else if (preg_match('/^([0-9]+)-([0-9]+)$/',$s,$m)) {
+ $m1 = intval($m[1]); $m2 = intval($m[2]);
+ if ($m2 <= $m1)
+ die("bad serial number range ($s)");
+ $query .= $pre . "(serno>=$m[1] and serno<=$m[2])";
+ }
+ else
+ die("illegal serial number ($s)");
+ $pre = " or ";
+ }
+ }
+ $query .= " order by serno";
+ if ($serno == '')
+ $query .= " limit $offset,$limit";
+
+ $r = mysql_query($query);
function print_cell($str) {
if ($str == '')
<table width="100%">
<tr>
<td align=center><?php
- if ($verbose)
- echo "<a href=\"browse.php?verbose=0\">Terse Listing</a>";
- else
- echo "<a href=\"browse.php?verbose=1\">Verbose Listing</a>";
+ printf("<a href=\"%s?submit=Browse&offset=%d&verbose=%d%s\">%s Listing</a>\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose");
?></td>
<td align=center><a href="index.php">Back to Start</a></td>
</tr>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// mysql database access info
# Host: localhost Database : hymod_bddb
# (C) Copyright 2001
-# Murray Jensen <Murray.Jensen@cmst.csiro.au>
-# CSIRO Manufacturing Science and Technology, Preston Lab
+# Murray Jensen <Murray.Jensen@csiro.au>
+# CSIRO Manufacturing and Infrastructure Technology, Preston Lab
# --------------------------------------------------------
#
rev tinyint(3) unsigned zerofill NOT NULL,
location char(64),
comments text,
- sdram0 enum('32M','64M','128M','256M'),
- sdram1 enum('32M','64M','128M','256M'),
- sdram2 enum('32M','64M','128M','256M'),
- sdram3 enum('32M','64M','128M','256M'),
- flash0 enum('4M','8M','16M','32M','64M'),
- flash1 enum('4M','8M','16M','32M','64M'),
- flash2 enum('4M','8M','16M','32M','64M'),
- flash3 enum('4M','8M','16M','32M','64M'),
- zbt0 enum('512K','1M','2M','4M'),
- zbt1 enum('512K','1M','2M','4M'),
- zbt2 enum('512K','1M','2M','4M'),
- zbt3 enum('512K','1M','2M','4M'),
- zbt4 enum('512K','1M','2M','4M'),
- zbt5 enum('512K','1M','2M','4M'),
- zbt6 enum('512K','1M','2M','4M'),
- zbt7 enum('512K','1M','2M','4M'),
- zbt8 enum('512K','1M','2M','4M'),
- zbt9 enum('512K','1M','2M','4M'),
- zbta enum('512K','1M','2M','4M'),
- zbtb enum('512K','1M','2M','4M'),
- zbtc enum('512K','1M','2M','4M'),
- zbtd enum('512K','1M','2M','4M'),
- zbte enum('512K','1M','2M','4M'),
- zbtf enum('512K','1M','2M','4M'),
- xlxtyp0 enum('XCV300E','XCV400E','XCV600E'),
- xlxtyp1 enum('XCV300E','XCV400E','XCV600E'),
- xlxtyp2 enum('XCV300E','XCV400E','XCV600E'),
- xlxtyp3 enum('XCV300E','XCV400E','XCV600E'),
- xlxspd0 enum('6','7','8'),
- xlxspd1 enum('6','7','8'),
- xlxspd2 enum('6','7','8'),
- xlxspd3 enum('6','7','8'),
+ sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ zbt0 enum('512K','1M','2M','4M','8M','16M'),
+ zbt1 enum('512K','1M','2M','4M','8M','16M'),
+ zbt2 enum('512K','1M','2M','4M','8M','16M'),
+ zbt3 enum('512K','1M','2M','4M','8M','16M'),
+ zbt4 enum('512K','1M','2M','4M','8M','16M'),
+ zbt5 enum('512K','1M','2M','4M','8M','16M'),
+ zbt6 enum('512K','1M','2M','4M','8M','16M'),
+ zbt7 enum('512K','1M','2M','4M','8M','16M'),
+ zbt8 enum('512K','1M','2M','4M','8M','16M'),
+ zbt9 enum('512K','1M','2M','4M','8M','16M'),
+ zbta enum('512K','1M','2M','4M','8M','16M'),
+ zbtb enum('512K','1M','2M','4M','8M','16M'),
+ zbtc enum('512K','1M','2M','4M','8M','16M'),
+ zbtd enum('512K','1M','2M','4M','8M','16M'),
+ zbte enum('512K','1M','2M','4M','8M','16M'),
+ zbtf enum('512K','1M','2M','4M','8M','16M'),
+ xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxspd0 enum('6','7','8','4','5','9','10','11','12'),
+ xlxspd1 enum('6','7','8','4','5','9','10','11','12'),
+ xlxspd2 enum('6','7','8','4','5','9','10','11','12'),
+ xlxspd3 enum('6','7','8','4','5','9','10','11','12'),
xlxtmp0 enum('COM','IND'),
xlxtmp1 enum('COM','IND'),
xlxtmp2 enum('COM','IND'),
xlxgrd1 enum('NORMAL','ENGSAMP'),
xlxgrd2 enum('NORMAL','ENGSAMP'),
xlxgrd3 enum('NORMAL','ENGSAMP'),
- cputyp enum('MPC8260'),
- cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ'),
- cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ'),
- busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ'),
- hstype enum('AMCC-S2064A'),
- hschin enum('0','1','2','3','4'),
- hschout enum('0','1','2','3','4'),
+ cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'),
+ cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
+ cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
+ busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
+ hstype enum('AMCC-S2064A','Xilinx-Rockets'),
+ hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
+ hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
PRIMARY KEY (serno),
KEY serno (serno),
UNIQUE serno_2 (serno)
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// contains mysql user id and password - keep secret
require("config.php");
- if (isset($logout)) {
+ if (isset($_REQUEST['logout'])) {
Header("status: 401 Unauthorized");
Header("HTTP/1.0 401 Unauthorized");
Header("WWW-authenticate: basic realm=\"$bddb_label\"");
// board type
$type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY');
- // sdram sizes (nbits array is for write into eeprom config file)
- $sdram_vals = array('','32M','64M','128M','256M');
- $sdram_nbits = array(0,25,26,27,28);
+ // Xilinx fpga types
+ $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140');
- // flash sizes (nbits array is for write into eeprom config file)
- $flash_vals = array('','4M','8M','16M','32M','64M');
- $flash_nbits = array(0,22,23,24,25,26);
+ // Xilinx fpga speeds
+ $xlxspd_vals = array('','6','7','8','4','5','9','10','11','12');
- // zbt ram sizes (nbits array is for write into eeprom config file)
- $zbt_vals = array('','512K','1M','2M','4M');
- $zbt_nbits = array(0,19,20,21,22);
-
- // Xilinx attributes
- $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000');
- $xlxspd_vals = array('','6','7','8','4','5');
+ // Xilinx fpga temperatures (commercial or industrial)
$xlxtmp_vals = array('','COM','IND');
+
+ // Xilinx fpga grades (normal or engineering sample)
$xlxgrd_vals = array('','NORMAL','ENGSAMP');
- // processor attributes
- $cputyp_vals = array('','MPC8260');
- $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ');
+ // CPU types
+ $cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560');
+
+ // CPU/BUS/CPM clock speeds
+ $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ');
+
+ // sdram sizes (nbits array is for eeprom config file)
+ $sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G');
+ $sdram_nbits = array(0,25,26,27,28,29,30,31,32);
+
+ // flash sizes (nbits array is for eeprom config file)
+ $flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G');
+ $flash_nbits = array(0,22,23,24,25,26,27,28,29,30);
+
+ // zbt ram sizes (nbits array is for write into eeprom config file)
+ $zbt_vals = array('','512K','1M','2M','4M','8M','16M');
+ $zbt_nbits = array(0,19,20,21,22,23,24);
// high-speed serial attributes
- $hstype_vals = array('','AMCC-S2064A');
- $hschin_vals = array('0','1','2','3','4');
- $hschout_vals = array('0','1','2','3','4');
+ $hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets');
+ $hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
+ $hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
// value filters - used when outputting html
function rev_filter($num) {
echo "<hr></hr>\n";
echo "<table width=\"100%\"><tr><td align=left>\n<address>" .
"If you have any problems, email " .
- "<a href=\"mailto:Murray.Jensen@cmst.csiro.au\">" .
+ "<a href=\"mailto:Murray.Jensen@csiro.au\">" .
"Murray Jensen" .
"</a></address>\n" .
"</td><td align=right>\n" .
end_field();
}
+ // print a mysql ENUM as an html SELECT INPUT
+ function print_enum_select($name, $array, $vals, $def = -1) {
+
+ begin_field($name);
+
+ echo "\t\t<select name=$name>\n";
+
+ if (key_in_array($name, $array))
+ $chk = array_search($array[$name], $vals, FALSE);
+ else
+ $chk = $def;
+
+ $nval = count($vals);
+
+ for ($i = 0; $i < $nval; $i++) {
+
+ $val = $vals[$i];
+ if ($val == '')
+ $pval = "none";
+ else
+ $pval = "$val";
+
+ printf("\t\t\t<option " .
+ "value=\"%s\"%s>%s</option>\n",
+ $val, $i == $chk ? " selected" : "", $pval);
+ }
+
+ echo "\t\t</select>\n";
+
+ end_field();
+ }
+
// print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT
function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) {
$name = sprintf("%s%x", $base, $i);
- if (isset($GLOBALS[$name])) {
+ if (isset($_REQUEST[$name])) {
$retval .= sprintf(", %s='%s'",
- $name, $GLOBALS[$name]);
+ $name, $_REQUEST[$name]);
}
}
$name = sprintf("%s%x", $base, $i);
- if (isset($GLOBALS[$name]))
+ if (isset($_REQUEST[$name]))
$retval++;
}
function gen_eth_addr($serno) {
- $ethaddr_high = (mt_rand(0, 65535) & 0xfeff) | 0x0200;
- $ethaddr_low = mt_rand(0, 4294967295);
+ $ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200;
+ $ethaddr_mid = mt_rand(0, 65535);
+ $ethaddr_low = mt_rand(0, 65535);
return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx",
- $ethaddr_high >> 8, $ethaddr_high & 0xff,
- $ethaddr_low >> 24, ($ethaddr_low >> 16) & 0xff,
- ($ethaddr_low >> 8) & 0xff, $ethaddr_low & 0xff);
+ $ethaddr_hgh >> 8, $ethaddr_hgh & 0xff,
+ $ethaddr_mid >> 8, $ethaddr_mid & 0xff,
+ $ethaddr_low >> 8, $ethaddr_low & 0xff);
}
// check that an ethernet address is valid
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// dodelete page (hymod_bddb / boards)
pg_head("$bddb_label - Delete Board Results");
- if (!($serno=intval($serno)))
+ if (!isset($_REQUEST['serno']))
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
mysql_query("delete from boards where serno=$serno");
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// dodelete page (hymod_bddb / boards)
pg_head("$bddb_label - Delete Log Entry Results");
- if (!($serno=intval($serno)))
+ if (!isset($_REQUEST['serno']))
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
- if (!isset($logno) || $logno == 0)
+ if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0)
die("the log entry number not specified!");
+ $logno=$_REQUEST['logno'];
mysql_query("delete from log where serno=$serno and logno=$logno");
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
pg_head("$bddb_label - Edit Board Results");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
$query="update boards set";
- if (isset($ethaddr)) {
+ if (isset($_REQUEST['ethaddr'])) {
+ $ethaddr=$_REQUEST['ethaddr'];
if (!eth_addr_is_valid($ethaddr))
die("ethaddr is invalid ('$ethaddr')");
$query.=" ethaddr='$ethaddr',";
}
- if (isset($date)) {
+ if (isset($_REQUEST['date'])) {
+ $date=$_REQUEST['date'];
list($y, $m, $d) = split("-", $date);
if (!checkdate($m, $d, $y) || $y < 1999)
die("date is invalid (input '$date', " .
$query.=" date='$date'";
}
- if (isset($batch)) {
+ if (isset($_REQUEST['batch'])) {
+ $batch=$_REQUEST['batch'];
if (strlen($batch) > 32)
die("batch field too long (>32)");
$query.=", batch='$batch'";
}
- if (isset($type)) {
+ if (isset($_REQUEST['type'])) {
+ $type=$_REQUEST['type'];
if (!in_array($type, $type_vals))
die("Invalid type ($type) specified");
$query.=", type='$type'";
}
- if (isset($rev)) {
+ if (isset($_REQUEST['rev'])) {
+ $rev=$_REQUEST['rev'];
if (($rev = intval($rev)) <= 0 || $rev > 255)
die("Revision number is invalid ($rev)");
$query.=sprintf(", rev=%d", $rev);
}
- if (isset($location)) {
+ if (isset($_REQUEST['location'])) {
+ $location=$_REQUEST['location'];
if (strlen($location) > 64)
die("location field too long (>64)");
$query.=", location='$location'";
}
- if (isset($comments))
+ if (isset($_REQUEST['comments']))
+ $comments=$_REQUEST['comments'];
$query.=", comments='" . rawurlencode($comments) . "'";
$query.=gather_enum_multi_query("sdram", 4);
if (count_enum_multi("xlxgrd", 4) != $nxlx)
die("number of xilinx grades not same as number of types");
- if (isset($cputyp)) {
+ if (isset($_REQUEST['cputyp'])) {
+ $cputyp=$_REQUEST['cputyp'];
$query.=", cputyp='$cputyp'";
- if ($cpuspd == '')
+ if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '')
die("must specify cpu speed if cpu type is defined");
+ $cpuspd=$_REQUEST['cpuspd'];
$query.=", cpuspd='$cpuspd'";
- if ($cpmspd == '')
+ if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '')
die("must specify cpm speed if cpu type is defined");
+ $cpmspd=$_REQUEST['cpmspd'];
$query.=", cpmspd='$cpmspd'";
- if ($busspd == '')
+ if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '')
die("must specify bus speed if cpu type is defined");
+ $busspd=$_REQUEST['busspd'];
$query.=", busspd='$busspd'";
}
else {
- if (isset($cpuspd))
+ if (isset($_REQUEST['cpuspd']))
die("can't specify cpu speed if there is no cpu");
- if (isset($cpmspd))
+ if (isset($_REQUEST['cpmspd']))
die("can't specify cpm speed if there is no cpu");
- if (isset($busspd))
+ if (isset($_REQUEST['busspd']))
die("can't specify bus speed if there is no cpu");
}
- if (isset($hschin)) {
+ if (isset($_REQUEST['hschin'])) {
+ $hschin=$_REQUEST['hschin'];
if (($hschin = intval($hschin)) < 0 || $hschin > 4)
die("Invalid number of hs input chans ($hschin)");
}
else
$hschin = 0;
- if (isset($hschout)) {
+ if (isset($_REQUEST['hschout'])) {
+ $hschout=$_REQUEST['hschout'];
if (($hschout = intval($hschout)) < 0 || $hschout > 4)
die("Invalid number of hs output chans ($hschout)");
}
else
$hschout = 0;
- if (isset($hstype))
+ if (isset($_REQUEST['hstype'])) {
+ $hstype=$_REQUEST['hstype'];
$query.=", hstype='$hstype'";
+ }
else {
- if ($hschin != 0)
+ if ($_REQUEST['hschin'] != 0)
die("number of high-speed input channels must be zero"
. " if high-speed chip is not present");
- if ($hschout != 0)
+ if ($_REQUEST['hschout'] != 0)
die("number of high-speed output channels must be zero"
. " if high-speed chip is not present");
}
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
pg_head("$bddb_label - Edit Log Entry Results");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
- if (!isset($logno) || $logno == 0)
+ if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
die("log number not specified!");
+ $logno=intval($_REQUEST['logno']);
$query="update log set";
- if (isset($date)) {
+ if (isset($_REQUEST['date'])) {
+ $date=$_REQUEST['date'];
list($y, $m, $d) = split("-", $date);
if (!checkdate($m, $d, $y) || $y < 1999)
die("date is invalid (input '$date', " .
$query.=" date='$date'";
}
- if (isset($who))
+ if (isset($_REQUEST['who'])) {
+ $who=$_REQUEST['who'];
$query.=", who='" . $who . "'";
+ }
- if (isset($details))
+ if (isset($_REQUEST['details'])) {
+ $details=$_REQUEST['details'];
$query.=", details='" . rawurlencode($details) . "'";
+ }
$query.=" where serno=$serno and logno=$logno";
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
pg_head("$bddb_label - Board Registration Results");
- if (($serno=intval($serno)) != 0)
+ if (isset($_REQUEST['serno'])) {
+ $serno=$_REQUEST['serno'];
die("serial number must not be set ($serno) when Creating!");
+ }
$query="update boards set";
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
pg_head("$bddb_label - Add Log Entry Results");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("serial number not specified!");
+ $serno=intval($_REQUEST['serno']);
- if (isset($logno))
+ if (isset($_REQUEST['logno'])) {
+ $logno=$_REQUEST['logno'];
die("log number must not be set ($logno) when Creating!");
+ }
$query="update log set serno=$serno";
die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')");
$query.=", date='$date'";
- if (isset($who))
+ if (isset($_REQUEST['who'])) {
+ $who=$_REQUEST['who'];
$query.=", who='" . $who . "'";
+ }
- if (isset($details))
+ if (isset($_REQUEST['details'])) {
+ $details=$_REQUEST['details'];
$query.=", details='" . rawurlencode($details) . "'";
+ }
// echo "final query = '$query'<br>\n";
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
pg_head("$bddb_label - Edit Board Registration");
if ($serno == 0)
- die("serial number not specified!");
+ die("serial number not specified or invalid!");
$pserno = sprintf("%010d", $serno);
// xlxgrd[0-3] enum('NORMAL','ENGSAMP')
print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1);
- // cputyp enum('MPC8260')
+ // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
print_enum("cputyp", $row, $cputyp_vals);
- // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpuspd", $row, $clk_vals);
+ // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpuspd", $row, $clk_vals);
- // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpmspd", $row, $clk_vals);
+ // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpmspd", $row, $clk_vals);
- // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("busspd", $row, $clk_vals);
+ // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("busspd", $row, $clk_vals);
// hstype enum('AMCC-S2064A')
print_enum("hstype", $row, $hstype_vals);
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
pg_head("$bddb_label - Edit Board Log Entry");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("serial number not specified!");
+ $serno=intval($_REQUEST['serno']);
- if (!isset($logno) || $logno == 0)
+ if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
die("log number not specified!");
+ $logno=intval($_REQUEST['logno']);
$pserno = sprintf("%010d", $serno);
$plogno = sprintf("%010d", $logno);
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
- if (!isset($serno))
- $serno = 0;
- else
- $serno = intval($serno);
+ $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
- if (!isset($submit))
- $submit = "[NOT SET]";
+ $submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]";
switch ($submit) {
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
require("defs.php");
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
<form action=donew.php method=POST>
<p></p>
<?php
+ $serno=intval($serno);
// if a serial number was supplied, fetch the record
// and use its contents as defaults
if ($serno != 0) {
else
$row = array();
- echo "<input type=hidden name=serno value=0>\n";
-
begin_table(5);
// date date
// xlxgrd[0-3] enum('NORMAL','ENGSAMP')
print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1);
- // cputyp enum('MPC8260')
+ // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
print_enum("cputyp", $row, $cputyp_vals, 1);
- // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpuspd", $row, $clk_vals, 4);
+ // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpuspd", $row, $clk_vals, 4);
- // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpmspd", $row, $clk_vals, 4);
+ // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpmspd", $row, $clk_vals, 4);
- // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("busspd", $row, $clk_vals, 2);
+ // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("busspd", $row, $clk_vals, 2);
// hstype enum('AMCC-S2064A')
print_enum("hstype", $row, $hstype_vals, 1);
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
pg_head("$bddb_label - New Log Entry");
- if ($serno == 0)
- die("serial number not specified!");
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
+ die("serial number not specified or invalid!");
+ $serno=intval($_REQUEST['serno']);
- if (isset($logno))
- die("log number must not be specified when adding!");
+ if (isset($_REQUEST['logno'])) {
+ $logno=$_REQUEST['logno'];
+ die("log number must not be specified when adding! ($logno)");
+ }
?>
<form action=donewlog.php method=POST>
<p></p>
print_field("date", array('date' => date("Y-m-d")));
// who char(20)
- print_field("who", "");
+ print_field("who", array());
// details text
print_field_multiline("details", array(), 60, 10, 'text_filter');
#include <stdlib.h>
#include <unistd.h>
-#define __ASSEMBLY__ /* Dirty trick to get only #defines */
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__ /* Dirty trick to get only #defines */
+#endif
+#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
#include <config.h>
#undef __ASSEMBLY__
int main (int argc, char **argv)
{
#ifdef ENV_IS_EMBEDDED
- int crc ;
- unsigned char *envptr = &environment,
- *dataptr = envptr + ENV_HEADER_SIZE;
- unsigned int datasize = ENV_SIZE;
+ int crc;
+ unsigned char *envptr = &environment,
+ *dataptr = envptr + ENV_HEADER_SIZE;
+ unsigned int datasize = ENV_SIZE;
- crc = crc32(0, dataptr, datasize) ;
+ crc = crc32 (0, dataptr, datasize);
- /* Check if verbose mode is activated passing a parameter to the program */
- if (argc > 1) {
- printf("CRC32 from offset %08X to %08X of environment = %08X\n",
- (unsigned int)(dataptr - envptr),
- (unsigned int)(dataptr - envptr) + datasize,
- crc);
- } else {
- printf("0x%08X\n", crc);
- }
+ /* Check if verbose mode is activated passing a parameter to the program */
+ if (argc > 1) {
+ printf ("CRC32 from offset %08X to %08X of environment = %08X\n",
+ (unsigned int) (dataptr - envptr),
+ (unsigned int) (dataptr - envptr) + datasize,
+ crc);
+ } else {
+ printf ("0x%08X\n", crc);
+ }
#else
- printf("0\n");
+ printf ("0\n");
#endif
- return EXIT_SUCCESS;
+ return EXIT_SUCCESS;
}
#
# (C) Copyright 2000
-# Murray Jensen <Murray.Jensen@cmst.csiro.au>
+# Murray Jensen <Murray.Jensen@csiro.au>
#
# See file CREDITS for list of people who contributed to this
# project.
projects / platform / kernel / u-boot.git / commitdiff