riscv: cpu: jh7110: Add support for jh7110 SoC 49/291949/1
authorYanhong Wang <yanhong.wang@starfivetech.com>
Wed, 29 Mar 2023 03:42:08 +0000 (11:42 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 25 Apr 2023 06:25:06 +0000 (15:25 +0900)
commitc715c7c3a1be07a19b76e0e1db5882a3dfa1a14d
treeece48a6a71443fab1bba1db9814ff1886182106a
parent81ba1b56b7d58de1d7016b1b60d35aa3028b4613
riscv: cpu: jh7110: Add support for jh7110 SoC

Add StarFive JH7110 SoC to support RISC-V arch.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit 218534153ec8932a873dcca48a1a2b4aba0e32b5)

Change-Id: Id2377db738c5f419c81564089435a7b3b24519b8
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
arch/riscv/cpu/jh7110/Makefile [new file with mode: 0644]
arch/riscv/cpu/jh7110/cpu.c [new file with mode: 0644]
arch/riscv/cpu/jh7110/dram.c [new file with mode: 0644]
arch/riscv/cpu/jh7110/spl.c [new file with mode: 0644]
arch/riscv/include/asm/arch-jh7110/regs.h [new file with mode: 0644]
arch/riscv/include/asm/arch-jh7110/spl.h [new file with mode: 0644]