mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE

[platform/kernel/u-boot.git] / include / configs / suvd3.h

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 6aacbc2..8b3b454 100644 (file)
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -43,26 +43,11 @@
 #define CONFIG_83XX_PCICLK             66000000
 
 /*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR                0xE0000000
-
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
-
-/*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
@@ -110,9 +95,6 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-/* FLASH */
-#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -122,9 +104,6 @@
  * PRIO1/PIGGY on the local bus CS1
  */
 
-/* KMBEC_FPGA */
-#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -212,14 +191,6 @@
 #define CONFIG_SYS_BOOTMAPSZ           (8 << 20)
 
 /*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          (HID0_ENABLE_MACHINE_CHECK | \
-                                        HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2                        HID2_HBE
-
-/*
  * Internal Definitions
  */
 #define BOOTFLASH_START        0xF0000000
@@ -318,10 +289,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP   0x80000000
-#define CONFIG_SYS_LCRR_EADC   0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
-
 #define CONFIG_SYS_LBC_LBCR    0x00000000
 
 #define CONFIG_SYS_APP1_BASE           0xA0000000
@@ -342,13 +309,7 @@
  *
  */
 
-/* APP1 */
-#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V)
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB)
 
-/* APP2 */
-#define CONFIG_SYS_BR3_PRELIM  (0xB0000000 | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
 
 #define CONFIG_SYS_MAMR        (MxMR_GPL_x4DIS | \
                         0x0000c000 | \