mpc83xx: Kconfig: Migrate HRCW to Kconfig

[platform/kernel/u-boot.git] / include / configs / sbc8349.h

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 2520a77..fd67aca 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -22,12 +22,6 @@
 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2             /* support for 2nd PCI controller */
 
-#ifdef CONFIG_PCI_33M
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_8X1
-#else  /* 66M */
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_4X1
-#endif
-
 #define CONFIG_SYS_IMMR                0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
@@ -374,71 +368,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A