include/configs/yosemite.h

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************
   9  * yosemite.h - configuration for Yosemite & Yellowstone boards
  10  ***********************************************************************/
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*-----------------------------------------------------------------------
  15  * High Level Configuration Options
  16  *----------------------------------------------------------------------*/
  17 /* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
  18 #ifndef CONFIG_YELLOWSTONE
  19 #define CONFIG_440EP            1       /* Specific PPC440EP support    */
  20 #define CONFIG_HOSTNAME         yosemite
  21 #else
  22 #define CONFIG_440GR            1       /* Specific PPC440GR support    */
  23 #define CONFIG_HOSTNAME         yellowstone
  24 #endif
  25 #define CONFIG_440              1       /* ... PPC440 family            */
  26 #define CONFIG_SYS_CLK_FREQ     66666666    /* external freq to pll     */
  27
  28 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  29
  30 /*
  31  * Include common defines/options for all AMCC eval boards
  32  */
  33 #include "amcc-common.h"
  34
  35 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  36 #define CONFIG_BOARD_RESET      1       /* call board_reset()           */
  37
  38 /*-----------------------------------------------------------------------
  39  * Base addresses -- Note these are effective addresses where the
  40  * actual resources get mapped (not physical addresses)
  41  *----------------------------------------------------------------------*/
  42 #define CONFIG_SYS_FLASH_BASE           0xfc000000          /* start of FLASH   */
  43 #define CONFIG_SYS_PCI_MEMBASE          0xa0000000          /* mapped pci memory*/
  44 #define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  45 #define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  46 #define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  47
  48 /*Don't change either of these*/
  49 #define CONFIG_SYS_PCI_BASE             0xe0000000          /* internal PCI regs*/
  50 /*Don't change either of these*/
  51
  52 #define CONFIG_SYS_USB_DEVICE          0x50000000
  53 #define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
  54 #define CONFIG_SYS_BCSR_BASE            (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
  55 #define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
  56
  57 /*-----------------------------------------------------------------------
  58  * Initial RAM & stack pointer (placed in SDRAM)
  59  *----------------------------------------------------------------------*/
  60 #define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  61 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000              /* DCache       */
  62 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  63 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  64 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  65
  66 /*-----------------------------------------------------------------------
  67  * Serial Port
  68  *----------------------------------------------------------------------*/
  69 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  70 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200 /* use external 11.059MHz clk  */
  71
  72 /*-----------------------------------------------------------------------
  73  * Environment
  74  *----------------------------------------------------------------------*/
  75 /*
  76  * Define here the location of the environment variables (FLASH or EEPROM).
  77  * Note: DENX encourages to use redundant environment in FLASH.
  78  */
  79 #if 1
  80 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  81 #else
  82 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars      */
  83 #endif
  84
  85 /*-----------------------------------------------------------------------
  86  * FLASH related
  87  *----------------------------------------------------------------------*/
  88 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
  89 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
  90 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1                /* AMD RESET for STM 29W320DB!  */
  91
  92 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
  93 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
  94
  95 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
  96 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
  97
  98 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
  99
 100 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 101
 102 #ifdef CONFIG_ENV_IS_IN_FLASH
 103 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 104 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 105 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 106
 107 /* Address and size of Redundant Environment Sector     */
 108 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 109 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 110 #endif /* CONFIG_ENV_IS_IN_FLASH */
 111
 112 /*-----------------------------------------------------------------------
 113  * DDR SDRAM
 114  *----------------------------------------------------------------------*/
 115 #undef CONFIG_SPD_EEPROM               /* Don't use SPD EEPROM for setup    */
 116 #define CONFIG_SYS_KBYTES_SDRAM        (128 * 1024)    /* 128MB             */
 117 #define CONFIG_SYS_SDRAM_BANKS          (2)
 118
 119 /*-----------------------------------------------------------------------
 120  * I2C
 121  *----------------------------------------------------------------------*/
 122 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 123
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 126 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 128
 129 #ifdef CONFIG_ENV_IS_IN_EEPROM
 130 #define CONFIG_ENV_SIZE         0x200       /* Size of Environment vars */
 131 #define CONFIG_ENV_OFFSET               0x0
 132 #endif /* CONFIG_ENV_IS_IN_EEPROM */
 133
 134 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 135 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 136 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 137 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 138 #define CONFIG_SYS_DTT_MAX_TEMP 70
 139 #define CONFIG_SYS_DTT_LOW_TEMP -30
 140 #define CONFIG_SYS_DTT_HYSTERESIS       3
 141
 142 /*
 143  * Default environment variables
 144  */
 145 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 146         CONFIG_AMCC_DEF_ENV                                             \
 147         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 148         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 149         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 150         "kernel_addr=fc000000\0"                                        \
 151         "ramdisk_addr=fc180000\0"                                       \
 152         ""
 153
 154 #define CONFIG_HAS_ETH0         1       /* add support for "ethaddr"    */
 155 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 156 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 157 #define CONFIG_PHY1_ADDR        3
 158
 159 /* Partitions */
 160
 161 #ifdef CONFIG_440EP
 162 /* USB */
 163 #define CONFIG_USB_OHCI_NEW
 164 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 165
 166 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 167 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 168 #define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
 169 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 170 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 171
 172 /* Comment this out to enable USB 1.1 device */
 173 #define USB_2_0_DEVICE
 174
 175 #define CONFIG_SUPPORT_VFAT
 176 #endif /* CONFIG_440EP */
 177
 178 #ifdef DEBUG
 179 #define CONFIG_PANIC_HANG
 180 #else
 181 #define CONFIG_HW_WATCHDOG                      /* watchdog */
 182 #endif
 183
 184 /*
 185  * Commands additional to the ones defined in amcc-common.h
 186  */
 187 #define CONFIG_CMD_DTT
 188 #define CONFIG_CMD_PCI
 189
 190 #ifdef CONFIG_440EP
 191 #endif
 192
 193 /*-----------------------------------------------------------------------
 194  * PCI stuff
 195  *-----------------------------------------------------------------------
 196  */
 197 /* General PCI */
 198 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 199 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 200 #define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 201
 202 /* Board-specific PCI */
 203 #define CONFIG_SYS_PCI_TARGET_INIT
 204 #define CONFIG_SYS_PCI_MASTER_INIT
 205
 206 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 207 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever */
 208
 209 /*-----------------------------------------------------------------------
 210  * External Bus Controller (EBC) Setup
 211  *----------------------------------------------------------------------*/
 212 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 213 #define CONFIG_SYS_CPLD         0x80000000
 214
 215 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 216 #define CONFIG_SYS_EBC_PB0AP            0x03017300
 217 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0xda000)
 218
 219 /* Memory Bank 2 (CPLD) initialization                                          */
 220 #define CONFIG_SYS_EBC_PB2AP            0x04814500
 221 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_CPLD | 0x18000)
 222
 223 #define CONFIG_SYS_BCSR5_PCI66EN        0x80
 224
 225 #endif  /* __CONFIG_H */