include/configs/xpedite537x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2008 Extreme Engineering Solutions, Inc.
   4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   5  */
   6
   7 /*
   8  * xpedite537x board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_SYS_BOARD_NAME   "XPedite5370"
  17 #define CONFIG_SYS_FORM_3U_VPX  1
  18
  19 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  20 #define CONFIG_PCIE1            1       /* PCIE controller 1 */
  21 #define CONFIG_PCIE2            1       /* PCIE controller 2 */
  22 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  23 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  24 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  25
  26 /*
  27  * Multicore config
  28  */
  29 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  30 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  31
  32 /*
  33  * DDR config
  34  */
  35 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  36 #define CONFIG_DDR_SPD
  37 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  38 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  39 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  40 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  41 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  42 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  43 #define CONFIG_DDR_ECC
  44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  45 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  46 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  47 #define CONFIG_VERY_BIG_RAM
  48
  49 #ifndef __ASSEMBLY__
  50 #include <linux/stringify.h>
  51 extern unsigned long get_board_sys_clk(unsigned long dummy);
  52 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  53 #endif
  54
  55 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  56 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  57
  58 /*
  59  * These can be toggled for performance analysis, otherwise use default.
  60  */
  61 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  62 #define CONFIG_BTB                      /* toggle branch predition */
  63 #define CONFIG_ENABLE_36BIT_PHYS        1
  64
  65 #define CONFIG_SYS_CCSRBAR              0xef000000
  66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  67
  68 /*
  69  * Diagnostics
  70  */
  71 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
  72                                          CONFIG_SYS_POST_I2C)
  73 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
  74 #define I2C_ADDR_IGNORE_LIST            {0x50}
  75
  76 /*
  77  * Memory map
  78  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  79  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
  80  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
  81  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
  82  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
  83  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
  84  * 0xee00_0000  0xee00_ffff     Boot page translation   4K non-cacheable
  85  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
  86  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
  87  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
  88  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
  89  */
  90
  91 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
  92
  93 /*
  94  * NAND flash configuration
  95  */
  96 #define CONFIG_SYS_NAND_BASE            0xef800000
  97 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
  98 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
  99                                          CONFIG_SYS_NAND_BASE2}
 100 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 101 #define CONFIG_NAND_FSL_ELBC
 102
 103 /*
 104  * NOR flash configuration
 105  */
 106 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 107 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 108 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 109 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 110 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 111 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 112 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 113 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 114                                                   {0xf7f40000, 0xc0000} }
 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 116
 117 /*
 118  * Chip select configuration
 119  */
 120 /* NOR Flash 0 on CS0 */
 121 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 122                                  BR_PS_16               | \
 123                                  BR_V)
 124 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 125                                  OR_GPCM_CSNT           | \
 126                                  OR_GPCM_XACS           | \
 127                                  OR_GPCM_ACS_DIV2       | \
 128                                  OR_GPCM_SCY_8          | \
 129                                  OR_GPCM_TRLX           | \
 130                                  OR_GPCM_EHTR           | \
 131                                  OR_GPCM_EAD)
 132
 133 /* NOR Flash 1 on CS1 */
 134 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 135                                  BR_PS_16               | \
 136                                  BR_V)
 137 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 138
 139 /* NAND flash on CS2 */
 140 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 141                                  (2<<BR_DECC_SHIFT)     | \
 142                                  BR_PS_8                | \
 143                                  BR_MS_FCM              | \
 144                                  BR_V)
 145
 146 /* NAND flash on CS2 */
 147 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 148                                  OR_FCM_PGS     | \
 149                                  OR_FCM_CSCT    | \
 150                                  OR_FCM_CST     | \
 151                                  OR_FCM_CHT     | \
 152                                  OR_FCM_SCY_1   | \
 153                                  OR_FCM_TRLX    | \
 154                                  OR_FCM_EHTR)
 155
 156 /* NAND flash on CS3 */
 157 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 158                                  (2<<BR_DECC_SHIFT)     | \
 159                                  BR_PS_8                | \
 160                                  BR_MS_FCM              | \
 161                                  BR_V)
 162 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 163
 164 /*
 165  * Use L1 as initial stack
 166  */
 167 #define CONFIG_SYS_INIT_RAM_LOCK        1
 168 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 169 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 170
 171 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 172 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 173
 174 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 175 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 176
 177 /*
 178  * Serial Port
 179  */
 180 #define CONFIG_SYS_NS16550_SERIAL
 181 #define CONFIG_SYS_NS16550_REG_SIZE     1
 182 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 183 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 184 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 185 #define CONFIG_SYS_BAUDRATE_TABLE       \
 186         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 187 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 188 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 189
 190 /*
 191  * I2C
 192  */
 193 #define CONFIG_SYS_I2C
 194 #define CONFIG_SYS_I2C_FSL
 195 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 196 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 197 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 198 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 199 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 200 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 201 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 202
 203 /* PEX8518 slave I2C interface */
 204 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 205
 206 /* I2C DS1631 temperature sensor */
 207 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 208
 209 /* I2C EEPROM - AT24C128B */
 210 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 213 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 214
 215 /* I2C RTC */
 216 #define CONFIG_RTC_M41T11               1
 217 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 218 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 219
 220 /* GPIO */
 221 #define CONFIG_PCA953X
 222 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 223 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 224 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 225 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 226 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 227
 228 /*
 229  * PU = pulled high, PD = pulled low
 230  * I = input, O = output, IO = input/output
 231  */
 232 /* PCA9557 @ 0x18*/
 233 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 234 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 235 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 236 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 237 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 238 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 239 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2        0x40 /* VID2 of ISL6262 */
 240 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3        0x80 /* VID3 of ISL6262 */
 241
 242 /* PCA9557 @ 0x1c*/
 243 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 244 #define CONFIG_SYS_PCA953X_XMC0_MVMR0           0x02 /* XMC EEPROM write protect */
 245 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 246 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 247 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 248 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 249 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 250 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 251
 252 /* PCA9557 @ 0x1e*/
 253 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 254 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 255 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 256 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 257 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 258 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; tied to VPX P0.GAP */
 259 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
 260
 261 /* PCA9557 @ 0x1f */
 262 #define CONFIG_SYS_PCA953X_GPIO_VPX0            0x01 /* PU */
 263 #define CONFIG_SYS_PCA953X_GPIO_VPX1            0x02 /* PU */
 264 #define CONFIG_SYS_PCA953X_GPIO_VPX2            0x04 /* PU */
 265 #define CONFIG_SYS_PCA953X_GPIO_VPX3            0x08 /* PU */
 266 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL        0x10 /* PD; I2C master source for FRU SEEPROM */
 267
 268 /*
 269  * General PCI
 270  * Memory space is mapped 1-1, but I/O space must start from 0.
 271  */
 272 /* PCIE1 - VPX P1 */
 273 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 274 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 275 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 276 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 277 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 278 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 279
 280 /* PCIE2 - PEX8518 */
 281 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 282 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 283 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 284 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 285 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 286 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 287
 288 /*
 289  * Networking options
 290  */
 291 #define CONFIG_TSEC_TBI
 292 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 293 #define CONFIG_ETHPRIME         "eTSEC2"
 294
 295 /*
 296  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 297  * 1000mbps SGMII link
 298  */
 299 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 300                 TBICR_PHY_RESET \
 301                 | TBICR_FULL_DUPLEX \
 302                 | TBICR_SPEED1_SET \
 303                 )
 304
 305 #define CONFIG_TSEC1            1
 306 #define CONFIG_TSEC1_NAME       "eTSEC1"
 307 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 308 #define TSEC1_PHY_ADDR          1
 309 #define TSEC1_PHYIDX            0
 310 #define CONFIG_HAS_ETH0
 311
 312 #define CONFIG_TSEC2            1
 313 #define CONFIG_TSEC2_NAME       "eTSEC2"
 314 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 315 #define TSEC2_PHY_ADDR          2
 316 #define TSEC2_PHYIDX            0
 317 #define CONFIG_HAS_ETH1
 318
 319 /*
 320  * Miscellaneous configurable options
 321  */
 322 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 323 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 324 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 325
 326 /*
 327  * For booting Linux, the board info and command line data
 328  * have to be in the first 16 MB of memory, since this is
 329  * the maximum mapped by the Linux kernel during initialization.
 330  */
 331 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 332 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 333
 334 /*
 335  * Environment Configuration
 336  */
 337
 338 /*
 339  * Flash memory map:
 340  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 341  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 342  * fff00000 - fff3ffff     Pri FDT (256KB)
 343  * fef00000 - ffefffff     Pri OS image (16MB)
 344  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 345  *
 346  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 347  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 348  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 349  * f6f00000 - f7efffff     Sec OS image (16MB)
 350  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 351  */
 352 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 353 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 354 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 355 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 356 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 357 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 358
 359 #define CONFIG_PROG_UBOOT1                                              \
 360         "$download_cmd $loadaddr $ubootfile; "                          \
 361         "if test $? -eq 0; then "                                       \
 362                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 363                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 364                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 365                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 366                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 367                 "if test $? -ne 0; then "                               \
 368                         "echo PROGRAM FAILED; "                         \
 369                 "else; "                                                \
 370                         "echo PROGRAM SUCCEEDED; "                      \
 371                 "fi; "                                                  \
 372         "else; "                                                        \
 373                 "echo DOWNLOAD FAILED; "                                \
 374         "fi;"
 375
 376 #define CONFIG_PROG_UBOOT2                                              \
 377         "$download_cmd $loadaddr $ubootfile; "                          \
 378         "if test $? -eq 0; then "                                       \
 379                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 380                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 381                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 382                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 383                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 384                 "if test $? -ne 0; then "                               \
 385                         "echo PROGRAM FAILED; "                         \
 386                 "else; "                                                \
 387                         "echo PROGRAM SUCCEEDED; "                      \
 388                 "fi; "                                                  \
 389         "else; "                                                        \
 390                 "echo DOWNLOAD FAILED; "                                \
 391         "fi;"
 392
 393 #define CONFIG_BOOT_OS_NET                                              \
 394         "$download_cmd $osaddr $osfile; "                               \
 395         "if test $? -eq 0; then "                                       \
 396                 "if test -n $fdtaddr; then "                            \
 397                         "$download_cmd $fdtaddr $fdtfile; "             \
 398                         "if test $? -eq 0; then "                       \
 399                                 "bootm $osaddr - $fdtaddr; "            \
 400                         "else; "                                        \
 401                                 "echo FDT DOWNLOAD FAILED; "            \
 402                         "fi; "                                          \
 403                 "else; "                                                \
 404                         "bootm $osaddr; "                               \
 405                 "fi; "                                                  \
 406         "else; "                                                        \
 407                 "echo OS DOWNLOAD FAILED; "                             \
 408         "fi;"
 409
 410 #define CONFIG_PROG_OS1                                                 \
 411         "$download_cmd $osaddr $osfile; "                               \
 412         "if test $? -eq 0; then "                                       \
 413                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 414                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 415                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 416                 "if test $? -ne 0; then "                               \
 417                         "echo OS PROGRAM FAILED; "                      \
 418                 "else; "                                                \
 419                         "echo OS PROGRAM SUCCEEDED; "                   \
 420                 "fi; "                                                  \
 421         "else; "                                                        \
 422                 "echo OS DOWNLOAD FAILED; "                             \
 423         "fi;"
 424
 425 #define CONFIG_PROG_OS2                                                 \
 426         "$download_cmd $osaddr $osfile; "                               \
 427         "if test $? -eq 0; then "                                       \
 428                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 429                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 430                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 431                 "if test $? -ne 0; then "                               \
 432                         "echo OS PROGRAM FAILED; "                      \
 433                 "else; "                                                \
 434                         "echo OS PROGRAM SUCCEEDED; "                   \
 435                 "fi; "                                                  \
 436         "else; "                                                        \
 437                 "echo OS DOWNLOAD FAILED; "                             \
 438         "fi;"
 439
 440 #define CONFIG_PROG_FDT1                                                \
 441         "$download_cmd $fdtaddr $fdtfile; "                             \
 442         "if test $? -eq 0; then "                                       \
 443                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 444                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 445                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 446                 "if test $? -ne 0; then "                               \
 447                         "echo FDT PROGRAM FAILED; "                     \
 448                 "else; "                                                \
 449                         "echo FDT PROGRAM SUCCEEDED; "                  \
 450                 "fi; "                                                  \
 451         "else; "                                                        \
 452                 "echo FDT DOWNLOAD FAILED; "                            \
 453         "fi;"
 454
 455 #define CONFIG_PROG_FDT2                                                \
 456         "$download_cmd $fdtaddr $fdtfile; "                             \
 457         "if test $? -eq 0; then "                                       \
 458                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 459                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 460                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 461                 "if test $? -ne 0; then "                               \
 462                         "echo FDT PROGRAM FAILED; "                     \
 463                 "else; "                                                \
 464                         "echo FDT PROGRAM SUCCEEDED; "                  \
 465                 "fi; "                                                  \
 466         "else; "                                                        \
 467                 "echo FDT DOWNLOAD FAILED; "                            \
 468         "fi;"
 469
 470 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 471         "autoload=yes\0"                                                \
 472         "download_cmd=tftp\0"                                           \
 473         "console_args=console=ttyS0,115200\0"                           \
 474         "root_args=root=/dev/nfs rw\0"                                  \
 475         "misc_args=ip=on\0"                                             \
 476         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 477         "bootfile=/home/user/file\0"                                    \
 478         "osfile=/home/user/board.uImage\0"                              \
 479         "fdtfile=/home/user/board.dtb\0"                                \
 480         "ubootfile=/home/user/u-boot.bin\0"                             \
 481         "fdtaddr=0x1e00000\0"                                           \
 482         "osaddr=0x1000000\0"                                            \
 483         "loadaddr=0x1000000\0"                                          \
 484         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 485         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 486         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 487         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 488         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 489         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 490         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 491         "bootcmd_flash1=run set_bootargs; "                             \
 492                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 493         "bootcmd_flash2=run set_bootargs; "                             \
 494                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 495         "bootcmd=run bootcmd_flash1\0"
 496 #endif  /* __CONFIG_H */