include/configs/xpedite517x.h

   1 /*
   2  * Copyright 2009 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * xpedite517x board configuration file
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_SYS_BOARD_NAME   "XPedite5170"
  18 #define CONFIG_SYS_FORM_3U_VPX  1
  19 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  20 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  21 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  22 #define CONFIG_ALTIVEC          1
  23
  24 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  25 #define CONFIG_PCIE1            1       /* PCIE controller 1 */
  26 #define CONFIG_PCIE2            1       /* PCIE controller 2 */
  27 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  28 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  29 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  30
  31 /*
  32  * DDR config
  33  */
  34 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  35 #define CONFIG_DDR_SPD
  36 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  37 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  38 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  39 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  40 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  41 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  42 #define CONFIG_DDR_ECC
  43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  44 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  45 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  46 #define CONFIG_VERY_BIG_RAM
  47 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  48
  49 /*
  50  * virtual address to be used for temporary mappings.  There
  51  * should be 128k free at this VA.
  52  */
  53 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  54
  55 #ifndef __ASSEMBLY__
  56 extern unsigned long get_board_sys_clk(unsigned long dummy);
  57 #endif
  58
  59 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC86xx */
  60
  61 /*
  62  * L2CR setup
  63  */
  64 #define CONFIG_SYS_L2
  65 #define L2_INIT         0
  66 #define L2_ENABLE       (L2CR_L2E)
  67
  68 /*
  69  * Base addresses -- Note these are effective addresses where the
  70  * actual resources get mapped (not physical addresses)
  71  */
  72 #define CONFIG_SYS_CCSRBAR              0xef000000      /* relocated CCSRBAR */
  73 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR
  74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  75 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  76 #define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
  77
  78 /*
  79  * Diagnostics
  80  */
  81 #define CONFIG_SYS_MEMTEST_START        0x10000000
  82 #define CONFIG_SYS_MEMTEST_END          0x20000000
  83 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY |\
  84                                          CONFIG_SYS_POST_I2C)
  85 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
  86 #define I2C_ADDR_IGNORE_LIST            {0x50}
  87
  88 /*
  89  * Memory map
  90  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  91  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
  92  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
  93  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
  94  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
  95  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
  96  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
  97  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
  98  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
  99  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
 100  */
 101
 102 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_4 | LCRR_EADC_3)
 103
 104 /*
 105  * NAND flash configuration
 106  */
 107 #define CONFIG_SYS_NAND_BASE            0xef800000
 108 #define CONFIG_SYS_NAND_BASE2           0xef840000      /* Unused at this time */
 109 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
 110 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 111 #define CONFIG_NAND_ACTL
 112 #define CONFIG_SYS_NAND_ACTL_ALE        (1 << 14)       /* C_LA14 */
 113 #define CONFIG_SYS_NAND_ACTL_CLE        (1 << 15)       /* C_LA15 */
 114 #define CONFIG_SYS_NAND_ACTL_NCE        0               /* NCE not controlled by ADDR */
 115 #define CONFIG_SYS_NAND_ACTL_DELAY      25
 116 #define CONFIG_JFFS2_NAND
 117
 118 /*
 119  * NOR flash configuration
 120  */
 121 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 122 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 123 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 126 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 127 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 128 #define CONFIG_FLASH_CFI_DRIVER
 129 #define CONFIG_SYS_FLASH_CFI
 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 131 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff00000, 0xc0000}, \
 132                                                   {0xf7f00000, 0xc0000} }
 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 134 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 135
 136 /*
 137  * Chip select configuration
 138  */
 139 /* NOR Flash 0 on CS0 */
 140 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  |\
 141                                  BR_PS_16               |\
 142                                  BR_V)
 143 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            |\
 144                                  OR_GPCM_CSNT           |\
 145                                  OR_GPCM_XACS           |\
 146                                  OR_GPCM_ACS_DIV2       |\
 147                                  OR_GPCM_SCY_8          |\
 148                                  OR_GPCM_TRLX           |\
 149                                  OR_GPCM_EHTR           |\
 150                                  OR_GPCM_EAD)
 151
 152 /* NOR Flash 1 on CS1 */
 153 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 |\
 154                                  BR_PS_16               |\
 155                                  BR_V)
 156 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 157
 158 /* NAND flash on CS2 */
 159 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   |\
 160                                  BR_PS_8                |\
 161                                  BR_V)
 162 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB            |\
 163                                  OR_GPCM_BCTLD          |\
 164                                  OR_GPCM_CSNT           |\
 165                                  OR_GPCM_ACS_DIV4       |\
 166                                  OR_GPCM_SCY_4          |\
 167                                  OR_GPCM_TRLX           |\
 168                                  OR_GPCM_EHTR)
 169
 170 /* Optional NAND flash on CS3 */
 171 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  |\
 172                                  BR_PS_8                |\
 173                                  BR_V)
 174 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 175
 176 /*
 177  * Use L1 as initial stack
 178  */
 179 #define CONFIG_SYS_INIT_RAM_LOCK        1
 180 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 181 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 182
 183 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 184 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 185
 186 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 187 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 188
 189 /*
 190  * Serial Port
 191  */
 192 #define CONFIG_SYS_NS16550_SERIAL
 193 #define CONFIG_SYS_NS16550_REG_SIZE     1
 194 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 195 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 196 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 197 #define CONFIG_SYS_BAUDRATE_TABLE       \
 198         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 199 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 200 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 201
 202 /*
 203  * I2C
 204  */
 205 #define CONFIG_SYS_I2C
 206 #define CONFIG_SYS_I2C_FSL
 207 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 208 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 209 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 210 #define CONFIG_SYS_FSL_I2C2_SPEED       100000
 211 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 212 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 213
 214 /* PEX8518 slave I2C interface */
 215 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 216
 217 /* I2C DS1631 temperature sensor */
 218 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 219
 220 /* I2C EEPROM - AT24C128B */
 221 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 222 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 225
 226 /* I2C RTC */
 227 #define CONFIG_RTC_M41T11               1
 228 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 229 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 230
 231 /* GPIO */
 232 #define CONFIG_PCA953X
 233 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 234 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 235 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 236 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 237 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 238 #define CONFIG_SYS_I2C_PCA9553_ADDR     0x62
 239
 240 /*
 241  * PU = pulled high, PD = pulled low
 242  * I = input, O = output, IO = input/output
 243  */
 244 /* PCA9557 @ 0x18*/
 245 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 246 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 247 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 248 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 249 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 250 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 251
 252 /* PCA9557 @ 0x1c*/
 253 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 254 #define CONFIG_SYS_PCA953X_PLUG_GPIO0           0x02 /* Samtec connector GPIO */
 255 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 256 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 257 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 258 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 259 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 260 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 261
 262 /* PCA9557 @ 0x1e*/
 263 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 264 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 265 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 266 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 267 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 268 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; VPX Geographical address parity */
 269 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; VPX P1 SYSCON */
 270
 271 /* PCA9557 @ 0x1f */
 272 #define CONFIG_SYS_PCA953X_VPX_GPIO0            0x01 /* PU; VPX P15 GPIO */
 273 #define CONFIG_SYS_PCA953X_VPX_GPIO1            0x02 /* PU; VPX P15 GPIO */
 274 #define CONFIG_SYS_PCA953X_VPX_GPIO2            0x04 /* PU; VPX P15 GPIO */
 275 #define CONFIG_SYS_PCA953X_VPX_GPIO3            0x08 /* PU; VPX P15 GPIO */
 276
 277 /*
 278  * General PCI
 279  * Memory space is mapped 1-1, but I/O space must start from 0.
 280  */
 281 /* PCIE1 - PEX8518 */
 282 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 283 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 284 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 285 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 286 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 287 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 288
 289 /* PCIE2 - VPX P1 */
 290 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 291 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 292 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 293 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 294 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 295 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 296
 297 /*
 298  * Networking options
 299  */
 300 #define CONFIG_MII              1       /* MII PHY management */
 301 #define CONFIG_ETHPRIME         "eTSEC1"
 302
 303 #define CONFIG_TSEC1            1
 304 #define CONFIG_TSEC1_NAME       "eTSEC1"
 305 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 306 #define TSEC1_PHY_ADDR          1
 307 #define TSEC1_PHYIDX            0
 308 #define CONFIG_HAS_ETH0
 309
 310 #define CONFIG_TSEC2            1
 311 #define CONFIG_TSEC2_NAME       "eTSEC2"
 312 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 313 #define TSEC2_PHY_ADDR          2
 314 #define TSEC2_PHYIDX            0
 315 #define CONFIG_HAS_ETH1
 316
 317 /*
 318  * BAT mappings
 319  */
 320 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 321 #define CONFIG_SYS_CCSR_DEFAULT_DBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 322                                          BATL_PP_RW                     |\
 323                                          BATL_CACHEINHIBIT              |\
 324                                          BATL_GUARDEDSTORAGE)
 325 #define CONFIG_SYS_CCSR_DEFAULT_DBATU   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 326                                          BATU_BL_1M                     |\
 327                                          BATU_VS                        |\
 328                                          BATU_VP)
 329 #define CONFIG_SYS_CCSR_DEFAULT_IBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 330                                          BATL_PP_RW                     |\
 331                                          BATL_CACHEINHIBIT)
 332 #define CONFIG_SYS_CCSR_DEFAULT_IBATU   CONFIG_SYS_CCSR_DEFAULT_DBATU
 333 #endif
 334
 335 /*
 336  * BAT0         2G      Cacheable, non-guarded
 337  * 0x0000_0000  2G      DDR
 338  */
 339 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 340 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 341 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 342 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 343
 344 /*
 345  * BAT1         1G      Cache-inhibited, guarded
 346  * 0x8000_0000  1G      PCI-Express 1 Memory
 347  */
 348 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 349                                  BATL_PP_RW                     |\
 350                                  BATL_CACHEINHIBIT              |\
 351                                  BATL_GUARDEDSTORAGE)
 352 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 353                                  BATU_BL_1G                     |\
 354                                  BATU_VS                        |\
 355                                  BATU_VP)
 356 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 357                                  BATL_PP_RW                     |\
 358                                  BATL_CACHEINHIBIT)
 359 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 360
 361 /*
 362  * BAT2         512M    Cache-inhibited, guarded
 363  * 0xc000_0000  512M    PCI-Express 2 Memory
 364  */
 365 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 366                                  BATL_PP_RW                     |\
 367                                  BATL_CACHEINHIBIT              |\
 368                                  BATL_GUARDEDSTORAGE)
 369 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 370                                  BATU_BL_512M                   |\
 371                                  BATU_VS                        |\
 372                                  BATU_VP)
 373 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 374                                  BATL_PP_RW                     |\
 375                                  BATL_CACHEINHIBIT)
 376 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 377
 378 /*
 379  * BAT3         1M      Cache-inhibited, guarded
 380  * 0xe000_0000  1M      CCSR
 381  */
 382 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR             |\
 383                                  BATL_PP_RW                     |\
 384                                  BATL_CACHEINHIBIT              |\
 385                                  BATL_GUARDEDSTORAGE)
 386 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR             |\
 387                                  BATU_BL_1M                     |\
 388                                  BATU_VS                        |\
 389                                  BATU_VP)
 390 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR             |\
 391                                  BATL_PP_RW                     |\
 392                                  BATL_CACHEINHIBIT)
 393 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 394
 395 /*
 396  * BAT4         32M     Cache-inhibited, guarded
 397  * 0xe200_0000  16M     PCI-Express 1 I/O
 398  * 0xe300_0000  16M     PCI-Express 2 I/0
 399  */
 400 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 401                                  BATL_PP_RW                     |\
 402                                  BATL_CACHEINHIBIT              |\
 403                                  BATL_GUARDEDSTORAGE)
 404 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 405                                  BATU_BL_32M                    |\
 406                                  BATU_VS                        |\
 407                                  BATU_VP)
 408 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 409                                  BATL_PP_RW                     |\
 410                                  BATL_CACHEINHIBIT)
 411 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 412
 413 /*
 414  * BAT5         128K    Cacheable, non-guarded
 415  * 0xe400_1000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 416  */
 417 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR       |\
 418                                  BATL_PP_RW                     |\
 419                                  BATL_MEMCOHERENCE)
 420 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR       |\
 421                                  BATU_BL_128K                   |\
 422                                  BATU_VS                        |\
 423                                  BATU_VP)
 424 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 425 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 426
 427 /*
 428  * BAT6         256M    Cache-inhibited, guarded
 429  * 0xf000_0000  256M    FLASH
 430  */
 431 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE2         |\
 432                                  BATL_PP_RW                     |\
 433                                  BATL_CACHEINHIBIT              |\
 434                                  BATL_GUARDEDSTORAGE)
 435 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE          |\
 436                                  BATU_BL_256M                   |\
 437                                  BATU_VS                        |\
 438                                  BATU_VP)
 439 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE          |\
 440                                  BATL_PP_RW                     |\
 441                                  BATL_MEMCOHERENCE)
 442 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 443
 444 /* Map the last 1M of flash where we're running from reset */
 445 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 446                                  BATL_PP_RW                     |\
 447                                  BATL_CACHEINHIBIT              |\
 448                                  BATL_GUARDEDSTORAGE)
 449 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE                   |\
 450                                  BATU_BL_1M                     |\
 451                                  BATU_VS                        |\
 452                                  BATU_VP)
 453 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 454                                  BATL_PP_RW                     |\
 455                                  BATL_MEMCOHERENCE)
 456 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 457
 458 /*
 459  * BAT7         64M     Cache-inhibited, guarded
 460  * 0xe800_0000  64K     NAND FLASH
 461  * 0xe804_0000  128K    DUART Registers
 462  */
 463 #define CONFIG_SYS_DBAT7L       (CONFIG_SYS_NAND_BASE           |\
 464                                  BATL_PP_RW                     |\
 465                                  BATL_CACHEINHIBIT              |\
 466                                  BATL_GUARDEDSTORAGE)
 467 #define CONFIG_SYS_DBAT7U       (CONFIG_SYS_NAND_BASE           |\
 468                                  BATU_BL_512K                   |\
 469                                  BATU_VS                        |\
 470                                  BATU_VP)
 471 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_NAND_BASE           |\
 472                                  BATL_PP_RW                     |\
 473                                  BATL_CACHEINHIBIT)
 474 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 475
 476 /*
 477  * Miscellaneous configurable options
 478  */
 479 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 480 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 481 #define CONFIG_PREBOOT                          /* enable preboot variable */
 482 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 483
 484 /*
 485  * For booting Linux, the board info and command line data
 486  * have to be in the first 16 MB of memory, since this is
 487  * the maximum mapped by the Linux kernel during initialization.
 488  */
 489 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 490 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 491
 492 /*
 493  * Environment Configuration
 494  */
 495 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 496 #define CONFIG_ENV_SIZE         0x8000
 497 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 498
 499 /*
 500  * Flash memory map:
 501  * fffc0000 - ffffffff  Pri FDT (256KB)
 502  * fff80000 - fffbffff  Pri U-Boot Environment (256 KB)
 503  * fff00000 - fff7ffff  Pri U-Boot (512 KB)
 504  * fef00000 - ffefffff  Pri OS image (16MB)
 505  * f8000000 - feefffff  Pri OS Use/Filesystem (111MB)
 506  *
 507  * f7fc0000 - f7ffffff  Sec FDT (256KB)
 508  * f7f80000 - f7fbffff  Sec U-Boot Environment (256 KB)
 509  * f7f00000 - f7f7ffff  Sec U-Boot (512 KB)
 510  * f6f00000 - f7efffff  Sec OS image (16MB)
 511  * f0000000 - f6efffff  Sec OS Use/Filesystem (111MB)
 512  */
 513 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff00000)
 514 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f00000)
 515 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfffc0000)
 516 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7fc0000)
 517 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 518 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 519
 520 #define CONFIG_PROG_UBOOT1                                              \
 521         "$download_cmd $loadaddr $ubootfile; "                          \
 522         "if test $? -eq 0; then "                                       \
 523                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 524                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 525                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 526                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 527                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 528                 "if test $? -ne 0; then "                               \
 529                         "echo PROGRAM FAILED; "                         \
 530                 "else; "                                                \
 531                         "echo PROGRAM SUCCEEDED; "                      \
 532                 "fi; "                                                  \
 533         "else; "                                                        \
 534                 "echo DOWNLOAD FAILED; "                                \
 535         "fi;"
 536
 537 #define CONFIG_PROG_UBOOT2                                              \
 538         "$download_cmd $loadaddr $ubootfile; "                          \
 539         "if test $? -eq 0; then "                                       \
 540                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 541                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 542                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 543                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 544                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 545                 "if test $? -ne 0; then "                               \
 546                         "echo PROGRAM FAILED; "                         \
 547                 "else; "                                                \
 548                         "echo PROGRAM SUCCEEDED; "                      \
 549                 "fi; "                                                  \
 550         "else; "                                                        \
 551                 "echo DOWNLOAD FAILED; "                                \
 552         "fi;"
 553
 554 #define CONFIG_BOOT_OS_NET                                              \
 555         "$download_cmd $osaddr $osfile; "                               \
 556         "if test $? -eq 0; then "                                       \
 557                 "if test -n $fdtaddr; then "                            \
 558                         "$download_cmd $fdtaddr $fdtfile; "             \
 559                         "if test $? -eq 0; then "                       \
 560                                 "bootm $osaddr - $fdtaddr; "            \
 561                         "else; "                                        \
 562                                 "echo FDT DOWNLOAD FAILED; "            \
 563                         "fi; "                                          \
 564                 "else; "                                                \
 565                         "bootm $osaddr; "                               \
 566                 "fi; "                                                  \
 567         "else; "                                                        \
 568                 "echo OS DOWNLOAD FAILED; "                             \
 569         "fi;"
 570
 571 #define CONFIG_PROG_OS1                                                 \
 572         "$download_cmd $osaddr $osfile; "                               \
 573         "if test $? -eq 0; then "                                       \
 574                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 575                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 576                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 577                 "if test $? -ne 0; then "                               \
 578                         "echo OS PROGRAM FAILED; "                      \
 579                 "else; "                                                \
 580                         "echo OS PROGRAM SUCCEEDED; "                   \
 581                 "fi; "                                                  \
 582         "else; "                                                        \
 583                 "echo OS DOWNLOAD FAILED; "                             \
 584         "fi;"
 585
 586 #define CONFIG_PROG_OS2                                                 \
 587         "$download_cmd $osaddr $osfile; "                               \
 588         "if test $? -eq 0; then "                                       \
 589                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 590                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 591                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 592                 "if test $? -ne 0; then "                               \
 593                         "echo OS PROGRAM FAILED; "                      \
 594                 "else; "                                                \
 595                         "echo OS PROGRAM SUCCEEDED; "                   \
 596                 "fi; "                                                  \
 597         "else; "                                                        \
 598                 "echo OS DOWNLOAD FAILED; "                             \
 599         "fi;"
 600
 601 #define CONFIG_PROG_FDT1                                                \
 602         "$download_cmd $fdtaddr $fdtfile; "                             \
 603         "if test $? -eq 0; then "                                       \
 604                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 605                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 606                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 607                 "if test $? -ne 0; then "                               \
 608                         "echo FDT PROGRAM FAILED; "                     \
 609                 "else; "                                                \
 610                         "echo FDT PROGRAM SUCCEEDED; "                  \
 611                 "fi; "                                                  \
 612         "else; "                                                        \
 613                 "echo FDT DOWNLOAD FAILED; "                            \
 614         "fi;"
 615
 616 #define CONFIG_PROG_FDT2                                                \
 617         "$download_cmd $fdtaddr $fdtfile; "                             \
 618         "if test $? -eq 0; then "                                       \
 619                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 620                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 621                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 622                 "if test $? -ne 0; then "                               \
 623                         "echo FDT PROGRAM FAILED; "                     \
 624                 "else; "                                                \
 625                         "echo FDT PROGRAM SUCCEEDED; "                  \
 626                 "fi; "                                                  \
 627         "else; "                                                        \
 628                 "echo FDT DOWNLOAD FAILED; "                            \
 629         "fi;"
 630
 631 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 632         "autoload=yes\0"                                                \
 633         "download_cmd=tftp\0"                                           \
 634         "console_args=console=ttyS0,115200\0"                           \
 635         "root_args=root=/dev/nfs rw\0"                                  \
 636         "misc_args=ip=on\0"                                             \
 637         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 638         "bootfile=/home/user/file\0"                                    \
 639         "osfile=/home/user/board.uImage\0"                              \
 640         "fdtfile=/home/user/board.dtb\0"                                \
 641         "ubootfile=/home/user/u-boot.bin\0"                             \
 642         "fdtaddr=0x1e00000\0"                                           \
 643         "osaddr=0x1000000\0"                                            \
 644         "loadaddr=0x1000000\0"                                          \
 645         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 646         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 647         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 648         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 649         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 650         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 651         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 652         "bootcmd_flash1=run set_bootargs; "                             \
 653                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 654         "bootcmd_flash2=run set_bootargs; "                             \
 655                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 656         "bootcmd=run bootcmd_flash1\0"
 657 #endif  /* __CONFIG_H */