include/configs/xpedite517x.h

   1 /*
   2  * Copyright 2009 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * xpedite517x board configuration file
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  18 #define CONFIG_XPEDITE5140      1       /* MPC8641HPCN board specific */
  19 #define CONFIG_SYS_BOARD_NAME   "XPedite5170"
  20 #define CONFIG_SYS_FORM_3U_VPX  1
  21 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  22 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_pre_init */
  23 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  24 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  25 #define CONFIG_ALTIVEC          1
  26
  27 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  28
  29 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  30 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play */
  31 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  32 #define CONFIG_PCIE1            1       /* PCIE controller 1 */
  33 #define CONFIG_PCIE2            1       /* PCIE controller 2 */
  34 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  35 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  36 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  37 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  38
  39 /*
  40  * DDR config
  41  */
  42 #define CONFIG_SYS_FSL_DDR2
  43 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  44 #define CONFIG_DDR_SPD
  45 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  46 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  47 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  48 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  49 #define CONFIG_NUM_DDR_CONTROLLERS      2
  50 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  51 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  52 #define CONFIG_DDR_ECC
  53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  54 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  55 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  56 #define CONFIG_VERY_BIG_RAM
  57 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  58
  59 /*
  60  * virtual address to be used for temporary mappings.  There
  61  * should be 128k free at this VA.
  62  */
  63 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  64
  65 #ifndef __ASSEMBLY__
  66 extern unsigned long get_board_sys_clk(unsigned long dummy);
  67 #endif
  68
  69 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC86xx */
  70
  71 /*
  72  * L2CR setup
  73  */
  74 #define CONFIG_SYS_L2
  75 #define L2_INIT         0
  76 #define L2_ENABLE       (L2CR_L2E)
  77
  78 /*
  79  * Base addresses -- Note these are effective addresses where the
  80  * actual resources get mapped (not physical addresses)
  81  */
  82 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  83 #define CONFIG_SYS_CCSRBAR              0xef000000      /* relocated CCSRBAR */
  84 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR
  85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  86 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  87 #define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
  88
  89 /*
  90  * Diagnostics
  91  */
  92 #define CONFIG_SYS_ALT_MEMTEST
  93 #define CONFIG_SYS_MEMTEST_START        0x10000000
  94 #define CONFIG_SYS_MEMTEST_END          0x20000000
  95 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY |\
  96                                          CONFIG_SYS_POST_I2C)
  97 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_DS1621_ADDR,    \
  98                                          CONFIG_SYS_I2C_DS4510_ADDR,    \
  99                                          CONFIG_SYS_I2C_EEPROM_ADDR,    \
 100                                          CONFIG_SYS_I2C_LM90_ADDR,      \
 101                                          CONFIG_SYS_I2C_PCA9553_ADDR,   \
 102                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
 103                                          CONFIG_SYS_I2C_PCA953X_ADDR1,  \
 104                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
 105                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
 106                                          CONFIG_SYS_I2C_PEX8518_ADDR,   \
 107                                          CONFIG_SYS_I2C_RTC_ADDR}
 108 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
 109 #define I2C_ADDR_IGNORE_LIST            {0x50}
 110
 111 /*
 112  * Memory map
 113  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 114  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
 115  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
 116  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
 117  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
 118  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
 119  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
 120  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
 121  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
 122  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
 123  */
 124
 125 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_4 | LCRR_EADC_3)
 126
 127 /*
 128  * NAND flash configuration
 129  */
 130 #define CONFIG_SYS_NAND_BASE            0xef800000
 131 #define CONFIG_SYS_NAND_BASE2           0xef840000      /* Unused at this time */
 132 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
 133 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 134 #define CONFIG_NAND_ACTL
 135 #define CONFIG_SYS_NAND_ACTL_ALE        (1 << 14)       /* C_LA14 */
 136 #define CONFIG_SYS_NAND_ACTL_CLE        (1 << 15)       /* C_LA15 */
 137 #define CONFIG_SYS_NAND_ACTL_NCE        0               /* NCE not controlled by ADDR */
 138 #define CONFIG_SYS_NAND_ACTL_DELAY      25
 139 #define CONFIG_JFFS2_NAND
 140
 141 /*
 142  * NOR flash configuration
 143  */
 144 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 145 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 146 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 147 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 148 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 149 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 150 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 151 #define CONFIG_FLASH_CFI_DRIVER
 152 #define CONFIG_SYS_FLASH_CFI
 153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 154 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff00000, 0xc0000}, \
 155                                                   {0xf7f00000, 0xc0000} }
 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 157 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 158
 159 /*
 160  * Chip select configuration
 161  */
 162 /* NOR Flash 0 on CS0 */
 163 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  |\
 164                                  BR_PS_16               |\
 165                                  BR_V)
 166 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            |\
 167                                  OR_GPCM_CSNT           |\
 168                                  OR_GPCM_XACS           |\
 169                                  OR_GPCM_ACS_DIV2       |\
 170                                  OR_GPCM_SCY_8          |\
 171                                  OR_GPCM_TRLX           |\
 172                                  OR_GPCM_EHTR           |\
 173                                  OR_GPCM_EAD)
 174
 175 /* NOR Flash 1 on CS1 */
 176 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 |\
 177                                  BR_PS_16               |\
 178                                  BR_V)
 179 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 180
 181 /* NAND flash on CS2 */
 182 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   |\
 183                                  BR_PS_8                |\
 184                                  BR_V)
 185 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB            |\
 186                                  OR_GPCM_BCTLD          |\
 187                                  OR_GPCM_CSNT           |\
 188                                  OR_GPCM_ACS_DIV4       |\
 189                                  OR_GPCM_SCY_4          |\
 190                                  OR_GPCM_TRLX           |\
 191                                  OR_GPCM_EHTR)
 192
 193 /* Optional NAND flash on CS3 */
 194 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  |\
 195                                  BR_PS_8                |\
 196                                  BR_V)
 197 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 198
 199 /*
 200  * Use L1 as initial stack
 201  */
 202 #define CONFIG_SYS_INIT_RAM_LOCK        1
 203 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 204 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 205
 206 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 207 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 208
 209 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 210 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 211
 212 /*
 213  * Serial Port
 214  */
 215 #define CONFIG_CONS_INDEX               1
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE     1
 218 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 221 #define CONFIG_SYS_BAUDRATE_TABLE       \
 222         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 223 #define CONFIG_BAUDRATE                 115200
 224 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 225 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 226
 227 /*
 228  * I2C
 229  */
 230 #define CONFIG_SYS_I2C
 231 #define CONFIG_SYS_I2C_FSL
 232 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 233 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 234 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 235 #define CONFIG_SYS_FSL_I2C2_SPEED       100000
 236 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 237 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 238
 239 /* PEX8518 slave I2C interface */
 240 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 241
 242 /* I2C DS1631 temperature sensor */
 243 #define CONFIG_SYS_I2C_DS1621_ADDR      0x48
 244 #define CONFIG_DTT_DS1621
 245 #define CONFIG_DTT_SENSORS              { 0 }
 246 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 247
 248 /* I2C EEPROM - AT24C128B */
 249 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 253
 254 /* I2C RTC */
 255 #define CONFIG_RTC_M41T11               1
 256 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 257 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 258
 259 /* GPIO/EEPROM/SRAM */
 260 #define CONFIG_DS4510
 261 #define CONFIG_SYS_I2C_DS4510_ADDR      0x51
 262
 263 /* GPIO */
 264 #define CONFIG_PCA953X
 265 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 266 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 267 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 268 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 269 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 270 #define CONFIG_SYS_I2C_PCA9553_ADDR     0x62
 271
 272 /*
 273  * PU = pulled high, PD = pulled low
 274  * I = input, O = output, IO = input/output
 275  */
 276 /* PCA9557 @ 0x18*/
 277 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 278 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 279 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 280 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 281 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 282 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 283
 284 /* PCA9557 @ 0x1c*/
 285 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 286 #define CONFIG_SYS_PCA953X_PLUG_GPIO0           0x02 /* Samtec connector GPIO */
 287 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 288 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 289 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 290 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 291 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 292 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 293
 294 /* PCA9557 @ 0x1e*/
 295 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 296 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 297 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 298 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 299 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 300 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; VPX Geographical address parity */
 301 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; VPX P1 SYSCON */
 302
 303 /* PCA9557 @ 0x1f */
 304 #define CONFIG_SYS_PCA953X_VPX_GPIO0            0x01 /* PU; VPX P15 GPIO */
 305 #define CONFIG_SYS_PCA953X_VPX_GPIO1            0x02 /* PU; VPX P15 GPIO */
 306 #define CONFIG_SYS_PCA953X_VPX_GPIO2            0x04 /* PU; VPX P15 GPIO */
 307 #define CONFIG_SYS_PCA953X_VPX_GPIO3            0x08 /* PU; VPX P15 GPIO */
 308
 309 /*
 310  * General PCI
 311  * Memory space is mapped 1-1, but I/O space must start from 0.
 312  */
 313 /* PCIE1 - PEX8518 */
 314 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 315 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 316 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 317 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 318 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 319 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 320
 321 /* PCIE2 - VPX P1 */
 322 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 323 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 324 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 325 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 326 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 327 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 328
 329 /*
 330  * Networking options
 331  */
 332 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 333 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 334 #define CONFIG_MII              1       /* MII PHY management */
 335 #define CONFIG_ETHPRIME         "eTSEC1"
 336
 337 #define CONFIG_TSEC1            1
 338 #define CONFIG_TSEC1_NAME       "eTSEC1"
 339 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 340 #define TSEC1_PHY_ADDR          1
 341 #define TSEC1_PHYIDX            0
 342 #define CONFIG_HAS_ETH0
 343
 344 #define CONFIG_TSEC2            1
 345 #define CONFIG_TSEC2_NAME       "eTSEC2"
 346 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 347 #define TSEC2_PHY_ADDR          2
 348 #define TSEC2_PHYIDX            0
 349 #define CONFIG_HAS_ETH1
 350
 351 /*
 352  * BAT mappings
 353  */
 354 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 355 #define CONFIG_SYS_CCSR_DEFAULT_DBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 356                                          BATL_PP_RW                     |\
 357                                          BATL_CACHEINHIBIT              |\
 358                                          BATL_GUARDEDSTORAGE)
 359 #define CONFIG_SYS_CCSR_DEFAULT_DBATU   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 360                                          BATU_BL_1M                     |\
 361                                          BATU_VS                        |\
 362                                          BATU_VP)
 363 #define CONFIG_SYS_CCSR_DEFAULT_IBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 364                                          BATL_PP_RW                     |\
 365                                          BATL_CACHEINHIBIT)
 366 #define CONFIG_SYS_CCSR_DEFAULT_IBATU   CONFIG_SYS_CCSR_DEFAULT_DBATU
 367 #endif
 368
 369 /*
 370  * BAT0         2G      Cacheable, non-guarded
 371  * 0x0000_0000  2G      DDR
 372  */
 373 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 374 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 375 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 376 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 377
 378 /*
 379  * BAT1         1G      Cache-inhibited, guarded
 380  * 0x8000_0000  1G      PCI-Express 1 Memory
 381  */
 382 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 383                                  BATL_PP_RW                     |\
 384                                  BATL_CACHEINHIBIT              |\
 385                                  BATL_GUARDEDSTORAGE)
 386 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 387                                  BATU_BL_1G                     |\
 388                                  BATU_VS                        |\
 389                                  BATU_VP)
 390 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 391                                  BATL_PP_RW                     |\
 392                                  BATL_CACHEINHIBIT)
 393 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 394
 395 /*
 396  * BAT2         512M    Cache-inhibited, guarded
 397  * 0xc000_0000  512M    PCI-Express 2 Memory
 398  */
 399 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 400                                  BATL_PP_RW                     |\
 401                                  BATL_CACHEINHIBIT              |\
 402                                  BATL_GUARDEDSTORAGE)
 403 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 404                                  BATU_BL_512M                   |\
 405                                  BATU_VS                        |\
 406                                  BATU_VP)
 407 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 408                                  BATL_PP_RW                     |\
 409                                  BATL_CACHEINHIBIT)
 410 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 411
 412 /*
 413  * BAT3         1M      Cache-inhibited, guarded
 414  * 0xe000_0000  1M      CCSR
 415  */
 416 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR             |\
 417                                  BATL_PP_RW                     |\
 418                                  BATL_CACHEINHIBIT              |\
 419                                  BATL_GUARDEDSTORAGE)
 420 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR             |\
 421                                  BATU_BL_1M                     |\
 422                                  BATU_VS                        |\
 423                                  BATU_VP)
 424 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR             |\
 425                                  BATL_PP_RW                     |\
 426                                  BATL_CACHEINHIBIT)
 427 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 428
 429 /*
 430  * BAT4         32M     Cache-inhibited, guarded
 431  * 0xe200_0000  16M     PCI-Express 1 I/O
 432  * 0xe300_0000  16M     PCI-Express 2 I/0
 433  */
 434 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 435                                  BATL_PP_RW                     |\
 436                                  BATL_CACHEINHIBIT              |\
 437                                  BATL_GUARDEDSTORAGE)
 438 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 439                                  BATU_BL_32M                    |\
 440                                  BATU_VS                        |\
 441                                  BATU_VP)
 442 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 443                                  BATL_PP_RW                     |\
 444                                  BATL_CACHEINHIBIT)
 445 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 446
 447 /*
 448  * BAT5         128K    Cacheable, non-guarded
 449  * 0xe400_1000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 450  */
 451 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR       |\
 452                                  BATL_PP_RW                     |\
 453                                  BATL_MEMCOHERENCE)
 454 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR       |\
 455                                  BATU_BL_128K                   |\
 456                                  BATU_VS                        |\
 457                                  BATU_VP)
 458 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 459 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 460
 461 /*
 462  * BAT6         256M    Cache-inhibited, guarded
 463  * 0xf000_0000  256M    FLASH
 464  */
 465 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE2         |\
 466                                  BATL_PP_RW                     |\
 467                                  BATL_CACHEINHIBIT              |\
 468                                  BATL_GUARDEDSTORAGE)
 469 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE          |\
 470                                  BATU_BL_256M                   |\
 471                                  BATU_VS                        |\
 472                                  BATU_VP)
 473 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE          |\
 474                                  BATL_PP_RW                     |\
 475                                  BATL_MEMCOHERENCE)
 476 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 477
 478 /* Map the last 1M of flash where we're running from reset */
 479 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 480                                  BATL_PP_RW                     |\
 481                                  BATL_CACHEINHIBIT              |\
 482                                  BATL_GUARDEDSTORAGE)
 483 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE                   |\
 484                                  BATU_BL_1M                     |\
 485                                  BATU_VS                        |\
 486                                  BATU_VP)
 487 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 488                                  BATL_PP_RW                     |\
 489                                  BATL_MEMCOHERENCE)
 490 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 491
 492 /*
 493  * BAT7         64M     Cache-inhibited, guarded
 494  * 0xe800_0000  64K     NAND FLASH
 495  * 0xe804_0000  128K    DUART Registers
 496  */
 497 #define CONFIG_SYS_DBAT7L       (CONFIG_SYS_NAND_BASE           |\
 498                                  BATL_PP_RW                     |\
 499                                  BATL_CACHEINHIBIT              |\
 500                                  BATL_GUARDEDSTORAGE)
 501 #define CONFIG_SYS_DBAT7U       (CONFIG_SYS_NAND_BASE           |\
 502                                  BATU_BL_512K                   |\
 503                                  BATU_VS                        |\
 504                                  BATU_VP)
 505 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_NAND_BASE           |\
 506                                  BATL_PP_RW                     |\
 507                                  BATL_CACHEINHIBIT)
 508 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 509
 510 /*
 511  * Command configuration.
 512  */
 513 #define CONFIG_CMD_DATE
 514 #define CONFIG_CMD_DS4510
 515 #define CONFIG_CMD_DS4510_INFO
 516 #define CONFIG_CMD_DTT
 517 #define CONFIG_CMD_EEPROM
 518 #define CONFIG_CMD_IRQ
 519 #define CONFIG_CMD_JFFS2
 520 #define CONFIG_CMD_NAND
 521 #define CONFIG_CMD_PCA953X
 522 #define CONFIG_CMD_PCA953X_INFO
 523 #define CONFIG_CMD_PCI
 524 #define CONFIG_CMD_PCI_ENUM
 525 #define CONFIG_CMD_REGINFO
 526
 527 /*
 528  * Miscellaneous configurable options
 529  */
 530 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 531 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 532 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 533 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 534 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 535 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 536 #define CONFIG_CMDLINE_EDITING  1               /* Command-line editing */
 537 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 538 #define CONFIG_PANIC_HANG                       /* do not reset board on panic */
 539 #define CONFIG_PREBOOT                          /* enable preboot variable */
 540 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 541
 542 /*
 543  * For booting Linux, the board info and command line data
 544  * have to be in the first 16 MB of memory, since this is
 545  * the maximum mapped by the Linux kernel during initialization.
 546  */
 547 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 548 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 549
 550 /*
 551  * Environment Configuration
 552  */
 553 #define CONFIG_ENV_IS_IN_FLASH  1
 554 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 555 #define CONFIG_ENV_SIZE         0x8000
 556 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 557
 558 /*
 559  * Flash memory map:
 560  * fffc0000 - ffffffff  Pri FDT (256KB)
 561  * fff80000 - fffbffff  Pri U-Boot Environment (256 KB)
 562  * fff00000 - fff7ffff  Pri U-Boot (512 KB)
 563  * fef00000 - ffefffff  Pri OS image (16MB)
 564  * f8000000 - feefffff  Pri OS Use/Filesystem (111MB)
 565  *
 566  * f7fc0000 - f7ffffff  Sec FDT (256KB)
 567  * f7f80000 - f7fbffff  Sec U-Boot Environment (256 KB)
 568  * f7f00000 - f7f7ffff  Sec U-Boot (512 KB)
 569  * f6f00000 - f7efffff  Sec OS image (16MB)
 570  * f0000000 - f6efffff  Sec OS Use/Filesystem (111MB)
 571  */
 572 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff00000)
 573 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f00000)
 574 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfffc0000)
 575 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7fc0000)
 576 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 577 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 578
 579 #define CONFIG_PROG_UBOOT1                                              \
 580         "$download_cmd $loadaddr $ubootfile; "                          \
 581         "if test $? -eq 0; then "                                       \
 582                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 583                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 584                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 585                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 586                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 587                 "if test $? -ne 0; then "                               \
 588                         "echo PROGRAM FAILED; "                         \
 589                 "else; "                                                \
 590                         "echo PROGRAM SUCCEEDED; "                      \
 591                 "fi; "                                                  \
 592         "else; "                                                        \
 593                 "echo DOWNLOAD FAILED; "                                \
 594         "fi;"
 595
 596 #define CONFIG_PROG_UBOOT2                                              \
 597         "$download_cmd $loadaddr $ubootfile; "                          \
 598         "if test $? -eq 0; then "                                       \
 599                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 600                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 601                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 602                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 603                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 604                 "if test $? -ne 0; then "                               \
 605                         "echo PROGRAM FAILED; "                         \
 606                 "else; "                                                \
 607                         "echo PROGRAM SUCCEEDED; "                      \
 608                 "fi; "                                                  \
 609         "else; "                                                        \
 610                 "echo DOWNLOAD FAILED; "                                \
 611         "fi;"
 612
 613 #define CONFIG_BOOT_OS_NET                                              \
 614         "$download_cmd $osaddr $osfile; "                               \
 615         "if test $? -eq 0; then "                                       \
 616                 "if test -n $fdtaddr; then "                            \
 617                         "$download_cmd $fdtaddr $fdtfile; "             \
 618                         "if test $? -eq 0; then "                       \
 619                                 "bootm $osaddr - $fdtaddr; "            \
 620                         "else; "                                        \
 621                                 "echo FDT DOWNLOAD FAILED; "            \
 622                         "fi; "                                          \
 623                 "else; "                                                \
 624                         "bootm $osaddr; "                               \
 625                 "fi; "                                                  \
 626         "else; "                                                        \
 627                 "echo OS DOWNLOAD FAILED; "                             \
 628         "fi;"
 629
 630 #define CONFIG_PROG_OS1                                                 \
 631         "$download_cmd $osaddr $osfile; "                               \
 632         "if test $? -eq 0; then "                                       \
 633                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 634                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 635                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 636                 "if test $? -ne 0; then "                               \
 637                         "echo OS PROGRAM FAILED; "                      \
 638                 "else; "                                                \
 639                         "echo OS PROGRAM SUCCEEDED; "                   \
 640                 "fi; "                                                  \
 641         "else; "                                                        \
 642                 "echo OS DOWNLOAD FAILED; "                             \
 643         "fi;"
 644
 645 #define CONFIG_PROG_OS2                                                 \
 646         "$download_cmd $osaddr $osfile; "                               \
 647         "if test $? -eq 0; then "                                       \
 648                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 649                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 650                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 651                 "if test $? -ne 0; then "                               \
 652                         "echo OS PROGRAM FAILED; "                      \
 653                 "else; "                                                \
 654                         "echo OS PROGRAM SUCCEEDED; "                   \
 655                 "fi; "                                                  \
 656         "else; "                                                        \
 657                 "echo OS DOWNLOAD FAILED; "                             \
 658         "fi;"
 659
 660 #define CONFIG_PROG_FDT1                                                \
 661         "$download_cmd $fdtaddr $fdtfile; "                             \
 662         "if test $? -eq 0; then "                                       \
 663                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 664                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 665                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 666                 "if test $? -ne 0; then "                               \
 667                         "echo FDT PROGRAM FAILED; "                     \
 668                 "else; "                                                \
 669                         "echo FDT PROGRAM SUCCEEDED; "                  \
 670                 "fi; "                                                  \
 671         "else; "                                                        \
 672                 "echo FDT DOWNLOAD FAILED; "                            \
 673         "fi;"
 674
 675 #define CONFIG_PROG_FDT2                                                \
 676         "$download_cmd $fdtaddr $fdtfile; "                             \
 677         "if test $? -eq 0; then "                                       \
 678                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 679                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 680                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 681                 "if test $? -ne 0; then "                               \
 682                         "echo FDT PROGRAM FAILED; "                     \
 683                 "else; "                                                \
 684                         "echo FDT PROGRAM SUCCEEDED; "                  \
 685                 "fi; "                                                  \
 686         "else; "                                                        \
 687                 "echo FDT DOWNLOAD FAILED; "                            \
 688         "fi;"
 689
 690 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 691         "autoload=yes\0"                                                \
 692         "download_cmd=tftp\0"                                           \
 693         "console_args=console=ttyS0,115200\0"                           \
 694         "root_args=root=/dev/nfs rw\0"                                  \
 695         "misc_args=ip=on\0"                                             \
 696         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 697         "bootfile=/home/user/file\0"                                    \
 698         "osfile=/home/user/board.uImage\0"                              \
 699         "fdtfile=/home/user/board.dtb\0"                                \
 700         "ubootfile=/home/user/u-boot.bin\0"                             \
 701         "fdtaddr=0x1e00000\0"                                           \
 702         "osaddr=0x1000000\0"                                            \
 703         "loadaddr=0x1000000\0"                                          \
 704         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 705         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 706         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 707         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 708         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 709         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 710         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 711         "bootcmd_flash1=run set_bootargs; "                             \
 712                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 713         "bootcmd_flash2=run set_bootargs; "                             \
 714                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 715         "bootcmd=run bootcmd_flash1\0"
 716 #endif  /* __CONFIG_H */