include/configs/xpedite517x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009 Extreme Engineering Solutions, Inc.
   4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   5  */
   6
   7 /*
   8  * xpedite517x board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_SYS_BOARD_NAME   "XPedite5170"
  17 #define CONFIG_SYS_FORM_3U_VPX  1
  18 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  19 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  20 #define CONFIG_ALTIVEC          1
  21
  22 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  23 #define CONFIG_PCIE1            1       /* PCIE controller 1 */
  24 #define CONFIG_PCIE2            1       /* PCIE controller 2 */
  25 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  26 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  27 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  28
  29 /*
  30  * DDR config
  31  */
  32 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  33 #define CONFIG_DDR_SPD
  34 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  35 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  36 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  37 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  38 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  39 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  40 #define CONFIG_DDR_ECC
  41 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  42 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  43 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  44 #define CONFIG_VERY_BIG_RAM
  45 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  46
  47 /*
  48  * virtual address to be used for temporary mappings.  There
  49  * should be 128k free at this VA.
  50  */
  51 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  52
  53 #ifndef __ASSEMBLY__
  54 extern unsigned long get_board_sys_clk(unsigned long dummy);
  55 #endif
  56
  57 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC86xx */
  58
  59 /*
  60  * L2CR setup
  61  */
  62 #define CONFIG_SYS_L2
  63 #define L2_INIT         0
  64 #define L2_ENABLE       (L2CR_L2E)
  65
  66 /*
  67  * Base addresses -- Note these are effective addresses where the
  68  * actual resources get mapped (not physical addresses)
  69  */
  70 #define CONFIG_SYS_CCSRBAR              0xef000000      /* relocated CCSRBAR */
  71 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR
  72 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  73 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  74 #define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
  75
  76 /*
  77  * Diagnostics
  78  */
  79 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY |\
  80                                          CONFIG_SYS_POST_I2C)
  81 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
  82 #define I2C_ADDR_IGNORE_LIST            {0x50}
  83
  84 /*
  85  * Memory map
  86  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  87  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
  88  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
  89  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
  90  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
  91  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
  92  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
  93  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
  94  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
  95  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
  96  */
  97
  98 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_4 | LCRR_EADC_3)
  99
 100 /*
 101  * NAND flash configuration
 102  */
 103 #define CONFIG_SYS_NAND_BASE            0xef800000
 104 #define CONFIG_SYS_NAND_BASE2           0xef840000      /* Unused at this time */
 105 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
 106 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 107 #define CONFIG_NAND_ACTL
 108 #define CONFIG_SYS_NAND_ACTL_ALE        (1 << 14)       /* C_LA14 */
 109 #define CONFIG_SYS_NAND_ACTL_CLE        (1 << 15)       /* C_LA15 */
 110 #define CONFIG_SYS_NAND_ACTL_NCE        0               /* NCE not controlled by ADDR */
 111 #define CONFIG_SYS_NAND_ACTL_DELAY      25
 112 #define CONFIG_JFFS2_NAND
 113
 114 /*
 115  * NOR flash configuration
 116  */
 117 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 118 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 119 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 120 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 121 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 122 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 123 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 124 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff00000, 0xc0000}, \
 125                                                   {0xf7f00000, 0xc0000} }
 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 127 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 128
 129 /*
 130  * Chip select configuration
 131  */
 132 /* NOR Flash 0 on CS0 */
 133 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  |\
 134                                  BR_PS_16               |\
 135                                  BR_V)
 136 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            |\
 137                                  OR_GPCM_CSNT           |\
 138                                  OR_GPCM_XACS           |\
 139                                  OR_GPCM_ACS_DIV2       |\
 140                                  OR_GPCM_SCY_8          |\
 141                                  OR_GPCM_TRLX           |\
 142                                  OR_GPCM_EHTR           |\
 143                                  OR_GPCM_EAD)
 144
 145 /* NOR Flash 1 on CS1 */
 146 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 |\
 147                                  BR_PS_16               |\
 148                                  BR_V)
 149 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 150
 151 /* NAND flash on CS2 */
 152 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   |\
 153                                  BR_PS_8                |\
 154                                  BR_V)
 155 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB            |\
 156                                  OR_GPCM_BCTLD          |\
 157                                  OR_GPCM_CSNT           |\
 158                                  OR_GPCM_ACS_DIV4       |\
 159                                  OR_GPCM_SCY_4          |\
 160                                  OR_GPCM_TRLX           |\
 161                                  OR_GPCM_EHTR)
 162
 163 /* Optional NAND flash on CS3 */
 164 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  |\
 165                                  BR_PS_8                |\
 166                                  BR_V)
 167 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 168
 169 /*
 170  * Use L1 as initial stack
 171  */
 172 #define CONFIG_SYS_INIT_RAM_LOCK        1
 173 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 174 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 175
 176 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 177 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 178
 179 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 180 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 181
 182 /*
 183  * Serial Port
 184  */
 185 #define CONFIG_SYS_NS16550_SERIAL
 186 #define CONFIG_SYS_NS16550_REG_SIZE     1
 187 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 188 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 189 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 190 #define CONFIG_SYS_BAUDRATE_TABLE       \
 191         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 192 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 193 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 194
 195 /*
 196  * I2C
 197  */
 198 #define CONFIG_SYS_I2C
 199 #define CONFIG_SYS_I2C_FSL
 200 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 201 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 202 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 203 #define CONFIG_SYS_FSL_I2C2_SPEED       100000
 204 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 205 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 206
 207 /* PEX8518 slave I2C interface */
 208 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 209
 210 /* I2C DS1631 temperature sensor */
 211 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 212
 213 /* I2C EEPROM - AT24C128B */
 214 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 218
 219 /* I2C RTC */
 220 #define CONFIG_RTC_M41T11               1
 221 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 222 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 223
 224 /* GPIO */
 225 #define CONFIG_PCA953X
 226 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 227 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 228 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 229 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 230 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 231 #define CONFIG_SYS_I2C_PCA9553_ADDR     0x62
 232
 233 /*
 234  * PU = pulled high, PD = pulled low
 235  * I = input, O = output, IO = input/output
 236  */
 237 /* PCA9557 @ 0x18*/
 238 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 239 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 240 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 241 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 242 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 243 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 244
 245 /* PCA9557 @ 0x1c*/
 246 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 247 #define CONFIG_SYS_PCA953X_PLUG_GPIO0           0x02 /* Samtec connector GPIO */
 248 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 249 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 250 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 251 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 252 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 253 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 254
 255 /* PCA9557 @ 0x1e*/
 256 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 257 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 258 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 259 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 260 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 261 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; VPX Geographical address parity */
 262 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; VPX P1 SYSCON */
 263
 264 /* PCA9557 @ 0x1f */
 265 #define CONFIG_SYS_PCA953X_VPX_GPIO0            0x01 /* PU; VPX P15 GPIO */
 266 #define CONFIG_SYS_PCA953X_VPX_GPIO1            0x02 /* PU; VPX P15 GPIO */
 267 #define CONFIG_SYS_PCA953X_VPX_GPIO2            0x04 /* PU; VPX P15 GPIO */
 268 #define CONFIG_SYS_PCA953X_VPX_GPIO3            0x08 /* PU; VPX P15 GPIO */
 269
 270 /*
 271  * General PCI
 272  * Memory space is mapped 1-1, but I/O space must start from 0.
 273  */
 274 /* PCIE1 - PEX8518 */
 275 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 276 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 277 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 278 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 279 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 280 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 281
 282 /* PCIE2 - VPX P1 */
 283 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 284 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 285 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 286 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 287 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 288 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 289
 290 /*
 291  * Networking options
 292  */
 293 #define CONFIG_ETHPRIME         "eTSEC1"
 294
 295 #define CONFIG_TSEC1            1
 296 #define CONFIG_TSEC1_NAME       "eTSEC1"
 297 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 298 #define TSEC1_PHY_ADDR          1
 299 #define TSEC1_PHYIDX            0
 300 #define CONFIG_HAS_ETH0
 301
 302 #define CONFIG_TSEC2            1
 303 #define CONFIG_TSEC2_NAME       "eTSEC2"
 304 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 305 #define TSEC2_PHY_ADDR          2
 306 #define TSEC2_PHYIDX            0
 307 #define CONFIG_HAS_ETH1
 308
 309 /*
 310  * BAT mappings
 311  */
 312 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 313 #define CONFIG_SYS_CCSR_DEFAULT_DBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 314                                          BATL_PP_RW                     |\
 315                                          BATL_CACHEINHIBIT              |\
 316                                          BATL_GUARDEDSTORAGE)
 317 #define CONFIG_SYS_CCSR_DEFAULT_DBATU   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 318                                          BATU_BL_1M                     |\
 319                                          BATU_VS                        |\
 320                                          BATU_VP)
 321 #define CONFIG_SYS_CCSR_DEFAULT_IBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 322                                          BATL_PP_RW                     |\
 323                                          BATL_CACHEINHIBIT)
 324 #define CONFIG_SYS_CCSR_DEFAULT_IBATU   CONFIG_SYS_CCSR_DEFAULT_DBATU
 325 #endif
 326
 327 /*
 328  * BAT0         2G      Cacheable, non-guarded
 329  * 0x0000_0000  2G      DDR
 330  */
 331 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 332 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 333 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 334 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 335
 336 /*
 337  * BAT1         1G      Cache-inhibited, guarded
 338  * 0x8000_0000  1G      PCI-Express 1 Memory
 339  */
 340 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 341                                  BATL_PP_RW                     |\
 342                                  BATL_CACHEINHIBIT              |\
 343                                  BATL_GUARDEDSTORAGE)
 344 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 345                                  BATU_BL_1G                     |\
 346                                  BATU_VS                        |\
 347                                  BATU_VP)
 348 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 349                                  BATL_PP_RW                     |\
 350                                  BATL_CACHEINHIBIT)
 351 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 352
 353 /*
 354  * BAT2         512M    Cache-inhibited, guarded
 355  * 0xc000_0000  512M    PCI-Express 2 Memory
 356  */
 357 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 358                                  BATL_PP_RW                     |\
 359                                  BATL_CACHEINHIBIT              |\
 360                                  BATL_GUARDEDSTORAGE)
 361 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 362                                  BATU_BL_512M                   |\
 363                                  BATU_VS                        |\
 364                                  BATU_VP)
 365 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 366                                  BATL_PP_RW                     |\
 367                                  BATL_CACHEINHIBIT)
 368 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 369
 370 /*
 371  * BAT3         1M      Cache-inhibited, guarded
 372  * 0xe000_0000  1M      CCSR
 373  */
 374 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR             |\
 375                                  BATL_PP_RW                     |\
 376                                  BATL_CACHEINHIBIT              |\
 377                                  BATL_GUARDEDSTORAGE)
 378 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR             |\
 379                                  BATU_BL_1M                     |\
 380                                  BATU_VS                        |\
 381                                  BATU_VP)
 382 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR             |\
 383                                  BATL_PP_RW                     |\
 384                                  BATL_CACHEINHIBIT)
 385 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 386
 387 /*
 388  * BAT4         32M     Cache-inhibited, guarded
 389  * 0xe200_0000  16M     PCI-Express 1 I/O
 390  * 0xe300_0000  16M     PCI-Express 2 I/0
 391  */
 392 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 393                                  BATL_PP_RW                     |\
 394                                  BATL_CACHEINHIBIT              |\
 395                                  BATL_GUARDEDSTORAGE)
 396 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 397                                  BATU_BL_32M                    |\
 398                                  BATU_VS                        |\
 399                                  BATU_VP)
 400 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 401                                  BATL_PP_RW                     |\
 402                                  BATL_CACHEINHIBIT)
 403 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 404
 405 /*
 406  * BAT5         128K    Cacheable, non-guarded
 407  * 0xe400_1000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 408  */
 409 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR       |\
 410                                  BATL_PP_RW                     |\
 411                                  BATL_MEMCOHERENCE)
 412 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR       |\
 413                                  BATU_BL_128K                   |\
 414                                  BATU_VS                        |\
 415                                  BATU_VP)
 416 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 417 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 418
 419 /*
 420  * BAT6         256M    Cache-inhibited, guarded
 421  * 0xf000_0000  256M    FLASH
 422  */
 423 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE2         |\
 424                                  BATL_PP_RW                     |\
 425                                  BATL_CACHEINHIBIT              |\
 426                                  BATL_GUARDEDSTORAGE)
 427 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE          |\
 428                                  BATU_BL_256M                   |\
 429                                  BATU_VS                        |\
 430                                  BATU_VP)
 431 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE          |\
 432                                  BATL_PP_RW                     |\
 433                                  BATL_MEMCOHERENCE)
 434 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 435
 436 /* Map the last 1M of flash where we're running from reset */
 437 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 438                                  BATL_PP_RW                     |\
 439                                  BATL_CACHEINHIBIT              |\
 440                                  BATL_GUARDEDSTORAGE)
 441 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE                   |\
 442                                  BATU_BL_1M                     |\
 443                                  BATU_VS                        |\
 444                                  BATU_VP)
 445 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 446                                  BATL_PP_RW                     |\
 447                                  BATL_MEMCOHERENCE)
 448 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 449
 450 /*
 451  * BAT7         64M     Cache-inhibited, guarded
 452  * 0xe800_0000  64K     NAND FLASH
 453  * 0xe804_0000  128K    DUART Registers
 454  */
 455 #define CONFIG_SYS_DBAT7L       (CONFIG_SYS_NAND_BASE           |\
 456                                  BATL_PP_RW                     |\
 457                                  BATL_CACHEINHIBIT              |\
 458                                  BATL_GUARDEDSTORAGE)
 459 #define CONFIG_SYS_DBAT7U       (CONFIG_SYS_NAND_BASE           |\
 460                                  BATU_BL_512K                   |\
 461                                  BATU_VS                        |\
 462                                  BATU_VP)
 463 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_NAND_BASE           |\
 464                                  BATL_PP_RW                     |\
 465                                  BATL_CACHEINHIBIT)
 466 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 467
 468 /*
 469  * Miscellaneous configurable options
 470  */
 471 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 472 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 473 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 474
 475 /*
 476  * For booting Linux, the board info and command line data
 477  * have to be in the first 16 MB of memory, since this is
 478  * the maximum mapped by the Linux kernel during initialization.
 479  */
 480 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 481 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 482
 483 /*
 484  * Environment Configuration
 485  */
 486
 487 /*
 488  * Flash memory map:
 489  * fffc0000 - ffffffff  Pri FDT (256KB)
 490  * fff80000 - fffbffff  Pri U-Boot Environment (256 KB)
 491  * fff00000 - fff7ffff  Pri U-Boot (512 KB)
 492  * fef00000 - ffefffff  Pri OS image (16MB)
 493  * f8000000 - feefffff  Pri OS Use/Filesystem (111MB)
 494  *
 495  * f7fc0000 - f7ffffff  Sec FDT (256KB)
 496  * f7f80000 - f7fbffff  Sec U-Boot Environment (256 KB)
 497  * f7f00000 - f7f7ffff  Sec U-Boot (512 KB)
 498  * f6f00000 - f7efffff  Sec OS image (16MB)
 499  * f0000000 - f6efffff  Sec OS Use/Filesystem (111MB)
 500  */
 501 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff00000)
 502 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f00000)
 503 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfffc0000)
 504 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7fc0000)
 505 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 506 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 507
 508 #define CONFIG_PROG_UBOOT1                                              \
 509         "$download_cmd $loadaddr $ubootfile; "                          \
 510         "if test $? -eq 0; then "                                       \
 511                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 512                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 513                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 514                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 515                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 516                 "if test $? -ne 0; then "                               \
 517                         "echo PROGRAM FAILED; "                         \
 518                 "else; "                                                \
 519                         "echo PROGRAM SUCCEEDED; "                      \
 520                 "fi; "                                                  \
 521         "else; "                                                        \
 522                 "echo DOWNLOAD FAILED; "                                \
 523         "fi;"
 524
 525 #define CONFIG_PROG_UBOOT2                                              \
 526         "$download_cmd $loadaddr $ubootfile; "                          \
 527         "if test $? -eq 0; then "                                       \
 528                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 529                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 530                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 531                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 532                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 533                 "if test $? -ne 0; then "                               \
 534                         "echo PROGRAM FAILED; "                         \
 535                 "else; "                                                \
 536                         "echo PROGRAM SUCCEEDED; "                      \
 537                 "fi; "                                                  \
 538         "else; "                                                        \
 539                 "echo DOWNLOAD FAILED; "                                \
 540         "fi;"
 541
 542 #define CONFIG_BOOT_OS_NET                                              \
 543         "$download_cmd $osaddr $osfile; "                               \
 544         "if test $? -eq 0; then "                                       \
 545                 "if test -n $fdtaddr; then "                            \
 546                         "$download_cmd $fdtaddr $fdtfile; "             \
 547                         "if test $? -eq 0; then "                       \
 548                                 "bootm $osaddr - $fdtaddr; "            \
 549                         "else; "                                        \
 550                                 "echo FDT DOWNLOAD FAILED; "            \
 551                         "fi; "                                          \
 552                 "else; "                                                \
 553                         "bootm $osaddr; "                               \
 554                 "fi; "                                                  \
 555         "else; "                                                        \
 556                 "echo OS DOWNLOAD FAILED; "                             \
 557         "fi;"
 558
 559 #define CONFIG_PROG_OS1                                                 \
 560         "$download_cmd $osaddr $osfile; "                               \
 561         "if test $? -eq 0; then "                                       \
 562                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 563                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 564                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 565                 "if test $? -ne 0; then "                               \
 566                         "echo OS PROGRAM FAILED; "                      \
 567                 "else; "                                                \
 568                         "echo OS PROGRAM SUCCEEDED; "                   \
 569                 "fi; "                                                  \
 570         "else; "                                                        \
 571                 "echo OS DOWNLOAD FAILED; "                             \
 572         "fi;"
 573
 574 #define CONFIG_PROG_OS2                                                 \
 575         "$download_cmd $osaddr $osfile; "                               \
 576         "if test $? -eq 0; then "                                       \
 577                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 578                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 579                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 580                 "if test $? -ne 0; then "                               \
 581                         "echo OS PROGRAM FAILED; "                      \
 582                 "else; "                                                \
 583                         "echo OS PROGRAM SUCCEEDED; "                   \
 584                 "fi; "                                                  \
 585         "else; "                                                        \
 586                 "echo OS DOWNLOAD FAILED; "                             \
 587         "fi;"
 588
 589 #define CONFIG_PROG_FDT1                                                \
 590         "$download_cmd $fdtaddr $fdtfile; "                             \
 591         "if test $? -eq 0; then "                                       \
 592                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 593                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 594                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 595                 "if test $? -ne 0; then "                               \
 596                         "echo FDT PROGRAM FAILED; "                     \
 597                 "else; "                                                \
 598                         "echo FDT PROGRAM SUCCEEDED; "                  \
 599                 "fi; "                                                  \
 600         "else; "                                                        \
 601                 "echo FDT DOWNLOAD FAILED; "                            \
 602         "fi;"
 603
 604 #define CONFIG_PROG_FDT2                                                \
 605         "$download_cmd $fdtaddr $fdtfile; "                             \
 606         "if test $? -eq 0; then "                                       \
 607                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 608                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 609                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 610                 "if test $? -ne 0; then "                               \
 611                         "echo FDT PROGRAM FAILED; "                     \
 612                 "else; "                                                \
 613                         "echo FDT PROGRAM SUCCEEDED; "                  \
 614                 "fi; "                                                  \
 615         "else; "                                                        \
 616                 "echo FDT DOWNLOAD FAILED; "                            \
 617         "fi;"
 618
 619 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 620         "autoload=yes\0"                                                \
 621         "download_cmd=tftp\0"                                           \
 622         "console_args=console=ttyS0,115200\0"                           \
 623         "root_args=root=/dev/nfs rw\0"                                  \
 624         "misc_args=ip=on\0"                                             \
 625         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 626         "bootfile=/home/user/file\0"                                    \
 627         "osfile=/home/user/board.uImage\0"                              \
 628         "fdtfile=/home/user/board.dtb\0"                                \
 629         "ubootfile=/home/user/u-boot.bin\0"                             \
 630         "fdtaddr=0x1e00000\0"                                           \
 631         "osaddr=0x1000000\0"                                            \
 632         "loadaddr=0x1000000\0"                                          \
 633         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 634         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 635         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 636         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 637         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 638         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 639         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 640         "bootcmd_flash1=run set_bootargs; "                             \
 641                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 642         "bootcmd_flash2=run set_bootargs; "                             \
 643                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 644         "bootcmd=run bootcmd_flash1\0"
 645 #endif  /* __CONFIG_H */