1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WORK Microwave work_92105 board configuration file
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
9 #ifndef __CONFIG_WORK_92105_H__
10 #define __CONFIG_WORK_92105_H__
12 /* SoC and board defines */
13 #include <linux/sizes.h>
14 #include <asm/arch/cpu.h>
17 * Define work_92105 machine type by hand -- done only for compatibility
18 * with original board code
20 #define CONFIG_MACH_TYPE 736
22 #if !defined(CONFIG_SPL_BUILD)
23 #define CONFIG_SKIP_LOWLEVEL_INIT
27 * Memory configurations
29 #define CONFIG_SYS_MALLOC_LEN SZ_1M
30 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
31 #define CONFIG_SYS_SDRAM_SIZE SZ_128M
33 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
36 - GENERATED_GBL_DATA_SIZE)
42 #define CONFIG_LPC32XX_ETH
43 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
50 #define CONFIG_SYS_I2C_SPEED 350000
60 #define CONFIG_RTC_DS1374
63 * U-Boot General Configurations
65 #define CONFIG_SYS_CBSIZE 1024
66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
69 * NAND chip timings for FIXME: which one?
72 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
73 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
74 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
75 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
76 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
77 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
78 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
84 /* driver configuration */
85 #define CONFIG_SYS_NAND_SELF_INIT
86 #define CONFIG_SYS_MAX_NAND_DEVICE 1
87 #define CONFIG_SYS_MAX_NAND_CHIPS 1
88 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
89 #define CONFIG_NAND_LPC32XX_MLC
95 #define CONFIG_LPC32XX_GPIO
104 #define CONFIG_CMDLINE_TAG
105 #define CONFIG_SETUP_MEMORY_TAGS
106 #define CONFIG_INITRD_TAG
108 #define CONFIG_BOOTFILE "uImage"
109 #define CONFIG_LOADADDR 0x80008000
115 /* SPL will be executed at offset 0 */
116 /* SPL will use SRAM as stack */
117 #define CONFIG_SPL_STACK 0x0000FFF8
118 /* Use the framework and generic lib */
119 /* SPL will use serial */
120 /* SPL will load U-Boot from NAND offset 0x40000 */
121 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
122 #define CONFIG_SPL_PAD_TO 0x20000
123 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
124 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
125 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
126 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
129 * Include SoC specific configuration
131 #include <asm/arch/config.h>
133 #endif /* __CONFIG_WORK_92105_H__*/