include/configs/vpac270.h

   1 /*
   2  * Voipac PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Board Configuration Options
  27  */
  28 #define CONFIG_PXA27X           1       /* Marvell PXA270 CPU */
  29 #define CONFIG_VPAC270          1       /* Voipac PXA270 board */
  30 #define CONFIG_SYS_TEXT_BASE    0x0
  31
  32 /*
  33  * Environment settings
  34  */
  35 #define CONFIG_ENV_OVERWRITE
  36 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
  37 #define CONFIG_ARCH_CPU_INIT
  38 #define CONFIG_BOOTCOMMAND                                              \
  39         "if mmc init && fatload mmc 0 0xa4000000 uImage; then "         \
  40                 "bootm 0xa4000000; "                                    \
  41         "fi; "                                                          \
  42         "if usb reset && fatload usb 0 0xa4000000 uImage; then "        \
  43                 "bootm 0xa4000000; "                                    \
  44         "fi; "                                                          \
  45         "if ide reset && fatload ide 0 0xa4000000 uImage; then "        \
  46                 "bootm 0xa4000000; "                                    \
  47         "fi; "                                                          \
  48         "bootm 0x60000;"
  49 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
  50 #define CONFIG_TIMESTAMP
  51 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  52 #define CONFIG_CMDLINE_TAG
  53 #define CONFIG_SETUP_MEMORY_TAGS
  54 #define CONFIG_LZMA                     /* LZMA compression support */
  55
  56 /*
  57  * Serial Console Configuration
  58  */
  59 #define CONFIG_PXA_SERIAL
  60 #define CONFIG_FFUART                   1
  61 #define CONFIG_BAUDRATE                 115200
  62 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  63
  64 /*
  65  * Bootloader Components Configuration
  66  */
  67 #include <config_cmd_default.h>
  68
  69 #define CONFIG_CMD_NET
  70 #define CONFIG_CMD_ENV
  71 #undef  CONFIG_CMD_IMLS
  72 #define CONFIG_CMD_MMC
  73 #define CONFIG_CMD_USB
  74 #undef  CONFIG_LCD
  75 #define CONFIG_CMD_IDE
  76
  77 #ifdef  CONFIG_ONENAND
  78 #undef  CONFIG_CMD_FLASH
  79 #define CONFIG_CMD_ONENAND
  80 #else
  81 #define CONFIG_CMD_FLASH
  82 #undef  CONFIG_CMD_ONENAND
  83 #endif
  84
  85 /*
  86  * Networking Configuration
  87  *  chip on the Voipac PXA270 board
  88  */
  89 #ifdef  CONFIG_CMD_NET
  90 #define CONFIG_CMD_PING
  91 #define CONFIG_CMD_DHCP
  92
  93 #define CONFIG_DRIVER_DM9000            1
  94 #define CONFIG_DM9000_BASE              0x08000300      /* CS2 */
  95 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  96 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  97 #define CONFIG_NET_RETRY_COUNT          10
  98
  99 #define CONFIG_BOOTP_BOOTFILESIZE
 100 #define CONFIG_BOOTP_BOOTPATH
 101 #define CONFIG_BOOTP_GATEWAY
 102 #define CONFIG_BOOTP_HOSTNAME
 103 #endif
 104
 105 /*
 106  * MMC Card Configuration
 107  */
 108 #ifdef  CONFIG_CMD_MMC
 109 #define CONFIG_MMC
 110 #define CONFIG_GENERIC_MMC
 111 #define CONFIG_PXA_MMC_GENERIC
 112 #define CONFIG_SYS_MMC_BASE             0xF0000000
 113 #define CONFIG_CMD_FAT
 114 #define CONFIG_CMD_EXT2
 115 #define CONFIG_DOS_PARTITION
 116 #endif
 117
 118 /*
 119  * KGDB
 120  */
 121 #ifdef  CONFIG_CMD_KGDB
 122 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
 123 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
 124 #endif
 125
 126 /*
 127  * HUSH Shell Configuration
 128  */
 129 #define CONFIG_SYS_HUSH_PARSER          1
 130 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 131
 132 #define CONFIG_SYS_LONGHELP
 133 #ifdef  CONFIG_SYS_HUSH_PARSER
 134 #define CONFIG_SYS_PROMPT               "$ "
 135 #else
 136 #define CONFIG_SYS_PROMPT               "=> "
 137 #endif
 138 #define CONFIG_SYS_CBSIZE               256
 139 #define CONFIG_SYS_PBSIZE               \
 140         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 141 #define CONFIG_SYS_MAXARGS              16
 142 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 143 #define CONFIG_SYS_DEVICE_NULLDEV       1
 144
 145 /*
 146  * Clock Configuration
 147  */
 148 #define CONFIG_SYS_HZ                   1000            /* Timer @ 3250000 Hz */
 149 #define CONFIG_SYS_CPUSPEED             0x190           /* 312MHz */
 150
 151 /*
 152  * Stack sizes
 153  */
 154 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
 155 #ifdef  CONFIG_USE_IRQ
 156 #define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
 157 #define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
 158 #endif
 159
 160 /*
 161  * DRAM Map
 162  */
 163 #define CONFIG_NR_DRAM_BANKS            2               /* 2 banks of DRAM */
 164 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 165 #define PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
 166
 167 #ifdef  CONFIG_RAM_256M
 168 #define PHYS_SDRAM_2                    0x80000000      /* SDRAM Bank #2 */
 169 #define PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
 170 #endif
 171
 172 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 173 #ifdef  CONFIG_RAM_256M
 174 #define CONFIG_SYS_DRAM_SIZE            0x10000000      /* 256 MB DRAM */
 175 #else
 176 #define CONFIG_SYS_DRAM_SIZE            0x08000000      /* 128 MB DRAM */
 177 #endif
 178
 179 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 180 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 181
 182 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 183 #define CONFIG_SYS_IPL_LOAD_ADDR        (0x5c000000)
 184 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 185 #define CONFIG_SYS_INIT_SP_ADDR         \
 186         (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
 187
 188 /*
 189  * NOR FLASH
 190  */
 191 #define CONFIG_SYS_MONITOR_BASE         0x0
 192 #define CONFIG_SYS_MONITOR_LEN          0x40000
 193 #define CONFIG_ENV_ADDR                 \
 194                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 195 #define CONFIG_ENV_SIZE                 0x4000
 196
 197 #if     defined(CONFIG_CMD_FLASH)       /* NOR */
 198 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 199
 200 #ifdef  CONFIG_RAM_256M
 201 #define PHYS_FLASH_2                    0x02000000      /* Flash Bank #2 */
 202 #endif
 203
 204 #define CONFIG_SYS_FLASH_CFI
 205 #define CONFIG_FLASH_CFI_DRIVER         1
 206
 207 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 208 #ifdef  CONFIG_RAM_256M
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 210 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2 }
 211 #else
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 213 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 214 #endif
 215
 216 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ)
 217 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ)
 218
 219 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 220 #define CONFIG_SYS_FLASH_PROTECTION             1
 221
 222 #define CONFIG_ENV_IS_IN_FLASH          1
 223
 224 /*
 225  * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the
 226  * flash consists of 0x20000 bytes big sectors.
 227  */
 228 #if     (CONFIG_ENV_ADDR <= 0x18000)
 229 #define CONFIG_ENV_SECT_SIZE            0x8000
 230 #else
 231 #define CONFIG_ENV_SECT_SIZE            0x20000
 232 #endif
 233
 234 #elif   defined(CONFIG_CMD_ONENAND)     /* OneNAND */
 235 #define CONFIG_SYS_NO_FLASH
 236 #define CONFIG_SYS_ONENAND_BASE         0x00000000
 237
 238 #define CONFIG_ENV_IS_IN_ONENAND        1
 239 #define CONFIG_ENV_SECT_SIZE            0x20000
 240
 241 #else   /* No flash */
 242 #define CONFIG_SYS_NO_FLASH
 243 #define CONFIG_SYS_ENV_IS_NOWHERE
 244 #endif
 245
 246 /*
 247  * IDE
 248  */
 249 #ifdef  CONFIG_CMD_IDE
 250 #define CONFIG_LBA48
 251 #undef  CONFIG_IDE_LED
 252 #undef  CONFIG_IDE_RESET
 253
 254 #define __io
 255
 256 #define CONFIG_SYS_IDE_MAXBUS           1
 257 #define CONFIG_SYS_IDE_MAXDEVICE        1
 258
 259 #define CONFIG_SYS_ATA_BASE_ADDR        0x0c000000
 260 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0
 261
 262 #define CONFIG_SYS_ATA_DATA_OFFSET      0x120
 263 #define CONFIG_SYS_ATA_REG_OFFSET       0x120
 264 #define CONFIG_SYS_ATA_ALT_OFFSET       0x120
 265
 266 #define CONFIG_SYS_ATA_STRIDE           2
 267 #endif
 268
 269 /*
 270  * GPIO settings
 271  */
 272 #define CONFIG_SYS_GPSR0_VAL    0x01308800
 273 #define CONFIG_SYS_GPSR1_VAL    0x00cf0000
 274 #define CONFIG_SYS_GPSR2_VAL    0x922ac000
 275 #define CONFIG_SYS_GPSR3_VAL    0x0161e800
 276
 277 #define CONFIG_SYS_GPCR0_VAL    0x00010000
 278 #define CONFIG_SYS_GPCR1_VAL    0x0
 279 #define CONFIG_SYS_GPCR2_VAL    0x0
 280 #define CONFIG_SYS_GPCR3_VAL    0x0
 281
 282 #define CONFIG_SYS_GPDR0_VAL    0xcbb18800
 283 #define CONFIG_SYS_GPDR1_VAL    0xfccfa981
 284 #define CONFIG_SYS_GPDR2_VAL    0x922affff
 285 #define CONFIG_SYS_GPDR3_VAL    0x0161e904
 286
 287 #define CONFIG_SYS_GAFR0_L_VAL  0x00100000
 288 #define CONFIG_SYS_GAFR0_U_VAL  0xa5da8510
 289 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 290 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5a0aa
 291 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 292 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a401
 293 #define CONFIG_SYS_GAFR3_L_VAL  0x54010310
 294 #define CONFIG_SYS_GAFR3_U_VAL  0x00025401
 295
 296 #define CONFIG_SYS_PSSR_VAL     0x30
 297
 298 /*
 299  * Clock settings
 300  */
 301 #define CONFIG_SYS_CKEN         0x00500240
 302 #define CONFIG_SYS_CCCR         0x02000290
 303
 304 /*
 305  * Memory settings
 306  */
 307 #define CONFIG_SYS_MSC0_VAL     0x3ffc95fa
 308 #define CONFIG_SYS_MSC1_VAL     0x02ccf974
 309 #define CONFIG_SYS_MSC2_VAL     0x00000000
 310 #ifdef  CONFIG_RAM_256M
 311 #define CONFIG_SYS_MDCNFG_VAL   0x8ad30ad3
 312 #else
 313 #define CONFIG_SYS_MDCNFG_VAL   0x88000ad3
 314 #endif
 315 #define CONFIG_SYS_MDREFR_VAL   0x201fe01e
 316 #define CONFIG_SYS_MDMRS_VAL    0x00000000
 317 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
 318 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 319 #define CONFIG_SYS_MEM_BUF_IMP  0x0f
 320
 321 /*
 322  * PCMCIA and CF Interfaces
 323  */
 324 #define CONFIG_SYS_MECR_VAL     0x00000001
 325 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
 326 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 327 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
 328 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 329 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
 330 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 331
 332 /*
 333  * LCD
 334  */
 335 #ifdef  CONFIG_LCD
 336 #define CONFIG_VOIPAC_LCD
 337 #endif
 338
 339 /*
 340  * USB
 341  */
 342 #ifdef  CONFIG_CMD_USB
 343 #define CONFIG_USB_OHCI_NEW
 344 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 345 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
 346 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 347 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
 348 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "vpac270"
 349 #define CONFIG_USB_STORAGE
 350 #endif
 351
 352 #endif  /* __CONFIG_H */