ed18dbeb3268e8c90f49c1c6751e9af50dcdea7a
[platform/kernel/u-boot.git] / include / configs / vpac270.h
1 /*
2  * Voipac PXA270 configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #ifndef __CONFIG_H
23 #define __CONFIG_H
24
25 /*
26  * High Level Board Configuration Options
27  */
28 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
29 #define CONFIG_VPAC270          1       /* Voipac PXA270 board */
30 #define CONFIG_SYS_TEXT_BASE    0xa0000000
31
32 #ifdef  CONFIG_ONENAND
33 #define CONFIG_SPL
34 #define CONFIG_SPL_ONENAND_SUPPORT
35 #define CONFIG_SPL_ONENAND_LOAD_ADDR    0x2000
36 #define CONFIG_SPL_ONENAND_LOAD_SIZE    \
37         (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
38 #define CONFIG_SPL_TEXT_BASE    0x5c000000
39 #define CONFIG_SPL_LDSCRIPT     "board/vpac270/u-boot-spl.lds"
40 #endif
41
42 /*
43  * Environment settings
44  */
45 #define CONFIG_ENV_OVERWRITE
46 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
47 #define CONFIG_ARCH_CPU_INIT
48 #define CONFIG_BOOTCOMMAND                                              \
49         "if mmc init && fatload mmc 0 0xa4000000 uImage; then "         \
50                 "bootm 0xa4000000; "                                    \
51         "fi; "                                                          \
52         "if usb reset && fatload usb 0 0xa4000000 uImage; then "        \
53                 "bootm 0xa4000000; "                                    \
54         "fi; "                                                          \
55         "if ide reset && fatload ide 0 0xa4000000 uImage; then "        \
56                 "bootm 0xa4000000; "                                    \
57         "fi; "                                                          \
58         "bootm 0x60000;"
59
60 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
61         "update_onenand="                                               \
62                 "onenand erase 0x0 0x80000 ; "                          \
63                 "onenand write 0xa0000000 0x0 0x80000"
64
65 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
66 #define CONFIG_TIMESTAMP
67 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
68 #define CONFIG_CMDLINE_TAG
69 #define CONFIG_SETUP_MEMORY_TAGS
70 #define CONFIG_LZMA                     /* LZMA compression support */
71 #define CONFIG_OF_LIBFDT
72
73 /*
74  * Serial Console Configuration
75  */
76 #define CONFIG_PXA_SERIAL
77 #define CONFIG_FFUART                   1
78 #define CONFIG_BAUDRATE                 115200
79
80 /*
81  * Bootloader Components Configuration
82  */
83 #include <config_cmd_default.h>
84
85 #define CONFIG_CMD_NET
86 #define CONFIG_CMD_ENV
87 #undef  CONFIG_CMD_IMLS
88 #define CONFIG_CMD_MMC
89 #define CONFIG_CMD_USB
90 #undef  CONFIG_LCD
91 #define CONFIG_CMD_IDE
92
93 #ifdef  CONFIG_ONENAND
94 #undef  CONFIG_CMD_FLASH
95 #define CONFIG_CMD_ONENAND
96 #else
97 #define CONFIG_CMD_FLASH
98 #undef  CONFIG_CMD_ONENAND
99 #endif
100
101 /*
102  * Networking Configuration
103  *  chip on the Voipac PXA270 board
104  */
105 #ifdef  CONFIG_CMD_NET
106 #define CONFIG_CMD_PING
107 #define CONFIG_CMD_DHCP
108
109 #define CONFIG_DRIVER_DM9000            1
110 #define CONFIG_DM9000_BASE              0x08000300      /* CS2 */
111 #define DM9000_IO                       (CONFIG_DM9000_BASE)
112 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
113 #define CONFIG_NET_RETRY_COUNT          10
114
115 #define CONFIG_BOOTP_BOOTFILESIZE
116 #define CONFIG_BOOTP_BOOTPATH
117 #define CONFIG_BOOTP_GATEWAY
118 #define CONFIG_BOOTP_HOSTNAME
119 #endif
120
121 /*
122  * MMC Card Configuration
123  */
124 #ifdef  CONFIG_CMD_MMC
125 #define CONFIG_MMC
126 #define CONFIG_GENERIC_MMC
127 #define CONFIG_PXA_MMC_GENERIC
128 #define CONFIG_SYS_MMC_BASE             0xF0000000
129 #define CONFIG_CMD_FAT
130 #define CONFIG_CMD_EXT2
131 #define CONFIG_DOS_PARTITION
132 #endif
133
134 /*
135  * KGDB
136  */
137 #ifdef  CONFIG_CMD_KGDB
138 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
139 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
140 #endif
141
142 /*
143  * HUSH Shell Configuration
144  */
145 #define CONFIG_SYS_HUSH_PARSER          1
146 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
147
148 #define CONFIG_SYS_LONGHELP
149 #ifdef  CONFIG_SYS_HUSH_PARSER
150 #define CONFIG_SYS_PROMPT               "$ "
151 #else
152 #define CONFIG_SYS_PROMPT               "=> "
153 #endif
154 #define CONFIG_SYS_CBSIZE               256
155 #define CONFIG_SYS_PBSIZE               \
156         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
157 #define CONFIG_SYS_MAXARGS              16
158 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
159 #define CONFIG_SYS_DEVICE_NULLDEV       1
160 #define CONFIG_CMDLINE_EDITING          1
161 #define CONFIG_AUTO_COMPLETE            1
162
163 /*
164  * Clock Configuration
165  */
166 #define CONFIG_SYS_HZ                   1000            /* Timer @ 3250000 Hz */
167 #define CONFIG_SYS_CPUSPEED             0x190           /* 312MHz */
168
169 /*
170  * Stack sizes
171  */
172 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
173 #ifdef  CONFIG_USE_IRQ
174 #define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
175 #define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
176 #endif
177
178 /*
179  * DRAM Map
180  */
181 #define CONFIG_NR_DRAM_BANKS            2               /* 2 banks of DRAM */
182 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
183 #define PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
184
185 #ifdef  CONFIG_RAM_256M
186 #define PHYS_SDRAM_2                    0x80000000      /* SDRAM Bank #2 */
187 #define PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
188 #endif
189
190 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
191 #ifdef  CONFIG_RAM_256M
192 #define CONFIG_SYS_DRAM_SIZE            0x10000000      /* 256 MB DRAM */
193 #else
194 #define CONFIG_SYS_DRAM_SIZE            0x08000000      /* 128 MB DRAM */
195 #endif
196
197 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
198 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
199
200 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
201 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
202 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
203
204 /*
205  * NOR FLASH
206  */
207 #define CONFIG_SYS_MONITOR_BASE         0x0
208 #define CONFIG_SYS_MONITOR_LEN          0x80000
209 #define CONFIG_ENV_ADDR                 \
210                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
211 #define CONFIG_ENV_SIZE                 0x20000
212 #define CONFIG_ENV_SECT_SIZE            0x20000
213
214 #if     defined(CONFIG_CMD_FLASH)       /* NOR */
215 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
216
217 #ifdef  CONFIG_RAM_256M
218 #define PHYS_FLASH_2                    0x02000000      /* Flash Bank #2 */
219 #endif
220
221 #define CONFIG_SYS_FLASH_CFI
222 #define CONFIG_FLASH_CFI_DRIVER         1
223
224 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
225 #ifdef  CONFIG_RAM_256M
226 #define CONFIG_SYS_MAX_FLASH_BANKS      2
227 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2 }
228 #else
229 #define CONFIG_SYS_MAX_FLASH_BANKS      1
230 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
231 #endif
232
233 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ)
234 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ)
235
236 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
237 #define CONFIG_SYS_FLASH_PROTECTION             1
238
239 #define CONFIG_ENV_IS_IN_FLASH          1
240
241 #elif   defined(CONFIG_CMD_ONENAND)     /* OneNAND */
242 #define CONFIG_SYS_NO_FLASH
243 #define CONFIG_SYS_ONENAND_BASE         0x00000000
244
245 #define CONFIG_ENV_IS_IN_ONENAND        1
246
247 #else   /* No flash */
248 #define CONFIG_SYS_NO_FLASH
249 #define CONFIG_SYS_ENV_IS_NOWHERE
250 #endif
251
252 /*
253  * IDE
254  */
255 #ifdef  CONFIG_CMD_IDE
256 #define CONFIG_LBA48
257 #undef  CONFIG_IDE_LED
258 #undef  CONFIG_IDE_RESET
259
260 #define __io
261
262 #define CONFIG_SYS_IDE_MAXBUS           1
263 #define CONFIG_SYS_IDE_MAXDEVICE        1
264
265 #define CONFIG_SYS_ATA_BASE_ADDR        0x0c000000
266 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0
267
268 #define CONFIG_SYS_ATA_DATA_OFFSET      0x120
269 #define CONFIG_SYS_ATA_REG_OFFSET       0x120
270 #define CONFIG_SYS_ATA_ALT_OFFSET       0x120
271
272 #define CONFIG_SYS_ATA_STRIDE           2
273 #endif
274
275 /*
276  * GPIO settings
277  */
278 #define CONFIG_SYS_GPSR0_VAL    0x01308800
279 #define CONFIG_SYS_GPSR1_VAL    0x00cf0000
280 #define CONFIG_SYS_GPSR2_VAL    0x922ac000
281 #define CONFIG_SYS_GPSR3_VAL    0x0161e800
282
283 #define CONFIG_SYS_GPCR0_VAL    0x00010000
284 #define CONFIG_SYS_GPCR1_VAL    0x0
285 #define CONFIG_SYS_GPCR2_VAL    0x0
286 #define CONFIG_SYS_GPCR3_VAL    0x0
287
288 #define CONFIG_SYS_GPDR0_VAL    0xcbb18800
289 #define CONFIG_SYS_GPDR1_VAL    0xfccfa981
290 #define CONFIG_SYS_GPDR2_VAL    0x922affff
291 #define CONFIG_SYS_GPDR3_VAL    0x0161e904
292
293 #define CONFIG_SYS_GAFR0_L_VAL  0x00100000
294 #define CONFIG_SYS_GAFR0_U_VAL  0xa5da8510
295 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
296 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5a0aa
297 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
298 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a401
299 #define CONFIG_SYS_GAFR3_L_VAL  0x54010310
300 #define CONFIG_SYS_GAFR3_U_VAL  0x00025401
301
302 #define CONFIG_SYS_PSSR_VAL     0x30
303
304 /*
305  * Clock settings
306  */
307 #define CONFIG_SYS_CKEN         0x00500240
308 #define CONFIG_SYS_CCCR         0x02000290
309
310 /*
311  * Memory settings
312  */
313 #define CONFIG_SYS_MSC0_VAL     0x3ffc95fa
314 #define CONFIG_SYS_MSC1_VAL     0x02ccf974
315 #define CONFIG_SYS_MSC2_VAL     0x00000000
316 #ifdef  CONFIG_RAM_256M
317 #define CONFIG_SYS_MDCNFG_VAL   0x8ad30ad3
318 #else
319 #define CONFIG_SYS_MDCNFG_VAL   0x88000ad3
320 #endif
321 #define CONFIG_SYS_MDREFR_VAL   0x201fe01e
322 #define CONFIG_SYS_MDMRS_VAL    0x00000000
323 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
324 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
325 #define CONFIG_SYS_MEM_BUF_IMP  0x0f
326
327 /*
328  * PCMCIA and CF Interfaces
329  */
330 #define CONFIG_SYS_MECR_VAL     0x00000001
331 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
332 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
333 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
334 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
335 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
336 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
337
338 /*
339  * LCD
340  */
341 #ifdef  CONFIG_LCD
342 #define CONFIG_VOIPAC_LCD
343 #endif
344
345 /*
346  * USB
347  */
348 #ifdef  CONFIG_CMD_USB
349 #define CONFIG_USB_OHCI_NEW
350 #define CONFIG_SYS_USB_OHCI_CPU_INIT
351 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
352 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
353 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
354 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "vpac270"
355 #define CONFIG_USB_STORAGE
356 #endif
357
358 #endif  /* __CONFIG_H */