include/configs/vexpress_aemv8a.h

   1 /*
   2  * Configuration for Versatile Express. Parts were derived from other ARM
   3  *   configurations.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __VEXPRESS_AEMV8A_H
   9 #define __VEXPRESS_AEMV8A_H
  10
  11 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  12 #ifndef CONFIG_SEMIHOSTING
  13 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
  14 #endif
  15 #define CONFIG_ARMV8_SWITCH_TO_EL1
  16 #endif
  17
  18 #define CONFIG_REMAKE_ELF
  19
  20 /* Link Definitions */
  21 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
  22         defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
  23 /* ATF loads u-boot here for BASE_FVP model */
  24 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  25 #elif CONFIG_TARGET_VEXPRESS64_JUNO
  26 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  27 #endif
  28
  29 #define CONFIG_SYS_BOOTM_LEN (64 << 20)      /* Increase max gunzip size */
  30
  31 /* CS register bases for the original memory map. */
  32 #define V2M_PA_CS0                      0x00000000
  33 #define V2M_PA_CS1                      0x14000000
  34 #define V2M_PA_CS2                      0x18000000
  35 #define V2M_PA_CS3                      0x1c000000
  36 #define V2M_PA_CS4                      0x0c000000
  37 #define V2M_PA_CS5                      0x10000000
  38
  39 #define V2M_PERIPH_OFFSET(x)            (x << 16)
  40 #define V2M_SYSREGS                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  41 #define V2M_SYSCTL                      (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  42 #define V2M_SERIAL_BUS_PCI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  43
  44 #define V2M_BASE                        0x80000000
  45
  46 /* Common peripherals relative to CS7. */
  47 #define V2M_AACI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  48 #define V2M_MMCI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  49 #define V2M_KMI0                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  50 #define V2M_KMI1                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  51
  52 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  53 #define V2M_UART0                       0x7ff80000
  54 #define V2M_UART1                       0x7ff70000
  55 #else /* Not Juno */
  56 #define V2M_UART0                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  57 #define V2M_UART1                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  58 #define V2M_UART2                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  59 #define V2M_UART3                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  60 #endif
  61
  62 #define V2M_WDT                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  63
  64 #define V2M_TIMER01                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  65 #define V2M_TIMER23                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  66
  67 #define V2M_SERIAL_BUS_DVI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
  68 #define V2M_RTC                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
  69
  70 #define V2M_CF                          (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
  71
  72 #define V2M_CLCD                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
  73
  74 /* System register offsets. */
  75 #define V2M_SYS_CFGDATA                 (V2M_SYSREGS + 0x0a0)
  76 #define V2M_SYS_CFGCTRL                 (V2M_SYSREGS + 0x0a4)
  77 #define V2M_SYS_CFGSTAT                 (V2M_SYSREGS + 0x0a8)
  78
  79 /* Generic Timer Definitions */
  80 #define COUNTER_FREQUENCY               (0x1800000)     /* 24MHz */
  81
  82 /* Generic Interrupt Controller Definitions */
  83 #ifdef CONFIG_GICV3
  84 #define GICD_BASE                       (0x2f000000)
  85 #define GICR_BASE                       (0x2f100000)
  86 #else
  87
  88 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
  89         defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
  90 #define GICD_BASE                       (0x2f000000)
  91 #define GICC_BASE                       (0x2c000000)
  92 #elif CONFIG_TARGET_VEXPRESS64_JUNO
  93 #define GICD_BASE                       (0x2C010000)
  94 #define GICC_BASE                       (0x2C02f000)
  95 #endif
  96 #endif /* !CONFIG_GICV3 */
  97
  98 /* Size of malloc() pool */
  99 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (8 << 20))
 100
 101 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
 102 /* The Vexpress64 simulators use SMSC91C111 */
 103 #define CONFIG_SMC91111                 1
 104 #define CONFIG_SMC91111_BASE            (0x01A000000)
 105 #endif
 106
 107 /* PL011 Serial Configuration */
 108 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 109 #define CONFIG_PL011_CLOCK              7273800
 110 #else
 111 #define CONFIG_PL011_CLOCK              24000000
 112 #endif
 113
 114 /*#define CONFIG_MENU_SHOW*/
 115
 116 /* BOOTP options */
 117 #define CONFIG_BOOTP_BOOTFILESIZE
 118
 119 /* Miscellaneous configurable options */
 120 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x10000000)
 121
 122 /* Physical Memory Map */
 123 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 124 /* Top 16MB reserved for secure world use */
 125 #define DRAM_SEC_SIZE           0x01000000
 126 #define PHYS_SDRAM_1_SIZE       0x80000000 - DRAM_SEC_SIZE
 127 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM_1
 128
 129 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 130 #define CONFIG_NR_DRAM_BANKS            2
 131 #define PHYS_SDRAM_2                    (0x880000000)
 132 #define PHYS_SDRAM_2_SIZE               0x180000000
 133 #else
 134 #define CONFIG_NR_DRAM_BANKS            1
 135 #endif
 136
 137 /* Enable memtest */
 138 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
 139 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
 140
 141 /* Initial environment variables */
 142 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 143 /*
 144  * Defines where the kernel and FDT exist in NOR flash and where it will
 145  * be copied into DRAM
 146  */
 147 #define CONFIG_EXTRA_ENV_SETTINGS       \
 148                                 "kernel_name=norkern\0" \
 149                                 "kernel_alt_name=Image\0"       \
 150                                 "kernel_addr=0x80080000\0" \
 151                                 "initrd_name=ramdisk.img\0"     \
 152                                 "initrd_addr=0x84000000\0"      \
 153                                 "fdtfile=board.dtb\0" \
 154                                 "fdt_alt_name=juno\0" \
 155                                 "fdt_addr=0x83000000\0" \
 156                                 "fdt_high=0xffffffffffffffff\0" \
 157                                 "initrd_high=0xffffffffffffffff\0" \
 158
 159 /* Copy the kernel and FDT to DRAM memory and boot */
 160 #define CONFIG_BOOTCOMMAND      "afs load ${kernel_name} ${kernel_addr} ; " \
 161                                 "if test $? -eq 1; then "\
 162                                 "  echo Loading ${kernel_alt_name} instead of "\
 163                                 "${kernel_name}; "\
 164                                 "  afs load ${kernel_alt_name} ${kernel_addr};"\
 165                                 "fi ; "\
 166                                 "afs load  ${fdtfile} ${fdt_addr} ; " \
 167                                 "if test $? -eq 1; then "\
 168                                 "  echo Loading ${fdt_alt_name} instead of "\
 169                                 "${fdtfile}; "\
 170                                 "  afs load ${fdt_alt_name} ${fdt_addr}; "\
 171                                 "fi ; "\
 172                                 "fdt addr ${fdt_addr}; fdt resize; " \
 173                                 "if afs load  ${initrd_name} ${initrd_addr} ; "\
 174                                 "then "\
 175                                 "  setenv initrd_param ${initrd_addr}; "\
 176                                 "  else setenv initrd_param -; "\
 177                                 "fi ; " \
 178                                 "booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
 179
 180
 181 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
 182 #define CONFIG_EXTRA_ENV_SETTINGS       \
 183                                 "kernel_name=Image\0"           \
 184                                 "kernel_addr=0x80080000\0"      \
 185                                 "initrd_name=ramdisk.img\0"     \
 186                                 "initrd_addr=0x88000000\0"      \
 187                                 "fdtfile=devtree.dtb\0"         \
 188                                 "fdt_addr=0x83000000\0"         \
 189                                 "fdt_high=0xffffffffffffffff\0" \
 190                                 "initrd_high=0xffffffffffffffff\0"
 191
 192 #define CONFIG_BOOTCOMMAND      "smhload ${kernel_name} ${kernel_addr}; " \
 193                                 "smhload ${fdtfile} ${fdt_addr}; " \
 194                                 "smhload ${initrd_name} ${initrd_addr} "\
 195                                 "initrd_end; " \
 196                                 "fdt addr ${fdt_addr}; fdt resize; " \
 197                                 "fdt chosen ${initrd_addr} ${initrd_end}; " \
 198                                 "booti $kernel_addr - $fdt_addr"
 199
 200
 201 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
 202 #define CONFIG_EXTRA_ENV_SETTINGS       \
 203                                 "kernel_addr=0x80080000\0"      \
 204                                 "initrd_addr=0x84000000\0"      \
 205                                 "fdt_addr=0x83000000\0"         \
 206                                 "fdt_high=0xffffffffffffffff\0" \
 207                                 "initrd_high=0xffffffffffffffff\0"
 208
 209 #define CONFIG_BOOTCOMMAND      "booti $kernel_addr $initrd_addr $fdt_addr"
 210
 211
 212 #endif
 213
 214 /* Monitor Command Prompt */
 215 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 216 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 217
 218 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 219 #define CONFIG_SYS_FLASH_BASE           0x08000000
 220 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
 221 #define CONFIG_SYS_MAX_FLASH_SECT       259
 222 /* Store environment at top of flash in the same location as blank.img */
 223 /* in the Juno firmware. */
 224 #define CONFIG_ENV_ADDR                 0x0BFC0000
 225 #define CONFIG_ENV_SECT_SIZE            0x00010000
 226 #else
 227 #define CONFIG_SYS_FLASH_BASE           0x0C000000
 228 /* 256 x 256KiB sectors */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       256
 230 /* Store environment at top of flash */
 231 #define CONFIG_ENV_ADDR                 0x0FFC0000
 232 #define CONFIG_ENV_SECT_SIZE            0x00040000
 233 #endif
 234
 235 #define CONFIG_SYS_FLASH_CFI            1
 236 #define CONFIG_FLASH_CFI_DRIVER         1
 237 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 238 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 239
 240 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
 241 #define CONFIG_SYS_FLASH_PROTECTION     /* The devices have real protection */
 242 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
 243 #define FLASH_MAX_SECTOR_SIZE           0x00040000
 244 #define CONFIG_ENV_SIZE                 CONFIG_ENV_SECT_SIZE
 245
 246 #endif /* __VEXPRESS_AEMV8A_H */