Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
[platform/kernel/u-boot.git] / include / configs / tuxx1.h
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *                    Dave Liu <daveliu@freescale.com>
4  *
5  * Copyright (C) 2007 Logic Product Development, Inc.
6  *                    Peter Barada <peterb@logicpd.com>
7  *
8  * Copyright (C) 2007 MontaVista Software, Inc.
9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
10  *
11  * (C) Copyright 2008
12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13  *
14  * (C) Copyright 2010-2011
15  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
16  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
17  *
18  * This program is free software; you can redistribute it and/or
19  * modify it under the terms of the GNU General Public License as
20  * published by the Free Software Foundation; either version 2 of
21  * the License, or (at your option) any later version.
22  */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28  * High Level Configuration Options
29  */
30 #define CONFIG_TUXXX            /* TUXX1 board (tuxa1/tuda1) specific */
31 #define CONFIG_HOSTNAME         tuxx1
32 #ifdef CONFIG_KM_DISABLE_APP2
33 #define CONFIG_KM_BOARD_NAME   "tuge1"
34 #else
35 #define CONFIG_KM_BOARD_NAME   "tuxx1"
36 #endif
37
38 #define CONFIG_SYS_TEXT_BASE    0xF0000000
39
40 /* include common defines/options for all 8321 Keymile boards */
41 #include "km/km8321-common.h"
42
43 #define CONFIG_SYS_APP1_BASE    0xA0000000    /* PAXG */
44 #define CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
45 #ifndef CONFIG_KM_DISABLE_APP2
46 #define CONFIG_SYS_APP2_BASE    0xB0000000    /* PINC3 */
47 #define CONFIG_SYS_APP2_SIZE    256 /* Megabytes */
48 #endif
49
50 /*
51  * Init Local Bus Memory Controller:
52  *
53  * Bank Bus     Machine PortSz  Size  Device on TUDA1  TUXA1  TUGE1
54  * ---- ---     ------- ------  -----  ----------------------------
55  *  2   Local   GPCM    8 bit  256MB             PAXG  LPXF   PAXI
56  *  3   Local   GPCM    8 bit  256MB             PINC3 PINC2  unused
57  *
58  */
59
60 /*
61  * Configuration for C2 on the local bus
62  */
63 /* Window base at flash base */
64 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
65 /* Window size: 256 MB */
66 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
67
68 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
69                                  BR_PS_8 | \
70                                  BR_MS_GPCM | \
71                                  BR_V)
72
73 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
74                                  OR_GPCM_CSNT | \
75                                  OR_GPCM_ACS_DIV4 | \
76                                  OR_GPCM_SCY_2 | \
77                                  OR_GPCM_TRLX_SET | \
78                                  OR_GPCM_EHTR_CLEAR | \
79                                  OR_GPCM_EAD)
80 #ifndef CONFIG_KM_DISABLE_APP2
81 /*
82  * Configuration for C3 on the local bus
83  */
84 /* Access window base at PINC3 base */
85 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
86 /* Window size: 256 MB */
87 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
88
89 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
90                                  BR_PS_8 |              \
91                                  BR_MS_GPCM |           \
92                                  BR_V)
93
94 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
95                                  OR_GPCM_CSNT | \
96                                  OR_GPCM_ACS_DIV2 | \
97                                  OR_GPCM_SCY_2 | \
98                                  OR_GPCM_TRLX_SET | \
99                                  OR_GPCM_EHTR_CLEAR)
100
101 #define CONFIG_SYS_MAMR         (MxMR_GPL_x4DIS | \
102                                  0x0000c000 | \
103                                  MxMR_WLFx_2X)
104 #endif
105
106 /*
107  * MMU Setup
108  */
109 /* APP1: icache cacheable, but dcache-inhibit and guarded */
110 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | \
111                                  BATL_PP_RW | \
112                                  BATL_MEMCOHERENCE)
113 /* 512M should also include APP2... */
114 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | \
115                                  BATU_BL_256M | \
116                                  BATU_VS | \
117                                  BATU_VP)
118 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | \
119                                  BATL_PP_RW | \
120                                  BATL_CACHEINHIBIT | \
121                                  BATL_GUARDEDSTORAGE)
122 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
123
124 #ifdef CONFIG_KM_DISABLE_APP2
125 #define CONFIG_SYS_IBAT6L       (0)
126 #define CONFIG_SYS_IBAT6U       (0)
127 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
128 #else
129 /* APP2:  icache cacheable, but dcache-inhibit and guarded */
130 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | \
131                                  BATL_PP_RW | \
132                                  BATL_MEMCOHERENCE)
133 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | \
134                                  BATU_BL_256M | \
135                                  BATU_VS | \
136                                  BATU_VP)
137 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | \
138                                  BATL_PP_RW | \
139                                  BATL_CACHEINHIBIT | \
140                                  BATL_GUARDEDSTORAGE)
141 #endif
142 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
143
144 #define CONFIG_SYS_IBAT7L       (0)
145 #define CONFIG_SYS_IBAT7U       (0)
146 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
147 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
148
149 #endif /* __CONFIG_H */