include/configs/tricorder.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2006-2008
   4  * Texas Instruments.
   5  * Richard Woodruff <r-woodruff2@ti.com>
   6  * Syed Mohammed Khasim <x0khasim@ti.com>
   7  *
   8  * (C) Copyright 2012
   9  * Corscience GmbH & Co. KG
  10  * Thomas Weber <weber@corscience.de>
  11  *
  12  * Configuration settings for the Tricorder board.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
  19 /*
  20  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  21  * 64 bytes before this address should be set aside for u-boot.img's
  22  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  23  * other needs.
  24  */
  25
  26 #include <asm/arch/cpu.h>               /* get chip and board defs */
  27 #include <asm/arch/omap.h>
  28
  29 /* Clock Defines */
  30 #define V_OSCK                          26000000 /* Clock output from T2 */
  31 #define V_SCLK                          (V_OSCK >> 1)
  32
  33 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  34 #define CONFIG_SETUP_MEMORY_TAGS
  35 #define CONFIG_INITRD_TAG
  36 #define CONFIG_REVISION_TAG
  37
  38 /* Size of malloc() pool */
  39 #define CONFIG_SYS_MALLOC_LEN           (1024*1024)
  40
  41 /* Hardware drivers */
  42
  43 /* NS16550 Configuration */
  44 #define CONFIG_SYS_NS16550_SERIAL
  45 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  46 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  47
  48 /* select serial console configuration */
  49 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  50 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  51                                         115200}
  52
  53 /* I2C */
  54 #define CONFIG_SYS_I2C
  55
  56
  57 /* EEPROM */
  58 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
  59 #define CONFIG_SYS_EEPROM_BUS_NUM       1
  60
  61 /* TWL4030 */
  62
  63 /* Board NAND Info */
  64 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  65                                                         /* to access nand at */
  66                                                         /* CS0 */
  67 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  68                                                         /* devices */
  69 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  70 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  71
  72 /* needed for ubi */
  73
  74 /* Environment information (this is the common part) */
  75
  76
  77 /* hang() the board on panic() */
  78
  79 /* environment placement (for NAND), is different for FLASHCARD but does not
  80  * harm there */
  81 #define CONFIG_ENV_OFFSET_REDUND        0x2A0000    /* redundant env start */
  82 #define CONFIG_ENV_RANGE                (384 << 10) /* allow badblocks in env */
  83
  84 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
  85  * value can not be used here! */
  86 #define CONFIG_LOADADDR         0x82000000
  87
  88 #define CONFIG_COMMON_ENV_SETTINGS \
  89         "console=ttyO2,115200n8\0" \
  90         "mmcdev=0\0" \
  91         "vram=3M\0" \
  92         "defaultdisplay=lcd\0" \
  93         "kernelopts=mtdoops.mtddev=3\0" \
  94         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  95         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  96         "commonargs=" \
  97                 "setenv bootargs console=${console} " \
  98                 "${mtdparts} " \
  99                 "${kernelopts} " \
 100                 "vt.global_cursor_default=0 " \
 101                 "vram=${vram} " \
 102                 "omapdss.def_disp=${defaultdisplay}\0"
 103
 104 #define CONFIG_BOOTCOMMAND "run autoboot"
 105
 106 /* specific environment settings for different use cases
 107  * FLASHCARD: used to run a rdimage from sdcard to program the device
 108  * 'NORMAL': used to boot kernel from sdcard, nand, ...
 109  *
 110  * The main aim for the FLASHCARD skin is to have an embedded environment
 111  * which will not be influenced by any data already on the device.
 112  */
 113 #ifdef CONFIG_FLASHCARD
 114 /* the rdaddr is 16 MiB before the loadaddr */
 115 #define CONFIG_ENV_RDADDR       "rdaddr=0x81000000\0"
 116
 117 #define CONFIG_EXTRA_ENV_SETTINGS \
 118         CONFIG_COMMON_ENV_SETTINGS \
 119         CONFIG_ENV_RDADDR \
 120         "autoboot=" \
 121         "run commonargs; " \
 122         "setenv bootargs ${bootargs} " \
 123                 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
 124                 "rdinit=/sbin/init; " \
 125         "mmc dev ${mmcdev}; mmc rescan; " \
 126         "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
 127         "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
 128         "bootm ${loadaddr} ${rdaddr}\0"
 129
 130 #else /* CONFIG_FLASHCARD */
 131
 132 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 133
 134 #define CONFIG_EXTRA_ENV_SETTINGS \
 135         CONFIG_COMMON_ENV_SETTINGS \
 136         "mmcargs=" \
 137                 "run commonargs; " \
 138                 "setenv bootargs ${bootargs} " \
 139                 "root=/dev/mmcblk0p2 " \
 140                 "rootwait " \
 141                 "rw\0" \
 142         "nandargs=" \
 143                 "run commonargs; " \
 144                 "setenv bootargs ${bootargs} " \
 145                 "root=ubi0:root " \
 146                 "ubi.mtd=7 " \
 147                 "rootfstype=ubifs " \
 148                 "ro\0" \
 149         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 150         "bootscript=echo Running bootscript from mmc ...; " \
 151                 "source ${loadaddr}\0" \
 152         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 153         "mmcboot=echo Booting from mmc ...; " \
 154                 "run mmcargs; " \
 155                 "bootm ${loadaddr}\0" \
 156         "loaduimage_ubi=ubi part ubi; " \
 157                 "ubifsmount ubi:root; " \
 158                 "ubifsload ${loadaddr} /boot/uImage\0" \
 159         "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
 160         "nandboot=echo Booting from nand ...; " \
 161                 "run nandargs; " \
 162                 "run loaduimage_nand; " \
 163                 "bootm ${loadaddr}\0" \
 164         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 165                         "if run loadbootscript; then " \
 166                                 "run bootscript; " \
 167                         "else " \
 168                                 "if run loaduimage; then " \
 169                                         "run mmcboot; " \
 170                                 "else run nandboot; " \
 171                                 "fi; " \
 172                         "fi; " \
 173                 "else run nandboot; fi\0"
 174
 175 #endif /* CONFIG_FLASHCARD */
 176
 177 /* Miscellaneous configurable options */
 178 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 179
 180 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x00000000)
 181 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 182                                         0x07000000) /* 112 MB */
 183
 184 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 185
 186 /*
 187  * OMAP3 has 12 GP timers, they can be driven by the system clock
 188  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 189  * This rate is divided by a local divisor.
 190  */
 191 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 192 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 193
 194 /*  Physical Memory Map  */
 195 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 196 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 197
 198 /* NAND and environment organization  */
 199 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 200
 201 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 202 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 203 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 204 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 205                                                 CONFIG_SYS_INIT_RAM_SIZE - \
 206                                                 GENERATED_GBL_DATA_SIZE)
 207
 208 /* SRAM config */
 209 #define CONFIG_SYS_SRAM_START           0x40200000
 210 #define CONFIG_SYS_SRAM_SIZE            0x10000
 211
 212 /* Defines for SPL */
 213
 214 #define CONFIG_SPL_NAND_BASE
 215 #define CONFIG_SPL_NAND_DRIVERS
 216 #define CONFIG_SPL_NAND_ECC
 217 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 218 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 219
 220 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 221                                          CONFIG_SPL_TEXT_BASE)
 222
 223 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 224 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 225
 226 /* NAND boot config */
 227 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 228 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 229 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 230 #define CONFIG_SYS_NAND_OOBSIZE         64
 231 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 232 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 233 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
 234                                          13, 14, 16, 17, 18, 19, 20, 21, 22, \
 235                                          23, 24, 25, 26, 27, 28, 30, 31, 32, \
 236                                          33, 34, 35, 36, 37, 38, 39, 40, 41, \
 237                                          42, 44, 45, 46, 47, 48, 49, 50, 51, \
 238                                          52, 53, 54, 55, 56}
 239
 240 #define CONFIG_SYS_NAND_ECCSIZE         512
 241 #define CONFIG_SYS_NAND_ECCBYTES        13
 242 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 243
 244 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 245
 246 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 247 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x100000
 248
 249 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 250 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 251
 252 #define CONFIG_SYS_MEMTEST_SCRATCH      0x81000000
 253 #endif /* __CONFIG_H */