1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2008
5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Syed Mohammed Khasim <x0khasim@ti.com>
9 * Corscience GmbH & Co. KG
10 * Thomas Weber <weber@corscience.de>
12 * Configuration settings for the Tricorder board.
18 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
20 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
21 * 64 bytes before this address should be set aside for u-boot.img's
22 * header. That is 0x800FFFC0--0x80100000 should not be used for any
26 #include <asm/arch/cpu.h> /* get chip and board defs */
27 #include <asm/arch/omap.h>
30 #define V_OSCK 26000000 /* Clock output from T2 */
31 #define V_SCLK (V_OSCK >> 1)
33 #define CONFIG_MISC_INIT_R
35 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
36 #define CONFIG_SETUP_MEMORY_TAGS
37 #define CONFIG_INITRD_TAG
38 #define CONFIG_REVISION_TAG
40 /* Size of malloc() pool */
41 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
43 /* Hardware drivers */
45 /* NS16550 Configuration */
46 #define CONFIG_SYS_NS16550_SERIAL
47 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
48 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
50 /* select serial console configuration */
51 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
52 #define CONFIG_SERIAL3 3
53 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
57 #define CONFIG_SYS_I2C
61 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
62 #define CONFIG_SYS_EEPROM_BUS_NUM 1
65 #define CONFIG_TWL4030_LED
69 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
71 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
72 /* to access nand at */
74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
76 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
77 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
81 /* Environment information (this is the common part) */
84 /* hang() the board on panic() */
86 /* environment placement (for NAND), is different for FLASHCARD but does not
88 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
89 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
90 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
91 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
93 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
94 * value can not be used here! */
95 #define CONFIG_LOADADDR 0x82000000
97 #define CONFIG_COMMON_ENV_SETTINGS \
98 "console=ttyO2,115200n8\0" \
101 "defaultdisplay=lcd\0" \
102 "kernelopts=mtdoops.mtddev=3\0" \
103 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
104 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
106 "setenv bootargs console=${console} " \
109 "vt.global_cursor_default=0 " \
111 "omapdss.def_disp=${defaultdisplay}\0"
113 #define CONFIG_BOOTCOMMAND "run autoboot"
115 /* specific environment settings for different use cases
116 * FLASHCARD: used to run a rdimage from sdcard to program the device
117 * 'NORMAL': used to boot kernel from sdcard, nand, ...
119 * The main aim for the FLASHCARD skin is to have an embedded environment
120 * which will not be influenced by any data already on the device.
122 #ifdef CONFIG_FLASHCARD
123 /* the rdaddr is 16 MiB before the loadaddr */
124 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
126 #define CONFIG_EXTRA_ENV_SETTINGS \
127 CONFIG_COMMON_ENV_SETTINGS \
131 "setenv bootargs ${bootargs} " \
132 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
133 "rdinit=/sbin/init; " \
134 "mmc dev ${mmcdev}; mmc rescan; " \
135 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
136 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
137 "bootm ${loadaddr} ${rdaddr}\0"
139 #else /* CONFIG_FLASHCARD */
141 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
143 #define CONFIG_EXTRA_ENV_SETTINGS \
144 CONFIG_COMMON_ENV_SETTINGS \
147 "setenv bootargs ${bootargs} " \
148 "root=/dev/mmcblk0p2 " \
153 "setenv bootargs ${bootargs} " \
156 "rootfstype=ubifs " \
158 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
159 "bootscript=echo Running bootscript from mmc ...; " \
160 "source ${loadaddr}\0" \
161 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
162 "mmcboot=echo Booting from mmc ...; " \
164 "bootm ${loadaddr}\0" \
165 "loaduimage_ubi=ubi part ubi; " \
166 "ubifsmount ubi:root; " \
167 "ubifsload ${loadaddr} /boot/uImage\0" \
168 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
169 "nandboot=echo Booting from nand ...; " \
171 "run loaduimage_nand; " \
172 "bootm ${loadaddr}\0" \
173 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
174 "if run loadbootscript; then " \
177 "if run loaduimage; then " \
179 "else run nandboot; " \
182 "else run nandboot; fi\0"
184 #endif /* CONFIG_FLASHCARD */
186 /* Miscellaneous configurable options */
187 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
189 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
190 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
191 0x07000000) /* 112 MB */
193 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
196 * OMAP3 has 12 GP timers, they can be driven by the system clock
197 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
198 * This rate is divided by a local divisor.
200 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
201 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
203 /* Physical Memory Map */
204 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
205 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
206 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
208 /* NAND and environment organization */
209 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
211 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
212 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
213 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
214 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
215 CONFIG_SYS_INIT_RAM_SIZE - \
216 GENERATED_GBL_DATA_SIZE)
219 #define CONFIG_SYS_SRAM_START 0x40200000
220 #define CONFIG_SYS_SRAM_SIZE 0x10000
222 /* Defines for SPL */
224 #define CONFIG_SPL_NAND_BASE
225 #define CONFIG_SPL_NAND_DRIVERS
226 #define CONFIG_SPL_NAND_ECC
227 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
228 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
230 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
231 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
232 CONFIG_SPL_TEXT_BASE)
234 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
235 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
237 /* NAND boot config */
238 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
239 #define CONFIG_SYS_NAND_PAGE_COUNT 64
240 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
241 #define CONFIG_SYS_NAND_OOBSIZE 64
242 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
243 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
244 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
245 13, 14, 16, 17, 18, 19, 20, 21, 22, \
246 23, 24, 25, 26, 27, 28, 30, 31, 32, \
247 33, 34, 35, 36, 37, 38, 39, 40, 41, \
248 42, 44, 45, 46, 47, 48, 49, 50, 51, \
251 #define CONFIG_SYS_NAND_ECCSIZE 512
252 #define CONFIG_SYS_NAND_ECCBYTES 13
253 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
255 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
257 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
258 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
260 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
261 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
263 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
264 #endif /* __CONFIG_H */