include/configs/trats.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Samsung Electronics
   4  * Heungjun Kim <riverful.kim@samsung.com>
   5  *
   6  * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
   7  */
   8
   9 #ifndef __CONFIG_TRATS_H
  10 #define __CONFIG_TRATS_H
  11
  12 #include <configs/exynos4-common.h>
  13
  14 #define CONFIG_TRATS
  15
  16 #define CONFIG_TIZEN                    /* TIZEN lib */
  17
  18 #ifndef CONFIG_SYS_L2CACHE_OFF
  19 #define CONFIG_SYS_L2_PL310
  20 #define CONFIG_SYS_PL310_BASE   0x10502000
  21 #endif
  22
  23 /* TRATS has 4 banks of DRAM */
  24 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  25 #define PHYS_SDRAM_1                    CONFIG_SYS_SDRAM_BASE
  26 #define SDRAM_BANK_SIZE                 (256 << 20)     /* 256 MB */
  27
  28 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
  29                                         - GENERATED_GBL_DATA_SIZE)
  30
  31 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20)       /* ram console */
  32
  33 /* Tizen - partitions definitions */
  34 #define PARTS_CSA               "csa-mmc"
  35 #define PARTS_BOOT              "boot"
  36 #define PARTS_QBOOT             "qboot"
  37 #define PARTS_CSC               "csc"
  38 #define PARTS_ROOT              "platform"
  39 #define PARTS_DATA              "data"
  40 #define PARTS_UMS               "ums"
  41
  42 #define PARTS_DEFAULT \
  43         "uuid_disk=${uuid_gpt_disk};" \
  44         "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
  45         "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
  46         "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
  47         "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
  48         "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
  49         "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
  50         "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
  51
  52 #define CONFIG_DFU_ALT \
  53         "u-boot raw 0x80 0x400;" \
  54         "/uImage ext4 0 2;" \
  55         "/modem.bin ext4 0 2;" \
  56         "/exynos4210-trats.dtb ext4 0 2;" \
  57         ""PARTS_CSA" part 0 1;" \
  58         ""PARTS_BOOT" part 0 2;" \
  59         ""PARTS_QBOOT" part 0 3;" \
  60         ""PARTS_CSC" part 0 4;" \
  61         ""PARTS_ROOT" part 0 5;" \
  62         ""PARTS_DATA" part 0 6;" \
  63         ""PARTS_UMS" part 0 7;" \
  64         "params.bin raw 0x38 0x8;" \
  65         "/Image.itb ext4 0 2\0"
  66
  67 #define CONFIG_EXTRA_ENV_SETTINGS \
  68         "bootk=" \
  69                 "run loaduimage;" \
  70                 "if run loaddtb; then " \
  71                         "bootm 0x40007FC0 - ${fdtaddr};" \
  72                 "fi;" \
  73                 "bootm 0x40007FC0;\0" \
  74         "updatebackup=" \
  75                 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
  76                 "mmc dev 0 0\0" \
  77         "updatebootb=" \
  78                 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
  79         "lpj=lpj=3981312\0" \
  80         "nfsboot=" \
  81                 "setenv bootargs root=/dev/nfs rw " \
  82                 "nfsroot=${nfsroot},nolock,tcp " \
  83                 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  84                 "${netmask}:generic:usb0:off ${console} ${meminfo}" \
  85                 "; run bootk\0" \
  86         "ramfsboot=" \
  87                 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
  88                 "${console} ${meminfo} " \
  89                 "initrd=0x43000000,8M ramdisk=8192\0" \
  90         "mmcboot=" \
  91                 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
  92                 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
  93                 "run bootk\0" \
  94         "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
  95         "boottrace=setenv opts initcall_debug; run bootcmd\0" \
  96         "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
  97         "verify=n\0" \
  98         "rootfstype=ext4\0" \
  99         "console=console=ttySAC2,115200n8\0" \
 100         "meminfo=crashkernel=32M@0x50000000\0" \
 101         "nfsroot=/nfsroot/arm\0" \
 102         "bootblock=10\0" \
 103         "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
 104         "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
 105                 "${fdtfile}\0" \
 106         "mmcdev=0\0" \
 107         "mmcbootpart=2\0" \
 108         "mmcrootpart=5\0" \
 109         "opts=always_resume=1\0" \
 110         "partitions=" PARTS_DEFAULT \
 111         "dfu_alt_info=" CONFIG_DFU_ALT \
 112         "spladdr=0x40000100\0" \
 113         "splsize=0x200\0" \
 114         "splfile=falcon.bin\0" \
 115         "spl_export=" \
 116                    "setexpr spl_imgsize ${splsize} + 8 ;" \
 117                    "setenv spl_imgsize 0x${spl_imgsize};" \
 118                    "setexpr spl_imgaddr ${spladdr} - 8 ;" \
 119                    "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
 120                    "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
 121                    "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 122                    "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
 123                    "spl export atags 0x40007FC0;" \
 124                    "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
 125                    "mw.l ${spl_addr_tmp} ${splsize};" \
 126                    "ext4write mmc ${mmcdev}:${mmcbootpart}" \
 127                    " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
 128                    "setenv spl_imgsize;" \
 129                    "setenv spl_imgaddr;" \
 130                    "setenv spl_addr_tmp;\0" \
 131         ENV_ITB \
 132         "fdtaddr=40800000\0" \
 133
 134 /* Falcon mode definitions */
 135 #define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
 136
 137 /* GPT */
 138
 139 /* Security subsystem - enable hw_rand() */
 140 #define CONFIG_EXYNOS_ACE_SHA
 141
 142 /* Common misc for Samsung */
 143 #define CONFIG_MISC_COMMON
 144
 145 /* Download menu - Samsung common */
 146 #define CONFIG_LCD_MENU
 147
 148 /* Download menu - definitions for check keys */
 149 #ifndef __ASSEMBLY__
 150
 151 #define KEY_PWR_PMIC_NAME               "MAX8997_PMIC"
 152 #define KEY_PWR_STATUS_REG              MAX8997_REG_STATUS1
 153 #define KEY_PWR_STATUS_MASK             (1 << 0)
 154 #define KEY_PWR_INTERRUPT_REG           MAX8997_REG_INT1
 155 #define KEY_PWR_INTERRUPT_MASK          (1 << 0)
 156
 157 #define KEY_VOL_UP_GPIO                 EXYNOS4_GPIO_X20
 158 #define KEY_VOL_DOWN_GPIO               EXYNOS4_GPIO_X21
 159 #endif /* __ASSEMBLY__ */
 160
 161 /* LCD console */
 162 #define LCD_BPP                 LCD_COLOR16
 163
 164 /* LCD */
 165 #define CONFIG_FB_ADDR          0x52504000
 166 #define CONFIG_EXYNOS_MIPI_DSIM
 167 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
 168
 169 #endif  /* __CONFIG_H */