1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
6 * Copyright (C) 2009 TechNexion Ltd.
13 * High Level Configuration Options
16 #include <asm/arch/cpu.h> /* get chip and board defs */
17 #include <asm/arch/omap.h>
20 #define V_OSCK 26000000 /* Clock output from T2 */
21 #define V_SCLK (V_OSCK >> 1)
26 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
33 * NS16550 Configuration
35 #define CONFIG_SYS_NS16550_SERIAL
36 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
37 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
40 * select serial console configuration
42 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
44 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
47 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
52 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
56 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
60 * Miscellaneous configurable options
62 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
64 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
68 * AM3517 has 12 GP timers, they can be driven by the system clock
69 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
70 * This rate is divided by a local divisor.
72 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
73 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
78 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
79 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
82 * FLASH and environment organization
85 /* **** PISMO SUPPORT *** */
87 /* Redundant Environment */
88 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
90 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
91 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
92 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
93 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
94 CONFIG_SYS_INIT_RAM_SIZE - \
95 GENERATED_GBL_DATA_SIZE)
98 * ethernet support, EMAC
101 #define CONFIG_NET_RETRY_COUNT 10
103 /* Defines for SPL */
104 #define CONFIG_SPL_CONSOLE
105 #define CONFIG_SPL_NAND_SOFTECC
106 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
108 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
109 CONFIG_SPL_TEXT_BASE)
110 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
112 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
113 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
114 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
115 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
117 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
120 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
121 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
123 /* RAW SD card / eMMC */
124 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
125 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
126 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
128 /* NAND boot config */
129 #define CONFIG_SYS_NAND_PAGE_COUNT 64
130 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
131 #define CONFIG_SYS_NAND_OOBSIZE 64
132 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
133 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
134 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
135 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
136 48, 49, 50, 51, 52, 53, 54, 55,\
137 56, 57, 58, 59, 60, 61, 62, 63}
138 #define CONFIG_SYS_NAND_ECCSIZE 256
139 #define CONFIG_SYS_NAND_ECCBYTES 3
140 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
142 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
144 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
145 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
147 /* Setup MTD for NAND on the SOM */
149 #define CONFIG_TAM3517_SETTINGS \
151 "nandargs=setenv bootargs root=${nandroot} " \
152 "rootfstype=${nandrootfstype}\0" \
153 "nfsargs=setenv bootargs root=/dev/nfs rw " \
154 "nfsroot=${serverip}:${rootpath}\0" \
155 "ramargs=setenv bootargs root=/dev/ram rw\0" \
156 "addip_sta=setenv bootargs ${bootargs} " \
157 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
158 ":${hostname}:${netdev}:off panic=1\0" \
159 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
160 "addip=if test -n ${ipdyn};then run addip_dyn;" \
161 "else run addip_sta;fi\0" \
162 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
163 "addtty=setenv bootargs ${bootargs}" \
164 " console=ttyO0,${baudrate}\0" \
165 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
166 "loadaddr=82000000\0" \
167 "kernel_addr_r=82000000\0" \
168 "hostname=" CONFIG_HOSTNAME "\0" \
169 "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
170 "flash_self=run ramargs addip addtty addmtd addmisc;" \
171 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
172 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
173 "bootm ${kernel_addr}\0" \
174 "nandboot=run nandargs addip addtty addmtd addmisc;" \
175 "nand read ${kernel_addr_r} kernel\0" \
176 "bootm ${kernel_addr_r}\0" \
177 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
178 "run nfsargs addip addtty addmtd addmisc;" \
179 "bootm ${kernel_addr_r}\0" \
180 "net_self=if run net_self_load;then " \
181 "run ramargs addip addtty addmtd addmisc;" \
182 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
183 "else echo Images not loades;fi\0" \
184 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
185 "load=tftp ${loadaddr} ${u-boot}\0" \
186 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
187 "mlo=" CONFIG_HOSTNAME "/MLO\0" \
188 "uboot_addr=0x80000\0" \
189 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
190 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
191 "updatemlo=nandecc hw;nand erase 0 20000;" \
192 "nand write ${loadaddr} 0 20000\0" \
193 "upd=if run load;then echo Updating u-boot;if run update;" \
194 "then echo U-Boot updated;" \
195 "else echo Error updating u-boot !;" \
196 "echo Board without bootloader !!;" \
198 "else echo U-Boot not downloaded..exiting;fi\0" \
201 * this is common code for all TAM3517 boards.
202 * MAC address is stored from manufacturer in
205 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
207 * The I2C EEPROM on the TAM3517 contains
208 * mac address and production data
210 struct tam3517_module_info {
215 * bit 0~47 : sequence number
216 * bit 48~55 : week of year, from 0.
219 unsigned long long sequence_number;
222 * bit 0~7 : revision fixed
223 * bit 8~15 : revision major
226 unsigned int revision;
227 unsigned char eth_addr[4][8];
228 unsigned char _rev[100];
231 #define TAM3517_READ_EEPROM(info, ret) \
233 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
234 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
235 (void *)info, sizeof(*info))) \
241 #define TAM3517_READ_MAC_FROM_EEPROM(info) \
243 char buf[80], ethname[20]; \
245 memset(buf, 0, sizeof(buf)); \
246 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
247 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
248 (info)->eth_addr[i][5], \
249 (info)->eth_addr[i][4], \
250 (info)->eth_addr[i][3], \
251 (info)->eth_addr[i][2], \
252 (info)->eth_addr[i][1], \
253 (info)->eth_addr[i][0]); \
256 sprintf(ethname, "eth%daddr", i); \
258 strcpy(ethname, "ethaddr"); \
259 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
260 env_set(ethname, buf); \
264 /* The following macros are taken from Technexion's documentation */
265 #define TAM3517_sequence_number(info) \
266 ((info)->sequence_number % 0x1000000000000LL)
267 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
268 #define TAM3517_year(info) ((info)->sequence_number >> 56)
269 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
270 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
271 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
273 #define TAM3517_PRINT_SOM_INFO(info) \
275 printf("Vendor:%s\n", (info)->customer); \
276 printf("SOM: %s\n", (info)->product); \
277 printf("SeqNr: %02llu%02llu%012llu\n", \
278 TAM3517_year(info), \
279 TAM3517_week_of_year(info), \
280 TAM3517_sequence_number(info)); \
281 printf("Rev: TN%u %u.%u\n", \
282 TAM3517_revision_tn(info), \
283 TAM3517_revision_major(info), \
284 TAM3517_revision_fixed(info)); \
289 #endif /* __TAM3517_H */