include/configs/socrates.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2008
   4  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   5  *
   6  * Wolfgang Denk <wd@denx.de>
   7  * Copyright 2004 Freescale Semiconductor.
   8  * (C) Copyright 2002,2003 Motorola,Inc.
   9  * Xianghua Xiao <X.Xiao@motorola.com>
  10  */
  11
  12 /*
  13  * Socrates
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SOCRATES         1
  21
  22 /*
  23  * Only possible on E500 Version 2 or newer cores.
  24  */
  25
  26 /*
  27  * sysclk for MPC85xx
  28  *
  29  * Two valid values are:
  30  *    33000000
  31  *    66000000
  32  *
  33  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  34  * is likely the desired value here, so that is now the default.
  35  * The board, however, can run at 66MHz.  In any event, this value
  36  * must match the settings of some switches.  Details can be found
  37  * in the README.mpc85xxads.
  38  */
  39
  40 /*
  41  * These can be toggled for performance analysis, otherwise use default.
  42  */
  43 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
  44
  45 #define CFG_SYS_INIT_DBCR DBCR_IDM              /* Enable Debug Exceptions      */
  46
  47 #undef  CFG_SYS_DRAM_TEST                       /* memory test, takes time      */
  48
  49 #define CFG_SYS_CCSRBAR         0xE0000000
  50 #define CFG_SYS_CCSRBAR_PHYS_LOW        CFG_SYS_CCSRBAR
  51
  52 /* DDR Setup */
  53
  54 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  55
  56 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  57 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  58 #define CONFIG_VERY_BIG_RAM
  59
  60 /* I2C addresses of SPD EEPROMs */
  61 #define SPD_EEPROM_ADDRESS      0x50    /* CTLR 0 DIMM 0 */
  62
  63
  64 /* Hardcoded values, to use instead of SPD */
  65 #define CFG_SYS_DDR_CS0_BNDS            0x0000000f
  66 #define CFG_SYS_DDR_CS0_CONFIG          0x80010102
  67 #define CFG_SYS_DDR_TIMING_0            0x00260802
  68 #define CFG_SYS_DDR_TIMING_1            0x3935D322
  69 #define CFG_SYS_DDR_TIMING_2            0x14904CC8
  70 #define CFG_SYS_DDR_MODE                        0x00480432
  71 #define CFG_SYS_DDR_INTERVAL            0x030C0100
  72 #define CFG_SYS_DDR_CONFIG_2            0x04400000
  73 #define CFG_SYS_DDR_CONFIG                      0xC3008000
  74 #define CFG_SYS_DDR_CLK_CONTROL         0x03800000
  75 #define CFG_SYS_SDRAM_SIZE                      256 /* in Megs */
  76
  77 /*
  78  * Flash on the LocalBus
  79  */
  80 #define CFG_SYS_FLASH0          0xFE000000
  81 #define CFG_SYS_FLASH1          0xFC000000
  82 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH1, CFG_SYS_FLASH0 }
  83
  84 #define CFG_SYS_LBC_FLASH_BASE  CFG_SYS_FLASH1  /* Localbus flash start */
  85 #define CFG_SYS_FLASH_BASE              CFG_SYS_LBC_FLASH_BASE /* start of FLASH        */
  86
  87 #define CFG_SYS_LBC_LCRR                0x00030004    /* LB clock ratio reg     */
  88 #define CFG_SYS_LBC_LBCR                0x00000000    /* LB config reg          */
  89 #define CFG_SYS_LBC_LSRT                0x20000000    /* LB sdram refresh timer */
  90 #define CFG_SYS_LBC_MRTPR               0x20000000    /* LB refresh timer presc.*/
  91
  92 #define CFG_SYS_INIT_RAM_ADDR   0xe4010000      /* Initial RAM address  */
  93 #define CFG_SYS_INIT_RAM_SIZE   0x4000          /* Size used area in RAM*/
  94
  95 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  96
  97 /* FPGA and NAND */
  98 #define CFG_SYS_FPGA_BASE               0xc0000000
  99 #define CFG_SYS_FPGA_SIZE               0x00100000      /* 1 MB         */
 100
 101 #define CFG_SYS_NAND_BASE               (CFG_SYS_FPGA_BASE + 0x70)
 102
 103 /* LIME GDC */
 104 #define CFG_SYS_LIME_BASE               0xc8000000
 105
 106 /*
 107  * General PCI
 108  * Memory space is mapped 1-1.
 109  */
 110
 111 #define CFG_SYS_PCI1_MEM_PHYS   0x80000000
 112 #define CFG_SYS_PCI1_IO_PHYS    0xE2000000
 113
 114 #define CONFIG_TSEC1    1
 115 #define CONFIG_TSEC1_NAME       "TSEC0"
 116 #define CONFIG_TSEC3    1
 117 #define CONFIG_TSEC3_NAME       "TSEC1"
 118 #undef CONFIG_MPC85XX_FEC
 119
 120 #define TSEC1_PHY_ADDR          0
 121 #define TSEC3_PHY_ADDR          1
 122
 123 #define TSEC1_PHYIDX            0
 124 #define TSEC3_PHYIDX            0
 125 #define TSEC1_FLAGS             TSEC_GIGABIT
 126 #define TSEC3_FLAGS             TSEC_GIGABIT
 127
 128 /* Options are: TSEC[0,1] */
 129
 130 /*
 131  * Miscellaneous configurable options
 132  */
 133
 134 /*
 135  * For booting Linux, the board info and command line data
 136  * have to be in the first 8 MB of memory, since this is
 137  * the maximum mapped by the Linux kernel during initialization.
 138  */
 139 #define CFG_SYS_BOOTMAPSZ       (8 << 20)       /* Initial Memory map for Linux */
 140
 141
 142 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 143         "netdev=eth0\0"                                                 \
 144         "consdev=ttyS0\0"                                               \
 145         "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
 146         "bootfile=/home/tftp/syscon3/uImage\0"                          \
 147         "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
 148         "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
 149         "uboot_addr=FFF60000\0"                                         \
 150         "kernel_addr=FE000000\0"                                        \
 151         "fdt_addr=FE1E0000\0"                                           \
 152         "ramdisk_addr=FE200000\0"                                       \
 153         "fdt_addr_r=B00000\0"                                           \
 154         "kernel_addr_r=200000\0"                                        \
 155         "ramdisk_addr_r=400000\0"                                       \
 156         "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
 157         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 158         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 159                 "nfsroot=$serverip:$rootpath\0"                         \
 160         "addcons=setenv bootargs $bootargs "                            \
 161                 "console=$consdev,$baudrate\0"                          \
 162         "addip=setenv bootargs $bootargs "                              \
 163                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 164                 ":$hostname:$netdev:off panic=1\0"                      \
 165         "boot_nor=run ramargs addcons;"                                 \
 166                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 167         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 168                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 169                 "run nfsargs addip addcons;"                            \
 170                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 171         "update_uboot=tftp 100000 ${uboot_file};"                       \
 172                 "protect off fff60000 ffffffff;"                        \
 173                 "era fff60000 ffffffff;"                                \
 174                 "cp.b 100000 fff60000 ${filesize};"                     \
 175                 "setenv filesize;saveenv\0"                             \
 176         "update_kernel=tftp 100000 ${bootfile};"                        \
 177                 "era fe000000 fe1dffff;"                                \
 178                 "cp.b 100000 fe000000 ${filesize};"                     \
 179                 "setenv filesize;saveenv\0"                             \
 180         "update_fdt=tftp 100000 ${fdt_file};"                           \
 181                 "era fe1e0000 fe1fffff;"                                \
 182                 "cp.b 100000 fe1e0000 ${filesize};"                     \
 183                 "setenv filesize;saveenv\0"                             \
 184         "update_initrd=tftp 100000 ${initrd_file};"                     \
 185                 "era fe200000 fe9fffff;"                                \
 186                 "cp.b 100000 fe200000 ${filesize};"                     \
 187                 "setenv filesize;saveenv\0"                             \
 188         "clean_data=era fea00000 fff5ffff\0"                            \
 189         "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
 190         "load_usb=usb start;"                                           \
 191                 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
 192         "boot_usb=run load_usb usbargs addcons;"                        \
 193                 "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
 194                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 195         ""
 196
 197 /* pass open firmware flat tree */
 198
 199 #endif  /* __CONFIG_H */