include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18 #define CPU_RELEASE_ADDR                0xFFD12210
  19
  20 /*
  21  * U-Boot console configurations
  22  */
  23
  24 /* Extend size of kernel image for uncompression */
  25 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  26
  27 /*
  28  * U-Boot run time memory configurations
  29  */
  30 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  31 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  32 #ifdef CONFIG_SPL_BUILD
  33 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  34                                         + CONFIG_SYS_INIT_RAM_SIZE \
  35                                         - SOC64_HANDOFF_SIZE)
  36 #else
  37 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  38                                         + 0x100000)
  39 #endif
  40 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  41
  42 /*
  43  * U-Boot environment configurations
  44  */
  45
  46 /*
  47  * QSPI support
  48  */
  49  #ifdef CONFIG_CADENCE_QSPI
  50 /* Enable it if you want to use dual-stacked mode */
  51 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  52
  53 /* Flash device info */
  54
  55 #ifndef CONFIG_SPL_BUILD
  56 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  57 #endif /* CONFIG_SPL_BUILD */
  58
  59 #endif /* CONFIG_CADENCE_QSPI */
  60
  61 /*
  62  * Environment variable
  63  */
  64 #define CONFIG_EXTRA_ENV_SETTINGS \
  65         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  66         "bootfile=" CONFIG_BOOTFILE "\0" \
  67         "fdt_addr=8000000\0" \
  68         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  69         "mmcroot=/dev/mmcblk0p2\0" \
  70         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  71                 " root=${mmcroot} rw rootwait;" \
  72                 "booti ${loadaddr} - ${fdt_addr}\0" \
  73         "mmcload=mmc rescan;" \
  74                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  75                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  76         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  77                 " root=${mmcroot} rw rootwait;" \
  78                 "bootm ${loadaddr}\0" \
  79         "mmcfitload=mmc rescan;" \
  80                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  81         "linux_qspi_enable=if sf probe; then " \
  82                 "echo Enabling QSPI at Linux DTB...;" \
  83                 "fdt addr ${fdt_addr}; fdt resize;" \
  84                 "fdt set /soc/spi@ff8d2000 status okay;" \
  85                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  86                 " ${qspi_clock}; fi; \0" \
  87         "scriptaddr=0x02100000\0" \
  88         "scriptfile=u-boot.scr\0" \
  89         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  90                    "then source ${scriptaddr}; fi\0" \
  91         "socfpga_legacy_reset_compat=1\0"
  92
  93 /*
  94  * External memory configurations
  95  */
  96 #define PHYS_SDRAM_1                    0x0
  97 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
  98 #define CONFIG_SYS_SDRAM_BASE           0
  99
 100 /*
 101  * Serial / UART configurations
 102  */
 103 #define CONFIG_SYS_NS16550_CLK          100000000
 104 #define CONFIG_SYS_NS16550_MEM32
 105
 106 /*
 107  * SDMMC configurations
 108  */
 109 #ifdef CONFIG_CMD_MMC
 110 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 111 #endif
 112 /*
 113  * Flash configurations
 114  */
 115
 116 /* Ethernet on SoC (EMAC) */
 117 #if defined(CONFIG_CMD_NET)
 118 #define CONFIG_DW_ALTDESCRIPTOR
 119 #endif /* CONFIG_CMD_NET */
 120
 121 /*
 122  * L4 Watchdog
 123  */
 124 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 125 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 126 #ifndef __ASSEMBLY__
 127 unsigned int cm_get_l4_sys_free_clk_hz(void);
 128 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 129 #endif
 130 #else
 131 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 132 #endif
 133
 134 /*
 135  * SPL memory layout
 136  *
 137  * On chip RAM
 138  * 0xFFE0_0000 ...... Start of OCRAM
 139  * SPL code, rwdata
 140  * empty space
 141  * 0xFFEx_xxxx ...... Top of stack (grows down)
 142  * 0xFFEy_yyyy ...... Global Data
 143  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 144  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 145  * 0xFFE3_FFFF ...... End of OCRAM
 146  *
 147  * SDRAM
 148  * 0x0000_0000 ...... Start of SDRAM_1
 149  * unused / empty space for image loading
 150  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 151  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 152  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 153  *
 154  */
 155 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 156 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 157 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 158 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 159 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 160                                         - CONFIG_SPL_BSS_MAX_SIZE)
 161 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 162 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 163                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 164
 165 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */