include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_SYS_LOAD_ADDR                    0x2000000
  19 #define CONFIG_REMAKE_ELF
  20 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  21 #define CPU_RELEASE_ADDR                0xFFD12210
  22
  23 /*
  24  * U-Boot console configurations
  25  */
  26 #define CONFIG_SYS_MAXARGS              64
  27 #define CONFIG_SYS_CBSIZE               2048
  28 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  29                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  30 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  31
  32 /* Extend size of kernel image for uncompression */
  33 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  34
  35 /*
  36  * U-Boot run time memory configurations
  37  */
  38 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  39 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  42                                         + CONFIG_SYS_INIT_RAM_SIZE \
  43                                         - SOC64_HANDOFF_SIZE)
  44 #else
  45 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  46                                         + 0x100000)
  47 #endif
  48 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  49 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  50
  51 /*
  52  * U-Boot environment configurations
  53  */
  54
  55 /*
  56  * QSPI support
  57  */
  58  #ifdef CONFIG_CADENCE_QSPI
  59 /* Enable it if you want to use dual-stacked mode */
  60 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  61
  62 /* Flash device info */
  63
  64 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  65
  66 #ifndef CONFIG_SPL_BUILD
  67 #define CONFIG_MTD_PARTITIONS
  68 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  69 #endif /* CONFIG_SPL_BUILD */
  70
  71 #ifndef __ASSEMBLY__
  72 unsigned int cm_get_qspi_controller_clk_hz(void);
  73 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  74 #endif
  75
  76 #endif /* CONFIG_CADENCE_QSPI */
  77
  78 /*
  79  * Environment variable
  80  */
  81
  82 #ifdef CONFIG_FIT
  83 #define CONFIG_BOOTFILE "kernel.itb"
  84 #else
  85 #define CONFIG_BOOTFILE "Image"
  86 #endif
  87
  88 #define CONFIG_EXTRA_ENV_SETTINGS \
  89         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  90         "bootfile=" CONFIG_BOOTFILE "\0" \
  91         "fdt_addr=8000000\0" \
  92         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  93         "mmcroot=/dev/mmcblk0p2\0" \
  94         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  95                 " root=${mmcroot} rw rootwait;" \
  96                 "booti ${loadaddr} - ${fdt_addr}\0" \
  97         "mmcload=mmc rescan;" \
  98                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  99                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 100         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
 101                 " root=${mmcroot} rw rootwait;" \
 102                 "bootm ${loadaddr}\0" \
 103         "mmcfitload=mmc rescan;" \
 104                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 105         "linux_qspi_enable=if sf probe; then " \
 106                 "echo Enabling QSPI at Linux DTB...;" \
 107                 "fdt addr ${fdt_addr}; fdt resize;" \
 108                 "fdt set /soc/spi@ff8d2000 status okay;" \
 109                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 110                 " ${qspi_clock}; fi; \0" \
 111         "scriptaddr=0x02100000\0" \
 112         "scriptfile=u-boot.scr\0" \
 113         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 114                    "then source ${scriptaddr}; fi\0" \
 115         "socfpga_legacy_reset_compat=1\0"
 116
 117 /*
 118  * External memory configurations
 119  */
 120 #define PHYS_SDRAM_1                    0x0
 121 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 122 #define CONFIG_SYS_SDRAM_BASE           0
 123
 124 /*
 125  * Serial / UART configurations
 126  */
 127 #define CONFIG_SYS_NS16550_CLK          100000000
 128 #define CONFIG_SYS_NS16550_MEM32
 129
 130 /*
 131  * Timer & watchdog configurations
 132  */
 133 #define COUNTER_FREQUENCY               400000000
 134
 135 /*
 136  * SDMMC configurations
 137  */
 138 #ifdef CONFIG_CMD_MMC
 139 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 140 #endif
 141 /*
 142  * Flash configurations
 143  */
 144 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 145
 146 /* Ethernet on SoC (EMAC) */
 147 #if defined(CONFIG_CMD_NET)
 148 #define CONFIG_DW_ALTDESCRIPTOR
 149 #endif /* CONFIG_CMD_NET */
 150
 151 /*
 152  * L4 Watchdog
 153  */
 154 #ifndef CONFIG_SPL_BUILD
 155 #undef CONFIG_HW_WATCHDOG
 156 #undef CONFIG_DESIGNWARE_WATCHDOG
 157 #endif
 158 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 159 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 160 #ifndef __ASSEMBLY__
 161 unsigned int cm_get_l4_sys_free_clk_hz(void);
 162 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 163 #endif
 164 #else
 165 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 166 #endif
 167
 168 /*
 169  * SPL memory layout
 170  *
 171  * On chip RAM
 172  * 0xFFE0_0000 ...... Start of OCRAM
 173  * SPL code, rwdata
 174  * empty space
 175  * 0xFFEx_xxxx ...... Top of stack (grows down)
 176  * 0xFFEy_yyyy ...... Global Data
 177  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 178  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 179  * 0xFFE3_FFFF ...... End of OCRAM
 180  *
 181  * SDRAM
 182  * 0x0000_0000 ...... Start of SDRAM_1
 183  * unused / empty space for image loading
 184  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 185  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 186  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 187  *
 188  */
 189 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 190 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 191 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 192 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 193 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 194                                         - CONFIG_SPL_BSS_MAX_SIZE)
 195 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 196 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 197                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 198
 199 /* SPL SDMMC boot support */
 200 #ifdef CONFIG_SPL_LOAD_FIT
 201 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 202 #else
 203 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 204 #endif
 205
 206 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */