1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
8 #include <linux/stringify.h>
11 * Memory configurations
13 #define PHYS_SDRAM_1 0x0
14 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
15 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
16 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
17 #define CONFIG_SPL_PAD_TO 0x10000
18 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
19 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
20 #define CONFIG_SPL_PAD_TO 0x40000
21 /* SPL memory allocation configuration, this is for FAT implementation */
22 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
23 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
25 #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
26 CONFIG_SYS_SPL_MALLOC_SIZE)
27 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
28 CONFIG_SYS_INIT_RAM_SIZE)
32 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
33 * SRAM as bootcounter storage. Make sure to not put the stack directly
34 * at this address to not overwrite the bootcounter by checking, if the
35 * bootcounter address is located in the internal SRAM.
37 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
38 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
39 CONFIG_SYS_INIT_RAM_SIZE)))
40 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
42 #define CONFIG_SPL_STACK \
43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
47 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
48 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
49 * in U-Boot pre-reloc is higher than in SPL.
51 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
52 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
54 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
57 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
60 * U-Boot general configurations
62 /* Print buffer size */
67 #define CONFIG_SYS_L2_PL310
68 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
71 * Ethernet on SoC (EMAC)
74 #define CONFIG_DW_ALTDESCRIPTOR
80 #ifdef CONFIG_CMD_FPGA
81 #define CONFIG_FPGA_COUNT 1
88 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
89 #define CONFIG_SYS_TIMER_COUNTS_DOWN
90 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
91 #ifndef CONFIG_SYS_TIMER_RATE
92 #define CONFIG_SYS_TIMER_RATE 25000000
99 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
100 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
105 #ifdef CONFIG_CMD_MMC
107 /* using smaller max blk cnt to avoid flooding the limited stack we have */
108 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
114 #ifdef CONFIG_NAND_DENALI
115 #define CONFIG_SYS_MAX_NAND_DEVICE 1
116 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
117 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
125 * USB Gadget (DFU, UMS)
127 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
128 #define DFU_DEFAULT_POLL_TIMEOUT 300
131 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
132 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
139 /* Environment for SDMMC boot */
141 /* Environment for QSPI boot */
146 * SRAM Memory layout for gen 5:
148 * 0xFFFF_0000 ...... Start of SRAM
149 * 0xFFFF_xxxx ...... Top of stack (grows down)
150 * 0xFFFF_yyyy ...... Global Data
151 * 0xFFFF_zzzz ...... Malloc area
152 * 0xFFFF_FFFF ...... End of SRAM
154 * SRAM Memory layout for Arria 10:
155 * 0xFFE0_0000 ...... Start of SRAM (bottom)
156 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
157 * 0xFFEy_yyyy ...... Global Data
158 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
159 * 0xFFE3_FFFF ...... End of SRAM (top)
161 #ifndef CONFIG_SPL_TEXT_BASE
162 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
165 /* SPL SDMMC boot support */
166 #ifdef CONFIG_SPL_MMC
167 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
168 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
172 /* SPL QSPI boot support */
174 /* SPL NAND boot support */
176 /* Extra Environment */
177 #ifndef CONFIG_SPL_BUILD
179 #ifdef CONFIG_CMD_DHCP
180 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
182 #define BOOT_TARGET_DEVICES_DHCP(func)
185 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
186 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
188 #define BOOT_TARGET_DEVICES_PXE(func)
191 #ifdef CONFIG_CMD_MMC
192 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
194 #define BOOT_TARGET_DEVICES_MMC(func)
197 #define BOOT_TARGET_DEVICES(func) \
198 BOOT_TARGET_DEVICES_MMC(func) \
199 BOOT_TARGET_DEVICES_PXE(func) \
200 BOOT_TARGET_DEVICES_DHCP(func)
202 #include <config_distro_bootcmd.h>
204 #ifndef CONFIG_EXTRA_ENV_SETTINGS
205 #define CONFIG_EXTRA_ENV_SETTINGS \
206 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
207 "bootm_size=0xa000000\0" \
208 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
209 "fdt_addr_r=0x02000000\0" \
210 "scriptaddr=0x02100000\0" \
211 "pxefile_addr_r=0x02200000\0" \
212 "ramdisk_addr_r=0x02300000\0" \
213 "socfpga_legacy_reset_compat=1\0" \
219 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */