include/configs/sbc8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * WindRiver SBC8349 U-Boot configuration file.
   4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   5  *
   6  * Paul Gortmaker <paul.gortmaker@windriver.com>
   7  * Based on the MPC8349EMDS config.
   8  */
   9
  10 /*
  11  * sbc8349 board configuration file.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  */
  20 #define CONFIG_E300             1       /* E300 Family */
  21
  22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  23 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  24
  25 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  26
  27 /*
  28  * DDR Setup
  29  */
  30 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  31 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  32 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  33 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  34
  35 /*
  36  * 32-bit data path mode.
  37  *
  38  * Please note that using this mode for devices with the real density of 64-bit
  39  * effectively reduces the amount of available memory due to the effect of
  40  * wrapping around while translating address to row/columns, for example in the
  41  * 256MB module the upper 128MB get aliased with contents of the lower
  42  * 128MB); normally this define should be used for devices with real 32-bit
  43  * data path.
  44  */
  45 #undef CONFIG_DDR_32BIT
  46
  47 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
  48 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  49                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  50 #define CONFIG_DDR_2T_TIMING
  51
  52 #if defined(CONFIG_SPD_EEPROM)
  53 /*
  54  * Determine DDR configuration from I2C interface.
  55  */
  56 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  57
  58 #else
  59 /*
  60  * Manually set up DDR parameters
  61  * NB: manual DDR setup untested on sbc834x
  62  */
  63 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  64 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  65                                         | CSCONFIG_ROW_BIT_13 \
  66                                         | CSCONFIG_COL_BIT_10)
  67 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  68 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  69 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  70 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  71
  72 #if defined(CONFIG_DDR_32BIT)
  73 /* set burst length to 8 for 32-bit data path */
  74                                 /* DLL,normal,seq,4/2.5, 8 burst len */
  75 #define CONFIG_SYS_DDR_MODE     0x00000023
  76 #else
  77 /* the default burst length is 4 - for 64-bit data path */
  78                                 /* DLL,normal,seq,4/2.5, 4 burst len */
  79 #define CONFIG_SYS_DDR_MODE     0x00000022
  80 #endif
  81 #endif
  82
  83 /*
  84  * SDRAM on the Local Bus
  85  */
  86 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
  87 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
  88
  89 /*
  90  * FLASH on the Local Bus
  91  */
  92 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
  93 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
  94
  95
  96 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  97 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
  98
  99 #undef CONFIG_SYS_FLASH_CHECKSUM
 100 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 101 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 102
 103 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 104
 105 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 106 #define CONFIG_SYS_RAMBOOT
 107 #else
 108 #undef  CONFIG_SYS_RAMBOOT
 109 #endif
 110
 111 #define CONFIG_SYS_INIT_RAM_LOCK        1
 112                                         /* Initial RAM address */
 113 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 114                                         /* Size of used area in RAM*/
 115 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 116
 117 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 118                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 119 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 120
 121 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 122 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 123
 124 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 125
 126 /*
 127  * Serial Port
 128  */
 129 #define CONFIG_SYS_NS16550_SERIAL
 130 #define CONFIG_SYS_NS16550_REG_SIZE    1
 131 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 132
 133 #define CONFIG_SYS_BAUDRATE_TABLE  \
 134                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 135
 136 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 137 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 138
 139 /* I2C */
 140 #define CONFIG_SYS_I2C
 141 #define CONFIG_SYS_I2C_FSL
 142 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 143 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 144 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 145 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 146 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 147 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 148 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 149 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 150
 151 /* TSEC */
 152 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 153 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 154 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 155 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 156
 157 /*
 158  * General PCI
 159  * Addresses are mapped 1-1.
 160  */
 161 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 162 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 163 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 164 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 165 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 166 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 167 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 168 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 169 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 170
 171 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 172 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 173 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 174 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 175 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 176 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 177 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 178 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 179 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 180
 181 #if defined(CONFIG_PCI)
 182
 183 #undef CONFIG_EEPRO100
 184 #undef CONFIG_TULIP
 185
 186 #if !defined(CONFIG_PCI_PNP)
 187         #define PCI_ENET0_IOADDR        0xFIXME
 188         #define PCI_ENET0_MEMADDR       0xFIXME
 189         #define PCI_IDSEL_NUMBER        0xFIXME
 190 #endif
 191
 192 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 193 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 194
 195 #endif  /* CONFIG_PCI */
 196
 197 /*
 198  * TSEC configuration
 199  */
 200
 201 #if defined(CONFIG_TSEC_ENET)
 202
 203 #define CONFIG_TSEC1    1
 204 #define CONFIG_TSEC1_NAME       "TSEC0"
 205 #define CONFIG_TSEC2    1
 206 #define CONFIG_TSEC2_NAME       "TSEC1"
 207 #define CONFIG_PHY_BCM5421S     1
 208 #define TSEC1_PHY_ADDR          0x19
 209 #define TSEC2_PHY_ADDR          0x1a
 210 #define TSEC1_PHYIDX            0
 211 #define TSEC2_PHYIDX            0
 212 #define TSEC1_FLAGS             TSEC_GIGABIT
 213 #define TSEC2_FLAGS             TSEC_GIGABIT
 214
 215 /* Options are: TSEC[0-1] */
 216 #define CONFIG_ETHPRIME         "TSEC0"
 217
 218 #endif  /* CONFIG_TSEC_ENET */
 219
 220 /*
 221  * Environment
 222  */
 223 #ifndef CONFIG_SYS_RAMBOOT
 224 /* Address and size of Redundant Environment Sector     */
 225 #endif
 226
 227 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 228 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 229
 230 /*
 231  * BOOTP options
 232  */
 233 #define CONFIG_BOOTP_BOOTFILESIZE
 234
 235 /*
 236  * Command line configuration.
 237  */
 238
 239 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 240
 241 /*
 242  * Miscellaneous configurable options
 243  */
 244 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 245
 246 /*
 247  * For booting Linux, the board info and command line data
 248  * have to be in the first 256 MB of memory, since this is
 249  * the maximum mapped by the Linux kernel during initialization.
 250  */
 251                                 /* Initial Memory map for Linux*/
 252 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 253
 254 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 255
 256 /* System IO Config */
 257 #define CONFIG_SYS_SICRH 0
 258 #define CONFIG_SYS_SICRL SICRL_LDP_A
 259
 260 #ifdef CONFIG_PCI
 261 #define CONFIG_PCI_INDIRECT_BRIDGE
 262 #endif
 263
 264 #if defined(CONFIG_CMD_KGDB)
 265 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 266 #endif
 267
 268 /*
 269  * Environment Configuration
 270  */
 271 #define CONFIG_ENV_OVERWRITE
 272
 273 #if defined(CONFIG_TSEC_ENET)
 274 #define CONFIG_HAS_ETH0
 275 #define CONFIG_HAS_ETH1
 276 #endif
 277
 278 #define CONFIG_HOSTNAME         "SBC8349"
 279 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 280 #define CONFIG_BOOTFILE         "uImage"
 281
 282                                 /* default location for tftp and bootm */
 283 #define CONFIG_LOADADDR         800000
 284
 285 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 286         "netdev=eth0\0"                                                 \
 287         "hostname=sbc8349\0"                                            \
 288         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 289                 "nfsroot=${serverip}:${rootpath}\0"                     \
 290         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 291         "addip=setenv bootargs ${bootargs} "                            \
 292                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 293                 ":${hostname}:${netdev}:off panic=1\0"                  \
 294         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 295         "flash_nfs=run nfsargs addip addtty;"                           \
 296                 "bootm ${kernel_addr}\0"                                \
 297         "flash_self=run ramargs addip addtty;"                          \
 298                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 299         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 300                 "bootm\0"                                               \
 301         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 302         "update=protect off ff800000 ff83ffff; "                        \
 303                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 304         "upd=run load update\0"                                         \
 305         "fdtaddr=780000\0"                                              \
 306         "fdtfile=sbc8349.dtb\0"                                         \
 307         ""
 308
 309 #define CONFIG_NFSBOOTCOMMAND                                           \
 310         "setenv bootargs root=/dev/nfs rw "                             \
 311                 "nfsroot=$serverip:$rootpath "                          \
 312                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 313                                                         "$netdev:off "  \
 314                 "console=$consoledev,$baudrate $othbootargs;"           \
 315         "tftp $loadaddr $bootfile;"                                     \
 316         "tftp $fdtaddr $fdtfile;"                                       \
 317         "bootm $loadaddr - $fdtaddr"
 318
 319 #define CONFIG_RAMBOOTCOMMAND                                           \
 320         "setenv bootargs root=/dev/ram rw "                             \
 321                 "console=$consoledev,$baudrate $othbootargs;"           \
 322         "tftp $ramdiskaddr $ramdiskfile;"                               \
 323         "tftp $loadaddr $bootfile;"                                     \
 324         "tftp $fdtaddr $fdtfile;"                                       \
 325         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 326
 327 #define CONFIG_BOOTCOMMAND      "run flash_self"
 328
 329 #endif  /* __CONFIG_H */