include/configs/sbc8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * WindRiver SBC8349 U-Boot configuration file.
   4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   5  *
   6  * Paul Gortmaker <paul.gortmaker@windriver.com>
   7  * Based on the MPC8349EMDS config.
   8  */
   9
  10 /*
  11  * sbc8349 board configuration file.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  */
  20 #define CONFIG_E300             1       /* E300 Family */
  21
  22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  23 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  24
  25 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  26 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  27 #define CONFIG_SYS_MEMTEST_END          0x00100000
  28
  29 /*
  30  * DDR Setup
  31  */
  32 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  33 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  34 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  35 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  36
  37 /*
  38  * 32-bit data path mode.
  39  *
  40  * Please note that using this mode for devices with the real density of 64-bit
  41  * effectively reduces the amount of available memory due to the effect of
  42  * wrapping around while translating address to row/columns, for example in the
  43  * 256MB module the upper 128MB get aliased with contents of the lower
  44  * 128MB); normally this define should be used for devices with real 32-bit
  45  * data path.
  46  */
  47 #undef CONFIG_DDR_32BIT
  48
  49 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  50 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  51 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  52 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  53                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  54 #define CONFIG_DDR_2T_TIMING
  55
  56 #if defined(CONFIG_SPD_EEPROM)
  57 /*
  58  * Determine DDR configuration from I2C interface.
  59  */
  60 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  61
  62 #else
  63 /*
  64  * Manually set up DDR parameters
  65  * NB: manual DDR setup untested on sbc834x
  66  */
  67 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  68 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  69                                         | CSCONFIG_ROW_BIT_13 \
  70                                         | CSCONFIG_COL_BIT_10)
  71 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  72 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  73 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  74 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  75
  76 #if defined(CONFIG_DDR_32BIT)
  77 /* set burst length to 8 for 32-bit data path */
  78                                 /* DLL,normal,seq,4/2.5, 8 burst len */
  79 #define CONFIG_SYS_DDR_MODE     0x00000023
  80 #else
  81 /* the default burst length is 4 - for 64-bit data path */
  82                                 /* DLL,normal,seq,4/2.5, 4 burst len */
  83 #define CONFIG_SYS_DDR_MODE     0x00000022
  84 #endif
  85 #endif
  86
  87 /*
  88  * SDRAM on the Local Bus
  89  */
  90 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
  91 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
  92
  93 /*
  94  * FLASH on the Local Bus
  95  */
  96 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
  97 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
  98
  99
 100 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 101 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 102
 103 #undef CONFIG_SYS_FLASH_CHECKSUM
 104 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 105 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 106
 107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 108
 109 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 110 #define CONFIG_SYS_RAMBOOT
 111 #else
 112 #undef  CONFIG_SYS_RAMBOOT
 113 #endif
 114
 115 #define CONFIG_SYS_INIT_RAM_LOCK        1
 116                                         /* Initial RAM address */
 117 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 118                                         /* Size of used area in RAM*/
 119 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 120
 121 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 122                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 123 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 124
 125 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 126 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 127
 128 /*
 129  * Local Bus LCRR and LBCR regs
 130  *    LCRR:  DLL bypass, Clock divider is 4
 131  * External Local Bus rate is
 132  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 133  */
 134 #define CONFIG_SYS_LBC_LBCR     0x00000000
 135
 136 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 137
 138 /*
 139  * Serial Port
 140  */
 141 #define CONFIG_SYS_NS16550_SERIAL
 142 #define CONFIG_SYS_NS16550_REG_SIZE    1
 143 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 144
 145 #define CONFIG_SYS_BAUDRATE_TABLE  \
 146                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 147
 148 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 149 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 150
 151 /* I2C */
 152 #define CONFIG_SYS_I2C
 153 #define CONFIG_SYS_I2C_FSL
 154 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 155 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 156 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 157 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 158 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 159 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 160 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 161 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 162
 163 /* TSEC */
 164 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 165 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 166 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 167 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 168
 169 /*
 170  * General PCI
 171  * Addresses are mapped 1-1.
 172  */
 173 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 174 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 175 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 176 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 177 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 178 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 179 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 180 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 181 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 182
 183 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 184 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 185 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 186 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 187 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 188 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 189 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 190 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 191 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 192
 193 #if defined(CONFIG_PCI)
 194
 195 #undef CONFIG_EEPRO100
 196 #undef CONFIG_TULIP
 197
 198 #if !defined(CONFIG_PCI_PNP)
 199         #define PCI_ENET0_IOADDR        0xFIXME
 200         #define PCI_ENET0_MEMADDR       0xFIXME
 201         #define PCI_IDSEL_NUMBER        0xFIXME
 202 #endif
 203
 204 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 205 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 206
 207 #endif  /* CONFIG_PCI */
 208
 209 /*
 210  * TSEC configuration
 211  */
 212
 213 #if defined(CONFIG_TSEC_ENET)
 214
 215 #define CONFIG_TSEC1    1
 216 #define CONFIG_TSEC1_NAME       "TSEC0"
 217 #define CONFIG_TSEC2    1
 218 #define CONFIG_TSEC2_NAME       "TSEC1"
 219 #define CONFIG_PHY_BCM5421S     1
 220 #define TSEC1_PHY_ADDR          0x19
 221 #define TSEC2_PHY_ADDR          0x1a
 222 #define TSEC1_PHYIDX            0
 223 #define TSEC2_PHYIDX            0
 224 #define TSEC1_FLAGS             TSEC_GIGABIT
 225 #define TSEC2_FLAGS             TSEC_GIGABIT
 226
 227 /* Options are: TSEC[0-1] */
 228 #define CONFIG_ETHPRIME         "TSEC0"
 229
 230 #endif  /* CONFIG_TSEC_ENET */
 231
 232 /*
 233  * Environment
 234  */
 235 #ifndef CONFIG_SYS_RAMBOOT
 236         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 237         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 238         #define CONFIG_ENV_SIZE         0x2000
 239
 240 /* Address and size of Redundant Environment Sector     */
 241 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 242 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 243
 244 #else
 245         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 246         #define CONFIG_ENV_SIZE         0x2000
 247 #endif
 248
 249 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 250 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 251
 252 /*
 253  * BOOTP options
 254  */
 255 #define CONFIG_BOOTP_BOOTFILESIZE
 256
 257 /*
 258  * Command line configuration.
 259  */
 260
 261 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 262
 263 /*
 264  * Miscellaneous configurable options
 265  */
 266 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 267
 268 /*
 269  * For booting Linux, the board info and command line data
 270  * have to be in the first 256 MB of memory, since this is
 271  * the maximum mapped by the Linux kernel during initialization.
 272  */
 273                                 /* Initial Memory map for Linux*/
 274 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 275
 276 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 277
 278 /* System IO Config */
 279 #define CONFIG_SYS_SICRH 0
 280 #define CONFIG_SYS_SICRL SICRL_LDP_A
 281
 282 #ifdef CONFIG_PCI
 283 #define CONFIG_PCI_INDIRECT_BRIDGE
 284 #endif
 285
 286 #if defined(CONFIG_CMD_KGDB)
 287 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 288 #endif
 289
 290 /*
 291  * Environment Configuration
 292  */
 293 #define CONFIG_ENV_OVERWRITE
 294
 295 #if defined(CONFIG_TSEC_ENET)
 296 #define CONFIG_HAS_ETH0
 297 #define CONFIG_HAS_ETH1
 298 #endif
 299
 300 #define CONFIG_HOSTNAME         "SBC8349"
 301 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 302 #define CONFIG_BOOTFILE         "uImage"
 303
 304                                 /* default location for tftp and bootm */
 305 #define CONFIG_LOADADDR         800000
 306
 307 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 308         "netdev=eth0\0"                                                 \
 309         "hostname=sbc8349\0"                                            \
 310         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 311                 "nfsroot=${serverip}:${rootpath}\0"                     \
 312         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 313         "addip=setenv bootargs ${bootargs} "                            \
 314                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 315                 ":${hostname}:${netdev}:off panic=1\0"                  \
 316         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 317         "flash_nfs=run nfsargs addip addtty;"                           \
 318                 "bootm ${kernel_addr}\0"                                \
 319         "flash_self=run ramargs addip addtty;"                          \
 320                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 321         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 322                 "bootm\0"                                               \
 323         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 324         "update=protect off ff800000 ff83ffff; "                        \
 325                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 326         "upd=run load update\0"                                         \
 327         "fdtaddr=780000\0"                                              \
 328         "fdtfile=sbc8349.dtb\0"                                         \
 329         ""
 330
 331 #define CONFIG_NFSBOOTCOMMAND                                           \
 332         "setenv bootargs root=/dev/nfs rw "                             \
 333                 "nfsroot=$serverip:$rootpath "                          \
 334                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 335                                                         "$netdev:off "  \
 336                 "console=$consoledev,$baudrate $othbootargs;"           \
 337         "tftp $loadaddr $bootfile;"                                     \
 338         "tftp $fdtaddr $fdtfile;"                                       \
 339         "bootm $loadaddr - $fdtaddr"
 340
 341 #define CONFIG_RAMBOOTCOMMAND                                           \
 342         "setenv bootargs root=/dev/ram rw "                             \
 343                 "console=$consoledev,$baudrate $othbootargs;"           \
 344         "tftp $ramdiskaddr $ramdiskfile;"                               \
 345         "tftp $loadaddr $bootfile;"                                     \
 346         "tftp $fdtaddr $fdtfile;"                                       \
 347         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 348
 349 #define CONFIG_BOOTCOMMAND      "run flash_self"
 350
 351 #endif  /* __CONFIG_H */