include/configs/sama5d3xek.h

   1 /*
   2  * Configuation settings for the SAMA5D3xEK board.
   3  *
   4  * Copyright (C) 2012 - 2013 Atmel
   5  *
   6  * based on at91sam9m10g45ek.h by:
   7  * Stelian Pop <stelian@popies.net>
   8  * Lead Tech Design <www.leadtechdesign.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #include "at91-sama5_common.h"
  17
  18 /*
  19  * This needs to be defined for the OHCI code to work but it is defined as
  20  * ATMEL_ID_UHPHS in the CPU specific header files.
  21  */
  22 #define ATMEL_ID_UHP                    32
  23
  24 /*
  25  * Specify the clock enable bit in the PMC_SCER register.
  26  */
  27 #define ATMEL_PMC_UHP                   (1 <<  6)
  28
  29 /* board specific (not enough SRAM) */
  30 #define CONFIG_SAMA5D3_LCD_BASE         0x23E00000
  31
  32 /* NOR flash */
  33 #ifdef CONFIG_MTD_NOR_FLASH
  34 #define CONFIG_FLASH_CFI_DRIVER
  35 #define CONFIG_SYS_FLASH_CFI
  36 #define CONFIG_SYS_FLASH_PROTECTION
  37 #define CONFIG_SYS_FLASH_BASE           0x10000000
  38 #define CONFIG_SYS_MAX_FLASH_SECT       131
  39 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  40 #endif
  41
  42 /* SDRAM */
  43 #define CONFIG_NR_DRAM_BANKS            1
  44 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  45 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
  46
  47 #ifdef CONFIG_SPL_BUILD
  48 #define CONFIG_SYS_INIT_SP_ADDR         0x318000
  49 #else
  50 #define CONFIG_SYS_INIT_SP_ADDR \
  51         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  52 #endif
  53
  54 /* SerialFlash */
  55
  56 #ifdef CONFIG_CMD_SF
  57 #define CONFIG_SF_DEFAULT_SPEED         30000000
  58 #endif
  59
  60 /* NAND flash */
  61 #ifdef CONFIG_CMD_NAND
  62 #define CONFIG_NAND_ATMEL
  63 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  64 #define CONFIG_SYS_NAND_BASE            0x60000000
  65 /* our ALE is AD21 */
  66 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  67 /* our CLE is AD22 */
  68 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  69 #define CONFIG_SYS_NAND_ONFI_DETECTION
  70 #endif
  71 /* PMECC & PMERRLOC */
  72 #define CONFIG_ATMEL_NAND_HWECC
  73 #define CONFIG_ATMEL_NAND_HW_PMECC
  74 #define CONFIG_PMECC_CAP                4
  75 #define CONFIG_PMECC_SECTOR_SIZE        512
  76
  77 /* USB */
  78
  79 #ifdef CONFIG_CMD_USB
  80 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  81 #define CONFIG_USB_OHCI_NEW
  82 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  83 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_BASE_OHCI
  84 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "sama5d3"
  85 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      3
  86 #endif
  87
  88 #define CONFIG_SYS_LOAD_ADDR                    0x22000000 /* load address */
  89
  90 /* SPL */
  91 #define CONFIG_SPL_TEXT_BASE            0x300000
  92 #define CONFIG_SPL_MAX_SIZE             0x18000
  93 #define CONFIG_SPL_BSS_START_ADDR       0x20000000
  94 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  95 #define CONFIG_SYS_SPL_MALLOC_START     0x20080000
  96 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
  97
  98 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
  99
 100 #ifdef CONFIG_SD_BOOT
 101 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 102 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 103
 104 #elif CONFIG_SPI_BOOT
 105 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x10000
 106
 107 #elif CONFIG_NAND_BOOT
 108 #define CONFIG_SPL_NAND_DRIVERS
 109 #define CONFIG_SPL_NAND_BASE
 110 #endif
 111 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 112 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 113 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 114 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 115 #define CONFIG_SYS_NAND_OOBSIZE         64
 116 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 117 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
 118 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 119
 120 #endif