3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Configuation settings for the WindRiver PPMC8260 board.
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /*****************************************************************************
39 * These settings must match the way _your_ board is set up
41 *****************************************************************************/
43 /* What is the oscillator's (UX2) frequency in Hz? */
44 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
46 /*-----------------------------------------------------------------------
47 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
48 *-----------------------------------------------------------------------
49 * What should MODCK_H be? It is dependent on the oscillator
50 * frequency, MODCK[1-3], and desired CPM and core frequencies.
51 * Here are some example values (all frequencies are in MHz):
53 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
54 * ------- ---------- --- --- ---- ----- ----- -----
55 * 0x2 0x2 33 133 133 Close Open Close
56 * 0x2 0x3 33 133 166 Close Open Open
57 * 0x2 0x4 33 133 200 Open Close Close
58 * 0x2 0x5 33 133 233 Open Close Open
59 * 0x2 0x6 33 133 266 Open Open Close
61 * 0x5 0x5 66 133 133 Open Close Open
62 * 0x5 0x6 66 133 166 Open Open Close
63 * 0x5 0x7 66 133 200 Open Open Open
64 * 0x6 0x0 66 133 233 Close Close Close
65 * 0x6 0x1 66 133 266 Close Close Open
66 * 0x6 0x2 66 133 300 Close Open Close
68 #define CFG_PPMC_MODCK_H 0x05
70 /* Define this if you want to boot from 0x00000100. If you don't define
71 * this, you will need to program the bootloader to 0xfff00000, and
72 * get the hardware reset config words at 0xfe000000. The simplest
73 * way to do that is to program the bootloader at both addresses.
74 * It is suggested that you just let U-Boot live at 0x00000000.
76 #define CFG_PPMC_BOOT_LOW 1
78 /* What should the base address of the main FLASH be and how big is
79 * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
80 * The main FLASH is whichever is connected to *CS0. U-Boot expects
81 * this to be the SIMM.
83 #define CFG_FLASH0_BASE 0xFE000000
84 #define CFG_FLASH0_SIZE 16
86 /* What should be the base address of the first SDRAM DIMM and how big is
89 #define CFG_SDRAM0_BASE 0x00000000
90 #define CFG_SDRAM0_SIZE 128
92 /* What should be the base address of the second SDRAM DIMM and how big is
95 #define CFG_SDRAM1_BASE 0x08000000
96 #define CFG_SDRAM1_SIZE 128
98 /* What should be the base address of the on board SDRAM and how big is
101 #define CFG_SDRAM2_BASE 0x38000000
102 #define CFG_SDRAM2_SIZE 16
104 /* What should be the base address of the MAILBOX and how big is it
106 * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
108 #define CFG_MAILBOX_BASE 0x32000000
109 #define CFG_MAILBOX_SIZE 8192
111 /* What is the base address of the I/O select lines and how big is it
115 #define CFG_IOSELECT_BASE 0xE0000000
116 #define CFG_IOSELECT_SIZE 32
119 /* What should be the base address of the LEDs and switch S0?
120 * If you don't want them enabled, don't define this.
122 #define CFG_LED_BASE 0xF1000000
125 * PPMC8260 with 256 16 MB DIMM:
127 * 0x0000 0000 Exception Vector code, 8k
130 * 0x0000 2000 Free for Application Use
136 * 0x0FF5 FF30 Monitor Stack (Growing downward)
137 * Monitor Stack Buffer (0x80)
138 * 0x0FF5 FFB0 Board Info Data
139 * 0x0FF6 0000 Malloc Arena
140 * : CFG_ENV_SECT_SIZE, 256k
141 * : CFG_MALLOC_LEN, 128k
142 * 0x0FFC 0000 RAM Copy of Monitor Code
143 * : CFG_MONITOR_LEN, 256k
144 * 0x0FFF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
149 * select serial console configuration
151 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
152 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
155 * if CONFIG_CONS_NONE is defined, then the serial console routines must
157 * The console can be on SMC1 or SMC2
159 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
160 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
161 #undef CONFIG_CONS_NONE /* define if console on neither */
162 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
165 * select ethernet configuration
167 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
168 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
171 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
172 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
175 #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
176 #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
177 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
178 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
179 #define CONFIG_MII /* MII PHY management */
180 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
182 * Port pins used for bit-banged MII communictions (if applicable).
184 #define MDIO_PORT 2 /* Port C */
185 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
186 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
187 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
189 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
190 else iop->pdat &= ~0x00400000
192 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
193 else iop->pdat &= ~0x00200000
195 #define MIIDELAY udelay(1)
198 /* Define this to reserve an entire FLASH sector (256 KB) for
199 * environment variables. Otherwise, the environment will be
200 * put in the same sector as U-Boot, and changing variables
201 * will erase U-Boot temporarily
203 #define CFG_ENV_IN_OWN_SECT 1
205 /* Define to allow the user to overwrite serial and ethaddr */
206 #define CONFIG_ENV_OVERWRITE
208 /* What should the console's baud rate be? */
209 #define CONFIG_BAUDRATE 9600
211 /* Ethernet MAC address */
213 #define CONFIG_ETHADDR 00:a0:1e:90:2b:00
215 /* Define this to set the last octet of the ethernet address
216 * from the DS0-DS7 switch and light the leds with the result
217 * The DS0-DS7 switch and the leds are backwards with respect
218 * to each other. DS7 is on the board edge side of both the
219 * led strip and the DS0-DS7 switch.
221 #define CONFIG_MISC_INIT_R
223 /* Set to a positive value to delay for running BOOTCOMMAND */
224 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
227 /* Be selective on what keys can delay or stop the autoboot process
230 # define CONFIG_AUTOBOOT_KEYED
231 # define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
232 # define CONFIG_AUTOBOOT_STOP_STR " "
233 # undef CONFIG_AUTOBOOT_DELAY_STR
234 # define DEBUG_BOOTKEYS 0
237 /* Define a command string that is automatically executed when no character
238 * is read on the console interface withing "Boot Delay" after reset.
240 #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
241 #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
243 #ifdef CONFIG_BOOT_ROOT_INITRD
244 #define CONFIG_BOOTCOMMAND \
248 "setenv bootargs root=/dev/ram0 rw " \
249 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
251 #endif /* CONFIG_BOOT_ROOT_INITRD */
253 #ifdef CONFIG_BOOT_ROOT_NFS
254 #define CONFIG_BOOTCOMMAND \
258 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
259 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
261 #endif /* CONFIG_BOOT_ROOT_NFS */
263 /* Add support for a few extra bootp options like:
267 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
268 CONFIG_BOOTP_BOOTFILESIZE | \
271 /* undef this to save memory */
274 /* Monitor Command Prompt */
275 #define CFG_PROMPT "=> "
279 * Command line configuration.
281 #include <config_cmd_default.h>
283 #define CONFIG_CMD_ELF
284 #define CONFIG_CMD_ASKENV
285 #define CONFIG_CMD_REGINFO
286 #define CONFIG_CMD_MEMTEST
287 #define CONFIG_CMD_MII
288 #define CONFIG_CMD_IMMAP
290 #undef CONFIG_CMD_KGDB
293 /* Where do the internal registers live? */
294 #define CFG_IMMR 0xf0000000
296 /*****************************************************************************
298 * You should not have to modify any of the following settings
300 *****************************************************************************/
302 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
303 #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
304 #define CONFIG_CPM2 1 /* Has a CPM2 */
307 * Miscellaneous configurable options
309 #if defined(CONFIG_CMD_KGDB)
310 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
312 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
315 /* Print Buffer Size */
316 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
318 #define CFG_MAXARGS 32 /* max number of command args */
320 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
322 #define CFG_LOAD_ADDR 0x140000 /* default load address */
323 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
325 #define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
326 /* the exception vector table */
327 /* to the end of the DRAM */
328 /* less monitor and malloc area */
329 #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
330 #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
332 + CFG_ENV_SECT_SIZE \
335 #define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
336 - CFG_MEM_END_USAGE )
338 /* valid baudrates */
339 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
342 * Low Level Configuration Settings
343 * (address mappings, register initial values, etc.)
344 * You should know what you are doing if you make changes here.
347 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
349 * Attention: This is board specific
353 #define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
356 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
358 * Attention: this is board-specific
361 * - Select bus for bd/buffers (see 28-13)
362 * - Enable Full Duplex in FSMR
364 #define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
365 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
366 #define CFG_CPMFCR_RAMTYPE 0
367 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
368 #endif /* CONFIG_ETHER_INDEX */
370 #define CFG_FLASH_BASE CFG_FLASH0_BASE
371 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
372 #define CFG_SDRAM_BASE CFG_SDRAM0_BASE
373 #define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
375 /*-----------------------------------------------------------------------
376 * Hard Reset Configuration Words
378 #if defined(CFG_PPMC_BOOT_LOW)
379 # define CFG_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
381 # define CFG_PPMC_HRCW_BOOT_FLAGS (0)
382 #endif /* defined(CFG_PPMC_BOOT_LOW) */
384 /* get the HRCW ISB field from CFG_IMMR */
385 #define CFG_PPMC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
386 ((CFG_IMMR & 0x01000000) >> 7) | \
387 ((CFG_IMMR & 0x00100000) >> 4) )
389 #define CFG_HRCW_MASTER ( HRCW_EBM | \
393 CFG_PPMC_HRCW_IMMR | \
398 (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
399 CFG_PPMC_HRCW_BOOT_FLAGS )
402 #define CFG_HRCW_SLAVE1 0
403 #define CFG_HRCW_SLAVE2 0
404 #define CFG_HRCW_SLAVE3 0
405 #define CFG_HRCW_SLAVE4 0
406 #define CFG_HRCW_SLAVE5 0
407 #define CFG_HRCW_SLAVE6 0
408 #define CFG_HRCW_SLAVE7 0
410 /*-----------------------------------------------------------------------
411 * Definitions for initial stack pointer and data area (in DPRAM)
413 #define CFG_INIT_RAM_ADDR CFG_IMMR
414 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
415 #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
416 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
417 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
419 /*-----------------------------------------------------------------------
420 * Start addresses for the final memory configuration
421 * (Set up by the startup code)
422 * Please note that CFG_SDRAM_BASE _must_ start at 0
423 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
425 #define CFG_MONITOR_BASE CFG_FLASH0_BASE
427 #ifndef CFG_MONITOR_BASE
428 #define CFG_MONITOR_BASE 0x0ff80000
431 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
435 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
436 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
439 * For booting Linux, the board info and command line data
440 * have to be in the first 8 MB of memory, since this is
441 * the maximum mapped by the Linux kernel during initialization.
443 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
445 /*-----------------------------------------------------------------------
446 * FLASH and environment organization
449 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
450 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
451 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
452 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
453 #define CFG_FLASH_INCREMENT 0 /* there is only one bank */
454 #define CFG_FLASH_PROTECTION 1 /* use hardware protection */
455 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
460 # define CFG_ENV_IS_IN_FLASH 1
461 # ifdef CFG_ENV_IN_OWN_SECT
462 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
463 # define CFG_ENV_SECT_SIZE 0x40000
465 # define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
466 # define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
467 # define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
468 # endif /* CFG_ENV_IN_OWN_SECT */
471 # define CFG_ENV_IS_IN_FLASH 1
472 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
473 #define CFG_ENV_SIZE 0x1000
474 # define CFG_ENV_SECT_SIZE 0x40000
475 #endif /* CFG_RAMBOOT */
477 /*-----------------------------------------------------------------------
478 * Cache Configuration
480 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
482 #if defined(CONFIG_CMD_KGDB)
483 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
486 /*-----------------------------------------------------------------------
487 * HIDx - Hardware Implementation-dependent Registers 2-11
488 *-----------------------------------------------------------------------
489 * HID0 also contains cache control - initially enable both caches and
490 * invalidate contents, then the final state leaves only the instruction
491 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
492 * but Soft reset does not.
494 * HID1 has only read-only information - nothing to set.
496 #define CFG_HID0_INIT (HID0_ICE |\
503 #define CFG_HID0_FINAL (HID0_ICE |\
509 /*-----------------------------------------------------------------------
510 * RMR - Reset Mode Register
511 *-----------------------------------------------------------------------
515 /*-----------------------------------------------------------------------
516 * BCR - Bus Configuration 4-25
517 *-----------------------------------------------------------------------
519 #define CFG_BCR (BCR_EBM |\
522 /*-----------------------------------------------------------------------
523 * SIUMCR - SIU Module Configuration 4-31
524 * Ref Section 4.3.2.6 page 4-31
525 *-----------------------------------------------------------------------
528 #define CFG_SIUMCR (SIUMCR_ESE |\
538 /*-----------------------------------------------------------------------
539 * SYPCR - System Protection Control 11-9
540 * SYPCR can only be written once after reset!
541 *-----------------------------------------------------------------------
542 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
544 #define CFG_SYPCR (SYPCR_SWTC |\
551 /*-----------------------------------------------------------------------
552 * TMCNTSC - Time Counter Status and Control 4-40
553 *-----------------------------------------------------------------------
554 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
555 * and enable Time Counter
557 #define CFG_TMCNTSC (TMCNTSC_SEC |\
562 /*-----------------------------------------------------------------------
563 * PISCR - Periodic Interrupt Status and Control 4-42
564 *-----------------------------------------------------------------------
565 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
568 #define CFG_PISCR (PISCR_PS |\
572 /*-----------------------------------------------------------------------
573 * SCCR - System Clock Control 9-8
574 *-----------------------------------------------------------------------
578 /*-----------------------------------------------------------------------
579 * RCCR - RISC Controller Configuration 13-7
580 *-----------------------------------------------------------------------
585 * Initialize Memory Controller:
587 * Bank Bus Machine PortSz Device
588 * ---- --- ------- ------ ------
589 * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
591 * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
592 * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
593 * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
594 * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
595 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
596 * 7 60x GPCM 8 bit LEDs, switches
598 * (*) This configuration requires the PPMC8260 be configured
599 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
600 * the on board FLASH. In other words, JP24 should have
601 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
605 /*-----------------------------------------------------------------------
606 * BR0,BR1 - Base Register
607 * Ref: Section 10.3.1 on page 10-14
608 * OR0,OR1 - Option Register
609 * Ref: Section 10.3.2 on page 10-18
610 *-----------------------------------------------------------------------
613 /* Bank 0,1 - FLASH SIMM
615 * This expects the FLASH SIMM to be connected to *CS0
616 * It consists of 4 AM29F080B parts.
618 * Note: For the 4 MB SIMM, *CS1 is unused.
621 /* BR0 is configured as follows:
623 * - Base address of 0xFE000000
625 * - Data errors checking is disabled
626 * - Read and write access
628 * - Access are handled by the memory controller according to MSEL
629 * - Not used for atomic operations
630 * - No data pipelining is done
633 #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
638 /* OR0 is configured as follows:
641 * - *BCTL0 is asserted upon access to the current memory bank
642 * - *CW / *WE are negated a quarter of a clock earlier
643 * - *CS is output at the same time as the address lines
644 * - Uses a clock cycle length of 5
645 * - *PSDVAL is generated internally by the memory controller
646 * unless *GTA is asserted earlier externally.
647 * - Relaxed timing is generated by the GPCM for accesses
648 * initiated to this memory region.
649 * - One idle clock is inserted between a read access from the
650 * current bank and the next access.
652 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
659 /*-----------------------------------------------------------------------
660 * BR2,BR3 - Base Register
661 * Ref: Section 10.3.1 on page 10-14
662 * OR2,OR3 - Option Register
663 * Ref: Section 10.3.2 on page 10-16
664 *-----------------------------------------------------------------------
668 * Bank 2,3 - 128 MB SDRAM DIMM
671 /* With a 128 MB DIMM, the BR2 is configured as follows:
673 * - Base address of 0x00000000/0x08000000
674 * - 64 bit port size (60x bus only)
675 * - Data errors checking is disabled
676 * - Read and write access
678 * - Access are handled by the memory controller according to MSEL
679 * - Not used for atomic operations
680 * - No data pipelining is done
683 #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
688 #define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
693 /* With a 128 MB DIMM, the OR2 is configured as follows:
696 * - 4 internal banks per device
697 * - Row start address bit is A8 with PSDMR[PBI] = 0
698 * - 13 row address lines
699 * - Back-to-back page mode
700 * - Internal bank interleaving within save device enabled
703 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
705 ORxS_ROWST_PBI0_A7 |\
708 #define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
710 ORxS_ROWST_PBI0_A7 |\
714 /*-----------------------------------------------------------------------
715 * PSDMR - 60x Bus SDRAM Mode Register
716 * Ref: Section 10.3.3 on page 10-21
717 *-----------------------------------------------------------------------
720 /* With a 128 MB DIMM, the PSDMR is configured as follows:
722 * - Page Based Interleaving,
725 * - Address Multiplexing where A5 is output on A14 pin
726 * (A6 on A15, and so on),
727 * - use address pins A13-A15 as bank select,
728 * - A9 is output on SDA10 during an ACTIVATE command,
729 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
730 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
732 * - earliest timing for READ/WRITE command after ACTIVATE command is
734 * - earliest timing for PRECHARGE after last data was read is 1 clock,
735 * - earliest timing for PRECHARGE after last data was written is 1 clock,
736 * - External Address Multiplexing enabled
737 * - CAS Latency is 2.
739 #define CFG_PSDMR (PSDMR_RFEN |\
740 PSDMR_SDAM_A14_IS_A5 |\
741 PSDMR_BSMA_A13_A15 |\
742 PSDMR_SDA10_PBI0_A9 |\
752 #define CFG_PSRT 0x0e
753 #define CFG_MPTPR MPTPR_PTP_DIV32
756 /*-----------------------------------------------------------------------
757 * BR4 - Base Register
758 * Ref: Section 10.3.1 on page 10-14
759 * OR4 - Option Register
760 * Ref: Section 10.3.2 on page 10-16
761 *-----------------------------------------------------------------------
765 * Bank 4 - On board SDRAM
768 /* With 16 MB of onboard SDRAM BR4 is configured as follows
770 * - Base address 0x38000000
772 * - Data error checking disabled
773 * - Read/Write access
775 * - Not used for atomic operations
776 * - No data pipelining is done
781 #define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
788 * With 16MB SDRAM, OR4 is configured as follows
789 * - 4 internal banks per device
790 * - Row start address bit is A10 with LSDMR[PBI] = 0
791 * - 12 row address lines
792 * - Back-to-back page mode
793 * - Internal bank interleaving within save device enabled
796 #define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE) |\
798 ORxS_ROWST_PBI0_A10 |\
802 /*-----------------------------------------------------------------------
803 * LSDMR - Local Bus SDRAM Mode Register
804 * Ref: Section 10.3.4 on page 10-24
805 *-----------------------------------------------------------------------
808 /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
810 * - Page Based Interleaving,
813 * - Address Multiplexing where A5 is output on A13 pin
814 * (A6 on A15, and so on),
815 * - use address pins A15-A17 as bank select,
816 * - A11 is output on SDA10 during an ACTIVATE command,
817 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
818 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
820 * - earliest timing for READ/WRITE command after ACTIVATE command is
822 * - SDRAM burst length is 8
823 * - earliest timing for PRECHARGE after last data was read is 1 clock,
824 * - earliest timing for PRECHARGE after last data was written is 1 clock,
825 * - External Address Multiplexing disabled
826 * - CAS Latency is 2.
828 #define CFG_LSDMR (PSDMR_RFEN |\
829 PSDMR_SDAM_A13_IS_A5 |\
830 PSDMR_BSMA_A15_A17 |\
831 PSDMR_SDA10_PBI0_A11 |\
840 #define CFG_LSRT 0x0e
842 /*-----------------------------------------------------------------------
843 * BR5 - Base Register
844 * Ref: Section 10.3.1 on page 10-14
845 * OR5 - Option Register
846 * Ref: Section 10.3.2 on page 10-16
847 *-----------------------------------------------------------------------
851 * Bank 5 EEProm and Mailbox
853 * The EEPROM and mailbox live on the same chip select.
854 * the eeprom is selected if the MSb of the address is set and the mailbox is
855 * selected if the MSb of the address is clear.
859 /* BR5 is configured as follows:
861 * - Base address of 0x32000000/0xF2000000
863 * - Data error checking disabled
864 * - Read/Write access
867 * - No data pipelining is done
871 #define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
876 /* OR5 is configured as follows
877 * - buffer control enabled
878 * - chip select negated normally
879 * - CS output 1/2 clock after address
881 * - *PSDVAL is generated internally by the memory controller
882 * unless *GTA is asserted earlier externally.
883 * - Relaxed timing is generated by the GPCM for accesses
884 * initiated to this memory region.
885 * - One idle clock is inserted between a read access from the
886 * current bank and the next access.
889 #define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
895 /*-----------------------------------------------------------------------
896 * BR6 - Base Register
897 * Ref: Section 10.3.1 on page 10-14
898 * OR6 - Option Register
899 * Ref: Section 10.3.2 on page 10-18
900 *-----------------------------------------------------------------------
903 /* Bank 6 - I/O select
907 /* BR6 is configured as follows:
909 * - Base address of 0xE0000000
911 * - Data errors checking is disabled
912 * - Read and write access
914 * - Access are handled by the memory controller according to MSEL
915 * - Not used for atomic operations
916 * - No data pipelining is done
919 #define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
924 /* OR6 is configured as follows
925 * - buffer control enabled
926 * - chip select negated normally
927 * - CS output 1/2 clock after address
929 * - *PSDVAL is generated internally by the memory controller
930 * unless *GTA is asserted earlier externally.
931 * - Relaxed timing is generated by the GPCM for accesses
932 * initiated to this memory region.
933 * - One idle clock is inserted between a read access from the
934 * current bank and the next access.
937 #define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
944 /*-----------------------------------------------------------------------
945 * BR7 - Base Register
946 * Ref: Section 10.3.1 on page 10-14
947 * OR7 - Option Register
948 * Ref: Section 10.3.2 on page 10-18
949 *-----------------------------------------------------------------------
952 /* Bank 7 - LEDs and switches
954 * LEDs are at 0x00001 (write only)
955 * switches are at 0x00001 (read only)
959 /* BR7 is configured as follows:
961 * - Base address of 0xA0000000
963 * - Data errors checking is disabled
964 * - Read and write access
966 * - Access are handled by the memory controller according to MSEL
967 * - Not used for atomic operations
968 * - No data pipelining is done
971 #define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
977 /* OR7 is configured as follows:
980 * - *BCTL0 is asserted upon access to the current memory bank
981 * - *CW / *WE are negated a quarter of a clock earlier
982 * - *CS is output at the same time as the address lines
983 * - Uses a clock cycle length of 15
984 * - *PSDVAL is generated internally by the memory controller
985 * unless *GTA is asserted earlier externally.
986 * - Relaxed timing is generated by the GPCM for accesses
987 * initiated to this memory region.
988 * - One idle clock is inserted between a read access from the
989 * current bank and the next access.
991 #define CFG_OR7_PRELIM (ORxG_AM_MSK |\
997 #endif /* CFG_LED_BASE */
1000 * Internal Definitions
1004 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1005 #define BOOTFLAG_WARM 0x02 /* Software reboot */
1007 #endif /* __CONFIG_H */