3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Configuation settings for the WindRiver PPMC8260 board.
15 * SPDX-License-Identifier: GPL-2.0+
21 #define CONFIG_SYS_TEXT_BASE 0xfe000000
23 /*****************************************************************************
25 * These settings must match the way _your_ board is set up
27 *****************************************************************************/
29 /* What is the oscillator's (UX2) frequency in Hz? */
30 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
32 /*-----------------------------------------------------------------------
33 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
34 *-----------------------------------------------------------------------
35 * What should MODCK_H be? It is dependent on the oscillator
36 * frequency, MODCK[1-3], and desired CPM and core frequencies.
37 * Here are some example values (all frequencies are in MHz):
39 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
40 * ------- ---------- --- --- ---- ----- ----- -----
41 * 0x2 0x2 33 133 133 Close Open Close
42 * 0x2 0x3 33 133 166 Close Open Open
43 * 0x2 0x4 33 133 200 Open Close Close
44 * 0x2 0x5 33 133 233 Open Close Open
45 * 0x2 0x6 33 133 266 Open Open Close
47 * 0x5 0x5 66 133 133 Open Close Open
48 * 0x5 0x6 66 133 166 Open Open Close
49 * 0x5 0x7 66 133 200 Open Open Open
50 * 0x6 0x0 66 133 233 Close Close Close
51 * 0x6 0x1 66 133 266 Close Close Open
52 * 0x6 0x2 66 133 300 Close Open Close
54 #define CONFIG_SYS_PPMC_MODCK_H 0x05
56 /* Define this if you want to boot from 0x00000100. If you don't define
57 * this, you will need to program the bootloader to 0xfff00000, and
58 * get the hardware reset config words at 0xfe000000. The simplest
59 * way to do that is to program the bootloader at both addresses.
60 * It is suggested that you just let U-Boot live at 0x00000000.
62 #define CONFIG_SYS_PPMC_BOOT_LOW 1
64 /* What should the base address of the main FLASH be and how big is
65 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk
66 * The main FLASH is whichever is connected to *CS0. U-Boot expects
67 * this to be the SIMM.
69 #define CONFIG_SYS_FLASH0_BASE 0xFE000000
70 #define CONFIG_SYS_FLASH0_SIZE 16
72 /* What should be the base address of the first SDRAM DIMM and how big is
75 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
76 #define CONFIG_SYS_SDRAM0_SIZE 128
78 /* What should be the base address of the second SDRAM DIMM and how big is
81 #define CONFIG_SYS_SDRAM1_BASE 0x08000000
82 #define CONFIG_SYS_SDRAM1_SIZE 128
84 /* What should be the base address of the on board SDRAM and how big is
87 #define CONFIG_SYS_SDRAM2_BASE 0x38000000
88 #define CONFIG_SYS_SDRAM2_SIZE 16
90 /* What should be the base address of the MAILBOX and how big is it
92 * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
94 #define CONFIG_SYS_MAILBOX_BASE 0x32000000
95 #define CONFIG_SYS_MAILBOX_SIZE 8192
97 /* What is the base address of the I/O select lines and how big is it
101 #define CONFIG_SYS_IOSELECT_BASE 0xE0000000
102 #define CONFIG_SYS_IOSELECT_SIZE 32
105 /* What should be the base address of the LEDs and switch S0?
106 * If you don't want them enabled, don't define this.
108 #define CONFIG_SYS_LED_BASE 0xF1000000
111 * PPMC8260 with 256 16 MB DIMM:
113 * 0x0000 0000 Exception Vector code, 8k
116 * 0x0000 2000 Free for Application Use
122 * 0x0FF5 FF30 Monitor Stack (Growing downward)
123 * Monitor Stack Buffer (0x80)
124 * 0x0FF5 FFB0 Board Info Data
125 * 0x0FF6 0000 Malloc Arena
126 * : CONFIG_ENV_SECT_SIZE, 256k
127 * : CONFIG_SYS_MALLOC_LEN, 128k
128 * 0x0FFC 0000 RAM Copy of Monitor Code
129 * : CONFIG_SYS_MONITOR_LEN, 256k
130 * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
135 * select serial console configuration
137 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
138 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
141 * if CONFIG_CONS_NONE is defined, then the serial console routines must
143 * The console can be on SMC1 or SMC2
145 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
146 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
147 #undef CONFIG_CONS_NONE /* define if console on neither */
148 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
151 * select ethernet configuration
153 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
154 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
157 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
158 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
161 #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
162 #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
163 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
164 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
165 #define CONFIG_MII /* MII PHY management */
166 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
168 * Port pins used for bit-banged MII communictions (if applicable).
170 #define MDIO_PORT 2 /* Port C */
171 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
172 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
173 #define MDC_DECLARE MDIO_DECLARE
175 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
176 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
177 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
179 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
180 else iop->pdat &= ~0x00400000
182 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
183 else iop->pdat &= ~0x00200000
185 #define MIIDELAY udelay(1)
188 /* Define this to reserve an entire FLASH sector (256 KB) for
189 * environment variables. Otherwise, the environment will be
190 * put in the same sector as U-Boot, and changing variables
191 * will erase U-Boot temporarily
193 #define CONFIG_ENV_IN_OWN_SECT 1
195 /* Define to allow the user to overwrite serial and ethaddr */
196 #define CONFIG_ENV_OVERWRITE
198 /* What should the console's baud rate be? */
199 #define CONFIG_BAUDRATE 9600
201 /* Ethernet MAC address */
203 #define CONFIG_ETHADDR 00:a0:1e:90:2b:00
205 /* Define this to set the last octet of the ethernet address
206 * from the DS0-DS7 switch and light the leds with the result
207 * The DS0-DS7 switch and the leds are backwards with respect
208 * to each other. DS7 is on the board edge side of both the
209 * led strip and the DS0-DS7 switch.
211 #define CONFIG_MISC_INIT_R
213 /* Set to a positive value to delay for running BOOTCOMMAND */
214 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
217 /* Be selective on what keys can delay or stop the autoboot process
220 # define CONFIG_AUTOBOOT_KEYED
221 # define CONFIG_AUTOBOOT_PROMPT \
222 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
223 # define CONFIG_AUTOBOOT_STOP_STR " "
224 # undef CONFIG_AUTOBOOT_DELAY_STR
225 # define DEBUG_BOOTKEYS 0
228 /* Define a command string that is automatically executed when no character
229 * is read on the console interface withing "Boot Delay" after reset.
231 #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
232 #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
234 #ifdef CONFIG_BOOT_ROOT_INITRD
235 #define CONFIG_BOOTCOMMAND \
239 "setenv bootargs root=/dev/ram0 rw " \
240 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
242 #endif /* CONFIG_BOOT_ROOT_INITRD */
244 #ifdef CONFIG_BOOT_ROOT_NFS
245 #define CONFIG_BOOTCOMMAND \
249 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
250 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
252 #endif /* CONFIG_BOOT_ROOT_NFS */
258 #define CONFIG_BOOTP_SUBNETMASK
259 #define CONFIG_BOOTP_GATEWAY
260 #define CONFIG_BOOTP_HOSTNAME
261 #define CONFIG_BOOTP_BOOTPATH
262 #define CONFIG_BOOTP_BOOTFILESIZE
263 #define CONFIG_BOOTP_DNS
266 /* undef this to save memory */
267 #define CONFIG_SYS_LONGHELP
269 /* Monitor Command Prompt */
273 * Command line configuration.
275 #include <config_cmd_default.h>
277 #define CONFIG_CMD_ELF
278 #define CONFIG_CMD_ASKENV
279 #define CONFIG_CMD_REGINFO
280 #define CONFIG_CMD_MEMTEST
281 #define CONFIG_CMD_MII
282 #define CONFIG_CMD_IMMAP
284 #undef CONFIG_CMD_KGDB
287 /* Where do the internal registers live? */
288 #define CONFIG_SYS_IMMR 0xf0000000
290 /*****************************************************************************
292 * You should not have to modify any of the following settings
294 *****************************************************************************/
296 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
297 #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
298 #define CONFIG_CPM2 1 /* Has a CPM2 */
301 * Miscellaneous configurable options
303 #if defined(CONFIG_CMD_KGDB)
304 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
306 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
309 /* Print Buffer Size */
310 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
312 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
314 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
316 #define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */
317 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
319 #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
320 /* the exception vector table */
321 /* to the end of the DRAM */
322 /* less monitor and malloc area */
323 #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
324 #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
325 + CONFIG_SYS_MALLOC_LEN \
326 + CONFIG_ENV_SECT_SIZE \
327 + CONFIG_SYS_STACK_USAGE )
329 #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
330 - CONFIG_SYS_MEM_END_USAGE )
333 * Low Level Configuration Settings
334 * (address mappings, register initial values, etc.)
335 * You should know what you are doing if you make changes here.
338 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
340 * Attention: This is board specific
344 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
347 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
349 * Attention: this is board-specific
352 * - Select bus for bd/buffers (see 28-13)
353 * - Enable Full Duplex in FSMR
355 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
356 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
357 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
358 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
359 #endif /* CONFIG_ETHER_INDEX */
361 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
362 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
363 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
364 #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
366 /*-----------------------------------------------------------------------
367 * Hard Reset Configuration Words
369 #if defined(CONFIG_SYS_PPMC_BOOT_LOW)
370 # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
372 # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0)
373 #endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
375 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
376 #define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
377 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
378 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
380 #define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \
384 CONFIG_SYS_PPMC_HRCW_IMMR | \
389 (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
390 CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
393 #define CONFIG_SYS_HRCW_SLAVE1 0
394 #define CONFIG_SYS_HRCW_SLAVE2 0
395 #define CONFIG_SYS_HRCW_SLAVE3 0
396 #define CONFIG_SYS_HRCW_SLAVE4 0
397 #define CONFIG_SYS_HRCW_SLAVE5 0
398 #define CONFIG_SYS_HRCW_SLAVE6 0
399 #define CONFIG_SYS_HRCW_SLAVE7 0
401 /*-----------------------------------------------------------------------
402 * Definitions for initial stack pointer and data area (in DPRAM)
404 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
405 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
406 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
407 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
409 /*-----------------------------------------------------------------------
410 * Start addresses for the final memory configuration
411 * (Set up by the startup code)
412 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
413 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
417 #ifndef CONFIG_SYS_MONITOR_BASE
418 #define CONFIG_SYS_MONITOR_BASE 0x0ff80000
421 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
422 # define CONFIG_SYS_RAMBOOT
425 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
426 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
429 * For booting Linux, the board info and command line data
430 * have to be in the first 8 MB of memory, since this is
431 * the maximum mapped by the Linux kernel during initialization.
433 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
435 /*-----------------------------------------------------------------------
436 * FLASH and environment organization
439 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
440 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
441 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
442 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
443 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
444 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
445 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
448 #ifndef CONFIG_SYS_RAMBOOT
450 # define CONFIG_ENV_IS_IN_FLASH 1
451 # ifdef CONFIG_ENV_IN_OWN_SECT
452 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
453 # define CONFIG_ENV_SECT_SIZE 0x40000
455 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
456 # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
457 # define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
458 # endif /* CONFIG_ENV_IN_OWN_SECT */
461 # define CONFIG_ENV_IS_IN_FLASH 1
462 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
463 #define CONFIG_ENV_SIZE 0x1000
464 # define CONFIG_ENV_SECT_SIZE 0x40000
465 #endif /* CONFIG_SYS_RAMBOOT */
467 /*-----------------------------------------------------------------------
468 * Cache Configuration
470 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
472 #if defined(CONFIG_CMD_KGDB)
473 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
476 /*-----------------------------------------------------------------------
477 * HIDx - Hardware Implementation-dependent Registers 2-11
478 *-----------------------------------------------------------------------
479 * HID0 also contains cache control - initially enable both caches and
480 * invalidate contents, then the final state leaves only the instruction
481 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
482 * but Soft reset does not.
484 * HID1 has only read-only information - nothing to set.
486 #define CONFIG_SYS_HID0_INIT (HID0_ICE |\
493 #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
497 #define CONFIG_SYS_HID2 0
499 /*-----------------------------------------------------------------------
500 * RMR - Reset Mode Register
501 *-----------------------------------------------------------------------
503 #define CONFIG_SYS_RMR 0
505 /*-----------------------------------------------------------------------
506 * BCR - Bus Configuration 4-25
507 *-----------------------------------------------------------------------
509 #define CONFIG_SYS_BCR (BCR_EBM |\
512 /*-----------------------------------------------------------------------
513 * SIUMCR - SIU Module Configuration 4-31
514 * Ref Section 4.3.2.6 page 4-31
515 *-----------------------------------------------------------------------
518 #define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\
528 /*-----------------------------------------------------------------------
529 * SYPCR - System Protection Control 11-9
530 * SYPCR can only be written once after reset!
531 *-----------------------------------------------------------------------
532 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
534 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
541 /*-----------------------------------------------------------------------
542 * TMCNTSC - Time Counter Status and Control 4-40
543 *-----------------------------------------------------------------------
544 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
545 * and enable Time Counter
547 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
552 /*-----------------------------------------------------------------------
553 * PISCR - Periodic Interrupt Status and Control 4-42
554 *-----------------------------------------------------------------------
555 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
558 #define CONFIG_SYS_PISCR (PISCR_PS |\
562 /*-----------------------------------------------------------------------
563 * SCCR - System Clock Control 9-8
564 *-----------------------------------------------------------------------
566 #define CONFIG_SYS_SCCR 0
568 /*-----------------------------------------------------------------------
569 * RCCR - RISC Controller Configuration 13-7
570 *-----------------------------------------------------------------------
572 #define CONFIG_SYS_RCCR 0
575 * Initialize Memory Controller:
577 * Bank Bus Machine PortSz Device
578 * ---- --- ------- ------ ------
579 * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
581 * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
582 * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
583 * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
584 * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
585 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
586 * 7 60x GPCM 8 bit LEDs, switches
588 * (*) This configuration requires the PPMC8260 be configured
589 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
590 * the on board FLASH. In other words, JP24 should have
591 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
595 /*-----------------------------------------------------------------------
596 * BR0,BR1 - Base Register
597 * Ref: Section 10.3.1 on page 10-14
598 * OR0,OR1 - Option Register
599 * Ref: Section 10.3.2 on page 10-18
600 *-----------------------------------------------------------------------
603 /* Bank 0,1 - FLASH SIMM
605 * This expects the FLASH SIMM to be connected to *CS0
606 * It consists of 4 AM29F080B parts.
608 * Note: For the 4 MB SIMM, *CS1 is unused.
611 /* BR0 is configured as follows:
613 * - Base address of 0xFE000000
615 * - Data errors checking is disabled
616 * - Read and write access
618 * - Access are handled by the memory controller according to MSEL
619 * - Not used for atomic operations
620 * - No data pipelining is done
623 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
628 /* OR0 is configured as follows:
631 * - *BCTL0 is asserted upon access to the current memory bank
632 * - *CW / *WE are negated a quarter of a clock earlier
633 * - *CS is output at the same time as the address lines
634 * - Uses a clock cycle length of 5
635 * - *PSDVAL is generated internally by the memory controller
636 * unless *GTA is asserted earlier externally.
637 * - Relaxed timing is generated by the GPCM for accesses
638 * initiated to this memory region.
639 * - One idle clock is inserted between a read access from the
640 * current bank and the next access.
642 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
649 /*-----------------------------------------------------------------------
650 * BR2,BR3 - Base Register
651 * Ref: Section 10.3.1 on page 10-14
652 * OR2,OR3 - Option Register
653 * Ref: Section 10.3.2 on page 10-16
654 *-----------------------------------------------------------------------
658 * Bank 2,3 - 128 MB SDRAM DIMM
661 /* With a 128 MB DIMM, the BR2 is configured as follows:
663 * - Base address of 0x00000000/0x08000000
664 * - 64 bit port size (60x bus only)
665 * - Data errors checking is disabled
666 * - Read and write access
668 * - Access are handled by the memory controller according to MSEL
669 * - Not used for atomic operations
670 * - No data pipelining is done
673 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
678 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
683 /* With a 128 MB DIMM, the OR2 is configured as follows:
686 * - 4 internal banks per device
687 * - Row start address bit is A8 with PSDMR[PBI] = 0
688 * - 13 row address lines
689 * - Back-to-back page mode
690 * - Internal bank interleaving within save device enabled
693 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
695 ORxS_ROWST_PBI0_A7 |\
698 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
700 ORxS_ROWST_PBI0_A7 |\
704 /*-----------------------------------------------------------------------
705 * PSDMR - 60x Bus SDRAM Mode Register
706 * Ref: Section 10.3.3 on page 10-21
707 *-----------------------------------------------------------------------
710 /* With a 128 MB DIMM, the PSDMR is configured as follows:
712 * - Page Based Interleaving,
715 * - Address Multiplexing where A5 is output on A14 pin
716 * (A6 on A15, and so on),
717 * - use address pins A13-A15 as bank select,
718 * - A9 is output on SDA10 during an ACTIVATE command,
719 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
720 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
722 * - earliest timing for READ/WRITE command after ACTIVATE command is
724 * - earliest timing for PRECHARGE after last data was read is 1 clock,
725 * - earliest timing for PRECHARGE after last data was written is 1 clock,
726 * - External Address Multiplexing enabled
727 * - CAS Latency is 2.
729 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
730 PSDMR_SDAM_A14_IS_A5 |\
731 PSDMR_BSMA_A13_A15 |\
732 PSDMR_SDA10_PBI0_A9 |\
742 #define CONFIG_SYS_PSRT 0x0e
743 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
746 /*-----------------------------------------------------------------------
747 * BR4 - Base Register
748 * Ref: Section 10.3.1 on page 10-14
749 * OR4 - Option Register
750 * Ref: Section 10.3.2 on page 10-16
751 *-----------------------------------------------------------------------
755 * Bank 4 - On board SDRAM
758 /* With 16 MB of onboard SDRAM BR4 is configured as follows
760 * - Base address 0x38000000
762 * - Data error checking disabled
763 * - Read/Write access
765 * - Not used for atomic operations
766 * - No data pipelining is done
771 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
778 * With 16MB SDRAM, OR4 is configured as follows
779 * - 4 internal banks per device
780 * - Row start address bit is A10 with LSDMR[PBI] = 0
781 * - 12 row address lines
782 * - Back-to-back page mode
783 * - Internal bank interleaving within save device enabled
786 #define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\
788 ORxS_ROWST_PBI0_A10 |\
792 /*-----------------------------------------------------------------------
793 * LSDMR - Local Bus SDRAM Mode Register
794 * Ref: Section 10.3.4 on page 10-24
795 *-----------------------------------------------------------------------
798 /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
800 * - Page Based Interleaving,
803 * - Address Multiplexing where A5 is output on A13 pin
804 * (A6 on A15, and so on),
805 * - use address pins A15-A17 as bank select,
806 * - A11 is output on SDA10 during an ACTIVATE command,
807 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
808 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
810 * - earliest timing for READ/WRITE command after ACTIVATE command is
812 * - SDRAM burst length is 8
813 * - earliest timing for PRECHARGE after last data was read is 1 clock,
814 * - earliest timing for PRECHARGE after last data was written is 1 clock,
815 * - External Address Multiplexing disabled
816 * - CAS Latency is 2.
818 #define CONFIG_SYS_LSDMR (PSDMR_RFEN |\
819 PSDMR_SDAM_A13_IS_A5 |\
820 PSDMR_BSMA_A15_A17 |\
821 PSDMR_SDA10_PBI0_A11 |\
830 #define CONFIG_SYS_LSRT 0x0e
832 /*-----------------------------------------------------------------------
833 * BR5 - Base Register
834 * Ref: Section 10.3.1 on page 10-14
835 * OR5 - Option Register
836 * Ref: Section 10.3.2 on page 10-16
837 *-----------------------------------------------------------------------
841 * Bank 5 EEProm and Mailbox
843 * The EEPROM and mailbox live on the same chip select.
844 * the eeprom is selected if the MSb of the address is set and the mailbox is
845 * selected if the MSb of the address is clear.
849 /* BR5 is configured as follows:
851 * - Base address of 0x32000000/0xF2000000
853 * - Data error checking disabled
854 * - Read/Write access
857 * - No data pipelining is done
861 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
866 /* OR5 is configured as follows
867 * - buffer control enabled
868 * - chip select negated normally
869 * - CS output 1/2 clock after address
871 * - *PSDVAL is generated internally by the memory controller
872 * unless *GTA is asserted earlier externally.
873 * - Relaxed timing is generated by the GPCM for accesses
874 * initiated to this memory region.
875 * - One idle clock is inserted between a read access from the
876 * current bank and the next access.
879 #define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
885 /*-----------------------------------------------------------------------
886 * BR6 - Base Register
887 * Ref: Section 10.3.1 on page 10-14
888 * OR6 - Option Register
889 * Ref: Section 10.3.2 on page 10-18
890 *-----------------------------------------------------------------------
893 /* Bank 6 - I/O select
897 /* BR6 is configured as follows:
899 * - Base address of 0xE0000000
901 * - Data errors checking is disabled
902 * - Read and write access
904 * - Access are handled by the memory controller according to MSEL
905 * - Not used for atomic operations
906 * - No data pipelining is done
909 #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
914 /* OR6 is configured as follows
915 * - buffer control enabled
916 * - chip select negated normally
917 * - CS output 1/2 clock after address
919 * - *PSDVAL is generated internally by the memory controller
920 * unless *GTA is asserted earlier externally.
921 * - Relaxed timing is generated by the GPCM for accesses
922 * initiated to this memory region.
923 * - One idle clock is inserted between a read access from the
924 * current bank and the next access.
927 #define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
934 /*-----------------------------------------------------------------------
935 * BR7 - Base Register
936 * Ref: Section 10.3.1 on page 10-14
937 * OR7 - Option Register
938 * Ref: Section 10.3.2 on page 10-18
939 *-----------------------------------------------------------------------
942 /* Bank 7 - LEDs and switches
944 * LEDs are at 0x00001 (write only)
945 * switches are at 0x00001 (read only)
947 #ifdef CONFIG_SYS_LED_BASE
949 /* BR7 is configured as follows:
951 * - Base address of 0xA0000000
953 * - Data errors checking is disabled
954 * - Read and write access
956 * - Access are handled by the memory controller according to MSEL
957 * - Not used for atomic operations
958 * - No data pipelining is done
961 #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\
967 /* OR7 is configured as follows:
970 * - *BCTL0 is asserted upon access to the current memory bank
971 * - *CW / *WE are negated a quarter of a clock earlier
972 * - *CS is output at the same time as the address lines
973 * - Uses a clock cycle length of 15
974 * - *PSDVAL is generated internally by the memory controller
975 * unless *GTA is asserted earlier externally.
976 * - Relaxed timing is generated by the GPCM for accesses
977 * initiated to this memory region.
978 * - One idle clock is inserted between a read access from the
979 * current bank and the next access.
981 #define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\
987 #endif /* CONFIG_SYS_LED_BASE */
988 #endif /* __CONFIG_H */