b8ce17e807d5ba20b8e58a698f5ea7dff4d49e19
[platform/kernel/u-boot.git] / include / configs / pm9263.h
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Ilko Iliev <www.ronetix.at>
6  *
7  * Configuation settings for the RONETIX PM9263 board.
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16  * SoC must be defined first, before hardware.h is included.
17  * In this case SoC is defined in boards.cfg.
18  */
19 #include <asm/hardware.h>
20
21 /* ARM asynchronous clock */
22 #define CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_DISPLAY_BOARDINFO
24
25 #define MASTER_PLL_DIV          6
26 #define MASTER_PLL_MUL          65
27 #define MAIN_PLL_DIV            2       /* 2 or 4 */
28 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
29 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
30
31 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9263"
32 #define CONFIG_PM9263           1       /* on a Ronetix PM9263 Board    */
33 #define CONFIG_ARCH_CPU_INIT
34 #define CONFIG_SYS_TEXT_BASE    0
35
36 #define MACH_TYPE_PM9263        1475
37 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9263
38
39 /* clocks */
40 #define CONFIG_SYS_MOR_VAL                                              \
41                 (AT91_PMC_MOR_MOSCEN |                                  \
42                  (255 << 8))            /* Main Oscillator Start-up Time */
43 #define CONFIG_SYS_PLLAR_VAL                                            \
44                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
45                  AT91_PMC_PLLXR_OUT(3) |                                \
46                  AT91_PMC_PLLXR_PLLCOUNT(0x3f) |        /* PLL Counter */\
47                  (2 << 28) |            /* PLL Clock Frequency Range */ \
48                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
49
50 #if (MAIN_PLL_DIV == 2)
51 /* PCK/2 = MCK Master Clock from PLLA */
52 #define CONFIG_SYS_MCKR1_VAL            \
53                 (AT91_PMC_MCKR_CSS_SLOW |       \
54                  AT91_PMC_MCKR_PRES_1 | \
55                  AT91_PMC_MCKR_MDIV_2)
56 /* PCK/2 = MCK Master Clock from PLLA */
57 #define CONFIG_SYS_MCKR2_VAL            \
58                 (AT91_PMC_MCKR_CSS_PLLA |       \
59                  AT91_PMC_MCKR_PRES_1 | \
60                  AT91_PMC_MCKR_MDIV_2)
61 #else
62 /* PCK/4 = MCK Master Clock from PLLA */
63 #define CONFIG_SYS_MCKR1_VAL                    \
64                 (AT91_PMC_MCKR_CSS_SLOW |               \
65                  AT91_PMC_MCKR_PRES_1 |         \
66                  AT91_PMC_MCKR_MDIV_4)
67 /* PCK/4 = MCK Master Clock from PLLA */
68 #define CONFIG_SYS_MCKR2_VAL                    \
69                 (AT91_PMC_MCKR_CSS_PLLA |               \
70                  AT91_PMC_MCKR_PRES_1 |         \
71                  AT91_PMC_MCKR_MDIV_4)
72 #endif
73 /* define PDC[31:16] as DATA[31:16] */
74 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
75 /* no pull-up for D[31:16] */
76 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
77 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
78 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL                                   \
79         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
80          AT91_MATRIX_CSA_EBI_CS1A)
81
82 /* SDRAM */
83 /* SDRAMC_MR Mode register */
84 #define CONFIG_SYS_SDRC_MR_VAL1         0
85 /* SDRAMC_TR - Refresh Timer register */
86 #define CONFIG_SYS_SDRC_TR_VAL1         0x3AA
87 /* SDRAMC_CR - Configuration register*/
88 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
89                 (AT91_SDRAMC_NC_9 |                                             \
90                  AT91_SDRAMC_NR_13 |                                            \
91                  AT91_SDRAMC_NB_4 |                                             \
92                  AT91_SDRAMC_CAS_2 |                                            \
93                  AT91_SDRAMC_DBW_32 |                                           \
94                  (2 <<  8) |    /* tWR -  Write Recovery Delay */               \
95                  (7 << 12) |    /* tRC -  Row Cycle Delay */                    \
96                  (2 << 16) |    /* tRP -  Row Precharge Delay */                \
97                  (2 << 20) |    /* tRCD - Row to Column Delay */                \
98                  (5 << 24) |    /* tRAS - Active to Precharge Delay */          \
99                  (8 << 28))     /* tXSR - Exit Self Refresh to Active Delay */
100
101 /* Memory Device Register -> SDRAM */
102 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
103 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
104 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
105 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
106 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
107 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
108 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
109 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
110 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
111 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
112 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
113 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
114 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
115 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
116 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
117 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
118 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
119 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
120
121 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
122 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
123                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
124                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
125 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
126                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
127                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
128 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
129                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
130 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
131                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
132                  AT91_SMC_MODE_DBW_16 |                         \
133                  AT91_SMC_MODE_TDF |                            \
134                  AT91_SMC_MODE_TDF_CYCLE(6))
135
136 /* user reset enable */
137 #define CONFIG_SYS_RSTC_RMR_VAL                 \
138                 (AT91_RSTC_KEY |                \
139                 AT91_RSTC_CR_PROCRST |          \
140                 AT91_RSTC_MR_ERSTL(1) | \
141                 AT91_RSTC_MR_ERSTL(2))
142
143 /* Disable Watchdog */
144 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
145                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
146                  AT91_WDT_MR_WDV(0xfff) |                                       \
147                  AT91_WDT_MR_WDDIS |                            \
148                  AT91_WDT_MR_WDD(0xfff))
149
150 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
151 #define CONFIG_SETUP_MEMORY_TAGS 1
152 #define CONFIG_INITRD_TAG       1
153
154 #undef CONFIG_SKIP_LOWLEVEL_INIT
155 #define CONFIG_USER_LOWLEVEL_INIT       1
156 #define CONFIG_BOARD_EARLY_INIT_F
157
158 /*
159  * Hardware drivers
160  */
161 #define CONFIG_AT91_GPIO        1
162 #define CONFIG_ATMEL_USART      1
163 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
164 #define CONFIG_USART_ID                 ATMEL_ID_SYS
165
166 /* LCD */
167 #define CONFIG_LCD                      1
168 #define LCD_BPP                         LCD_COLOR8
169 #define CONFIG_LCD_LOGO                 1
170 #undef LCD_TEST_PATTERN
171 #define CONFIG_LCD_INFO                 1
172 #define CONFIG_LCD_INFO_BELOW_LOGO      1
173 #define CONFIG_SYS_WHITE_ON_BLACK       1
174 #define CONFIG_ATMEL_LCD                1
175 #define CONFIG_ATMEL_LCD_BGR555         1
176 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
177
178 #define CONFIG_LCD_IN_PSRAM             1
179
180 /* LED */
181 #define CONFIG_AT91_LED
182 #define CONFIG_RED_LED          GPIO_PIN_PB(7) /* this is the power led */
183 #define CONFIG_GREEN_LED        GPIO_PIN_PB(8) /* this is the user1 led */
184
185
186 /*
187  * BOOTP options
188  */
189 #define CONFIG_BOOTP_BOOTFILESIZE       1
190 #define CONFIG_BOOTP_BOOTPATH           1
191 #define CONFIG_BOOTP_GATEWAY            1
192 #define CONFIG_BOOTP_HOSTNAME           1
193
194 /*
195  * Command line configuration.
196  */
197 #define CONFIG_CMD_NAND         1
198
199 /* SDRAM */
200 #define CONFIG_NR_DRAM_BANKS    1
201 #define PHYS_SDRAM              0x20000000
202 #define PHYS_SDRAM_SIZE         0x04000000      /* 64 megs */
203
204 /* DataFlash */
205 #define CONFIG_ATMEL_DATAFLASH_SPI
206 #define CONFIG_HAS_DATAFLASH                    1
207 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
208 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
209 #define AT91_SPI_CLK                            15000000
210 #define DATAFLASH_TCSS                          (0x1a << 16)
211 #define DATAFLASH_TCHS                          (0x1 << 24)
212
213 /* NOR flash, if populated */
214 #define CONFIG_SYS_FLASH_CFI            1
215 #define CONFIG_FLASH_CFI_DRIVER         1
216 #define PHYS_FLASH_1                    0x10000000
217 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
218 #define CONFIG_SYS_MAX_FLASH_SECT       256
219 #define CONFIG_SYS_MAX_FLASH_BANKS      1
220
221 /* NAND flash */
222 #ifdef CONFIG_CMD_NAND
223 #define CONFIG_NAND_ATMEL
224 #define CONFIG_SYS_MAX_NAND_DEVICE      1
225 #define CONFIG_SYS_NAND_BASE            0x40000000
226 #define CONFIG_SYS_NAND_DBW_8           1
227 /* our ALE is AD21 */
228 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
229 /* our CLE is AD22 */
230 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
231 #define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PD(15)
232 #define CONFIG_SYS_NAND_READY_PIN       GPIO_PIN_PB(30)
233
234 #endif
235
236 #define CONFIG_CMD_JFFS2                1
237 #define CONFIG_JFFS2_CMDLINE            1
238 #define CONFIG_JFFS2_NAND               1
239 #define CONFIG_JFFS2_DEV                "nand0" /* NAND device jffs2 lives on */
240 #define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
241 #define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition size*/
242
243 /* PSRAM */
244 #define PHYS_PSRAM                      0x70000000
245 #define PHYS_PSRAM_SIZE                 0x00400000      /* 4MB */
246 /* Slave EBI1, PSRAM connected */
247 #define CONFIG_PSRAM_SCFG               (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY   | \
248                                          AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)      | \
249                                          AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED    | \
250                                          AT91_MATRIX_SCFG_SLOT_CYCLE(255))
251
252 /* Ethernet */
253 #define CONFIG_MACB                     1
254 #define CONFIG_RMII                     1
255 #define CONFIG_NET_RETRY_COUNT          20
256 #define CONFIG_RESET_PHY_R              1
257
258 /* USB */
259 #define CONFIG_USB_ATMEL
260 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
261 #define CONFIG_USB_OHCI_NEW                     1
262 #define CONFIG_DOS_PARTITION                    1
263 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
264 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
265 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
266 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
267 #define CONFIG_USB_STORAGE                      1
268
269 #define CONFIG_SYS_LOAD_ADDR                    0x22000000      /* load address */
270
271 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
272 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
273
274 #define CONFIG_SYS_USE_FLASH    1
275 #undef CONFIG_SYS_USE_DATAFLASH
276 #undef CONFIG_SYS_USE_NANDFLASH
277
278 #ifdef CONFIG_SYS_USE_DATAFLASH
279
280 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
281 #define CONFIG_ENV_IS_IN_DATAFLASH
282 #define CFG_MONITOR_BASE        (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
283 #define CONFIG_ENV_OFFSET       0x4200
284 #define CONFIG_ENV_ADDR         (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
285 #define CONFIG_ENV_SIZE         0x4200
286 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
287 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
288                                 "root=/dev/mtdblock0 " \
289                                 "mtdparts=atmel_nand:-(root) "\
290                                 "rw rootfstype=jffs2"
291
292 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
293
294 /* bootstrap + u-boot + env + linux in nandflash */
295 #define CONFIG_ENV_IS_IN_NAND
296 #define CONFIG_ENV_OFFSET               0x60000
297 #define CONFIG_ENV_OFFSET_REDUND        0x80000
298 #define CONFIG_ENV_SIZE         0x20000         /* 1 sector = 128 kB */
299 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
300 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "         \
301                                 "root=/dev/mtdblock5 "          \
302                                 "mtdparts=atmel_nand:"          \
303                                         "128k(bootstrap)ro,"    \
304                                         "256k(uboot)ro,"        \
305                                         "128k(env1)ro,"         \
306                                         "128k(env2)ro,"         \
307                                         "2M(linux),"            \
308                                         "-(root) "              \
309                                 "rw rootfstype=jffs2"
310
311 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
312
313 #define CONFIG_ENV_IS_IN_FLASH  1
314 #define CONFIG_ENV_OFFSET       0x40000
315 #define CONFIG_ENV_SECT_SIZE    0x10000
316 #define CONFIG_ENV_SIZE         0x10000
317 #define CONFIG_ENV_OVERWRITE    1
318
319 /* JFFS Partition offset set */
320 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
321 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
322
323 /* 512k reserved for u-boot */
324 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
325
326 #define CONFIG_BOOTCOMMAND              "run flashboot"
327 #define CONFIG_ROOTPATH                 "/ronetix/rootfs"
328
329 #define CONFIG_CON_ROT                  "fbcon=rotate:3 "
330 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock4 rootfstype=jffs2 "\
331                                         CONFIG_CON_ROT
332
333 #define MTDIDS_DEFAULT                  "nor0=physmap-flash.0,nand0=nand"
334 #define MTDPARTS_DEFAULT                \
335         "mtdparts=physmap-flash.0:"     \
336                 "256k(u-boot)ro,"       \
337                 "64k(u-boot-env)ro,"    \
338                 "1408k(kernel),"        \
339                 "-(rootfs);"            \
340         "nand:-(nand)"
341
342 #define CONFIG_EXTRA_ENV_SETTINGS                               \
343         "mtdids=" MTDIDS_DEFAULT "\0"                           \
344         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
345         "partition=nand0,0\0"                                   \
346         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
347         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
348                 CONFIG_CON_ROT                                  \
349                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
350         "addip=setenv bootargs $(bootargs) "                    \
351                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
352                 ":$(hostname):eth0:off\0"                       \
353         "ramboot=tftpboot 0x22000000 vmImage;"                  \
354                 "run ramargs;run addip;bootm 22000000\0"        \
355         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
356                 "run nfsargs;run addip;bootm 22000000\0"        \
357         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
358         ""
359
360 #else
361 #error "Undefined memory device"
362 #endif
363
364 #define CONFIG_BAUDRATE                 115200
365
366 #define CONFIG_SYS_CBSIZE               256
367 #define CONFIG_SYS_MAXARGS              16
368 #define CONFIG_SYS_PBSIZE               \
369                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
370 #define CONFIG_SYS_LONGHELP             1
371 #define CONFIG_CMDLINE_EDITING          1
372
373 /*
374  * Size of malloc() pool
375  */
376 #define CONFIG_SYS_MALLOC_LEN   ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
377
378 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
379 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
380                                 GENERATED_GBL_DATA_SIZE)
381
382 #endif