1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __IMX8M_PICOPI_H
7 #define __IMX8M_PICOPI_H
9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h>
12 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
14 #ifdef CONFIG_SPL_BUILD
15 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
16 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
17 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
18 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
19 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
21 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
22 #define CONFIG_MALLOC_F_ADDR 0x182000
23 /* For RAW image gives a error info not panic */
24 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
29 #if defined(CONFIG_CMD_NET)
30 #define CONFIG_FEC_MXC_PHYADDR 1
33 /* Initial environment variables */
34 #define CONFIG_EXTRA_ENV_SETTINGS \
37 "console=ttymxc0,115200\0" \
38 "fdt_addr=0x43000000\0" \
39 "fdt_high=0xffffffffffffffff\0" \
40 "fdt_file=imx8mq-pico-pi.dtb\0" \
41 "initrd_addr=0x43800000\0" \
42 "initrd_high=0xffffffffffffffff\0" \
43 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
45 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
46 "mmcautodetect=yes\0" \
47 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
49 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
50 "bootscript=echo Running bootscript from mmc ...; source\0" \
51 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
52 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
53 "mmcboot=echo Booting from mmc ...; " \
55 "echo wait for boot; " \
57 "netargs=setenv bootargs console=${console} " \
59 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
60 "netboot=echo Booting from net ...; " \
62 "if test ${ip_dyn} = yes; then " \
63 "setenv get_cmd dhcp; " \
65 "setenv get_cmd tftp; " \
67 "${get_cmd} ${loadaddr} ${image}; " \
70 /* Link Definitions */
72 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
73 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
76 #define CONFIG_SYS_SDRAM_BASE 0x40000000
77 #define PHYS_SDRAM 0x40000000
78 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
80 #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
82 #define CONFIG_SYS_FSL_USDHC_NUM 2
83 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
85 #define CONFIG_SYS_BOOTM_LEN SZ_128M